1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the V3H Starter Kit board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77980.dtsi"
11
12/ {
13	model = "Renesas V3H Starter Kit board";
14	compatible = "renesas,v3hsk", "renesas,r8a77980";
15
16	aliases {
17		serial0 = &scif0;
18		ethernet0 = &gether;
19	};
20
21	chosen {
22		stdout-path = "serial0:115200n8";
23	};
24
25	hdmi-out {
26		compatible = "hdmi-connector";
27		type = "a";
28
29		port {
30			hdmi_con: endpoint {
31				remote-endpoint = <&adv7511_out>;
32			};
33		};
34	};
35
36	lvds-decoder {
37		compatible = "thine,thc63lvd1024";
38		vcc-supply = <&vcc3v3_d5>;
39
40		ports {
41			#address-cells = <1>;
42			#size-cells = <0>;
43
44			port@0 {
45				reg = <0>;
46				thc63lvd1024_in: endpoint {
47					remote-endpoint = <&lvds0_out>;
48				};
49			};
50
51			port@2 {
52				reg = <2>;
53				thc63lvd1024_out: endpoint {
54					remote-endpoint = <&adv7511_in>;
55				};
56			};
57		};
58	};
59
60	memory@48000000 {
61		device_type = "memory";
62		/* first 128MB is reserved for secure area. */
63		reg = <0 0x48000000 0 0x78000000>;
64	};
65
66	osc1_clk: osc1-clock {
67		compatible = "fixed-clock";
68		#clock-cells = <0>;
69		clock-frequency = <148500000>;
70	};
71
72	vcc1v8_d4: regulator-0 {
73		compatible = "regulator-fixed";
74		regulator-name = "VCC1V8_D4";
75		regulator-min-microvolt = <1800000>;
76		regulator-max-microvolt = <1800000>;
77		regulator-boot-on;
78		regulator-always-on;
79	};
80
81	vcc3v3_d5: regulator-1 {
82		compatible = "regulator-fixed";
83		regulator-name = "VCC3V3_D5";
84		regulator-min-microvolt = <3300000>;
85		regulator-max-microvolt = <3300000>;
86		regulator-boot-on;
87		regulator-always-on;
88	};
89};
90
91&du {
92	clocks = <&cpg CPG_MOD 724>,
93		 <&osc1_clk>;
94	clock-names = "du.0", "dclkin.0";
95	status = "okay";
96};
97
98&extal_clk {
99	clock-frequency = <16666666>;
100};
101
102&extalr_clk {
103	clock-frequency = <32768>;
104};
105
106&gether {
107	pinctrl-0 = <&gether_pins>;
108	pinctrl-names = "default";
109
110	phy-mode = "rgmii";
111	phy-handle = <&phy0>;
112	renesas,no-ether-link;
113	status = "okay";
114
115	phy0: ethernet-phy@0 {
116		reg = <0>;
117		interrupt-parent = <&gpio4>;
118		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
119	};
120};
121
122&i2c0 {
123	pinctrl-0 = <&i2c0_pins>;
124	pinctrl-names = "default";
125
126	status = "okay";
127	clock-frequency = <400000>;
128
129	hdmi@39 {
130		compatible = "adi,adv7511w";
131		#sound-dai-cells = <0>;
132		reg = <0x39>;
133		interrupt-parent = <&gpio1>;
134		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
135		avdd-supply = <&vcc1v8_d4>;
136		dvdd-supply = <&vcc1v8_d4>;
137		pvdd-supply = <&vcc1v8_d4>;
138		bgvdd-supply = <&vcc1v8_d4>;
139		dvdd-3v-supply = <&vcc3v3_d5>;
140
141		adi,input-depth = <8>;
142		adi,input-colorspace = "rgb";
143		adi,input-clock = "1x";
144
145		ports {
146			#address-cells = <1>;
147			#size-cells = <0>;
148
149			port@0 {
150				reg = <0>;
151				adv7511_in: endpoint {
152					remote-endpoint = <&thc63lvd1024_out>;
153				};
154			};
155
156			port@1 {
157				reg = <1>;
158				adv7511_out: endpoint {
159					remote-endpoint = <&hdmi_con>;
160				};
161			};
162		};
163	};
164};
165
166&lvds0 {
167	status = "okay";
168
169	ports {
170		port@1 {
171			lvds0_out: endpoint {
172				remote-endpoint = <&thc63lvd1024_in>;
173			};
174		};
175	};
176};
177
178&pfc {
179	gether_pins: gether {
180		groups = "gether_mdio_a", "gether_rgmii",
181			 "gether_txcrefclk", "gether_txcrefclk_mega";
182		function = "gether";
183	};
184
185	i2c0_pins: i2c0 {
186		groups = "i2c0";
187		function = "i2c0";
188	};
189
190	qspi0_pins: qspi0 {
191		groups = "qspi0_ctrl", "qspi0_data4";
192		function = "qspi0";
193	};
194
195	scif0_pins: scif0 {
196		groups = "scif0_data";
197		function = "scif0";
198	};
199
200	scif_clk_pins: scif_clk {
201		groups = "scif_clk_b";
202		function = "scif_clk";
203	};
204};
205
206&rpc {
207	pinctrl-0 = <&qspi0_pins>;
208	pinctrl-names = "default";
209
210	status = "okay";
211
212	flash@0 {
213		compatible = "spansion,s25fs512s", "jedec,spi-nor";
214		reg = <0>;
215		spi-max-frequency = <50000000>;
216		spi-rx-bus-width = <4>;
217
218		partitions {
219			compatible = "fixed-partitions";
220			#address-cells = <1>;
221			#size-cells = <1>;
222
223			bootparam@0 {
224				reg = <0x00000000 0x040000>;
225				read-only;
226			};
227			cr7@40000 {
228				reg = <0x00040000 0x080000>;
229				read-only;
230			};
231			cert_header_sa3@c0000 {
232				reg = <0x000c0000 0x080000>;
233				read-only;
234			};
235			bl2@140000 {
236				reg = <0x00140000 0x040000>;
237				read-only;
238			};
239			cert_header_sa6@180000 {
240				reg = <0x00180000 0x040000>;
241				read-only;
242			};
243			bl31@1c0000 {
244				reg = <0x001c0000 0x460000>;
245				read-only;
246			};
247			uboot@640000 {
248				reg = <0x00640000 0x0c0000>;
249				read-only;
250			};
251			uboot-env@700000 {
252				reg = <0x00700000 0x040000>;
253				read-only;
254			};
255			dtb@740000 {
256				reg = <0x00740000 0x080000>;
257			};
258			kernel@7c0000 {
259				reg = <0x007c0000 0x1400000>;
260			};
261			user@1bc0000 {
262				reg = <0x01bc0000 0x2440000>;
263			};
264		};
265	};
266};
267
268&rwdt {
269	timeout-sec = <60>;
270	status = "okay";
271};
272
273&scif0 {
274	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
275	pinctrl-names = "default";
276
277	status = "okay";
278};
279
280&scif_clk {
281	clock-frequency = <14745600>;
282};
283