1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the V3H Starter Kit board 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77980.dtsi" 11 12/ { 13 model = "Renesas V3H Starter Kit board"; 14 compatible = "renesas,v3hsk", "renesas,r8a77980"; 15 16 aliases { 17 serial0 = &scif0; 18 ethernet0 = &gether; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 hdmi-out { 26 compatible = "hdmi-connector"; 27 type = "a"; 28 29 port { 30 hdmi_con: endpoint { 31 remote-endpoint = <&adv7511_out>; 32 }; 33 }; 34 }; 35 36 lvds-decoder { 37 compatible = "thine,thc63lvd1024"; 38 vcc-supply = <&vcc3v3_d5>; 39 40 ports { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 port@0 { 45 reg = <0>; 46 thc63lvd1024_in: endpoint { 47 remote-endpoint = <&lvds0_out>; 48 }; 49 }; 50 51 port@2 { 52 reg = <2>; 53 thc63lvd1024_out: endpoint { 54 remote-endpoint = <&adv7511_in>; 55 }; 56 }; 57 }; 58 }; 59 60 memory@48000000 { 61 device_type = "memory"; 62 /* first 128MB is reserved for secure area. */ 63 reg = <0 0x48000000 0 0x78000000>; 64 }; 65 66 osc1_clk: osc1-clock { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <148500000>; 70 }; 71 72 vcc1v8_d4: regulator-0 { 73 compatible = "regulator-fixed"; 74 regulator-name = "VCC1V8_D4"; 75 regulator-min-microvolt = <1800000>; 76 regulator-max-microvolt = <1800000>; 77 regulator-boot-on; 78 regulator-always-on; 79 }; 80 81 vcc3v3_d5: regulator-1 { 82 compatible = "regulator-fixed"; 83 regulator-name = "VCC3V3_D5"; 84 regulator-min-microvolt = <3300000>; 85 regulator-max-microvolt = <3300000>; 86 regulator-boot-on; 87 regulator-always-on; 88 }; 89}; 90 91&du { 92 clocks = <&cpg CPG_MOD 724>, 93 <&osc1_clk>; 94 clock-names = "du.0", "dclkin.0"; 95 status = "okay"; 96}; 97 98&extal_clk { 99 clock-frequency = <16666666>; 100}; 101 102&extalr_clk { 103 clock-frequency = <32768>; 104}; 105 106&gether { 107 pinctrl-0 = <&gether_pins>; 108 pinctrl-names = "default"; 109 110 phy-mode = "rgmii"; 111 phy-handle = <&phy0>; 112 renesas,no-ether-link; 113 status = "okay"; 114 115 phy0: ethernet-phy@0 { 116 compatible = "ethernet-phy-id0022.1622", 117 "ethernet-phy-ieee802.3-c22"; 118 reg = <0>; 119 interrupt-parent = <&gpio4>; 120 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 121 }; 122}; 123 124&i2c0 { 125 pinctrl-0 = <&i2c0_pins>; 126 pinctrl-names = "default"; 127 128 status = "okay"; 129 clock-frequency = <400000>; 130 131 hdmi@39 { 132 compatible = "adi,adv7511w"; 133 #sound-dai-cells = <0>; 134 reg = <0x39>; 135 interrupt-parent = <&gpio1>; 136 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 137 avdd-supply = <&vcc1v8_d4>; 138 dvdd-supply = <&vcc1v8_d4>; 139 pvdd-supply = <&vcc1v8_d4>; 140 bgvdd-supply = <&vcc1v8_d4>; 141 dvdd-3v-supply = <&vcc3v3_d5>; 142 143 adi,input-depth = <8>; 144 adi,input-colorspace = "rgb"; 145 adi,input-clock = "1x"; 146 147 ports { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 port@0 { 152 reg = <0>; 153 adv7511_in: endpoint { 154 remote-endpoint = <&thc63lvd1024_out>; 155 }; 156 }; 157 158 port@1 { 159 reg = <1>; 160 adv7511_out: endpoint { 161 remote-endpoint = <&hdmi_con>; 162 }; 163 }; 164 }; 165 }; 166}; 167 168&lvds0 { 169 status = "okay"; 170 171 ports { 172 port@1 { 173 lvds0_out: endpoint { 174 remote-endpoint = <&thc63lvd1024_in>; 175 }; 176 }; 177 }; 178}; 179 180&pfc { 181 gether_pins: gether { 182 groups = "gether_mdio_a", "gether_rgmii", 183 "gether_txcrefclk", "gether_txcrefclk_mega"; 184 function = "gether"; 185 }; 186 187 i2c0_pins: i2c0 { 188 groups = "i2c0"; 189 function = "i2c0"; 190 }; 191 192 qspi0_pins: qspi0 { 193 groups = "qspi0_ctrl", "qspi0_data4"; 194 function = "qspi0"; 195 }; 196 197 scif0_pins: scif0 { 198 groups = "scif0_data"; 199 function = "scif0"; 200 }; 201 202 scif_clk_pins: scif_clk { 203 groups = "scif_clk_b"; 204 function = "scif_clk"; 205 }; 206}; 207 208&rpc { 209 pinctrl-0 = <&qspi0_pins>; 210 pinctrl-names = "default"; 211 212 status = "okay"; 213 214 flash@0 { 215 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 216 reg = <0>; 217 spi-max-frequency = <50000000>; 218 spi-rx-bus-width = <4>; 219 220 partitions { 221 compatible = "fixed-partitions"; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 225 bootparam@0 { 226 reg = <0x00000000 0x040000>; 227 read-only; 228 }; 229 cr7@40000 { 230 reg = <0x00040000 0x080000>; 231 read-only; 232 }; 233 cert_header_sa3@c0000 { 234 reg = <0x000c0000 0x080000>; 235 read-only; 236 }; 237 bl2@140000 { 238 reg = <0x00140000 0x040000>; 239 read-only; 240 }; 241 cert_header_sa6@180000 { 242 reg = <0x00180000 0x040000>; 243 read-only; 244 }; 245 bl31@1c0000 { 246 reg = <0x001c0000 0x460000>; 247 read-only; 248 }; 249 uboot@640000 { 250 reg = <0x00640000 0x0c0000>; 251 read-only; 252 }; 253 uboot-env@700000 { 254 reg = <0x00700000 0x040000>; 255 read-only; 256 }; 257 dtb@740000 { 258 reg = <0x00740000 0x080000>; 259 }; 260 kernel@7c0000 { 261 reg = <0x007c0000 0x1400000>; 262 }; 263 user@1bc0000 { 264 reg = <0x01bc0000 0x2440000>; 265 }; 266 }; 267 }; 268}; 269 270&rwdt { 271 timeout-sec = <60>; 272 status = "okay"; 273}; 274 275&scif0 { 276 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 277 pinctrl-names = "default"; 278 279 status = "okay"; 280}; 281 282&scif_clk { 283 clock-frequency = <14745600>; 284}; 285