1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the V3H Starter Kit board 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77980.dtsi" 11 12/ { 13 model = "Renesas V3H Starter Kit board"; 14 compatible = "renesas,v3hsk", "renesas,r8a77980"; 15 16 aliases { 17 serial0 = &scif0; 18 ethernet0 = &gether; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@48000000 { 26 device_type = "memory"; 27 /* first 128MB is reserved for secure area. */ 28 reg = <0 0x48000000 0 0x78000000>; 29 }; 30}; 31 32&extal_clk { 33 clock-frequency = <16666666>; 34}; 35 36&extalr_clk { 37 clock-frequency = <32768>; 38}; 39 40&gether { 41 pinctrl-0 = <&gether_pins>; 42 pinctrl-names = "default"; 43 44 phy-mode = "rgmii"; 45 phy-handle = <&phy0>; 46 renesas,no-ether-link; 47 status = "okay"; 48 49 phy0: ethernet-phy@0 { 50 reg = <0>; 51 interrupt-parent = <&gpio4>; 52 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 53 }; 54}; 55 56&pfc { 57 gether_pins: gether { 58 groups = "gether_mdio_a", "gether_rgmii", 59 "gether_txcrefclk", "gether_txcrefclk_mega"; 60 function = "gether"; 61 }; 62 63 scif0_pins: scif0 { 64 groups = "scif0_data"; 65 function = "scif0"; 66 }; 67 68 scif_clk_pins: scif_clk { 69 groups = "scif_clk_b"; 70 function = "scif_clk"; 71 }; 72}; 73 74&scif0 { 75 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 76 pinctrl-names = "default"; 77 78 status = "okay"; 79}; 80 81&scif_clk { 82 clock-frequency = <14745600>; 83}; 84