1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Condor board with R-Car V3H
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77980.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Renesas Condor board based on r8a77980";
15	compatible = "renesas,condor", "renesas,r8a77980";
16
17	aliases {
18		serial0 = &scif0;
19		ethernet0 = &gether;
20	};
21
22	chosen {
23		stdout-path = "serial0:115200n8";
24	};
25
26	d1_8v: regulator-2 {
27		compatible = "regulator-fixed";
28		regulator-name = "D1.8V";
29		regulator-min-microvolt = <1800000>;
30		regulator-max-microvolt = <1800000>;
31		regulator-boot-on;
32		regulator-always-on;
33	};
34
35	d3_3v: regulator-0 {
36		compatible = "regulator-fixed";
37		regulator-name = "D3.3V";
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		regulator-boot-on;
41		regulator-always-on;
42	};
43
44	hdmi-out {
45		compatible = "hdmi-connector";
46		type = "a";
47
48		port {
49			hdmi_con: endpoint {
50				remote-endpoint = <&adv7511_out>;
51			};
52		};
53	};
54
55	lvds-decoder {
56		compatible = "thine,thc63lvd1024";
57		vcc-supply = <&d3_3v>;
58
59		ports {
60			#address-cells = <1>;
61			#size-cells = <0>;
62
63			port@0 {
64				reg = <0>;
65				thc63lvd1024_in: endpoint {
66					remote-endpoint = <&lvds0_out>;
67				};
68			};
69
70			port@2 {
71				reg = <2>;
72				thc63lvd1024_out: endpoint {
73					remote-endpoint = <&adv7511_in>;
74				};
75			};
76		};
77	};
78
79	memory@48000000 {
80		device_type = "memory";
81		/* first 128MB is reserved for secure area. */
82		reg = <0 0x48000000 0 0x78000000>;
83	};
84
85	vddq_vin01: regulator-1 {
86		compatible = "regulator-fixed";
87		regulator-name = "VDDQ_VIN01";
88		regulator-min-microvolt = <1800000>;
89		regulator-max-microvolt = <1800000>;
90		regulator-boot-on;
91		regulator-always-on;
92	};
93
94	x1_clk: x1-clock {
95		compatible = "fixed-clock";
96		#clock-cells = <0>;
97		clock-frequency = <148500000>;
98	};
99};
100
101&canfd {
102	pinctrl-0 = <&canfd0_pins>;
103	pinctrl-names = "default";
104	status = "okay";
105
106	channel0 {
107		status = "okay";
108	};
109};
110
111&du {
112	clocks = <&cpg CPG_MOD 724>,
113		 <&x1_clk>;
114	clock-names = "du.0", "dclkin.0";
115	status = "okay";
116};
117
118&extal_clk {
119	clock-frequency = <16666666>;
120};
121
122&extalr_clk {
123	clock-frequency = <32768>;
124};
125
126&gether {
127	pinctrl-0 = <&gether_pins>;
128	pinctrl-names = "default";
129
130	phy-mode = "rgmii-id";
131	phy-handle = <&phy0>;
132	renesas,no-ether-link;
133	status = "okay";
134
135	phy0: ethernet-phy@0 {
136		compatible = "ethernet-phy-id0022.1622",
137			     "ethernet-phy-ieee802.3-c22";
138		rxc-skew-ps = <1500>;
139		reg = <0>;
140		interrupt-parent = <&gpio4>;
141		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
142		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
143	};
144};
145
146&i2c0 {
147	pinctrl-0 = <&i2c0_pins>;
148	pinctrl-names = "default";
149
150	status = "okay";
151	clock-frequency = <400000>;
152
153	io_expander0: gpio@20 {
154		compatible = "onnn,pca9654";
155		reg = <0x20>;
156		gpio-controller;
157		#gpio-cells = <2>;
158	};
159
160	io_expander1: gpio@21 {
161		compatible = "onnn,pca9654";
162		reg = <0x21>;
163		gpio-controller;
164		#gpio-cells = <2>;
165	};
166
167	hdmi@39 {
168		compatible = "adi,adv7511w";
169		reg = <0x39>;
170		interrupt-parent = <&gpio1>;
171		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
172		avdd-supply = <&d1_8v>;
173		dvdd-supply = <&d1_8v>;
174		pvdd-supply = <&d1_8v>;
175		bgvdd-supply = <&d1_8v>;
176		dvdd-3v-supply = <&d3_3v>;
177
178		adi,input-depth = <8>;
179		adi,input-colorspace = "rgb";
180		adi,input-clock = "1x";
181
182		ports {
183			#address-cells = <1>;
184			#size-cells = <0>;
185
186			port@0 {
187				reg = <0>;
188				adv7511_in: endpoint {
189					remote-endpoint = <&thc63lvd1024_out>;
190				};
191			};
192
193			port@1 {
194				reg = <1>;
195				adv7511_out: endpoint {
196					remote-endpoint = <&hdmi_con>;
197				};
198			};
199		};
200	};
201};
202
203&lvds0 {
204	status = "okay";
205
206	ports {
207		port@1 {
208			lvds0_out: endpoint {
209				remote-endpoint = <&thc63lvd1024_in>;
210			};
211		};
212	};
213};
214
215&mmc0 {
216	pinctrl-0 = <&mmc_pins>;
217	pinctrl-1 = <&mmc_pins>;
218	pinctrl-names = "default", "state_uhs";
219
220	vmmc-supply = <&d3_3v>;
221	vqmmc-supply = <&vddq_vin01>;
222	mmc-hs200-1_8v;
223	bus-width = <8>;
224	no-sd;
225	no-sdio;
226	non-removable;
227	status = "okay";
228};
229
230&pciec {
231	status = "okay";
232};
233
234&pcie_bus_clk {
235	clock-frequency = <100000000>;
236};
237
238&pcie_phy {
239	status = "okay";
240};
241
242&pfc {
243	canfd0_pins: canfd0 {
244		groups = "canfd0_data_a";
245		function = "canfd0";
246	};
247
248	gether_pins: gether {
249		groups = "gether_mdio_a", "gether_rgmii",
250			 "gether_txcrefclk", "gether_txcrefclk_mega";
251		function = "gether";
252	};
253
254	i2c0_pins: i2c0 {
255		groups = "i2c0";
256		function = "i2c0";
257	};
258
259	mmc_pins: mmc {
260		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
261		function = "mmc";
262		power-source = <1800>;
263	};
264
265	qspi0_pins: qspi0 {
266		groups = "qspi0_ctrl", "qspi0_data4";
267		function = "qspi0";
268	};
269
270	scif0_pins: scif0 {
271		groups = "scif0_data";
272		function = "scif0";
273	};
274
275	scif_clk_pins: scif_clk {
276		groups = "scif_clk_b";
277		function = "scif_clk";
278	};
279};
280
281&rpc {
282	pinctrl-0 = <&qspi0_pins>;
283	pinctrl-names = "default";
284
285	status = "okay";
286
287	flash@0 {
288		compatible = "spansion,s25fs512s", "jedec,spi-nor";
289		reg = <0>;
290		spi-max-frequency = <50000000>;
291		spi-rx-bus-width = <4>;
292
293		partitions {
294			compatible = "fixed-partitions";
295			#address-cells = <1>;
296			#size-cells = <1>;
297
298			bootparam@0 {
299				reg = <0x00000000 0x040000>;
300				read-only;
301			};
302			cr7@40000 {
303				reg = <0x00040000 0x080000>;
304				read-only;
305			};
306			cert_header_sa3@c0000 {
307				reg = <0x000c0000 0x080000>;
308				read-only;
309			};
310			bl2@140000 {
311				reg = <0x00140000 0x040000>;
312				read-only;
313			};
314			cert_header_sa6@180000 {
315				reg = <0x00180000 0x040000>;
316				read-only;
317			};
318			bl31@1c0000 {
319				reg = <0x001c0000 0x460000>;
320				read-only;
321			};
322			uboot@640000 {
323				reg = <0x00640000 0x0c0000>;
324				read-only;
325			};
326			uboot-env@700000 {
327				reg = <0x00700000 0x040000>;
328				read-only;
329			};
330			dtb@740000 {
331				reg = <0x00740000 0x080000>;
332			};
333			kernel@7c0000 {
334				reg = <0x007c0000 0x1400000>;
335			};
336			user@1bc0000 {
337				reg = <0x01bc0000 0x2440000>;
338			};
339		};
340	};
341};
342
343&rwdt {
344	timeout-sec = <60>;
345	status = "okay";
346};
347
348&scif0 {
349	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
350	pinctrl-names = "default";
351
352	status = "okay";
353};
354
355&scif_clk {
356	clock-frequency = <14745600>;
357};
358