1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Condor board 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77980.dtsi" 11 12/ { 13 model = "Renesas Condor board based on r8a77980"; 14 compatible = "renesas,condor", "renesas,r8a77980"; 15 16 aliases { 17 serial0 = &scif0; 18 ethernet0 = &avb; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@48000000 { 26 device_type = "memory"; 27 /* first 128MB is reserved for secure area. */ 28 reg = <0 0x48000000 0 0x78000000>; 29 }; 30 31 d3_3v: regulator-0 { 32 compatible = "regulator-fixed"; 33 regulator-name = "D3.3V"; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 regulator-boot-on; 37 regulator-always-on; 38 }; 39 40 vddq_vin01: regulator-1 { 41 compatible = "regulator-fixed"; 42 regulator-name = "VDDQ_VIN01"; 43 regulator-min-microvolt = <1800000>; 44 regulator-max-microvolt = <1800000>; 45 regulator-boot-on; 46 regulator-always-on; 47 }; 48}; 49 50&avb { 51 pinctrl-0 = <&avb_pins>; 52 pinctrl-names = "default"; 53 54 phy-mode = "rgmii-id"; 55 phy-handle = <&phy0>; 56 renesas,no-ether-link; 57 status = "okay"; 58 59 phy0: ethernet-phy@0 { 60 rxc-skew-ps = <1500>; 61 reg = <0>; 62 }; 63}; 64 65&canfd { 66 pinctrl-0 = <&canfd0_pins>; 67 pinctrl-names = "default"; 68 status = "okay"; 69 70 channel0 { 71 status = "okay"; 72 }; 73}; 74 75&extal_clk { 76 clock-frequency = <16666666>; 77}; 78 79&extalr_clk { 80 clock-frequency = <32768>; 81}; 82 83&i2c0 { 84 pinctrl-0 = <&i2c0_pins>; 85 pinctrl-names = "default"; 86 87 status = "okay"; 88 clock-frequency = <400000>; 89 90 io_expander0: gpio@20 { 91 compatible = "onnn,pca9654"; 92 reg = <0x20>; 93 gpio-controller; 94 #gpio-cells = <2>; 95 }; 96 97 io_expander1: gpio@21 { 98 compatible = "onnn,pca9654"; 99 reg = <0x21>; 100 gpio-controller; 101 #gpio-cells = <2>; 102 }; 103}; 104 105&mmc0 { 106 pinctrl-0 = <&mmc_pins>; 107 pinctrl-1 = <&mmc_pins_uhs>; 108 pinctrl-names = "default", "state_uhs"; 109 110 vmmc-supply = <&d3_3v>; 111 vqmmc-supply = <&vddq_vin01>; 112 mmc-hs200-1_8v; 113 bus-width = <8>; 114 non-removable; 115 status = "okay"; 116}; 117 118&pfc { 119 avb_pins: avb { 120 groups = "avb_mdio", "avb_rgmii"; 121 function = "avb"; 122 }; 123 124 canfd0_pins: canfd0 { 125 groups = "canfd0_data_a"; 126 function = "canfd0"; 127 }; 128 129 i2c0_pins: i2c0 { 130 groups = "i2c0"; 131 function = "i2c0"; 132 }; 133 134 mmc_pins: mmc { 135 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 136 function = "mmc"; 137 power-source = <3300>; 138 }; 139 140 mmc_pins_uhs: mmc_uhs { 141 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 142 function = "mmc"; 143 power-source = <1800>; 144 }; 145 146 scif0_pins: scif0 { 147 groups = "scif0_data"; 148 function = "scif0"; 149 }; 150 151 scif_clk_pins: scif_clk { 152 groups = "scif_clk_b"; 153 function = "scif_clk"; 154 }; 155}; 156 157&scif0 { 158 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 159 pinctrl-names = "default"; 160 161 status = "okay"; 162}; 163 164&scif_clk { 165 clock-frequency = <14745600>; 166}; 167