1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3M (R8A77970) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77970-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/power/r8a77970-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77970"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 }; 26 27 /* External CAN clock - to be overridden by boards that provide it */ 28 can_clk: can { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 a53_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0>; 42 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 43 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 44 next-level-cache = <&L2_CA53>; 45 enable-method = "psci"; 46 }; 47 48 a53_1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <1>; 52 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 53 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 54 next-level-cache = <&L2_CA53>; 55 enable-method = "psci"; 56 }; 57 58 L2_CA53: cache-controller { 59 compatible = "cache"; 60 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 61 cache-unified; 62 cache-level = <2>; 63 }; 64 }; 65 66 extal_clk: extal { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 /* This value must be overridden by the board */ 70 clock-frequency = <0>; 71 }; 72 73 extalr_clk: extalr { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 /* This value must be overridden by the board */ 77 clock-frequency = <0>; 78 }; 79 80 pmu_a53 { 81 compatible = "arm,cortex-a53-pmu"; 82 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 83 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&a53_0>, <&a53_1>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0", "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 /* External SCIF clock - to be overridden by boards that provide it */ 93 scif_clk: scif { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <0>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 rwdt: watchdog@e6020000 { 108 compatible = "renesas,r8a77970-wdt", 109 "renesas,rcar-gen3-wdt"; 110 reg = <0 0xe6020000 0 0x0c>; 111 clocks = <&cpg CPG_MOD 402>; 112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 113 resets = <&cpg 402>; 114 status = "disabled"; 115 }; 116 117 gpio0: gpio@e6050000 { 118 compatible = "renesas,gpio-r8a77970", 119 "renesas,rcar-gen3-gpio"; 120 reg = <0 0xe6050000 0 0x50>; 121 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pfc 0 0 22>; 125 #interrupt-cells = <2>; 126 interrupt-controller; 127 clocks = <&cpg CPG_MOD 912>; 128 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 129 resets = <&cpg 912>; 130 }; 131 132 gpio1: gpio@e6051000 { 133 compatible = "renesas,gpio-r8a77970", 134 "renesas,rcar-gen3-gpio"; 135 reg = <0 0xe6051000 0 0x50>; 136 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 137 #gpio-cells = <2>; 138 gpio-controller; 139 gpio-ranges = <&pfc 0 32 28>; 140 #interrupt-cells = <2>; 141 interrupt-controller; 142 clocks = <&cpg CPG_MOD 911>; 143 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 144 resets = <&cpg 911>; 145 }; 146 147 gpio2: gpio@e6052000 { 148 compatible = "renesas,gpio-r8a77970", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6052000 0 0x50>; 151 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 64 17>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 910>; 158 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 159 resets = <&cpg 910>; 160 }; 161 162 gpio3: gpio@e6053000 { 163 compatible = "renesas,gpio-r8a77970", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6053000 0 0x50>; 166 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 96 17>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 909>; 173 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 174 resets = <&cpg 909>; 175 }; 176 177 gpio4: gpio@e6054000 { 178 compatible = "renesas,gpio-r8a77970", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6054000 0 0x50>; 181 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 128 6>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 908>; 188 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 189 resets = <&cpg 908>; 190 }; 191 192 gpio5: gpio@e6055000 { 193 compatible = "renesas,gpio-r8a77970", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6055000 0 0x50>; 196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 160 15>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 907>; 203 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 204 resets = <&cpg 907>; 205 }; 206 207 pfc: pinctrl@e6060000 { 208 compatible = "renesas,pfc-r8a77970"; 209 reg = <0 0xe6060000 0 0x504>; 210 }; 211 212 cmt0: timer@e60f0000 { 213 compatible = "renesas,r8a77970-cmt0", 214 "renesas,rcar-gen3-cmt0"; 215 reg = <0 0xe60f0000 0 0x1004>; 216 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cpg CPG_MOD 303>; 219 clock-names = "fck"; 220 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 221 resets = <&cpg 303>; 222 status = "disabled"; 223 }; 224 225 cmt1: timer@e6130000 { 226 compatible = "renesas,r8a77970-cmt1", 227 "renesas,rcar-gen3-cmt1"; 228 reg = <0 0xe6130000 0 0x1004>; 229 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cpg CPG_MOD 302>; 238 clock-names = "fck"; 239 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 240 resets = <&cpg 302>; 241 status = "disabled"; 242 }; 243 244 cmt2: timer@e6140000 { 245 compatible = "renesas,r8a77970-cmt1", 246 "renesas,rcar-gen3-cmt1"; 247 reg = <0 0xe6140000 0 0x1004>; 248 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cpg CPG_MOD 301>; 257 clock-names = "fck"; 258 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 259 resets = <&cpg 301>; 260 status = "disabled"; 261 }; 262 263 cmt3: timer@e6148000 { 264 compatible = "renesas,r8a77970-cmt1", 265 "renesas,rcar-gen3-cmt1"; 266 reg = <0 0xe6148000 0 0x1004>; 267 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cpg CPG_MOD 300>; 276 clock-names = "fck"; 277 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 278 resets = <&cpg 300>; 279 status = "disabled"; 280 }; 281 282 cpg: clock-controller@e6150000 { 283 compatible = "renesas,r8a77970-cpg-mssr"; 284 reg = <0 0xe6150000 0 0x1000>; 285 clocks = <&extal_clk>, <&extalr_clk>; 286 clock-names = "extal", "extalr"; 287 #clock-cells = <2>; 288 #power-domain-cells = <0>; 289 #reset-cells = <1>; 290 }; 291 292 rst: reset-controller@e6160000 { 293 compatible = "renesas,r8a77970-rst"; 294 reg = <0 0xe6160000 0 0x200>; 295 }; 296 297 sysc: system-controller@e6180000 { 298 compatible = "renesas,r8a77970-sysc"; 299 reg = <0 0xe6180000 0 0x440>; 300 #power-domain-cells = <1>; 301 }; 302 303 thermal: thermal@e6190000 { 304 compatible = "renesas,thermal-r8a77970"; 305 reg = <0 0xe6190000 0 0x10>, 306 <0 0xe6190100 0 0x120>; 307 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 522>; 311 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 312 resets = <&cpg 522>; 313 #thermal-sensor-cells = <0>; 314 }; 315 316 intc_ex: interrupt-controller@e61c0000 { 317 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 318 #interrupt-cells = <2>; 319 interrupt-controller; 320 reg = <0 0xe61c0000 0 0x200>; 321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 407>; 328 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 329 resets = <&cpg 407>; 330 }; 331 332 tmu0: timer@e61e0000 { 333 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 334 reg = <0 0xe61e0000 0 0x30>; 335 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cpg CPG_MOD 125>; 339 clock-names = "fck"; 340 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 341 resets = <&cpg 125>; 342 status = "disabled"; 343 }; 344 345 tmu1: timer@e6fc0000 { 346 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 347 reg = <0 0xe6fc0000 0 0x30>; 348 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cpg CPG_MOD 124>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 354 resets = <&cpg 124>; 355 status = "disabled"; 356 }; 357 358 tmu2: timer@e6fd0000 { 359 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 360 reg = <0 0xe6fd0000 0 0x30>; 361 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cpg CPG_MOD 123>; 365 clock-names = "fck"; 366 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 367 resets = <&cpg 123>; 368 status = "disabled"; 369 }; 370 371 tmu3: timer@e6fe0000 { 372 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 373 reg = <0 0xe6fe0000 0 0x30>; 374 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 122>; 378 clock-names = "fck"; 379 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 380 resets = <&cpg 122>; 381 status = "disabled"; 382 }; 383 384 tmu4: timer@ffc00000 { 385 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 386 reg = <0 0xffc00000 0 0x30>; 387 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 121>; 391 clock-names = "fck"; 392 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 393 resets = <&cpg 121>; 394 status = "disabled"; 395 }; 396 397 i2c0: i2c@e6500000 { 398 compatible = "renesas,i2c-r8a77970", 399 "renesas,rcar-gen3-i2c"; 400 reg = <0 0xe6500000 0 0x40>; 401 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cpg CPG_MOD 931>; 403 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 404 resets = <&cpg 931>; 405 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 406 <&dmac2 0x91>, <&dmac2 0x90>; 407 dma-names = "tx", "rx", "tx", "rx"; 408 i2c-scl-internal-delay-ns = <6>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c1: i2c@e6508000 { 415 compatible = "renesas,i2c-r8a77970", 416 "renesas,rcar-gen3-i2c"; 417 reg = <0 0xe6508000 0 0x40>; 418 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 930>; 420 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 421 resets = <&cpg 930>; 422 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 423 <&dmac2 0x93>, <&dmac2 0x92>; 424 dma-names = "tx", "rx", "tx", "rx"; 425 i2c-scl-internal-delay-ns = <6>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c2: i2c@e6510000 { 432 compatible = "renesas,i2c-r8a77970", 433 "renesas,rcar-gen3-i2c"; 434 reg = <0 0xe6510000 0 0x40>; 435 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cpg CPG_MOD 929>; 437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 438 resets = <&cpg 929>; 439 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 440 <&dmac2 0x95>, <&dmac2 0x94>; 441 dma-names = "tx", "rx", "tx", "rx"; 442 i2c-scl-internal-delay-ns = <6>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@e66d0000 { 449 compatible = "renesas,i2c-r8a77970", 450 "renesas,rcar-gen3-i2c"; 451 reg = <0 0xe66d0000 0 0x40>; 452 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 928>; 454 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 455 resets = <&cpg 928>; 456 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 457 <&dmac2 0x97>, <&dmac2 0x96>; 458 dma-names = "tx", "rx", "tx", "rx"; 459 i2c-scl-internal-delay-ns = <6>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 status = "disabled"; 463 }; 464 465 i2c4: i2c@e66d8000 { 466 compatible = "renesas,i2c-r8a77970", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe66d8000 0 0x40>; 469 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 927>; 471 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 472 resets = <&cpg 927>; 473 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 474 <&dmac2 0x99>, <&dmac2 0x98>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 i2c-scl-internal-delay-ns = <6>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 hscif0: serial@e6540000 { 483 compatible = "renesas,hscif-r8a77970", 484 "renesas,rcar-gen3-hscif", 485 "renesas,hscif"; 486 reg = <0 0xe6540000 0 96>; 487 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cpg CPG_MOD 520>, 489 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 490 <&scif_clk>; 491 clock-names = "fck", "brg_int", "scif_clk"; 492 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 493 <&dmac2 0x31>, <&dmac2 0x30>; 494 dma-names = "tx", "rx", "tx", "rx"; 495 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 496 resets = <&cpg 520>; 497 status = "disabled"; 498 }; 499 500 hscif1: serial@e6550000 { 501 compatible = "renesas,hscif-r8a77970", 502 "renesas,rcar-gen3-hscif", 503 "renesas,hscif"; 504 reg = <0 0xe6550000 0 96>; 505 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 519>, 507 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 508 <&scif_clk>; 509 clock-names = "fck", "brg_int", "scif_clk"; 510 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 511 <&dmac2 0x33>, <&dmac2 0x32>; 512 dma-names = "tx", "rx", "tx", "rx"; 513 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 514 resets = <&cpg 519>; 515 status = "disabled"; 516 }; 517 518 hscif2: serial@e6560000 { 519 compatible = "renesas,hscif-r8a77970", 520 "renesas,rcar-gen3-hscif", 521 "renesas,hscif"; 522 reg = <0 0xe6560000 0 96>; 523 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&cpg CPG_MOD 518>, 525 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 526 <&scif_clk>; 527 clock-names = "fck", "brg_int", "scif_clk"; 528 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 529 <&dmac2 0x35>, <&dmac2 0x34>; 530 dma-names = "tx", "rx", "tx", "rx"; 531 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 532 resets = <&cpg 518>; 533 status = "disabled"; 534 }; 535 536 hscif3: serial@e66a0000 { 537 compatible = "renesas,hscif-r8a77970", 538 "renesas,rcar-gen3-hscif", "renesas,hscif"; 539 reg = <0 0xe66a0000 0 96>; 540 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cpg CPG_MOD 517>, 542 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 543 <&scif_clk>; 544 clock-names = "fck", "brg_int", "scif_clk"; 545 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 546 <&dmac2 0x37>, <&dmac2 0x36>; 547 dma-names = "tx", "rx", "tx", "rx"; 548 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 549 resets = <&cpg 517>; 550 status = "disabled"; 551 }; 552 553 canfd: can@e66c0000 { 554 compatible = "renesas,r8a77970-canfd", 555 "renesas,rcar-gen3-canfd"; 556 reg = <0 0xe66c0000 0 0x8000>; 557 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 914>, 560 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 561 <&can_clk>; 562 clock-names = "fck", "canfd", "can_clk"; 563 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 564 assigned-clock-rates = <40000000>; 565 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 566 resets = <&cpg 914>; 567 status = "disabled"; 568 569 channel0 { 570 status = "disabled"; 571 }; 572 573 channel1 { 574 status = "disabled"; 575 }; 576 }; 577 578 avb: ethernet@e6800000 { 579 compatible = "renesas,etheravb-r8a77970", 580 "renesas,etheravb-rcar-gen3"; 581 reg = <0 0xe6800000 0 0x800>; 582 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "ch0", "ch1", "ch2", "ch3", 608 "ch4", "ch5", "ch6", "ch7", 609 "ch8", "ch9", "ch10", "ch11", 610 "ch12", "ch13", "ch14", "ch15", 611 "ch16", "ch17", "ch18", "ch19", 612 "ch20", "ch21", "ch22", "ch23", 613 "ch24"; 614 clocks = <&cpg CPG_MOD 812>; 615 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 616 resets = <&cpg 812>; 617 phy-mode = "rgmii"; 618 rx-internal-delay-ps = <0>; 619 tx-internal-delay-ps = <0>; 620 iommus = <&ipmmu_rt 3>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 pwm0: pwm@e6e30000 { 627 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 628 reg = <0 0xe6e30000 0 8>; 629 #pwm-cells = <2>; 630 clocks = <&cpg CPG_MOD 523>; 631 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 632 resets = <&cpg 523>; 633 status = "disabled"; 634 }; 635 636 pwm1: pwm@e6e31000 { 637 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 638 reg = <0 0xe6e31000 0 8>; 639 #pwm-cells = <2>; 640 clocks = <&cpg CPG_MOD 523>; 641 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 642 resets = <&cpg 523>; 643 status = "disabled"; 644 }; 645 646 pwm2: pwm@e6e32000 { 647 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 648 reg = <0 0xe6e32000 0 8>; 649 #pwm-cells = <2>; 650 clocks = <&cpg CPG_MOD 523>; 651 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 652 resets = <&cpg 523>; 653 status = "disabled"; 654 }; 655 656 pwm3: pwm@e6e33000 { 657 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 658 reg = <0 0xe6e33000 0 8>; 659 #pwm-cells = <2>; 660 clocks = <&cpg CPG_MOD 523>; 661 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 662 resets = <&cpg 523>; 663 status = "disabled"; 664 }; 665 666 pwm4: pwm@e6e34000 { 667 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 668 reg = <0 0xe6e34000 0 8>; 669 #pwm-cells = <2>; 670 clocks = <&cpg CPG_MOD 523>; 671 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 672 resets = <&cpg 523>; 673 status = "disabled"; 674 }; 675 676 scif0: serial@e6e60000 { 677 compatible = "renesas,scif-r8a77970", 678 "renesas,rcar-gen3-scif", 679 "renesas,scif"; 680 reg = <0 0xe6e60000 0 64>; 681 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 207>, 683 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 684 <&scif_clk>; 685 clock-names = "fck", "brg_int", "scif_clk"; 686 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 687 <&dmac2 0x51>, <&dmac2 0x50>; 688 dma-names = "tx", "rx", "tx", "rx"; 689 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 690 resets = <&cpg 207>; 691 status = "disabled"; 692 }; 693 694 scif1: serial@e6e68000 { 695 compatible = "renesas,scif-r8a77970", 696 "renesas,rcar-gen3-scif", 697 "renesas,scif"; 698 reg = <0 0xe6e68000 0 64>; 699 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cpg CPG_MOD 206>, 701 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 702 <&scif_clk>; 703 clock-names = "fck", "brg_int", "scif_clk"; 704 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 705 <&dmac2 0x53>, <&dmac2 0x52>; 706 dma-names = "tx", "rx", "tx", "rx"; 707 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 708 resets = <&cpg 206>; 709 status = "disabled"; 710 }; 711 712 scif3: serial@e6c50000 { 713 compatible = "renesas,scif-r8a77970", 714 "renesas,rcar-gen3-scif", 715 "renesas,scif"; 716 reg = <0 0xe6c50000 0 64>; 717 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cpg CPG_MOD 204>, 719 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 720 <&scif_clk>; 721 clock-names = "fck", "brg_int", "scif_clk"; 722 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 723 <&dmac2 0x57>, <&dmac2 0x56>; 724 dma-names = "tx", "rx", "tx", "rx"; 725 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 726 resets = <&cpg 204>; 727 status = "disabled"; 728 }; 729 730 scif4: serial@e6c40000 { 731 compatible = "renesas,scif-r8a77970", 732 "renesas,rcar-gen3-scif", "renesas,scif"; 733 reg = <0 0xe6c40000 0 64>; 734 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cpg CPG_MOD 203>, 736 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 737 <&scif_clk>; 738 clock-names = "fck", "brg_int", "scif_clk"; 739 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 740 <&dmac2 0x59>, <&dmac2 0x58>; 741 dma-names = "tx", "rx", "tx", "rx"; 742 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 743 resets = <&cpg 203>; 744 status = "disabled"; 745 }; 746 747 tpu: pwm@e6e80000 { 748 compatible = "renesas,tpu-r8a77970", "renesas,tpu"; 749 reg = <0 0xe6e80000 0 0x148>; 750 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cpg CPG_MOD 304>; 752 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 753 resets = <&cpg 304>; 754 #pwm-cells = <3>; 755 status = "disabled"; 756 }; 757 758 msiof0: spi@e6e90000 { 759 compatible = "renesas,msiof-r8a77970", 760 "renesas,rcar-gen3-msiof"; 761 reg = <0 0xe6e90000 0 0x64>; 762 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cpg CPG_MOD 211>; 764 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 765 resets = <&cpg 211>; 766 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 767 <&dmac2 0x41>, <&dmac2 0x40>; 768 dma-names = "tx", "rx", "tx", "rx"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 msiof1: spi@e6ea0000 { 775 compatible = "renesas,msiof-r8a77970", 776 "renesas,rcar-gen3-msiof"; 777 reg = <0 0xe6ea0000 0 0x0064>; 778 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 210>; 780 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 781 resets = <&cpg 210>; 782 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 783 <&dmac2 0x43>, <&dmac2 0x42>; 784 dma-names = "tx", "rx", "tx", "rx"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "disabled"; 788 }; 789 790 msiof2: spi@e6c00000 { 791 compatible = "renesas,msiof-r8a77970", 792 "renesas,rcar-gen3-msiof"; 793 reg = <0 0xe6c00000 0 0x0064>; 794 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&cpg CPG_MOD 209>; 796 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 797 resets = <&cpg 209>; 798 dmas = <&dmac1 0x45>, <&dmac1 0x44>, 799 <&dmac2 0x45>, <&dmac2 0x44>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 msiof3: spi@e6c10000 { 807 compatible = "renesas,msiof-r8a77970", 808 "renesas,rcar-gen3-msiof"; 809 reg = <0 0xe6c10000 0 0x0064>; 810 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cpg CPG_MOD 208>; 812 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 813 resets = <&cpg 208>; 814 dmas = <&dmac1 0x47>, <&dmac1 0x46>, 815 <&dmac2 0x47>, <&dmac2 0x46>; 816 dma-names = "tx", "rx", "tx", "rx"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 vin0: video@e6ef0000 { 823 compatible = "renesas,vin-r8a77970"; 824 reg = <0 0xe6ef0000 0 0x1000>; 825 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD 811>; 827 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 828 resets = <&cpg 811>; 829 renesas,id = <0>; 830 status = "disabled"; 831 832 ports { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 port@1 { 837 #address-cells = <1>; 838 #size-cells = <0>; 839 840 reg = <1>; 841 842 vin0csi40: endpoint@2 { 843 reg = <2>; 844 remote-endpoint = <&csi40vin0>; 845 }; 846 }; 847 }; 848 }; 849 850 vin1: video@e6ef1000 { 851 compatible = "renesas,vin-r8a77970"; 852 reg = <0 0xe6ef1000 0 0x1000>; 853 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&cpg CPG_MOD 810>; 855 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 856 resets = <&cpg 810>; 857 renesas,id = <1>; 858 status = "disabled"; 859 860 ports { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 port@1 { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 868 reg = <1>; 869 870 vin1csi40: endpoint@2 { 871 reg = <2>; 872 remote-endpoint = <&csi40vin1>; 873 }; 874 }; 875 }; 876 }; 877 878 vin2: video@e6ef2000 { 879 compatible = "renesas,vin-r8a77970"; 880 reg = <0 0xe6ef2000 0 0x1000>; 881 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&cpg CPG_MOD 809>; 883 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 884 resets = <&cpg 809>; 885 renesas,id = <2>; 886 status = "disabled"; 887 888 ports { 889 #address-cells = <1>; 890 #size-cells = <0>; 891 892 port@1 { 893 #address-cells = <1>; 894 #size-cells = <0>; 895 896 reg = <1>; 897 898 vin2csi40: endpoint@2 { 899 reg = <2>; 900 remote-endpoint = <&csi40vin2>; 901 }; 902 }; 903 }; 904 }; 905 906 vin3: video@e6ef3000 { 907 compatible = "renesas,vin-r8a77970"; 908 reg = <0 0xe6ef3000 0 0x1000>; 909 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&cpg CPG_MOD 808>; 911 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 912 resets = <&cpg 808>; 913 renesas,id = <3>; 914 status = "disabled"; 915 916 ports { 917 #address-cells = <1>; 918 #size-cells = <0>; 919 920 port@1 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 924 reg = <1>; 925 926 vin3csi40: endpoint@2 { 927 reg = <2>; 928 remote-endpoint = <&csi40vin3>; 929 }; 930 }; 931 }; 932 }; 933 934 dmac1: dma-controller@e7300000 { 935 compatible = "renesas,dmac-r8a77970", 936 "renesas,rcar-dmac"; 937 reg = <0 0xe7300000 0 0x10000>; 938 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 947 interrupt-names = "error", 948 "ch0", "ch1", "ch2", "ch3", 949 "ch4", "ch5", "ch6", "ch7"; 950 clocks = <&cpg CPG_MOD 218>; 951 clock-names = "fck"; 952 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 953 resets = <&cpg 218>; 954 #dma-cells = <1>; 955 dma-channels = <8>; 956 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 957 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 958 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 959 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 960 }; 961 962 dmac2: dma-controller@e7310000 { 963 compatible = "renesas,dmac-r8a77970", 964 "renesas,rcar-dmac"; 965 reg = <0 0xe7310000 0 0x10000>; 966 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "error", 976 "ch0", "ch1", "ch2", "ch3", 977 "ch4", "ch5", "ch6", "ch7"; 978 clocks = <&cpg CPG_MOD 217>; 979 clock-names = "fck"; 980 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 981 resets = <&cpg 217>; 982 #dma-cells = <1>; 983 dma-channels = <8>; 984 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 985 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 986 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 987 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 988 }; 989 990 ipmmu_ds1: iommu@e7740000 { 991 compatible = "renesas,ipmmu-r8a77970"; 992 reg = <0 0xe7740000 0 0x1000>; 993 renesas,ipmmu-main = <&ipmmu_mm 0>; 994 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 995 #iommu-cells = <1>; 996 }; 997 998 ipmmu_ir: iommu@ff8b0000 { 999 compatible = "renesas,ipmmu-r8a77970"; 1000 reg = <0 0xff8b0000 0 0x1000>; 1001 renesas,ipmmu-main = <&ipmmu_mm 3>; 1002 power-domains = <&sysc R8A77970_PD_A3IR>; 1003 #iommu-cells = <1>; 1004 }; 1005 1006 ipmmu_mm: iommu@e67b0000 { 1007 compatible = "renesas,ipmmu-r8a77970"; 1008 reg = <0 0xe67b0000 0 0x1000>; 1009 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1011 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1012 #iommu-cells = <1>; 1013 }; 1014 1015 ipmmu_rt: iommu@ffc80000 { 1016 compatible = "renesas,ipmmu-r8a77970"; 1017 reg = <0 0xffc80000 0 0x1000>; 1018 renesas,ipmmu-main = <&ipmmu_mm 7>; 1019 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1020 #iommu-cells = <1>; 1021 }; 1022 1023 ipmmu_vi0: iommu@febd0000 { 1024 compatible = "renesas,ipmmu-r8a77970"; 1025 reg = <0 0xfebd0000 0 0x1000>; 1026 renesas,ipmmu-main = <&ipmmu_mm 9>; 1027 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1028 #iommu-cells = <1>; 1029 }; 1030 1031 mmc0: mmc@ee140000 { 1032 compatible = "renesas,sdhi-r8a77970", 1033 "renesas,rcar-gen3-sdhi"; 1034 reg = <0 0xee140000 0 0x2000>; 1035 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&cpg CPG_MOD 314>; 1037 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1038 resets = <&cpg 314>; 1039 max-frequency = <200000000>; 1040 iommus = <&ipmmu_ds1 32>; 1041 status = "disabled"; 1042 }; 1043 1044 rpc: spi@ee200000 { 1045 compatible = "renesas,r8a77970-rpc-if", 1046 "renesas,rcar-gen3-rpc-if"; 1047 reg = <0 0xee200000 0 0x200>, 1048 <0 0x08000000 0 0x4000000>, 1049 <0 0xee208000 0 0x100>; 1050 reg-names = "regs", "dirmap", "wbuf"; 1051 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&cpg CPG_MOD 917>; 1053 clock-names = "rpc"; 1054 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1055 resets = <&cpg 917>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 gic: interrupt-controller@f1010000 { 1062 compatible = "arm,gic-400"; 1063 #interrupt-cells = <3>; 1064 #address-cells = <0>; 1065 interrupt-controller; 1066 reg = <0 0xf1010000 0 0x1000>, 1067 <0 0xf1020000 0 0x20000>, 1068 <0 0xf1040000 0 0x20000>, 1069 <0 0xf1060000 0 0x20000>; 1070 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 1071 IRQ_TYPE_LEVEL_HIGH)>; 1072 clocks = <&cpg CPG_MOD 408>; 1073 clock-names = "clk"; 1074 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1075 resets = <&cpg 408>; 1076 }; 1077 1078 vspd0: vsp@fea20000 { 1079 compatible = "renesas,vsp2"; 1080 reg = <0 0xfea20000 0 0x5000>; 1081 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&cpg CPG_MOD 623>; 1083 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1084 resets = <&cpg 623>; 1085 renesas,fcp = <&fcpvd0>; 1086 }; 1087 1088 fcpvd0: fcp@fea27000 { 1089 compatible = "renesas,fcpv"; 1090 reg = <0 0xfea27000 0 0x200>; 1091 clocks = <&cpg CPG_MOD 603>; 1092 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1093 resets = <&cpg 603>; 1094 }; 1095 1096 csi40: csi2@feaa0000 { 1097 compatible = "renesas,r8a77970-csi2"; 1098 reg = <0 0xfeaa0000 0 0x10000>; 1099 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cpg CPG_MOD 716>; 1101 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1102 resets = <&cpg 716>; 1103 status = "disabled"; 1104 1105 ports { 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 1109 port@0 { 1110 reg = <0>; 1111 }; 1112 1113 port@1 { 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 1117 reg = <1>; 1118 1119 csi40vin0: endpoint@0 { 1120 reg = <0>; 1121 remote-endpoint = <&vin0csi40>; 1122 }; 1123 csi40vin1: endpoint@1 { 1124 reg = <1>; 1125 remote-endpoint = <&vin1csi40>; 1126 }; 1127 csi40vin2: endpoint@2 { 1128 reg = <2>; 1129 remote-endpoint = <&vin2csi40>; 1130 }; 1131 csi40vin3: endpoint@3 { 1132 reg = <3>; 1133 remote-endpoint = <&vin3csi40>; 1134 }; 1135 }; 1136 }; 1137 }; 1138 1139 du: display@feb00000 { 1140 compatible = "renesas,du-r8a77970"; 1141 reg = <0 0xfeb00000 0 0x80000>; 1142 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&cpg CPG_MOD 724>; 1144 clock-names = "du.0"; 1145 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1146 resets = <&cpg 724>; 1147 reset-names = "du.0"; 1148 renesas,vsps = <&vspd0 0>; 1149 1150 status = "disabled"; 1151 1152 ports { 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 1156 port@0 { 1157 reg = <0>; 1158 du_out_rgb: endpoint { 1159 }; 1160 }; 1161 1162 port@1 { 1163 reg = <1>; 1164 du_out_lvds0: endpoint { 1165 remote-endpoint = <&lvds0_in>; 1166 }; 1167 }; 1168 }; 1169 }; 1170 1171 lvds0: lvds-encoder@feb90000 { 1172 compatible = "renesas,r8a77970-lvds"; 1173 reg = <0 0xfeb90000 0 0x14>; 1174 clocks = <&cpg CPG_MOD 727>; 1175 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1176 resets = <&cpg 727>; 1177 status = "disabled"; 1178 1179 ports { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 port@0 { 1184 reg = <0>; 1185 lvds0_in: endpoint { 1186 remote-endpoint = 1187 <&du_out_lvds0>; 1188 }; 1189 }; 1190 port@1 { 1191 reg = <1>; 1192 lvds0_out: endpoint { 1193 }; 1194 }; 1195 }; 1196 }; 1197 1198 prr: chipid@fff00044 { 1199 compatible = "renesas,prr"; 1200 reg = <0 0xfff00044 0 4>; 1201 }; 1202 }; 1203 1204 thermal-zones { 1205 cpu-thermal { 1206 polling-delay-passive = <250>; 1207 polling-delay = <1000>; 1208 thermal-sensors = <&thermal>; 1209 1210 cooling-maps { 1211 }; 1212 1213 trips { 1214 cpu-crit { 1215 temperature = <120000>; 1216 hysteresis = <2000>; 1217 type = "critical"; 1218 }; 1219 }; 1220 }; 1221 }; 1222 1223 timer { 1224 compatible = "arm,armv8-timer"; 1225 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1226 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1227 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1228 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1229 }; 1230}; 1231