1cba59c25SWolfram Sang// SPDX-License-Identifier: GPL-2.0 2cc3e267eSSergei Shtylyov/* 3cc3e267eSSergei Shtylyov * Device Tree Source for the V3M Starter Kit board 4cc3e267eSSergei Shtylyov * 5cc3e267eSSergei Shtylyov * Copyright (C) 2017 Renesas Electronics Corp. 6cc3e267eSSergei Shtylyov * Copyright (C) 2017 Cogent Embedded, Inc. 7cc3e267eSSergei Shtylyov */ 8cc3e267eSSergei Shtylyov 9cc3e267eSSergei Shtylyov/dts-v1/; 10cc3e267eSSergei Shtylyov#include "r8a77970.dtsi" 11cc3e267eSSergei Shtylyov 12cc3e267eSSergei Shtylyov/ { 13cc3e267eSSergei Shtylyov model = "Renesas V3M Starter Kit board"; 14cc3e267eSSergei Shtylyov compatible = "renesas,v3msk", "renesas,r8a77970"; 15cc3e267eSSergei Shtylyov 16cc3e267eSSergei Shtylyov aliases { 17cc3e267eSSergei Shtylyov serial0 = &scif0; 18cc3e267eSSergei Shtylyov }; 19cc3e267eSSergei Shtylyov 20cc3e267eSSergei Shtylyov chosen { 21cc3e267eSSergei Shtylyov stdout-path = "serial0:115200n8"; 22cc3e267eSSergei Shtylyov }; 23cc3e267eSSergei Shtylyov 24cc3e267eSSergei Shtylyov memory@48000000 { 25cc3e267eSSergei Shtylyov device_type = "memory"; 26cc3e267eSSergei Shtylyov /* first 128MB is reserved for secure area. */ 27cc3e267eSSergei Shtylyov reg = <0x0 0x48000000 0x0 0x38000000>; 28cc3e267eSSergei Shtylyov }; 290c1861feSSergei Shtylyov 300c1861feSSergei Shtylyov osc5_clk: osc5-clock { 310c1861feSSergei Shtylyov compatible = "fixed-clock"; 320c1861feSSergei Shtylyov #clock-cells = <0>; 330c1861feSSergei Shtylyov clock-frequency = <148500000>; 340c1861feSSergei Shtylyov }; 350c1861feSSergei Shtylyov 360c1861feSSergei Shtylyov vcc_d1_8v: regulator-0 { 370c1861feSSergei Shtylyov compatible = "regulator-fixed"; 380c1861feSSergei Shtylyov regulator-name = "VCC_D1.8V"; 390c1861feSSergei Shtylyov regulator-min-microvolt = <1800000>; 400c1861feSSergei Shtylyov regulator-max-microvolt = <1800000>; 410c1861feSSergei Shtylyov regulator-boot-on; 420c1861feSSergei Shtylyov regulator-always-on; 430c1861feSSergei Shtylyov }; 440c1861feSSergei Shtylyov 450c1861feSSergei Shtylyov vcc_d3_3v: regulator-1 { 460c1861feSSergei Shtylyov compatible = "regulator-fixed"; 470c1861feSSergei Shtylyov regulator-name = "VCC_D3.3V"; 480c1861feSSergei Shtylyov regulator-min-microvolt = <3300000>; 490c1861feSSergei Shtylyov regulator-max-microvolt = <3300000>; 500c1861feSSergei Shtylyov regulator-boot-on; 510c1861feSSergei Shtylyov regulator-always-on; 520c1861feSSergei Shtylyov }; 530c1861feSSergei Shtylyov 540c1861feSSergei Shtylyov lvds-decoder { 550c1861feSSergei Shtylyov compatible = "thine,thc63lvd1024"; 560c1861feSSergei Shtylyov vcc-supply = <&vcc_d3_3v>; 570c1861feSSergei Shtylyov 580c1861feSSergei Shtylyov ports { 590c1861feSSergei Shtylyov #address-cells = <1>; 600c1861feSSergei Shtylyov #size-cells = <0>; 610c1861feSSergei Shtylyov 620c1861feSSergei Shtylyov port@0 { 630c1861feSSergei Shtylyov reg = <0>; 640c1861feSSergei Shtylyov thc63lvd1024_in: endpoint { 650c1861feSSergei Shtylyov remote-endpoint = <&lvds0_out>; 660c1861feSSergei Shtylyov }; 670c1861feSSergei Shtylyov }; 680c1861feSSergei Shtylyov 690c1861feSSergei Shtylyov port@2 { 700c1861feSSergei Shtylyov reg = <2>; 710c1861feSSergei Shtylyov thc63lvd1024_out: endpoint { 720c1861feSSergei Shtylyov remote-endpoint = <&adv7511_in>; 730c1861feSSergei Shtylyov }; 740c1861feSSergei Shtylyov }; 750c1861feSSergei Shtylyov }; 760c1861feSSergei Shtylyov }; 770c1861feSSergei Shtylyov 780c1861feSSergei Shtylyov hdmi-out { 790c1861feSSergei Shtylyov compatible = "hdmi-connector"; 800c1861feSSergei Shtylyov type = "a"; 810c1861feSSergei Shtylyov 820c1861feSSergei Shtylyov port { 830c1861feSSergei Shtylyov hdmi_con: endpoint { 840c1861feSSergei Shtylyov remote-endpoint = <&adv7511_out>; 850c1861feSSergei Shtylyov }; 860c1861feSSergei Shtylyov }; 870c1861feSSergei Shtylyov }; 88cc3e267eSSergei Shtylyov}; 89cc3e267eSSergei Shtylyov 90a6b1b735SSergei Shtylyov&avb { 9168d3b03fSSergei Shtylyov pinctrl-0 = <&avb_pins>; 9268d3b03fSSergei Shtylyov pinctrl-names = "default"; 9368d3b03fSSergei Shtylyov 94a6b1b735SSergei Shtylyov renesas,no-ether-link; 95a6b1b735SSergei Shtylyov phy-handle = <&phy0>; 969dcd1f26SJacopo Mondi phy-mode = "rgmii-id"; 97a6b1b735SSergei Shtylyov status = "okay"; 98a6b1b735SSergei Shtylyov 99a6b1b735SSergei Shtylyov phy0: ethernet-phy@0 { 100a6b1b735SSergei Shtylyov rxc-skew-ps = <1500>; 101a6b1b735SSergei Shtylyov reg = <0>; 102a6b1b735SSergei Shtylyov }; 103a6b1b735SSergei Shtylyov}; 104a6b1b735SSergei Shtylyov 1050c1861feSSergei Shtylyov&du { 1060c1861feSSergei Shtylyov clocks = <&cpg CPG_MOD 724>, 1070c1861feSSergei Shtylyov <&osc5_clk>; 1080c1861feSSergei Shtylyov clock-names = "du.0", "dclkin.0"; 1090c1861feSSergei Shtylyov status = "okay"; 1100c1861feSSergei Shtylyov}; 1110c1861feSSergei Shtylyov 112cc3e267eSSergei Shtylyov&extal_clk { 113cc3e267eSSergei Shtylyov clock-frequency = <16666666>; 114cc3e267eSSergei Shtylyov}; 115cc3e267eSSergei Shtylyov 116cc3e267eSSergei Shtylyov&extalr_clk { 117cc3e267eSSergei Shtylyov clock-frequency = <32768>; 118cc3e267eSSergei Shtylyov}; 119cc3e267eSSergei Shtylyov 120ca565be2SSergei Shtylyov&pfc { 12168d3b03fSSergei Shtylyov avb_pins: avb0 { 12268d3b03fSSergei Shtylyov groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; 12368d3b03fSSergei Shtylyov function = "avb0"; 12468d3b03fSSergei Shtylyov }; 12568d3b03fSSergei Shtylyov 1260c1861feSSergei Shtylyov i2c0_pins: i2c0 { 1270c1861feSSergei Shtylyov groups = "i2c0"; 1280c1861feSSergei Shtylyov function = "i2c0"; 1290c1861feSSergei Shtylyov }; 1300c1861feSSergei Shtylyov 131ca565be2SSergei Shtylyov scif0_pins: scif0 { 132ca565be2SSergei Shtylyov groups = "scif0_data"; 133ca565be2SSergei Shtylyov function = "scif0"; 134ca565be2SSergei Shtylyov }; 135ca565be2SSergei Shtylyov}; 136ca565be2SSergei Shtylyov 1370c1861feSSergei Shtylyov&i2c0 { 1380c1861feSSergei Shtylyov pinctrl-0 = <&i2c0_pins>; 1390c1861feSSergei Shtylyov pinctrl-names = "default"; 1400c1861feSSergei Shtylyov 1410c1861feSSergei Shtylyov status = "okay"; 1420c1861feSSergei Shtylyov clock-frequency = <400000>; 1430c1861feSSergei Shtylyov 1440c1861feSSergei Shtylyov hdmi@39{ 1450c1861feSSergei Shtylyov compatible = "adi,adv7511w"; 1460c1861feSSergei Shtylyov #sound-dai-cells = <0>; 1470c1861feSSergei Shtylyov reg = <0x39>; 1480c1861feSSergei Shtylyov interrupt-parent = <&gpio1>; 1490c1861feSSergei Shtylyov interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 1500c1861feSSergei Shtylyov avdd-supply = <&vcc_d1_8v>; 1510c1861feSSergei Shtylyov dvdd-supply = <&vcc_d1_8v>; 1520c1861feSSergei Shtylyov pvdd-supply = <&vcc_d1_8v>; 1530c1861feSSergei Shtylyov bgvdd-supply = <&vcc_d1_8v>; 1540c1861feSSergei Shtylyov dvdd-3v-supply = <&vcc_d3_3v>; 1550c1861feSSergei Shtylyov 1560c1861feSSergei Shtylyov adi,input-depth = <8>; 1570c1861feSSergei Shtylyov adi,input-colorspace = "rgb"; 1580c1861feSSergei Shtylyov adi,input-clock = "1x"; 1590c1861feSSergei Shtylyov adi,input-style = <1>; 1600c1861feSSergei Shtylyov adi,input-justification = "evenly"; 1610c1861feSSergei Shtylyov 1620c1861feSSergei Shtylyov ports { 1630c1861feSSergei Shtylyov #address-cells = <1>; 1640c1861feSSergei Shtylyov #size-cells = <0>; 1650c1861feSSergei Shtylyov 1660c1861feSSergei Shtylyov port@0 { 1670c1861feSSergei Shtylyov reg = <0>; 1680c1861feSSergei Shtylyov adv7511_in: endpoint { 1690c1861feSSergei Shtylyov remote-endpoint = <&thc63lvd1024_out>; 1700c1861feSSergei Shtylyov }; 1710c1861feSSergei Shtylyov }; 1720c1861feSSergei Shtylyov 1730c1861feSSergei Shtylyov port@1 { 1740c1861feSSergei Shtylyov reg = <1>; 1750c1861feSSergei Shtylyov adv7511_out: endpoint { 1760c1861feSSergei Shtylyov remote-endpoint = <&hdmi_con>; 1770c1861feSSergei Shtylyov }; 1780c1861feSSergei Shtylyov }; 1790c1861feSSergei Shtylyov }; 1800c1861feSSergei Shtylyov }; 1810c1861feSSergei Shtylyov}; 1820c1861feSSergei Shtylyov 1830c1861feSSergei Shtylyov&lvds0 { 1840c1861feSSergei Shtylyov status = "okay"; 1850c1861feSSergei Shtylyov 1860c1861feSSergei Shtylyov ports { 1870c1861feSSergei Shtylyov port@1 { 1880c1861feSSergei Shtylyov lvds0_out: endpoint { 1890c1861feSSergei Shtylyov remote-endpoint = <&thc63lvd1024_in>; 1900c1861feSSergei Shtylyov }; 1910c1861feSSergei Shtylyov }; 1920c1861feSSergei Shtylyov }; 1930c1861feSSergei Shtylyov}; 1940c1861feSSergei Shtylyov 195cc3e267eSSergei Shtylyov&scif0 { 196ca565be2SSergei Shtylyov pinctrl-0 = <&scif0_pins>; 197ca565be2SSergei Shtylyov pinctrl-names = "default"; 198ca565be2SSergei Shtylyov 199cc3e267eSSergei Shtylyov status = "okay"; 200cc3e267eSSergei Shtylyov}; 201