1cba59c25SWolfram Sang// SPDX-License-Identifier: GPL-2.0
2cc3e267eSSergei Shtylyov/*
3cc3e267eSSergei Shtylyov * Device Tree Source for the V3M Starter Kit board
4cc3e267eSSergei Shtylyov *
5cc3e267eSSergei Shtylyov * Copyright (C) 2017 Renesas Electronics Corp.
6cc3e267eSSergei Shtylyov * Copyright (C) 2017 Cogent Embedded, Inc.
7cc3e267eSSergei Shtylyov */
8cc3e267eSSergei Shtylyov
9cc3e267eSSergei Shtylyov/dts-v1/;
10cc3e267eSSergei Shtylyov#include "r8a77970.dtsi"
11732e8ee0SGeert Uytterhoeven#include <dt-bindings/gpio/gpio.h>
12cc3e267eSSergei Shtylyov
13cc3e267eSSergei Shtylyov/ {
14cc3e267eSSergei Shtylyov	model = "Renesas V3M Starter Kit board";
15cc3e267eSSergei Shtylyov	compatible = "renesas,v3msk", "renesas,r8a77970";
16cc3e267eSSergei Shtylyov
17cc3e267eSSergei Shtylyov	aliases {
18*8cc5dcfaSWolfram Sang		i2c0 = &i2c0;
19*8cc5dcfaSWolfram Sang		i2c1 = &i2c1;
20*8cc5dcfaSWolfram Sang		i2c2 = &i2c2;
21*8cc5dcfaSWolfram Sang		i2c3 = &i2c3;
22*8cc5dcfaSWolfram Sang		i2c4 = &i2c4;
23cc3e267eSSergei Shtylyov		serial0 = &scif0;
24cc3e267eSSergei Shtylyov	};
25cc3e267eSSergei Shtylyov
26cc3e267eSSergei Shtylyov	chosen {
27cc3e267eSSergei Shtylyov		stdout-path = "serial0:115200n8";
28cc3e267eSSergei Shtylyov	};
29cc3e267eSSergei Shtylyov
3043afe206SYoshihiro Kaneko	hdmi-out {
3143afe206SYoshihiro Kaneko		compatible = "hdmi-connector";
3243afe206SYoshihiro Kaneko		type = "a";
3343afe206SYoshihiro Kaneko
3443afe206SYoshihiro Kaneko		port {
3543afe206SYoshihiro Kaneko			hdmi_con: endpoint {
3643afe206SYoshihiro Kaneko				remote-endpoint = <&adv7511_out>;
3743afe206SYoshihiro Kaneko			};
3843afe206SYoshihiro Kaneko		};
3943afe206SYoshihiro Kaneko	};
4043afe206SYoshihiro Kaneko
4143afe206SYoshihiro Kaneko	lvds-decoder {
4243afe206SYoshihiro Kaneko		compatible = "thine,thc63lvd1024";
4343afe206SYoshihiro Kaneko		vcc-supply = <&vcc_d3_3v>;
4443afe206SYoshihiro Kaneko
4543afe206SYoshihiro Kaneko		ports {
4643afe206SYoshihiro Kaneko			#address-cells = <1>;
4743afe206SYoshihiro Kaneko			#size-cells = <0>;
4843afe206SYoshihiro Kaneko
4943afe206SYoshihiro Kaneko			port@0 {
5043afe206SYoshihiro Kaneko				reg = <0>;
5143afe206SYoshihiro Kaneko				thc63lvd1024_in: endpoint {
5243afe206SYoshihiro Kaneko					remote-endpoint = <&lvds0_out>;
5343afe206SYoshihiro Kaneko				};
5443afe206SYoshihiro Kaneko			};
5543afe206SYoshihiro Kaneko
5643afe206SYoshihiro Kaneko			port@2 {
5743afe206SYoshihiro Kaneko				reg = <2>;
5843afe206SYoshihiro Kaneko				thc63lvd1024_out: endpoint {
5943afe206SYoshihiro Kaneko					remote-endpoint = <&adv7511_in>;
6043afe206SYoshihiro Kaneko				};
6143afe206SYoshihiro Kaneko			};
6243afe206SYoshihiro Kaneko		};
6343afe206SYoshihiro Kaneko	};
6443afe206SYoshihiro Kaneko
65cc3e267eSSergei Shtylyov	memory@48000000 {
66cc3e267eSSergei Shtylyov		device_type = "memory";
67cc3e267eSSergei Shtylyov		/* first 128MB is reserved for secure area. */
68a422ec20SValentine Barshak		reg = <0x0 0x48000000 0x0 0x78000000>;
69cc3e267eSSergei Shtylyov	};
700c1861feSSergei Shtylyov
710c1861feSSergei Shtylyov	osc5_clk: osc5-clock {
720c1861feSSergei Shtylyov		compatible = "fixed-clock";
730c1861feSSergei Shtylyov		#clock-cells = <0>;
740c1861feSSergei Shtylyov		clock-frequency = <148500000>;
750c1861feSSergei Shtylyov	};
760c1861feSSergei Shtylyov
770c1861feSSergei Shtylyov	vcc_d1_8v: regulator-0 {
780c1861feSSergei Shtylyov		compatible = "regulator-fixed";
790c1861feSSergei Shtylyov		regulator-name = "VCC_D1.8V";
800c1861feSSergei Shtylyov		regulator-min-microvolt = <1800000>;
810c1861feSSergei Shtylyov		regulator-max-microvolt = <1800000>;
820c1861feSSergei Shtylyov		regulator-boot-on;
830c1861feSSergei Shtylyov		regulator-always-on;
840c1861feSSergei Shtylyov	};
850c1861feSSergei Shtylyov
860c1861feSSergei Shtylyov	vcc_d3_3v: regulator-1 {
870c1861feSSergei Shtylyov		compatible = "regulator-fixed";
880c1861feSSergei Shtylyov		regulator-name = "VCC_D3.3V";
890c1861feSSergei Shtylyov		regulator-min-microvolt = <3300000>;
900c1861feSSergei Shtylyov		regulator-max-microvolt = <3300000>;
910c1861feSSergei Shtylyov		regulator-boot-on;
920c1861feSSergei Shtylyov		regulator-always-on;
930c1861feSSergei Shtylyov	};
940c1861feSSergei Shtylyov
958d9923b3SSergei Shtylyov	vcc_vddq_vin0: regulator-2 {
968d9923b3SSergei Shtylyov		compatible = "regulator-fixed";
978d9923b3SSergei Shtylyov		regulator-name = "VCC_VDDQ_VIN0";
988d9923b3SSergei Shtylyov		regulator-min-microvolt = <3300000>;
998d9923b3SSergei Shtylyov		regulator-max-microvolt = <3300000>;
1008d9923b3SSergei Shtylyov		regulator-boot-on;
1018d9923b3SSergei Shtylyov		regulator-always-on;
1028d9923b3SSergei Shtylyov	};
103cc3e267eSSergei Shtylyov};
104cc3e267eSSergei Shtylyov
105a6b1b735SSergei Shtylyov&avb {
10668d3b03fSSergei Shtylyov	pinctrl-0 = <&avb_pins>;
10768d3b03fSSergei Shtylyov	pinctrl-names = "default";
10868d3b03fSSergei Shtylyov
109a6b1b735SSergei Shtylyov	renesas,no-ether-link;
110a6b1b735SSergei Shtylyov	phy-handle = <&phy0>;
1119b810181SGeert Uytterhoeven	rx-internal-delay-ps = <1800>;
1129b810181SGeert Uytterhoeven	tx-internal-delay-ps = <2000>;
113a6b1b735SSergei Shtylyov	status = "okay";
114a6b1b735SSergei Shtylyov
115a6b1b735SSergei Shtylyov	phy0: ethernet-phy@0 {
116722d55f3SGeert Uytterhoeven		compatible = "ethernet-phy-id0022.1622",
117722d55f3SGeert Uytterhoeven			     "ethernet-phy-ieee802.3-c22";
118a6b1b735SSergei Shtylyov		rxc-skew-ps = <1500>;
119a6b1b735SSergei Shtylyov		reg = <0>;
120d5e5790cSSergei Shtylyov		interrupt-parent = <&gpio1>;
121d5e5790cSSergei Shtylyov		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
122732e8ee0SGeert Uytterhoeven		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
123a6b1b735SSergei Shtylyov	};
124a6b1b735SSergei Shtylyov};
125a6b1b735SSergei Shtylyov
1260c1861feSSergei Shtylyov&du {
1270c1861feSSergei Shtylyov	clocks = <&cpg CPG_MOD 724>,
1280c1861feSSergei Shtylyov		 <&osc5_clk>;
1290c1861feSSergei Shtylyov	clock-names = "du.0", "dclkin.0";
1300c1861feSSergei Shtylyov	status = "okay";
1310c1861feSSergei Shtylyov};
1320c1861feSSergei Shtylyov
133cc3e267eSSergei Shtylyov&extal_clk {
134cc3e267eSSergei Shtylyov	clock-frequency = <16666666>;
135cc3e267eSSergei Shtylyov};
136cc3e267eSSergei Shtylyov
137cc3e267eSSergei Shtylyov&extalr_clk {
138cc3e267eSSergei Shtylyov	clock-frequency = <32768>;
139cc3e267eSSergei Shtylyov};
140cc3e267eSSergei Shtylyov
1410c1861feSSergei Shtylyov&i2c0 {
1420c1861feSSergei Shtylyov	pinctrl-0 = <&i2c0_pins>;
1430c1861feSSergei Shtylyov	pinctrl-names = "default";
1440c1861feSSergei Shtylyov
1450c1861feSSergei Shtylyov	status = "okay";
1460c1861feSSergei Shtylyov	clock-frequency = <400000>;
1470c1861feSSergei Shtylyov
1480c1861feSSergei Shtylyov	hdmi@39 {
1490c1861feSSergei Shtylyov		compatible = "adi,adv7511w";
1500c1861feSSergei Shtylyov		#sound-dai-cells = <0>;
1510c1861feSSergei Shtylyov		reg = <0x39>;
1520c1861feSSergei Shtylyov		interrupt-parent = <&gpio1>;
1530c1861feSSergei Shtylyov		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
1540c1861feSSergei Shtylyov		avdd-supply = <&vcc_d1_8v>;
1550c1861feSSergei Shtylyov		dvdd-supply = <&vcc_d1_8v>;
1560c1861feSSergei Shtylyov		pvdd-supply = <&vcc_d1_8v>;
1570c1861feSSergei Shtylyov		bgvdd-supply = <&vcc_d1_8v>;
1580c1861feSSergei Shtylyov		dvdd-3v-supply = <&vcc_d3_3v>;
1590c1861feSSergei Shtylyov
1600c1861feSSergei Shtylyov		adi,input-depth = <8>;
1610c1861feSSergei Shtylyov		adi,input-colorspace = "rgb";
1620c1861feSSergei Shtylyov		adi,input-clock = "1x";
1630c1861feSSergei Shtylyov
1640c1861feSSergei Shtylyov		ports {
1650c1861feSSergei Shtylyov			#address-cells = <1>;
1660c1861feSSergei Shtylyov			#size-cells = <0>;
1670c1861feSSergei Shtylyov
1680c1861feSSergei Shtylyov			port@0 {
1690c1861feSSergei Shtylyov				reg = <0>;
1700c1861feSSergei Shtylyov				adv7511_in: endpoint {
1710c1861feSSergei Shtylyov					remote-endpoint = <&thc63lvd1024_out>;
1720c1861feSSergei Shtylyov				};
1730c1861feSSergei Shtylyov			};
1740c1861feSSergei Shtylyov
1750c1861feSSergei Shtylyov			port@1 {
1760c1861feSSergei Shtylyov				reg = <1>;
1770c1861feSSergei Shtylyov				adv7511_out: endpoint {
1780c1861feSSergei Shtylyov					remote-endpoint = <&hdmi_con>;
1790c1861feSSergei Shtylyov				};
1800c1861feSSergei Shtylyov			};
1810c1861feSSergei Shtylyov		};
1820c1861feSSergei Shtylyov	};
1830c1861feSSergei Shtylyov};
1840c1861feSSergei Shtylyov
1850c1861feSSergei Shtylyov&lvds0 {
1860c1861feSSergei Shtylyov	status = "okay";
1870c1861feSSergei Shtylyov
1880c1861feSSergei Shtylyov	ports {
1890c1861feSSergei Shtylyov		port@1 {
1900c1861feSSergei Shtylyov			lvds0_out: endpoint {
1910c1861feSSergei Shtylyov				remote-endpoint = <&thc63lvd1024_in>;
1920c1861feSSergei Shtylyov			};
1930c1861feSSergei Shtylyov		};
1940c1861feSSergei Shtylyov	};
1950c1861feSSergei Shtylyov};
1960c1861feSSergei Shtylyov
1978d9923b3SSergei Shtylyov&mmc0 {
1988d9923b3SSergei Shtylyov	pinctrl-0 = <&mmc_pins>;
1998d9923b3SSergei Shtylyov	pinctrl-names = "default";
2008d9923b3SSergei Shtylyov
2018d9923b3SSergei Shtylyov	vmmc-supply = <&vcc_d3_3v>;
2028d9923b3SSergei Shtylyov	vqmmc-supply = <&vcc_vddq_vin0>;
2038d9923b3SSergei Shtylyov	bus-width = <8>;
2048d9923b3SSergei Shtylyov	non-removable;
2058d9923b3SSergei Shtylyov	status = "okay";
2068d9923b3SSergei Shtylyov};
2078d9923b3SSergei Shtylyov
20843afe206SYoshihiro Kaneko&pfc {
20943afe206SYoshihiro Kaneko	avb_pins: avb0 {
21043afe206SYoshihiro Kaneko		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
21143afe206SYoshihiro Kaneko		function = "avb0";
21243afe206SYoshihiro Kaneko	};
21343afe206SYoshihiro Kaneko
21443afe206SYoshihiro Kaneko	i2c0_pins: i2c0 {
21543afe206SYoshihiro Kaneko		groups = "i2c0";
21643afe206SYoshihiro Kaneko		function = "i2c0";
21743afe206SYoshihiro Kaneko	};
21843afe206SYoshihiro Kaneko
21943afe206SYoshihiro Kaneko	mmc_pins: mmc_3_3v {
22043afe206SYoshihiro Kaneko		groups = "mmc_data8", "mmc_ctrl";
22143afe206SYoshihiro Kaneko		function = "mmc";
22243afe206SYoshihiro Kaneko		power-source = <3300>;
22343afe206SYoshihiro Kaneko	};
22443afe206SYoshihiro Kaneko
225daa36ae0SSergei Shtylyov	qspi0_pins: qspi0 {
226daa36ae0SSergei Shtylyov		groups = "qspi0_ctrl", "qspi0_data4";
227daa36ae0SSergei Shtylyov		function = "qspi0";
228daa36ae0SSergei Shtylyov	};
229daa36ae0SSergei Shtylyov
23043afe206SYoshihiro Kaneko	scif0_pins: scif0 {
23143afe206SYoshihiro Kaneko		groups = "scif0_data";
23243afe206SYoshihiro Kaneko		function = "scif0";
23343afe206SYoshihiro Kaneko	};
23443afe206SYoshihiro Kaneko};
23543afe206SYoshihiro Kaneko
236daa36ae0SSergei Shtylyov&rpc {
237daa36ae0SSergei Shtylyov	pinctrl-0 = <&qspi0_pins>;
238daa36ae0SSergei Shtylyov	pinctrl-names = "default";
239daa36ae0SSergei Shtylyov
240daa36ae0SSergei Shtylyov	status = "okay";
241daa36ae0SSergei Shtylyov
242daa36ae0SSergei Shtylyov	flash@0 {
243daa36ae0SSergei Shtylyov		compatible = "spansion,s25fs512s", "jedec,spi-nor";
244daa36ae0SSergei Shtylyov		reg = <0>;
245daa36ae0SSergei Shtylyov		spi-max-frequency = <50000000>;
246daa36ae0SSergei Shtylyov		spi-rx-bus-width = <4>;
247daa36ae0SSergei Shtylyov
248daa36ae0SSergei Shtylyov		partitions {
249daa36ae0SSergei Shtylyov			compatible = "fixed-partitions";
250daa36ae0SSergei Shtylyov			#address-cells = <1>;
251daa36ae0SSergei Shtylyov			#size-cells = <1>;
252daa36ae0SSergei Shtylyov
253daa36ae0SSergei Shtylyov			bootparam@0 {
254daa36ae0SSergei Shtylyov				reg = <0x00000000 0x040000>;
255daa36ae0SSergei Shtylyov				read-only;
256daa36ae0SSergei Shtylyov			};
257daa36ae0SSergei Shtylyov			cr7@40000 {
258daa36ae0SSergei Shtylyov				reg = <0x00040000 0x080000>;
259daa36ae0SSergei Shtylyov				read-only;
260daa36ae0SSergei Shtylyov			};
261daa36ae0SSergei Shtylyov			cert_header_sa3@c0000 {
262daa36ae0SSergei Shtylyov				reg = <0x000c0000 0x080000>;
263daa36ae0SSergei Shtylyov				read-only;
264daa36ae0SSergei Shtylyov			};
265daa36ae0SSergei Shtylyov			bl2@140000 {
266daa36ae0SSergei Shtylyov				reg = <0x00140000 0x040000>;
267daa36ae0SSergei Shtylyov				read-only;
268daa36ae0SSergei Shtylyov			};
269daa36ae0SSergei Shtylyov			cert_header_sa6@180000 {
270daa36ae0SSergei Shtylyov				reg = <0x00180000 0x040000>;
271daa36ae0SSergei Shtylyov				read-only;
272daa36ae0SSergei Shtylyov			};
273daa36ae0SSergei Shtylyov			bl31@1c0000 {
274daa36ae0SSergei Shtylyov				reg = <0x001c0000 0x460000>;
275daa36ae0SSergei Shtylyov				read-only;
276daa36ae0SSergei Shtylyov			};
277daa36ae0SSergei Shtylyov			uboot@640000 {
278daa36ae0SSergei Shtylyov				reg = <0x00640000 0x0c0000>;
279daa36ae0SSergei Shtylyov				read-only;
280daa36ae0SSergei Shtylyov			};
281daa36ae0SSergei Shtylyov			uboot-env@700000 {
282daa36ae0SSergei Shtylyov				reg = <0x00700000 0x040000>;
283daa36ae0SSergei Shtylyov				read-only;
284daa36ae0SSergei Shtylyov			};
285daa36ae0SSergei Shtylyov			dtb@740000 {
286daa36ae0SSergei Shtylyov				reg = <0x00740000 0x080000>;
287daa36ae0SSergei Shtylyov			};
288daa36ae0SSergei Shtylyov			kernel@7c0000 {
289daa36ae0SSergei Shtylyov				reg = <0x007c0000 0x1400000>;
290daa36ae0SSergei Shtylyov			};
291daa36ae0SSergei Shtylyov			user@1bc0000 {
292daa36ae0SSergei Shtylyov				reg = <0x01bc0000 0x2440000>;
293daa36ae0SSergei Shtylyov			};
294daa36ae0SSergei Shtylyov		};
295daa36ae0SSergei Shtylyov	};
296daa36ae0SSergei Shtylyov};
297daa36ae0SSergei Shtylyov
298cc3e267eSSergei Shtylyov&scif0 {
299ca565be2SSergei Shtylyov	pinctrl-0 = <&scif0_pins>;
300ca565be2SSergei Shtylyov	pinctrl-names = "default";
301ca565be2SSergei Shtylyov
302cc3e267eSSergei Shtylyov	status = "okay";
303cc3e267eSSergei Shtylyov};
304