1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77965 SoC 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Based on r8a7796.dtsi 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 */ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#define CPG_AUDIO_CLK_I 10 15 16/ { 17 compatible = "renesas,r8a77965"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a57_0: cpu@0 { 31 compatible = "arm,cortex-a57", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc 0>; 35 next-level-cache = <&L2_CA57>; 36 enable-method = "psci"; 37 }; 38 39 a57_1: cpu@1 { 40 compatible = "arm,cortex-a57","arm,armv8"; 41 reg = <0x1>; 42 device_type = "cpu"; 43 power-domains = <&sysc 1>; 44 next-level-cache = <&L2_CA57>; 45 enable-method = "psci"; 46 }; 47 48 L2_CA57: cache-controller-0 { 49 compatible = "cache"; 50 reg = <0>; 51 power-domains = <&sysc 12>; 52 cache-unified; 53 cache-level = <2>; 54 }; 55 }; 56 57 extal_clk: extal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 /* This value must be overridden by the board */ 61 clock-frequency = <0>; 62 }; 63 64 extalr_clk: extalr { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 /* This value must be overridden by the board */ 68 clock-frequency = <0>; 69 }; 70 71 /* 72 * The external audio clocks are configured as 0 Hz fixed frequency 73 * clocks by default. 74 * Boards that provide audio clocks should override them. 75 */ 76 audio_clk_a: audio_clk_a { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <0>; 80 }; 81 82 audio_clk_b: audio_clk_b { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <0>; 86 }; 87 88 audio_clk_c: audio_clk_c { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <0>; 92 }; 93 94 /* External CAN clock - to be overridden by boards that provide it */ 95 can_clk: can { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <0>; 99 }; 100 101 /* External SCIF clock - to be overridden by boards that provide it */ 102 scif_clk: scif { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 /* External PCIe clock - can be overridden by the board */ 109 pcie_bus_clk: pcie_bus { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <0>; 113 }; 114 115 /* External USB clocks - can be overridden by the board */ 116 usb3s0_clk: usb3s0 { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <0>; 120 }; 121 122 usb_extal_clk: usb_extal { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <0>; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 131 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 132 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 133 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 134 }; 135 136 pmu_a57 { 137 compatible = "arm,cortex-a57-pmu"; 138 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 139 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 140 interrupt-affinity = <&a57_0>, 141 <&a57_1>; 142 }; 143 144 soc { 145 compatible = "simple-bus"; 146 interrupt-parent = <&gic>; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 gic: interrupt-controller@f1010000 { 152 compatible = "arm,gic-400"; 153 #interrupt-cells = <3>; 154 #address-cells = <0>; 155 interrupt-controller; 156 reg = <0x0 0xf1010000 0 0x1000>, 157 <0x0 0xf1020000 0 0x20000>, 158 <0x0 0xf1040000 0 0x20000>, 159 <0x0 0xf1060000 0 0x20000>; 160 interrupts = <GIC_PPI 9 161 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 162 clocks = <&cpg CPG_MOD 408>; 163 clock-names = "clk"; 164 power-domains = <&sysc 32>; 165 resets = <&cpg 408>; 166 }; 167 168 pfc: pin-controller@e6060000 { 169 compatible = "renesas,pfc-r8a77965"; 170 reg = <0 0xe6060000 0 0x50c>; 171 }; 172 173 cpg: clock-controller@e6150000 { 174 compatible = "renesas,r8a77965-cpg-mssr"; 175 reg = <0 0xe6150000 0 0x1000>; 176 clocks = <&extal_clk>, <&extalr_clk>; 177 clock-names = "extal", "extalr"; 178 #clock-cells = <2>; 179 #power-domain-cells = <0>; 180 #reset-cells = <1>; 181 }; 182 183 rst: reset-controller@e6160000 { 184 compatible = "renesas,r8a77965-rst"; 185 reg = <0 0xe6160000 0 0x0200>; 186 }; 187 188 prr: chipid@fff00044 { 189 compatible = "renesas,prr"; 190 reg = <0 0xfff00044 0 4>; 191 }; 192 193 sysc: system-controller@e6180000 { 194 compatible = "renesas,r8a77965-sysc"; 195 reg = <0 0xe6180000 0 0x0400>; 196 #power-domain-cells = <1>; 197 }; 198 199 gpio0: gpio@e6050000 { 200 compatible = "renesas,gpio-r8a77965", 201 "renesas,rcar-gen3-gpio"; 202 reg = <0 0xe6050000 0 0x50>; 203 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 204 #gpio-cells = <2>; 205 gpio-controller; 206 gpio-ranges = <&pfc 0 0 16>; 207 #interrupt-cells = <2>; 208 interrupt-controller; 209 clocks = <&cpg CPG_MOD 912>; 210 power-domains = <&sysc 32>; 211 resets = <&cpg 912>; 212 }; 213 214 gpio1: gpio@e6051000 { 215 compatible = "renesas,gpio-r8a77965", 216 "renesas,rcar-gen3-gpio"; 217 reg = <0 0xe6051000 0 0x50>; 218 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 219 #gpio-cells = <2>; 220 gpio-controller; 221 gpio-ranges = <&pfc 0 32 29>; 222 #interrupt-cells = <2>; 223 interrupt-controller; 224 clocks = <&cpg CPG_MOD 911>; 225 power-domains = <&sysc 32>; 226 resets = <&cpg 911>; 227 }; 228 229 gpio2: gpio@e6052000 { 230 compatible = "renesas,gpio-r8a77965", 231 "renesas,rcar-gen3-gpio"; 232 reg = <0 0xe6052000 0 0x50>; 233 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 234 #gpio-cells = <2>; 235 gpio-controller; 236 gpio-ranges = <&pfc 0 64 15>; 237 #interrupt-cells = <2>; 238 interrupt-controller; 239 clocks = <&cpg CPG_MOD 910>; 240 power-domains = <&sysc 32>; 241 resets = <&cpg 910>; 242 }; 243 244 gpio3: gpio@e6053000 { 245 compatible = "renesas,gpio-r8a77965", 246 "renesas,rcar-gen3-gpio"; 247 reg = <0 0xe6053000 0 0x50>; 248 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 249 #gpio-cells = <2>; 250 gpio-controller; 251 gpio-ranges = <&pfc 0 96 16>; 252 #interrupt-cells = <2>; 253 interrupt-controller; 254 clocks = <&cpg CPG_MOD 909>; 255 power-domains = <&sysc 32>; 256 resets = <&cpg 909>; 257 }; 258 259 gpio4: gpio@e6054000 { 260 compatible = "renesas,gpio-r8a77965", 261 "renesas,rcar-gen3-gpio"; 262 reg = <0 0xe6054000 0 0x50>; 263 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 264 #gpio-cells = <2>; 265 gpio-controller; 266 gpio-ranges = <&pfc 0 128 18>; 267 #interrupt-cells = <2>; 268 interrupt-controller; 269 clocks = <&cpg CPG_MOD 908>; 270 power-domains = <&sysc 32>; 271 resets = <&cpg 908>; 272 }; 273 274 gpio5: gpio@e6055000 { 275 compatible = "renesas,gpio-r8a77965", 276 "renesas,rcar-gen3-gpio"; 277 reg = <0 0xe6055000 0 0x50>; 278 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 279 #gpio-cells = <2>; 280 gpio-controller; 281 gpio-ranges = <&pfc 0 160 26>; 282 #interrupt-cells = <2>; 283 interrupt-controller; 284 clocks = <&cpg CPG_MOD 907>; 285 power-domains = <&sysc 32>; 286 resets = <&cpg 907>; 287 }; 288 289 gpio6: gpio@e6055400 { 290 compatible = "renesas,gpio-r8a77965", 291 "renesas,rcar-gen3-gpio"; 292 reg = <0 0xe6055400 0 0x50>; 293 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 294 #gpio-cells = <2>; 295 gpio-controller; 296 gpio-ranges = <&pfc 0 192 32>; 297 #interrupt-cells = <2>; 298 interrupt-controller; 299 clocks = <&cpg CPG_MOD 906>; 300 power-domains = <&sysc 32>; 301 resets = <&cpg 906>; 302 }; 303 304 gpio7: gpio@e6055800 { 305 compatible = "renesas,gpio-r8a77965", 306 "renesas,rcar-gen3-gpio"; 307 reg = <0 0xe6055800 0 0x50>; 308 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 309 #gpio-cells = <2>; 310 gpio-controller; 311 gpio-ranges = <&pfc 0 224 4>; 312 #interrupt-cells = <2>; 313 interrupt-controller; 314 clocks = <&cpg CPG_MOD 905>; 315 power-domains = <&sysc 32>; 316 resets = <&cpg 905>; 317 }; 318 319 intc_ex: interrupt-controller@e61c0000 { 320 reg = <0 0xe61c0000 0 0x200>; 321 /* placeholder */ 322 }; 323 324 dmac0: dma-controller@e6700000 { 325 compatible = "renesas,dmac-r8a77965", 326 "renesas,rcar-dmac"; 327 reg = <0 0xe6700000 0 0x10000>; 328 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 344 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-names = "error", 346 "ch0", "ch1", "ch2", "ch3", 347 "ch4", "ch5", "ch6", "ch7", 348 "ch8", "ch9", "ch10", "ch11", 349 "ch12", "ch13", "ch14", "ch15"; 350 clocks = <&cpg CPG_MOD 219>; 351 clock-names = "fck"; 352 power-domains = <&sysc 32>; 353 resets = <&cpg 219>; 354 #dma-cells = <1>; 355 dma-channels = <16>; 356 }; 357 358 dmac1: dma-controller@e7300000 { 359 compatible = "renesas,dmac-r8a77965", 360 "renesas,rcar-dmac"; 361 reg = <0 0xe7300000 0 0x10000>; 362 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 376 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 377 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 378 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 379 interrupt-names = "error", 380 "ch0", "ch1", "ch2", "ch3", 381 "ch4", "ch5", "ch6", "ch7", 382 "ch8", "ch9", "ch10", "ch11", 383 "ch12", "ch13", "ch14", "ch15"; 384 clocks = <&cpg CPG_MOD 218>; 385 clock-names = "fck"; 386 power-domains = <&sysc 32>; 387 resets = <&cpg 218>; 388 #dma-cells = <1>; 389 dma-channels = <16>; 390 }; 391 392 dmac2: dma-controller@e7310000 { 393 compatible = "renesas,dmac-r8a77965", 394 "renesas,rcar-dmac"; 395 reg = <0 0xe7310000 0 0x10000>; 396 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 397 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 399 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 400 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 401 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 402 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 403 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 404 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 405 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 406 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 407 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 408 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 409 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 410 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 411 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 412 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "error", 414 "ch0", "ch1", "ch2", "ch3", 415 "ch4", "ch5", "ch6", "ch7", 416 "ch8", "ch9", "ch10", "ch11", 417 "ch12", "ch13", "ch14", "ch15"; 418 clocks = <&cpg CPG_MOD 217>; 419 clock-names = "fck"; 420 power-domains = <&sysc 32>; 421 resets = <&cpg 217>; 422 #dma-cells = <1>; 423 dma-channels = <16>; 424 }; 425 426 scif0: serial@e6e60000 { 427 compatible = "renesas,scif-r8a77965", 428 "renesas,rcar-gen3-scif", "renesas,scif"; 429 reg = <0 0xe6e60000 0 64>; 430 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&cpg CPG_MOD 207>, 432 <&cpg CPG_CORE 20>, 433 <&scif_clk>; 434 clock-names = "fck", "brg_int", "scif_clk"; 435 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 436 <&dmac2 0x51>, <&dmac2 0x50>; 437 dma-names = "tx", "rx", "tx", "rx"; 438 power-domains = <&sysc 32>; 439 resets = <&cpg 207>; 440 status = "disabled"; 441 }; 442 443 scif1: serial@e6e68000 { 444 compatible = "renesas,scif-r8a77965", 445 "renesas,rcar-gen3-scif", "renesas,scif"; 446 reg = <0 0xe6e68000 0 64>; 447 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&cpg CPG_MOD 206>, 449 <&cpg CPG_CORE 20>, 450 <&scif_clk>; 451 clock-names = "fck", "brg_int", "scif_clk"; 452 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 453 <&dmac2 0x53>, <&dmac2 0x52>; 454 dma-names = "tx", "rx", "tx", "rx"; 455 power-domains = <&sysc 32>; 456 resets = <&cpg 206>; 457 status = "disabled"; 458 }; 459 460 scif2: serial@e6e88000 { 461 compatible = "renesas,scif-r8a77965", 462 "renesas,rcar-gen3-scif", "renesas,scif"; 463 reg = <0 0xe6e88000 0 64>; 464 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cpg CPG_MOD 310>, 466 <&cpg CPG_CORE 20>, 467 <&scif_clk>; 468 clock-names = "fck", "brg_int", "scif_clk"; 469 power-domains = <&sysc 32>; 470 resets = <&cpg 310>; 471 status = "disabled"; 472 }; 473 474 scif3: serial@e6c50000 { 475 compatible = "renesas,scif-r8a77965", 476 "renesas,rcar-gen3-scif", "renesas,scif"; 477 reg = <0 0xe6c50000 0 64>; 478 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cpg CPG_MOD 204>, 480 <&cpg CPG_CORE 20>, 481 <&scif_clk>; 482 clock-names = "fck", "brg_int", "scif_clk"; 483 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 484 dma-names = "tx", "rx"; 485 power-domains = <&sysc 32>; 486 resets = <&cpg 204>; 487 status = "disabled"; 488 }; 489 490 scif4: serial@e6c40000 { 491 compatible = "renesas,scif-r8a77965", 492 "renesas,rcar-gen3-scif", "renesas,scif"; 493 reg = <0 0xe6c40000 0 64>; 494 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&cpg CPG_MOD 203>, 496 <&cpg CPG_CORE 20>, 497 <&scif_clk>; 498 clock-names = "fck", "brg_int", "scif_clk"; 499 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 500 dma-names = "tx", "rx"; 501 power-domains = <&sysc 32>; 502 resets = <&cpg 203>; 503 status = "disabled"; 504 }; 505 506 scif5: serial@e6f30000 { 507 compatible = "renesas,scif-r8a77965", 508 "renesas,rcar-gen3-scif", "renesas,scif"; 509 reg = <0 0xe6f30000 0 64>; 510 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cpg CPG_MOD 202>, 512 <&cpg CPG_CORE 20>, 513 <&scif_clk>; 514 clock-names = "fck", "brg_int", "scif_clk"; 515 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 516 <&dmac2 0x5b>, <&dmac2 0x5a>; 517 dma-names = "tx", "rx", "tx", "rx"; 518 power-domains = <&sysc 32>; 519 resets = <&cpg 202>; 520 status = "disabled"; 521 }; 522 523 avb: ethernet@e6800000 { 524 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 525 /* placeholder */ 526 }; 527 528 csi20: csi2@fea80000 { 529 reg = <0 0xfea80000 0 0x10000>; 530 /* placeholder */ 531 }; 532 533 csi40: csi2@feaa0000 { 534 reg = <0 0xfeaa0000 0 0x10000>; 535 /* placeholder */ 536 }; 537 538 vin0: video@e6ef0000 { 539 reg = <0 0xe6ef0000 0 0x1000>; 540 /* placeholder */ 541 }; 542 543 vin1: video@e6ef1000 { 544 reg = <0 0xe6ef1000 0 0x1000>; 545 /* placeholder */ 546 }; 547 548 vin2: video@e6ef2000 { 549 reg = <0 0xe6ef2000 0 0x1000>; 550 /* placeholder */ 551 }; 552 553 vin3: video@e6ef3000 { 554 reg = <0 0xe6ef3000 0 0x1000>; 555 /* placeholder */ 556 }; 557 558 vin4: video@e6ef4000 { 559 reg = <0 0xe6ef4000 0 0x1000>; 560 /* placeholder */ 561 }; 562 563 vin5: video@e6ef5000 { 564 reg = <0 0xe6ef5000 0 0x1000>; 565 /* placeholder */ 566 }; 567 568 vin6: video@e6ef6000 { 569 reg = <0 0xe6ef6000 0 0x1000>; 570 /* placeholder */ 571 }; 572 573 vin7: video@e6ef7000 { 574 reg = <0 0xe6ef7000 0 0x1000>; 575 /* placeholder */ 576 }; 577 578 ohci0: usb@ee080000 { 579 reg = <0 0xee080000 0 0x100>; 580 /* placeholder */ 581 }; 582 583 ehci0: usb@ee080100 { 584 reg = <0 0xee080100 0 0x100>; 585 /* placeholder */ 586 }; 587 588 usb2_phy0: usb-phy@ee080200 { 589 reg = <0 0xee080200 0 0x700>; 590 /* placeholder */ 591 }; 592 593 ohci1: usb@ee0a0000 { 594 reg = <0 0xee0a0000 0 0x100>; 595 /* placeholder */ 596 }; 597 598 ehci1: usb@ee0a0100 { 599 reg = <0 0xee0a0100 0 0x100>; 600 /* placeholder */ 601 }; 602 603 i2c0: i2c@e6500000 { 604 reg = <0 0xe6500000 0 0x40>; 605 /* placeholder */ 606 }; 607 608 i2c1: i2c@e6508000 { 609 reg = <0 0xe6508000 0 0x40>; 610 /* placeholder */ 611 }; 612 613 i2c2: i2c@e6510000 { 614 reg = <0 0xe6510000 0 0x40>; 615 /* placeholder */ 616 }; 617 618 i2c3: i2c@e66d0000 { 619 reg = <0 0xe66d0000 0 0x40>; 620 /* placeholder */ 621 }; 622 623 i2c4: i2c@e66d8000 { 624 reg = <0 0xe66d8000 0 0x40>; 625 /* placeholder */ 626 }; 627 628 i2c5: i2c@e66e0000 { 629 reg = <0 0xe66e0000 0 0x40>; 630 /* placeholder */ 631 }; 632 633 i2c6: i2c@e66e8000 { 634 reg = <0 0xe66e8000 0 0x40>; 635 /* placeholder */ 636 }; 637 638 i2c_dvfs: i2c@e60b0000 { 639 reg = <0 0xe60b0000 0 0x425>; 640 /* placeholder */ 641 }; 642 643 pwm0: pwm@e6e30000 { 644 reg = <0 0xe6e30000 0 8>; 645 /* placeholder */ 646 }; 647 648 pwm1: pwm@e6e31000 { 649 reg = <0 0xe6e31000 0 8>; 650 /* placeholder */ 651 }; 652 653 pwm2: pwm@e6e32000 { 654 reg = <0 0xe6e32000 0 8>; 655 /* placeholder */ 656 }; 657 658 pwm3: pwm@e6e33000 { 659 reg = <0 0xe6e33000 0 8>; 660 /* placeholder */ 661 }; 662 663 pwm4: pwm@e6e34000 { 664 reg = <0 0xe6e34000 0 8>; 665 /* placeholder */ 666 }; 667 668 pwm5: pwm@e6e35000 { 669 reg = <0 0xe6e35000 0 8>; 670 /* placeholder */ 671 }; 672 673 pwm6: pwm@e6e36000 { 674 reg = <0 0xe6e36000 0 8>; 675 /* placeholder */ 676 }; 677 678 du: display@feb00000 { 679 reg = <0 0xfeb00000 0 0x80000>, 680 <0 0xfeb90000 0 0x14>; 681 /* placeholder */ 682 683 ports { 684 port@0 { 685 reg = <0>; 686 du_out_rgb: endpoint { 687 }; 688 }; 689 port@1 { 690 reg = <1>; 691 du_out_hdmi0: endpoint { 692 }; 693 }; 694 port@2 { 695 reg = <2>; 696 du_out_lvds0: endpoint { 697 }; 698 }; 699 }; 700 }; 701 702 hsusb: usb@e6590000 { 703 reg = <0 0xe6590000 0 0x100>; 704 /* placeholder */ 705 }; 706 707 pciec0: pcie@fe000000 { 708 reg = <0 0xfe000000 0 0x80000>; 709 /* placeholder */ 710 }; 711 712 pciec1: pcie@ee800000 { 713 reg = <0 0xee800000 0 0x80000>; 714 /* placeholder */ 715 }; 716 717 rcar_sound: sound@ec500000 { 718 reg = <0 0xec500000 0 0x1000>, /* SCU */ 719 <0 0xec5a0000 0 0x100>, /* ADG */ 720 <0 0xec540000 0 0x1000>, /* SSIU */ 721 <0 0xec541000 0 0x280>, /* SSI */ 722 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 723 /* placeholder */ 724 725 rcar_sound,dvc { 726 dvc0: dvc-0 { 727 }; 728 dvc1: dvc-1 { 729 }; 730 }; 731 732 rcar_sound,src { 733 src0: src-0 { 734 }; 735 src1: src-1 { 736 }; 737 }; 738 739 rcar_sound,ssi { 740 ssi0: ssi-0 { 741 }; 742 ssi1: ssi-1 { 743 }; 744 }; 745 }; 746 747 usb2_phy1: usb-phy@ee0a0200 { 748 reg = <0 0xee0a0200 0 0x700>; 749 /* placeholder */ 750 }; 751 752 sdhi0: sd@ee100000 { 753 reg = <0 0xee100000 0 0x2000>; 754 /* placeholder */ 755 }; 756 757 sdhi1: sd@ee120000 { 758 reg = <0 0xee120000 0 0x2000>; 759 /* placeholder */ 760 }; 761 762 sdhi2: sd@ee140000 { 763 reg = <0 0xee140000 0 0x2000>; 764 /* placeholder */ 765 }; 766 767 sdhi3: sd@ee160000 { 768 reg = <0 0xee160000 0 0x2000>; 769 /* placeholder */ 770 }; 771 772 usb3_phy0: usb-phy@e65ee000 { 773 reg = <0 0xe65ee000 0 0x90>; 774 /* placeholder */ 775 }; 776 777 usb3_peri0: usb@ee020000 { 778 reg = <0 0xee020000 0 0x400>; 779 /* placeholder */ 780 }; 781 782 xhci0: usb@ee000000 { 783 reg = <0 0xee000000 0 0xc00>; 784 /* placeholder */ 785 }; 786 787 wdt0: watchdog@e6020000 { 788 reg = <0 0xe6020000 0 0x0c>; 789 /* placeholder */ 790 }; 791 }; 792}; 793