1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <830000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <830000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <830000>; 66 clock-latency-ns = <300000>; 67 opp-suspend; 68 }; 69 opp-1600000000 { 70 opp-hz = /bits/ 64 <1600000000>; 71 opp-microvolt = <900000>; 72 clock-latency-ns = <300000>; 73 turbo-mode; 74 }; 75 opp-1700000000 { 76 opp-hz = /bits/ 64 <1700000000>; 77 opp-microvolt = <900000>; 78 clock-latency-ns = <300000>; 79 turbo-mode; 80 }; 81 opp-1800000000 { 82 opp-hz = /bits/ 64 <1800000000>; 83 opp-microvolt = <960000>; 84 clock-latency-ns = <300000>; 85 turbo-mode; 86 }; 87 }; 88 89 cluster1_opp: opp_table1 { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-800000000 { 94 opp-hz = /bits/ 64 <800000000>; 95 opp-microvolt = <820000>; 96 clock-latency-ns = <300000>; 97 }; 98 opp-1000000000 { 99 opp-hz = /bits/ 64 <1000000000>; 100 opp-microvolt = <820000>; 101 clock-latency-ns = <300000>; 102 }; 103 opp-1200000000 { 104 opp-hz = /bits/ 64 <1200000000>; 105 opp-microvolt = <820000>; 106 clock-latency-ns = <300000>; 107 }; 108 opp-1300000000 { 109 opp-hz = /bits/ 64 <1300000000>; 110 opp-microvolt = <820000>; 111 clock-latency-ns = <300000>; 112 turbo-mode; 113 }; 114 }; 115 116 cpus { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&a57_0>; 124 }; 125 core1 { 126 cpu = <&a57_1>; 127 }; 128 }; 129 130 cluster1 { 131 core0 { 132 cpu = <&a53_0>; 133 }; 134 core1 { 135 cpu = <&a53_1>; 136 }; 137 core2 { 138 cpu = <&a53_2>; 139 }; 140 core3 { 141 cpu = <&a53_3>; 142 }; 143 }; 144 }; 145 146 a57_0: cpu@0 { 147 compatible = "arm,cortex-a57"; 148 reg = <0x0>; 149 device_type = "cpu"; 150 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 151 next-level-cache = <&L2_CA57>; 152 enable-method = "psci"; 153 cpu-idle-states = <&CPU_SLEEP_0>; 154 dynamic-power-coefficient = <854>; 155 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 156 operating-points-v2 = <&cluster0_opp>; 157 capacity-dmips-mhz = <1024>; 158 #cooling-cells = <2>; 159 }; 160 161 a57_1: cpu@1 { 162 compatible = "arm,cortex-a57"; 163 reg = <0x1>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 166 next-level-cache = <&L2_CA57>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0>; 169 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 170 operating-points-v2 = <&cluster0_opp>; 171 capacity-dmips-mhz = <1024>; 172 #cooling-cells = <2>; 173 }; 174 175 a53_0: cpu@100 { 176 compatible = "arm,cortex-a53"; 177 reg = <0x100>; 178 device_type = "cpu"; 179 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 180 next-level-cache = <&L2_CA53>; 181 enable-method = "psci"; 182 cpu-idle-states = <&CPU_SLEEP_1>; 183 #cooling-cells = <2>; 184 dynamic-power-coefficient = <277>; 185 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 186 operating-points-v2 = <&cluster1_opp>; 187 capacity-dmips-mhz = <535>; 188 }; 189 190 a53_1: cpu@101 { 191 compatible = "arm,cortex-a53"; 192 reg = <0x101>; 193 device_type = "cpu"; 194 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 195 next-level-cache = <&L2_CA53>; 196 enable-method = "psci"; 197 cpu-idle-states = <&CPU_SLEEP_1>; 198 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 199 operating-points-v2 = <&cluster1_opp>; 200 capacity-dmips-mhz = <535>; 201 }; 202 203 a53_2: cpu@102 { 204 compatible = "arm,cortex-a53"; 205 reg = <0x102>; 206 device_type = "cpu"; 207 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 208 next-level-cache = <&L2_CA53>; 209 enable-method = "psci"; 210 cpu-idle-states = <&CPU_SLEEP_1>; 211 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 212 operating-points-v2 = <&cluster1_opp>; 213 capacity-dmips-mhz = <535>; 214 }; 215 216 a53_3: cpu@103 { 217 compatible = "arm,cortex-a53"; 218 reg = <0x103>; 219 device_type = "cpu"; 220 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 221 next-level-cache = <&L2_CA53>; 222 enable-method = "psci"; 223 cpu-idle-states = <&CPU_SLEEP_1>; 224 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 225 operating-points-v2 = <&cluster1_opp>; 226 capacity-dmips-mhz = <535>; 227 }; 228 229 L2_CA57: cache-controller-0 { 230 compatible = "cache"; 231 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 232 cache-unified; 233 cache-level = <2>; 234 }; 235 236 L2_CA53: cache-controller-1 { 237 compatible = "cache"; 238 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 239 cache-unified; 240 cache-level = <2>; 241 }; 242 243 idle-states { 244 entry-method = "psci"; 245 246 CPU_SLEEP_0: cpu-sleep-0 { 247 compatible = "arm,idle-state"; 248 arm,psci-suspend-param = <0x0010000>; 249 local-timer-stop; 250 entry-latency-us = <400>; 251 exit-latency-us = <500>; 252 min-residency-us = <4000>; 253 }; 254 255 CPU_SLEEP_1: cpu-sleep-1 { 256 compatible = "arm,idle-state"; 257 arm,psci-suspend-param = <0x0010000>; 258 local-timer-stop; 259 entry-latency-us = <700>; 260 exit-latency-us = <700>; 261 min-residency-us = <5000>; 262 }; 263 }; 264 }; 265 266 extal_clk: extal { 267 compatible = "fixed-clock"; 268 #clock-cells = <0>; 269 /* This value must be overridden by the board */ 270 clock-frequency = <0>; 271 }; 272 273 extalr_clk: extalr { 274 compatible = "fixed-clock"; 275 #clock-cells = <0>; 276 /* This value must be overridden by the board */ 277 clock-frequency = <0>; 278 }; 279 280 /* External PCIe clock - can be overridden by the board */ 281 pcie_bus_clk: pcie_bus { 282 compatible = "fixed-clock"; 283 #clock-cells = <0>; 284 clock-frequency = <0>; 285 }; 286 287 pmu_a53 { 288 compatible = "arm,cortex-a53-pmu"; 289 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 292 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 294 }; 295 296 pmu_a57 { 297 compatible = "arm,cortex-a57-pmu"; 298 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 299 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-affinity = <&a57_0>, <&a57_1>; 301 }; 302 303 psci { 304 compatible = "arm,psci-1.0", "arm,psci-0.2"; 305 method = "smc"; 306 }; 307 308 /* External SCIF clock - to be overridden by boards that provide it */ 309 scif_clk: scif { 310 compatible = "fixed-clock"; 311 #clock-cells = <0>; 312 clock-frequency = <0>; 313 }; 314 315 soc { 316 compatible = "simple-bus"; 317 interrupt-parent = <&gic>; 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 322 rwdt: watchdog@e6020000 { 323 compatible = "renesas,r8a77961-wdt", 324 "renesas,rcar-gen3-wdt"; 325 reg = <0 0xe6020000 0 0x0c>; 326 clocks = <&cpg CPG_MOD 402>; 327 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 328 resets = <&cpg 402>; 329 status = "disabled"; 330 }; 331 332 gpio0: gpio@e6050000 { 333 compatible = "renesas,gpio-r8a77961", 334 "renesas,rcar-gen3-gpio"; 335 reg = <0 0xe6050000 0 0x50>; 336 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 337 #gpio-cells = <2>; 338 gpio-controller; 339 gpio-ranges = <&pfc 0 0 16>; 340 #interrupt-cells = <2>; 341 interrupt-controller; 342 clocks = <&cpg CPG_MOD 912>; 343 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 344 resets = <&cpg 912>; 345 }; 346 347 gpio1: gpio@e6051000 { 348 compatible = "renesas,gpio-r8a77961", 349 "renesas,rcar-gen3-gpio"; 350 reg = <0 0xe6051000 0 0x50>; 351 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 352 #gpio-cells = <2>; 353 gpio-controller; 354 gpio-ranges = <&pfc 0 32 29>; 355 #interrupt-cells = <2>; 356 interrupt-controller; 357 clocks = <&cpg CPG_MOD 911>; 358 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 359 resets = <&cpg 911>; 360 }; 361 362 gpio2: gpio@e6052000 { 363 compatible = "renesas,gpio-r8a77961", 364 "renesas,rcar-gen3-gpio"; 365 reg = <0 0xe6052000 0 0x50>; 366 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 367 #gpio-cells = <2>; 368 gpio-controller; 369 gpio-ranges = <&pfc 0 64 15>; 370 #interrupt-cells = <2>; 371 interrupt-controller; 372 clocks = <&cpg CPG_MOD 910>; 373 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 374 resets = <&cpg 910>; 375 }; 376 377 gpio3: gpio@e6053000 { 378 compatible = "renesas,gpio-r8a77961", 379 "renesas,rcar-gen3-gpio"; 380 reg = <0 0xe6053000 0 0x50>; 381 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 382 #gpio-cells = <2>; 383 gpio-controller; 384 gpio-ranges = <&pfc 0 96 16>; 385 #interrupt-cells = <2>; 386 interrupt-controller; 387 clocks = <&cpg CPG_MOD 909>; 388 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 389 resets = <&cpg 909>; 390 }; 391 392 gpio4: gpio@e6054000 { 393 compatible = "renesas,gpio-r8a77961", 394 "renesas,rcar-gen3-gpio"; 395 reg = <0 0xe6054000 0 0x50>; 396 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 397 #gpio-cells = <2>; 398 gpio-controller; 399 gpio-ranges = <&pfc 0 128 18>; 400 #interrupt-cells = <2>; 401 interrupt-controller; 402 clocks = <&cpg CPG_MOD 908>; 403 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 404 resets = <&cpg 908>; 405 }; 406 407 gpio5: gpio@e6055000 { 408 compatible = "renesas,gpio-r8a77961", 409 "renesas,rcar-gen3-gpio"; 410 reg = <0 0xe6055000 0 0x50>; 411 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 412 #gpio-cells = <2>; 413 gpio-controller; 414 gpio-ranges = <&pfc 0 160 26>; 415 #interrupt-cells = <2>; 416 interrupt-controller; 417 clocks = <&cpg CPG_MOD 907>; 418 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 419 resets = <&cpg 907>; 420 }; 421 422 gpio6: gpio@e6055400 { 423 compatible = "renesas,gpio-r8a77961", 424 "renesas,rcar-gen3-gpio"; 425 reg = <0 0xe6055400 0 0x50>; 426 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 427 #gpio-cells = <2>; 428 gpio-controller; 429 gpio-ranges = <&pfc 0 192 32>; 430 #interrupt-cells = <2>; 431 interrupt-controller; 432 clocks = <&cpg CPG_MOD 906>; 433 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 434 resets = <&cpg 906>; 435 }; 436 437 gpio7: gpio@e6055800 { 438 compatible = "renesas,gpio-r8a77961", 439 "renesas,rcar-gen3-gpio"; 440 reg = <0 0xe6055800 0 0x50>; 441 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 442 #gpio-cells = <2>; 443 gpio-controller; 444 gpio-ranges = <&pfc 0 224 4>; 445 #interrupt-cells = <2>; 446 interrupt-controller; 447 clocks = <&cpg CPG_MOD 905>; 448 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 449 resets = <&cpg 905>; 450 }; 451 452 pfc: pinctrl@e6060000 { 453 compatible = "renesas,pfc-r8a77961"; 454 reg = <0 0xe6060000 0 0x50c>; 455 }; 456 457 cmt0: timer@e60f0000 { 458 compatible = "renesas,r8a77961-cmt0", 459 "renesas,rcar-gen3-cmt0"; 460 reg = <0 0xe60f0000 0 0x1004>; 461 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&cpg CPG_MOD 303>; 464 clock-names = "fck"; 465 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 466 resets = <&cpg 303>; 467 status = "disabled"; 468 }; 469 470 cmt1: timer@e6130000 { 471 compatible = "renesas,r8a77961-cmt1", 472 "renesas,rcar-gen3-cmt1"; 473 reg = <0 0xe6130000 0 0x1004>; 474 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cpg CPG_MOD 302>; 483 clock-names = "fck"; 484 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 485 resets = <&cpg 302>; 486 status = "disabled"; 487 }; 488 489 cmt2: timer@e6140000 { 490 compatible = "renesas,r8a77961-cmt1", 491 "renesas,rcar-gen3-cmt1"; 492 reg = <0 0xe6140000 0 0x1004>; 493 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&cpg CPG_MOD 301>; 502 clock-names = "fck"; 503 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 504 resets = <&cpg 301>; 505 status = "disabled"; 506 }; 507 508 cmt3: timer@e6148000 { 509 compatible = "renesas,r8a77961-cmt1", 510 "renesas,rcar-gen3-cmt1"; 511 reg = <0 0xe6148000 0 0x1004>; 512 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&cpg CPG_MOD 300>; 521 clock-names = "fck"; 522 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 523 resets = <&cpg 300>; 524 status = "disabled"; 525 }; 526 527 cpg: clock-controller@e6150000 { 528 compatible = "renesas,r8a77961-cpg-mssr"; 529 reg = <0 0xe6150000 0 0x1000>; 530 clocks = <&extal_clk>, <&extalr_clk>; 531 clock-names = "extal", "extalr"; 532 #clock-cells = <2>; 533 #power-domain-cells = <0>; 534 #reset-cells = <1>; 535 }; 536 537 rst: reset-controller@e6160000 { 538 compatible = "renesas,r8a77961-rst"; 539 reg = <0 0xe6160000 0 0x0200>; 540 }; 541 542 sysc: system-controller@e6180000 { 543 compatible = "renesas,r8a77961-sysc"; 544 reg = <0 0xe6180000 0 0x0400>; 545 #power-domain-cells = <1>; 546 }; 547 548 tsc: thermal@e6198000 { 549 compatible = "renesas,r8a77961-thermal"; 550 reg = <0 0xe6198000 0 0x100>, 551 <0 0xe61a0000 0 0x100>, 552 <0 0xe61a8000 0 0x100>; 553 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 522>; 557 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 558 resets = <&cpg 522>; 559 #thermal-sensor-cells = <1>; 560 }; 561 562 intc_ex: interrupt-controller@e61c0000 { 563 compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; 564 #interrupt-cells = <2>; 565 interrupt-controller; 566 reg = <0 0xe61c0000 0 0x200>; 567 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD 407>; 574 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 575 resets = <&cpg 407>; 576 }; 577 578 tmu0: timer@e61e0000 { 579 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 580 reg = <0 0xe61e0000 0 0x30>; 581 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cpg CPG_MOD 125>; 585 clock-names = "fck"; 586 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 587 resets = <&cpg 125>; 588 status = "disabled"; 589 }; 590 591 tmu1: timer@e6fc0000 { 592 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 593 reg = <0 0xe6fc0000 0 0x30>; 594 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 124>; 598 clock-names = "fck"; 599 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 600 resets = <&cpg 124>; 601 status = "disabled"; 602 }; 603 604 tmu2: timer@e6fd0000 { 605 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 606 reg = <0 0xe6fd0000 0 0x30>; 607 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&cpg CPG_MOD 123>; 611 clock-names = "fck"; 612 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 613 resets = <&cpg 123>; 614 status = "disabled"; 615 }; 616 617 tmu3: timer@e6fe0000 { 618 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 619 reg = <0 0xe6fe0000 0 0x30>; 620 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cpg CPG_MOD 122>; 624 clock-names = "fck"; 625 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 626 resets = <&cpg 122>; 627 status = "disabled"; 628 }; 629 630 tmu4: timer@ffc00000 { 631 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 632 reg = <0 0xffc00000 0 0x30>; 633 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&cpg CPG_MOD 121>; 637 clock-names = "fck"; 638 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 639 resets = <&cpg 121>; 640 status = "disabled"; 641 }; 642 643 i2c0: i2c@e6500000 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 compatible = "renesas,i2c-r8a77961", 647 "renesas,rcar-gen3-i2c"; 648 reg = <0 0xe6500000 0 0x40>; 649 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 931>; 651 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 652 resets = <&cpg 931>; 653 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 654 <&dmac2 0x91>, <&dmac2 0x90>; 655 dma-names = "tx", "rx", "tx", "rx"; 656 i2c-scl-internal-delay-ns = <110>; 657 status = "disabled"; 658 }; 659 660 i2c1: i2c@e6508000 { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 compatible = "renesas,i2c-r8a77961", 664 "renesas,rcar-gen3-i2c"; 665 reg = <0 0xe6508000 0 0x40>; 666 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD 930>; 668 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 669 resets = <&cpg 930>; 670 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 671 <&dmac2 0x93>, <&dmac2 0x92>; 672 dma-names = "tx", "rx", "tx", "rx"; 673 i2c-scl-internal-delay-ns = <6>; 674 status = "disabled"; 675 }; 676 677 i2c2: i2c@e6510000 { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 compatible = "renesas,i2c-r8a77961", 681 "renesas,rcar-gen3-i2c"; 682 reg = <0 0xe6510000 0 0x40>; 683 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 929>; 685 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 686 resets = <&cpg 929>; 687 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 688 <&dmac2 0x95>, <&dmac2 0x94>; 689 dma-names = "tx", "rx", "tx", "rx"; 690 i2c-scl-internal-delay-ns = <6>; 691 status = "disabled"; 692 }; 693 694 i2c3: i2c@e66d0000 { 695 #address-cells = <1>; 696 #size-cells = <0>; 697 compatible = "renesas,i2c-r8a77961", 698 "renesas,rcar-gen3-i2c"; 699 reg = <0 0xe66d0000 0 0x40>; 700 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 928>; 702 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 703 resets = <&cpg 928>; 704 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 705 dma-names = "tx", "rx"; 706 i2c-scl-internal-delay-ns = <110>; 707 status = "disabled"; 708 }; 709 710 i2c4: i2c@e66d8000 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 compatible = "renesas,i2c-r8a77961", 714 "renesas,rcar-gen3-i2c"; 715 reg = <0 0xe66d8000 0 0x40>; 716 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cpg CPG_MOD 927>; 718 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 719 resets = <&cpg 927>; 720 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 721 dma-names = "tx", "rx"; 722 i2c-scl-internal-delay-ns = <110>; 723 status = "disabled"; 724 }; 725 726 i2c5: i2c@e66e0000 { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 compatible = "renesas,i2c-r8a77961", 730 "renesas,rcar-gen3-i2c"; 731 reg = <0 0xe66e0000 0 0x40>; 732 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cpg CPG_MOD 919>; 734 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 735 resets = <&cpg 919>; 736 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 737 dma-names = "tx", "rx"; 738 i2c-scl-internal-delay-ns = <110>; 739 status = "disabled"; 740 }; 741 742 i2c6: i2c@e66e8000 { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 compatible = "renesas,i2c-r8a77961", 746 "renesas,rcar-gen3-i2c"; 747 reg = <0 0xe66e8000 0 0x40>; 748 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cpg CPG_MOD 918>; 750 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 751 resets = <&cpg 918>; 752 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 753 dma-names = "tx", "rx"; 754 i2c-scl-internal-delay-ns = <6>; 755 status = "disabled"; 756 }; 757 758 i2c_dvfs: i2c@e60b0000 { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 compatible = "renesas,iic-r8a77961", 762 "renesas,rcar-gen3-iic", 763 "renesas,rmobile-iic"; 764 reg = <0 0xe60b0000 0 0x425>; 765 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cpg CPG_MOD 926>; 767 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 768 resets = <&cpg 926>; 769 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 770 dma-names = "tx", "rx"; 771 status = "disabled"; 772 }; 773 774 hscif0: serial@e6540000 { 775 compatible = "renesas,hscif-r8a77961", 776 "renesas,rcar-gen3-hscif", 777 "renesas,hscif"; 778 reg = <0 0xe6540000 0 0x60>; 779 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&cpg CPG_MOD 520>, 781 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 782 <&scif_clk>; 783 clock-names = "fck", "brg_int", "scif_clk"; 784 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 785 <&dmac2 0x31>, <&dmac2 0x30>; 786 dma-names = "tx", "rx", "tx", "rx"; 787 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 788 resets = <&cpg 520>; 789 status = "disabled"; 790 }; 791 792 hscif1: serial@e6550000 { 793 compatible = "renesas,hscif-r8a77961", 794 "renesas,rcar-gen3-hscif", 795 "renesas,hscif"; 796 reg = <0 0xe6550000 0 0x60>; 797 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&cpg CPG_MOD 519>, 799 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 800 <&scif_clk>; 801 clock-names = "fck", "brg_int", "scif_clk"; 802 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 803 <&dmac2 0x33>, <&dmac2 0x32>; 804 dma-names = "tx", "rx", "tx", "rx"; 805 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 806 resets = <&cpg 519>; 807 status = "disabled"; 808 }; 809 810 hscif2: serial@e6560000 { 811 compatible = "renesas,hscif-r8a77961", 812 "renesas,rcar-gen3-hscif", 813 "renesas,hscif"; 814 reg = <0 0xe6560000 0 0x60>; 815 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&cpg CPG_MOD 518>, 817 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 818 <&scif_clk>; 819 clock-names = "fck", "brg_int", "scif_clk"; 820 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 821 <&dmac2 0x35>, <&dmac2 0x34>; 822 dma-names = "tx", "rx", "tx", "rx"; 823 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 824 resets = <&cpg 518>; 825 status = "disabled"; 826 }; 827 828 hscif3: serial@e66a0000 { 829 compatible = "renesas,hscif-r8a77961", 830 "renesas,rcar-gen3-hscif", 831 "renesas,hscif"; 832 reg = <0 0xe66a0000 0 0x60>; 833 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&cpg CPG_MOD 517>, 835 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 836 <&scif_clk>; 837 clock-names = "fck", "brg_int", "scif_clk"; 838 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 839 dma-names = "tx", "rx"; 840 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 841 resets = <&cpg 517>; 842 status = "disabled"; 843 }; 844 845 hscif4: serial@e66b0000 { 846 compatible = "renesas,hscif-r8a77961", 847 "renesas,rcar-gen3-hscif", 848 "renesas,hscif"; 849 reg = <0 0xe66b0000 0 0x60>; 850 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cpg CPG_MOD 516>, 852 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 853 <&scif_clk>; 854 clock-names = "fck", "brg_int", "scif_clk"; 855 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 856 dma-names = "tx", "rx"; 857 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 858 resets = <&cpg 516>; 859 status = "disabled"; 860 }; 861 862 hsusb: usb@e6590000 { 863 compatible = "renesas,usbhs-r8a77961", 864 "renesas,rcar-gen3-usbhs"; 865 reg = <0 0xe6590000 0 0x200>; 866 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 868 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 869 <&usb_dmac1 0>, <&usb_dmac1 1>; 870 dma-names = "ch0", "ch1", "ch2", "ch3"; 871 renesas,buswait = <11>; 872 phys = <&usb2_phy0 3>; 873 phy-names = "usb"; 874 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 875 resets = <&cpg 704>, <&cpg 703>; 876 status = "disabled"; 877 }; 878 879 usb_dmac0: dma-controller@e65a0000 { 880 compatible = "renesas,r8a77961-usb-dmac", 881 "renesas,usb-dmac"; 882 reg = <0 0xe65a0000 0 0x100>; 883 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "ch0", "ch1"; 886 clocks = <&cpg CPG_MOD 330>; 887 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 888 resets = <&cpg 330>; 889 #dma-cells = <1>; 890 dma-channels = <2>; 891 }; 892 893 usb_dmac1: dma-controller@e65b0000 { 894 compatible = "renesas,r8a77961-usb-dmac", 895 "renesas,usb-dmac"; 896 reg = <0 0xe65b0000 0 0x100>; 897 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "ch0", "ch1"; 900 clocks = <&cpg CPG_MOD 331>; 901 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 902 resets = <&cpg 331>; 903 #dma-cells = <1>; 904 dma-channels = <2>; 905 }; 906 907 usb3_phy0: usb-phy@e65ee000 { 908 compatible = "renesas,r8a77961-usb3-phy", 909 "renesas,rcar-gen3-usb3-phy"; 910 reg = <0 0xe65ee000 0 0x90>; 911 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 912 <&usb_extal_clk>; 913 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 914 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 915 resets = <&cpg 328>; 916 #phy-cells = <0>; 917 status = "disabled"; 918 }; 919 920 arm_cc630p: crypto@e6601000 { 921 compatible = "arm,cryptocell-630p-ree"; 922 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 923 reg = <0x0 0xe6601000 0 0x1000>; 924 clocks = <&cpg CPG_MOD 229>; 925 resets = <&cpg 229>; 926 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 927 }; 928 929 dmac0: dma-controller@e6700000 { 930 compatible = "renesas,dmac-r8a77961", 931 "renesas,rcar-dmac"; 932 reg = <0 0xe6700000 0 0x10000>; 933 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "error", 951 "ch0", "ch1", "ch2", "ch3", 952 "ch4", "ch5", "ch6", "ch7", 953 "ch8", "ch9", "ch10", "ch11", 954 "ch12", "ch13", "ch14", "ch15"; 955 clocks = <&cpg CPG_MOD 219>; 956 clock-names = "fck"; 957 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 958 resets = <&cpg 219>; 959 #dma-cells = <1>; 960 dma-channels = <16>; 961 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 962 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 963 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 964 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 965 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 966 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 967 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 968 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 969 }; 970 971 dmac1: dma-controller@e7300000 { 972 compatible = "renesas,dmac-r8a77961", 973 "renesas,rcar-dmac"; 974 reg = <0 0xe7300000 0 0x10000>; 975 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 992 interrupt-names = "error", 993 "ch0", "ch1", "ch2", "ch3", 994 "ch4", "ch5", "ch6", "ch7", 995 "ch8", "ch9", "ch10", "ch11", 996 "ch12", "ch13", "ch14", "ch15"; 997 clocks = <&cpg CPG_MOD 218>; 998 clock-names = "fck"; 999 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1000 resets = <&cpg 218>; 1001 #dma-cells = <1>; 1002 dma-channels = <16>; 1003 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1004 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1005 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1006 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1007 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1008 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1009 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1010 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1011 }; 1012 1013 dmac2: dma-controller@e7310000 { 1014 compatible = "renesas,dmac-r8a77961", 1015 "renesas,rcar-dmac"; 1016 reg = <0 0xe7310000 0 0x10000>; 1017 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1034 interrupt-names = "error", 1035 "ch0", "ch1", "ch2", "ch3", 1036 "ch4", "ch5", "ch6", "ch7", 1037 "ch8", "ch9", "ch10", "ch11", 1038 "ch12", "ch13", "ch14", "ch15"; 1039 clocks = <&cpg CPG_MOD 217>; 1040 clock-names = "fck"; 1041 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1042 resets = <&cpg 217>; 1043 #dma-cells = <1>; 1044 dma-channels = <16>; 1045 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1046 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1047 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1048 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1049 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1050 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1051 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1052 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1053 }; 1054 1055 ipmmu_ds0: iommu@e6740000 { 1056 compatible = "renesas,ipmmu-r8a77961"; 1057 reg = <0 0xe6740000 0 0x1000>; 1058 renesas,ipmmu-main = <&ipmmu_mm 0>; 1059 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1060 #iommu-cells = <1>; 1061 }; 1062 1063 ipmmu_ds1: iommu@e7740000 { 1064 compatible = "renesas,ipmmu-r8a77961"; 1065 reg = <0 0xe7740000 0 0x1000>; 1066 renesas,ipmmu-main = <&ipmmu_mm 1>; 1067 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1068 #iommu-cells = <1>; 1069 }; 1070 1071 ipmmu_hc: iommu@e6570000 { 1072 compatible = "renesas,ipmmu-r8a77961"; 1073 reg = <0 0xe6570000 0 0x1000>; 1074 renesas,ipmmu-main = <&ipmmu_mm 2>; 1075 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1076 #iommu-cells = <1>; 1077 }; 1078 1079 ipmmu_ir: iommu@ff8b0000 { 1080 compatible = "renesas,ipmmu-r8a77961"; 1081 reg = <0 0xff8b0000 0 0x1000>; 1082 renesas,ipmmu-main = <&ipmmu_mm 3>; 1083 power-domains = <&sysc R8A77961_PD_A3IR>; 1084 #iommu-cells = <1>; 1085 }; 1086 1087 ipmmu_mm: iommu@e67b0000 { 1088 compatible = "renesas,ipmmu-r8a77961"; 1089 reg = <0 0xe67b0000 0 0x1000>; 1090 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1092 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1093 #iommu-cells = <1>; 1094 }; 1095 1096 ipmmu_mp: iommu@ec670000 { 1097 compatible = "renesas,ipmmu-r8a77961"; 1098 reg = <0 0xec670000 0 0x1000>; 1099 renesas,ipmmu-main = <&ipmmu_mm 4>; 1100 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1101 #iommu-cells = <1>; 1102 }; 1103 1104 ipmmu_pv0: iommu@fd800000 { 1105 compatible = "renesas,ipmmu-r8a77961"; 1106 reg = <0 0xfd800000 0 0x1000>; 1107 renesas,ipmmu-main = <&ipmmu_mm 5>; 1108 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1109 #iommu-cells = <1>; 1110 }; 1111 1112 ipmmu_pv1: iommu@fd950000 { 1113 compatible = "renesas,ipmmu-r8a77961"; 1114 reg = <0 0xfd950000 0 0x1000>; 1115 renesas,ipmmu-main = <&ipmmu_mm 6>; 1116 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1117 #iommu-cells = <1>; 1118 }; 1119 1120 ipmmu_rt: iommu@ffc80000 { 1121 compatible = "renesas,ipmmu-r8a77961"; 1122 reg = <0 0xffc80000 0 0x1000>; 1123 renesas,ipmmu-main = <&ipmmu_mm 7>; 1124 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1125 #iommu-cells = <1>; 1126 }; 1127 1128 ipmmu_vc0: iommu@fe6b0000 { 1129 compatible = "renesas,ipmmu-r8a77961"; 1130 reg = <0 0xfe6b0000 0 0x1000>; 1131 renesas,ipmmu-main = <&ipmmu_mm 8>; 1132 power-domains = <&sysc R8A77961_PD_A3VC>; 1133 #iommu-cells = <1>; 1134 }; 1135 1136 ipmmu_vi0: iommu@febd0000 { 1137 compatible = "renesas,ipmmu-r8a77961"; 1138 reg = <0 0xfebd0000 0 0x1000>; 1139 renesas,ipmmu-main = <&ipmmu_mm 9>; 1140 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1141 #iommu-cells = <1>; 1142 }; 1143 1144 avb: ethernet@e6800000 { 1145 compatible = "renesas,etheravb-r8a77961", 1146 "renesas,etheravb-rcar-gen3"; 1147 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1148 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1173 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1174 "ch4", "ch5", "ch6", "ch7", 1175 "ch8", "ch9", "ch10", "ch11", 1176 "ch12", "ch13", "ch14", "ch15", 1177 "ch16", "ch17", "ch18", "ch19", 1178 "ch20", "ch21", "ch22", "ch23", 1179 "ch24"; 1180 clocks = <&cpg CPG_MOD 812>; 1181 clock-names = "fck"; 1182 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1183 resets = <&cpg 812>; 1184 phy-mode = "rgmii"; 1185 rx-internal-delay-ps = <0>; 1186 tx-internal-delay-ps = <0>; 1187 iommus = <&ipmmu_ds0 16>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 can0: can@e6c30000 { 1194 compatible = "renesas,can-r8a77961", 1195 "renesas,rcar-gen3-can"; 1196 reg = <0 0xe6c30000 0 0x1000>; 1197 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cpg CPG_MOD 916>, 1199 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1200 <&can_clk>; 1201 clock-names = "clkp1", "clkp2", "can_clk"; 1202 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1203 assigned-clock-rates = <40000000>; 1204 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1205 resets = <&cpg 916>; 1206 status = "disabled"; 1207 }; 1208 1209 can1: can@e6c38000 { 1210 compatible = "renesas,can-r8a77961", 1211 "renesas,rcar-gen3-can"; 1212 reg = <0 0xe6c38000 0 0x1000>; 1213 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1214 clocks = <&cpg CPG_MOD 915>, 1215 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1216 <&can_clk>; 1217 clock-names = "clkp1", "clkp2", "can_clk"; 1218 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1219 assigned-clock-rates = <40000000>; 1220 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1221 resets = <&cpg 915>; 1222 status = "disabled"; 1223 }; 1224 1225 pwm0: pwm@e6e30000 { 1226 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1227 reg = <0 0xe6e30000 0 8>; 1228 #pwm-cells = <2>; 1229 clocks = <&cpg CPG_MOD 523>; 1230 resets = <&cpg 523>; 1231 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1232 status = "disabled"; 1233 }; 1234 1235 pwm1: pwm@e6e31000 { 1236 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1237 reg = <0 0xe6e31000 0 8>; 1238 #pwm-cells = <2>; 1239 clocks = <&cpg CPG_MOD 523>; 1240 resets = <&cpg 523>; 1241 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1242 status = "disabled"; 1243 }; 1244 1245 pwm2: pwm@e6e32000 { 1246 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1247 reg = <0 0xe6e32000 0 8>; 1248 #pwm-cells = <2>; 1249 clocks = <&cpg CPG_MOD 523>; 1250 resets = <&cpg 523>; 1251 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1252 status = "disabled"; 1253 }; 1254 1255 pwm3: pwm@e6e33000 { 1256 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1257 reg = <0 0xe6e33000 0 8>; 1258 #pwm-cells = <2>; 1259 clocks = <&cpg CPG_MOD 523>; 1260 resets = <&cpg 523>; 1261 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1262 status = "disabled"; 1263 }; 1264 1265 pwm4: pwm@e6e34000 { 1266 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1267 reg = <0 0xe6e34000 0 8>; 1268 #pwm-cells = <2>; 1269 clocks = <&cpg CPG_MOD 523>; 1270 resets = <&cpg 523>; 1271 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1272 status = "disabled"; 1273 }; 1274 1275 pwm5: pwm@e6e35000 { 1276 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1277 reg = <0 0xe6e35000 0 8>; 1278 #pwm-cells = <2>; 1279 clocks = <&cpg CPG_MOD 523>; 1280 resets = <&cpg 523>; 1281 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1282 status = "disabled"; 1283 }; 1284 1285 pwm6: pwm@e6e36000 { 1286 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1287 reg = <0 0xe6e36000 0 8>; 1288 #pwm-cells = <2>; 1289 clocks = <&cpg CPG_MOD 523>; 1290 resets = <&cpg 523>; 1291 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1292 status = "disabled"; 1293 }; 1294 1295 scif0: serial@e6e60000 { 1296 compatible = "renesas,scif-r8a77961", 1297 "renesas,rcar-gen3-scif", "renesas,scif"; 1298 reg = <0 0xe6e60000 0 64>; 1299 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&cpg CPG_MOD 207>, 1301 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1302 <&scif_clk>; 1303 clock-names = "fck", "brg_int", "scif_clk"; 1304 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1305 <&dmac2 0x51>, <&dmac2 0x50>; 1306 dma-names = "tx", "rx", "tx", "rx"; 1307 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1308 resets = <&cpg 207>; 1309 status = "disabled"; 1310 }; 1311 1312 scif1: serial@e6e68000 { 1313 compatible = "renesas,scif-r8a77961", 1314 "renesas,rcar-gen3-scif", "renesas,scif"; 1315 reg = <0 0xe6e68000 0 64>; 1316 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&cpg CPG_MOD 206>, 1318 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1319 <&scif_clk>; 1320 clock-names = "fck", "brg_int", "scif_clk"; 1321 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1322 <&dmac2 0x53>, <&dmac2 0x52>; 1323 dma-names = "tx", "rx", "tx", "rx"; 1324 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1325 resets = <&cpg 206>; 1326 status = "disabled"; 1327 }; 1328 1329 scif2: serial@e6e88000 { 1330 compatible = "renesas,scif-r8a77961", 1331 "renesas,rcar-gen3-scif", "renesas,scif"; 1332 reg = <0 0xe6e88000 0 64>; 1333 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1334 clocks = <&cpg CPG_MOD 310>, 1335 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1336 <&scif_clk>; 1337 clock-names = "fck", "brg_int", "scif_clk"; 1338 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1339 <&dmac2 0x13>, <&dmac2 0x12>; 1340 dma-names = "tx", "rx", "tx", "rx"; 1341 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1342 resets = <&cpg 310>; 1343 status = "disabled"; 1344 }; 1345 1346 scif3: serial@e6c50000 { 1347 compatible = "renesas,scif-r8a77961", 1348 "renesas,rcar-gen3-scif", "renesas,scif"; 1349 reg = <0 0xe6c50000 0 64>; 1350 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&cpg CPG_MOD 204>, 1352 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1353 <&scif_clk>; 1354 clock-names = "fck", "brg_int", "scif_clk"; 1355 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1356 dma-names = "tx", "rx"; 1357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1358 resets = <&cpg 204>; 1359 status = "disabled"; 1360 }; 1361 1362 scif4: serial@e6c40000 { 1363 compatible = "renesas,scif-r8a77961", 1364 "renesas,rcar-gen3-scif", "renesas,scif"; 1365 reg = <0 0xe6c40000 0 64>; 1366 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1367 clocks = <&cpg CPG_MOD 203>, 1368 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1369 <&scif_clk>; 1370 clock-names = "fck", "brg_int", "scif_clk"; 1371 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1372 dma-names = "tx", "rx"; 1373 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1374 resets = <&cpg 203>; 1375 status = "disabled"; 1376 }; 1377 1378 scif5: serial@e6f30000 { 1379 compatible = "renesas,scif-r8a77961", 1380 "renesas,rcar-gen3-scif", "renesas,scif"; 1381 reg = <0 0xe6f30000 0 64>; 1382 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&cpg CPG_MOD 202>, 1384 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1385 <&scif_clk>; 1386 clock-names = "fck", "brg_int", "scif_clk"; 1387 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1388 <&dmac2 0x5b>, <&dmac2 0x5a>; 1389 dma-names = "tx", "rx", "tx", "rx"; 1390 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1391 resets = <&cpg 202>; 1392 status = "disabled"; 1393 }; 1394 1395 tpu: pwm@e6e80000 { 1396 compatible = "renesas,tpu-r8a77961", "renesas,tpu"; 1397 reg = <0 0xe6e80000 0 0x148>; 1398 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&cpg CPG_MOD 304>; 1400 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1401 resets = <&cpg 304>; 1402 #pwm-cells = <3>; 1403 status = "disabled"; 1404 }; 1405 1406 msiof0: spi@e6e90000 { 1407 compatible = "renesas,msiof-r8a77961", 1408 "renesas,rcar-gen3-msiof"; 1409 reg = <0 0xe6e90000 0 0x0064>; 1410 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&cpg CPG_MOD 211>; 1412 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1413 <&dmac2 0x41>, <&dmac2 0x40>; 1414 dma-names = "tx", "rx", "tx", "rx"; 1415 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1416 resets = <&cpg 211>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 msiof1: spi@e6ea0000 { 1423 compatible = "renesas,msiof-r8a77961", 1424 "renesas,rcar-gen3-msiof"; 1425 reg = <0 0xe6ea0000 0 0x0064>; 1426 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&cpg CPG_MOD 210>; 1428 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1429 <&dmac2 0x43>, <&dmac2 0x42>; 1430 dma-names = "tx", "rx", "tx", "rx"; 1431 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1432 resets = <&cpg 210>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 1438 msiof2: spi@e6c00000 { 1439 compatible = "renesas,msiof-r8a77961", 1440 "renesas,rcar-gen3-msiof"; 1441 reg = <0 0xe6c00000 0 0x0064>; 1442 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1443 clocks = <&cpg CPG_MOD 209>; 1444 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1445 dma-names = "tx", "rx"; 1446 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1447 resets = <&cpg 209>; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 status = "disabled"; 1451 }; 1452 1453 msiof3: spi@e6c10000 { 1454 compatible = "renesas,msiof-r8a77961", 1455 "renesas,rcar-gen3-msiof"; 1456 reg = <0 0xe6c10000 0 0x0064>; 1457 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1458 clocks = <&cpg CPG_MOD 208>; 1459 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1460 dma-names = "tx", "rx"; 1461 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1462 resets = <&cpg 208>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 vin0: video@e6ef0000 { 1469 compatible = "renesas,vin-r8a77961"; 1470 reg = <0 0xe6ef0000 0 0x1000>; 1471 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1472 clocks = <&cpg CPG_MOD 811>; 1473 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1474 resets = <&cpg 811>; 1475 renesas,id = <0>; 1476 status = "disabled"; 1477 1478 ports { 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 1482 port@1 { 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 1486 reg = <1>; 1487 1488 vin0csi20: endpoint@0 { 1489 reg = <0>; 1490 remote-endpoint = <&csi20vin0>; 1491 }; 1492 vin0csi40: endpoint@2 { 1493 reg = <2>; 1494 remote-endpoint = <&csi40vin0>; 1495 }; 1496 }; 1497 }; 1498 }; 1499 1500 vin1: video@e6ef1000 { 1501 compatible = "renesas,vin-r8a77961"; 1502 reg = <0 0xe6ef1000 0 0x1000>; 1503 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1504 clocks = <&cpg CPG_MOD 810>; 1505 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1506 resets = <&cpg 810>; 1507 renesas,id = <1>; 1508 status = "disabled"; 1509 1510 ports { 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 1514 port@1 { 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 1518 reg = <1>; 1519 1520 vin1csi20: endpoint@0 { 1521 reg = <0>; 1522 remote-endpoint = <&csi20vin1>; 1523 }; 1524 vin1csi40: endpoint@2 { 1525 reg = <2>; 1526 remote-endpoint = <&csi40vin1>; 1527 }; 1528 }; 1529 }; 1530 }; 1531 1532 vin2: video@e6ef2000 { 1533 compatible = "renesas,vin-r8a77961"; 1534 reg = <0 0xe6ef2000 0 0x1000>; 1535 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1536 clocks = <&cpg CPG_MOD 809>; 1537 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1538 resets = <&cpg 809>; 1539 renesas,id = <2>; 1540 status = "disabled"; 1541 1542 ports { 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 1546 port@1 { 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 1550 reg = <1>; 1551 1552 vin2csi20: endpoint@0 { 1553 reg = <0>; 1554 remote-endpoint = <&csi20vin2>; 1555 }; 1556 vin2csi40: endpoint@2 { 1557 reg = <2>; 1558 remote-endpoint = <&csi40vin2>; 1559 }; 1560 }; 1561 }; 1562 }; 1563 1564 vin3: video@e6ef3000 { 1565 compatible = "renesas,vin-r8a77961"; 1566 reg = <0 0xe6ef3000 0 0x1000>; 1567 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1568 clocks = <&cpg CPG_MOD 808>; 1569 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1570 resets = <&cpg 808>; 1571 renesas,id = <3>; 1572 status = "disabled"; 1573 1574 ports { 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 1578 port@1 { 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 1582 reg = <1>; 1583 1584 vin3csi20: endpoint@0 { 1585 reg = <0>; 1586 remote-endpoint = <&csi20vin3>; 1587 }; 1588 vin3csi40: endpoint@2 { 1589 reg = <2>; 1590 remote-endpoint = <&csi40vin3>; 1591 }; 1592 }; 1593 }; 1594 }; 1595 1596 vin4: video@e6ef4000 { 1597 compatible = "renesas,vin-r8a77961"; 1598 reg = <0 0xe6ef4000 0 0x1000>; 1599 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&cpg CPG_MOD 807>; 1601 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1602 resets = <&cpg 807>; 1603 renesas,id = <4>; 1604 status = "disabled"; 1605 1606 ports { 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 1610 port@1 { 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 1614 reg = <1>; 1615 1616 vin4csi20: endpoint@0 { 1617 reg = <0>; 1618 remote-endpoint = <&csi20vin4>; 1619 }; 1620 vin4csi40: endpoint@2 { 1621 reg = <2>; 1622 remote-endpoint = <&csi40vin4>; 1623 }; 1624 }; 1625 }; 1626 }; 1627 1628 vin5: video@e6ef5000 { 1629 compatible = "renesas,vin-r8a77961"; 1630 reg = <0 0xe6ef5000 0 0x1000>; 1631 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1632 clocks = <&cpg CPG_MOD 806>; 1633 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1634 resets = <&cpg 806>; 1635 renesas,id = <5>; 1636 status = "disabled"; 1637 1638 ports { 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 1642 port@1 { 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 1646 reg = <1>; 1647 1648 vin5csi20: endpoint@0 { 1649 reg = <0>; 1650 remote-endpoint = <&csi20vin5>; 1651 }; 1652 vin5csi40: endpoint@2 { 1653 reg = <2>; 1654 remote-endpoint = <&csi40vin5>; 1655 }; 1656 }; 1657 }; 1658 }; 1659 1660 vin6: video@e6ef6000 { 1661 compatible = "renesas,vin-r8a77961"; 1662 reg = <0 0xe6ef6000 0 0x1000>; 1663 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1664 clocks = <&cpg CPG_MOD 805>; 1665 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1666 resets = <&cpg 805>; 1667 renesas,id = <6>; 1668 status = "disabled"; 1669 1670 ports { 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 1674 port@1 { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 reg = <1>; 1679 1680 vin6csi20: endpoint@0 { 1681 reg = <0>; 1682 remote-endpoint = <&csi20vin6>; 1683 }; 1684 vin6csi40: endpoint@2 { 1685 reg = <2>; 1686 remote-endpoint = <&csi40vin6>; 1687 }; 1688 }; 1689 }; 1690 }; 1691 1692 vin7: video@e6ef7000 { 1693 compatible = "renesas,vin-r8a77961"; 1694 reg = <0 0xe6ef7000 0 0x1000>; 1695 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&cpg CPG_MOD 804>; 1697 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1698 resets = <&cpg 804>; 1699 renesas,id = <7>; 1700 status = "disabled"; 1701 1702 ports { 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 1706 port@1 { 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 1710 reg = <1>; 1711 1712 vin7csi20: endpoint@0 { 1713 reg = <0>; 1714 remote-endpoint = <&csi20vin7>; 1715 }; 1716 vin7csi40: endpoint@2 { 1717 reg = <2>; 1718 remote-endpoint = <&csi40vin7>; 1719 }; 1720 }; 1721 }; 1722 }; 1723 1724 rcar_sound: sound@ec500000 { 1725 /* 1726 * #sound-dai-cells is required 1727 * 1728 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1729 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1730 */ 1731 /* 1732 * #clock-cells is required for audio_clkout0/1/2/3 1733 * 1734 * clkout : #clock-cells = <0>; <&rcar_sound>; 1735 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1736 */ 1737 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1738 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1739 <0 0xec5a0000 0 0x100>, /* ADG */ 1740 <0 0xec540000 0 0x1000>, /* SSIU */ 1741 <0 0xec541000 0 0x280>, /* SSI */ 1742 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1743 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1744 1745 clocks = <&cpg CPG_MOD 1005>, 1746 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1747 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1748 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1749 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1750 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1751 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1752 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1753 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1754 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1755 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1756 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1757 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1758 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1759 <&audio_clk_a>, <&audio_clk_b>, 1760 <&audio_clk_c>, 1761 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1762 clock-names = "ssi-all", 1763 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1764 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1765 "ssi.1", "ssi.0", 1766 "src.9", "src.8", "src.7", "src.6", 1767 "src.5", "src.4", "src.3", "src.2", 1768 "src.1", "src.0", 1769 "mix.1", "mix.0", 1770 "ctu.1", "ctu.0", 1771 "dvc.0", "dvc.1", 1772 "clk_a", "clk_b", "clk_c", "clk_i"; 1773 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1774 resets = <&cpg 1005>, 1775 <&cpg 1006>, <&cpg 1007>, 1776 <&cpg 1008>, <&cpg 1009>, 1777 <&cpg 1010>, <&cpg 1011>, 1778 <&cpg 1012>, <&cpg 1013>, 1779 <&cpg 1014>, <&cpg 1015>; 1780 reset-names = "ssi-all", 1781 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1782 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1783 "ssi.1", "ssi.0"; 1784 status = "disabled"; 1785 1786 rcar_sound,ctu { 1787 ctu00: ctu-0 { }; 1788 ctu01: ctu-1 { }; 1789 ctu02: ctu-2 { }; 1790 ctu03: ctu-3 { }; 1791 ctu10: ctu-4 { }; 1792 ctu11: ctu-5 { }; 1793 ctu12: ctu-6 { }; 1794 ctu13: ctu-7 { }; 1795 }; 1796 1797 rcar_sound,dvc { 1798 dvc0: dvc-0 { 1799 dmas = <&audma1 0xbc>; 1800 dma-names = "tx"; 1801 }; 1802 dvc1: dvc-1 { 1803 dmas = <&audma1 0xbe>; 1804 dma-names = "tx"; 1805 }; 1806 }; 1807 1808 rcar_sound,mix { 1809 mix0: mix-0 { }; 1810 mix1: mix-1 { }; 1811 }; 1812 1813 rcar_sound,src { 1814 src0: src-0 { 1815 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1816 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1817 dma-names = "rx", "tx"; 1818 }; 1819 src1: src-1 { 1820 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1821 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1822 dma-names = "rx", "tx"; 1823 }; 1824 src2: src-2 { 1825 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1826 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1827 dma-names = "rx", "tx"; 1828 }; 1829 src3: src-3 { 1830 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1831 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1832 dma-names = "rx", "tx"; 1833 }; 1834 src4: src-4 { 1835 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1836 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1837 dma-names = "rx", "tx"; 1838 }; 1839 src5: src-5 { 1840 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1841 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1842 dma-names = "rx", "tx"; 1843 }; 1844 src6: src-6 { 1845 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1846 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1847 dma-names = "rx", "tx"; 1848 }; 1849 src7: src-7 { 1850 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1851 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1852 dma-names = "rx", "tx"; 1853 }; 1854 src8: src-8 { 1855 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1856 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1857 dma-names = "rx", "tx"; 1858 }; 1859 src9: src-9 { 1860 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1861 dmas = <&audma0 0x97>, <&audma1 0xba>; 1862 dma-names = "rx", "tx"; 1863 }; 1864 }; 1865 1866 rcar_sound,ssi { 1867 ssi0: ssi-0 { 1868 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1869 dmas = <&audma0 0x01>, <&audma1 0x02>; 1870 dma-names = "rx", "tx"; 1871 }; 1872 ssi1: ssi-1 { 1873 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1874 dmas = <&audma0 0x03>, <&audma1 0x04>; 1875 dma-names = "rx", "tx"; 1876 }; 1877 ssi2: ssi-2 { 1878 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1879 dmas = <&audma0 0x05>, <&audma1 0x06>; 1880 dma-names = "rx", "tx"; 1881 }; 1882 ssi3: ssi-3 { 1883 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1884 dmas = <&audma0 0x07>, <&audma1 0x08>; 1885 dma-names = "rx", "tx"; 1886 }; 1887 ssi4: ssi-4 { 1888 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1889 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1890 dma-names = "rx", "tx"; 1891 }; 1892 ssi5: ssi-5 { 1893 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1894 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1895 dma-names = "rx", "tx"; 1896 }; 1897 ssi6: ssi-6 { 1898 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1899 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1900 dma-names = "rx", "tx"; 1901 }; 1902 ssi7: ssi-7 { 1903 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1904 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssi8: ssi-8 { 1908 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1909 dmas = <&audma0 0x11>, <&audma1 0x12>; 1910 dma-names = "rx", "tx"; 1911 }; 1912 ssi9: ssi-9 { 1913 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1914 dmas = <&audma0 0x13>, <&audma1 0x14>; 1915 dma-names = "rx", "tx"; 1916 }; 1917 }; 1918 1919 rcar_sound,ssiu { 1920 ssiu00: ssiu-0 { 1921 dmas = <&audma0 0x15>, <&audma1 0x16>; 1922 dma-names = "rx", "tx"; 1923 }; 1924 ssiu01: ssiu-1 { 1925 dmas = <&audma0 0x35>, <&audma1 0x36>; 1926 dma-names = "rx", "tx"; 1927 }; 1928 ssiu02: ssiu-2 { 1929 dmas = <&audma0 0x37>, <&audma1 0x38>; 1930 dma-names = "rx", "tx"; 1931 }; 1932 ssiu03: ssiu-3 { 1933 dmas = <&audma0 0x47>, <&audma1 0x48>; 1934 dma-names = "rx", "tx"; 1935 }; 1936 ssiu04: ssiu-4 { 1937 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1938 dma-names = "rx", "tx"; 1939 }; 1940 ssiu05: ssiu-5 { 1941 dmas = <&audma0 0x43>, <&audma1 0x44>; 1942 dma-names = "rx", "tx"; 1943 }; 1944 ssiu06: ssiu-6 { 1945 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1946 dma-names = "rx", "tx"; 1947 }; 1948 ssiu07: ssiu-7 { 1949 dmas = <&audma0 0x53>, <&audma1 0x54>; 1950 dma-names = "rx", "tx"; 1951 }; 1952 ssiu10: ssiu-8 { 1953 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1954 dma-names = "rx", "tx"; 1955 }; 1956 ssiu11: ssiu-9 { 1957 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1958 dma-names = "rx", "tx"; 1959 }; 1960 ssiu12: ssiu-10 { 1961 dmas = <&audma0 0x57>, <&audma1 0x58>; 1962 dma-names = "rx", "tx"; 1963 }; 1964 ssiu13: ssiu-11 { 1965 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1966 dma-names = "rx", "tx"; 1967 }; 1968 ssiu14: ssiu-12 { 1969 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1970 dma-names = "rx", "tx"; 1971 }; 1972 ssiu15: ssiu-13 { 1973 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1974 dma-names = "rx", "tx"; 1975 }; 1976 ssiu16: ssiu-14 { 1977 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1978 dma-names = "rx", "tx"; 1979 }; 1980 ssiu17: ssiu-15 { 1981 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1982 dma-names = "rx", "tx"; 1983 }; 1984 ssiu20: ssiu-16 { 1985 dmas = <&audma0 0x63>, <&audma1 0x64>; 1986 dma-names = "rx", "tx"; 1987 }; 1988 ssiu21: ssiu-17 { 1989 dmas = <&audma0 0x67>, <&audma1 0x68>; 1990 dma-names = "rx", "tx"; 1991 }; 1992 ssiu22: ssiu-18 { 1993 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1994 dma-names = "rx", "tx"; 1995 }; 1996 ssiu23: ssiu-19 { 1997 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1998 dma-names = "rx", "tx"; 1999 }; 2000 ssiu24: ssiu-20 { 2001 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 2002 dma-names = "rx", "tx"; 2003 }; 2004 ssiu25: ssiu-21 { 2005 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 2006 dma-names = "rx", "tx"; 2007 }; 2008 ssiu26: ssiu-22 { 2009 dmas = <&audma0 0xED>, <&audma1 0xEE>; 2010 dma-names = "rx", "tx"; 2011 }; 2012 ssiu27: ssiu-23 { 2013 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 2014 dma-names = "rx", "tx"; 2015 }; 2016 ssiu30: ssiu-24 { 2017 dmas = <&audma0 0x6f>, <&audma1 0x70>; 2018 dma-names = "rx", "tx"; 2019 }; 2020 ssiu31: ssiu-25 { 2021 dmas = <&audma0 0x21>, <&audma1 0x22>; 2022 dma-names = "rx", "tx"; 2023 }; 2024 ssiu32: ssiu-26 { 2025 dmas = <&audma0 0x23>, <&audma1 0x24>; 2026 dma-names = "rx", "tx"; 2027 }; 2028 ssiu33: ssiu-27 { 2029 dmas = <&audma0 0x25>, <&audma1 0x26>; 2030 dma-names = "rx", "tx"; 2031 }; 2032 ssiu34: ssiu-28 { 2033 dmas = <&audma0 0x27>, <&audma1 0x28>; 2034 dma-names = "rx", "tx"; 2035 }; 2036 ssiu35: ssiu-29 { 2037 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2038 dma-names = "rx", "tx"; 2039 }; 2040 ssiu36: ssiu-30 { 2041 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2042 dma-names = "rx", "tx"; 2043 }; 2044 ssiu37: ssiu-31 { 2045 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2046 dma-names = "rx", "tx"; 2047 }; 2048 ssiu40: ssiu-32 { 2049 dmas = <&audma0 0x71>, <&audma1 0x72>; 2050 dma-names = "rx", "tx"; 2051 }; 2052 ssiu41: ssiu-33 { 2053 dmas = <&audma0 0x17>, <&audma1 0x18>; 2054 dma-names = "rx", "tx"; 2055 }; 2056 ssiu42: ssiu-34 { 2057 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2058 dma-names = "rx", "tx"; 2059 }; 2060 ssiu43: ssiu-35 { 2061 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2062 dma-names = "rx", "tx"; 2063 }; 2064 ssiu44: ssiu-36 { 2065 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2066 dma-names = "rx", "tx"; 2067 }; 2068 ssiu45: ssiu-37 { 2069 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2070 dma-names = "rx", "tx"; 2071 }; 2072 ssiu46: ssiu-38 { 2073 dmas = <&audma0 0x31>, <&audma1 0x32>; 2074 dma-names = "rx", "tx"; 2075 }; 2076 ssiu47: ssiu-39 { 2077 dmas = <&audma0 0x33>, <&audma1 0x34>; 2078 dma-names = "rx", "tx"; 2079 }; 2080 ssiu50: ssiu-40 { 2081 dmas = <&audma0 0x73>, <&audma1 0x74>; 2082 dma-names = "rx", "tx"; 2083 }; 2084 ssiu60: ssiu-41 { 2085 dmas = <&audma0 0x75>, <&audma1 0x76>; 2086 dma-names = "rx", "tx"; 2087 }; 2088 ssiu70: ssiu-42 { 2089 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2090 dma-names = "rx", "tx"; 2091 }; 2092 ssiu80: ssiu-43 { 2093 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2094 dma-names = "rx", "tx"; 2095 }; 2096 ssiu90: ssiu-44 { 2097 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2098 dma-names = "rx", "tx"; 2099 }; 2100 ssiu91: ssiu-45 { 2101 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2102 dma-names = "rx", "tx"; 2103 }; 2104 ssiu92: ssiu-46 { 2105 dmas = <&audma0 0x81>, <&audma1 0x82>; 2106 dma-names = "rx", "tx"; 2107 }; 2108 ssiu93: ssiu-47 { 2109 dmas = <&audma0 0x83>, <&audma1 0x84>; 2110 dma-names = "rx", "tx"; 2111 }; 2112 ssiu94: ssiu-48 { 2113 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2114 dma-names = "rx", "tx"; 2115 }; 2116 ssiu95: ssiu-49 { 2117 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2118 dma-names = "rx", "tx"; 2119 }; 2120 ssiu96: ssiu-50 { 2121 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2122 dma-names = "rx", "tx"; 2123 }; 2124 ssiu97: ssiu-51 { 2125 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2126 dma-names = "rx", "tx"; 2127 }; 2128 }; 2129 }; 2130 2131 audma0: dma-controller@ec700000 { 2132 compatible = "renesas,dmac-r8a77961", 2133 "renesas,rcar-dmac"; 2134 reg = <0 0xec700000 0 0x10000>; 2135 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2152 interrupt-names = "error", 2153 "ch0", "ch1", "ch2", "ch3", 2154 "ch4", "ch5", "ch6", "ch7", 2155 "ch8", "ch9", "ch10", "ch11", 2156 "ch12", "ch13", "ch14", "ch15"; 2157 clocks = <&cpg CPG_MOD 502>; 2158 clock-names = "fck"; 2159 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2160 resets = <&cpg 502>; 2161 #dma-cells = <1>; 2162 dma-channels = <16>; 2163 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2164 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2165 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2166 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2167 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2168 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2169 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2170 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2171 }; 2172 2173 audma1: dma-controller@ec720000 { 2174 compatible = "renesas,dmac-r8a77961", 2175 "renesas,rcar-dmac"; 2176 reg = <0 0xec720000 0 0x10000>; 2177 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2194 interrupt-names = "error", 2195 "ch0", "ch1", "ch2", "ch3", 2196 "ch4", "ch5", "ch6", "ch7", 2197 "ch8", "ch9", "ch10", "ch11", 2198 "ch12", "ch13", "ch14", "ch15"; 2199 clocks = <&cpg CPG_MOD 501>; 2200 clock-names = "fck"; 2201 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2202 resets = <&cpg 501>; 2203 #dma-cells = <1>; 2204 dma-channels = <16>; 2205 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2206 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2207 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2208 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2209 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2210 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2211 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2212 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2213 }; 2214 2215 xhci0: usb@ee000000 { 2216 compatible = "renesas,xhci-r8a77961", 2217 "renesas,rcar-gen3-xhci"; 2218 reg = <0 0xee000000 0 0xc00>; 2219 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2220 clocks = <&cpg CPG_MOD 328>; 2221 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2222 resets = <&cpg 328>; 2223 status = "disabled"; 2224 }; 2225 2226 usb3_peri0: usb@ee020000 { 2227 compatible = "renesas,r8a77961-usb3-peri", 2228 "renesas,rcar-gen3-usb3-peri"; 2229 reg = <0 0xee020000 0 0x400>; 2230 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2231 clocks = <&cpg CPG_MOD 328>; 2232 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2233 resets = <&cpg 328>; 2234 status = "disabled"; 2235 }; 2236 2237 ohci0: usb@ee080000 { 2238 compatible = "generic-ohci"; 2239 reg = <0 0xee080000 0 0x100>; 2240 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2241 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2242 phys = <&usb2_phy0 1>; 2243 phy-names = "usb"; 2244 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2245 resets = <&cpg 703>, <&cpg 704>; 2246 status = "disabled"; 2247 }; 2248 2249 ohci1: usb@ee0a0000 { 2250 compatible = "generic-ohci"; 2251 reg = <0 0xee0a0000 0 0x100>; 2252 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2253 clocks = <&cpg CPG_MOD 702>; 2254 phys = <&usb2_phy1 1>; 2255 phy-names = "usb"; 2256 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2257 resets = <&cpg 702>; 2258 status = "disabled"; 2259 }; 2260 2261 ehci0: usb@ee080100 { 2262 compatible = "generic-ehci"; 2263 reg = <0 0xee080100 0 0x100>; 2264 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2266 phys = <&usb2_phy0 2>; 2267 phy-names = "usb"; 2268 companion = <&ohci0>; 2269 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2270 resets = <&cpg 703>, <&cpg 704>; 2271 status = "disabled"; 2272 }; 2273 2274 ehci1: usb@ee0a0100 { 2275 compatible = "generic-ehci"; 2276 reg = <0 0xee0a0100 0 0x100>; 2277 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2278 clocks = <&cpg CPG_MOD 702>; 2279 phys = <&usb2_phy1 2>; 2280 phy-names = "usb"; 2281 companion = <&ohci1>; 2282 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2283 resets = <&cpg 702>; 2284 status = "disabled"; 2285 }; 2286 2287 usb2_phy0: usb-phy@ee080200 { 2288 compatible = "renesas,usb2-phy-r8a77961", 2289 "renesas,rcar-gen3-usb2-phy"; 2290 reg = <0 0xee080200 0 0x700>; 2291 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2292 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2293 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2294 resets = <&cpg 703>, <&cpg 704>; 2295 #phy-cells = <1>; 2296 status = "disabled"; 2297 }; 2298 2299 usb2_phy1: usb-phy@ee0a0200 { 2300 compatible = "renesas,usb2-phy-r8a77961", 2301 "renesas,rcar-gen3-usb2-phy"; 2302 reg = <0 0xee0a0200 0 0x700>; 2303 clocks = <&cpg CPG_MOD 702>; 2304 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2305 resets = <&cpg 702>; 2306 #phy-cells = <1>; 2307 status = "disabled"; 2308 }; 2309 2310 sdhi0: mmc@ee100000 { 2311 compatible = "renesas,sdhi-r8a77961", 2312 "renesas,rcar-gen3-sdhi"; 2313 reg = <0 0xee100000 0 0x2000>; 2314 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2315 clocks = <&cpg CPG_MOD 314>; 2316 max-frequency = <200000000>; 2317 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2318 resets = <&cpg 314>; 2319 iommus = <&ipmmu_ds1 32>; 2320 status = "disabled"; 2321 }; 2322 2323 sdhi1: mmc@ee120000 { 2324 compatible = "renesas,sdhi-r8a77961", 2325 "renesas,rcar-gen3-sdhi"; 2326 reg = <0 0xee120000 0 0x2000>; 2327 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2328 clocks = <&cpg CPG_MOD 313>; 2329 max-frequency = <200000000>; 2330 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2331 resets = <&cpg 313>; 2332 iommus = <&ipmmu_ds1 33>; 2333 status = "disabled"; 2334 }; 2335 2336 sdhi2: mmc@ee140000 { 2337 compatible = "renesas,sdhi-r8a77961", 2338 "renesas,rcar-gen3-sdhi"; 2339 reg = <0 0xee140000 0 0x2000>; 2340 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2341 clocks = <&cpg CPG_MOD 312>; 2342 max-frequency = <200000000>; 2343 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2344 resets = <&cpg 312>; 2345 iommus = <&ipmmu_ds1 34>; 2346 status = "disabled"; 2347 }; 2348 2349 sdhi3: mmc@ee160000 { 2350 compatible = "renesas,sdhi-r8a77961", 2351 "renesas,rcar-gen3-sdhi"; 2352 reg = <0 0xee160000 0 0x2000>; 2353 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2354 clocks = <&cpg CPG_MOD 311>; 2355 max-frequency = <200000000>; 2356 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2357 resets = <&cpg 311>; 2358 iommus = <&ipmmu_ds1 35>; 2359 status = "disabled"; 2360 }; 2361 2362 gic: interrupt-controller@f1010000 { 2363 compatible = "arm,gic-400"; 2364 #interrupt-cells = <3>; 2365 #address-cells = <0>; 2366 interrupt-controller; 2367 reg = <0x0 0xf1010000 0 0x1000>, 2368 <0x0 0xf1020000 0 0x20000>, 2369 <0x0 0xf1040000 0 0x20000>, 2370 <0x0 0xf1060000 0 0x20000>; 2371 interrupts = <GIC_PPI 9 2372 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2373 clocks = <&cpg CPG_MOD 408>; 2374 clock-names = "clk"; 2375 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2376 resets = <&cpg 408>; 2377 }; 2378 2379 pciec0: pcie@fe000000 { 2380 compatible = "renesas,pcie-r8a77961", 2381 "renesas,pcie-rcar-gen3"; 2382 reg = <0 0xfe000000 0 0x80000>; 2383 #address-cells = <3>; 2384 #size-cells = <2>; 2385 bus-range = <0x00 0xff>; 2386 device_type = "pci"; 2387 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2388 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2389 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2390 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2391 /* Map all possible DDR as inbound ranges */ 2392 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2393 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2396 #interrupt-cells = <1>; 2397 interrupt-map-mask = <0 0 0 0>; 2398 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2399 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2400 clock-names = "pcie", "pcie_bus"; 2401 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2402 resets = <&cpg 319>; 2403 status = "disabled"; 2404 }; 2405 2406 pciec1: pcie@ee800000 { 2407 compatible = "renesas,pcie-r8a77961", 2408 "renesas,pcie-rcar-gen3"; 2409 reg = <0 0xee800000 0 0x80000>; 2410 #address-cells = <3>; 2411 #size-cells = <2>; 2412 bus-range = <0x00 0xff>; 2413 device_type = "pci"; 2414 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2415 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2416 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2417 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2418 /* Map all possible DDR as inbound ranges */ 2419 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2420 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2423 #interrupt-cells = <1>; 2424 interrupt-map-mask = <0 0 0 0>; 2425 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2426 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2427 clock-names = "pcie", "pcie_bus"; 2428 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2429 resets = <&cpg 318>; 2430 status = "disabled"; 2431 }; 2432 2433 fcpf0: fcp@fe950000 { 2434 compatible = "renesas,fcpf"; 2435 reg = <0 0xfe950000 0 0x200>; 2436 clocks = <&cpg CPG_MOD 615>; 2437 power-domains = <&sysc R8A77961_PD_A3VC>; 2438 resets = <&cpg 615>; 2439 }; 2440 2441 fcpvb0: fcp@fe96f000 { 2442 compatible = "renesas,fcpv"; 2443 reg = <0 0xfe96f000 0 0x200>; 2444 clocks = <&cpg CPG_MOD 607>; 2445 power-domains = <&sysc R8A77961_PD_A3VC>; 2446 resets = <&cpg 607>; 2447 }; 2448 2449 fcpvi0: fcp@fe9af000 { 2450 compatible = "renesas,fcpv"; 2451 reg = <0 0xfe9af000 0 0x200>; 2452 clocks = <&cpg CPG_MOD 611>; 2453 power-domains = <&sysc R8A77961_PD_A3VC>; 2454 resets = <&cpg 611>; 2455 iommus = <&ipmmu_vc0 19>; 2456 }; 2457 2458 fcpvd0: fcp@fea27000 { 2459 compatible = "renesas,fcpv"; 2460 reg = <0 0xfea27000 0 0x200>; 2461 clocks = <&cpg CPG_MOD 603>; 2462 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2463 resets = <&cpg 603>; 2464 iommus = <&ipmmu_vi0 8>; 2465 }; 2466 2467 fcpvd1: fcp@fea2f000 { 2468 compatible = "renesas,fcpv"; 2469 reg = <0 0xfea2f000 0 0x200>; 2470 clocks = <&cpg CPG_MOD 602>; 2471 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2472 resets = <&cpg 602>; 2473 iommus = <&ipmmu_vi0 9>; 2474 }; 2475 2476 fcpvd2: fcp@fea37000 { 2477 compatible = "renesas,fcpv"; 2478 reg = <0 0xfea37000 0 0x200>; 2479 clocks = <&cpg CPG_MOD 601>; 2480 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2481 resets = <&cpg 601>; 2482 iommus = <&ipmmu_vi0 10>; 2483 }; 2484 2485 vspb: vsp@fe960000 { 2486 compatible = "renesas,vsp2"; 2487 reg = <0 0xfe960000 0 0x8000>; 2488 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2489 clocks = <&cpg CPG_MOD 626>; 2490 power-domains = <&sysc R8A77961_PD_A3VC>; 2491 resets = <&cpg 626>; 2492 2493 renesas,fcp = <&fcpvb0>; 2494 }; 2495 2496 vspd0: vsp@fea20000 { 2497 compatible = "renesas,vsp2"; 2498 reg = <0 0xfea20000 0 0x5000>; 2499 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2500 clocks = <&cpg CPG_MOD 623>; 2501 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2502 resets = <&cpg 623>; 2503 2504 renesas,fcp = <&fcpvd0>; 2505 }; 2506 2507 vspd1: vsp@fea28000 { 2508 compatible = "renesas,vsp2"; 2509 reg = <0 0xfea28000 0 0x5000>; 2510 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2511 clocks = <&cpg CPG_MOD 622>; 2512 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2513 resets = <&cpg 622>; 2514 2515 renesas,fcp = <&fcpvd1>; 2516 }; 2517 2518 vspd2: vsp@fea30000 { 2519 compatible = "renesas,vsp2"; 2520 reg = <0 0xfea30000 0 0x5000>; 2521 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2522 clocks = <&cpg CPG_MOD 621>; 2523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2524 resets = <&cpg 621>; 2525 2526 renesas,fcp = <&fcpvd2>; 2527 }; 2528 2529 vspi0: vsp@fe9a0000 { 2530 compatible = "renesas,vsp2"; 2531 reg = <0 0xfe9a0000 0 0x8000>; 2532 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2533 clocks = <&cpg CPG_MOD 631>; 2534 power-domains = <&sysc R8A77961_PD_A3VC>; 2535 resets = <&cpg 631>; 2536 2537 renesas,fcp = <&fcpvi0>; 2538 }; 2539 2540 csi20: csi2@fea80000 { 2541 compatible = "renesas,r8a77961-csi2"; 2542 reg = <0 0xfea80000 0 0x10000>; 2543 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2544 clocks = <&cpg CPG_MOD 714>; 2545 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2546 resets = <&cpg 714>; 2547 status = "disabled"; 2548 2549 ports { 2550 #address-cells = <1>; 2551 #size-cells = <0>; 2552 2553 port@0 { 2554 reg = <0>; 2555 }; 2556 2557 port@1 { 2558 #address-cells = <1>; 2559 #size-cells = <0>; 2560 2561 reg = <1>; 2562 2563 csi20vin0: endpoint@0 { 2564 reg = <0>; 2565 remote-endpoint = <&vin0csi20>; 2566 }; 2567 csi20vin1: endpoint@1 { 2568 reg = <1>; 2569 remote-endpoint = <&vin1csi20>; 2570 }; 2571 csi20vin2: endpoint@2 { 2572 reg = <2>; 2573 remote-endpoint = <&vin2csi20>; 2574 }; 2575 csi20vin3: endpoint@3 { 2576 reg = <3>; 2577 remote-endpoint = <&vin3csi20>; 2578 }; 2579 csi20vin4: endpoint@4 { 2580 reg = <4>; 2581 remote-endpoint = <&vin4csi20>; 2582 }; 2583 csi20vin5: endpoint@5 { 2584 reg = <5>; 2585 remote-endpoint = <&vin5csi20>; 2586 }; 2587 csi20vin6: endpoint@6 { 2588 reg = <6>; 2589 remote-endpoint = <&vin6csi20>; 2590 }; 2591 csi20vin7: endpoint@7 { 2592 reg = <7>; 2593 remote-endpoint = <&vin7csi20>; 2594 }; 2595 }; 2596 }; 2597 }; 2598 2599 csi40: csi2@feaa0000 { 2600 compatible = "renesas,r8a77961-csi2"; 2601 reg = <0 0xfeaa0000 0 0x10000>; 2602 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2603 clocks = <&cpg CPG_MOD 716>; 2604 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2605 resets = <&cpg 716>; 2606 status = "disabled"; 2607 2608 ports { 2609 #address-cells = <1>; 2610 #size-cells = <0>; 2611 2612 port@0 { 2613 reg = <0>; 2614 }; 2615 2616 port@1 { 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 2620 reg = <1>; 2621 2622 csi40vin0: endpoint@0 { 2623 reg = <0>; 2624 remote-endpoint = <&vin0csi40>; 2625 }; 2626 csi40vin1: endpoint@1 { 2627 reg = <1>; 2628 remote-endpoint = <&vin1csi40>; 2629 }; 2630 csi40vin2: endpoint@2 { 2631 reg = <2>; 2632 remote-endpoint = <&vin2csi40>; 2633 }; 2634 csi40vin3: endpoint@3 { 2635 reg = <3>; 2636 remote-endpoint = <&vin3csi40>; 2637 }; 2638 csi40vin4: endpoint@4 { 2639 reg = <4>; 2640 remote-endpoint = <&vin4csi40>; 2641 }; 2642 csi40vin5: endpoint@5 { 2643 reg = <5>; 2644 remote-endpoint = <&vin5csi40>; 2645 }; 2646 csi40vin6: endpoint@6 { 2647 reg = <6>; 2648 remote-endpoint = <&vin6csi40>; 2649 }; 2650 csi40vin7: endpoint@7 { 2651 reg = <7>; 2652 remote-endpoint = <&vin7csi40>; 2653 }; 2654 }; 2655 2656 }; 2657 }; 2658 2659 hdmi0: hdmi@fead0000 { 2660 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2661 reg = <0 0xfead0000 0 0x10000>; 2662 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2663 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2664 clock-names = "iahb", "isfr"; 2665 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2666 resets = <&cpg 729>; 2667 status = "disabled"; 2668 2669 ports { 2670 #address-cells = <1>; 2671 #size-cells = <0>; 2672 port@0 { 2673 reg = <0>; 2674 dw_hdmi0_in: endpoint { 2675 remote-endpoint = <&du_out_hdmi0>; 2676 }; 2677 }; 2678 port@1 { 2679 reg = <1>; 2680 }; 2681 port@2 { 2682 /* HDMI sound */ 2683 reg = <2>; 2684 }; 2685 }; 2686 }; 2687 2688 du: display@feb00000 { 2689 compatible = "renesas,du-r8a77961"; 2690 reg = <0 0xfeb00000 0 0x70000>; 2691 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2694 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2695 <&cpg CPG_MOD 722>; 2696 clock-names = "du.0", "du.1", "du.2"; 2697 resets = <&cpg 724>, <&cpg 722>; 2698 reset-names = "du.0", "du.2"; 2699 2700 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2701 status = "disabled"; 2702 2703 ports { 2704 #address-cells = <1>; 2705 #size-cells = <0>; 2706 2707 port@0 { 2708 reg = <0>; 2709 du_out_rgb: endpoint { 2710 }; 2711 }; 2712 port@1 { 2713 reg = <1>; 2714 du_out_hdmi0: endpoint { 2715 remote-endpoint = <&dw_hdmi0_in>; 2716 }; 2717 }; 2718 port@2 { 2719 reg = <2>; 2720 du_out_lvds0: endpoint { 2721 }; 2722 }; 2723 }; 2724 }; 2725 2726 prr: chipid@fff00044 { 2727 compatible = "renesas,prr"; 2728 reg = <0 0xfff00044 0 4>; 2729 }; 2730 }; 2731 2732 thermal-zones { 2733 sensor_thermal1: sensor-thermal1 { 2734 polling-delay-passive = <250>; 2735 polling-delay = <1000>; 2736 thermal-sensors = <&tsc 0>; 2737 sustainable-power = <3874>; 2738 2739 trips { 2740 sensor1_crit: sensor1-crit { 2741 temperature = <120000>; 2742 hysteresis = <1000>; 2743 type = "critical"; 2744 }; 2745 }; 2746 }; 2747 2748 sensor_thermal2: sensor-thermal2 { 2749 polling-delay-passive = <250>; 2750 polling-delay = <1000>; 2751 thermal-sensors = <&tsc 1>; 2752 sustainable-power = <3874>; 2753 2754 trips { 2755 sensor2_crit: sensor2-crit { 2756 temperature = <120000>; 2757 hysteresis = <1000>; 2758 type = "critical"; 2759 }; 2760 }; 2761 }; 2762 2763 sensor_thermal3: sensor-thermal3 { 2764 polling-delay-passive = <250>; 2765 polling-delay = <1000>; 2766 thermal-sensors = <&tsc 2>; 2767 sustainable-power = <3874>; 2768 2769 cooling-maps { 2770 map0 { 2771 trip = <&target>; 2772 cooling-device = <&a57_0 2 4>; 2773 contribution = <1024>; 2774 }; 2775 map1 { 2776 trip = <&target>; 2777 cooling-device = <&a53_0 0 2>; 2778 contribution = <1024>; 2779 }; 2780 }; 2781 trips { 2782 target: trip-point1 { 2783 temperature = <100000>; 2784 hysteresis = <1000>; 2785 type = "passive"; 2786 }; 2787 2788 sensor3_crit: sensor3-crit { 2789 temperature = <120000>; 2790 hysteresis = <1000>; 2791 type = "critical"; 2792 }; 2793 }; 2794 }; 2795 }; 2796 2797 timer { 2798 compatible = "arm,armv8-timer"; 2799 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2800 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2801 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2802 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2803 }; 2804 2805 /* External USB clocks - can be overridden by the board */ 2806 usb3s0_clk: usb3s0 { 2807 compatible = "fixed-clock"; 2808 #clock-cells = <0>; 2809 clock-frequency = <0>; 2810 }; 2811 2812 usb_extal_clk: usb_extal { 2813 compatible = "fixed-clock"; 2814 #clock-cells = <0>; 2815 clock-frequency = <0>; 2816 }; 2817}; 2818