1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car H3 (R8A77951) SoC 4 * 5 * Copyright (C) 2015 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a7795-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 13 14#define SOC_HAS_HDMI1 15#define SOC_HAS_SATA 16#define SOC_HAS_USB2_CH2 17#define SOC_HAS_USB2_CH3 18 19/ { 20 compatible = "renesas,r8a7795"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 /* 25 * The external audio clocks are configured as 0 Hz fixed frequency 26 * clocks by default. 27 * Boards that provide audio clocks should override them. 28 */ 29 audio_clk_a: audio_clk_a { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 audio_clk_b: audio_clk_b { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 39 }; 40 41 audio_clk_c: audio_clk_c { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 /* External CAN clock - to be overridden by boards that provide it */ 48 can_clk: can { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 }; 53 54 cluster0_opp: opp-table-0 { 55 compatible = "operating-points-v2"; 56 opp-shared; 57 58 opp-500000000 { 59 opp-hz = /bits/ 64 <500000000>; 60 opp-microvolt = <830000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1000000000 { 64 opp-hz = /bits/ 64 <1000000000>; 65 opp-microvolt = <830000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1500000000 { 69 opp-hz = /bits/ 64 <1500000000>; 70 opp-microvolt = <830000>; 71 clock-latency-ns = <300000>; 72 opp-suspend; 73 }; 74 opp-1600000000 { 75 opp-hz = /bits/ 64 <1600000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 }; 79 opp-1700000000 { 80 opp-hz = /bits/ 64 <1700000000>; 81 opp-microvolt = <960000>; 82 clock-latency-ns = <300000>; 83 turbo-mode; 84 }; 85 }; 86 87 cluster1_opp: opp-table-1 { 88 compatible = "operating-points-v2"; 89 opp-shared; 90 91 opp-800000000 { 92 opp-hz = /bits/ 64 <800000000>; 93 opp-microvolt = <820000>; 94 clock-latency-ns = <300000>; 95 }; 96 opp-1000000000 { 97 opp-hz = /bits/ 64 <1000000000>; 98 opp-microvolt = <820000>; 99 clock-latency-ns = <300000>; 100 }; 101 opp-1200000000 { 102 opp-hz = /bits/ 64 <1200000000>; 103 opp-microvolt = <820000>; 104 clock-latency-ns = <300000>; 105 }; 106 }; 107 108 cpus { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 cpu-map { 113 cluster0 { 114 core0 { 115 cpu = <&a57_0>; 116 }; 117 core1 { 118 cpu = <&a57_1>; 119 }; 120 core2 { 121 cpu = <&a57_2>; 122 }; 123 core3 { 124 cpu = <&a57_3>; 125 }; 126 }; 127 128 cluster1 { 129 core0 { 130 cpu = <&a53_0>; 131 }; 132 core1 { 133 cpu = <&a53_1>; 134 }; 135 core2 { 136 cpu = <&a53_2>; 137 }; 138 core3 { 139 cpu = <&a53_3>; 140 }; 141 }; 142 }; 143 144 a57_0: cpu@0 { 145 compatible = "arm,cortex-a57"; 146 reg = <0x0>; 147 device_type = "cpu"; 148 power-domains = <&sysc R8A7795_PD_CA57_CPU0>; 149 next-level-cache = <&L2_CA57>; 150 enable-method = "psci"; 151 cpu-idle-states = <&CPU_SLEEP_0>; 152 dynamic-power-coefficient = <854>; 153 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 154 operating-points-v2 = <&cluster0_opp>; 155 capacity-dmips-mhz = <1024>; 156 #cooling-cells = <2>; 157 }; 158 159 a57_1: cpu@1 { 160 compatible = "arm,cortex-a57"; 161 reg = <0x1>; 162 device_type = "cpu"; 163 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 164 next-level-cache = <&L2_CA57>; 165 enable-method = "psci"; 166 cpu-idle-states = <&CPU_SLEEP_0>; 167 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 168 operating-points-v2 = <&cluster0_opp>; 169 capacity-dmips-mhz = <1024>; 170 #cooling-cells = <2>; 171 }; 172 173 a57_2: cpu@2 { 174 compatible = "arm,cortex-a57"; 175 reg = <0x2>; 176 device_type = "cpu"; 177 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 178 next-level-cache = <&L2_CA57>; 179 enable-method = "psci"; 180 cpu-idle-states = <&CPU_SLEEP_0>; 181 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 182 operating-points-v2 = <&cluster0_opp>; 183 capacity-dmips-mhz = <1024>; 184 #cooling-cells = <2>; 185 }; 186 187 a57_3: cpu@3 { 188 compatible = "arm,cortex-a57"; 189 reg = <0x3>; 190 device_type = "cpu"; 191 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 192 next-level-cache = <&L2_CA57>; 193 enable-method = "psci"; 194 cpu-idle-states = <&CPU_SLEEP_0>; 195 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 196 operating-points-v2 = <&cluster0_opp>; 197 capacity-dmips-mhz = <1024>; 198 #cooling-cells = <2>; 199 }; 200 201 a53_0: cpu@100 { 202 compatible = "arm,cortex-a53"; 203 reg = <0x100>; 204 device_type = "cpu"; 205 power-domains = <&sysc R8A7795_PD_CA53_CPU0>; 206 next-level-cache = <&L2_CA53>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_SLEEP_1>; 209 #cooling-cells = <2>; 210 dynamic-power-coefficient = <277>; 211 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 212 operating-points-v2 = <&cluster1_opp>; 213 capacity-dmips-mhz = <535>; 214 }; 215 216 a53_1: cpu@101 { 217 compatible = "arm,cortex-a53"; 218 reg = <0x101>; 219 device_type = "cpu"; 220 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 221 next-level-cache = <&L2_CA53>; 222 enable-method = "psci"; 223 cpu-idle-states = <&CPU_SLEEP_1>; 224 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 225 operating-points-v2 = <&cluster1_opp>; 226 capacity-dmips-mhz = <535>; 227 }; 228 229 a53_2: cpu@102 { 230 compatible = "arm,cortex-a53"; 231 reg = <0x102>; 232 device_type = "cpu"; 233 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 234 next-level-cache = <&L2_CA53>; 235 enable-method = "psci"; 236 cpu-idle-states = <&CPU_SLEEP_1>; 237 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 238 operating-points-v2 = <&cluster1_opp>; 239 capacity-dmips-mhz = <535>; 240 }; 241 242 a53_3: cpu@103 { 243 compatible = "arm,cortex-a53"; 244 reg = <0x103>; 245 device_type = "cpu"; 246 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 247 next-level-cache = <&L2_CA53>; 248 enable-method = "psci"; 249 cpu-idle-states = <&CPU_SLEEP_1>; 250 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 251 operating-points-v2 = <&cluster1_opp>; 252 capacity-dmips-mhz = <535>; 253 }; 254 255 L2_CA57: cache-controller-0 { 256 compatible = "cache"; 257 power-domains = <&sysc R8A7795_PD_CA57_SCU>; 258 cache-unified; 259 cache-level = <2>; 260 }; 261 262 L2_CA53: cache-controller-1 { 263 compatible = "cache"; 264 power-domains = <&sysc R8A7795_PD_CA53_SCU>; 265 cache-unified; 266 cache-level = <2>; 267 }; 268 269 idle-states { 270 entry-method = "psci"; 271 272 CPU_SLEEP_0: cpu-sleep-0 { 273 compatible = "arm,idle-state"; 274 arm,psci-suspend-param = <0x0010000>; 275 local-timer-stop; 276 entry-latency-us = <400>; 277 exit-latency-us = <500>; 278 min-residency-us = <4000>; 279 }; 280 281 CPU_SLEEP_1: cpu-sleep-1 { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x0010000>; 284 local-timer-stop; 285 entry-latency-us = <700>; 286 exit-latency-us = <700>; 287 min-residency-us = <5000>; 288 }; 289 }; 290 }; 291 292 extal_clk: extal { 293 compatible = "fixed-clock"; 294 #clock-cells = <0>; 295 /* This value must be overridden by the board */ 296 clock-frequency = <0>; 297 }; 298 299 extalr_clk: extalr { 300 compatible = "fixed-clock"; 301 #clock-cells = <0>; 302 /* This value must be overridden by the board */ 303 clock-frequency = <0>; 304 }; 305 306 /* External PCIe clock - can be overridden by the board */ 307 pcie_bus_clk: pcie_bus { 308 compatible = "fixed-clock"; 309 #clock-cells = <0>; 310 clock-frequency = <0>; 311 }; 312 313 pmu_a53 { 314 compatible = "arm,cortex-a53-pmu"; 315 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 316 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 317 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 318 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-affinity = <&a53_0>, 320 <&a53_1>, 321 <&a53_2>, 322 <&a53_3>; 323 }; 324 325 pmu_a57 { 326 compatible = "arm,cortex-a57-pmu"; 327 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 328 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 329 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 330 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-affinity = <&a57_0>, 332 <&a57_1>, 333 <&a57_2>, 334 <&a57_3>; 335 }; 336 337 psci { 338 compatible = "arm,psci-1.0", "arm,psci-0.2"; 339 method = "smc"; 340 }; 341 342 /* External SCIF clock - to be overridden by boards that provide it */ 343 scif_clk: scif { 344 compatible = "fixed-clock"; 345 #clock-cells = <0>; 346 clock-frequency = <0>; 347 }; 348 349 soc: soc { 350 compatible = "simple-bus"; 351 interrupt-parent = <&gic>; 352 353 #address-cells = <2>; 354 #size-cells = <2>; 355 ranges; 356 357 rwdt: watchdog@e6020000 { 358 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; 359 reg = <0 0xe6020000 0 0x0c>; 360 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&cpg CPG_MOD 402>; 362 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 363 resets = <&cpg 402>; 364 status = "disabled"; 365 }; 366 367 gpio0: gpio@e6050000 { 368 compatible = "renesas,gpio-r8a7795", 369 "renesas,rcar-gen3-gpio"; 370 reg = <0 0xe6050000 0 0x50>; 371 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 372 #gpio-cells = <2>; 373 gpio-controller; 374 gpio-ranges = <&pfc 0 0 16>; 375 #interrupt-cells = <2>; 376 interrupt-controller; 377 clocks = <&cpg CPG_MOD 912>; 378 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 379 resets = <&cpg 912>; 380 }; 381 382 gpio1: gpio@e6051000 { 383 compatible = "renesas,gpio-r8a7795", 384 "renesas,rcar-gen3-gpio"; 385 reg = <0 0xe6051000 0 0x50>; 386 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 387 #gpio-cells = <2>; 388 gpio-controller; 389 gpio-ranges = <&pfc 0 32 29>; 390 #interrupt-cells = <2>; 391 interrupt-controller; 392 clocks = <&cpg CPG_MOD 911>; 393 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 394 resets = <&cpg 911>; 395 }; 396 397 gpio2: gpio@e6052000 { 398 compatible = "renesas,gpio-r8a7795", 399 "renesas,rcar-gen3-gpio"; 400 reg = <0 0xe6052000 0 0x50>; 401 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 402 #gpio-cells = <2>; 403 gpio-controller; 404 gpio-ranges = <&pfc 0 64 15>; 405 #interrupt-cells = <2>; 406 interrupt-controller; 407 clocks = <&cpg CPG_MOD 910>; 408 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 409 resets = <&cpg 910>; 410 }; 411 412 gpio3: gpio@e6053000 { 413 compatible = "renesas,gpio-r8a7795", 414 "renesas,rcar-gen3-gpio"; 415 reg = <0 0xe6053000 0 0x50>; 416 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 417 #gpio-cells = <2>; 418 gpio-controller; 419 gpio-ranges = <&pfc 0 96 16>; 420 #interrupt-cells = <2>; 421 interrupt-controller; 422 clocks = <&cpg CPG_MOD 909>; 423 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 424 resets = <&cpg 909>; 425 }; 426 427 gpio4: gpio@e6054000 { 428 compatible = "renesas,gpio-r8a7795", 429 "renesas,rcar-gen3-gpio"; 430 reg = <0 0xe6054000 0 0x50>; 431 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 432 #gpio-cells = <2>; 433 gpio-controller; 434 gpio-ranges = <&pfc 0 128 18>; 435 #interrupt-cells = <2>; 436 interrupt-controller; 437 clocks = <&cpg CPG_MOD 908>; 438 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 439 resets = <&cpg 908>; 440 }; 441 442 gpio5: gpio@e6055000 { 443 compatible = "renesas,gpio-r8a7795", 444 "renesas,rcar-gen3-gpio"; 445 reg = <0 0xe6055000 0 0x50>; 446 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 447 #gpio-cells = <2>; 448 gpio-controller; 449 gpio-ranges = <&pfc 0 160 26>; 450 #interrupt-cells = <2>; 451 interrupt-controller; 452 clocks = <&cpg CPG_MOD 907>; 453 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 454 resets = <&cpg 907>; 455 }; 456 457 gpio6: gpio@e6055400 { 458 compatible = "renesas,gpio-r8a7795", 459 "renesas,rcar-gen3-gpio"; 460 reg = <0 0xe6055400 0 0x50>; 461 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 462 #gpio-cells = <2>; 463 gpio-controller; 464 gpio-ranges = <&pfc 0 192 32>; 465 #interrupt-cells = <2>; 466 interrupt-controller; 467 clocks = <&cpg CPG_MOD 906>; 468 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 469 resets = <&cpg 906>; 470 }; 471 472 gpio7: gpio@e6055800 { 473 compatible = "renesas,gpio-r8a7795", 474 "renesas,rcar-gen3-gpio"; 475 reg = <0 0xe6055800 0 0x50>; 476 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 477 #gpio-cells = <2>; 478 gpio-controller; 479 gpio-ranges = <&pfc 0 224 4>; 480 #interrupt-cells = <2>; 481 interrupt-controller; 482 clocks = <&cpg CPG_MOD 905>; 483 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 484 resets = <&cpg 905>; 485 }; 486 487 pfc: pinctrl@e6060000 { 488 compatible = "renesas,pfc-r8a7795"; 489 reg = <0 0xe6060000 0 0x50c>; 490 }; 491 492 cmt0: timer@e60f0000 { 493 compatible = "renesas,r8a7795-cmt0", 494 "renesas,rcar-gen3-cmt0"; 495 reg = <0 0xe60f0000 0 0x1004>; 496 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cpg CPG_MOD 303>; 499 clock-names = "fck"; 500 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 501 resets = <&cpg 303>; 502 status = "disabled"; 503 }; 504 505 cmt1: timer@e6130000 { 506 compatible = "renesas,r8a7795-cmt1", 507 "renesas,rcar-gen3-cmt1"; 508 reg = <0 0xe6130000 0 0x1004>; 509 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cpg CPG_MOD 302>; 518 clock-names = "fck"; 519 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 520 resets = <&cpg 302>; 521 status = "disabled"; 522 }; 523 524 cmt2: timer@e6140000 { 525 compatible = "renesas,r8a7795-cmt1", 526 "renesas,rcar-gen3-cmt1"; 527 reg = <0 0xe6140000 0 0x1004>; 528 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&cpg CPG_MOD 301>; 537 clock-names = "fck"; 538 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 539 resets = <&cpg 301>; 540 status = "disabled"; 541 }; 542 543 cmt3: timer@e6148000 { 544 compatible = "renesas,r8a7795-cmt1", 545 "renesas,rcar-gen3-cmt1"; 546 reg = <0 0xe6148000 0 0x1004>; 547 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 300>; 556 clock-names = "fck"; 557 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 558 resets = <&cpg 300>; 559 status = "disabled"; 560 }; 561 562 cpg: clock-controller@e6150000 { 563 compatible = "renesas,r8a7795-cpg-mssr"; 564 reg = <0 0xe6150000 0 0x1000>; 565 clocks = <&extal_clk>, <&extalr_clk>; 566 clock-names = "extal", "extalr"; 567 #clock-cells = <2>; 568 #power-domain-cells = <0>; 569 #reset-cells = <1>; 570 }; 571 572 rst: reset-controller@e6160000 { 573 compatible = "renesas,r8a7795-rst"; 574 reg = <0 0xe6160000 0 0x0200>; 575 }; 576 577 sysc: system-controller@e6180000 { 578 compatible = "renesas,r8a7795-sysc"; 579 reg = <0 0xe6180000 0 0x0400>; 580 #power-domain-cells = <1>; 581 }; 582 583 tsc: thermal@e6198000 { 584 compatible = "renesas,r8a7795-thermal"; 585 reg = <0 0xe6198000 0 0x100>, 586 <0 0xe61a0000 0 0x100>, 587 <0 0xe61a8000 0 0x100>; 588 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cpg CPG_MOD 522>; 592 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 593 resets = <&cpg 522>; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 intc_ex: interrupt-controller@e61c0000 { 598 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; 599 #interrupt-cells = <2>; 600 interrupt-controller; 601 reg = <0 0xe61c0000 0 0x200>; 602 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&cpg CPG_MOD 407>; 609 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 610 resets = <&cpg 407>; 611 }; 612 613 tmu0: timer@e61e0000 { 614 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 615 reg = <0 0xe61e0000 0 0x30>; 616 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cpg CPG_MOD 125>; 620 clock-names = "fck"; 621 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 622 resets = <&cpg 125>; 623 status = "disabled"; 624 }; 625 626 tmu1: timer@e6fc0000 { 627 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 628 reg = <0 0xe6fc0000 0 0x30>; 629 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 124>; 633 clock-names = "fck"; 634 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 635 resets = <&cpg 124>; 636 status = "disabled"; 637 }; 638 639 tmu2: timer@e6fd0000 { 640 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 641 reg = <0 0xe6fd0000 0 0x30>; 642 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cpg CPG_MOD 123>; 646 clock-names = "fck"; 647 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 648 resets = <&cpg 123>; 649 status = "disabled"; 650 }; 651 652 tmu3: timer@e6fe0000 { 653 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 654 reg = <0 0xe6fe0000 0 0x30>; 655 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 122>; 659 clock-names = "fck"; 660 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 661 resets = <&cpg 122>; 662 status = "disabled"; 663 }; 664 665 tmu4: timer@ffc00000 { 666 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 667 reg = <0 0xffc00000 0 0x30>; 668 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 121>; 672 clock-names = "fck"; 673 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 674 resets = <&cpg 121>; 675 status = "disabled"; 676 }; 677 678 i2c0: i2c@e6500000 { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 compatible = "renesas,i2c-r8a7795", 682 "renesas,rcar-gen3-i2c"; 683 reg = <0 0xe6500000 0 0x40>; 684 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cpg CPG_MOD 931>; 686 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 687 resets = <&cpg 931>; 688 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 689 <&dmac2 0x91>, <&dmac2 0x90>; 690 dma-names = "tx", "rx", "tx", "rx"; 691 i2c-scl-internal-delay-ns = <110>; 692 status = "disabled"; 693 }; 694 695 i2c1: i2c@e6508000 { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 compatible = "renesas,i2c-r8a7795", 699 "renesas,rcar-gen3-i2c"; 700 reg = <0 0xe6508000 0 0x40>; 701 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cpg CPG_MOD 930>; 703 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 704 resets = <&cpg 930>; 705 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 706 <&dmac2 0x93>, <&dmac2 0x92>; 707 dma-names = "tx", "rx", "tx", "rx"; 708 i2c-scl-internal-delay-ns = <6>; 709 status = "disabled"; 710 }; 711 712 i2c2: i2c@e6510000 { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 compatible = "renesas,i2c-r8a7795", 716 "renesas,rcar-gen3-i2c"; 717 reg = <0 0xe6510000 0 0x40>; 718 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cpg CPG_MOD 929>; 720 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 721 resets = <&cpg 929>; 722 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 723 <&dmac2 0x95>, <&dmac2 0x94>; 724 dma-names = "tx", "rx", "tx", "rx"; 725 i2c-scl-internal-delay-ns = <6>; 726 status = "disabled"; 727 }; 728 729 i2c3: i2c@e66d0000 { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 compatible = "renesas,i2c-r8a7795", 733 "renesas,rcar-gen3-i2c"; 734 reg = <0 0xe66d0000 0 0x40>; 735 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD 928>; 737 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 738 resets = <&cpg 928>; 739 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 740 dma-names = "tx", "rx"; 741 i2c-scl-internal-delay-ns = <110>; 742 status = "disabled"; 743 }; 744 745 i2c4: i2c@e66d8000 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 compatible = "renesas,i2c-r8a7795", 749 "renesas,rcar-gen3-i2c"; 750 reg = <0 0xe66d8000 0 0x40>; 751 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD 927>; 753 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 754 resets = <&cpg 927>; 755 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 756 dma-names = "tx", "rx"; 757 i2c-scl-internal-delay-ns = <110>; 758 status = "disabled"; 759 }; 760 761 i2c5: i2c@e66e0000 { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 compatible = "renesas,i2c-r8a7795", 765 "renesas,rcar-gen3-i2c"; 766 reg = <0 0xe66e0000 0 0x40>; 767 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cpg CPG_MOD 919>; 769 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 770 resets = <&cpg 919>; 771 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 772 dma-names = "tx", "rx"; 773 i2c-scl-internal-delay-ns = <110>; 774 status = "disabled"; 775 }; 776 777 i2c6: i2c@e66e8000 { 778 #address-cells = <1>; 779 #size-cells = <0>; 780 compatible = "renesas,i2c-r8a7795", 781 "renesas,rcar-gen3-i2c"; 782 reg = <0 0xe66e8000 0 0x40>; 783 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&cpg CPG_MOD 918>; 785 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 786 resets = <&cpg 918>; 787 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 788 dma-names = "tx", "rx"; 789 i2c-scl-internal-delay-ns = <6>; 790 status = "disabled"; 791 }; 792 793 i2c_dvfs: i2c@e60b0000 { 794 #address-cells = <1>; 795 #size-cells = <0>; 796 compatible = "renesas,iic-r8a7795", 797 "renesas,rcar-gen3-iic", 798 "renesas,rmobile-iic"; 799 reg = <0 0xe60b0000 0 0x425>; 800 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cpg CPG_MOD 926>; 802 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 803 resets = <&cpg 926>; 804 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 805 dma-names = "tx", "rx"; 806 status = "disabled"; 807 }; 808 809 hscif0: serial@e6540000 { 810 compatible = "renesas,hscif-r8a7795", 811 "renesas,rcar-gen3-hscif", 812 "renesas,hscif"; 813 reg = <0 0xe6540000 0 96>; 814 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&cpg CPG_MOD 520>, 816 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 817 <&scif_clk>; 818 clock-names = "fck", "brg_int", "scif_clk"; 819 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 820 <&dmac2 0x31>, <&dmac2 0x30>; 821 dma-names = "tx", "rx", "tx", "rx"; 822 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 823 resets = <&cpg 520>; 824 status = "disabled"; 825 }; 826 827 hscif1: serial@e6550000 { 828 compatible = "renesas,hscif-r8a7795", 829 "renesas,rcar-gen3-hscif", 830 "renesas,hscif"; 831 reg = <0 0xe6550000 0 96>; 832 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&cpg CPG_MOD 519>, 834 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 835 <&scif_clk>; 836 clock-names = "fck", "brg_int", "scif_clk"; 837 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 838 <&dmac2 0x33>, <&dmac2 0x32>; 839 dma-names = "tx", "rx", "tx", "rx"; 840 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 841 resets = <&cpg 519>; 842 status = "disabled"; 843 }; 844 845 hscif2: serial@e6560000 { 846 compatible = "renesas,hscif-r8a7795", 847 "renesas,rcar-gen3-hscif", 848 "renesas,hscif"; 849 reg = <0 0xe6560000 0 96>; 850 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cpg CPG_MOD 518>, 852 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 853 <&scif_clk>; 854 clock-names = "fck", "brg_int", "scif_clk"; 855 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 856 <&dmac2 0x35>, <&dmac2 0x34>; 857 dma-names = "tx", "rx", "tx", "rx"; 858 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 859 resets = <&cpg 518>; 860 status = "disabled"; 861 }; 862 863 hscif3: serial@e66a0000 { 864 compatible = "renesas,hscif-r8a7795", 865 "renesas,rcar-gen3-hscif", 866 "renesas,hscif"; 867 reg = <0 0xe66a0000 0 96>; 868 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cpg CPG_MOD 517>, 870 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 871 <&scif_clk>; 872 clock-names = "fck", "brg_int", "scif_clk"; 873 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 874 dma-names = "tx", "rx"; 875 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 876 resets = <&cpg 517>; 877 status = "disabled"; 878 }; 879 880 hscif4: serial@e66b0000 { 881 compatible = "renesas,hscif-r8a7795", 882 "renesas,rcar-gen3-hscif", 883 "renesas,hscif"; 884 reg = <0 0xe66b0000 0 96>; 885 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cpg CPG_MOD 516>, 887 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 888 <&scif_clk>; 889 clock-names = "fck", "brg_int", "scif_clk"; 890 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 891 dma-names = "tx", "rx"; 892 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 893 resets = <&cpg 516>; 894 status = "disabled"; 895 }; 896 897 hsusb: usb@e6590000 { 898 compatible = "renesas,usbhs-r8a7795", 899 "renesas,rcar-gen3-usbhs"; 900 reg = <0 0xe6590000 0 0x200>; 901 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 903 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 904 <&usb_dmac1 0>, <&usb_dmac1 1>; 905 dma-names = "ch0", "ch1", "ch2", "ch3"; 906 renesas,buswait = <11>; 907 phys = <&usb2_phy0 3>; 908 phy-names = "usb"; 909 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 910 resets = <&cpg 704>, <&cpg 703>; 911 status = "disabled"; 912 }; 913 914 hsusb3: usb@e659c000 { 915 compatible = "renesas,usbhs-r8a7795", 916 "renesas,rcar-gen3-usbhs"; 917 reg = <0 0xe659c000 0 0x200>; 918 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; 920 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, 921 <&usb_dmac3 0>, <&usb_dmac3 1>; 922 dma-names = "ch0", "ch1", "ch2", "ch3"; 923 renesas,buswait = <11>; 924 phys = <&usb2_phy3 3>; 925 phy-names = "usb"; 926 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 927 resets = <&cpg 705>, <&cpg 700>; 928 status = "disabled"; 929 }; 930 931 usb_dmac0: dma-controller@e65a0000 { 932 compatible = "renesas,r8a7795-usb-dmac", 933 "renesas,usb-dmac"; 934 reg = <0 0xe65a0000 0 0x100>; 935 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "ch0", "ch1"; 938 clocks = <&cpg CPG_MOD 330>; 939 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 940 resets = <&cpg 330>; 941 #dma-cells = <1>; 942 dma-channels = <2>; 943 }; 944 945 usb_dmac1: dma-controller@e65b0000 { 946 compatible = "renesas,r8a7795-usb-dmac", 947 "renesas,usb-dmac"; 948 reg = <0 0xe65b0000 0 0x100>; 949 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "ch0", "ch1"; 952 clocks = <&cpg CPG_MOD 331>; 953 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 954 resets = <&cpg 331>; 955 #dma-cells = <1>; 956 dma-channels = <2>; 957 }; 958 959 usb_dmac2: dma-controller@e6460000 { 960 compatible = "renesas,r8a7795-usb-dmac", 961 "renesas,usb-dmac"; 962 reg = <0 0xe6460000 0 0x100>; 963 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 965 interrupt-names = "ch0", "ch1"; 966 clocks = <&cpg CPG_MOD 326>; 967 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 968 resets = <&cpg 326>; 969 #dma-cells = <1>; 970 dma-channels = <2>; 971 }; 972 973 usb_dmac3: dma-controller@e6470000 { 974 compatible = "renesas,r8a7795-usb-dmac", 975 "renesas,usb-dmac"; 976 reg = <0 0xe6470000 0 0x100>; 977 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 979 interrupt-names = "ch0", "ch1"; 980 clocks = <&cpg CPG_MOD 329>; 981 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 982 resets = <&cpg 329>; 983 #dma-cells = <1>; 984 dma-channels = <2>; 985 }; 986 987 usb3_phy0: usb-phy@e65ee000 { 988 compatible = "renesas,r8a7795-usb3-phy", 989 "renesas,rcar-gen3-usb3-phy"; 990 reg = <0 0xe65ee000 0 0x90>; 991 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 992 <&usb_extal_clk>; 993 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 994 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 995 resets = <&cpg 328>; 996 #phy-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 arm_cc630p: crypto@e6601000 { 1001 compatible = "arm,cryptocell-630p-ree"; 1002 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1003 reg = <0x0 0xe6601000 0 0x1000>; 1004 clocks = <&cpg CPG_MOD 229>; 1005 resets = <&cpg 229>; 1006 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1007 }; 1008 1009 dmac0: dma-controller@e6700000 { 1010 compatible = "renesas,dmac-r8a7795", 1011 "renesas,rcar-dmac"; 1012 reg = <0 0xe6700000 0 0x10000>; 1013 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "error", 1031 "ch0", "ch1", "ch2", "ch3", 1032 "ch4", "ch5", "ch6", "ch7", 1033 "ch8", "ch9", "ch10", "ch11", 1034 "ch12", "ch13", "ch14", "ch15"; 1035 clocks = <&cpg CPG_MOD 219>; 1036 clock-names = "fck"; 1037 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1038 resets = <&cpg 219>; 1039 #dma-cells = <1>; 1040 dma-channels = <16>; 1041 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1042 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1043 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1044 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1045 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1046 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1047 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1048 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1049 }; 1050 1051 dmac1: dma-controller@e7300000 { 1052 compatible = "renesas,dmac-r8a7795", 1053 "renesas,rcar-dmac"; 1054 reg = <0 0xe7300000 0 0x10000>; 1055 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1072 interrupt-names = "error", 1073 "ch0", "ch1", "ch2", "ch3", 1074 "ch4", "ch5", "ch6", "ch7", 1075 "ch8", "ch9", "ch10", "ch11", 1076 "ch12", "ch13", "ch14", "ch15"; 1077 clocks = <&cpg CPG_MOD 218>; 1078 clock-names = "fck"; 1079 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1080 resets = <&cpg 218>; 1081 #dma-cells = <1>; 1082 dma-channels = <16>; 1083 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1084 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1085 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1086 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1087 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1088 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1089 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1090 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1091 }; 1092 1093 dmac2: dma-controller@e7310000 { 1094 compatible = "renesas,dmac-r8a7795", 1095 "renesas,rcar-dmac"; 1096 reg = <0 0xe7310000 0 0x10000>; 1097 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1114 interrupt-names = "error", 1115 "ch0", "ch1", "ch2", "ch3", 1116 "ch4", "ch5", "ch6", "ch7", 1117 "ch8", "ch9", "ch10", "ch11", 1118 "ch12", "ch13", "ch14", "ch15"; 1119 clocks = <&cpg CPG_MOD 217>; 1120 clock-names = "fck"; 1121 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1122 resets = <&cpg 217>; 1123 #dma-cells = <1>; 1124 dma-channels = <16>; 1125 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1126 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1127 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1128 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1129 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1130 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1131 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1132 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1133 }; 1134 1135 ipmmu_ds0: iommu@e6740000 { 1136 compatible = "renesas,ipmmu-r8a7795"; 1137 reg = <0 0xe6740000 0 0x1000>; 1138 renesas,ipmmu-main = <&ipmmu_mm 0>; 1139 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1140 #iommu-cells = <1>; 1141 }; 1142 1143 ipmmu_ds1: iommu@e7740000 { 1144 compatible = "renesas,ipmmu-r8a7795"; 1145 reg = <0 0xe7740000 0 0x1000>; 1146 renesas,ipmmu-main = <&ipmmu_mm 1>; 1147 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1148 #iommu-cells = <1>; 1149 }; 1150 1151 ipmmu_hc: iommu@e6570000 { 1152 compatible = "renesas,ipmmu-r8a7795"; 1153 reg = <0 0xe6570000 0 0x1000>; 1154 renesas,ipmmu-main = <&ipmmu_mm 2>; 1155 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1156 #iommu-cells = <1>; 1157 }; 1158 1159 ipmmu_ir: iommu@ff8b0000 { 1160 compatible = "renesas,ipmmu-r8a7795"; 1161 reg = <0 0xff8b0000 0 0x1000>; 1162 renesas,ipmmu-main = <&ipmmu_mm 3>; 1163 power-domains = <&sysc R8A7795_PD_A3IR>; 1164 #iommu-cells = <1>; 1165 }; 1166 1167 ipmmu_mm: iommu@e67b0000 { 1168 compatible = "renesas,ipmmu-r8a7795"; 1169 reg = <0 0xe67b0000 0 0x1000>; 1170 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1172 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1173 #iommu-cells = <1>; 1174 }; 1175 1176 ipmmu_mp0: iommu@ec670000 { 1177 compatible = "renesas,ipmmu-r8a7795"; 1178 reg = <0 0xec670000 0 0x1000>; 1179 renesas,ipmmu-main = <&ipmmu_mm 4>; 1180 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1181 #iommu-cells = <1>; 1182 }; 1183 1184 ipmmu_pv0: iommu@fd800000 { 1185 compatible = "renesas,ipmmu-r8a7795"; 1186 reg = <0 0xfd800000 0 0x1000>; 1187 renesas,ipmmu-main = <&ipmmu_mm 6>; 1188 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1189 #iommu-cells = <1>; 1190 }; 1191 1192 ipmmu_pv1: iommu@fd950000 { 1193 compatible = "renesas,ipmmu-r8a7795"; 1194 reg = <0 0xfd950000 0 0x1000>; 1195 renesas,ipmmu-main = <&ipmmu_mm 7>; 1196 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1197 #iommu-cells = <1>; 1198 }; 1199 1200 ipmmu_pv2: iommu@fd960000 { 1201 compatible = "renesas,ipmmu-r8a7795"; 1202 reg = <0 0xfd960000 0 0x1000>; 1203 renesas,ipmmu-main = <&ipmmu_mm 8>; 1204 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1205 #iommu-cells = <1>; 1206 }; 1207 1208 ipmmu_pv3: iommu@fd970000 { 1209 compatible = "renesas,ipmmu-r8a7795"; 1210 reg = <0 0xfd970000 0 0x1000>; 1211 renesas,ipmmu-main = <&ipmmu_mm 9>; 1212 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1213 #iommu-cells = <1>; 1214 }; 1215 1216 ipmmu_rt: iommu@ffc80000 { 1217 compatible = "renesas,ipmmu-r8a7795"; 1218 reg = <0 0xffc80000 0 0x1000>; 1219 renesas,ipmmu-main = <&ipmmu_mm 10>; 1220 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1221 #iommu-cells = <1>; 1222 }; 1223 1224 ipmmu_vc0: iommu@fe6b0000 { 1225 compatible = "renesas,ipmmu-r8a7795"; 1226 reg = <0 0xfe6b0000 0 0x1000>; 1227 renesas,ipmmu-main = <&ipmmu_mm 12>; 1228 power-domains = <&sysc R8A7795_PD_A3VC>; 1229 #iommu-cells = <1>; 1230 }; 1231 1232 ipmmu_vc1: iommu@fe6f0000 { 1233 compatible = "renesas,ipmmu-r8a7795"; 1234 reg = <0 0xfe6f0000 0 0x1000>; 1235 renesas,ipmmu-main = <&ipmmu_mm 13>; 1236 power-domains = <&sysc R8A7795_PD_A3VC>; 1237 #iommu-cells = <1>; 1238 }; 1239 1240 ipmmu_vi0: iommu@febd0000 { 1241 compatible = "renesas,ipmmu-r8a7795"; 1242 reg = <0 0xfebd0000 0 0x1000>; 1243 renesas,ipmmu-main = <&ipmmu_mm 14>; 1244 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1245 #iommu-cells = <1>; 1246 }; 1247 1248 ipmmu_vi1: iommu@febe0000 { 1249 compatible = "renesas,ipmmu-r8a7795"; 1250 reg = <0 0xfebe0000 0 0x1000>; 1251 renesas,ipmmu-main = <&ipmmu_mm 15>; 1252 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1253 #iommu-cells = <1>; 1254 }; 1255 1256 ipmmu_vp0: iommu@fe990000 { 1257 compatible = "renesas,ipmmu-r8a7795"; 1258 reg = <0 0xfe990000 0 0x1000>; 1259 renesas,ipmmu-main = <&ipmmu_mm 16>; 1260 power-domains = <&sysc R8A7795_PD_A3VP>; 1261 #iommu-cells = <1>; 1262 }; 1263 1264 ipmmu_vp1: iommu@fe980000 { 1265 compatible = "renesas,ipmmu-r8a7795"; 1266 reg = <0 0xfe980000 0 0x1000>; 1267 renesas,ipmmu-main = <&ipmmu_mm 17>; 1268 power-domains = <&sysc R8A7795_PD_A3VP>; 1269 #iommu-cells = <1>; 1270 }; 1271 1272 avb: ethernet@e6800000 { 1273 compatible = "renesas,etheravb-r8a7795", 1274 "renesas,etheravb-rcar-gen3"; 1275 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1276 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1301 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1302 "ch4", "ch5", "ch6", "ch7", 1303 "ch8", "ch9", "ch10", "ch11", 1304 "ch12", "ch13", "ch14", "ch15", 1305 "ch16", "ch17", "ch18", "ch19", 1306 "ch20", "ch21", "ch22", "ch23", 1307 "ch24"; 1308 clocks = <&cpg CPG_MOD 812>; 1309 clock-names = "fck"; 1310 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1311 resets = <&cpg 812>; 1312 phy-mode = "rgmii"; 1313 rx-internal-delay-ps = <0>; 1314 tx-internal-delay-ps = <0>; 1315 iommus = <&ipmmu_ds0 16>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 can0: can@e6c30000 { 1322 compatible = "renesas,can-r8a7795", 1323 "renesas,rcar-gen3-can"; 1324 reg = <0 0xe6c30000 0 0x1000>; 1325 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cpg CPG_MOD 916>, 1327 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1328 <&can_clk>; 1329 clock-names = "clkp1", "clkp2", "can_clk"; 1330 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1331 assigned-clock-rates = <40000000>; 1332 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1333 resets = <&cpg 916>; 1334 status = "disabled"; 1335 }; 1336 1337 can1: can@e6c38000 { 1338 compatible = "renesas,can-r8a7795", 1339 "renesas,rcar-gen3-can"; 1340 reg = <0 0xe6c38000 0 0x1000>; 1341 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cpg CPG_MOD 915>, 1343 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1344 <&can_clk>; 1345 clock-names = "clkp1", "clkp2", "can_clk"; 1346 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1347 assigned-clock-rates = <40000000>; 1348 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1349 resets = <&cpg 915>; 1350 status = "disabled"; 1351 }; 1352 1353 canfd: can@e66c0000 { 1354 compatible = "renesas,r8a7795-canfd", 1355 "renesas,rcar-gen3-canfd"; 1356 reg = <0 0xe66c0000 0 0x8000>; 1357 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1359 interrupt-names = "ch_int", "g_int"; 1360 clocks = <&cpg CPG_MOD 914>, 1361 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1362 <&can_clk>; 1363 clock-names = "fck", "canfd", "can_clk"; 1364 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1365 assigned-clock-rates = <40000000>; 1366 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1367 resets = <&cpg 914>; 1368 status = "disabled"; 1369 1370 channel0 { 1371 status = "disabled"; 1372 }; 1373 1374 channel1 { 1375 status = "disabled"; 1376 }; 1377 }; 1378 1379 pwm0: pwm@e6e30000 { 1380 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1381 reg = <0 0xe6e30000 0 0x8>; 1382 clocks = <&cpg CPG_MOD 523>; 1383 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1384 resets = <&cpg 523>; 1385 #pwm-cells = <2>; 1386 status = "disabled"; 1387 }; 1388 1389 pwm1: pwm@e6e31000 { 1390 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1391 reg = <0 0xe6e31000 0 0x8>; 1392 clocks = <&cpg CPG_MOD 523>; 1393 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1394 resets = <&cpg 523>; 1395 #pwm-cells = <2>; 1396 status = "disabled"; 1397 }; 1398 1399 pwm2: pwm@e6e32000 { 1400 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1401 reg = <0 0xe6e32000 0 0x8>; 1402 clocks = <&cpg CPG_MOD 523>; 1403 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1404 resets = <&cpg 523>; 1405 #pwm-cells = <2>; 1406 status = "disabled"; 1407 }; 1408 1409 pwm3: pwm@e6e33000 { 1410 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1411 reg = <0 0xe6e33000 0 0x8>; 1412 clocks = <&cpg CPG_MOD 523>; 1413 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1414 resets = <&cpg 523>; 1415 #pwm-cells = <2>; 1416 status = "disabled"; 1417 }; 1418 1419 pwm4: pwm@e6e34000 { 1420 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1421 reg = <0 0xe6e34000 0 0x8>; 1422 clocks = <&cpg CPG_MOD 523>; 1423 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1424 resets = <&cpg 523>; 1425 #pwm-cells = <2>; 1426 status = "disabled"; 1427 }; 1428 1429 pwm5: pwm@e6e35000 { 1430 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1431 reg = <0 0xe6e35000 0 0x8>; 1432 clocks = <&cpg CPG_MOD 523>; 1433 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1434 resets = <&cpg 523>; 1435 #pwm-cells = <2>; 1436 status = "disabled"; 1437 }; 1438 1439 pwm6: pwm@e6e36000 { 1440 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1441 reg = <0 0xe6e36000 0 0x8>; 1442 clocks = <&cpg CPG_MOD 523>; 1443 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1444 resets = <&cpg 523>; 1445 #pwm-cells = <2>; 1446 status = "disabled"; 1447 }; 1448 1449 scif0: serial@e6e60000 { 1450 compatible = "renesas,scif-r8a7795", 1451 "renesas,rcar-gen3-scif", "renesas,scif"; 1452 reg = <0 0xe6e60000 0 64>; 1453 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1454 clocks = <&cpg CPG_MOD 207>, 1455 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1456 <&scif_clk>; 1457 clock-names = "fck", "brg_int", "scif_clk"; 1458 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1459 <&dmac2 0x51>, <&dmac2 0x50>; 1460 dma-names = "tx", "rx", "tx", "rx"; 1461 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1462 resets = <&cpg 207>; 1463 status = "disabled"; 1464 }; 1465 1466 scif1: serial@e6e68000 { 1467 compatible = "renesas,scif-r8a7795", 1468 "renesas,rcar-gen3-scif", "renesas,scif"; 1469 reg = <0 0xe6e68000 0 64>; 1470 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&cpg CPG_MOD 206>, 1472 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1473 <&scif_clk>; 1474 clock-names = "fck", "brg_int", "scif_clk"; 1475 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1476 <&dmac2 0x53>, <&dmac2 0x52>; 1477 dma-names = "tx", "rx", "tx", "rx"; 1478 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1479 resets = <&cpg 206>; 1480 status = "disabled"; 1481 }; 1482 1483 scif2: serial@e6e88000 { 1484 compatible = "renesas,scif-r8a7795", 1485 "renesas,rcar-gen3-scif", "renesas,scif"; 1486 reg = <0 0xe6e88000 0 64>; 1487 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&cpg CPG_MOD 310>, 1489 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1490 <&scif_clk>; 1491 clock-names = "fck", "brg_int", "scif_clk"; 1492 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1493 <&dmac2 0x13>, <&dmac2 0x12>; 1494 dma-names = "tx", "rx", "tx", "rx"; 1495 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1496 resets = <&cpg 310>; 1497 status = "disabled"; 1498 }; 1499 1500 scif3: serial@e6c50000 { 1501 compatible = "renesas,scif-r8a7795", 1502 "renesas,rcar-gen3-scif", "renesas,scif"; 1503 reg = <0 0xe6c50000 0 64>; 1504 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1505 clocks = <&cpg CPG_MOD 204>, 1506 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1507 <&scif_clk>; 1508 clock-names = "fck", "brg_int", "scif_clk"; 1509 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1510 dma-names = "tx", "rx"; 1511 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1512 resets = <&cpg 204>; 1513 status = "disabled"; 1514 }; 1515 1516 scif4: serial@e6c40000 { 1517 compatible = "renesas,scif-r8a7795", 1518 "renesas,rcar-gen3-scif", "renesas,scif"; 1519 reg = <0 0xe6c40000 0 64>; 1520 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&cpg CPG_MOD 203>, 1522 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1523 <&scif_clk>; 1524 clock-names = "fck", "brg_int", "scif_clk"; 1525 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1526 dma-names = "tx", "rx"; 1527 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1528 resets = <&cpg 203>; 1529 status = "disabled"; 1530 }; 1531 1532 scif5: serial@e6f30000 { 1533 compatible = "renesas,scif-r8a7795", 1534 "renesas,rcar-gen3-scif", "renesas,scif"; 1535 reg = <0 0xe6f30000 0 64>; 1536 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1537 clocks = <&cpg CPG_MOD 202>, 1538 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1539 <&scif_clk>; 1540 clock-names = "fck", "brg_int", "scif_clk"; 1541 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1542 <&dmac2 0x5b>, <&dmac2 0x5a>; 1543 dma-names = "tx", "rx", "tx", "rx"; 1544 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1545 resets = <&cpg 202>; 1546 status = "disabled"; 1547 }; 1548 1549 tpu: pwm@e6e80000 { 1550 compatible = "renesas,tpu-r8a7795", "renesas,tpu"; 1551 reg = <0 0xe6e80000 0 0x148>; 1552 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1553 clocks = <&cpg CPG_MOD 304>; 1554 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1555 resets = <&cpg 304>; 1556 #pwm-cells = <3>; 1557 status = "disabled"; 1558 }; 1559 1560 msiof0: spi@e6e90000 { 1561 compatible = "renesas,msiof-r8a7795", 1562 "renesas,rcar-gen3-msiof"; 1563 reg = <0 0xe6e90000 0 0x0064>; 1564 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cpg CPG_MOD 211>; 1566 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1567 <&dmac2 0x41>, <&dmac2 0x40>; 1568 dma-names = "tx", "rx", "tx", "rx"; 1569 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1570 resets = <&cpg 211>; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 msiof1: spi@e6ea0000 { 1577 compatible = "renesas,msiof-r8a7795", 1578 "renesas,rcar-gen3-msiof"; 1579 reg = <0 0xe6ea0000 0 0x0064>; 1580 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1581 clocks = <&cpg CPG_MOD 210>; 1582 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1583 <&dmac2 0x43>, <&dmac2 0x42>; 1584 dma-names = "tx", "rx", "tx", "rx"; 1585 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1586 resets = <&cpg 210>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 msiof2: spi@e6c00000 { 1593 compatible = "renesas,msiof-r8a7795", 1594 "renesas,rcar-gen3-msiof"; 1595 reg = <0 0xe6c00000 0 0x0064>; 1596 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1597 clocks = <&cpg CPG_MOD 209>; 1598 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1599 dma-names = "tx", "rx"; 1600 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1601 resets = <&cpg 209>; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 msiof3: spi@e6c10000 { 1608 compatible = "renesas,msiof-r8a7795", 1609 "renesas,rcar-gen3-msiof"; 1610 reg = <0 0xe6c10000 0 0x0064>; 1611 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1612 clocks = <&cpg CPG_MOD 208>; 1613 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1614 dma-names = "tx", "rx"; 1615 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1616 resets = <&cpg 208>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 status = "disabled"; 1620 }; 1621 1622 vin0: video@e6ef0000 { 1623 compatible = "renesas,vin-r8a7795"; 1624 reg = <0 0xe6ef0000 0 0x1000>; 1625 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&cpg CPG_MOD 811>; 1627 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1628 resets = <&cpg 811>; 1629 renesas,id = <0>; 1630 status = "disabled"; 1631 1632 ports { 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 1636 port@1 { 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 1640 reg = <1>; 1641 1642 vin0csi20: endpoint@0 { 1643 reg = <0>; 1644 remote-endpoint = <&csi20vin0>; 1645 }; 1646 vin0csi40: endpoint@2 { 1647 reg = <2>; 1648 remote-endpoint = <&csi40vin0>; 1649 }; 1650 }; 1651 }; 1652 }; 1653 1654 vin1: video@e6ef1000 { 1655 compatible = "renesas,vin-r8a7795"; 1656 reg = <0 0xe6ef1000 0 0x1000>; 1657 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&cpg CPG_MOD 810>; 1659 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1660 resets = <&cpg 810>; 1661 renesas,id = <1>; 1662 status = "disabled"; 1663 1664 ports { 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 1668 port@1 { 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 1672 reg = <1>; 1673 1674 vin1csi20: endpoint@0 { 1675 reg = <0>; 1676 remote-endpoint = <&csi20vin1>; 1677 }; 1678 vin1csi40: endpoint@2 { 1679 reg = <2>; 1680 remote-endpoint = <&csi40vin1>; 1681 }; 1682 }; 1683 }; 1684 }; 1685 1686 vin2: video@e6ef2000 { 1687 compatible = "renesas,vin-r8a7795"; 1688 reg = <0 0xe6ef2000 0 0x1000>; 1689 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1690 clocks = <&cpg CPG_MOD 809>; 1691 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1692 resets = <&cpg 809>; 1693 renesas,id = <2>; 1694 status = "disabled"; 1695 1696 ports { 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 1700 port@1 { 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 1704 reg = <1>; 1705 1706 vin2csi20: endpoint@0 { 1707 reg = <0>; 1708 remote-endpoint = <&csi20vin2>; 1709 }; 1710 vin2csi40: endpoint@2 { 1711 reg = <2>; 1712 remote-endpoint = <&csi40vin2>; 1713 }; 1714 }; 1715 }; 1716 }; 1717 1718 vin3: video@e6ef3000 { 1719 compatible = "renesas,vin-r8a7795"; 1720 reg = <0 0xe6ef3000 0 0x1000>; 1721 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&cpg CPG_MOD 808>; 1723 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1724 resets = <&cpg 808>; 1725 renesas,id = <3>; 1726 status = "disabled"; 1727 1728 ports { 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 1732 port@1 { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 reg = <1>; 1737 1738 vin3csi20: endpoint@0 { 1739 reg = <0>; 1740 remote-endpoint = <&csi20vin3>; 1741 }; 1742 vin3csi40: endpoint@2 { 1743 reg = <2>; 1744 remote-endpoint = <&csi40vin3>; 1745 }; 1746 }; 1747 }; 1748 }; 1749 1750 vin4: video@e6ef4000 { 1751 compatible = "renesas,vin-r8a7795"; 1752 reg = <0 0xe6ef4000 0 0x1000>; 1753 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1754 clocks = <&cpg CPG_MOD 807>; 1755 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1756 resets = <&cpg 807>; 1757 renesas,id = <4>; 1758 status = "disabled"; 1759 1760 ports { 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 1764 port@1 { 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 reg = <1>; 1769 1770 vin4csi20: endpoint@0 { 1771 reg = <0>; 1772 remote-endpoint = <&csi20vin4>; 1773 }; 1774 vin4csi41: endpoint@3 { 1775 reg = <3>; 1776 remote-endpoint = <&csi41vin4>; 1777 }; 1778 }; 1779 }; 1780 }; 1781 1782 vin5: video@e6ef5000 { 1783 compatible = "renesas,vin-r8a7795"; 1784 reg = <0 0xe6ef5000 0 0x1000>; 1785 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1786 clocks = <&cpg CPG_MOD 806>; 1787 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1788 resets = <&cpg 806>; 1789 renesas,id = <5>; 1790 status = "disabled"; 1791 1792 ports { 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 1796 port@1 { 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 1800 reg = <1>; 1801 1802 vin5csi20: endpoint@0 { 1803 reg = <0>; 1804 remote-endpoint = <&csi20vin5>; 1805 }; 1806 vin5csi41: endpoint@3 { 1807 reg = <3>; 1808 remote-endpoint = <&csi41vin5>; 1809 }; 1810 }; 1811 }; 1812 }; 1813 1814 vin6: video@e6ef6000 { 1815 compatible = "renesas,vin-r8a7795"; 1816 reg = <0 0xe6ef6000 0 0x1000>; 1817 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1818 clocks = <&cpg CPG_MOD 805>; 1819 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1820 resets = <&cpg 805>; 1821 renesas,id = <6>; 1822 status = "disabled"; 1823 1824 ports { 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 1828 port@1 { 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 1832 reg = <1>; 1833 1834 vin6csi20: endpoint@0 { 1835 reg = <0>; 1836 remote-endpoint = <&csi20vin6>; 1837 }; 1838 vin6csi41: endpoint@3 { 1839 reg = <3>; 1840 remote-endpoint = <&csi41vin6>; 1841 }; 1842 }; 1843 }; 1844 }; 1845 1846 vin7: video@e6ef7000 { 1847 compatible = "renesas,vin-r8a7795"; 1848 reg = <0 0xe6ef7000 0 0x1000>; 1849 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1850 clocks = <&cpg CPG_MOD 804>; 1851 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1852 resets = <&cpg 804>; 1853 renesas,id = <7>; 1854 status = "disabled"; 1855 1856 ports { 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 1860 port@1 { 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 1864 reg = <1>; 1865 1866 vin7csi20: endpoint@0 { 1867 reg = <0>; 1868 remote-endpoint = <&csi20vin7>; 1869 }; 1870 vin7csi41: endpoint@3 { 1871 reg = <3>; 1872 remote-endpoint = <&csi41vin7>; 1873 }; 1874 }; 1875 }; 1876 }; 1877 1878 drif00: rif@e6f40000 { 1879 compatible = "renesas,r8a7795-drif", 1880 "renesas,rcar-gen3-drif"; 1881 reg = <0 0xe6f40000 0 0x64>; 1882 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&cpg CPG_MOD 515>; 1884 clock-names = "fck"; 1885 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 1886 dma-names = "rx", "rx"; 1887 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1888 resets = <&cpg 515>; 1889 renesas,bonding = <&drif01>; 1890 status = "disabled"; 1891 }; 1892 1893 drif01: rif@e6f50000 { 1894 compatible = "renesas,r8a7795-drif", 1895 "renesas,rcar-gen3-drif"; 1896 reg = <0 0xe6f50000 0 0x64>; 1897 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1898 clocks = <&cpg CPG_MOD 514>; 1899 clock-names = "fck"; 1900 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 1901 dma-names = "rx", "rx"; 1902 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1903 resets = <&cpg 514>; 1904 renesas,bonding = <&drif00>; 1905 status = "disabled"; 1906 }; 1907 1908 drif10: rif@e6f60000 { 1909 compatible = "renesas,r8a7795-drif", 1910 "renesas,rcar-gen3-drif"; 1911 reg = <0 0xe6f60000 0 0x64>; 1912 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1913 clocks = <&cpg CPG_MOD 513>; 1914 clock-names = "fck"; 1915 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 1916 dma-names = "rx", "rx"; 1917 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1918 resets = <&cpg 513>; 1919 renesas,bonding = <&drif11>; 1920 status = "disabled"; 1921 }; 1922 1923 drif11: rif@e6f70000 { 1924 compatible = "renesas,r8a7795-drif", 1925 "renesas,rcar-gen3-drif"; 1926 reg = <0 0xe6f70000 0 0x64>; 1927 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&cpg CPG_MOD 512>; 1929 clock-names = "fck"; 1930 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 1931 dma-names = "rx", "rx"; 1932 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1933 resets = <&cpg 512>; 1934 renesas,bonding = <&drif10>; 1935 status = "disabled"; 1936 }; 1937 1938 drif20: rif@e6f80000 { 1939 compatible = "renesas,r8a7795-drif", 1940 "renesas,rcar-gen3-drif"; 1941 reg = <0 0xe6f80000 0 0x64>; 1942 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1943 clocks = <&cpg CPG_MOD 511>; 1944 clock-names = "fck"; 1945 dmas = <&dmac1 0x28>, <&dmac2 0x28>; 1946 dma-names = "rx", "rx"; 1947 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1948 resets = <&cpg 511>; 1949 renesas,bonding = <&drif21>; 1950 status = "disabled"; 1951 }; 1952 1953 drif21: rif@e6f90000 { 1954 compatible = "renesas,r8a7795-drif", 1955 "renesas,rcar-gen3-drif"; 1956 reg = <0 0xe6f90000 0 0x64>; 1957 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1958 clocks = <&cpg CPG_MOD 510>; 1959 clock-names = "fck"; 1960 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; 1961 dma-names = "rx", "rx"; 1962 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1963 resets = <&cpg 510>; 1964 renesas,bonding = <&drif20>; 1965 status = "disabled"; 1966 }; 1967 1968 drif30: rif@e6fa0000 { 1969 compatible = "renesas,r8a7795-drif", 1970 "renesas,rcar-gen3-drif"; 1971 reg = <0 0xe6fa0000 0 0x64>; 1972 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1973 clocks = <&cpg CPG_MOD 509>; 1974 clock-names = "fck"; 1975 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; 1976 dma-names = "rx", "rx"; 1977 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1978 resets = <&cpg 509>; 1979 renesas,bonding = <&drif31>; 1980 status = "disabled"; 1981 }; 1982 1983 drif31: rif@e6fb0000 { 1984 compatible = "renesas,r8a7795-drif", 1985 "renesas,rcar-gen3-drif"; 1986 reg = <0 0xe6fb0000 0 0x64>; 1987 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1988 clocks = <&cpg CPG_MOD 508>; 1989 clock-names = "fck"; 1990 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; 1991 dma-names = "rx", "rx"; 1992 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1993 resets = <&cpg 508>; 1994 renesas,bonding = <&drif30>; 1995 status = "disabled"; 1996 }; 1997 1998 rcar_sound: sound@ec500000 { 1999 /* 2000 * #sound-dai-cells is required if simple-card 2001 * 2002 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 2003 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 2004 */ 2005 /* 2006 * #clock-cells is required for audio_clkout0/1/2/3 2007 * 2008 * clkout : #clock-cells = <0>; <&rcar_sound>; 2009 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 2010 */ 2011 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; 2012 reg = <0 0xec500000 0 0x1000>, /* SCU */ 2013 <0 0xec5a0000 0 0x100>, /* ADG */ 2014 <0 0xec540000 0 0x1000>, /* SSIU */ 2015 <0 0xec541000 0 0x280>, /* SSI */ 2016 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 2017 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 2018 2019 clocks = <&cpg CPG_MOD 1005>, 2020 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 2021 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 2022 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 2023 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 2024 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 2025 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 2026 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 2027 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 2028 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 2029 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 2030 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 2031 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 2032 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 2033 <&audio_clk_a>, <&audio_clk_b>, 2034 <&audio_clk_c>, 2035 <&cpg CPG_CORE R8A7795_CLK_S0D4>; 2036 clock-names = "ssi-all", 2037 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 2038 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 2039 "ssi.1", "ssi.0", 2040 "src.9", "src.8", "src.7", "src.6", 2041 "src.5", "src.4", "src.3", "src.2", 2042 "src.1", "src.0", 2043 "mix.1", "mix.0", 2044 "ctu.1", "ctu.0", 2045 "dvc.0", "dvc.1", 2046 "clk_a", "clk_b", "clk_c", "clk_i"; 2047 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2048 resets = <&cpg 1005>, 2049 <&cpg 1006>, <&cpg 1007>, 2050 <&cpg 1008>, <&cpg 1009>, 2051 <&cpg 1010>, <&cpg 1011>, 2052 <&cpg 1012>, <&cpg 1013>, 2053 <&cpg 1014>, <&cpg 1015>; 2054 reset-names = "ssi-all", 2055 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 2056 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 2057 "ssi.1", "ssi.0"; 2058 status = "disabled"; 2059 2060 rcar_sound,dvc { 2061 dvc0: dvc-0 { 2062 dmas = <&audma1 0xbc>; 2063 dma-names = "tx"; 2064 }; 2065 dvc1: dvc-1 { 2066 dmas = <&audma1 0xbe>; 2067 dma-names = "tx"; 2068 }; 2069 }; 2070 2071 rcar_sound,mix { 2072 mix0: mix-0 { }; 2073 mix1: mix-1 { }; 2074 }; 2075 2076 rcar_sound,ctu { 2077 ctu00: ctu-0 { }; 2078 ctu01: ctu-1 { }; 2079 ctu02: ctu-2 { }; 2080 ctu03: ctu-3 { }; 2081 ctu10: ctu-4 { }; 2082 ctu11: ctu-5 { }; 2083 ctu12: ctu-6 { }; 2084 ctu13: ctu-7 { }; 2085 }; 2086 2087 rcar_sound,src { 2088 src0: src-0 { 2089 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2090 dmas = <&audma0 0x85>, <&audma1 0x9a>; 2091 dma-names = "rx", "tx"; 2092 }; 2093 src1: src-1 { 2094 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2095 dmas = <&audma0 0x87>, <&audma1 0x9c>; 2096 dma-names = "rx", "tx"; 2097 }; 2098 src2: src-2 { 2099 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2100 dmas = <&audma0 0x89>, <&audma1 0x9e>; 2101 dma-names = "rx", "tx"; 2102 }; 2103 src3: src-3 { 2104 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2105 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 2106 dma-names = "rx", "tx"; 2107 }; 2108 src4: src-4 { 2109 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2110 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 2111 dma-names = "rx", "tx"; 2112 }; 2113 src5: src-5 { 2114 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2115 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 2116 dma-names = "rx", "tx"; 2117 }; 2118 src6: src-6 { 2119 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2120 dmas = <&audma0 0x91>, <&audma1 0xb4>; 2121 dma-names = "rx", "tx"; 2122 }; 2123 src7: src-7 { 2124 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2125 dmas = <&audma0 0x93>, <&audma1 0xb6>; 2126 dma-names = "rx", "tx"; 2127 }; 2128 src8: src-8 { 2129 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2130 dmas = <&audma0 0x95>, <&audma1 0xb8>; 2131 dma-names = "rx", "tx"; 2132 }; 2133 src9: src-9 { 2134 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 2135 dmas = <&audma0 0x97>, <&audma1 0xba>; 2136 dma-names = "rx", "tx"; 2137 }; 2138 }; 2139 2140 rcar_sound,ssiu { 2141 ssiu00: ssiu-0 { 2142 dmas = <&audma0 0x15>, <&audma1 0x16>; 2143 dma-names = "rx", "tx"; 2144 }; 2145 ssiu01: ssiu-1 { 2146 dmas = <&audma0 0x35>, <&audma1 0x36>; 2147 dma-names = "rx", "tx"; 2148 }; 2149 ssiu02: ssiu-2 { 2150 dmas = <&audma0 0x37>, <&audma1 0x38>; 2151 dma-names = "rx", "tx"; 2152 }; 2153 ssiu03: ssiu-3 { 2154 dmas = <&audma0 0x47>, <&audma1 0x48>; 2155 dma-names = "rx", "tx"; 2156 }; 2157 ssiu04: ssiu-4 { 2158 dmas = <&audma0 0x3F>, <&audma1 0x40>; 2159 dma-names = "rx", "tx"; 2160 }; 2161 ssiu05: ssiu-5 { 2162 dmas = <&audma0 0x43>, <&audma1 0x44>; 2163 dma-names = "rx", "tx"; 2164 }; 2165 ssiu06: ssiu-6 { 2166 dmas = <&audma0 0x4F>, <&audma1 0x50>; 2167 dma-names = "rx", "tx"; 2168 }; 2169 ssiu07: ssiu-7 { 2170 dmas = <&audma0 0x53>, <&audma1 0x54>; 2171 dma-names = "rx", "tx"; 2172 }; 2173 ssiu10: ssiu-8 { 2174 dmas = <&audma0 0x49>, <&audma1 0x4a>; 2175 dma-names = "rx", "tx"; 2176 }; 2177 ssiu11: ssiu-9 { 2178 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 2179 dma-names = "rx", "tx"; 2180 }; 2181 ssiu12: ssiu-10 { 2182 dmas = <&audma0 0x57>, <&audma1 0x58>; 2183 dma-names = "rx", "tx"; 2184 }; 2185 ssiu13: ssiu-11 { 2186 dmas = <&audma0 0x59>, <&audma1 0x5A>; 2187 dma-names = "rx", "tx"; 2188 }; 2189 ssiu14: ssiu-12 { 2190 dmas = <&audma0 0x5F>, <&audma1 0x60>; 2191 dma-names = "rx", "tx"; 2192 }; 2193 ssiu15: ssiu-13 { 2194 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 2195 dma-names = "rx", "tx"; 2196 }; 2197 ssiu16: ssiu-14 { 2198 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 2199 dma-names = "rx", "tx"; 2200 }; 2201 ssiu17: ssiu-15 { 2202 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 2203 dma-names = "rx", "tx"; 2204 }; 2205 ssiu20: ssiu-16 { 2206 dmas = <&audma0 0x63>, <&audma1 0x64>; 2207 dma-names = "rx", "tx"; 2208 }; 2209 ssiu21: ssiu-17 { 2210 dmas = <&audma0 0x67>, <&audma1 0x68>; 2211 dma-names = "rx", "tx"; 2212 }; 2213 ssiu22: ssiu-18 { 2214 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 2215 dma-names = "rx", "tx"; 2216 }; 2217 ssiu23: ssiu-19 { 2218 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 2219 dma-names = "rx", "tx"; 2220 }; 2221 ssiu24: ssiu-20 { 2222 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 2223 dma-names = "rx", "tx"; 2224 }; 2225 ssiu25: ssiu-21 { 2226 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 2227 dma-names = "rx", "tx"; 2228 }; 2229 ssiu26: ssiu-22 { 2230 dmas = <&audma0 0xED>, <&audma1 0xEE>; 2231 dma-names = "rx", "tx"; 2232 }; 2233 ssiu27: ssiu-23 { 2234 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 2235 dma-names = "rx", "tx"; 2236 }; 2237 ssiu30: ssiu-24 { 2238 dmas = <&audma0 0x6f>, <&audma1 0x70>; 2239 dma-names = "rx", "tx"; 2240 }; 2241 ssiu31: ssiu-25 { 2242 dmas = <&audma0 0x21>, <&audma1 0x22>; 2243 dma-names = "rx", "tx"; 2244 }; 2245 ssiu32: ssiu-26 { 2246 dmas = <&audma0 0x23>, <&audma1 0x24>; 2247 dma-names = "rx", "tx"; 2248 }; 2249 ssiu33: ssiu-27 { 2250 dmas = <&audma0 0x25>, <&audma1 0x26>; 2251 dma-names = "rx", "tx"; 2252 }; 2253 ssiu34: ssiu-28 { 2254 dmas = <&audma0 0x27>, <&audma1 0x28>; 2255 dma-names = "rx", "tx"; 2256 }; 2257 ssiu35: ssiu-29 { 2258 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2259 dma-names = "rx", "tx"; 2260 }; 2261 ssiu36: ssiu-30 { 2262 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2263 dma-names = "rx", "tx"; 2264 }; 2265 ssiu37: ssiu-31 { 2266 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2267 dma-names = "rx", "tx"; 2268 }; 2269 ssiu40: ssiu-32 { 2270 dmas = <&audma0 0x71>, <&audma1 0x72>; 2271 dma-names = "rx", "tx"; 2272 }; 2273 ssiu41: ssiu-33 { 2274 dmas = <&audma0 0x17>, <&audma1 0x18>; 2275 dma-names = "rx", "tx"; 2276 }; 2277 ssiu42: ssiu-34 { 2278 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2279 dma-names = "rx", "tx"; 2280 }; 2281 ssiu43: ssiu-35 { 2282 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2283 dma-names = "rx", "tx"; 2284 }; 2285 ssiu44: ssiu-36 { 2286 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2287 dma-names = "rx", "tx"; 2288 }; 2289 ssiu45: ssiu-37 { 2290 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2291 dma-names = "rx", "tx"; 2292 }; 2293 ssiu46: ssiu-38 { 2294 dmas = <&audma0 0x31>, <&audma1 0x32>; 2295 dma-names = "rx", "tx"; 2296 }; 2297 ssiu47: ssiu-39 { 2298 dmas = <&audma0 0x33>, <&audma1 0x34>; 2299 dma-names = "rx", "tx"; 2300 }; 2301 ssiu50: ssiu-40 { 2302 dmas = <&audma0 0x73>, <&audma1 0x74>; 2303 dma-names = "rx", "tx"; 2304 }; 2305 ssiu60: ssiu-41 { 2306 dmas = <&audma0 0x75>, <&audma1 0x76>; 2307 dma-names = "rx", "tx"; 2308 }; 2309 ssiu70: ssiu-42 { 2310 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2311 dma-names = "rx", "tx"; 2312 }; 2313 ssiu80: ssiu-43 { 2314 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2315 dma-names = "rx", "tx"; 2316 }; 2317 ssiu90: ssiu-44 { 2318 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2319 dma-names = "rx", "tx"; 2320 }; 2321 ssiu91: ssiu-45 { 2322 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2323 dma-names = "rx", "tx"; 2324 }; 2325 ssiu92: ssiu-46 { 2326 dmas = <&audma0 0x81>, <&audma1 0x82>; 2327 dma-names = "rx", "tx"; 2328 }; 2329 ssiu93: ssiu-47 { 2330 dmas = <&audma0 0x83>, <&audma1 0x84>; 2331 dma-names = "rx", "tx"; 2332 }; 2333 ssiu94: ssiu-48 { 2334 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2335 dma-names = "rx", "tx"; 2336 }; 2337 ssiu95: ssiu-49 { 2338 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2339 dma-names = "rx", "tx"; 2340 }; 2341 ssiu96: ssiu-50 { 2342 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2343 dma-names = "rx", "tx"; 2344 }; 2345 ssiu97: ssiu-51 { 2346 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2347 dma-names = "rx", "tx"; 2348 }; 2349 }; 2350 2351 rcar_sound,ssi { 2352 ssi0: ssi-0 { 2353 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2354 dmas = <&audma0 0x01>, <&audma1 0x02>; 2355 dma-names = "rx", "tx"; 2356 }; 2357 ssi1: ssi-1 { 2358 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2359 dmas = <&audma0 0x03>, <&audma1 0x04>; 2360 dma-names = "rx", "tx"; 2361 }; 2362 ssi2: ssi-2 { 2363 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2364 dmas = <&audma0 0x05>, <&audma1 0x06>; 2365 dma-names = "rx", "tx"; 2366 }; 2367 ssi3: ssi-3 { 2368 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2369 dmas = <&audma0 0x07>, <&audma1 0x08>; 2370 dma-names = "rx", "tx"; 2371 }; 2372 ssi4: ssi-4 { 2373 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2374 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2375 dma-names = "rx", "tx"; 2376 }; 2377 ssi5: ssi-5 { 2378 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2379 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2380 dma-names = "rx", "tx"; 2381 }; 2382 ssi6: ssi-6 { 2383 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2384 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2385 dma-names = "rx", "tx"; 2386 }; 2387 ssi7: ssi-7 { 2388 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2389 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2390 dma-names = "rx", "tx"; 2391 }; 2392 ssi8: ssi-8 { 2393 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2394 dmas = <&audma0 0x11>, <&audma1 0x12>; 2395 dma-names = "rx", "tx"; 2396 }; 2397 ssi9: ssi-9 { 2398 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2399 dmas = <&audma0 0x13>, <&audma1 0x14>; 2400 dma-names = "rx", "tx"; 2401 }; 2402 }; 2403 }; 2404 2405 mlp: mlp@ec520000 { 2406 compatible = "renesas,r8a7795-mlp", 2407 "renesas,rcar-gen3-mlp"; 2408 reg = <0 0xec520000 0 0x800>; 2409 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2410 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; 2411 clocks = <&cpg CPG_MOD 802>; 2412 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2413 resets = <&cpg 802>; 2414 status = "disabled"; 2415 }; 2416 2417 audma0: dma-controller@ec700000 { 2418 compatible = "renesas,dmac-r8a7795", 2419 "renesas,rcar-dmac"; 2420 reg = <0 0xec700000 0 0x10000>; 2421 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2438 interrupt-names = "error", 2439 "ch0", "ch1", "ch2", "ch3", 2440 "ch4", "ch5", "ch6", "ch7", 2441 "ch8", "ch9", "ch10", "ch11", 2442 "ch12", "ch13", "ch14", "ch15"; 2443 clocks = <&cpg CPG_MOD 502>; 2444 clock-names = "fck"; 2445 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2446 resets = <&cpg 502>; 2447 #dma-cells = <1>; 2448 dma-channels = <16>; 2449 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2450 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2451 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2452 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2453 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2454 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2455 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2456 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2457 }; 2458 2459 audma1: dma-controller@ec720000 { 2460 compatible = "renesas,dmac-r8a7795", 2461 "renesas,rcar-dmac"; 2462 reg = <0 0xec720000 0 0x10000>; 2463 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2480 interrupt-names = "error", 2481 "ch0", "ch1", "ch2", "ch3", 2482 "ch4", "ch5", "ch6", "ch7", 2483 "ch8", "ch9", "ch10", "ch11", 2484 "ch12", "ch13", "ch14", "ch15"; 2485 clocks = <&cpg CPG_MOD 501>; 2486 clock-names = "fck"; 2487 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2488 resets = <&cpg 501>; 2489 #dma-cells = <1>; 2490 dma-channels = <16>; 2491 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2492 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2493 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2494 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2495 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2496 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2497 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2498 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2499 }; 2500 2501 xhci0: usb@ee000000 { 2502 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; 2503 reg = <0 0xee000000 0 0xc00>; 2504 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2505 clocks = <&cpg CPG_MOD 328>; 2506 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2507 resets = <&cpg 328>; 2508 status = "disabled"; 2509 }; 2510 2511 usb3_peri0: usb@ee020000 { 2512 compatible = "renesas,r8a7795-usb3-peri", 2513 "renesas,rcar-gen3-usb3-peri"; 2514 reg = <0 0xee020000 0 0x400>; 2515 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2516 clocks = <&cpg CPG_MOD 328>; 2517 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2518 resets = <&cpg 328>; 2519 status = "disabled"; 2520 }; 2521 2522 ohci0: usb@ee080000 { 2523 compatible = "generic-ohci"; 2524 reg = <0 0xee080000 0 0x100>; 2525 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2526 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2527 phys = <&usb2_phy0 1>; 2528 phy-names = "usb"; 2529 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2530 resets = <&cpg 703>, <&cpg 704>; 2531 status = "disabled"; 2532 }; 2533 2534 ohci1: usb@ee0a0000 { 2535 compatible = "generic-ohci"; 2536 reg = <0 0xee0a0000 0 0x100>; 2537 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2538 clocks = <&cpg CPG_MOD 702>; 2539 phys = <&usb2_phy1 1>; 2540 phy-names = "usb"; 2541 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2542 resets = <&cpg 702>; 2543 status = "disabled"; 2544 }; 2545 2546 ohci2: usb@ee0c0000 { 2547 compatible = "generic-ohci"; 2548 reg = <0 0xee0c0000 0 0x100>; 2549 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2550 clocks = <&cpg CPG_MOD 701>; 2551 phys = <&usb2_phy2 1>; 2552 phy-names = "usb"; 2553 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2554 resets = <&cpg 701>; 2555 status = "disabled"; 2556 }; 2557 2558 ohci3: usb@ee0e0000 { 2559 compatible = "generic-ohci"; 2560 reg = <0 0xee0e0000 0 0x100>; 2561 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2562 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2563 phys = <&usb2_phy3 1>; 2564 phy-names = "usb"; 2565 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2566 resets = <&cpg 700>, <&cpg 705>; 2567 status = "disabled"; 2568 }; 2569 2570 ehci0: usb@ee080100 { 2571 compatible = "generic-ehci"; 2572 reg = <0 0xee080100 0 0x100>; 2573 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2574 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2575 phys = <&usb2_phy0 2>; 2576 phy-names = "usb"; 2577 companion = <&ohci0>; 2578 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2579 resets = <&cpg 703>, <&cpg 704>; 2580 status = "disabled"; 2581 }; 2582 2583 ehci1: usb@ee0a0100 { 2584 compatible = "generic-ehci"; 2585 reg = <0 0xee0a0100 0 0x100>; 2586 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2587 clocks = <&cpg CPG_MOD 702>; 2588 phys = <&usb2_phy1 2>; 2589 phy-names = "usb"; 2590 companion = <&ohci1>; 2591 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2592 resets = <&cpg 702>; 2593 status = "disabled"; 2594 }; 2595 2596 ehci2: usb@ee0c0100 { 2597 compatible = "generic-ehci"; 2598 reg = <0 0xee0c0100 0 0x100>; 2599 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2600 clocks = <&cpg CPG_MOD 701>; 2601 phys = <&usb2_phy2 2>; 2602 phy-names = "usb"; 2603 companion = <&ohci2>; 2604 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2605 resets = <&cpg 701>; 2606 status = "disabled"; 2607 }; 2608 2609 ehci3: usb@ee0e0100 { 2610 compatible = "generic-ehci"; 2611 reg = <0 0xee0e0100 0 0x100>; 2612 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2613 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2614 phys = <&usb2_phy3 2>; 2615 phy-names = "usb"; 2616 companion = <&ohci3>; 2617 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2618 resets = <&cpg 700>, <&cpg 705>; 2619 status = "disabled"; 2620 }; 2621 2622 usb2_phy0: usb-phy@ee080200 { 2623 compatible = "renesas,usb2-phy-r8a7795", 2624 "renesas,rcar-gen3-usb2-phy"; 2625 reg = <0 0xee080200 0 0x700>; 2626 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2627 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2628 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2629 resets = <&cpg 703>, <&cpg 704>; 2630 #phy-cells = <1>; 2631 status = "disabled"; 2632 }; 2633 2634 usb2_phy1: usb-phy@ee0a0200 { 2635 compatible = "renesas,usb2-phy-r8a7795", 2636 "renesas,rcar-gen3-usb2-phy"; 2637 reg = <0 0xee0a0200 0 0x700>; 2638 clocks = <&cpg CPG_MOD 702>; 2639 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2640 resets = <&cpg 702>; 2641 #phy-cells = <1>; 2642 status = "disabled"; 2643 }; 2644 2645 usb2_phy2: usb-phy@ee0c0200 { 2646 compatible = "renesas,usb2-phy-r8a7795", 2647 "renesas,rcar-gen3-usb2-phy"; 2648 reg = <0 0xee0c0200 0 0x700>; 2649 clocks = <&cpg CPG_MOD 701>; 2650 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2651 resets = <&cpg 701>; 2652 #phy-cells = <1>; 2653 status = "disabled"; 2654 }; 2655 2656 usb2_phy3: usb-phy@ee0e0200 { 2657 compatible = "renesas,usb2-phy-r8a7795", 2658 "renesas,rcar-gen3-usb2-phy"; 2659 reg = <0 0xee0e0200 0 0x700>; 2660 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2661 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2662 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2663 resets = <&cpg 700>, <&cpg 705>; 2664 #phy-cells = <1>; 2665 status = "disabled"; 2666 }; 2667 2668 sdhi0: mmc@ee100000 { 2669 compatible = "renesas,sdhi-r8a7795", 2670 "renesas,rcar-gen3-sdhi"; 2671 reg = <0 0xee100000 0 0x2000>; 2672 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2673 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; 2674 clock-names = "core", "clkh"; 2675 max-frequency = <200000000>; 2676 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2677 resets = <&cpg 314>; 2678 iommus = <&ipmmu_ds1 32>; 2679 status = "disabled"; 2680 }; 2681 2682 sdhi1: mmc@ee120000 { 2683 compatible = "renesas,sdhi-r8a7795", 2684 "renesas,rcar-gen3-sdhi"; 2685 reg = <0 0xee120000 0 0x2000>; 2686 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2687 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; 2688 clock-names = "core", "clkh"; 2689 max-frequency = <200000000>; 2690 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2691 resets = <&cpg 313>; 2692 iommus = <&ipmmu_ds1 33>; 2693 status = "disabled"; 2694 }; 2695 2696 sdhi2: mmc@ee140000 { 2697 compatible = "renesas,sdhi-r8a7795", 2698 "renesas,rcar-gen3-sdhi"; 2699 reg = <0 0xee140000 0 0x2000>; 2700 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2701 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; 2702 clock-names = "core", "clkh"; 2703 max-frequency = <200000000>; 2704 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2705 resets = <&cpg 312>; 2706 iommus = <&ipmmu_ds1 34>; 2707 status = "disabled"; 2708 }; 2709 2710 sdhi3: mmc@ee160000 { 2711 compatible = "renesas,sdhi-r8a7795", 2712 "renesas,rcar-gen3-sdhi"; 2713 reg = <0 0xee160000 0 0x2000>; 2714 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2715 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; 2716 clock-names = "core", "clkh"; 2717 max-frequency = <200000000>; 2718 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2719 resets = <&cpg 311>; 2720 iommus = <&ipmmu_ds1 35>; 2721 status = "disabled"; 2722 }; 2723 2724 rpc: spi@ee200000 { 2725 compatible = "renesas,r8a7795-rpc-if", 2726 "renesas,rcar-gen3-rpc-if"; 2727 reg = <0 0xee200000 0 0x200>, 2728 <0 0x08000000 0 0x04000000>, 2729 <0 0xee208000 0 0x100>; 2730 reg-names = "regs", "dirmap", "wbuf"; 2731 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2732 clocks = <&cpg CPG_MOD 917>; 2733 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2734 resets = <&cpg 917>; 2735 #address-cells = <1>; 2736 #size-cells = <0>; 2737 status = "disabled"; 2738 }; 2739 2740 sata: sata@ee300000 { 2741 compatible = "renesas,sata-r8a7795", 2742 "renesas,rcar-gen3-sata"; 2743 reg = <0 0xee300000 0 0x200000>; 2744 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2745 clocks = <&cpg CPG_MOD 815>; 2746 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2747 resets = <&cpg 815>; 2748 status = "disabled"; 2749 iommus = <&ipmmu_hc 2>; 2750 }; 2751 2752 gic: interrupt-controller@f1010000 { 2753 compatible = "arm,gic-400"; 2754 #interrupt-cells = <3>; 2755 #address-cells = <0>; 2756 interrupt-controller; 2757 reg = <0x0 0xf1010000 0 0x1000>, 2758 <0x0 0xf1020000 0 0x20000>, 2759 <0x0 0xf1040000 0 0x20000>, 2760 <0x0 0xf1060000 0 0x20000>; 2761 interrupts = <GIC_PPI 9 2762 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2763 clocks = <&cpg CPG_MOD 408>; 2764 clock-names = "clk"; 2765 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2766 resets = <&cpg 408>; 2767 }; 2768 2769 pciec0: pcie@fe000000 { 2770 compatible = "renesas,pcie-r8a7795", 2771 "renesas,pcie-rcar-gen3"; 2772 reg = <0 0xfe000000 0 0x80000>; 2773 #address-cells = <3>; 2774 #size-cells = <2>; 2775 bus-range = <0x00 0xff>; 2776 device_type = "pci"; 2777 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2778 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2779 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2780 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2781 /* Map all possible DDR as inbound ranges */ 2782 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 2783 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2786 #interrupt-cells = <1>; 2787 interrupt-map-mask = <0 0 0 0>; 2788 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2789 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2790 clock-names = "pcie", "pcie_bus"; 2791 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2792 resets = <&cpg 319>; 2793 status = "disabled"; 2794 }; 2795 2796 pciec1: pcie@ee800000 { 2797 compatible = "renesas,pcie-r8a7795", 2798 "renesas,pcie-rcar-gen3"; 2799 reg = <0 0xee800000 0 0x80000>; 2800 #address-cells = <3>; 2801 #size-cells = <2>; 2802 bus-range = <0x00 0xff>; 2803 device_type = "pci"; 2804 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2805 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2806 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2807 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2808 /* Map all possible DDR as inbound ranges */ 2809 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 2810 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2813 #interrupt-cells = <1>; 2814 interrupt-map-mask = <0 0 0 0>; 2815 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2816 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2817 clock-names = "pcie", "pcie_bus"; 2818 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2819 resets = <&cpg 318>; 2820 status = "disabled"; 2821 }; 2822 2823 pciec0_ep: pcie-ep@fe000000 { 2824 compatible = "renesas,r8a7795-pcie-ep", 2825 "renesas,rcar-gen3-pcie-ep"; 2826 reg = <0x0 0xfe000000 0 0x80000>, 2827 <0x0 0xfe100000 0 0x100000>, 2828 <0x0 0xfe200000 0 0x200000>, 2829 <0x0 0x30000000 0 0x8000000>, 2830 <0x0 0x38000000 0 0x8000000>; 2831 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2832 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2835 clocks = <&cpg CPG_MOD 319>; 2836 clock-names = "pcie"; 2837 resets = <&cpg 319>; 2838 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2839 status = "disabled"; 2840 }; 2841 2842 pciec1_ep: pcie-ep@ee800000 { 2843 compatible = "renesas,r8a7795-pcie-ep", 2844 "renesas,rcar-gen3-pcie-ep"; 2845 reg = <0x0 0xee800000 0 0x80000>, 2846 <0x0 0xee900000 0 0x100000>, 2847 <0x0 0xeea00000 0 0x200000>, 2848 <0x0 0xc0000000 0 0x8000000>, 2849 <0x0 0xc8000000 0 0x8000000>; 2850 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2851 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2854 clocks = <&cpg CPG_MOD 318>; 2855 clock-names = "pcie"; 2856 resets = <&cpg 318>; 2857 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2858 status = "disabled"; 2859 }; 2860 2861 imr-lx4@fe860000 { 2862 compatible = "renesas,r8a7795-imr-lx4", 2863 "renesas,imr-lx4"; 2864 reg = <0 0xfe860000 0 0x2000>; 2865 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2866 clocks = <&cpg CPG_MOD 823>; 2867 power-domains = <&sysc R8A7795_PD_A3VC>; 2868 resets = <&cpg 823>; 2869 }; 2870 2871 imr-lx4@fe870000 { 2872 compatible = "renesas,r8a7795-imr-lx4", 2873 "renesas,imr-lx4"; 2874 reg = <0 0xfe870000 0 0x2000>; 2875 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2876 clocks = <&cpg CPG_MOD 822>; 2877 power-domains = <&sysc R8A7795_PD_A3VC>; 2878 resets = <&cpg 822>; 2879 }; 2880 2881 imr-lx4@fe880000 { 2882 compatible = "renesas,r8a7795-imr-lx4", 2883 "renesas,imr-lx4"; 2884 reg = <0 0xfe880000 0 0x2000>; 2885 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 2886 clocks = <&cpg CPG_MOD 821>; 2887 power-domains = <&sysc R8A7795_PD_A3VC>; 2888 resets = <&cpg 821>; 2889 }; 2890 2891 imr-lx4@fe890000 { 2892 compatible = "renesas,r8a7795-imr-lx4", 2893 "renesas,imr-lx4"; 2894 reg = <0 0xfe890000 0 0x2000>; 2895 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 2896 clocks = <&cpg CPG_MOD 820>; 2897 power-domains = <&sysc R8A7795_PD_A3VC>; 2898 resets = <&cpg 820>; 2899 }; 2900 2901 vspbc: vsp@fe920000 { 2902 compatible = "renesas,vsp2"; 2903 reg = <0 0xfe920000 0 0x8000>; 2904 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2905 clocks = <&cpg CPG_MOD 624>; 2906 power-domains = <&sysc R8A7795_PD_A3VP>; 2907 resets = <&cpg 624>; 2908 2909 renesas,fcp = <&fcpvb1>; 2910 }; 2911 2912 vspbd: vsp@fe960000 { 2913 compatible = "renesas,vsp2"; 2914 reg = <0 0xfe960000 0 0x8000>; 2915 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2916 clocks = <&cpg CPG_MOD 626>; 2917 power-domains = <&sysc R8A7795_PD_A3VP>; 2918 resets = <&cpg 626>; 2919 2920 renesas,fcp = <&fcpvb0>; 2921 }; 2922 2923 vspd0: vsp@fea20000 { 2924 compatible = "renesas,vsp2"; 2925 reg = <0 0xfea20000 0 0x5000>; 2926 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2927 clocks = <&cpg CPG_MOD 623>; 2928 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2929 resets = <&cpg 623>; 2930 2931 renesas,fcp = <&fcpvd0>; 2932 }; 2933 2934 vspd1: vsp@fea28000 { 2935 compatible = "renesas,vsp2"; 2936 reg = <0 0xfea28000 0 0x5000>; 2937 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2938 clocks = <&cpg CPG_MOD 622>; 2939 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2940 resets = <&cpg 622>; 2941 2942 renesas,fcp = <&fcpvd1>; 2943 }; 2944 2945 vspd2: vsp@fea30000 { 2946 compatible = "renesas,vsp2"; 2947 reg = <0 0xfea30000 0 0x5000>; 2948 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2949 clocks = <&cpg CPG_MOD 621>; 2950 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2951 resets = <&cpg 621>; 2952 2953 renesas,fcp = <&fcpvd2>; 2954 }; 2955 2956 vspi0: vsp@fe9a0000 { 2957 compatible = "renesas,vsp2"; 2958 reg = <0 0xfe9a0000 0 0x8000>; 2959 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2960 clocks = <&cpg CPG_MOD 631>; 2961 power-domains = <&sysc R8A7795_PD_A3VP>; 2962 resets = <&cpg 631>; 2963 2964 renesas,fcp = <&fcpvi0>; 2965 }; 2966 2967 vspi1: vsp@fe9b0000 { 2968 compatible = "renesas,vsp2"; 2969 reg = <0 0xfe9b0000 0 0x8000>; 2970 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 2971 clocks = <&cpg CPG_MOD 630>; 2972 power-domains = <&sysc R8A7795_PD_A3VP>; 2973 resets = <&cpg 630>; 2974 2975 renesas,fcp = <&fcpvi1>; 2976 }; 2977 2978 fdp1@fe940000 { 2979 compatible = "renesas,fdp1"; 2980 reg = <0 0xfe940000 0 0x2400>; 2981 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2982 clocks = <&cpg CPG_MOD 119>; 2983 power-domains = <&sysc R8A7795_PD_A3VP>; 2984 resets = <&cpg 119>; 2985 renesas,fcp = <&fcpf0>; 2986 }; 2987 2988 fdp1@fe944000 { 2989 compatible = "renesas,fdp1"; 2990 reg = <0 0xfe944000 0 0x2400>; 2991 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2992 clocks = <&cpg CPG_MOD 118>; 2993 power-domains = <&sysc R8A7795_PD_A3VP>; 2994 resets = <&cpg 118>; 2995 renesas,fcp = <&fcpf1>; 2996 }; 2997 2998 fcpf0: fcp@fe950000 { 2999 compatible = "renesas,fcpf"; 3000 reg = <0 0xfe950000 0 0x200>; 3001 clocks = <&cpg CPG_MOD 615>; 3002 power-domains = <&sysc R8A7795_PD_A3VP>; 3003 resets = <&cpg 615>; 3004 iommus = <&ipmmu_vp0 0>; 3005 }; 3006 3007 fcpf1: fcp@fe951000 { 3008 compatible = "renesas,fcpf"; 3009 reg = <0 0xfe951000 0 0x200>; 3010 clocks = <&cpg CPG_MOD 614>; 3011 power-domains = <&sysc R8A7795_PD_A3VP>; 3012 resets = <&cpg 614>; 3013 iommus = <&ipmmu_vp1 1>; 3014 }; 3015 3016 fcpvb0: fcp@fe96f000 { 3017 compatible = "renesas,fcpv"; 3018 reg = <0 0xfe96f000 0 0x200>; 3019 clocks = <&cpg CPG_MOD 607>; 3020 power-domains = <&sysc R8A7795_PD_A3VP>; 3021 resets = <&cpg 607>; 3022 iommus = <&ipmmu_vp0 5>; 3023 }; 3024 3025 fcpvb1: fcp@fe92f000 { 3026 compatible = "renesas,fcpv"; 3027 reg = <0 0xfe92f000 0 0x200>; 3028 clocks = <&cpg CPG_MOD 606>; 3029 power-domains = <&sysc R8A7795_PD_A3VP>; 3030 resets = <&cpg 606>; 3031 iommus = <&ipmmu_vp1 7>; 3032 }; 3033 3034 fcpvi0: fcp@fe9af000 { 3035 compatible = "renesas,fcpv"; 3036 reg = <0 0xfe9af000 0 0x200>; 3037 clocks = <&cpg CPG_MOD 611>; 3038 power-domains = <&sysc R8A7795_PD_A3VP>; 3039 resets = <&cpg 611>; 3040 iommus = <&ipmmu_vp0 8>; 3041 }; 3042 3043 fcpvi1: fcp@fe9bf000 { 3044 compatible = "renesas,fcpv"; 3045 reg = <0 0xfe9bf000 0 0x200>; 3046 clocks = <&cpg CPG_MOD 610>; 3047 power-domains = <&sysc R8A7795_PD_A3VP>; 3048 resets = <&cpg 610>; 3049 iommus = <&ipmmu_vp1 9>; 3050 }; 3051 3052 fcpvd0: fcp@fea27000 { 3053 compatible = "renesas,fcpv"; 3054 reg = <0 0xfea27000 0 0x200>; 3055 clocks = <&cpg CPG_MOD 603>; 3056 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3057 resets = <&cpg 603>; 3058 iommus = <&ipmmu_vi0 8>; 3059 }; 3060 3061 fcpvd1: fcp@fea2f000 { 3062 compatible = "renesas,fcpv"; 3063 reg = <0 0xfea2f000 0 0x200>; 3064 clocks = <&cpg CPG_MOD 602>; 3065 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3066 resets = <&cpg 602>; 3067 iommus = <&ipmmu_vi0 9>; 3068 }; 3069 3070 fcpvd2: fcp@fea37000 { 3071 compatible = "renesas,fcpv"; 3072 reg = <0 0xfea37000 0 0x200>; 3073 clocks = <&cpg CPG_MOD 601>; 3074 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3075 resets = <&cpg 601>; 3076 iommus = <&ipmmu_vi1 10>; 3077 }; 3078 3079 cmm0: cmm@fea40000 { 3080 compatible = "renesas,r8a7795-cmm", 3081 "renesas,rcar-gen3-cmm"; 3082 reg = <0 0xfea40000 0 0x1000>; 3083 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3084 clocks = <&cpg CPG_MOD 711>; 3085 resets = <&cpg 711>; 3086 }; 3087 3088 cmm1: cmm@fea50000 { 3089 compatible = "renesas,r8a7795-cmm", 3090 "renesas,rcar-gen3-cmm"; 3091 reg = <0 0xfea50000 0 0x1000>; 3092 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3093 clocks = <&cpg CPG_MOD 710>; 3094 resets = <&cpg 710>; 3095 }; 3096 3097 cmm2: cmm@fea60000 { 3098 compatible = "renesas,r8a7795-cmm", 3099 "renesas,rcar-gen3-cmm"; 3100 reg = <0 0xfea60000 0 0x1000>; 3101 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3102 clocks = <&cpg CPG_MOD 709>; 3103 resets = <&cpg 709>; 3104 }; 3105 3106 cmm3: cmm@fea70000 { 3107 compatible = "renesas,r8a7795-cmm", 3108 "renesas,rcar-gen3-cmm"; 3109 reg = <0 0xfea70000 0 0x1000>; 3110 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3111 clocks = <&cpg CPG_MOD 708>; 3112 resets = <&cpg 708>; 3113 }; 3114 3115 csi20: csi2@fea80000 { 3116 compatible = "renesas,r8a7795-csi2"; 3117 reg = <0 0xfea80000 0 0x10000>; 3118 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 3119 clocks = <&cpg CPG_MOD 714>; 3120 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3121 resets = <&cpg 714>; 3122 status = "disabled"; 3123 3124 ports { 3125 #address-cells = <1>; 3126 #size-cells = <0>; 3127 3128 port@0 { 3129 reg = <0>; 3130 }; 3131 3132 port@1 { 3133 #address-cells = <1>; 3134 #size-cells = <0>; 3135 3136 reg = <1>; 3137 3138 csi20vin0: endpoint@0 { 3139 reg = <0>; 3140 remote-endpoint = <&vin0csi20>; 3141 }; 3142 csi20vin1: endpoint@1 { 3143 reg = <1>; 3144 remote-endpoint = <&vin1csi20>; 3145 }; 3146 csi20vin2: endpoint@2 { 3147 reg = <2>; 3148 remote-endpoint = <&vin2csi20>; 3149 }; 3150 csi20vin3: endpoint@3 { 3151 reg = <3>; 3152 remote-endpoint = <&vin3csi20>; 3153 }; 3154 csi20vin4: endpoint@4 { 3155 reg = <4>; 3156 remote-endpoint = <&vin4csi20>; 3157 }; 3158 csi20vin5: endpoint@5 { 3159 reg = <5>; 3160 remote-endpoint = <&vin5csi20>; 3161 }; 3162 csi20vin6: endpoint@6 { 3163 reg = <6>; 3164 remote-endpoint = <&vin6csi20>; 3165 }; 3166 csi20vin7: endpoint@7 { 3167 reg = <7>; 3168 remote-endpoint = <&vin7csi20>; 3169 }; 3170 }; 3171 }; 3172 }; 3173 3174 csi40: csi2@feaa0000 { 3175 compatible = "renesas,r8a7795-csi2"; 3176 reg = <0 0xfeaa0000 0 0x10000>; 3177 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 3178 clocks = <&cpg CPG_MOD 716>; 3179 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3180 resets = <&cpg 716>; 3181 status = "disabled"; 3182 3183 ports { 3184 #address-cells = <1>; 3185 #size-cells = <0>; 3186 3187 port@0 { 3188 reg = <0>; 3189 }; 3190 3191 port@1 { 3192 #address-cells = <1>; 3193 #size-cells = <0>; 3194 3195 reg = <1>; 3196 3197 csi40vin0: endpoint@0 { 3198 reg = <0>; 3199 remote-endpoint = <&vin0csi40>; 3200 }; 3201 csi40vin1: endpoint@1 { 3202 reg = <1>; 3203 remote-endpoint = <&vin1csi40>; 3204 }; 3205 csi40vin2: endpoint@2 { 3206 reg = <2>; 3207 remote-endpoint = <&vin2csi40>; 3208 }; 3209 csi40vin3: endpoint@3 { 3210 reg = <3>; 3211 remote-endpoint = <&vin3csi40>; 3212 }; 3213 }; 3214 }; 3215 }; 3216 3217 csi41: csi2@feab0000 { 3218 compatible = "renesas,r8a7795-csi2"; 3219 reg = <0 0xfeab0000 0 0x10000>; 3220 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 3221 clocks = <&cpg CPG_MOD 715>; 3222 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3223 resets = <&cpg 715>; 3224 status = "disabled"; 3225 3226 ports { 3227 #address-cells = <1>; 3228 #size-cells = <0>; 3229 3230 port@0 { 3231 reg = <0>; 3232 }; 3233 3234 port@1 { 3235 #address-cells = <1>; 3236 #size-cells = <0>; 3237 3238 reg = <1>; 3239 3240 csi41vin4: endpoint@0 { 3241 reg = <0>; 3242 remote-endpoint = <&vin4csi41>; 3243 }; 3244 csi41vin5: endpoint@1 { 3245 reg = <1>; 3246 remote-endpoint = <&vin5csi41>; 3247 }; 3248 csi41vin6: endpoint@2 { 3249 reg = <2>; 3250 remote-endpoint = <&vin6csi41>; 3251 }; 3252 csi41vin7: endpoint@3 { 3253 reg = <3>; 3254 remote-endpoint = <&vin7csi41>; 3255 }; 3256 }; 3257 }; 3258 }; 3259 3260 hdmi0: hdmi@fead0000 { 3261 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 3262 reg = <0 0xfead0000 0 0x10000>; 3263 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 3264 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 3265 clock-names = "iahb", "isfr"; 3266 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3267 resets = <&cpg 729>; 3268 status = "disabled"; 3269 3270 ports { 3271 #address-cells = <1>; 3272 #size-cells = <0>; 3273 port@0 { 3274 reg = <0>; 3275 dw_hdmi0_in: endpoint { 3276 remote-endpoint = <&du_out_hdmi0>; 3277 }; 3278 }; 3279 port@1 { 3280 reg = <1>; 3281 }; 3282 port@2 { 3283 /* HDMI sound */ 3284 reg = <2>; 3285 }; 3286 }; 3287 }; 3288 3289 hdmi1: hdmi@feae0000 { 3290 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 3291 reg = <0 0xfeae0000 0 0x10000>; 3292 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; 3293 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 3294 clock-names = "iahb", "isfr"; 3295 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3296 resets = <&cpg 728>; 3297 status = "disabled"; 3298 3299 ports { 3300 #address-cells = <1>; 3301 #size-cells = <0>; 3302 port@0 { 3303 reg = <0>; 3304 dw_hdmi1_in: endpoint { 3305 remote-endpoint = <&du_out_hdmi1>; 3306 }; 3307 }; 3308 port@1 { 3309 reg = <1>; 3310 }; 3311 port@2 { 3312 /* HDMI sound */ 3313 reg = <2>; 3314 }; 3315 }; 3316 }; 3317 3318 du: display@feb00000 { 3319 compatible = "renesas,du-r8a7795"; 3320 reg = <0 0xfeb00000 0 0x80000>; 3321 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 3325 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 3326 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; 3327 clock-names = "du.0", "du.1", "du.2", "du.3"; 3328 resets = <&cpg 724>, <&cpg 722>; 3329 reset-names = "du.0", "du.2"; 3330 3331 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; 3332 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, 3333 <&vspd0 1>; 3334 3335 status = "disabled"; 3336 3337 ports { 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 3341 port@0 { 3342 reg = <0>; 3343 }; 3344 port@1 { 3345 reg = <1>; 3346 du_out_hdmi0: endpoint { 3347 remote-endpoint = <&dw_hdmi0_in>; 3348 }; 3349 }; 3350 port@2 { 3351 reg = <2>; 3352 du_out_hdmi1: endpoint { 3353 remote-endpoint = <&dw_hdmi1_in>; 3354 }; 3355 }; 3356 port@3 { 3357 reg = <3>; 3358 du_out_lvds0: endpoint { 3359 remote-endpoint = <&lvds0_in>; 3360 }; 3361 }; 3362 }; 3363 }; 3364 3365 lvds0: lvds@feb90000 { 3366 compatible = "renesas,r8a7795-lvds"; 3367 reg = <0 0xfeb90000 0 0x14>; 3368 clocks = <&cpg CPG_MOD 727>; 3369 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3370 resets = <&cpg 727>; 3371 status = "disabled"; 3372 3373 ports { 3374 #address-cells = <1>; 3375 #size-cells = <0>; 3376 3377 port@0 { 3378 reg = <0>; 3379 lvds0_in: endpoint { 3380 remote-endpoint = <&du_out_lvds0>; 3381 }; 3382 }; 3383 port@1 { 3384 reg = <1>; 3385 }; 3386 }; 3387 }; 3388 3389 prr: chipid@fff00044 { 3390 compatible = "renesas,prr"; 3391 reg = <0 0xfff00044 0 4>; 3392 }; 3393 }; 3394 3395 thermal-zones { 3396 sensor1_thermal: sensor1-thermal { 3397 polling-delay-passive = <250>; 3398 polling-delay = <1000>; 3399 thermal-sensors = <&tsc 0>; 3400 sustainable-power = <6313>; 3401 3402 trips { 3403 sensor1_crit: sensor1-crit { 3404 temperature = <120000>; 3405 hysteresis = <1000>; 3406 type = "critical"; 3407 }; 3408 }; 3409 }; 3410 3411 sensor2_thermal: sensor2-thermal { 3412 polling-delay-passive = <250>; 3413 polling-delay = <1000>; 3414 thermal-sensors = <&tsc 1>; 3415 sustainable-power = <6313>; 3416 3417 trips { 3418 sensor2_crit: sensor2-crit { 3419 temperature = <120000>; 3420 hysteresis = <1000>; 3421 type = "critical"; 3422 }; 3423 }; 3424 }; 3425 3426 sensor3_thermal: sensor3-thermal { 3427 polling-delay-passive = <250>; 3428 polling-delay = <1000>; 3429 thermal-sensors = <&tsc 2>; 3430 3431 trips { 3432 target: trip-point1 { 3433 temperature = <100000>; 3434 hysteresis = <1000>; 3435 type = "passive"; 3436 }; 3437 3438 sensor3_crit: sensor3-crit { 3439 temperature = <120000>; 3440 hysteresis = <1000>; 3441 type = "critical"; 3442 }; 3443 }; 3444 3445 cooling-maps { 3446 map0 { 3447 trip = <&target>; 3448 cooling-device = <&a57_0 2 4>; 3449 contribution = <1024>; 3450 }; 3451 3452 map1 { 3453 trip = <&target>; 3454 cooling-device = <&a53_0 0 2>; 3455 contribution = <1024>; 3456 }; 3457 }; 3458 }; 3459 }; 3460 3461 timer { 3462 compatible = "arm,armv8-timer"; 3463 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3464 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3465 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3466 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3467 }; 3468 3469 /* External USB clocks - can be overridden by the board */ 3470 usb3s0_clk: usb3s0 { 3471 compatible = "fixed-clock"; 3472 #clock-cells = <0>; 3473 clock-frequency = <0>; 3474 }; 3475 3476 usb_extal_clk: usb_extal { 3477 compatible = "fixed-clock"; 3478 #clock-cells = <0>; 3479 clock-frequency = <0>; 3480 }; 3481}; 3482