1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car H3 (R8A77951) SoC 4 * 5 * Copyright (C) 2015 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a7795-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 13 14#define SOC_HAS_HDMI1 15#define SOC_HAS_SATA 16#define SOC_HAS_USB2_CH2 17#define SOC_HAS_USB2_CH3 18 19/ { 20 compatible = "renesas,r8a7795"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 i2c2 = &i2c2; 28 i2c3 = &i2c3; 29 i2c4 = &i2c4; 30 i2c5 = &i2c5; 31 i2c6 = &i2c6; 32 i2c7 = &i2c_dvfs; 33 }; 34 35 /* 36 * The external audio clocks are configured as 0 Hz fixed frequency 37 * clocks by default. 38 * Boards that provide audio clocks should override them. 39 */ 40 audio_clk_a: audio_clk_a { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 }; 45 46 audio_clk_b: audio_clk_b { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 audio_clk_c: audio_clk_c { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 56 }; 57 58 /* External CAN clock - to be overridden by boards that provide it */ 59 can_clk: can { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 63 }; 64 65 cluster0_opp: opp-table-0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp-500000000 { 70 opp-hz = /bits/ 64 <500000000>; 71 opp-microvolt = <830000>; 72 clock-latency-ns = <300000>; 73 }; 74 opp-1000000000 { 75 opp-hz = /bits/ 64 <1000000000>; 76 opp-microvolt = <830000>; 77 clock-latency-ns = <300000>; 78 }; 79 opp-1500000000 { 80 opp-hz = /bits/ 64 <1500000000>; 81 opp-microvolt = <830000>; 82 clock-latency-ns = <300000>; 83 opp-suspend; 84 }; 85 opp-1600000000 { 86 opp-hz = /bits/ 64 <1600000000>; 87 opp-microvolt = <900000>; 88 clock-latency-ns = <300000>; 89 turbo-mode; 90 }; 91 opp-1700000000 { 92 opp-hz = /bits/ 64 <1700000000>; 93 opp-microvolt = <960000>; 94 clock-latency-ns = <300000>; 95 turbo-mode; 96 }; 97 }; 98 99 cluster1_opp: opp-table-1 { 100 compatible = "operating-points-v2"; 101 opp-shared; 102 103 opp-800000000 { 104 opp-hz = /bits/ 64 <800000000>; 105 opp-microvolt = <820000>; 106 clock-latency-ns = <300000>; 107 }; 108 opp-1000000000 { 109 opp-hz = /bits/ 64 <1000000000>; 110 opp-microvolt = <820000>; 111 clock-latency-ns = <300000>; 112 }; 113 opp-1200000000 { 114 opp-hz = /bits/ 64 <1200000000>; 115 opp-microvolt = <820000>; 116 clock-latency-ns = <300000>; 117 }; 118 }; 119 120 cpus { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 cpu-map { 125 cluster0 { 126 core0 { 127 cpu = <&a57_0>; 128 }; 129 core1 { 130 cpu = <&a57_1>; 131 }; 132 core2 { 133 cpu = <&a57_2>; 134 }; 135 core3 { 136 cpu = <&a57_3>; 137 }; 138 }; 139 140 cluster1 { 141 core0 { 142 cpu = <&a53_0>; 143 }; 144 core1 { 145 cpu = <&a53_1>; 146 }; 147 core2 { 148 cpu = <&a53_2>; 149 }; 150 core3 { 151 cpu = <&a53_3>; 152 }; 153 }; 154 }; 155 156 a57_0: cpu@0 { 157 compatible = "arm,cortex-a57"; 158 reg = <0x0>; 159 device_type = "cpu"; 160 power-domains = <&sysc R8A7795_PD_CA57_CPU0>; 161 next-level-cache = <&L2_CA57>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0>; 164 dynamic-power-coefficient = <854>; 165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 166 operating-points-v2 = <&cluster0_opp>; 167 capacity-dmips-mhz = <1024>; 168 #cooling-cells = <2>; 169 }; 170 171 a57_1: cpu@1 { 172 compatible = "arm,cortex-a57"; 173 reg = <0x1>; 174 device_type = "cpu"; 175 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 176 next-level-cache = <&L2_CA57>; 177 enable-method = "psci"; 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 180 operating-points-v2 = <&cluster0_opp>; 181 capacity-dmips-mhz = <1024>; 182 #cooling-cells = <2>; 183 }; 184 185 a57_2: cpu@2 { 186 compatible = "arm,cortex-a57"; 187 reg = <0x2>; 188 device_type = "cpu"; 189 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 190 next-level-cache = <&L2_CA57>; 191 enable-method = "psci"; 192 cpu-idle-states = <&CPU_SLEEP_0>; 193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 194 operating-points-v2 = <&cluster0_opp>; 195 capacity-dmips-mhz = <1024>; 196 #cooling-cells = <2>; 197 }; 198 199 a57_3: cpu@3 { 200 compatible = "arm,cortex-a57"; 201 reg = <0x3>; 202 device_type = "cpu"; 203 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 204 next-level-cache = <&L2_CA57>; 205 enable-method = "psci"; 206 cpu-idle-states = <&CPU_SLEEP_0>; 207 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 208 operating-points-v2 = <&cluster0_opp>; 209 capacity-dmips-mhz = <1024>; 210 #cooling-cells = <2>; 211 }; 212 213 a53_0: cpu@100 { 214 compatible = "arm,cortex-a53"; 215 reg = <0x100>; 216 device_type = "cpu"; 217 power-domains = <&sysc R8A7795_PD_CA53_CPU0>; 218 next-level-cache = <&L2_CA53>; 219 enable-method = "psci"; 220 cpu-idle-states = <&CPU_SLEEP_1>; 221 #cooling-cells = <2>; 222 dynamic-power-coefficient = <277>; 223 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 a53_1: cpu@101 { 229 compatible = "arm,cortex-a53"; 230 reg = <0x101>; 231 device_type = "cpu"; 232 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 233 next-level-cache = <&L2_CA53>; 234 enable-method = "psci"; 235 cpu-idle-states = <&CPU_SLEEP_1>; 236 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 237 operating-points-v2 = <&cluster1_opp>; 238 capacity-dmips-mhz = <535>; 239 }; 240 241 a53_2: cpu@102 { 242 compatible = "arm,cortex-a53"; 243 reg = <0x102>; 244 device_type = "cpu"; 245 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 246 next-level-cache = <&L2_CA53>; 247 enable-method = "psci"; 248 cpu-idle-states = <&CPU_SLEEP_1>; 249 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 250 operating-points-v2 = <&cluster1_opp>; 251 capacity-dmips-mhz = <535>; 252 }; 253 254 a53_3: cpu@103 { 255 compatible = "arm,cortex-a53"; 256 reg = <0x103>; 257 device_type = "cpu"; 258 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 259 next-level-cache = <&L2_CA53>; 260 enable-method = "psci"; 261 cpu-idle-states = <&CPU_SLEEP_1>; 262 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 263 operating-points-v2 = <&cluster1_opp>; 264 capacity-dmips-mhz = <535>; 265 }; 266 267 L2_CA57: cache-controller-0 { 268 compatible = "cache"; 269 power-domains = <&sysc R8A7795_PD_CA57_SCU>; 270 cache-unified; 271 cache-level = <2>; 272 }; 273 274 L2_CA53: cache-controller-1 { 275 compatible = "cache"; 276 power-domains = <&sysc R8A7795_PD_CA53_SCU>; 277 cache-unified; 278 cache-level = <2>; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 CPU_SLEEP_0: cpu-sleep-0 { 285 compatible = "arm,idle-state"; 286 arm,psci-suspend-param = <0x0010000>; 287 local-timer-stop; 288 entry-latency-us = <400>; 289 exit-latency-us = <500>; 290 min-residency-us = <4000>; 291 }; 292 293 CPU_SLEEP_1: cpu-sleep-1 { 294 compatible = "arm,idle-state"; 295 arm,psci-suspend-param = <0x0010000>; 296 local-timer-stop; 297 entry-latency-us = <700>; 298 exit-latency-us = <700>; 299 min-residency-us = <5000>; 300 }; 301 }; 302 }; 303 304 extal_clk: extal { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 /* This value must be overridden by the board */ 308 clock-frequency = <0>; 309 }; 310 311 extalr_clk: extalr { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 /* This value must be overridden by the board */ 315 clock-frequency = <0>; 316 }; 317 318 /* External PCIe clock - can be overridden by the board */ 319 pcie_bus_clk: pcie_bus { 320 compatible = "fixed-clock"; 321 #clock-cells = <0>; 322 clock-frequency = <0>; 323 }; 324 325 pmu_a53 { 326 compatible = "arm,cortex-a53-pmu"; 327 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 328 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 329 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 330 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-affinity = <&a53_0>, 332 <&a53_1>, 333 <&a53_2>, 334 <&a53_3>; 335 }; 336 337 pmu_a57 { 338 compatible = "arm,cortex-a57-pmu"; 339 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 340 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 341 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 342 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-affinity = <&a57_0>, 344 <&a57_1>, 345 <&a57_2>, 346 <&a57_3>; 347 }; 348 349 psci { 350 compatible = "arm,psci-1.0", "arm,psci-0.2"; 351 method = "smc"; 352 }; 353 354 /* External SCIF clock - to be overridden by boards that provide it */ 355 scif_clk: scif { 356 compatible = "fixed-clock"; 357 #clock-cells = <0>; 358 clock-frequency = <0>; 359 }; 360 361 soc: soc { 362 compatible = "simple-bus"; 363 interrupt-parent = <&gic>; 364 365 #address-cells = <2>; 366 #size-cells = <2>; 367 ranges; 368 369 rwdt: watchdog@e6020000 { 370 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; 371 reg = <0 0xe6020000 0 0x0c>; 372 clocks = <&cpg CPG_MOD 402>; 373 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 374 resets = <&cpg 402>; 375 status = "disabled"; 376 }; 377 378 gpio0: gpio@e6050000 { 379 compatible = "renesas,gpio-r8a7795", 380 "renesas,rcar-gen3-gpio"; 381 reg = <0 0xe6050000 0 0x50>; 382 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 383 #gpio-cells = <2>; 384 gpio-controller; 385 gpio-ranges = <&pfc 0 0 16>; 386 #interrupt-cells = <2>; 387 interrupt-controller; 388 clocks = <&cpg CPG_MOD 912>; 389 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 390 resets = <&cpg 912>; 391 }; 392 393 gpio1: gpio@e6051000 { 394 compatible = "renesas,gpio-r8a7795", 395 "renesas,rcar-gen3-gpio"; 396 reg = <0 0xe6051000 0 0x50>; 397 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 398 #gpio-cells = <2>; 399 gpio-controller; 400 gpio-ranges = <&pfc 0 32 29>; 401 #interrupt-cells = <2>; 402 interrupt-controller; 403 clocks = <&cpg CPG_MOD 911>; 404 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 405 resets = <&cpg 911>; 406 }; 407 408 gpio2: gpio@e6052000 { 409 compatible = "renesas,gpio-r8a7795", 410 "renesas,rcar-gen3-gpio"; 411 reg = <0 0xe6052000 0 0x50>; 412 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 413 #gpio-cells = <2>; 414 gpio-controller; 415 gpio-ranges = <&pfc 0 64 15>; 416 #interrupt-cells = <2>; 417 interrupt-controller; 418 clocks = <&cpg CPG_MOD 910>; 419 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 420 resets = <&cpg 910>; 421 }; 422 423 gpio3: gpio@e6053000 { 424 compatible = "renesas,gpio-r8a7795", 425 "renesas,rcar-gen3-gpio"; 426 reg = <0 0xe6053000 0 0x50>; 427 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 428 #gpio-cells = <2>; 429 gpio-controller; 430 gpio-ranges = <&pfc 0 96 16>; 431 #interrupt-cells = <2>; 432 interrupt-controller; 433 clocks = <&cpg CPG_MOD 909>; 434 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 435 resets = <&cpg 909>; 436 }; 437 438 gpio4: gpio@e6054000 { 439 compatible = "renesas,gpio-r8a7795", 440 "renesas,rcar-gen3-gpio"; 441 reg = <0 0xe6054000 0 0x50>; 442 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 443 #gpio-cells = <2>; 444 gpio-controller; 445 gpio-ranges = <&pfc 0 128 18>; 446 #interrupt-cells = <2>; 447 interrupt-controller; 448 clocks = <&cpg CPG_MOD 908>; 449 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 450 resets = <&cpg 908>; 451 }; 452 453 gpio5: gpio@e6055000 { 454 compatible = "renesas,gpio-r8a7795", 455 "renesas,rcar-gen3-gpio"; 456 reg = <0 0xe6055000 0 0x50>; 457 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 458 #gpio-cells = <2>; 459 gpio-controller; 460 gpio-ranges = <&pfc 0 160 26>; 461 #interrupt-cells = <2>; 462 interrupt-controller; 463 clocks = <&cpg CPG_MOD 907>; 464 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 465 resets = <&cpg 907>; 466 }; 467 468 gpio6: gpio@e6055400 { 469 compatible = "renesas,gpio-r8a7795", 470 "renesas,rcar-gen3-gpio"; 471 reg = <0 0xe6055400 0 0x50>; 472 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 473 #gpio-cells = <2>; 474 gpio-controller; 475 gpio-ranges = <&pfc 0 192 32>; 476 #interrupt-cells = <2>; 477 interrupt-controller; 478 clocks = <&cpg CPG_MOD 906>; 479 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 480 resets = <&cpg 906>; 481 }; 482 483 gpio7: gpio@e6055800 { 484 compatible = "renesas,gpio-r8a7795", 485 "renesas,rcar-gen3-gpio"; 486 reg = <0 0xe6055800 0 0x50>; 487 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 488 #gpio-cells = <2>; 489 gpio-controller; 490 gpio-ranges = <&pfc 0 224 4>; 491 #interrupt-cells = <2>; 492 interrupt-controller; 493 clocks = <&cpg CPG_MOD 905>; 494 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 495 resets = <&cpg 905>; 496 }; 497 498 pfc: pinctrl@e6060000 { 499 compatible = "renesas,pfc-r8a7795"; 500 reg = <0 0xe6060000 0 0x50c>; 501 }; 502 503 cmt0: timer@e60f0000 { 504 compatible = "renesas,r8a7795-cmt0", 505 "renesas,rcar-gen3-cmt0"; 506 reg = <0 0xe60f0000 0 0x1004>; 507 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cpg CPG_MOD 303>; 510 clock-names = "fck"; 511 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 512 resets = <&cpg 303>; 513 status = "disabled"; 514 }; 515 516 cmt1: timer@e6130000 { 517 compatible = "renesas,r8a7795-cmt1", 518 "renesas,rcar-gen3-cmt1"; 519 reg = <0 0xe6130000 0 0x1004>; 520 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&cpg CPG_MOD 302>; 529 clock-names = "fck"; 530 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 531 resets = <&cpg 302>; 532 status = "disabled"; 533 }; 534 535 cmt2: timer@e6140000 { 536 compatible = "renesas,r8a7795-cmt1", 537 "renesas,rcar-gen3-cmt1"; 538 reg = <0 0xe6140000 0 0x1004>; 539 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&cpg CPG_MOD 301>; 548 clock-names = "fck"; 549 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 550 resets = <&cpg 301>; 551 status = "disabled"; 552 }; 553 554 cmt3: timer@e6148000 { 555 compatible = "renesas,r8a7795-cmt1", 556 "renesas,rcar-gen3-cmt1"; 557 reg = <0 0xe6148000 0 0x1004>; 558 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&cpg CPG_MOD 300>; 567 clock-names = "fck"; 568 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 569 resets = <&cpg 300>; 570 status = "disabled"; 571 }; 572 573 cpg: clock-controller@e6150000 { 574 compatible = "renesas,r8a7795-cpg-mssr"; 575 reg = <0 0xe6150000 0 0x1000>; 576 clocks = <&extal_clk>, <&extalr_clk>; 577 clock-names = "extal", "extalr"; 578 #clock-cells = <2>; 579 #power-domain-cells = <0>; 580 #reset-cells = <1>; 581 }; 582 583 rst: reset-controller@e6160000 { 584 compatible = "renesas,r8a7795-rst"; 585 reg = <0 0xe6160000 0 0x0200>; 586 }; 587 588 sysc: system-controller@e6180000 { 589 compatible = "renesas,r8a7795-sysc"; 590 reg = <0 0xe6180000 0 0x0400>; 591 #power-domain-cells = <1>; 592 }; 593 594 tsc: thermal@e6198000 { 595 compatible = "renesas,r8a7795-thermal"; 596 reg = <0 0xe6198000 0 0x100>, 597 <0 0xe61a0000 0 0x100>, 598 <0 0xe61a8000 0 0x100>; 599 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cpg CPG_MOD 522>; 603 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 604 resets = <&cpg 522>; 605 #thermal-sensor-cells = <1>; 606 }; 607 608 intc_ex: interrupt-controller@e61c0000 { 609 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; 610 #interrupt-cells = <2>; 611 interrupt-controller; 612 reg = <0 0xe61c0000 0 0x200>; 613 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cpg CPG_MOD 407>; 620 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 621 resets = <&cpg 407>; 622 }; 623 624 tmu0: timer@e61e0000 { 625 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 626 reg = <0 0xe61e0000 0 0x30>; 627 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cpg CPG_MOD 125>; 631 clock-names = "fck"; 632 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 633 resets = <&cpg 125>; 634 status = "disabled"; 635 }; 636 637 tmu1: timer@e6fc0000 { 638 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 639 reg = <0 0xe6fc0000 0 0x30>; 640 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cpg CPG_MOD 124>; 644 clock-names = "fck"; 645 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 646 resets = <&cpg 124>; 647 status = "disabled"; 648 }; 649 650 tmu2: timer@e6fd0000 { 651 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 652 reg = <0 0xe6fd0000 0 0x30>; 653 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&cpg CPG_MOD 123>; 657 clock-names = "fck"; 658 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 659 resets = <&cpg 123>; 660 status = "disabled"; 661 }; 662 663 tmu3: timer@e6fe0000 { 664 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 665 reg = <0 0xe6fe0000 0 0x30>; 666 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&cpg CPG_MOD 122>; 670 clock-names = "fck"; 671 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 672 resets = <&cpg 122>; 673 status = "disabled"; 674 }; 675 676 tmu4: timer@ffc00000 { 677 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 678 reg = <0 0xffc00000 0 0x30>; 679 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 121>; 683 clock-names = "fck"; 684 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 685 resets = <&cpg 121>; 686 status = "disabled"; 687 }; 688 689 i2c0: i2c@e6500000 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 compatible = "renesas,i2c-r8a7795", 693 "renesas,rcar-gen3-i2c"; 694 reg = <0 0xe6500000 0 0x40>; 695 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cpg CPG_MOD 931>; 697 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 698 resets = <&cpg 931>; 699 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 700 <&dmac2 0x91>, <&dmac2 0x90>; 701 dma-names = "tx", "rx", "tx", "rx"; 702 i2c-scl-internal-delay-ns = <110>; 703 status = "disabled"; 704 }; 705 706 i2c1: i2c@e6508000 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 compatible = "renesas,i2c-r8a7795", 710 "renesas,rcar-gen3-i2c"; 711 reg = <0 0xe6508000 0 0x40>; 712 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cpg CPG_MOD 930>; 714 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 715 resets = <&cpg 930>; 716 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 717 <&dmac2 0x93>, <&dmac2 0x92>; 718 dma-names = "tx", "rx", "tx", "rx"; 719 i2c-scl-internal-delay-ns = <6>; 720 status = "disabled"; 721 }; 722 723 i2c2: i2c@e6510000 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 compatible = "renesas,i2c-r8a7795", 727 "renesas,rcar-gen3-i2c"; 728 reg = <0 0xe6510000 0 0x40>; 729 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cpg CPG_MOD 929>; 731 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 732 resets = <&cpg 929>; 733 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 734 <&dmac2 0x95>, <&dmac2 0x94>; 735 dma-names = "tx", "rx", "tx", "rx"; 736 i2c-scl-internal-delay-ns = <6>; 737 status = "disabled"; 738 }; 739 740 i2c3: i2c@e66d0000 { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 compatible = "renesas,i2c-r8a7795", 744 "renesas,rcar-gen3-i2c"; 745 reg = <0 0xe66d0000 0 0x40>; 746 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cpg CPG_MOD 928>; 748 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 749 resets = <&cpg 928>; 750 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 751 dma-names = "tx", "rx"; 752 i2c-scl-internal-delay-ns = <110>; 753 status = "disabled"; 754 }; 755 756 i2c4: i2c@e66d8000 { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 compatible = "renesas,i2c-r8a7795", 760 "renesas,rcar-gen3-i2c"; 761 reg = <0 0xe66d8000 0 0x40>; 762 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cpg CPG_MOD 927>; 764 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 765 resets = <&cpg 927>; 766 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 767 dma-names = "tx", "rx"; 768 i2c-scl-internal-delay-ns = <110>; 769 status = "disabled"; 770 }; 771 772 i2c5: i2c@e66e0000 { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 compatible = "renesas,i2c-r8a7795", 776 "renesas,rcar-gen3-i2c"; 777 reg = <0 0xe66e0000 0 0x40>; 778 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 919>; 780 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 781 resets = <&cpg 919>; 782 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 783 dma-names = "tx", "rx"; 784 i2c-scl-internal-delay-ns = <110>; 785 status = "disabled"; 786 }; 787 788 i2c6: i2c@e66e8000 { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 compatible = "renesas,i2c-r8a7795", 792 "renesas,rcar-gen3-i2c"; 793 reg = <0 0xe66e8000 0 0x40>; 794 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&cpg CPG_MOD 918>; 796 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 797 resets = <&cpg 918>; 798 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 799 dma-names = "tx", "rx"; 800 i2c-scl-internal-delay-ns = <6>; 801 status = "disabled"; 802 }; 803 804 i2c_dvfs: i2c@e60b0000 { 805 #address-cells = <1>; 806 #size-cells = <0>; 807 compatible = "renesas,iic-r8a7795", 808 "renesas,rcar-gen3-iic", 809 "renesas,rmobile-iic"; 810 reg = <0 0xe60b0000 0 0x425>; 811 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 926>; 813 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 814 resets = <&cpg 926>; 815 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 816 dma-names = "tx", "rx"; 817 status = "disabled"; 818 }; 819 820 hscif0: serial@e6540000 { 821 compatible = "renesas,hscif-r8a7795", 822 "renesas,rcar-gen3-hscif", 823 "renesas,hscif"; 824 reg = <0 0xe6540000 0 96>; 825 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD 520>, 827 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 828 <&scif_clk>; 829 clock-names = "fck", "brg_int", "scif_clk"; 830 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 831 <&dmac2 0x31>, <&dmac2 0x30>; 832 dma-names = "tx", "rx", "tx", "rx"; 833 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 834 resets = <&cpg 520>; 835 status = "disabled"; 836 }; 837 838 hscif1: serial@e6550000 { 839 compatible = "renesas,hscif-r8a7795", 840 "renesas,rcar-gen3-hscif", 841 "renesas,hscif"; 842 reg = <0 0xe6550000 0 96>; 843 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cpg CPG_MOD 519>, 845 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 846 <&scif_clk>; 847 clock-names = "fck", "brg_int", "scif_clk"; 848 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 849 <&dmac2 0x33>, <&dmac2 0x32>; 850 dma-names = "tx", "rx", "tx", "rx"; 851 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 852 resets = <&cpg 519>; 853 status = "disabled"; 854 }; 855 856 hscif2: serial@e6560000 { 857 compatible = "renesas,hscif-r8a7795", 858 "renesas,rcar-gen3-hscif", 859 "renesas,hscif"; 860 reg = <0 0xe6560000 0 96>; 861 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&cpg CPG_MOD 518>, 863 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 864 <&scif_clk>; 865 clock-names = "fck", "brg_int", "scif_clk"; 866 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 867 <&dmac2 0x35>, <&dmac2 0x34>; 868 dma-names = "tx", "rx", "tx", "rx"; 869 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 870 resets = <&cpg 518>; 871 status = "disabled"; 872 }; 873 874 hscif3: serial@e66a0000 { 875 compatible = "renesas,hscif-r8a7795", 876 "renesas,rcar-gen3-hscif", 877 "renesas,hscif"; 878 reg = <0 0xe66a0000 0 96>; 879 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cpg CPG_MOD 517>, 881 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 882 <&scif_clk>; 883 clock-names = "fck", "brg_int", "scif_clk"; 884 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 885 dma-names = "tx", "rx"; 886 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 887 resets = <&cpg 517>; 888 status = "disabled"; 889 }; 890 891 hscif4: serial@e66b0000 { 892 compatible = "renesas,hscif-r8a7795", 893 "renesas,rcar-gen3-hscif", 894 "renesas,hscif"; 895 reg = <0 0xe66b0000 0 96>; 896 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cpg CPG_MOD 516>, 898 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 899 <&scif_clk>; 900 clock-names = "fck", "brg_int", "scif_clk"; 901 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 902 dma-names = "tx", "rx"; 903 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 904 resets = <&cpg 516>; 905 status = "disabled"; 906 }; 907 908 hsusb: usb@e6590000 { 909 compatible = "renesas,usbhs-r8a7795", 910 "renesas,rcar-gen3-usbhs"; 911 reg = <0 0xe6590000 0 0x200>; 912 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 914 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 915 <&usb_dmac1 0>, <&usb_dmac1 1>; 916 dma-names = "ch0", "ch1", "ch2", "ch3"; 917 renesas,buswait = <11>; 918 phys = <&usb2_phy0 3>; 919 phy-names = "usb"; 920 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 921 resets = <&cpg 704>, <&cpg 703>; 922 status = "disabled"; 923 }; 924 925 hsusb3: usb@e659c000 { 926 compatible = "renesas,usbhs-r8a7795", 927 "renesas,rcar-gen3-usbhs"; 928 reg = <0 0xe659c000 0 0x200>; 929 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; 931 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, 932 <&usb_dmac3 0>, <&usb_dmac3 1>; 933 dma-names = "ch0", "ch1", "ch2", "ch3"; 934 renesas,buswait = <11>; 935 phys = <&usb2_phy3 3>; 936 phy-names = "usb"; 937 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 938 resets = <&cpg 705>, <&cpg 700>; 939 status = "disabled"; 940 }; 941 942 usb_dmac0: dma-controller@e65a0000 { 943 compatible = "renesas,r8a7795-usb-dmac", 944 "renesas,usb-dmac"; 945 reg = <0 0xe65a0000 0 0x100>; 946 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "ch0", "ch1"; 949 clocks = <&cpg CPG_MOD 330>; 950 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 951 resets = <&cpg 330>; 952 #dma-cells = <1>; 953 dma-channels = <2>; 954 }; 955 956 usb_dmac1: dma-controller@e65b0000 { 957 compatible = "renesas,r8a7795-usb-dmac", 958 "renesas,usb-dmac"; 959 reg = <0 0xe65b0000 0 0x100>; 960 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 962 interrupt-names = "ch0", "ch1"; 963 clocks = <&cpg CPG_MOD 331>; 964 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 965 resets = <&cpg 331>; 966 #dma-cells = <1>; 967 dma-channels = <2>; 968 }; 969 970 usb_dmac2: dma-controller@e6460000 { 971 compatible = "renesas,r8a7795-usb-dmac", 972 "renesas,usb-dmac"; 973 reg = <0 0xe6460000 0 0x100>; 974 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 976 interrupt-names = "ch0", "ch1"; 977 clocks = <&cpg CPG_MOD 326>; 978 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 979 resets = <&cpg 326>; 980 #dma-cells = <1>; 981 dma-channels = <2>; 982 }; 983 984 usb_dmac3: dma-controller@e6470000 { 985 compatible = "renesas,r8a7795-usb-dmac", 986 "renesas,usb-dmac"; 987 reg = <0 0xe6470000 0 0x100>; 988 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 990 interrupt-names = "ch0", "ch1"; 991 clocks = <&cpg CPG_MOD 329>; 992 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 993 resets = <&cpg 329>; 994 #dma-cells = <1>; 995 dma-channels = <2>; 996 }; 997 998 usb3_phy0: usb-phy@e65ee000 { 999 compatible = "renesas,r8a7795-usb3-phy", 1000 "renesas,rcar-gen3-usb3-phy"; 1001 reg = <0 0xe65ee000 0 0x90>; 1002 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 1003 <&usb_extal_clk>; 1004 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 1005 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1006 resets = <&cpg 328>; 1007 #phy-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 arm_cc630p: crypto@e6601000 { 1012 compatible = "arm,cryptocell-630p-ree"; 1013 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1014 reg = <0x0 0xe6601000 0 0x1000>; 1015 clocks = <&cpg CPG_MOD 229>; 1016 resets = <&cpg 229>; 1017 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1018 }; 1019 1020 dmac0: dma-controller@e6700000 { 1021 compatible = "renesas,dmac-r8a7795", 1022 "renesas,rcar-dmac"; 1023 reg = <0 0xe6700000 0 0x10000>; 1024 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1041 interrupt-names = "error", 1042 "ch0", "ch1", "ch2", "ch3", 1043 "ch4", "ch5", "ch6", "ch7", 1044 "ch8", "ch9", "ch10", "ch11", 1045 "ch12", "ch13", "ch14", "ch15"; 1046 clocks = <&cpg CPG_MOD 219>; 1047 clock-names = "fck"; 1048 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1049 resets = <&cpg 219>; 1050 #dma-cells = <1>; 1051 dma-channels = <16>; 1052 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1053 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1054 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1055 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1056 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1057 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1058 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1059 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1060 }; 1061 1062 dmac1: dma-controller@e7300000 { 1063 compatible = "renesas,dmac-r8a7795", 1064 "renesas,rcar-dmac"; 1065 reg = <0 0xe7300000 0 0x10000>; 1066 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "error", 1084 "ch0", "ch1", "ch2", "ch3", 1085 "ch4", "ch5", "ch6", "ch7", 1086 "ch8", "ch9", "ch10", "ch11", 1087 "ch12", "ch13", "ch14", "ch15"; 1088 clocks = <&cpg CPG_MOD 218>; 1089 clock-names = "fck"; 1090 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1091 resets = <&cpg 218>; 1092 #dma-cells = <1>; 1093 dma-channels = <16>; 1094 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1095 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1096 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1097 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1098 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1099 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1100 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1101 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1102 }; 1103 1104 dmac2: dma-controller@e7310000 { 1105 compatible = "renesas,dmac-r8a7795", 1106 "renesas,rcar-dmac"; 1107 reg = <0 0xe7310000 0 0x10000>; 1108 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1125 interrupt-names = "error", 1126 "ch0", "ch1", "ch2", "ch3", 1127 "ch4", "ch5", "ch6", "ch7", 1128 "ch8", "ch9", "ch10", "ch11", 1129 "ch12", "ch13", "ch14", "ch15"; 1130 clocks = <&cpg CPG_MOD 217>; 1131 clock-names = "fck"; 1132 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1133 resets = <&cpg 217>; 1134 #dma-cells = <1>; 1135 dma-channels = <16>; 1136 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1137 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1138 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1139 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1140 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1141 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1142 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1143 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1144 }; 1145 1146 ipmmu_ds0: iommu@e6740000 { 1147 compatible = "renesas,ipmmu-r8a7795"; 1148 reg = <0 0xe6740000 0 0x1000>; 1149 renesas,ipmmu-main = <&ipmmu_mm 0>; 1150 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1151 #iommu-cells = <1>; 1152 }; 1153 1154 ipmmu_ds1: iommu@e7740000 { 1155 compatible = "renesas,ipmmu-r8a7795"; 1156 reg = <0 0xe7740000 0 0x1000>; 1157 renesas,ipmmu-main = <&ipmmu_mm 1>; 1158 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1159 #iommu-cells = <1>; 1160 }; 1161 1162 ipmmu_hc: iommu@e6570000 { 1163 compatible = "renesas,ipmmu-r8a7795"; 1164 reg = <0 0xe6570000 0 0x1000>; 1165 renesas,ipmmu-main = <&ipmmu_mm 2>; 1166 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1167 #iommu-cells = <1>; 1168 }; 1169 1170 ipmmu_ir: iommu@ff8b0000 { 1171 compatible = "renesas,ipmmu-r8a7795"; 1172 reg = <0 0xff8b0000 0 0x1000>; 1173 renesas,ipmmu-main = <&ipmmu_mm 3>; 1174 power-domains = <&sysc R8A7795_PD_A3IR>; 1175 #iommu-cells = <1>; 1176 }; 1177 1178 ipmmu_mm: iommu@e67b0000 { 1179 compatible = "renesas,ipmmu-r8a7795"; 1180 reg = <0 0xe67b0000 0 0x1000>; 1181 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1183 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1184 #iommu-cells = <1>; 1185 }; 1186 1187 ipmmu_mp0: iommu@ec670000 { 1188 compatible = "renesas,ipmmu-r8a7795"; 1189 reg = <0 0xec670000 0 0x1000>; 1190 renesas,ipmmu-main = <&ipmmu_mm 4>; 1191 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1192 #iommu-cells = <1>; 1193 }; 1194 1195 ipmmu_pv0: iommu@fd800000 { 1196 compatible = "renesas,ipmmu-r8a7795"; 1197 reg = <0 0xfd800000 0 0x1000>; 1198 renesas,ipmmu-main = <&ipmmu_mm 6>; 1199 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1200 #iommu-cells = <1>; 1201 }; 1202 1203 ipmmu_pv1: iommu@fd950000 { 1204 compatible = "renesas,ipmmu-r8a7795"; 1205 reg = <0 0xfd950000 0 0x1000>; 1206 renesas,ipmmu-main = <&ipmmu_mm 7>; 1207 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1208 #iommu-cells = <1>; 1209 }; 1210 1211 ipmmu_pv2: iommu@fd960000 { 1212 compatible = "renesas,ipmmu-r8a7795"; 1213 reg = <0 0xfd960000 0 0x1000>; 1214 renesas,ipmmu-main = <&ipmmu_mm 8>; 1215 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1216 #iommu-cells = <1>; 1217 }; 1218 1219 ipmmu_pv3: iommu@fd970000 { 1220 compatible = "renesas,ipmmu-r8a7795"; 1221 reg = <0 0xfd970000 0 0x1000>; 1222 renesas,ipmmu-main = <&ipmmu_mm 9>; 1223 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1224 #iommu-cells = <1>; 1225 }; 1226 1227 ipmmu_rt: iommu@ffc80000 { 1228 compatible = "renesas,ipmmu-r8a7795"; 1229 reg = <0 0xffc80000 0 0x1000>; 1230 renesas,ipmmu-main = <&ipmmu_mm 10>; 1231 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1232 #iommu-cells = <1>; 1233 }; 1234 1235 ipmmu_vc0: iommu@fe6b0000 { 1236 compatible = "renesas,ipmmu-r8a7795"; 1237 reg = <0 0xfe6b0000 0 0x1000>; 1238 renesas,ipmmu-main = <&ipmmu_mm 12>; 1239 power-domains = <&sysc R8A7795_PD_A3VC>; 1240 #iommu-cells = <1>; 1241 }; 1242 1243 ipmmu_vc1: iommu@fe6f0000 { 1244 compatible = "renesas,ipmmu-r8a7795"; 1245 reg = <0 0xfe6f0000 0 0x1000>; 1246 renesas,ipmmu-main = <&ipmmu_mm 13>; 1247 power-domains = <&sysc R8A7795_PD_A3VC>; 1248 #iommu-cells = <1>; 1249 }; 1250 1251 ipmmu_vi0: iommu@febd0000 { 1252 compatible = "renesas,ipmmu-r8a7795"; 1253 reg = <0 0xfebd0000 0 0x1000>; 1254 renesas,ipmmu-main = <&ipmmu_mm 14>; 1255 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1256 #iommu-cells = <1>; 1257 }; 1258 1259 ipmmu_vi1: iommu@febe0000 { 1260 compatible = "renesas,ipmmu-r8a7795"; 1261 reg = <0 0xfebe0000 0 0x1000>; 1262 renesas,ipmmu-main = <&ipmmu_mm 15>; 1263 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1264 #iommu-cells = <1>; 1265 }; 1266 1267 ipmmu_vp0: iommu@fe990000 { 1268 compatible = "renesas,ipmmu-r8a7795"; 1269 reg = <0 0xfe990000 0 0x1000>; 1270 renesas,ipmmu-main = <&ipmmu_mm 16>; 1271 power-domains = <&sysc R8A7795_PD_A3VP>; 1272 #iommu-cells = <1>; 1273 }; 1274 1275 ipmmu_vp1: iommu@fe980000 { 1276 compatible = "renesas,ipmmu-r8a7795"; 1277 reg = <0 0xfe980000 0 0x1000>; 1278 renesas,ipmmu-main = <&ipmmu_mm 17>; 1279 power-domains = <&sysc R8A7795_PD_A3VP>; 1280 #iommu-cells = <1>; 1281 }; 1282 1283 avb: ethernet@e6800000 { 1284 compatible = "renesas,etheravb-r8a7795", 1285 "renesas,etheravb-rcar-gen3"; 1286 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1287 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1312 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1313 "ch4", "ch5", "ch6", "ch7", 1314 "ch8", "ch9", "ch10", "ch11", 1315 "ch12", "ch13", "ch14", "ch15", 1316 "ch16", "ch17", "ch18", "ch19", 1317 "ch20", "ch21", "ch22", "ch23", 1318 "ch24"; 1319 clocks = <&cpg CPG_MOD 812>; 1320 clock-names = "fck"; 1321 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1322 resets = <&cpg 812>; 1323 phy-mode = "rgmii"; 1324 rx-internal-delay-ps = <0>; 1325 tx-internal-delay-ps = <0>; 1326 iommus = <&ipmmu_ds0 16>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 can0: can@e6c30000 { 1333 compatible = "renesas,can-r8a7795", 1334 "renesas,rcar-gen3-can"; 1335 reg = <0 0xe6c30000 0 0x1000>; 1336 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&cpg CPG_MOD 916>, 1338 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1339 <&can_clk>; 1340 clock-names = "clkp1", "clkp2", "can_clk"; 1341 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1342 assigned-clock-rates = <40000000>; 1343 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1344 resets = <&cpg 916>; 1345 status = "disabled"; 1346 }; 1347 1348 can1: can@e6c38000 { 1349 compatible = "renesas,can-r8a7795", 1350 "renesas,rcar-gen3-can"; 1351 reg = <0 0xe6c38000 0 0x1000>; 1352 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cpg CPG_MOD 915>, 1354 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1355 <&can_clk>; 1356 clock-names = "clkp1", "clkp2", "can_clk"; 1357 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1358 assigned-clock-rates = <40000000>; 1359 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1360 resets = <&cpg 915>; 1361 status = "disabled"; 1362 }; 1363 1364 canfd: can@e66c0000 { 1365 compatible = "renesas,r8a7795-canfd", 1366 "renesas,rcar-gen3-canfd"; 1367 reg = <0 0xe66c0000 0 0x8000>; 1368 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&cpg CPG_MOD 914>, 1371 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1372 <&can_clk>; 1373 clock-names = "fck", "canfd", "can_clk"; 1374 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1375 assigned-clock-rates = <40000000>; 1376 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1377 resets = <&cpg 914>; 1378 status = "disabled"; 1379 1380 channel0 { 1381 status = "disabled"; 1382 }; 1383 1384 channel1 { 1385 status = "disabled"; 1386 }; 1387 }; 1388 1389 pwm0: pwm@e6e30000 { 1390 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1391 reg = <0 0xe6e30000 0 0x8>; 1392 clocks = <&cpg CPG_MOD 523>; 1393 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1394 resets = <&cpg 523>; 1395 #pwm-cells = <2>; 1396 status = "disabled"; 1397 }; 1398 1399 pwm1: pwm@e6e31000 { 1400 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1401 reg = <0 0xe6e31000 0 0x8>; 1402 clocks = <&cpg CPG_MOD 523>; 1403 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1404 resets = <&cpg 523>; 1405 #pwm-cells = <2>; 1406 status = "disabled"; 1407 }; 1408 1409 pwm2: pwm@e6e32000 { 1410 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1411 reg = <0 0xe6e32000 0 0x8>; 1412 clocks = <&cpg CPG_MOD 523>; 1413 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1414 resets = <&cpg 523>; 1415 #pwm-cells = <2>; 1416 status = "disabled"; 1417 }; 1418 1419 pwm3: pwm@e6e33000 { 1420 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1421 reg = <0 0xe6e33000 0 0x8>; 1422 clocks = <&cpg CPG_MOD 523>; 1423 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1424 resets = <&cpg 523>; 1425 #pwm-cells = <2>; 1426 status = "disabled"; 1427 }; 1428 1429 pwm4: pwm@e6e34000 { 1430 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1431 reg = <0 0xe6e34000 0 0x8>; 1432 clocks = <&cpg CPG_MOD 523>; 1433 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1434 resets = <&cpg 523>; 1435 #pwm-cells = <2>; 1436 status = "disabled"; 1437 }; 1438 1439 pwm5: pwm@e6e35000 { 1440 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1441 reg = <0 0xe6e35000 0 0x8>; 1442 clocks = <&cpg CPG_MOD 523>; 1443 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1444 resets = <&cpg 523>; 1445 #pwm-cells = <2>; 1446 status = "disabled"; 1447 }; 1448 1449 pwm6: pwm@e6e36000 { 1450 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1451 reg = <0 0xe6e36000 0 0x8>; 1452 clocks = <&cpg CPG_MOD 523>; 1453 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1454 resets = <&cpg 523>; 1455 #pwm-cells = <2>; 1456 status = "disabled"; 1457 }; 1458 1459 scif0: serial@e6e60000 { 1460 compatible = "renesas,scif-r8a7795", 1461 "renesas,rcar-gen3-scif", "renesas,scif"; 1462 reg = <0 0xe6e60000 0 64>; 1463 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1464 clocks = <&cpg CPG_MOD 207>, 1465 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1466 <&scif_clk>; 1467 clock-names = "fck", "brg_int", "scif_clk"; 1468 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1469 <&dmac2 0x51>, <&dmac2 0x50>; 1470 dma-names = "tx", "rx", "tx", "rx"; 1471 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1472 resets = <&cpg 207>; 1473 status = "disabled"; 1474 }; 1475 1476 scif1: serial@e6e68000 { 1477 compatible = "renesas,scif-r8a7795", 1478 "renesas,rcar-gen3-scif", "renesas,scif"; 1479 reg = <0 0xe6e68000 0 64>; 1480 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1481 clocks = <&cpg CPG_MOD 206>, 1482 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1483 <&scif_clk>; 1484 clock-names = "fck", "brg_int", "scif_clk"; 1485 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1486 <&dmac2 0x53>, <&dmac2 0x52>; 1487 dma-names = "tx", "rx", "tx", "rx"; 1488 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1489 resets = <&cpg 206>; 1490 status = "disabled"; 1491 }; 1492 1493 scif2: serial@e6e88000 { 1494 compatible = "renesas,scif-r8a7795", 1495 "renesas,rcar-gen3-scif", "renesas,scif"; 1496 reg = <0 0xe6e88000 0 64>; 1497 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&cpg CPG_MOD 310>, 1499 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1500 <&scif_clk>; 1501 clock-names = "fck", "brg_int", "scif_clk"; 1502 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1503 <&dmac2 0x13>, <&dmac2 0x12>; 1504 dma-names = "tx", "rx", "tx", "rx"; 1505 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1506 resets = <&cpg 310>; 1507 status = "disabled"; 1508 }; 1509 1510 scif3: serial@e6c50000 { 1511 compatible = "renesas,scif-r8a7795", 1512 "renesas,rcar-gen3-scif", "renesas,scif"; 1513 reg = <0 0xe6c50000 0 64>; 1514 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1515 clocks = <&cpg CPG_MOD 204>, 1516 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1517 <&scif_clk>; 1518 clock-names = "fck", "brg_int", "scif_clk"; 1519 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1520 dma-names = "tx", "rx"; 1521 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1522 resets = <&cpg 204>; 1523 status = "disabled"; 1524 }; 1525 1526 scif4: serial@e6c40000 { 1527 compatible = "renesas,scif-r8a7795", 1528 "renesas,rcar-gen3-scif", "renesas,scif"; 1529 reg = <0 0xe6c40000 0 64>; 1530 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1531 clocks = <&cpg CPG_MOD 203>, 1532 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1533 <&scif_clk>; 1534 clock-names = "fck", "brg_int", "scif_clk"; 1535 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1536 dma-names = "tx", "rx"; 1537 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1538 resets = <&cpg 203>; 1539 status = "disabled"; 1540 }; 1541 1542 scif5: serial@e6f30000 { 1543 compatible = "renesas,scif-r8a7795", 1544 "renesas,rcar-gen3-scif", "renesas,scif"; 1545 reg = <0 0xe6f30000 0 64>; 1546 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1547 clocks = <&cpg CPG_MOD 202>, 1548 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1549 <&scif_clk>; 1550 clock-names = "fck", "brg_int", "scif_clk"; 1551 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1552 <&dmac2 0x5b>, <&dmac2 0x5a>; 1553 dma-names = "tx", "rx", "tx", "rx"; 1554 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1555 resets = <&cpg 202>; 1556 status = "disabled"; 1557 }; 1558 1559 tpu: pwm@e6e80000 { 1560 compatible = "renesas,tpu-r8a7795", "renesas,tpu"; 1561 reg = <0 0xe6e80000 0 0x148>; 1562 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1563 clocks = <&cpg CPG_MOD 304>; 1564 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1565 resets = <&cpg 304>; 1566 #pwm-cells = <3>; 1567 status = "disabled"; 1568 }; 1569 1570 msiof0: spi@e6e90000 { 1571 compatible = "renesas,msiof-r8a7795", 1572 "renesas,rcar-gen3-msiof"; 1573 reg = <0 0xe6e90000 0 0x0064>; 1574 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&cpg CPG_MOD 211>; 1576 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1577 <&dmac2 0x41>, <&dmac2 0x40>; 1578 dma-names = "tx", "rx", "tx", "rx"; 1579 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1580 resets = <&cpg 211>; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 msiof1: spi@e6ea0000 { 1587 compatible = "renesas,msiof-r8a7795", 1588 "renesas,rcar-gen3-msiof"; 1589 reg = <0 0xe6ea0000 0 0x0064>; 1590 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&cpg CPG_MOD 210>; 1592 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1593 <&dmac2 0x43>, <&dmac2 0x42>; 1594 dma-names = "tx", "rx", "tx", "rx"; 1595 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1596 resets = <&cpg 210>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 status = "disabled"; 1600 }; 1601 1602 msiof2: spi@e6c00000 { 1603 compatible = "renesas,msiof-r8a7795", 1604 "renesas,rcar-gen3-msiof"; 1605 reg = <0 0xe6c00000 0 0x0064>; 1606 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1607 clocks = <&cpg CPG_MOD 209>; 1608 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1609 dma-names = "tx", "rx"; 1610 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1611 resets = <&cpg 209>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 msiof3: spi@e6c10000 { 1618 compatible = "renesas,msiof-r8a7795", 1619 "renesas,rcar-gen3-msiof"; 1620 reg = <0 0xe6c10000 0 0x0064>; 1621 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1622 clocks = <&cpg CPG_MOD 208>; 1623 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1624 dma-names = "tx", "rx"; 1625 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1626 resets = <&cpg 208>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 vin0: video@e6ef0000 { 1633 compatible = "renesas,vin-r8a7795"; 1634 reg = <0 0xe6ef0000 0 0x1000>; 1635 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&cpg CPG_MOD 811>; 1637 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1638 resets = <&cpg 811>; 1639 renesas,id = <0>; 1640 status = "disabled"; 1641 1642 ports { 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 1646 port@1 { 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 1650 reg = <1>; 1651 1652 vin0csi20: endpoint@0 { 1653 reg = <0>; 1654 remote-endpoint = <&csi20vin0>; 1655 }; 1656 vin0csi40: endpoint@2 { 1657 reg = <2>; 1658 remote-endpoint = <&csi40vin0>; 1659 }; 1660 }; 1661 }; 1662 }; 1663 1664 vin1: video@e6ef1000 { 1665 compatible = "renesas,vin-r8a7795"; 1666 reg = <0 0xe6ef1000 0 0x1000>; 1667 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&cpg CPG_MOD 810>; 1669 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1670 resets = <&cpg 810>; 1671 renesas,id = <1>; 1672 status = "disabled"; 1673 1674 ports { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 port@1 { 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 1682 reg = <1>; 1683 1684 vin1csi20: endpoint@0 { 1685 reg = <0>; 1686 remote-endpoint = <&csi20vin1>; 1687 }; 1688 vin1csi40: endpoint@2 { 1689 reg = <2>; 1690 remote-endpoint = <&csi40vin1>; 1691 }; 1692 }; 1693 }; 1694 }; 1695 1696 vin2: video@e6ef2000 { 1697 compatible = "renesas,vin-r8a7795"; 1698 reg = <0 0xe6ef2000 0 0x1000>; 1699 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1700 clocks = <&cpg CPG_MOD 809>; 1701 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1702 resets = <&cpg 809>; 1703 renesas,id = <2>; 1704 status = "disabled"; 1705 1706 ports { 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 1710 port@1 { 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 reg = <1>; 1715 1716 vin2csi20: endpoint@0 { 1717 reg = <0>; 1718 remote-endpoint = <&csi20vin2>; 1719 }; 1720 vin2csi40: endpoint@2 { 1721 reg = <2>; 1722 remote-endpoint = <&csi40vin2>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 vin3: video@e6ef3000 { 1729 compatible = "renesas,vin-r8a7795"; 1730 reg = <0 0xe6ef3000 0 0x1000>; 1731 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1732 clocks = <&cpg CPG_MOD 808>; 1733 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1734 resets = <&cpg 808>; 1735 renesas,id = <3>; 1736 status = "disabled"; 1737 1738 ports { 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 1742 port@1 { 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 1746 reg = <1>; 1747 1748 vin3csi20: endpoint@0 { 1749 reg = <0>; 1750 remote-endpoint = <&csi20vin3>; 1751 }; 1752 vin3csi40: endpoint@2 { 1753 reg = <2>; 1754 remote-endpoint = <&csi40vin3>; 1755 }; 1756 }; 1757 }; 1758 }; 1759 1760 vin4: video@e6ef4000 { 1761 compatible = "renesas,vin-r8a7795"; 1762 reg = <0 0xe6ef4000 0 0x1000>; 1763 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1764 clocks = <&cpg CPG_MOD 807>; 1765 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1766 resets = <&cpg 807>; 1767 renesas,id = <4>; 1768 status = "disabled"; 1769 1770 ports { 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 port@1 { 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 1778 reg = <1>; 1779 1780 vin4csi20: endpoint@0 { 1781 reg = <0>; 1782 remote-endpoint = <&csi20vin4>; 1783 }; 1784 vin4csi41: endpoint@3 { 1785 reg = <3>; 1786 remote-endpoint = <&csi41vin4>; 1787 }; 1788 }; 1789 }; 1790 }; 1791 1792 vin5: video@e6ef5000 { 1793 compatible = "renesas,vin-r8a7795"; 1794 reg = <0 0xe6ef5000 0 0x1000>; 1795 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1796 clocks = <&cpg CPG_MOD 806>; 1797 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1798 resets = <&cpg 806>; 1799 renesas,id = <5>; 1800 status = "disabled"; 1801 1802 ports { 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 port@1 { 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 1810 reg = <1>; 1811 1812 vin5csi20: endpoint@0 { 1813 reg = <0>; 1814 remote-endpoint = <&csi20vin5>; 1815 }; 1816 vin5csi41: endpoint@3 { 1817 reg = <3>; 1818 remote-endpoint = <&csi41vin5>; 1819 }; 1820 }; 1821 }; 1822 }; 1823 1824 vin6: video@e6ef6000 { 1825 compatible = "renesas,vin-r8a7795"; 1826 reg = <0 0xe6ef6000 0 0x1000>; 1827 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1828 clocks = <&cpg CPG_MOD 805>; 1829 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1830 resets = <&cpg 805>; 1831 renesas,id = <6>; 1832 status = "disabled"; 1833 1834 ports { 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 1838 port@1 { 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 1842 reg = <1>; 1843 1844 vin6csi20: endpoint@0 { 1845 reg = <0>; 1846 remote-endpoint = <&csi20vin6>; 1847 }; 1848 vin6csi41: endpoint@3 { 1849 reg = <3>; 1850 remote-endpoint = <&csi41vin6>; 1851 }; 1852 }; 1853 }; 1854 }; 1855 1856 vin7: video@e6ef7000 { 1857 compatible = "renesas,vin-r8a7795"; 1858 reg = <0 0xe6ef7000 0 0x1000>; 1859 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1860 clocks = <&cpg CPG_MOD 804>; 1861 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1862 resets = <&cpg 804>; 1863 renesas,id = <7>; 1864 status = "disabled"; 1865 1866 ports { 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 1870 port@1 { 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 1874 reg = <1>; 1875 1876 vin7csi20: endpoint@0 { 1877 reg = <0>; 1878 remote-endpoint = <&csi20vin7>; 1879 }; 1880 vin7csi41: endpoint@3 { 1881 reg = <3>; 1882 remote-endpoint = <&csi41vin7>; 1883 }; 1884 }; 1885 }; 1886 }; 1887 1888 drif00: rif@e6f40000 { 1889 compatible = "renesas,r8a7795-drif", 1890 "renesas,rcar-gen3-drif"; 1891 reg = <0 0xe6f40000 0 0x64>; 1892 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1893 clocks = <&cpg CPG_MOD 515>; 1894 clock-names = "fck"; 1895 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 1896 dma-names = "rx", "rx"; 1897 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1898 resets = <&cpg 515>; 1899 renesas,bonding = <&drif01>; 1900 status = "disabled"; 1901 }; 1902 1903 drif01: rif@e6f50000 { 1904 compatible = "renesas,r8a7795-drif", 1905 "renesas,rcar-gen3-drif"; 1906 reg = <0 0xe6f50000 0 0x64>; 1907 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1908 clocks = <&cpg CPG_MOD 514>; 1909 clock-names = "fck"; 1910 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 1911 dma-names = "rx", "rx"; 1912 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1913 resets = <&cpg 514>; 1914 renesas,bonding = <&drif00>; 1915 status = "disabled"; 1916 }; 1917 1918 drif10: rif@e6f60000 { 1919 compatible = "renesas,r8a7795-drif", 1920 "renesas,rcar-gen3-drif"; 1921 reg = <0 0xe6f60000 0 0x64>; 1922 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1923 clocks = <&cpg CPG_MOD 513>; 1924 clock-names = "fck"; 1925 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 1926 dma-names = "rx", "rx"; 1927 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1928 resets = <&cpg 513>; 1929 renesas,bonding = <&drif11>; 1930 status = "disabled"; 1931 }; 1932 1933 drif11: rif@e6f70000 { 1934 compatible = "renesas,r8a7795-drif", 1935 "renesas,rcar-gen3-drif"; 1936 reg = <0 0xe6f70000 0 0x64>; 1937 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1938 clocks = <&cpg CPG_MOD 512>; 1939 clock-names = "fck"; 1940 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 1941 dma-names = "rx", "rx"; 1942 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1943 resets = <&cpg 512>; 1944 renesas,bonding = <&drif10>; 1945 status = "disabled"; 1946 }; 1947 1948 drif20: rif@e6f80000 { 1949 compatible = "renesas,r8a7795-drif", 1950 "renesas,rcar-gen3-drif"; 1951 reg = <0 0xe6f80000 0 0x64>; 1952 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1953 clocks = <&cpg CPG_MOD 511>; 1954 clock-names = "fck"; 1955 dmas = <&dmac1 0x28>, <&dmac2 0x28>; 1956 dma-names = "rx", "rx"; 1957 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1958 resets = <&cpg 511>; 1959 renesas,bonding = <&drif21>; 1960 status = "disabled"; 1961 }; 1962 1963 drif21: rif@e6f90000 { 1964 compatible = "renesas,r8a7795-drif", 1965 "renesas,rcar-gen3-drif"; 1966 reg = <0 0xe6f90000 0 0x64>; 1967 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&cpg CPG_MOD 510>; 1969 clock-names = "fck"; 1970 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; 1971 dma-names = "rx", "rx"; 1972 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1973 resets = <&cpg 510>; 1974 renesas,bonding = <&drif20>; 1975 status = "disabled"; 1976 }; 1977 1978 drif30: rif@e6fa0000 { 1979 compatible = "renesas,r8a7795-drif", 1980 "renesas,rcar-gen3-drif"; 1981 reg = <0 0xe6fa0000 0 0x64>; 1982 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1983 clocks = <&cpg CPG_MOD 509>; 1984 clock-names = "fck"; 1985 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; 1986 dma-names = "rx", "rx"; 1987 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1988 resets = <&cpg 509>; 1989 renesas,bonding = <&drif31>; 1990 status = "disabled"; 1991 }; 1992 1993 drif31: rif@e6fb0000 { 1994 compatible = "renesas,r8a7795-drif", 1995 "renesas,rcar-gen3-drif"; 1996 reg = <0 0xe6fb0000 0 0x64>; 1997 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1998 clocks = <&cpg CPG_MOD 508>; 1999 clock-names = "fck"; 2000 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; 2001 dma-names = "rx", "rx"; 2002 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2003 resets = <&cpg 508>; 2004 renesas,bonding = <&drif30>; 2005 status = "disabled"; 2006 }; 2007 2008 rcar_sound: sound@ec500000 { 2009 /* 2010 * #sound-dai-cells is required 2011 * 2012 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 2013 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 2014 */ 2015 /* 2016 * #clock-cells is required for audio_clkout0/1/2/3 2017 * 2018 * clkout : #clock-cells = <0>; <&rcar_sound>; 2019 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 2020 */ 2021 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; 2022 reg = <0 0xec500000 0 0x1000>, /* SCU */ 2023 <0 0xec5a0000 0 0x100>, /* ADG */ 2024 <0 0xec540000 0 0x1000>, /* SSIU */ 2025 <0 0xec541000 0 0x280>, /* SSI */ 2026 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 2027 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 2028 2029 clocks = <&cpg CPG_MOD 1005>, 2030 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 2031 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 2032 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 2033 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 2034 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 2035 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 2036 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 2037 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 2038 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 2039 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 2040 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 2041 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 2042 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 2043 <&audio_clk_a>, <&audio_clk_b>, 2044 <&audio_clk_c>, 2045 <&cpg CPG_CORE R8A7795_CLK_S0D4>; 2046 clock-names = "ssi-all", 2047 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 2048 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 2049 "ssi.1", "ssi.0", 2050 "src.9", "src.8", "src.7", "src.6", 2051 "src.5", "src.4", "src.3", "src.2", 2052 "src.1", "src.0", 2053 "mix.1", "mix.0", 2054 "ctu.1", "ctu.0", 2055 "dvc.0", "dvc.1", 2056 "clk_a", "clk_b", "clk_c", "clk_i"; 2057 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2058 resets = <&cpg 1005>, 2059 <&cpg 1006>, <&cpg 1007>, 2060 <&cpg 1008>, <&cpg 1009>, 2061 <&cpg 1010>, <&cpg 1011>, 2062 <&cpg 1012>, <&cpg 1013>, 2063 <&cpg 1014>, <&cpg 1015>; 2064 reset-names = "ssi-all", 2065 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 2066 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 2067 "ssi.1", "ssi.0"; 2068 status = "disabled"; 2069 2070 rcar_sound,dvc { 2071 dvc0: dvc-0 { 2072 dmas = <&audma1 0xbc>; 2073 dma-names = "tx"; 2074 }; 2075 dvc1: dvc-1 { 2076 dmas = <&audma1 0xbe>; 2077 dma-names = "tx"; 2078 }; 2079 }; 2080 2081 rcar_sound,mix { 2082 mix0: mix-0 { }; 2083 mix1: mix-1 { }; 2084 }; 2085 2086 rcar_sound,ctu { 2087 ctu00: ctu-0 { }; 2088 ctu01: ctu-1 { }; 2089 ctu02: ctu-2 { }; 2090 ctu03: ctu-3 { }; 2091 ctu10: ctu-4 { }; 2092 ctu11: ctu-5 { }; 2093 ctu12: ctu-6 { }; 2094 ctu13: ctu-7 { }; 2095 }; 2096 2097 rcar_sound,src { 2098 src0: src-0 { 2099 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2100 dmas = <&audma0 0x85>, <&audma1 0x9a>; 2101 dma-names = "rx", "tx"; 2102 }; 2103 src1: src-1 { 2104 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2105 dmas = <&audma0 0x87>, <&audma1 0x9c>; 2106 dma-names = "rx", "tx"; 2107 }; 2108 src2: src-2 { 2109 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2110 dmas = <&audma0 0x89>, <&audma1 0x9e>; 2111 dma-names = "rx", "tx"; 2112 }; 2113 src3: src-3 { 2114 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2115 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 2116 dma-names = "rx", "tx"; 2117 }; 2118 src4: src-4 { 2119 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2120 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 2121 dma-names = "rx", "tx"; 2122 }; 2123 src5: src-5 { 2124 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2125 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 2126 dma-names = "rx", "tx"; 2127 }; 2128 src6: src-6 { 2129 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2130 dmas = <&audma0 0x91>, <&audma1 0xb4>; 2131 dma-names = "rx", "tx"; 2132 }; 2133 src7: src-7 { 2134 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2135 dmas = <&audma0 0x93>, <&audma1 0xb6>; 2136 dma-names = "rx", "tx"; 2137 }; 2138 src8: src-8 { 2139 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2140 dmas = <&audma0 0x95>, <&audma1 0xb8>; 2141 dma-names = "rx", "tx"; 2142 }; 2143 src9: src-9 { 2144 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 2145 dmas = <&audma0 0x97>, <&audma1 0xba>; 2146 dma-names = "rx", "tx"; 2147 }; 2148 }; 2149 2150 rcar_sound,ssiu { 2151 ssiu00: ssiu-0 { 2152 dmas = <&audma0 0x15>, <&audma1 0x16>; 2153 dma-names = "rx", "tx"; 2154 }; 2155 ssiu01: ssiu-1 { 2156 dmas = <&audma0 0x35>, <&audma1 0x36>; 2157 dma-names = "rx", "tx"; 2158 }; 2159 ssiu02: ssiu-2 { 2160 dmas = <&audma0 0x37>, <&audma1 0x38>; 2161 dma-names = "rx", "tx"; 2162 }; 2163 ssiu03: ssiu-3 { 2164 dmas = <&audma0 0x47>, <&audma1 0x48>; 2165 dma-names = "rx", "tx"; 2166 }; 2167 ssiu04: ssiu-4 { 2168 dmas = <&audma0 0x3F>, <&audma1 0x40>; 2169 dma-names = "rx", "tx"; 2170 }; 2171 ssiu05: ssiu-5 { 2172 dmas = <&audma0 0x43>, <&audma1 0x44>; 2173 dma-names = "rx", "tx"; 2174 }; 2175 ssiu06: ssiu-6 { 2176 dmas = <&audma0 0x4F>, <&audma1 0x50>; 2177 dma-names = "rx", "tx"; 2178 }; 2179 ssiu07: ssiu-7 { 2180 dmas = <&audma0 0x53>, <&audma1 0x54>; 2181 dma-names = "rx", "tx"; 2182 }; 2183 ssiu10: ssiu-8 { 2184 dmas = <&audma0 0x49>, <&audma1 0x4a>; 2185 dma-names = "rx", "tx"; 2186 }; 2187 ssiu11: ssiu-9 { 2188 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 2189 dma-names = "rx", "tx"; 2190 }; 2191 ssiu12: ssiu-10 { 2192 dmas = <&audma0 0x57>, <&audma1 0x58>; 2193 dma-names = "rx", "tx"; 2194 }; 2195 ssiu13: ssiu-11 { 2196 dmas = <&audma0 0x59>, <&audma1 0x5A>; 2197 dma-names = "rx", "tx"; 2198 }; 2199 ssiu14: ssiu-12 { 2200 dmas = <&audma0 0x5F>, <&audma1 0x60>; 2201 dma-names = "rx", "tx"; 2202 }; 2203 ssiu15: ssiu-13 { 2204 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 2205 dma-names = "rx", "tx"; 2206 }; 2207 ssiu16: ssiu-14 { 2208 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 2209 dma-names = "rx", "tx"; 2210 }; 2211 ssiu17: ssiu-15 { 2212 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 2213 dma-names = "rx", "tx"; 2214 }; 2215 ssiu20: ssiu-16 { 2216 dmas = <&audma0 0x63>, <&audma1 0x64>; 2217 dma-names = "rx", "tx"; 2218 }; 2219 ssiu21: ssiu-17 { 2220 dmas = <&audma0 0x67>, <&audma1 0x68>; 2221 dma-names = "rx", "tx"; 2222 }; 2223 ssiu22: ssiu-18 { 2224 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 2225 dma-names = "rx", "tx"; 2226 }; 2227 ssiu23: ssiu-19 { 2228 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 2229 dma-names = "rx", "tx"; 2230 }; 2231 ssiu24: ssiu-20 { 2232 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 2233 dma-names = "rx", "tx"; 2234 }; 2235 ssiu25: ssiu-21 { 2236 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 2237 dma-names = "rx", "tx"; 2238 }; 2239 ssiu26: ssiu-22 { 2240 dmas = <&audma0 0xED>, <&audma1 0xEE>; 2241 dma-names = "rx", "tx"; 2242 }; 2243 ssiu27: ssiu-23 { 2244 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 2245 dma-names = "rx", "tx"; 2246 }; 2247 ssiu30: ssiu-24 { 2248 dmas = <&audma0 0x6f>, <&audma1 0x70>; 2249 dma-names = "rx", "tx"; 2250 }; 2251 ssiu31: ssiu-25 { 2252 dmas = <&audma0 0x21>, <&audma1 0x22>; 2253 dma-names = "rx", "tx"; 2254 }; 2255 ssiu32: ssiu-26 { 2256 dmas = <&audma0 0x23>, <&audma1 0x24>; 2257 dma-names = "rx", "tx"; 2258 }; 2259 ssiu33: ssiu-27 { 2260 dmas = <&audma0 0x25>, <&audma1 0x26>; 2261 dma-names = "rx", "tx"; 2262 }; 2263 ssiu34: ssiu-28 { 2264 dmas = <&audma0 0x27>, <&audma1 0x28>; 2265 dma-names = "rx", "tx"; 2266 }; 2267 ssiu35: ssiu-29 { 2268 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2269 dma-names = "rx", "tx"; 2270 }; 2271 ssiu36: ssiu-30 { 2272 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2273 dma-names = "rx", "tx"; 2274 }; 2275 ssiu37: ssiu-31 { 2276 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2277 dma-names = "rx", "tx"; 2278 }; 2279 ssiu40: ssiu-32 { 2280 dmas = <&audma0 0x71>, <&audma1 0x72>; 2281 dma-names = "rx", "tx"; 2282 }; 2283 ssiu41: ssiu-33 { 2284 dmas = <&audma0 0x17>, <&audma1 0x18>; 2285 dma-names = "rx", "tx"; 2286 }; 2287 ssiu42: ssiu-34 { 2288 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2289 dma-names = "rx", "tx"; 2290 }; 2291 ssiu43: ssiu-35 { 2292 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2293 dma-names = "rx", "tx"; 2294 }; 2295 ssiu44: ssiu-36 { 2296 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2297 dma-names = "rx", "tx"; 2298 }; 2299 ssiu45: ssiu-37 { 2300 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2301 dma-names = "rx", "tx"; 2302 }; 2303 ssiu46: ssiu-38 { 2304 dmas = <&audma0 0x31>, <&audma1 0x32>; 2305 dma-names = "rx", "tx"; 2306 }; 2307 ssiu47: ssiu-39 { 2308 dmas = <&audma0 0x33>, <&audma1 0x34>; 2309 dma-names = "rx", "tx"; 2310 }; 2311 ssiu50: ssiu-40 { 2312 dmas = <&audma0 0x73>, <&audma1 0x74>; 2313 dma-names = "rx", "tx"; 2314 }; 2315 ssiu60: ssiu-41 { 2316 dmas = <&audma0 0x75>, <&audma1 0x76>; 2317 dma-names = "rx", "tx"; 2318 }; 2319 ssiu70: ssiu-42 { 2320 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2321 dma-names = "rx", "tx"; 2322 }; 2323 ssiu80: ssiu-43 { 2324 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2325 dma-names = "rx", "tx"; 2326 }; 2327 ssiu90: ssiu-44 { 2328 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2329 dma-names = "rx", "tx"; 2330 }; 2331 ssiu91: ssiu-45 { 2332 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2333 dma-names = "rx", "tx"; 2334 }; 2335 ssiu92: ssiu-46 { 2336 dmas = <&audma0 0x81>, <&audma1 0x82>; 2337 dma-names = "rx", "tx"; 2338 }; 2339 ssiu93: ssiu-47 { 2340 dmas = <&audma0 0x83>, <&audma1 0x84>; 2341 dma-names = "rx", "tx"; 2342 }; 2343 ssiu94: ssiu-48 { 2344 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2345 dma-names = "rx", "tx"; 2346 }; 2347 ssiu95: ssiu-49 { 2348 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2349 dma-names = "rx", "tx"; 2350 }; 2351 ssiu96: ssiu-50 { 2352 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2353 dma-names = "rx", "tx"; 2354 }; 2355 ssiu97: ssiu-51 { 2356 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2357 dma-names = "rx", "tx"; 2358 }; 2359 }; 2360 2361 rcar_sound,ssi { 2362 ssi0: ssi-0 { 2363 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2364 dmas = <&audma0 0x01>, <&audma1 0x02>; 2365 dma-names = "rx", "tx"; 2366 }; 2367 ssi1: ssi-1 { 2368 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2369 dmas = <&audma0 0x03>, <&audma1 0x04>; 2370 dma-names = "rx", "tx"; 2371 }; 2372 ssi2: ssi-2 { 2373 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2374 dmas = <&audma0 0x05>, <&audma1 0x06>; 2375 dma-names = "rx", "tx"; 2376 }; 2377 ssi3: ssi-3 { 2378 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2379 dmas = <&audma0 0x07>, <&audma1 0x08>; 2380 dma-names = "rx", "tx"; 2381 }; 2382 ssi4: ssi-4 { 2383 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2384 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2385 dma-names = "rx", "tx"; 2386 }; 2387 ssi5: ssi-5 { 2388 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2389 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2390 dma-names = "rx", "tx"; 2391 }; 2392 ssi6: ssi-6 { 2393 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2394 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2395 dma-names = "rx", "tx"; 2396 }; 2397 ssi7: ssi-7 { 2398 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2399 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2400 dma-names = "rx", "tx"; 2401 }; 2402 ssi8: ssi-8 { 2403 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2404 dmas = <&audma0 0x11>, <&audma1 0x12>; 2405 dma-names = "rx", "tx"; 2406 }; 2407 ssi9: ssi-9 { 2408 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2409 dmas = <&audma0 0x13>, <&audma1 0x14>; 2410 dma-names = "rx", "tx"; 2411 }; 2412 }; 2413 }; 2414 2415 audma0: dma-controller@ec700000 { 2416 compatible = "renesas,dmac-r8a7795", 2417 "renesas,rcar-dmac"; 2418 reg = <0 0xec700000 0 0x10000>; 2419 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2420 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2436 interrupt-names = "error", 2437 "ch0", "ch1", "ch2", "ch3", 2438 "ch4", "ch5", "ch6", "ch7", 2439 "ch8", "ch9", "ch10", "ch11", 2440 "ch12", "ch13", "ch14", "ch15"; 2441 clocks = <&cpg CPG_MOD 502>; 2442 clock-names = "fck"; 2443 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2444 resets = <&cpg 502>; 2445 #dma-cells = <1>; 2446 dma-channels = <16>; 2447 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2448 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2449 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2450 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2451 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2452 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2453 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2454 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2455 }; 2456 2457 audma1: dma-controller@ec720000 { 2458 compatible = "renesas,dmac-r8a7795", 2459 "renesas,rcar-dmac"; 2460 reg = <0 0xec720000 0 0x10000>; 2461 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2478 interrupt-names = "error", 2479 "ch0", "ch1", "ch2", "ch3", 2480 "ch4", "ch5", "ch6", "ch7", 2481 "ch8", "ch9", "ch10", "ch11", 2482 "ch12", "ch13", "ch14", "ch15"; 2483 clocks = <&cpg CPG_MOD 501>; 2484 clock-names = "fck"; 2485 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2486 resets = <&cpg 501>; 2487 #dma-cells = <1>; 2488 dma-channels = <16>; 2489 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2490 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2491 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2492 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2493 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2494 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2495 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2496 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2497 }; 2498 2499 xhci0: usb@ee000000 { 2500 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; 2501 reg = <0 0xee000000 0 0xc00>; 2502 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2503 clocks = <&cpg CPG_MOD 328>; 2504 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2505 resets = <&cpg 328>; 2506 status = "disabled"; 2507 }; 2508 2509 usb3_peri0: usb@ee020000 { 2510 compatible = "renesas,r8a7795-usb3-peri", 2511 "renesas,rcar-gen3-usb3-peri"; 2512 reg = <0 0xee020000 0 0x400>; 2513 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2514 clocks = <&cpg CPG_MOD 328>; 2515 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2516 resets = <&cpg 328>; 2517 status = "disabled"; 2518 }; 2519 2520 ohci0: usb@ee080000 { 2521 compatible = "generic-ohci"; 2522 reg = <0 0xee080000 0 0x100>; 2523 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2524 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2525 phys = <&usb2_phy0 1>; 2526 phy-names = "usb"; 2527 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2528 resets = <&cpg 703>, <&cpg 704>; 2529 status = "disabled"; 2530 }; 2531 2532 ohci1: usb@ee0a0000 { 2533 compatible = "generic-ohci"; 2534 reg = <0 0xee0a0000 0 0x100>; 2535 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2536 clocks = <&cpg CPG_MOD 702>; 2537 phys = <&usb2_phy1 1>; 2538 phy-names = "usb"; 2539 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2540 resets = <&cpg 702>; 2541 status = "disabled"; 2542 }; 2543 2544 ohci2: usb@ee0c0000 { 2545 compatible = "generic-ohci"; 2546 reg = <0 0xee0c0000 0 0x100>; 2547 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2548 clocks = <&cpg CPG_MOD 701>; 2549 phys = <&usb2_phy2 1>; 2550 phy-names = "usb"; 2551 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2552 resets = <&cpg 701>; 2553 status = "disabled"; 2554 }; 2555 2556 ohci3: usb@ee0e0000 { 2557 compatible = "generic-ohci"; 2558 reg = <0 0xee0e0000 0 0x100>; 2559 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2560 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2561 phys = <&usb2_phy3 1>; 2562 phy-names = "usb"; 2563 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2564 resets = <&cpg 700>, <&cpg 705>; 2565 status = "disabled"; 2566 }; 2567 2568 ehci0: usb@ee080100 { 2569 compatible = "generic-ehci"; 2570 reg = <0 0xee080100 0 0x100>; 2571 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2572 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2573 phys = <&usb2_phy0 2>; 2574 phy-names = "usb"; 2575 companion = <&ohci0>; 2576 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2577 resets = <&cpg 703>, <&cpg 704>; 2578 status = "disabled"; 2579 }; 2580 2581 ehci1: usb@ee0a0100 { 2582 compatible = "generic-ehci"; 2583 reg = <0 0xee0a0100 0 0x100>; 2584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2585 clocks = <&cpg CPG_MOD 702>; 2586 phys = <&usb2_phy1 2>; 2587 phy-names = "usb"; 2588 companion = <&ohci1>; 2589 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2590 resets = <&cpg 702>; 2591 status = "disabled"; 2592 }; 2593 2594 ehci2: usb@ee0c0100 { 2595 compatible = "generic-ehci"; 2596 reg = <0 0xee0c0100 0 0x100>; 2597 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2598 clocks = <&cpg CPG_MOD 701>; 2599 phys = <&usb2_phy2 2>; 2600 phy-names = "usb"; 2601 companion = <&ohci2>; 2602 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2603 resets = <&cpg 701>; 2604 status = "disabled"; 2605 }; 2606 2607 ehci3: usb@ee0e0100 { 2608 compatible = "generic-ehci"; 2609 reg = <0 0xee0e0100 0 0x100>; 2610 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2611 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2612 phys = <&usb2_phy3 2>; 2613 phy-names = "usb"; 2614 companion = <&ohci3>; 2615 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2616 resets = <&cpg 700>, <&cpg 705>; 2617 status = "disabled"; 2618 }; 2619 2620 usb2_phy0: usb-phy@ee080200 { 2621 compatible = "renesas,usb2-phy-r8a7795", 2622 "renesas,rcar-gen3-usb2-phy"; 2623 reg = <0 0xee080200 0 0x700>; 2624 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2625 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2626 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2627 resets = <&cpg 703>, <&cpg 704>; 2628 #phy-cells = <1>; 2629 status = "disabled"; 2630 }; 2631 2632 usb2_phy1: usb-phy@ee0a0200 { 2633 compatible = "renesas,usb2-phy-r8a7795", 2634 "renesas,rcar-gen3-usb2-phy"; 2635 reg = <0 0xee0a0200 0 0x700>; 2636 clocks = <&cpg CPG_MOD 702>; 2637 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2638 resets = <&cpg 702>; 2639 #phy-cells = <1>; 2640 status = "disabled"; 2641 }; 2642 2643 usb2_phy2: usb-phy@ee0c0200 { 2644 compatible = "renesas,usb2-phy-r8a7795", 2645 "renesas,rcar-gen3-usb2-phy"; 2646 reg = <0 0xee0c0200 0 0x700>; 2647 clocks = <&cpg CPG_MOD 701>; 2648 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2649 resets = <&cpg 701>; 2650 #phy-cells = <1>; 2651 status = "disabled"; 2652 }; 2653 2654 usb2_phy3: usb-phy@ee0e0200 { 2655 compatible = "renesas,usb2-phy-r8a7795", 2656 "renesas,rcar-gen3-usb2-phy"; 2657 reg = <0 0xee0e0200 0 0x700>; 2658 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2659 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2660 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2661 resets = <&cpg 700>, <&cpg 705>; 2662 #phy-cells = <1>; 2663 status = "disabled"; 2664 }; 2665 2666 sdhi0: mmc@ee100000 { 2667 compatible = "renesas,sdhi-r8a7795", 2668 "renesas,rcar-gen3-sdhi"; 2669 reg = <0 0xee100000 0 0x2000>; 2670 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2671 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; 2672 clock-names = "core", "clkh"; 2673 max-frequency = <200000000>; 2674 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2675 resets = <&cpg 314>; 2676 iommus = <&ipmmu_ds1 32>; 2677 status = "disabled"; 2678 }; 2679 2680 sdhi1: mmc@ee120000 { 2681 compatible = "renesas,sdhi-r8a7795", 2682 "renesas,rcar-gen3-sdhi"; 2683 reg = <0 0xee120000 0 0x2000>; 2684 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2685 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; 2686 clock-names = "core", "clkh"; 2687 max-frequency = <200000000>; 2688 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2689 resets = <&cpg 313>; 2690 iommus = <&ipmmu_ds1 33>; 2691 status = "disabled"; 2692 }; 2693 2694 sdhi2: mmc@ee140000 { 2695 compatible = "renesas,sdhi-r8a7795", 2696 "renesas,rcar-gen3-sdhi"; 2697 reg = <0 0xee140000 0 0x2000>; 2698 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2699 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; 2700 clock-names = "core", "clkh"; 2701 max-frequency = <200000000>; 2702 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2703 resets = <&cpg 312>; 2704 iommus = <&ipmmu_ds1 34>; 2705 status = "disabled"; 2706 }; 2707 2708 sdhi3: mmc@ee160000 { 2709 compatible = "renesas,sdhi-r8a7795", 2710 "renesas,rcar-gen3-sdhi"; 2711 reg = <0 0xee160000 0 0x2000>; 2712 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2713 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; 2714 clock-names = "core", "clkh"; 2715 max-frequency = <200000000>; 2716 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2717 resets = <&cpg 311>; 2718 iommus = <&ipmmu_ds1 35>; 2719 status = "disabled"; 2720 }; 2721 2722 sata: sata@ee300000 { 2723 compatible = "renesas,sata-r8a7795", 2724 "renesas,rcar-gen3-sata"; 2725 reg = <0 0xee300000 0 0x200000>; 2726 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2727 clocks = <&cpg CPG_MOD 815>; 2728 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2729 resets = <&cpg 815>; 2730 status = "disabled"; 2731 iommus = <&ipmmu_hc 2>; 2732 }; 2733 2734 gic: interrupt-controller@f1010000 { 2735 compatible = "arm,gic-400"; 2736 #interrupt-cells = <3>; 2737 #address-cells = <0>; 2738 interrupt-controller; 2739 reg = <0x0 0xf1010000 0 0x1000>, 2740 <0x0 0xf1020000 0 0x20000>, 2741 <0x0 0xf1040000 0 0x20000>, 2742 <0x0 0xf1060000 0 0x20000>; 2743 interrupts = <GIC_PPI 9 2744 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2745 clocks = <&cpg CPG_MOD 408>; 2746 clock-names = "clk"; 2747 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2748 resets = <&cpg 408>; 2749 }; 2750 2751 pciec0: pcie@fe000000 { 2752 compatible = "renesas,pcie-r8a7795", 2753 "renesas,pcie-rcar-gen3"; 2754 reg = <0 0xfe000000 0 0x80000>; 2755 #address-cells = <3>; 2756 #size-cells = <2>; 2757 bus-range = <0x00 0xff>; 2758 device_type = "pci"; 2759 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2760 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2761 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2762 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2763 /* Map all possible DDR as inbound ranges */ 2764 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 2765 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2768 #interrupt-cells = <1>; 2769 interrupt-map-mask = <0 0 0 0>; 2770 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2771 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2772 clock-names = "pcie", "pcie_bus"; 2773 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2774 resets = <&cpg 319>; 2775 status = "disabled"; 2776 }; 2777 2778 pciec1: pcie@ee800000 { 2779 compatible = "renesas,pcie-r8a7795", 2780 "renesas,pcie-rcar-gen3"; 2781 reg = <0 0xee800000 0 0x80000>; 2782 #address-cells = <3>; 2783 #size-cells = <2>; 2784 bus-range = <0x00 0xff>; 2785 device_type = "pci"; 2786 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2787 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2788 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2789 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2790 /* Map all possible DDR as inbound ranges */ 2791 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 2792 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2795 #interrupt-cells = <1>; 2796 interrupt-map-mask = <0 0 0 0>; 2797 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2798 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2799 clock-names = "pcie", "pcie_bus"; 2800 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2801 resets = <&cpg 318>; 2802 status = "disabled"; 2803 }; 2804 2805 pciec0_ep: pcie-ep@fe000000 { 2806 compatible = "renesas,r8a7795-pcie-ep", 2807 "renesas,rcar-gen3-pcie-ep"; 2808 reg = <0x0 0xfe000000 0 0x80000>, 2809 <0x0 0xfe100000 0 0x100000>, 2810 <0x0 0xfe200000 0 0x200000>, 2811 <0x0 0x30000000 0 0x8000000>, 2812 <0x0 0x38000000 0 0x8000000>; 2813 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2814 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2817 clocks = <&cpg CPG_MOD 319>; 2818 clock-names = "pcie"; 2819 resets = <&cpg 319>; 2820 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2821 status = "disabled"; 2822 }; 2823 2824 pciec1_ep: pcie-ep@ee800000 { 2825 compatible = "renesas,r8a7795-pcie-ep", 2826 "renesas,rcar-gen3-pcie-ep"; 2827 reg = <0x0 0xee800000 0 0x80000>, 2828 <0x0 0xee900000 0 0x100000>, 2829 <0x0 0xeea00000 0 0x200000>, 2830 <0x0 0xc0000000 0 0x8000000>, 2831 <0x0 0xc8000000 0 0x8000000>; 2832 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2833 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2836 clocks = <&cpg CPG_MOD 318>; 2837 clock-names = "pcie"; 2838 resets = <&cpg 318>; 2839 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2840 status = "disabled"; 2841 }; 2842 2843 imr-lx4@fe860000 { 2844 compatible = "renesas,r8a7795-imr-lx4", 2845 "renesas,imr-lx4"; 2846 reg = <0 0xfe860000 0 0x2000>; 2847 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2848 clocks = <&cpg CPG_MOD 823>; 2849 power-domains = <&sysc R8A7795_PD_A3VC>; 2850 resets = <&cpg 823>; 2851 }; 2852 2853 imr-lx4@fe870000 { 2854 compatible = "renesas,r8a7795-imr-lx4", 2855 "renesas,imr-lx4"; 2856 reg = <0 0xfe870000 0 0x2000>; 2857 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2858 clocks = <&cpg CPG_MOD 822>; 2859 power-domains = <&sysc R8A7795_PD_A3VC>; 2860 resets = <&cpg 822>; 2861 }; 2862 2863 imr-lx4@fe880000 { 2864 compatible = "renesas,r8a7795-imr-lx4", 2865 "renesas,imr-lx4"; 2866 reg = <0 0xfe880000 0 0x2000>; 2867 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 2868 clocks = <&cpg CPG_MOD 821>; 2869 power-domains = <&sysc R8A7795_PD_A3VC>; 2870 resets = <&cpg 821>; 2871 }; 2872 2873 imr-lx4@fe890000 { 2874 compatible = "renesas,r8a7795-imr-lx4", 2875 "renesas,imr-lx4"; 2876 reg = <0 0xfe890000 0 0x2000>; 2877 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 2878 clocks = <&cpg CPG_MOD 820>; 2879 power-domains = <&sysc R8A7795_PD_A3VC>; 2880 resets = <&cpg 820>; 2881 }; 2882 2883 vspbc: vsp@fe920000 { 2884 compatible = "renesas,vsp2"; 2885 reg = <0 0xfe920000 0 0x8000>; 2886 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2887 clocks = <&cpg CPG_MOD 624>; 2888 power-domains = <&sysc R8A7795_PD_A3VP>; 2889 resets = <&cpg 624>; 2890 2891 renesas,fcp = <&fcpvb1>; 2892 }; 2893 2894 vspbd: vsp@fe960000 { 2895 compatible = "renesas,vsp2"; 2896 reg = <0 0xfe960000 0 0x8000>; 2897 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2898 clocks = <&cpg CPG_MOD 626>; 2899 power-domains = <&sysc R8A7795_PD_A3VP>; 2900 resets = <&cpg 626>; 2901 2902 renesas,fcp = <&fcpvb0>; 2903 }; 2904 2905 vspd0: vsp@fea20000 { 2906 compatible = "renesas,vsp2"; 2907 reg = <0 0xfea20000 0 0x5000>; 2908 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2909 clocks = <&cpg CPG_MOD 623>; 2910 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2911 resets = <&cpg 623>; 2912 2913 renesas,fcp = <&fcpvd0>; 2914 }; 2915 2916 vspd1: vsp@fea28000 { 2917 compatible = "renesas,vsp2"; 2918 reg = <0 0xfea28000 0 0x5000>; 2919 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2920 clocks = <&cpg CPG_MOD 622>; 2921 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2922 resets = <&cpg 622>; 2923 2924 renesas,fcp = <&fcpvd1>; 2925 }; 2926 2927 vspd2: vsp@fea30000 { 2928 compatible = "renesas,vsp2"; 2929 reg = <0 0xfea30000 0 0x5000>; 2930 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2931 clocks = <&cpg CPG_MOD 621>; 2932 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2933 resets = <&cpg 621>; 2934 2935 renesas,fcp = <&fcpvd2>; 2936 }; 2937 2938 vspi0: vsp@fe9a0000 { 2939 compatible = "renesas,vsp2"; 2940 reg = <0 0xfe9a0000 0 0x8000>; 2941 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2942 clocks = <&cpg CPG_MOD 631>; 2943 power-domains = <&sysc R8A7795_PD_A3VP>; 2944 resets = <&cpg 631>; 2945 2946 renesas,fcp = <&fcpvi0>; 2947 }; 2948 2949 vspi1: vsp@fe9b0000 { 2950 compatible = "renesas,vsp2"; 2951 reg = <0 0xfe9b0000 0 0x8000>; 2952 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 2953 clocks = <&cpg CPG_MOD 630>; 2954 power-domains = <&sysc R8A7795_PD_A3VP>; 2955 resets = <&cpg 630>; 2956 2957 renesas,fcp = <&fcpvi1>; 2958 }; 2959 2960 fdp1@fe940000 { 2961 compatible = "renesas,fdp1"; 2962 reg = <0 0xfe940000 0 0x2400>; 2963 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2964 clocks = <&cpg CPG_MOD 119>; 2965 power-domains = <&sysc R8A7795_PD_A3VP>; 2966 resets = <&cpg 119>; 2967 renesas,fcp = <&fcpf0>; 2968 }; 2969 2970 fdp1@fe944000 { 2971 compatible = "renesas,fdp1"; 2972 reg = <0 0xfe944000 0 0x2400>; 2973 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2974 clocks = <&cpg CPG_MOD 118>; 2975 power-domains = <&sysc R8A7795_PD_A3VP>; 2976 resets = <&cpg 118>; 2977 renesas,fcp = <&fcpf1>; 2978 }; 2979 2980 fcpf0: fcp@fe950000 { 2981 compatible = "renesas,fcpf"; 2982 reg = <0 0xfe950000 0 0x200>; 2983 clocks = <&cpg CPG_MOD 615>; 2984 power-domains = <&sysc R8A7795_PD_A3VP>; 2985 resets = <&cpg 615>; 2986 iommus = <&ipmmu_vp0 0>; 2987 }; 2988 2989 fcpf1: fcp@fe951000 { 2990 compatible = "renesas,fcpf"; 2991 reg = <0 0xfe951000 0 0x200>; 2992 clocks = <&cpg CPG_MOD 614>; 2993 power-domains = <&sysc R8A7795_PD_A3VP>; 2994 resets = <&cpg 614>; 2995 iommus = <&ipmmu_vp1 1>; 2996 }; 2997 2998 fcpvb0: fcp@fe96f000 { 2999 compatible = "renesas,fcpv"; 3000 reg = <0 0xfe96f000 0 0x200>; 3001 clocks = <&cpg CPG_MOD 607>; 3002 power-domains = <&sysc R8A7795_PD_A3VP>; 3003 resets = <&cpg 607>; 3004 iommus = <&ipmmu_vp0 5>; 3005 }; 3006 3007 fcpvb1: fcp@fe92f000 { 3008 compatible = "renesas,fcpv"; 3009 reg = <0 0xfe92f000 0 0x200>; 3010 clocks = <&cpg CPG_MOD 606>; 3011 power-domains = <&sysc R8A7795_PD_A3VP>; 3012 resets = <&cpg 606>; 3013 iommus = <&ipmmu_vp1 7>; 3014 }; 3015 3016 fcpvi0: fcp@fe9af000 { 3017 compatible = "renesas,fcpv"; 3018 reg = <0 0xfe9af000 0 0x200>; 3019 clocks = <&cpg CPG_MOD 611>; 3020 power-domains = <&sysc R8A7795_PD_A3VP>; 3021 resets = <&cpg 611>; 3022 iommus = <&ipmmu_vp0 8>; 3023 }; 3024 3025 fcpvi1: fcp@fe9bf000 { 3026 compatible = "renesas,fcpv"; 3027 reg = <0 0xfe9bf000 0 0x200>; 3028 clocks = <&cpg CPG_MOD 610>; 3029 power-domains = <&sysc R8A7795_PD_A3VP>; 3030 resets = <&cpg 610>; 3031 iommus = <&ipmmu_vp1 9>; 3032 }; 3033 3034 fcpvd0: fcp@fea27000 { 3035 compatible = "renesas,fcpv"; 3036 reg = <0 0xfea27000 0 0x200>; 3037 clocks = <&cpg CPG_MOD 603>; 3038 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3039 resets = <&cpg 603>; 3040 iommus = <&ipmmu_vi0 8>; 3041 }; 3042 3043 fcpvd1: fcp@fea2f000 { 3044 compatible = "renesas,fcpv"; 3045 reg = <0 0xfea2f000 0 0x200>; 3046 clocks = <&cpg CPG_MOD 602>; 3047 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3048 resets = <&cpg 602>; 3049 iommus = <&ipmmu_vi0 9>; 3050 }; 3051 3052 fcpvd2: fcp@fea37000 { 3053 compatible = "renesas,fcpv"; 3054 reg = <0 0xfea37000 0 0x200>; 3055 clocks = <&cpg CPG_MOD 601>; 3056 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3057 resets = <&cpg 601>; 3058 iommus = <&ipmmu_vi1 10>; 3059 }; 3060 3061 cmm0: cmm@fea40000 { 3062 compatible = "renesas,r8a7795-cmm", 3063 "renesas,rcar-gen3-cmm"; 3064 reg = <0 0xfea40000 0 0x1000>; 3065 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3066 clocks = <&cpg CPG_MOD 711>; 3067 resets = <&cpg 711>; 3068 }; 3069 3070 cmm1: cmm@fea50000 { 3071 compatible = "renesas,r8a7795-cmm", 3072 "renesas,rcar-gen3-cmm"; 3073 reg = <0 0xfea50000 0 0x1000>; 3074 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3075 clocks = <&cpg CPG_MOD 710>; 3076 resets = <&cpg 710>; 3077 }; 3078 3079 cmm2: cmm@fea60000 { 3080 compatible = "renesas,r8a7795-cmm", 3081 "renesas,rcar-gen3-cmm"; 3082 reg = <0 0xfea60000 0 0x1000>; 3083 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3084 clocks = <&cpg CPG_MOD 709>; 3085 resets = <&cpg 709>; 3086 }; 3087 3088 cmm3: cmm@fea70000 { 3089 compatible = "renesas,r8a7795-cmm", 3090 "renesas,rcar-gen3-cmm"; 3091 reg = <0 0xfea70000 0 0x1000>; 3092 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3093 clocks = <&cpg CPG_MOD 708>; 3094 resets = <&cpg 708>; 3095 }; 3096 3097 csi20: csi2@fea80000 { 3098 compatible = "renesas,r8a7795-csi2"; 3099 reg = <0 0xfea80000 0 0x10000>; 3100 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 3101 clocks = <&cpg CPG_MOD 714>; 3102 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3103 resets = <&cpg 714>; 3104 status = "disabled"; 3105 3106 ports { 3107 #address-cells = <1>; 3108 #size-cells = <0>; 3109 3110 port@0 { 3111 reg = <0>; 3112 }; 3113 3114 port@1 { 3115 #address-cells = <1>; 3116 #size-cells = <0>; 3117 3118 reg = <1>; 3119 3120 csi20vin0: endpoint@0 { 3121 reg = <0>; 3122 remote-endpoint = <&vin0csi20>; 3123 }; 3124 csi20vin1: endpoint@1 { 3125 reg = <1>; 3126 remote-endpoint = <&vin1csi20>; 3127 }; 3128 csi20vin2: endpoint@2 { 3129 reg = <2>; 3130 remote-endpoint = <&vin2csi20>; 3131 }; 3132 csi20vin3: endpoint@3 { 3133 reg = <3>; 3134 remote-endpoint = <&vin3csi20>; 3135 }; 3136 csi20vin4: endpoint@4 { 3137 reg = <4>; 3138 remote-endpoint = <&vin4csi20>; 3139 }; 3140 csi20vin5: endpoint@5 { 3141 reg = <5>; 3142 remote-endpoint = <&vin5csi20>; 3143 }; 3144 csi20vin6: endpoint@6 { 3145 reg = <6>; 3146 remote-endpoint = <&vin6csi20>; 3147 }; 3148 csi20vin7: endpoint@7 { 3149 reg = <7>; 3150 remote-endpoint = <&vin7csi20>; 3151 }; 3152 }; 3153 }; 3154 }; 3155 3156 csi40: csi2@feaa0000 { 3157 compatible = "renesas,r8a7795-csi2"; 3158 reg = <0 0xfeaa0000 0 0x10000>; 3159 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 3160 clocks = <&cpg CPG_MOD 716>; 3161 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3162 resets = <&cpg 716>; 3163 status = "disabled"; 3164 3165 ports { 3166 #address-cells = <1>; 3167 #size-cells = <0>; 3168 3169 port@0 { 3170 reg = <0>; 3171 }; 3172 3173 port@1 { 3174 #address-cells = <1>; 3175 #size-cells = <0>; 3176 3177 reg = <1>; 3178 3179 csi40vin0: endpoint@0 { 3180 reg = <0>; 3181 remote-endpoint = <&vin0csi40>; 3182 }; 3183 csi40vin1: endpoint@1 { 3184 reg = <1>; 3185 remote-endpoint = <&vin1csi40>; 3186 }; 3187 csi40vin2: endpoint@2 { 3188 reg = <2>; 3189 remote-endpoint = <&vin2csi40>; 3190 }; 3191 csi40vin3: endpoint@3 { 3192 reg = <3>; 3193 remote-endpoint = <&vin3csi40>; 3194 }; 3195 }; 3196 }; 3197 }; 3198 3199 csi41: csi2@feab0000 { 3200 compatible = "renesas,r8a7795-csi2"; 3201 reg = <0 0xfeab0000 0 0x10000>; 3202 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 3203 clocks = <&cpg CPG_MOD 715>; 3204 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3205 resets = <&cpg 715>; 3206 status = "disabled"; 3207 3208 ports { 3209 #address-cells = <1>; 3210 #size-cells = <0>; 3211 3212 port@0 { 3213 reg = <0>; 3214 }; 3215 3216 port@1 { 3217 #address-cells = <1>; 3218 #size-cells = <0>; 3219 3220 reg = <1>; 3221 3222 csi41vin4: endpoint@0 { 3223 reg = <0>; 3224 remote-endpoint = <&vin4csi41>; 3225 }; 3226 csi41vin5: endpoint@1 { 3227 reg = <1>; 3228 remote-endpoint = <&vin5csi41>; 3229 }; 3230 csi41vin6: endpoint@2 { 3231 reg = <2>; 3232 remote-endpoint = <&vin6csi41>; 3233 }; 3234 csi41vin7: endpoint@3 { 3235 reg = <3>; 3236 remote-endpoint = <&vin7csi41>; 3237 }; 3238 }; 3239 }; 3240 }; 3241 3242 hdmi0: hdmi@fead0000 { 3243 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 3244 reg = <0 0xfead0000 0 0x10000>; 3245 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 3246 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 3247 clock-names = "iahb", "isfr"; 3248 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3249 resets = <&cpg 729>; 3250 status = "disabled"; 3251 3252 ports { 3253 #address-cells = <1>; 3254 #size-cells = <0>; 3255 port@0 { 3256 reg = <0>; 3257 dw_hdmi0_in: endpoint { 3258 remote-endpoint = <&du_out_hdmi0>; 3259 }; 3260 }; 3261 port@1 { 3262 reg = <1>; 3263 }; 3264 port@2 { 3265 /* HDMI sound */ 3266 reg = <2>; 3267 }; 3268 }; 3269 }; 3270 3271 hdmi1: hdmi@feae0000 { 3272 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 3273 reg = <0 0xfeae0000 0 0x10000>; 3274 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; 3275 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 3276 clock-names = "iahb", "isfr"; 3277 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3278 resets = <&cpg 728>; 3279 status = "disabled"; 3280 3281 ports { 3282 #address-cells = <1>; 3283 #size-cells = <0>; 3284 port@0 { 3285 reg = <0>; 3286 dw_hdmi1_in: endpoint { 3287 remote-endpoint = <&du_out_hdmi1>; 3288 }; 3289 }; 3290 port@1 { 3291 reg = <1>; 3292 }; 3293 port@2 { 3294 /* HDMI sound */ 3295 reg = <2>; 3296 }; 3297 }; 3298 }; 3299 3300 du: display@feb00000 { 3301 compatible = "renesas,du-r8a7795"; 3302 reg = <0 0xfeb00000 0 0x80000>; 3303 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 3307 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 3308 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; 3309 clock-names = "du.0", "du.1", "du.2", "du.3"; 3310 resets = <&cpg 724>, <&cpg 722>; 3311 reset-names = "du.0", "du.2"; 3312 3313 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; 3314 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, 3315 <&vspd0 1>; 3316 3317 status = "disabled"; 3318 3319 ports { 3320 #address-cells = <1>; 3321 #size-cells = <0>; 3322 3323 port@0 { 3324 reg = <0>; 3325 du_out_rgb: endpoint { 3326 }; 3327 }; 3328 port@1 { 3329 reg = <1>; 3330 du_out_hdmi0: endpoint { 3331 remote-endpoint = <&dw_hdmi0_in>; 3332 }; 3333 }; 3334 port@2 { 3335 reg = <2>; 3336 du_out_hdmi1: endpoint { 3337 remote-endpoint = <&dw_hdmi1_in>; 3338 }; 3339 }; 3340 port@3 { 3341 reg = <3>; 3342 du_out_lvds0: endpoint { 3343 remote-endpoint = <&lvds0_in>; 3344 }; 3345 }; 3346 }; 3347 }; 3348 3349 lvds0: lvds@feb90000 { 3350 compatible = "renesas,r8a7795-lvds"; 3351 reg = <0 0xfeb90000 0 0x14>; 3352 clocks = <&cpg CPG_MOD 727>; 3353 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3354 resets = <&cpg 727>; 3355 status = "disabled"; 3356 3357 ports { 3358 #address-cells = <1>; 3359 #size-cells = <0>; 3360 3361 port@0 { 3362 reg = <0>; 3363 lvds0_in: endpoint { 3364 remote-endpoint = <&du_out_lvds0>; 3365 }; 3366 }; 3367 port@1 { 3368 reg = <1>; 3369 lvds0_out: endpoint { 3370 }; 3371 }; 3372 }; 3373 }; 3374 3375 prr: chipid@fff00044 { 3376 compatible = "renesas,prr"; 3377 reg = <0 0xfff00044 0 4>; 3378 }; 3379 }; 3380 3381 thermal-zones { 3382 sensor1_thermal: sensor1-thermal { 3383 polling-delay-passive = <250>; 3384 polling-delay = <1000>; 3385 thermal-sensors = <&tsc 0>; 3386 sustainable-power = <6313>; 3387 3388 trips { 3389 sensor1_crit: sensor1-crit { 3390 temperature = <120000>; 3391 hysteresis = <1000>; 3392 type = "critical"; 3393 }; 3394 }; 3395 }; 3396 3397 sensor2_thermal: sensor2-thermal { 3398 polling-delay-passive = <250>; 3399 polling-delay = <1000>; 3400 thermal-sensors = <&tsc 1>; 3401 sustainable-power = <6313>; 3402 3403 trips { 3404 sensor2_crit: sensor2-crit { 3405 temperature = <120000>; 3406 hysteresis = <1000>; 3407 type = "critical"; 3408 }; 3409 }; 3410 }; 3411 3412 sensor3_thermal: sensor3-thermal { 3413 polling-delay-passive = <250>; 3414 polling-delay = <1000>; 3415 thermal-sensors = <&tsc 2>; 3416 3417 trips { 3418 target: trip-point1 { 3419 temperature = <100000>; 3420 hysteresis = <1000>; 3421 type = "passive"; 3422 }; 3423 3424 sensor3_crit: sensor3-crit { 3425 temperature = <120000>; 3426 hysteresis = <1000>; 3427 type = "critical"; 3428 }; 3429 }; 3430 3431 cooling-maps { 3432 map0 { 3433 trip = <&target>; 3434 cooling-device = <&a57_0 2 4>; 3435 contribution = <1024>; 3436 }; 3437 3438 map1 { 3439 trip = <&target>; 3440 cooling-device = <&a53_0 0 2>; 3441 contribution = <1024>; 3442 }; 3443 }; 3444 }; 3445 }; 3446 3447 timer { 3448 compatible = "arm,armv8-timer"; 3449 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3450 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3451 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3452 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3453 }; 3454 3455 /* External USB clocks - can be overridden by the board */ 3456 usb3s0_clk: usb3s0 { 3457 compatible = "fixed-clock"; 3458 #clock-cells = <0>; 3459 clock-frequency = <0>; 3460 }; 3461 3462 usb_extal_clk: usb_extal { 3463 compatible = "fixed-clock"; 3464 #clock-cells = <0>; 3465 clock-frequency = <0>; 3466 }; 3467}; 3468