1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11#include <dt-bindings/power/r8a774e1-sysc.h>
12
13#define CPG_AUDIO_CLK_I		R8A774E1_CLK_S0D4
14
15/ {
16	compatible = "renesas,r8a774e1";
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	/*
21	 * The external audio clocks are configured as 0 Hz fixed frequency
22	 * clocks by default.
23	 * Boards that provide audio clocks should override them.
24	 */
25	audio_clk_a: audio_clk_a {
26		compatible = "fixed-clock";
27		#clock-cells = <0>;
28		clock-frequency = <0>;
29	};
30
31	audio_clk_b: audio_clk_b {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <0>;
35	};
36
37	audio_clk_c: audio_clk_c {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <0>;
41	};
42
43	/* External CAN clock - to be overridden by boards that provide it */
44	can_clk: can {
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <0>;
48	};
49
50	cluster0_opp: opp-table-0 {
51		compatible = "operating-points-v2";
52		opp-shared;
53
54		opp-500000000 {
55			opp-hz = /bits/ 64 <500000000>;
56			opp-microvolt = <820000>;
57			clock-latency-ns = <300000>;
58		};
59		opp-1000000000 {
60			opp-hz = /bits/ 64 <1000000000>;
61			opp-microvolt = <820000>;
62			clock-latency-ns = <300000>;
63		};
64		opp-1500000000 {
65			opp-hz = /bits/ 64 <1500000000>;
66			opp-microvolt = <820000>;
67			clock-latency-ns = <300000>;
68			opp-suspend;
69		};
70	};
71
72	cluster1_opp: opp-table-1 {
73		compatible = "operating-points-v2";
74		opp-shared;
75
76		opp-800000000 {
77			opp-hz = /bits/ 64 <800000000>;
78			opp-microvolt = <820000>;
79			clock-latency-ns = <300000>;
80		};
81		opp-1000000000 {
82			opp-hz = /bits/ 64 <1000000000>;
83			opp-microvolt = <820000>;
84			clock-latency-ns = <300000>;
85		};
86		opp-1200000000 {
87			opp-hz = /bits/ 64 <1200000000>;
88			opp-microvolt = <820000>;
89			clock-latency-ns = <300000>;
90		};
91	};
92
93	cpus {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		cpu-map {
98			cluster0 {
99				core0 {
100					cpu = <&a57_0>;
101				};
102				core1 {
103					cpu = <&a57_1>;
104				};
105				core2 {
106					cpu = <&a57_2>;
107				};
108				core3 {
109					cpu = <&a57_3>;
110				};
111			};
112
113			cluster1 {
114				core0 {
115					cpu = <&a53_0>;
116				};
117				core1 {
118					cpu = <&a53_1>;
119				};
120				core2 {
121					cpu = <&a53_2>;
122				};
123				core3 {
124					cpu = <&a53_3>;
125				};
126			};
127		};
128
129		a57_0: cpu@0 {
130			compatible = "arm,cortex-a57";
131			reg = <0x0>;
132			device_type = "cpu";
133			power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
134			next-level-cache = <&L2_CA57>;
135			enable-method = "psci";
136			cpu-idle-states = <&CPU_SLEEP_0>;
137			dynamic-power-coefficient = <854>;
138			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
139			operating-points-v2 = <&cluster0_opp>;
140			capacity-dmips-mhz = <1024>;
141			#cooling-cells = <2>;
142		};
143
144		a57_1: cpu@1 {
145			compatible = "arm,cortex-a57";
146			reg = <0x1>;
147			device_type = "cpu";
148			power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
149			next-level-cache = <&L2_CA57>;
150			enable-method = "psci";
151			cpu-idle-states = <&CPU_SLEEP_0>;
152			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
153			operating-points-v2 = <&cluster0_opp>;
154			capacity-dmips-mhz = <1024>;
155			#cooling-cells = <2>;
156		};
157
158		a57_2: cpu@2 {
159			compatible = "arm,cortex-a57";
160			reg = <0x2>;
161			device_type = "cpu";
162			power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
163			next-level-cache = <&L2_CA57>;
164			enable-method = "psci";
165			cpu-idle-states = <&CPU_SLEEP_0>;
166			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
167			operating-points-v2 = <&cluster0_opp>;
168			capacity-dmips-mhz = <1024>;
169			#cooling-cells = <2>;
170		};
171
172		a57_3: cpu@3 {
173			compatible = "arm,cortex-a57";
174			reg = <0x3>;
175			device_type = "cpu";
176			power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
177			next-level-cache = <&L2_CA57>;
178			enable-method = "psci";
179			cpu-idle-states = <&CPU_SLEEP_0>;
180			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
181			operating-points-v2 = <&cluster0_opp>;
182			capacity-dmips-mhz = <1024>;
183			#cooling-cells = <2>;
184		};
185
186		a53_0: cpu@100 {
187			compatible = "arm,cortex-a53";
188			reg = <0x100>;
189			device_type = "cpu";
190			power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
191			next-level-cache = <&L2_CA53>;
192			enable-method = "psci";
193			cpu-idle-states = <&CPU_SLEEP_1>;
194			#cooling-cells = <2>;
195			dynamic-power-coefficient = <277>;
196			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
197			operating-points-v2 = <&cluster1_opp>;
198			capacity-dmips-mhz = <535>;
199		};
200
201		a53_1: cpu@101 {
202			compatible = "arm,cortex-a53";
203			reg = <0x101>;
204			device_type = "cpu";
205			power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
206			next-level-cache = <&L2_CA53>;
207			enable-method = "psci";
208			cpu-idle-states = <&CPU_SLEEP_1>;
209			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
210			operating-points-v2 = <&cluster1_opp>;
211			capacity-dmips-mhz = <535>;
212		};
213
214		a53_2: cpu@102 {
215			compatible = "arm,cortex-a53";
216			reg = <0x102>;
217			device_type = "cpu";
218			power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
219			next-level-cache = <&L2_CA53>;
220			enable-method = "psci";
221			cpu-idle-states = <&CPU_SLEEP_1>;
222			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
223			operating-points-v2 = <&cluster1_opp>;
224			capacity-dmips-mhz = <535>;
225		};
226
227		a53_3: cpu@103 {
228			compatible = "arm,cortex-a53";
229			reg = <0x103>;
230			device_type = "cpu";
231			power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
232			next-level-cache = <&L2_CA53>;
233			enable-method = "psci";
234			cpu-idle-states = <&CPU_SLEEP_1>;
235			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
236			operating-points-v2 = <&cluster1_opp>;
237			capacity-dmips-mhz = <535>;
238		};
239
240		L2_CA57: cache-controller-0 {
241			compatible = "cache";
242			power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
243			cache-unified;
244			cache-level = <2>;
245		};
246
247		L2_CA53: cache-controller-1 {
248			compatible = "cache";
249			power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
250			cache-unified;
251			cache-level = <2>;
252		};
253
254		idle-states {
255			entry-method = "psci";
256
257			CPU_SLEEP_0: cpu-sleep-0 {
258				compatible = "arm,idle-state";
259				arm,psci-suspend-param = <0x0010000>;
260				local-timer-stop;
261				entry-latency-us = <400>;
262				exit-latency-us = <500>;
263				min-residency-us = <4000>;
264			};
265
266			CPU_SLEEP_1: cpu-sleep-1 {
267				compatible = "arm,idle-state";
268				arm,psci-suspend-param = <0x0010000>;
269				local-timer-stop;
270				entry-latency-us = <700>;
271				exit-latency-us = <700>;
272				min-residency-us = <5000>;
273			};
274		};
275	};
276
277	extal_clk: extal {
278		compatible = "fixed-clock";
279		#clock-cells = <0>;
280		/* This value must be overridden by the board */
281		clock-frequency = <0>;
282	};
283
284	extalr_clk: extalr {
285		compatible = "fixed-clock";
286		#clock-cells = <0>;
287		/* This value must be overridden by the board */
288		clock-frequency = <0>;
289	};
290
291	/* External PCIe clock - can be overridden by the board */
292	pcie_bus_clk: pcie_bus {
293		compatible = "fixed-clock";
294		#clock-cells = <0>;
295		clock-frequency = <0>;
296	};
297
298	pmu_a53 {
299		compatible = "arm,cortex-a53-pmu";
300		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
301				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
302				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
303				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
304		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
305	};
306
307	pmu_a57 {
308		compatible = "arm,cortex-a57-pmu";
309		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
310				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
311				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
312				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
313		interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
314	};
315
316	psci {
317		compatible = "arm,psci-1.0", "arm,psci-0.2";
318		method = "smc";
319	};
320
321	/* External SCIF clock - to be overridden by boards that provide it */
322	scif_clk: scif {
323		compatible = "fixed-clock";
324		#clock-cells = <0>;
325		clock-frequency = <0>;
326	};
327
328	soc {
329		compatible = "simple-bus";
330		interrupt-parent = <&gic>;
331		#address-cells = <2>;
332		#size-cells = <2>;
333		ranges;
334
335		rwdt: watchdog@e6020000 {
336			compatible = "renesas,r8a774e1-wdt",
337				     "renesas,rcar-gen3-wdt";
338			reg = <0 0xe6020000 0 0x0c>;
339			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
340			clocks = <&cpg CPG_MOD 402>;
341			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
342			resets = <&cpg 402>;
343			status = "disabled";
344		};
345
346		gpio0: gpio@e6050000 {
347			compatible = "renesas,gpio-r8a774e1",
348				     "renesas,rcar-gen3-gpio";
349			reg = <0 0xe6050000 0 0x50>;
350			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
351			#gpio-cells = <2>;
352			gpio-controller;
353			gpio-ranges = <&pfc 0 0 16>;
354			#interrupt-cells = <2>;
355			interrupt-controller;
356			clocks = <&cpg CPG_MOD 912>;
357			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
358			resets = <&cpg 912>;
359		};
360
361		gpio1: gpio@e6051000 {
362			compatible = "renesas,gpio-r8a774e1",
363				     "renesas,rcar-gen3-gpio";
364			reg = <0 0xe6051000 0 0x50>;
365			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
366			#gpio-cells = <2>;
367			gpio-controller;
368			gpio-ranges = <&pfc 0 32 29>;
369			#interrupt-cells = <2>;
370			interrupt-controller;
371			clocks = <&cpg CPG_MOD 911>;
372			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
373			resets = <&cpg 911>;
374		};
375
376		gpio2: gpio@e6052000 {
377			compatible = "renesas,gpio-r8a774e1",
378				     "renesas,rcar-gen3-gpio";
379			reg = <0 0xe6052000 0 0x50>;
380			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
381			#gpio-cells = <2>;
382			gpio-controller;
383			gpio-ranges = <&pfc 0 64 15>;
384			#interrupt-cells = <2>;
385			interrupt-controller;
386			clocks = <&cpg CPG_MOD 910>;
387			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
388			resets = <&cpg 910>;
389		};
390
391		gpio3: gpio@e6053000 {
392			compatible = "renesas,gpio-r8a774e1",
393				     "renesas,rcar-gen3-gpio";
394			reg = <0 0xe6053000 0 0x50>;
395			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
396			#gpio-cells = <2>;
397			gpio-controller;
398			gpio-ranges = <&pfc 0 96 16>;
399			#interrupt-cells = <2>;
400			interrupt-controller;
401			clocks = <&cpg CPG_MOD 909>;
402			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
403			resets = <&cpg 909>;
404		};
405
406		gpio4: gpio@e6054000 {
407			compatible = "renesas,gpio-r8a774e1",
408				     "renesas,rcar-gen3-gpio";
409			reg = <0 0xe6054000 0 0x50>;
410			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
411			#gpio-cells = <2>;
412			gpio-controller;
413			gpio-ranges = <&pfc 0 128 18>;
414			#interrupt-cells = <2>;
415			interrupt-controller;
416			clocks = <&cpg CPG_MOD 908>;
417			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
418			resets = <&cpg 908>;
419		};
420
421		gpio5: gpio@e6055000 {
422			compatible = "renesas,gpio-r8a774e1",
423				     "renesas,rcar-gen3-gpio";
424			reg = <0 0xe6055000 0 0x50>;
425			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
426			#gpio-cells = <2>;
427			gpio-controller;
428			gpio-ranges = <&pfc 0 160 26>;
429			#interrupt-cells = <2>;
430			interrupt-controller;
431			clocks = <&cpg CPG_MOD 907>;
432			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
433			resets = <&cpg 907>;
434		};
435
436		gpio6: gpio@e6055400 {
437			compatible = "renesas,gpio-r8a774e1",
438				     "renesas,rcar-gen3-gpio";
439			reg = <0 0xe6055400 0 0x50>;
440			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
441			#gpio-cells = <2>;
442			gpio-controller;
443			gpio-ranges = <&pfc 0 192 32>;
444			#interrupt-cells = <2>;
445			interrupt-controller;
446			clocks = <&cpg CPG_MOD 906>;
447			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
448			resets = <&cpg 906>;
449		};
450
451		gpio7: gpio@e6055800 {
452			compatible = "renesas,gpio-r8a774e1",
453				     "renesas,rcar-gen3-gpio";
454			reg = <0 0xe6055800 0 0x50>;
455			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
456			#gpio-cells = <2>;
457			gpio-controller;
458			gpio-ranges = <&pfc 0 224 4>;
459			#interrupt-cells = <2>;
460			interrupt-controller;
461			clocks = <&cpg CPG_MOD 905>;
462			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
463			resets = <&cpg 905>;
464		};
465
466		pfc: pinctrl@e6060000 {
467			compatible = "renesas,pfc-r8a774e1";
468			reg = <0 0xe6060000 0 0x50c>;
469		};
470
471		cmt0: timer@e60f0000 {
472			compatible = "renesas,r8a774e1-cmt0",
473				     "renesas,rcar-gen3-cmt0";
474			reg = <0 0xe60f0000 0 0x1004>;
475			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
476				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
477			clocks = <&cpg CPG_MOD 303>;
478			clock-names = "fck";
479			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
480			resets = <&cpg 303>;
481			status = "disabled";
482		};
483
484		cmt1: timer@e6130000 {
485			compatible = "renesas,r8a774e1-cmt1",
486				     "renesas,rcar-gen3-cmt1";
487			reg = <0 0xe6130000 0 0x1004>;
488			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
489				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
490				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
491				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
492				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
493				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
494				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
495				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
496			clocks = <&cpg CPG_MOD 302>;
497			clock-names = "fck";
498			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
499			resets = <&cpg 302>;
500			status = "disabled";
501		};
502
503		cmt2: timer@e6140000 {
504			compatible = "renesas,r8a774e1-cmt1",
505				     "renesas,rcar-gen3-cmt1";
506			reg = <0 0xe6140000 0 0x1004>;
507			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
508				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
509				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
510				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
511				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
512				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
513				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
514				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
515			clocks = <&cpg CPG_MOD 301>;
516			clock-names = "fck";
517			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
518			resets = <&cpg 301>;
519			status = "disabled";
520		};
521
522		cmt3: timer@e6148000 {
523			compatible = "renesas,r8a774e1-cmt1",
524				     "renesas,rcar-gen3-cmt1";
525			reg = <0 0xe6148000 0 0x1004>;
526			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
527				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
528				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
529				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
530				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
531				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
532				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
533				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
534			clocks = <&cpg CPG_MOD 300>;
535			clock-names = "fck";
536			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
537			resets = <&cpg 300>;
538			status = "disabled";
539		};
540
541		cpg: clock-controller@e6150000 {
542			compatible = "renesas,r8a774e1-cpg-mssr";
543			reg = <0 0xe6150000 0 0x1000>;
544			clocks = <&extal_clk>, <&extalr_clk>;
545			clock-names = "extal", "extalr";
546			#clock-cells = <2>;
547			#power-domain-cells = <0>;
548			#reset-cells = <1>;
549		};
550
551		rst: reset-controller@e6160000 {
552			compatible = "renesas,r8a774e1-rst";
553			reg = <0 0xe6160000 0 0x0200>;
554		};
555
556		sysc: system-controller@e6180000 {
557			compatible = "renesas,r8a774e1-sysc";
558			reg = <0 0xe6180000 0 0x0400>;
559			#power-domain-cells = <1>;
560		};
561
562		tsc: thermal@e6198000 {
563			compatible = "renesas,r8a774e1-thermal";
564			reg = <0 0xe6198000 0 0x100>,
565			      <0 0xe61a0000 0 0x100>,
566			      <0 0xe61a8000 0 0x100>;
567			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
568				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
569				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
570			clocks = <&cpg CPG_MOD 522>;
571			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
572			resets = <&cpg 522>;
573			#thermal-sensor-cells = <1>;
574		};
575
576		intc_ex: interrupt-controller@e61c0000 {
577			compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
578			#interrupt-cells = <2>;
579			interrupt-controller;
580			reg = <0 0xe61c0000 0 0x200>;
581			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
582				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
583				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
584				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
585				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
586				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
587			clocks = <&cpg CPG_MOD 407>;
588			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
589			resets = <&cpg 407>;
590		};
591
592		tmu0: timer@e61e0000 {
593			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
594			reg = <0 0xe61e0000 0 0x30>;
595			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
596				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
597				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
598			clocks = <&cpg CPG_MOD 125>;
599			clock-names = "fck";
600			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
601			resets = <&cpg 125>;
602			status = "disabled";
603		};
604
605		tmu1: timer@e6fc0000 {
606			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
607			reg = <0 0xe6fc0000 0 0x30>;
608			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
609				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
610				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
611			clocks = <&cpg CPG_MOD 124>;
612			clock-names = "fck";
613			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
614			resets = <&cpg 124>;
615			status = "disabled";
616		};
617
618		tmu2: timer@e6fd0000 {
619			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
620			reg = <0 0xe6fd0000 0 0x30>;
621			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
622				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
623				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
624			clocks = <&cpg CPG_MOD 123>;
625			clock-names = "fck";
626			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
627			resets = <&cpg 123>;
628			status = "disabled";
629		};
630
631		tmu3: timer@e6fe0000 {
632			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
633			reg = <0 0xe6fe0000 0 0x30>;
634			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
635				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
636				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
637			clocks = <&cpg CPG_MOD 122>;
638			clock-names = "fck";
639			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
640			resets = <&cpg 122>;
641			status = "disabled";
642		};
643
644		tmu4: timer@ffc00000 {
645			compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
646			reg = <0 0xffc00000 0 0x30>;
647			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
648				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
649				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
650			clocks = <&cpg CPG_MOD 121>;
651			clock-names = "fck";
652			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
653			resets = <&cpg 121>;
654			status = "disabled";
655		};
656
657		i2c0: i2c@e6500000 {
658			#address-cells = <1>;
659			#size-cells = <0>;
660			compatible = "renesas,i2c-r8a774e1",
661				     "renesas,rcar-gen3-i2c";
662			reg = <0 0xe6500000 0 0x40>;
663			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
664			clocks = <&cpg CPG_MOD 931>;
665			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
666			resets = <&cpg 931>;
667			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
668			       <&dmac2 0x91>, <&dmac2 0x90>;
669			dma-names = "tx", "rx", "tx", "rx";
670			i2c-scl-internal-delay-ns = <110>;
671			status = "disabled";
672		};
673
674		i2c1: i2c@e6508000 {
675			#address-cells = <1>;
676			#size-cells = <0>;
677			compatible = "renesas,i2c-r8a774e1",
678				     "renesas,rcar-gen3-i2c";
679			reg = <0 0xe6508000 0 0x40>;
680			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
681			clocks = <&cpg CPG_MOD 930>;
682			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
683			resets = <&cpg 930>;
684			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
685			       <&dmac2 0x93>, <&dmac2 0x92>;
686			dma-names = "tx", "rx", "tx", "rx";
687			i2c-scl-internal-delay-ns = <6>;
688			status = "disabled";
689		};
690
691		i2c2: i2c@e6510000 {
692			#address-cells = <1>;
693			#size-cells = <0>;
694			compatible = "renesas,i2c-r8a774e1",
695				     "renesas,rcar-gen3-i2c";
696			reg = <0 0xe6510000 0 0x40>;
697			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
698			clocks = <&cpg CPG_MOD 929>;
699			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
700			resets = <&cpg 929>;
701			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
702			       <&dmac2 0x95>, <&dmac2 0x94>;
703			dma-names = "tx", "rx", "tx", "rx";
704			i2c-scl-internal-delay-ns = <6>;
705			status = "disabled";
706		};
707
708		i2c3: i2c@e66d0000 {
709			#address-cells = <1>;
710			#size-cells = <0>;
711			compatible = "renesas,i2c-r8a774e1",
712				     "renesas,rcar-gen3-i2c";
713			reg = <0 0xe66d0000 0 0x40>;
714			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
715			clocks = <&cpg CPG_MOD 928>;
716			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
717			resets = <&cpg 928>;
718			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
719			dma-names = "tx", "rx";
720			i2c-scl-internal-delay-ns = <110>;
721			status = "disabled";
722		};
723
724		i2c4: i2c@e66d8000 {
725			#address-cells = <1>;
726			#size-cells = <0>;
727			compatible = "renesas,i2c-r8a774e1",
728				     "renesas,rcar-gen3-i2c";
729			reg = <0 0xe66d8000 0 0x40>;
730			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
731			clocks = <&cpg CPG_MOD 927>;
732			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
733			resets = <&cpg 927>;
734			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
735			dma-names = "tx", "rx";
736			i2c-scl-internal-delay-ns = <110>;
737			status = "disabled";
738		};
739
740		i2c5: i2c@e66e0000 {
741			#address-cells = <1>;
742			#size-cells = <0>;
743			compatible = "renesas,i2c-r8a774e1",
744				     "renesas,rcar-gen3-i2c";
745			reg = <0 0xe66e0000 0 0x40>;
746			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
747			clocks = <&cpg CPG_MOD 919>;
748			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
749			resets = <&cpg 919>;
750			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
751			dma-names = "tx", "rx";
752			i2c-scl-internal-delay-ns = <110>;
753			status = "disabled";
754		};
755
756		i2c6: i2c@e66e8000 {
757			#address-cells = <1>;
758			#size-cells = <0>;
759			compatible = "renesas,i2c-r8a774e1",
760				     "renesas,rcar-gen3-i2c";
761			reg = <0 0xe66e8000 0 0x40>;
762			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
763			clocks = <&cpg CPG_MOD 918>;
764			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
765			resets = <&cpg 918>;
766			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
767			dma-names = "tx", "rx";
768			i2c-scl-internal-delay-ns = <6>;
769			status = "disabled";
770		};
771
772		i2c_dvfs: i2c@e60b0000 {
773			#address-cells = <1>;
774			#size-cells = <0>;
775			compatible = "renesas,iic-r8a774e1",
776				     "renesas,rcar-gen3-iic",
777				     "renesas,rmobile-iic";
778			reg = <0 0xe60b0000 0 0x425>;
779			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
780			clocks = <&cpg CPG_MOD 926>;
781			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
782			resets = <&cpg 926>;
783			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
784			dma-names = "tx", "rx";
785			status = "disabled";
786		};
787
788		hscif0: serial@e6540000 {
789			compatible = "renesas,hscif-r8a774e1",
790				     "renesas,rcar-gen3-hscif",
791				     "renesas,hscif";
792			reg = <0 0xe6540000 0 0x60>;
793			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
794			clocks = <&cpg CPG_MOD 520>,
795				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
796				 <&scif_clk>;
797			clock-names = "fck", "brg_int", "scif_clk";
798			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
799			       <&dmac2 0x31>, <&dmac2 0x30>;
800			dma-names = "tx", "rx", "tx", "rx";
801			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
802			resets = <&cpg 520>;
803			status = "disabled";
804		};
805
806		hscif1: serial@e6550000 {
807			compatible = "renesas,hscif-r8a774e1",
808				     "renesas,rcar-gen3-hscif",
809				     "renesas,hscif";
810			reg = <0 0xe6550000 0 0x60>;
811			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
812			clocks = <&cpg CPG_MOD 519>,
813				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
814				 <&scif_clk>;
815			clock-names = "fck", "brg_int", "scif_clk";
816			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
817			       <&dmac2 0x33>, <&dmac2 0x32>;
818			dma-names = "tx", "rx", "tx", "rx";
819			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
820			resets = <&cpg 519>;
821			status = "disabled";
822		};
823
824		hscif2: serial@e6560000 {
825			compatible = "renesas,hscif-r8a774e1",
826				     "renesas,rcar-gen3-hscif",
827				     "renesas,hscif";
828			reg = <0 0xe6560000 0 0x60>;
829			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
830			clocks = <&cpg CPG_MOD 518>,
831				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
832				 <&scif_clk>;
833			clock-names = "fck", "brg_int", "scif_clk";
834			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
835			       <&dmac2 0x35>, <&dmac2 0x34>;
836			dma-names = "tx", "rx", "tx", "rx";
837			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
838			resets = <&cpg 518>;
839			status = "disabled";
840		};
841
842		hscif3: serial@e66a0000 {
843			compatible = "renesas,hscif-r8a774e1",
844				     "renesas,rcar-gen3-hscif",
845				     "renesas,hscif";
846			reg = <0 0xe66a0000 0 0x60>;
847			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
848			clocks = <&cpg CPG_MOD 517>,
849				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
850				 <&scif_clk>;
851			clock-names = "fck", "brg_int", "scif_clk";
852			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
853			dma-names = "tx", "rx";
854			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
855			resets = <&cpg 517>;
856			status = "disabled";
857		};
858
859		hscif4: serial@e66b0000 {
860			compatible = "renesas,hscif-r8a774e1",
861				     "renesas,rcar-gen3-hscif",
862				     "renesas,hscif";
863			reg = <0 0xe66b0000 0 0x60>;
864			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
865			clocks = <&cpg CPG_MOD 516>,
866				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
867				 <&scif_clk>;
868			clock-names = "fck", "brg_int", "scif_clk";
869			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
870			dma-names = "tx", "rx";
871			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
872			resets = <&cpg 516>;
873			status = "disabled";
874		};
875
876		hsusb: usb@e6590000 {
877			compatible = "renesas,usbhs-r8a774e1",
878				     "renesas,rcar-gen3-usbhs";
879			reg = <0 0xe6590000 0 0x200>;
880			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
881			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
882			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
883			       <&usb_dmac1 0>, <&usb_dmac1 1>;
884			dma-names = "ch0", "ch1", "ch2", "ch3";
885			renesas,buswait = <11>;
886			phys = <&usb2_phy0 3>;
887			phy-names = "usb";
888			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
889			resets = <&cpg 704>, <&cpg 703>;
890			status = "disabled";
891		};
892
893		usb2_clksel: clock-controller@e6590630 {
894			compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
895				     "renesas,rcar-gen3-usb2-clock-sel";
896			reg = <0 0xe6590630 0 0x02>;
897			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
898				 <&usb_extal_clk>, <&usb3s0_clk>;
899			clock-names = "ehci_ohci", "hs-usb-if",
900				      "usb_extal", "usb_xtal";
901			#clock-cells = <0>;
902			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
903			resets = <&cpg 703>, <&cpg 704>;
904			reset-names = "ehci_ohci", "hs-usb-if";
905			status = "disabled";
906		};
907
908		usb_dmac0: dma-controller@e65a0000 {
909			compatible = "renesas,r8a774e1-usb-dmac",
910				     "renesas,usb-dmac";
911			reg = <0 0xe65a0000 0 0x100>;
912			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
913				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
914			interrupt-names = "ch0", "ch1";
915			clocks = <&cpg CPG_MOD 330>;
916			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
917			resets = <&cpg 330>;
918			#dma-cells = <1>;
919			dma-channels = <2>;
920		};
921
922		usb_dmac1: dma-controller@e65b0000 {
923			compatible = "renesas,r8a774e1-usb-dmac",
924				     "renesas,usb-dmac";
925			reg = <0 0xe65b0000 0 0x100>;
926			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
927				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
928			interrupt-names = "ch0", "ch1";
929			clocks = <&cpg CPG_MOD 331>;
930			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
931			resets = <&cpg 331>;
932			#dma-cells = <1>;
933			dma-channels = <2>;
934		};
935
936		usb3_phy0: usb-phy@e65ee000 {
937			compatible = "renesas,r8a774e1-usb3-phy",
938				     "renesas,rcar-gen3-usb3-phy";
939			reg = <0 0xe65ee000 0 0x90>;
940			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
941				 <&usb_extal_clk>;
942			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
943			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
944			resets = <&cpg 328>;
945			#phy-cells = <0>;
946			status = "disabled";
947		};
948
949		dmac0: dma-controller@e6700000 {
950			compatible = "renesas,dmac-r8a774e1",
951				     "renesas,rcar-dmac";
952			reg = <0 0xe6700000 0 0x10000>;
953			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
954				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
955				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
956				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
957				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
958				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
959				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
960				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
961				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
962				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
963				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
964				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
965				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
966				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
967				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
968				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
969				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
970			interrupt-names = "error",
971					  "ch0", "ch1", "ch2", "ch3",
972					  "ch4", "ch5", "ch6", "ch7",
973					  "ch8", "ch9", "ch10", "ch11",
974					  "ch12", "ch13", "ch14", "ch15";
975			clocks = <&cpg CPG_MOD 219>;
976			clock-names = "fck";
977			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
978			resets = <&cpg 219>;
979			#dma-cells = <1>;
980			dma-channels = <16>;
981			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
982				 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
983				 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
984				 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
985				 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
986				 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
987				 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
988				 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
989		};
990
991		dmac1: dma-controller@e7300000 {
992			compatible = "renesas,dmac-r8a774e1",
993				     "renesas,rcar-dmac";
994			reg = <0 0xe7300000 0 0x10000>;
995			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
996				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
997				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
998				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
999				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1000				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1001				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1002				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1003				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1004				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1005				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1006				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1007				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1008				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1009				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1010				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1011				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1012			interrupt-names = "error",
1013					  "ch0", "ch1", "ch2", "ch3",
1014					  "ch4", "ch5", "ch6", "ch7",
1015					  "ch8", "ch9", "ch10", "ch11",
1016					  "ch12", "ch13", "ch14", "ch15";
1017			clocks = <&cpg CPG_MOD 218>;
1018			clock-names = "fck";
1019			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1020			resets = <&cpg 218>;
1021			#dma-cells = <1>;
1022			dma-channels = <16>;
1023			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1024				 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1025				 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1026				 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1027				 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1028				 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1029				 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1030				 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1031		};
1032
1033		dmac2: dma-controller@e7310000 {
1034			compatible = "renesas,dmac-r8a774e1",
1035				     "renesas,rcar-dmac";
1036			reg = <0 0xe7310000 0 0x10000>;
1037			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1038				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1039				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1040				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1041				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1042				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1043				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1044				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1045				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1046				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1047				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1048				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1049				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1050				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1051				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1052				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1053				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1054			interrupt-names = "error",
1055					  "ch0", "ch1", "ch2", "ch3",
1056					  "ch4", "ch5", "ch6", "ch7",
1057					  "ch8", "ch9", "ch10", "ch11",
1058					  "ch12", "ch13", "ch14", "ch15";
1059			clocks = <&cpg CPG_MOD 217>;
1060			clock-names = "fck";
1061			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1062			resets = <&cpg 217>;
1063			#dma-cells = <1>;
1064			dma-channels = <16>;
1065			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1066				 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1067				 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1068				 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1069				 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1070				 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1071				 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1072				 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1073		};
1074
1075		ipmmu_ds0: iommu@e6740000 {
1076			compatible = "renesas,ipmmu-r8a774e1";
1077			reg = <0 0xe6740000 0 0x1000>;
1078			renesas,ipmmu-main = <&ipmmu_mm 0>;
1079			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1080			#iommu-cells = <1>;
1081		};
1082
1083		ipmmu_ds1: iommu@e7740000 {
1084			compatible = "renesas,ipmmu-r8a774e1";
1085			reg = <0 0xe7740000 0 0x1000>;
1086			renesas,ipmmu-main = <&ipmmu_mm 1>;
1087			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1088			#iommu-cells = <1>;
1089		};
1090
1091		ipmmu_hc: iommu@e6570000 {
1092			compatible = "renesas,ipmmu-r8a774e1";
1093			reg = <0 0xe6570000 0 0x1000>;
1094			renesas,ipmmu-main = <&ipmmu_mm 2>;
1095			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1096			#iommu-cells = <1>;
1097		};
1098
1099		ipmmu_mm: iommu@e67b0000 {
1100			compatible = "renesas,ipmmu-r8a774e1";
1101			reg = <0 0xe67b0000 0 0x1000>;
1102			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1103				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1104			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1105			#iommu-cells = <1>;
1106		};
1107
1108		ipmmu_mp0: iommu@ec670000 {
1109			compatible = "renesas,ipmmu-r8a774e1";
1110			reg = <0 0xec670000 0 0x1000>;
1111			renesas,ipmmu-main = <&ipmmu_mm 4>;
1112			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1113			#iommu-cells = <1>;
1114		};
1115
1116		ipmmu_pv0: iommu@fd800000 {
1117			compatible = "renesas,ipmmu-r8a774e1";
1118			reg = <0 0xfd800000 0 0x1000>;
1119			renesas,ipmmu-main = <&ipmmu_mm 6>;
1120			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1121			#iommu-cells = <1>;
1122		};
1123
1124		ipmmu_pv1: iommu@fd950000 {
1125			compatible = "renesas,ipmmu-r8a774e1";
1126			reg = <0 0xfd950000 0 0x1000>;
1127			renesas,ipmmu-main = <&ipmmu_mm 7>;
1128			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1129			#iommu-cells = <1>;
1130		};
1131
1132		ipmmu_pv2: iommu@fd960000 {
1133			compatible = "renesas,ipmmu-r8a774e1";
1134			reg = <0 0xfd960000 0 0x1000>;
1135			renesas,ipmmu-main = <&ipmmu_mm 8>;
1136			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1137			#iommu-cells = <1>;
1138		};
1139
1140		ipmmu_pv3: iommu@fd970000 {
1141			compatible = "renesas,ipmmu-r8a774e1";
1142			reg = <0 0xfd970000 0 0x1000>;
1143			renesas,ipmmu-main = <&ipmmu_mm 9>;
1144			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1145			#iommu-cells = <1>;
1146		};
1147
1148		ipmmu_vc0: iommu@fe6b0000 {
1149			compatible = "renesas,ipmmu-r8a774e1";
1150			reg = <0 0xfe6b0000 0 0x1000>;
1151			renesas,ipmmu-main = <&ipmmu_mm 12>;
1152			power-domains = <&sysc R8A774E1_PD_A3VC>;
1153			#iommu-cells = <1>;
1154		};
1155
1156		ipmmu_vc1: iommu@fe6f0000 {
1157			compatible = "renesas,ipmmu-r8a774e1";
1158			reg = <0 0xfe6f0000 0 0x1000>;
1159			renesas,ipmmu-main = <&ipmmu_mm 13>;
1160			power-domains = <&sysc R8A774E1_PD_A3VC>;
1161			#iommu-cells = <1>;
1162		};
1163
1164		ipmmu_vi0: iommu@febd0000 {
1165			compatible = "renesas,ipmmu-r8a774e1";
1166			reg = <0 0xfebd0000 0 0x1000>;
1167			renesas,ipmmu-main = <&ipmmu_mm 14>;
1168			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1169			#iommu-cells = <1>;
1170		};
1171
1172		ipmmu_vi1: iommu@febe0000 {
1173			compatible = "renesas,ipmmu-r8a774e1";
1174			reg = <0 0xfebe0000 0 0x1000>;
1175			renesas,ipmmu-main = <&ipmmu_mm 15>;
1176			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1177			#iommu-cells = <1>;
1178		};
1179
1180		ipmmu_vp0: iommu@fe990000 {
1181			compatible = "renesas,ipmmu-r8a774e1";
1182			reg = <0 0xfe990000 0 0x1000>;
1183			renesas,ipmmu-main = <&ipmmu_mm 16>;
1184			power-domains = <&sysc R8A774E1_PD_A3VP>;
1185			#iommu-cells = <1>;
1186		};
1187
1188		ipmmu_vp1: iommu@fe980000 {
1189			compatible = "renesas,ipmmu-r8a774e1";
1190			reg = <0 0xfe980000 0 0x1000>;
1191			renesas,ipmmu-main = <&ipmmu_mm 17>;
1192			power-domains = <&sysc R8A774E1_PD_A3VP>;
1193			#iommu-cells = <1>;
1194		};
1195
1196		avb: ethernet@e6800000 {
1197			compatible = "renesas,etheravb-r8a774e1",
1198				     "renesas,etheravb-rcar-gen3";
1199			reg = <0 0xe6800000 0 0x800>;
1200			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1201				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1202				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1203				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1204				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1205				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1206				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1207				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1208				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1209				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1210				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1211				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1212				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1213				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1214				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1215				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1216				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1217				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1218				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1219				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1220				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1221				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1222				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1223				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1224				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1225			interrupt-names = "ch0", "ch1", "ch2", "ch3",
1226					  "ch4", "ch5", "ch6", "ch7",
1227					  "ch8", "ch9", "ch10", "ch11",
1228					  "ch12", "ch13", "ch14", "ch15",
1229					  "ch16", "ch17", "ch18", "ch19",
1230					  "ch20", "ch21", "ch22", "ch23",
1231					  "ch24";
1232			clocks = <&cpg CPG_MOD 812>;
1233			clock-names = "fck";
1234			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1235			resets = <&cpg 812>;
1236			phy-mode = "rgmii";
1237			rx-internal-delay-ps = <0>;
1238			tx-internal-delay-ps = <0>;
1239			iommus = <&ipmmu_ds0 16>;
1240			#address-cells = <1>;
1241			#size-cells = <0>;
1242			status = "disabled";
1243		};
1244
1245		can0: can@e6c30000 {
1246			compatible = "renesas,can-r8a774e1",
1247				     "renesas,rcar-gen3-can";
1248			reg = <0 0xe6c30000 0 0x1000>;
1249			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1250			clocks = <&cpg CPG_MOD 916>,
1251				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1252				 <&can_clk>;
1253			clock-names = "clkp1", "clkp2", "can_clk";
1254			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1255			assigned-clock-rates = <40000000>;
1256			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1257			resets = <&cpg 916>;
1258			status = "disabled";
1259		};
1260
1261		can1: can@e6c38000 {
1262			compatible = "renesas,can-r8a774e1",
1263				     "renesas,rcar-gen3-can";
1264			reg = <0 0xe6c38000 0 0x1000>;
1265			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1266			clocks = <&cpg CPG_MOD 915>,
1267				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1268				 <&can_clk>;
1269			clock-names = "clkp1", "clkp2", "can_clk";
1270			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1271			assigned-clock-rates = <40000000>;
1272			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1273			resets = <&cpg 915>;
1274			status = "disabled";
1275		};
1276
1277		canfd: can@e66c0000 {
1278			compatible = "renesas,r8a774e1-canfd",
1279				     "renesas,rcar-gen3-canfd";
1280			reg = <0 0xe66c0000 0 0x8000>;
1281			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1282				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1283			clocks = <&cpg CPG_MOD 914>,
1284				 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1285				 <&can_clk>;
1286			clock-names = "fck", "canfd", "can_clk";
1287			assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1288			assigned-clock-rates = <40000000>;
1289			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1290			resets = <&cpg 914>;
1291			status = "disabled";
1292
1293			channel0 {
1294				status = "disabled";
1295			};
1296
1297			channel1 {
1298				status = "disabled";
1299			};
1300		};
1301
1302		pwm0: pwm@e6e30000 {
1303			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1304			reg = <0 0xe6e30000 0 0x8>;
1305			clocks = <&cpg CPG_MOD 523>;
1306			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1307			resets = <&cpg 523>;
1308			#pwm-cells = <2>;
1309			status = "disabled";
1310		};
1311
1312		pwm1: pwm@e6e31000 {
1313			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1314			reg = <0 0xe6e31000 0 0x8>;
1315			clocks = <&cpg CPG_MOD 523>;
1316			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1317			resets = <&cpg 523>;
1318			#pwm-cells = <2>;
1319			status = "disabled";
1320		};
1321
1322		pwm2: pwm@e6e32000 {
1323			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1324			reg = <0 0xe6e32000 0 0x8>;
1325			clocks = <&cpg CPG_MOD 523>;
1326			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1327			resets = <&cpg 523>;
1328			#pwm-cells = <2>;
1329			status = "disabled";
1330		};
1331
1332		pwm3: pwm@e6e33000 {
1333			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1334			reg = <0 0xe6e33000 0 0x8>;
1335			clocks = <&cpg CPG_MOD 523>;
1336			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1337			resets = <&cpg 523>;
1338			#pwm-cells = <2>;
1339			status = "disabled";
1340		};
1341
1342		pwm4: pwm@e6e34000 {
1343			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1344			reg = <0 0xe6e34000 0 0x8>;
1345			clocks = <&cpg CPG_MOD 523>;
1346			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1347			resets = <&cpg 523>;
1348			#pwm-cells = <2>;
1349			status = "disabled";
1350		};
1351
1352		pwm5: pwm@e6e35000 {
1353			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1354			reg = <0 0xe6e35000 0 0x8>;
1355			clocks = <&cpg CPG_MOD 523>;
1356			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1357			resets = <&cpg 523>;
1358			#pwm-cells = <2>;
1359			status = "disabled";
1360		};
1361
1362		pwm6: pwm@e6e36000 {
1363			compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1364			reg = <0 0xe6e36000 0 0x8>;
1365			clocks = <&cpg CPG_MOD 523>;
1366			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1367			resets = <&cpg 523>;
1368			#pwm-cells = <2>;
1369			status = "disabled";
1370		};
1371
1372		scif0: serial@e6e60000 {
1373			compatible = "renesas,scif-r8a774e1",
1374				     "renesas,rcar-gen3-scif", "renesas,scif";
1375			reg = <0 0xe6e60000 0 0x40>;
1376			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1377			clocks = <&cpg CPG_MOD 207>,
1378				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1379				 <&scif_clk>;
1380			clock-names = "fck", "brg_int", "scif_clk";
1381			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1382			       <&dmac2 0x51>, <&dmac2 0x50>;
1383			dma-names = "tx", "rx", "tx", "rx";
1384			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1385			resets = <&cpg 207>;
1386			status = "disabled";
1387		};
1388
1389		scif1: serial@e6e68000 {
1390			compatible = "renesas,scif-r8a774e1",
1391				     "renesas,rcar-gen3-scif", "renesas,scif";
1392			reg = <0 0xe6e68000 0 0x40>;
1393			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1394			clocks = <&cpg CPG_MOD 206>,
1395				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1396				 <&scif_clk>;
1397			clock-names = "fck", "brg_int", "scif_clk";
1398			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1399			       <&dmac2 0x53>, <&dmac2 0x52>;
1400			dma-names = "tx", "rx", "tx", "rx";
1401			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1402			resets = <&cpg 206>;
1403			status = "disabled";
1404		};
1405
1406		scif2: serial@e6e88000 {
1407			compatible = "renesas,scif-r8a774e1",
1408				     "renesas,rcar-gen3-scif", "renesas,scif";
1409			reg = <0 0xe6e88000 0 0x40>;
1410			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1411			clocks = <&cpg CPG_MOD 310>,
1412				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1413				 <&scif_clk>;
1414			clock-names = "fck", "brg_int", "scif_clk";
1415			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1416			       <&dmac2 0x13>, <&dmac2 0x12>;
1417			dma-names = "tx", "rx", "tx", "rx";
1418			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1419			resets = <&cpg 310>;
1420			status = "disabled";
1421		};
1422
1423		scif3: serial@e6c50000 {
1424			compatible = "renesas,scif-r8a774e1",
1425				     "renesas,rcar-gen3-scif", "renesas,scif";
1426			reg = <0 0xe6c50000 0 0x40>;
1427			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1428			clocks = <&cpg CPG_MOD 204>,
1429				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1430				 <&scif_clk>;
1431			clock-names = "fck", "brg_int", "scif_clk";
1432			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1433			dma-names = "tx", "rx";
1434			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1435			resets = <&cpg 204>;
1436			status = "disabled";
1437		};
1438
1439		scif4: serial@e6c40000 {
1440			compatible = "renesas,scif-r8a774e1",
1441				     "renesas,rcar-gen3-scif", "renesas,scif";
1442			reg = <0 0xe6c40000 0 0x40>;
1443			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1444			clocks = <&cpg CPG_MOD 203>,
1445				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1446				 <&scif_clk>;
1447			clock-names = "fck", "brg_int", "scif_clk";
1448			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1449			dma-names = "tx", "rx";
1450			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1451			resets = <&cpg 203>;
1452			status = "disabled";
1453		};
1454
1455		scif5: serial@e6f30000 {
1456			compatible = "renesas,scif-r8a774e1",
1457				     "renesas,rcar-gen3-scif", "renesas,scif";
1458			reg = <0 0xe6f30000 0 0x40>;
1459			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1460			clocks = <&cpg CPG_MOD 202>,
1461				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1462				 <&scif_clk>;
1463			clock-names = "fck", "brg_int", "scif_clk";
1464			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1465			       <&dmac2 0x5b>, <&dmac2 0x5a>;
1466			dma-names = "tx", "rx", "tx", "rx";
1467			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1468			resets = <&cpg 202>;
1469			status = "disabled";
1470		};
1471
1472		msiof0: spi@e6e90000 {
1473			compatible = "renesas,msiof-r8a774e1",
1474				     "renesas,rcar-gen3-msiof";
1475			reg = <0 0xe6e90000 0 0x0064>;
1476			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1477			clocks = <&cpg CPG_MOD 211>;
1478			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1479			       <&dmac2 0x41>, <&dmac2 0x40>;
1480			dma-names = "tx", "rx", "tx", "rx";
1481			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1482			resets = <&cpg 211>;
1483			#address-cells = <1>;
1484			#size-cells = <0>;
1485			status = "disabled";
1486		};
1487
1488		msiof1: spi@e6ea0000 {
1489			compatible = "renesas,msiof-r8a774e1",
1490				     "renesas,rcar-gen3-msiof";
1491			reg = <0 0xe6ea0000 0 0x0064>;
1492			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1493			clocks = <&cpg CPG_MOD 210>;
1494			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1495			       <&dmac2 0x43>, <&dmac2 0x42>;
1496			dma-names = "tx", "rx", "tx", "rx";
1497			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1498			resets = <&cpg 210>;
1499			#address-cells = <1>;
1500			#size-cells = <0>;
1501			status = "disabled";
1502		};
1503
1504		msiof2: spi@e6c00000 {
1505			compatible = "renesas,msiof-r8a774e1",
1506				     "renesas,rcar-gen3-msiof";
1507			reg = <0 0xe6c00000 0 0x0064>;
1508			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1509			clocks = <&cpg CPG_MOD 209>;
1510			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1511			dma-names = "tx", "rx";
1512			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1513			resets = <&cpg 209>;
1514			#address-cells = <1>;
1515			#size-cells = <0>;
1516			status = "disabled";
1517		};
1518
1519		msiof3: spi@e6c10000 {
1520			compatible = "renesas,msiof-r8a774e1",
1521				     "renesas,rcar-gen3-msiof";
1522			reg = <0 0xe6c10000 0 0x0064>;
1523			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1524			clocks = <&cpg CPG_MOD 208>;
1525			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1526			dma-names = "tx", "rx";
1527			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1528			resets = <&cpg 208>;
1529			#address-cells = <1>;
1530			#size-cells = <0>;
1531			status = "disabled";
1532		};
1533
1534		vin0: video@e6ef0000 {
1535			compatible = "renesas,vin-r8a774e1";
1536			reg = <0 0xe6ef0000 0 0x1000>;
1537			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1538			clocks = <&cpg CPG_MOD 811>;
1539			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1540			resets = <&cpg 811>;
1541			renesas,id = <0>;
1542			status = "disabled";
1543
1544			ports {
1545				#address-cells = <1>;
1546				#size-cells = <0>;
1547
1548				port@1 {
1549					#address-cells = <1>;
1550					#size-cells = <0>;
1551
1552					reg = <1>;
1553
1554					vin0csi20: endpoint@0 {
1555						reg = <0>;
1556						remote-endpoint = <&csi20vin0>;
1557					};
1558					vin0csi40: endpoint@2 {
1559						reg = <2>;
1560						remote-endpoint = <&csi40vin0>;
1561					};
1562				};
1563			};
1564		};
1565
1566		vin1: video@e6ef1000 {
1567			compatible = "renesas,vin-r8a774e1";
1568			reg = <0 0xe6ef1000 0 0x1000>;
1569			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1570			clocks = <&cpg CPG_MOD 810>;
1571			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1572			resets = <&cpg 810>;
1573			renesas,id = <1>;
1574			status = "disabled";
1575
1576			ports {
1577				#address-cells = <1>;
1578				#size-cells = <0>;
1579
1580				port@1 {
1581					#address-cells = <1>;
1582					#size-cells = <0>;
1583
1584					reg = <1>;
1585
1586					vin1csi20: endpoint@0 {
1587						reg = <0>;
1588						remote-endpoint = <&csi20vin1>;
1589					};
1590					vin1csi40: endpoint@2 {
1591						reg = <2>;
1592						remote-endpoint = <&csi40vin1>;
1593					};
1594				};
1595			};
1596		};
1597
1598		vin2: video@e6ef2000 {
1599			compatible = "renesas,vin-r8a774e1";
1600			reg = <0 0xe6ef2000 0 0x1000>;
1601			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1602			clocks = <&cpg CPG_MOD 809>;
1603			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1604			resets = <&cpg 809>;
1605			renesas,id = <2>;
1606			status = "disabled";
1607
1608			ports {
1609				#address-cells = <1>;
1610				#size-cells = <0>;
1611
1612				port@1 {
1613					#address-cells = <1>;
1614					#size-cells = <0>;
1615
1616					reg = <1>;
1617
1618					vin2csi20: endpoint@0 {
1619						reg = <0>;
1620						remote-endpoint = <&csi20vin2>;
1621					};
1622					vin2csi40: endpoint@2 {
1623						reg = <2>;
1624						remote-endpoint = <&csi40vin2>;
1625					};
1626				};
1627			};
1628		};
1629
1630		vin3: video@e6ef3000 {
1631			compatible = "renesas,vin-r8a774e1";
1632			reg = <0 0xe6ef3000 0 0x1000>;
1633			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1634			clocks = <&cpg CPG_MOD 808>;
1635			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1636			resets = <&cpg 808>;
1637			renesas,id = <3>;
1638			status = "disabled";
1639
1640			ports {
1641				#address-cells = <1>;
1642				#size-cells = <0>;
1643
1644				port@1 {
1645					#address-cells = <1>;
1646					#size-cells = <0>;
1647
1648					reg = <1>;
1649
1650					vin3csi20: endpoint@0 {
1651						reg = <0>;
1652						remote-endpoint = <&csi20vin3>;
1653					};
1654					vin3csi40: endpoint@2 {
1655						reg = <2>;
1656						remote-endpoint = <&csi40vin3>;
1657					};
1658				};
1659			};
1660		};
1661
1662		vin4: video@e6ef4000 {
1663			compatible = "renesas,vin-r8a774e1";
1664			reg = <0 0xe6ef4000 0 0x1000>;
1665			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1666			clocks = <&cpg CPG_MOD 807>;
1667			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1668			resets = <&cpg 807>;
1669			renesas,id = <4>;
1670			status = "disabled";
1671
1672			ports {
1673				#address-cells = <1>;
1674				#size-cells = <0>;
1675
1676				port@1 {
1677					#address-cells = <1>;
1678					#size-cells = <0>;
1679
1680					reg = <1>;
1681
1682					vin4csi20: endpoint@0 {
1683						reg = <0>;
1684						remote-endpoint = <&csi20vin4>;
1685					};
1686				};
1687			};
1688		};
1689
1690		vin5: video@e6ef5000 {
1691			compatible = "renesas,vin-r8a774e1";
1692			reg = <0 0xe6ef5000 0 0x1000>;
1693			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1694			clocks = <&cpg CPG_MOD 806>;
1695			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1696			resets = <&cpg 806>;
1697			renesas,id = <5>;
1698			status = "disabled";
1699
1700			ports {
1701				#address-cells = <1>;
1702				#size-cells = <0>;
1703
1704				port@1 {
1705					#address-cells = <1>;
1706					#size-cells = <0>;
1707
1708					reg = <1>;
1709
1710					vin5csi20: endpoint@0 {
1711						reg = <0>;
1712						remote-endpoint = <&csi20vin5>;
1713					};
1714				};
1715			};
1716		};
1717
1718		vin6: video@e6ef6000 {
1719			compatible = "renesas,vin-r8a774e1";
1720			reg = <0 0xe6ef6000 0 0x1000>;
1721			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1722			clocks = <&cpg CPG_MOD 805>;
1723			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1724			resets = <&cpg 805>;
1725			renesas,id = <6>;
1726			status = "disabled";
1727
1728			ports {
1729				#address-cells = <1>;
1730				#size-cells = <0>;
1731
1732				port@1 {
1733					#address-cells = <1>;
1734					#size-cells = <0>;
1735
1736					reg = <1>;
1737
1738					vin6csi20: endpoint@0 {
1739						reg = <0>;
1740						remote-endpoint = <&csi20vin6>;
1741					};
1742				};
1743			};
1744		};
1745
1746		vin7: video@e6ef7000 {
1747			compatible = "renesas,vin-r8a774e1";
1748			reg = <0 0xe6ef7000 0 0x1000>;
1749			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1750			clocks = <&cpg CPG_MOD 804>;
1751			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1752			resets = <&cpg 804>;
1753			renesas,id = <7>;
1754			status = "disabled";
1755
1756			ports {
1757				#address-cells = <1>;
1758				#size-cells = <0>;
1759
1760				port@1 {
1761					#address-cells = <1>;
1762					#size-cells = <0>;
1763
1764					reg = <1>;
1765
1766					vin7csi20: endpoint@0 {
1767						reg = <0>;
1768						remote-endpoint = <&csi20vin7>;
1769					};
1770				};
1771			};
1772		};
1773
1774		rcar_sound: sound@ec500000 {
1775			/*
1776			 * #sound-dai-cells is required
1777			 *
1778			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
1779			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
1780			 */
1781			/*
1782			 * #clock-cells is required for audio_clkout0/1/2/3
1783			 *
1784			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
1785			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
1786			 */
1787			compatible =  "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
1788			reg = <0 0xec500000 0 0x1000>, /* SCU */
1789			      <0 0xec5a0000 0 0x100>,  /* ADG */
1790			      <0 0xec540000 0 0x1000>, /* SSIU */
1791			      <0 0xec541000 0 0x280>,  /* SSI */
1792			      <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
1793			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1794
1795			clocks = <&cpg CPG_MOD 1005>,
1796				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1797				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1798				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1799				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1800				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1801				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1802				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1803				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1804				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1805				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1806				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1807				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1808				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1809				 <&audio_clk_a>, <&audio_clk_b>,
1810				 <&audio_clk_c>,
1811				 <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
1812			clock-names = "ssi-all",
1813				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1814				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1815				      "ssi.1", "ssi.0",
1816				      "src.9", "src.8", "src.7", "src.6",
1817				      "src.5", "src.4", "src.3", "src.2",
1818				      "src.1", "src.0",
1819				      "mix.1", "mix.0",
1820				      "ctu.1", "ctu.0",
1821				      "dvc.0", "dvc.1",
1822				      "clk_a", "clk_b", "clk_c", "clk_i";
1823			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1824			resets = <&cpg 1005>,
1825				 <&cpg 1006>, <&cpg 1007>,
1826				 <&cpg 1008>, <&cpg 1009>,
1827				 <&cpg 1010>, <&cpg 1011>,
1828				 <&cpg 1012>, <&cpg 1013>,
1829				 <&cpg 1014>, <&cpg 1015>;
1830			reset-names = "ssi-all",
1831				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1832				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1833				      "ssi.1", "ssi.0";
1834			status = "disabled";
1835
1836			rcar_sound,dvc {
1837				dvc0: dvc-0 {
1838					dmas = <&audma1 0xbc>;
1839					dma-names = "tx";
1840				};
1841				dvc1: dvc-1 {
1842					dmas = <&audma1 0xbe>;
1843					dma-names = "tx";
1844				};
1845			};
1846
1847			rcar_sound,mix {
1848				mix0: mix-0 { };
1849				mix1: mix-1 { };
1850			};
1851
1852			rcar_sound,ctu {
1853				ctu00: ctu-0 { };
1854				ctu01: ctu-1 { };
1855				ctu02: ctu-2 { };
1856				ctu03: ctu-3 { };
1857				ctu10: ctu-4 { };
1858				ctu11: ctu-5 { };
1859				ctu12: ctu-6 { };
1860				ctu13: ctu-7 { };
1861			};
1862
1863			rcar_sound,src {
1864				src0: src-0 {
1865					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1866					dmas = <&audma0 0x85>, <&audma1 0x9a>;
1867					dma-names = "rx", "tx";
1868				};
1869				src1: src-1 {
1870					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1871					dmas = <&audma0 0x87>, <&audma1 0x9c>;
1872					dma-names = "rx", "tx";
1873				};
1874				src2: src-2 {
1875					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1876					dmas = <&audma0 0x89>, <&audma1 0x9e>;
1877					dma-names = "rx", "tx";
1878				};
1879				src3: src-3 {
1880					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1881					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1882					dma-names = "rx", "tx";
1883				};
1884				src4: src-4 {
1885					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1886					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1887					dma-names = "rx", "tx";
1888				};
1889				src5: src-5 {
1890					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1891					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1892					dma-names = "rx", "tx";
1893				};
1894				src6: src-6 {
1895					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1896					dmas = <&audma0 0x91>, <&audma1 0xb4>;
1897					dma-names = "rx", "tx";
1898				};
1899				src7: src-7 {
1900					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1901					dmas = <&audma0 0x93>, <&audma1 0xb6>;
1902					dma-names = "rx", "tx";
1903				};
1904				src8: src-8 {
1905					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1906					dmas = <&audma0 0x95>, <&audma1 0xb8>;
1907					dma-names = "rx", "tx";
1908				};
1909				src9: src-9 {
1910					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1911					dmas = <&audma0 0x97>, <&audma1 0xba>;
1912					dma-names = "rx", "tx";
1913				};
1914			};
1915
1916			rcar_sound,ssiu {
1917				ssiu00: ssiu-0 {
1918					dmas = <&audma0 0x15>, <&audma1 0x16>;
1919					dma-names = "rx", "tx";
1920				};
1921				ssiu01: ssiu-1 {
1922					dmas = <&audma0 0x35>, <&audma1 0x36>;
1923					dma-names = "rx", "tx";
1924				};
1925				ssiu02: ssiu-2 {
1926					dmas = <&audma0 0x37>, <&audma1 0x38>;
1927					dma-names = "rx", "tx";
1928				};
1929				ssiu03: ssiu-3 {
1930					dmas = <&audma0 0x47>, <&audma1 0x48>;
1931					dma-names = "rx", "tx";
1932				};
1933				ssiu04: ssiu-4 {
1934					dmas = <&audma0 0x3F>, <&audma1 0x40>;
1935					dma-names = "rx", "tx";
1936				};
1937				ssiu05: ssiu-5 {
1938					dmas = <&audma0 0x43>, <&audma1 0x44>;
1939					dma-names = "rx", "tx";
1940				};
1941				ssiu06: ssiu-6 {
1942					dmas = <&audma0 0x4F>, <&audma1 0x50>;
1943					dma-names = "rx", "tx";
1944				};
1945				ssiu07: ssiu-7 {
1946					dmas = <&audma0 0x53>, <&audma1 0x54>;
1947					dma-names = "rx", "tx";
1948				};
1949				ssiu10: ssiu-8 {
1950					dmas = <&audma0 0x49>, <&audma1 0x4a>;
1951					dma-names = "rx", "tx";
1952				};
1953				ssiu11: ssiu-9 {
1954					dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1955					dma-names = "rx", "tx";
1956				};
1957				ssiu12: ssiu-10 {
1958					dmas = <&audma0 0x57>, <&audma1 0x58>;
1959					dma-names = "rx", "tx";
1960				};
1961				ssiu13: ssiu-11 {
1962					dmas = <&audma0 0x59>, <&audma1 0x5A>;
1963					dma-names = "rx", "tx";
1964				};
1965				ssiu14: ssiu-12 {
1966					dmas = <&audma0 0x5F>, <&audma1 0x60>;
1967					dma-names = "rx", "tx";
1968				};
1969				ssiu15: ssiu-13 {
1970					dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1971					dma-names = "rx", "tx";
1972				};
1973				ssiu16: ssiu-14 {
1974					dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1975					dma-names = "rx", "tx";
1976				};
1977				ssiu17: ssiu-15 {
1978					dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1979					dma-names = "rx", "tx";
1980				};
1981				ssiu20: ssiu-16 {
1982					dmas = <&audma0 0x63>, <&audma1 0x64>;
1983					dma-names = "rx", "tx";
1984				};
1985				ssiu21: ssiu-17 {
1986					dmas = <&audma0 0x67>, <&audma1 0x68>;
1987					dma-names = "rx", "tx";
1988				};
1989				ssiu22: ssiu-18 {
1990					dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1991					dma-names = "rx", "tx";
1992				};
1993				ssiu23: ssiu-19 {
1994					dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1995					dma-names = "rx", "tx";
1996				};
1997				ssiu24: ssiu-20 {
1998					dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1999					dma-names = "rx", "tx";
2000				};
2001				ssiu25: ssiu-21 {
2002					dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2003					dma-names = "rx", "tx";
2004				};
2005				ssiu26: ssiu-22 {
2006					dmas = <&audma0 0xED>, <&audma1 0xEE>;
2007					dma-names = "rx", "tx";
2008				};
2009				ssiu27: ssiu-23 {
2010					dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2011					dma-names = "rx", "tx";
2012				};
2013				ssiu30: ssiu-24 {
2014					dmas = <&audma0 0x6f>, <&audma1 0x70>;
2015					dma-names = "rx", "tx";
2016				};
2017				ssiu31: ssiu-25 {
2018					dmas = <&audma0 0x21>, <&audma1 0x22>;
2019					dma-names = "rx", "tx";
2020				};
2021				ssiu32: ssiu-26 {
2022					dmas = <&audma0 0x23>, <&audma1 0x24>;
2023					dma-names = "rx", "tx";
2024				};
2025				ssiu33: ssiu-27 {
2026					dmas = <&audma0 0x25>, <&audma1 0x26>;
2027					dma-names = "rx", "tx";
2028				};
2029				ssiu34: ssiu-28 {
2030					dmas = <&audma0 0x27>, <&audma1 0x28>;
2031					dma-names = "rx", "tx";
2032				};
2033				ssiu35: ssiu-29 {
2034					dmas = <&audma0 0x29>, <&audma1 0x2A>;
2035					dma-names = "rx", "tx";
2036				};
2037				ssiu36: ssiu-30 {
2038					dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2039					dma-names = "rx", "tx";
2040				};
2041				ssiu37: ssiu-31 {
2042					dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2043					dma-names = "rx", "tx";
2044				};
2045				ssiu40: ssiu-32 {
2046					dmas =	<&audma0 0x71>, <&audma1 0x72>;
2047					dma-names = "rx", "tx";
2048				};
2049				ssiu41: ssiu-33 {
2050					dmas = <&audma0 0x17>, <&audma1 0x18>;
2051					dma-names = "rx", "tx";
2052				};
2053				ssiu42: ssiu-34 {
2054					dmas = <&audma0 0x19>, <&audma1 0x1A>;
2055					dma-names = "rx", "tx";
2056				};
2057				ssiu43: ssiu-35 {
2058					dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2059					dma-names = "rx", "tx";
2060				};
2061				ssiu44: ssiu-36 {
2062					dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2063					dma-names = "rx", "tx";
2064				};
2065				ssiu45: ssiu-37 {
2066					dmas = <&audma0 0x1F>, <&audma1 0x20>;
2067					dma-names = "rx", "tx";
2068				};
2069				ssiu46: ssiu-38 {
2070					dmas = <&audma0 0x31>, <&audma1 0x32>;
2071					dma-names = "rx", "tx";
2072				};
2073				ssiu47: ssiu-39 {
2074					dmas = <&audma0 0x33>, <&audma1 0x34>;
2075					dma-names = "rx", "tx";
2076				};
2077				ssiu50: ssiu-40 {
2078					dmas = <&audma0 0x73>, <&audma1 0x74>;
2079					dma-names = "rx", "tx";
2080				};
2081				ssiu60: ssiu-41 {
2082					dmas = <&audma0 0x75>, <&audma1 0x76>;
2083					dma-names = "rx", "tx";
2084				};
2085				ssiu70: ssiu-42 {
2086					dmas = <&audma0 0x79>, <&audma1 0x7a>;
2087					dma-names = "rx", "tx";
2088				};
2089				ssiu80: ssiu-43 {
2090					dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2091					dma-names = "rx", "tx";
2092				};
2093				ssiu90: ssiu-44 {
2094					dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2095					dma-names = "rx", "tx";
2096				};
2097				ssiu91: ssiu-45 {
2098					dmas = <&audma0 0x7F>, <&audma1 0x80>;
2099					dma-names = "rx", "tx";
2100				};
2101				ssiu92: ssiu-46 {
2102					dmas = <&audma0 0x81>, <&audma1 0x82>;
2103					dma-names = "rx", "tx";
2104				};
2105				ssiu93: ssiu-47 {
2106					dmas = <&audma0 0x83>, <&audma1 0x84>;
2107					dma-names = "rx", "tx";
2108				};
2109				ssiu94: ssiu-48 {
2110					dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2111					dma-names = "rx", "tx";
2112				};
2113				ssiu95: ssiu-49 {
2114					dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2115					dma-names = "rx", "tx";
2116				};
2117				ssiu96: ssiu-50 {
2118					dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2119					dma-names = "rx", "tx";
2120				};
2121				ssiu97: ssiu-51 {
2122					dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2123					dma-names = "rx", "tx";
2124				};
2125			};
2126
2127			rcar_sound,ssi {
2128				ssi0: ssi-0 {
2129					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2130					dmas = <&audma0 0x01>, <&audma1 0x02>;
2131					dma-names = "rx", "tx";
2132				};
2133				ssi1: ssi-1 {
2134					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2135					dmas = <&audma0 0x03>, <&audma1 0x04>;
2136					dma-names = "rx", "tx";
2137				};
2138				ssi2: ssi-2 {
2139					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2140					dmas = <&audma0 0x05>, <&audma1 0x06>;
2141					dma-names = "rx", "tx";
2142				};
2143				ssi3: ssi-3 {
2144					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2145					dmas = <&audma0 0x07>, <&audma1 0x08>;
2146					dma-names = "rx", "tx";
2147				};
2148				ssi4: ssi-4 {
2149					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2150					dmas = <&audma0 0x09>, <&audma1 0x0a>;
2151					dma-names = "rx", "tx";
2152				};
2153				ssi5: ssi-5 {
2154					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2155					dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2156					dma-names = "rx", "tx";
2157				};
2158				ssi6: ssi-6 {
2159					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2160					dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2161					dma-names = "rx", "tx";
2162				};
2163				ssi7: ssi-7 {
2164					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2165					dmas = <&audma0 0x0f>, <&audma1 0x10>;
2166					dma-names = "rx", "tx";
2167				};
2168				ssi8: ssi-8 {
2169					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2170					dmas = <&audma0 0x11>, <&audma1 0x12>;
2171					dma-names = "rx", "tx";
2172				};
2173				ssi9: ssi-9 {
2174					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2175					dmas = <&audma0 0x13>, <&audma1 0x14>;
2176					dma-names = "rx", "tx";
2177				};
2178			};
2179		};
2180
2181		audma0: dma-controller@ec700000 {
2182			compatible = "renesas,dmac-r8a774e1",
2183				     "renesas,rcar-dmac";
2184			reg = <0 0xec700000 0 0x10000>;
2185			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2186				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2187				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2188				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2189				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2190				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2191				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2192				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2193				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2194				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2195				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2196				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2197				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2198				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2199				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2200				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2201				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2202			interrupt-names = "error",
2203					  "ch0", "ch1", "ch2", "ch3",
2204					  "ch4", "ch5", "ch6", "ch7",
2205					  "ch8", "ch9", "ch10", "ch11",
2206					  "ch12", "ch13", "ch14", "ch15";
2207			clocks = <&cpg CPG_MOD 502>;
2208			clock-names = "fck";
2209			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2210			resets = <&cpg 502>;
2211			#dma-cells = <1>;
2212			dma-channels = <16>;
2213			iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2214				 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2215				 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2216				 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2217				 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2218				 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2219				 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2220				 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
2221		};
2222
2223		audma1: dma-controller@ec720000 {
2224			compatible = "renesas,dmac-r8a774e1",
2225				     "renesas,rcar-dmac";
2226			reg = <0 0xec720000 0 0x10000>;
2227			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2228				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2229				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2230				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2231				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2232				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2233				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2234				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2235				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2236				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2237				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2238				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2239				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2240				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2241				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2242				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2243				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2244			interrupt-names = "error",
2245					  "ch0", "ch1", "ch2", "ch3",
2246					  "ch4", "ch5", "ch6", "ch7",
2247					  "ch8", "ch9", "ch10", "ch11",
2248					  "ch12", "ch13", "ch14", "ch15";
2249			clocks = <&cpg CPG_MOD 501>;
2250			clock-names = "fck";
2251			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2252			resets = <&cpg 501>;
2253			#dma-cells = <1>;
2254			dma-channels = <16>;
2255			iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2256				 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2257				 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2258				 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2259				 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2260				 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2261				 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2262				 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
2263		};
2264
2265		xhci0: usb@ee000000 {
2266			compatible = "renesas,xhci-r8a774e1",
2267				     "renesas,rcar-gen3-xhci";
2268			reg = <0 0xee000000 0 0xc00>;
2269			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2270			clocks = <&cpg CPG_MOD 328>;
2271			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2272			resets = <&cpg 328>;
2273			status = "disabled";
2274		};
2275
2276		usb3_peri0: usb@ee020000 {
2277			compatible = "renesas,r8a774e1-usb3-peri",
2278				     "renesas,rcar-gen3-usb3-peri";
2279			reg = <0 0xee020000 0 0x400>;
2280			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2281			clocks = <&cpg CPG_MOD 328>;
2282			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2283			resets = <&cpg 328>;
2284			status = "disabled";
2285		};
2286
2287		ohci0: usb@ee080000 {
2288			compatible = "generic-ohci";
2289			reg = <0 0xee080000 0 0x100>;
2290			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2291			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2292			phys = <&usb2_phy0 1>;
2293			phy-names = "usb";
2294			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2295			resets = <&cpg 703>, <&cpg 704>;
2296			status = "disabled";
2297		};
2298
2299		ohci1: usb@ee0a0000 {
2300			compatible = "generic-ohci";
2301			reg = <0 0xee0a0000 0 0x100>;
2302			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2303			clocks = <&cpg CPG_MOD 702>;
2304			phys = <&usb2_phy1 1>;
2305			phy-names = "usb";
2306			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2307			resets = <&cpg 702>;
2308			status = "disabled";
2309		};
2310
2311		ehci0: usb@ee080100 {
2312			compatible = "generic-ehci";
2313			reg = <0 0xee080100 0 0x100>;
2314			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2315			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2316			phys = <&usb2_phy0 2>;
2317			phy-names = "usb";
2318			companion = <&ohci0>;
2319			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2320			resets = <&cpg 703>, <&cpg 704>;
2321			status = "disabled";
2322		};
2323
2324		ehci1: usb@ee0a0100 {
2325			compatible = "generic-ehci";
2326			reg = <0 0xee0a0100 0 0x100>;
2327			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2328			clocks = <&cpg CPG_MOD 702>;
2329			phys = <&usb2_phy1 2>;
2330			phy-names = "usb";
2331			companion = <&ohci1>;
2332			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2333			resets = <&cpg 702>;
2334			status = "disabled";
2335		};
2336
2337		usb2_phy0: usb-phy@ee080200 {
2338			compatible = "renesas,usb2-phy-r8a774e1",
2339				     "renesas,rcar-gen3-usb2-phy";
2340			reg = <0 0xee080200 0 0x700>;
2341			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2342			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2343			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2344			resets = <&cpg 703>, <&cpg 704>;
2345			#phy-cells = <1>;
2346			status = "disabled";
2347		};
2348
2349		usb2_phy1: usb-phy@ee0a0200 {
2350			compatible = "renesas,usb2-phy-r8a774e1",
2351				     "renesas,rcar-gen3-usb2-phy";
2352			reg = <0 0xee0a0200 0 0x700>;
2353			clocks = <&cpg CPG_MOD 702>;
2354			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2355			resets = <&cpg 702>;
2356			#phy-cells = <1>;
2357			status = "disabled";
2358		};
2359
2360		sdhi0: mmc@ee100000 {
2361			compatible = "renesas,sdhi-r8a774e1",
2362				     "renesas,rcar-gen3-sdhi";
2363			reg = <0 0xee100000 0 0x2000>;
2364			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2365			clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
2366			clock-names = "core", "clkh";
2367			max-frequency = <200000000>;
2368			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2369			resets = <&cpg 314>;
2370			iommus = <&ipmmu_ds1 32>;
2371			status = "disabled";
2372		};
2373
2374		sdhi1: mmc@ee120000 {
2375			compatible = "renesas,sdhi-r8a774e1",
2376				     "renesas,rcar-gen3-sdhi";
2377			reg = <0 0xee120000 0 0x2000>;
2378			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2379			clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
2380			clock-names = "core", "clkh";
2381			max-frequency = <200000000>;
2382			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2383			resets = <&cpg 313>;
2384			iommus = <&ipmmu_ds1 33>;
2385			status = "disabled";
2386		};
2387
2388		sdhi2: mmc@ee140000 {
2389			compatible = "renesas,sdhi-r8a774e1",
2390				     "renesas,rcar-gen3-sdhi";
2391			reg = <0 0xee140000 0 0x2000>;
2392			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2393			clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
2394			clock-names = "core", "clkh";
2395			max-frequency = <200000000>;
2396			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2397			resets = <&cpg 312>;
2398			iommus = <&ipmmu_ds1 34>;
2399			status = "disabled";
2400		};
2401
2402		sdhi3: mmc@ee160000 {
2403			compatible = "renesas,sdhi-r8a774e1",
2404				     "renesas,rcar-gen3-sdhi";
2405			reg = <0 0xee160000 0 0x2000>;
2406			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2407			clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
2408			clock-names = "core", "clkh";
2409			max-frequency = <200000000>;
2410			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2411			resets = <&cpg 311>;
2412			iommus = <&ipmmu_ds1 35>;
2413			status = "disabled";
2414		};
2415
2416		rpc: spi@ee200000 {
2417			compatible = "renesas,r8a774e1-rpc-if",
2418				     "renesas,rcar-gen3-rpc-if";
2419			reg = <0 0xee200000 0 0x200>,
2420			      <0 0x08000000 0 0x4000000>,
2421			      <0 0xee208000 0 0x100>;
2422			reg-names = "regs", "dirmap", "wbuf";
2423			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2424			clocks = <&cpg CPG_MOD 917>;
2425			clock-names = "rpc";
2426			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2427			resets = <&cpg 917>;
2428			#address-cells = <1>;
2429			#size-cells = <0>;
2430			status = "disabled";
2431		};
2432
2433		sata: sata@ee300000 {
2434			compatible = "renesas,sata-r8a774e1",
2435				     "renesas,rcar-gen3-sata";
2436			reg = <0 0xee300000 0 0x200000>;
2437			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2438			clocks = <&cpg CPG_MOD 815>;
2439			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2440			resets = <&cpg 815>;
2441			iommus = <&ipmmu_hc 2>;
2442			status = "disabled";
2443		};
2444
2445		gic: interrupt-controller@f1010000 {
2446			compatible = "arm,gic-400";
2447			#interrupt-cells = <3>;
2448			#address-cells = <0>;
2449			interrupt-controller;
2450			reg = <0x0 0xf1010000 0 0x1000>,
2451			      <0x0 0xf1020000 0 0x20000>,
2452			      <0x0 0xf1040000 0 0x20000>,
2453			      <0x0 0xf1060000 0 0x20000>;
2454			interrupts = <GIC_PPI 9
2455					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2456			clocks = <&cpg CPG_MOD 408>;
2457			clock-names = "clk";
2458			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2459			resets = <&cpg 408>;
2460		};
2461
2462		pciec0: pcie@fe000000 {
2463			compatible = "renesas,pcie-r8a774e1",
2464				     "renesas,pcie-rcar-gen3";
2465			reg = <0 0xfe000000 0 0x80000>;
2466			#address-cells = <3>;
2467			#size-cells = <2>;
2468			bus-range = <0x00 0xff>;
2469			device_type = "pci";
2470			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2471				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2472				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2473				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2474			/* Map all possible DDR as inbound ranges */
2475			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2476			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2477				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2478				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2479			#interrupt-cells = <1>;
2480			interrupt-map-mask = <0 0 0 0>;
2481			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2482			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2483			clock-names = "pcie", "pcie_bus";
2484			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2485			resets = <&cpg 319>;
2486			status = "disabled";
2487		};
2488
2489		pciec1: pcie@ee800000 {
2490			compatible = "renesas,pcie-r8a774e1",
2491				     "renesas,pcie-rcar-gen3";
2492			reg = <0 0xee800000 0 0x80000>;
2493			#address-cells = <3>;
2494			#size-cells = <2>;
2495			bus-range = <0x00 0xff>;
2496			device_type = "pci";
2497			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2498				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2499				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2500				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2501			/* Map all possible DDR as inbound ranges */
2502			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2503			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2504				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2505				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2506			#interrupt-cells = <1>;
2507			interrupt-map-mask = <0 0 0 0>;
2508			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2509			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2510			clock-names = "pcie", "pcie_bus";
2511			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2512			resets = <&cpg 318>;
2513			status = "disabled";
2514		};
2515
2516		pciec0_ep: pcie-ep@fe000000 {
2517			compatible = "renesas,r8a774e1-pcie-ep",
2518				     "renesas,rcar-gen3-pcie-ep";
2519			reg = <0x0 0xfe000000 0 0x80000>,
2520			      <0x0 0xfe100000 0 0x100000>,
2521			      <0x0 0xfe200000 0 0x200000>,
2522			      <0x0 0x30000000 0 0x8000000>,
2523			      <0x0 0x38000000 0 0x8000000>;
2524			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2525			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2526				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2527				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2528			clocks = <&cpg CPG_MOD 319>;
2529			clock-names = "pcie";
2530			resets = <&cpg 319>;
2531			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2532			status = "disabled";
2533		};
2534
2535		pciec1_ep: pcie-ep@ee800000 {
2536			compatible = "renesas,r8a774e1-pcie-ep",
2537				     "renesas,rcar-gen3-pcie-ep";
2538			reg = <0x0 0xee800000 0 0x80000>,
2539			      <0x0 0xee900000 0 0x100000>,
2540			      <0x0 0xeea00000 0 0x200000>,
2541			      <0x0 0xc0000000 0 0x8000000>,
2542			      <0x0 0xc8000000 0 0x8000000>;
2543			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2544			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2545				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2546				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2547			clocks = <&cpg CPG_MOD 318>;
2548			clock-names = "pcie";
2549			resets = <&cpg 318>;
2550			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2551			status = "disabled";
2552		};
2553
2554		vspbc: vsp@fe920000 {
2555			compatible = "renesas,vsp2";
2556			reg = <0 0xfe920000 0 0x8000>;
2557			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2558			clocks = <&cpg CPG_MOD 624>;
2559			power-domains = <&sysc R8A774E1_PD_A3VP>;
2560			resets = <&cpg 624>;
2561
2562			renesas,fcp = <&fcpvb1>;
2563		};
2564
2565		vspbd: vsp@fe960000 {
2566			compatible = "renesas,vsp2";
2567			reg = <0 0xfe960000 0 0x8000>;
2568			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2569			clocks = <&cpg CPG_MOD 626>;
2570			power-domains = <&sysc R8A774E1_PD_A3VP>;
2571			resets = <&cpg 626>;
2572
2573			renesas,fcp = <&fcpvb0>;
2574		};
2575
2576		vspd0: vsp@fea20000 {
2577			compatible = "renesas,vsp2";
2578			reg = <0 0xfea20000 0 0x5000>;
2579			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2580			clocks = <&cpg CPG_MOD 623>;
2581			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2582			resets = <&cpg 623>;
2583
2584			renesas,fcp = <&fcpvd0>;
2585		};
2586
2587		vspd1: vsp@fea28000 {
2588			compatible = "renesas,vsp2";
2589			reg = <0 0xfea28000 0 0x5000>;
2590			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2591			clocks = <&cpg CPG_MOD 622>;
2592			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2593			resets = <&cpg 622>;
2594
2595			renesas,fcp = <&fcpvd1>;
2596		};
2597
2598		vspi0: vsp@fe9a0000 {
2599			compatible = "renesas,vsp2";
2600			reg = <0 0xfe9a0000 0 0x8000>;
2601			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2602			clocks = <&cpg CPG_MOD 631>;
2603			power-domains = <&sysc R8A774E1_PD_A3VP>;
2604			resets = <&cpg 631>;
2605
2606			renesas,fcp = <&fcpvi0>;
2607		};
2608
2609		vspi1: vsp@fe9b0000 {
2610			compatible = "renesas,vsp2";
2611			reg = <0 0xfe9b0000 0 0x8000>;
2612			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2613			clocks = <&cpg CPG_MOD 630>;
2614			power-domains = <&sysc R8A774E1_PD_A3VP>;
2615			resets = <&cpg 630>;
2616
2617			renesas,fcp = <&fcpvi1>;
2618		};
2619
2620		fdp1@fe940000 {
2621			compatible = "renesas,fdp1";
2622			reg = <0 0xfe940000 0 0x2400>;
2623			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2624			clocks = <&cpg CPG_MOD 119>;
2625			power-domains = <&sysc R8A774E1_PD_A3VP>;
2626			resets = <&cpg 119>;
2627			renesas,fcp = <&fcpf0>;
2628		};
2629
2630		fdp1@fe944000 {
2631			compatible = "renesas,fdp1";
2632			reg = <0 0xfe944000 0 0x2400>;
2633			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2634			clocks = <&cpg CPG_MOD 118>;
2635			power-domains = <&sysc R8A774E1_PD_A3VP>;
2636			resets = <&cpg 118>;
2637			renesas,fcp = <&fcpf1>;
2638		};
2639
2640		fcpf0: fcp@fe950000 {
2641			compatible = "renesas,fcpf";
2642			reg = <0 0xfe950000 0 0x200>;
2643			clocks = <&cpg CPG_MOD 615>;
2644			power-domains = <&sysc R8A774E1_PD_A3VP>;
2645			resets = <&cpg 615>;
2646		};
2647
2648		fcpf1: fcp@fe951000 {
2649			compatible = "renesas,fcpf";
2650			reg = <0 0xfe951000 0 0x200>;
2651			clocks = <&cpg CPG_MOD 614>;
2652			power-domains = <&sysc R8A774E1_PD_A3VP>;
2653			resets = <&cpg 614>;
2654		};
2655
2656		fcpvb0: fcp@fe96f000 {
2657			compatible = "renesas,fcpv";
2658			reg = <0 0xfe96f000 0 0x200>;
2659			clocks = <&cpg CPG_MOD 607>;
2660			power-domains = <&sysc R8A774E1_PD_A3VP>;
2661			resets = <&cpg 607>;
2662		};
2663
2664		fcpvb1: fcp@fe92f000 {
2665			compatible = "renesas,fcpv";
2666			reg = <0 0xfe92f000 0 0x200>;
2667			clocks = <&cpg CPG_MOD 606>;
2668			power-domains = <&sysc R8A774E1_PD_A3VP>;
2669			resets = <&cpg 606>;
2670		};
2671
2672		fcpvi0: fcp@fe9af000 {
2673			compatible = "renesas,fcpv";
2674			reg = <0 0xfe9af000 0 0x200>;
2675			clocks = <&cpg CPG_MOD 611>;
2676			power-domains = <&sysc R8A774E1_PD_A3VP>;
2677			resets = <&cpg 611>;
2678		};
2679
2680		fcpvi1: fcp@fe9bf000 {
2681			compatible = "renesas,fcpv";
2682			reg = <0 0xfe9bf000 0 0x200>;
2683			clocks = <&cpg CPG_MOD 610>;
2684			power-domains = <&sysc R8A774E1_PD_A3VP>;
2685			resets = <&cpg 610>;
2686		};
2687
2688		fcpvd0: fcp@fea27000 {
2689			compatible = "renesas,fcpv";
2690			reg = <0 0xfea27000 0 0x200>;
2691			clocks = <&cpg CPG_MOD 603>;
2692			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2693			resets = <&cpg 603>;
2694		};
2695
2696		fcpvd1: fcp@fea2f000 {
2697			compatible = "renesas,fcpv";
2698			reg = <0 0xfea2f000 0 0x200>;
2699			clocks = <&cpg CPG_MOD 602>;
2700			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2701			resets = <&cpg 602>;
2702		};
2703
2704		csi20: csi2@fea80000 {
2705			compatible = "renesas,r8a774e1-csi2";
2706			reg = <0 0xfea80000 0 0x10000>;
2707			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2708			clocks = <&cpg CPG_MOD 714>;
2709			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2710			resets = <&cpg 714>;
2711			status = "disabled";
2712
2713			ports {
2714				#address-cells = <1>;
2715				#size-cells = <0>;
2716
2717				port@0 {
2718					reg = <0>;
2719				};
2720
2721				port@1 {
2722					#address-cells = <1>;
2723					#size-cells = <0>;
2724
2725					reg = <1>;
2726
2727					csi20vin0: endpoint@0 {
2728						reg = <0>;
2729						remote-endpoint = <&vin0csi20>;
2730					};
2731					csi20vin1: endpoint@1 {
2732						reg = <1>;
2733						remote-endpoint = <&vin1csi20>;
2734					};
2735					csi20vin2: endpoint@2 {
2736						reg = <2>;
2737						remote-endpoint = <&vin2csi20>;
2738					};
2739					csi20vin3: endpoint@3 {
2740						reg = <3>;
2741						remote-endpoint = <&vin3csi20>;
2742					};
2743					csi20vin4: endpoint@4 {
2744						reg = <4>;
2745						remote-endpoint = <&vin4csi20>;
2746					};
2747					csi20vin5: endpoint@5 {
2748						reg = <5>;
2749						remote-endpoint = <&vin5csi20>;
2750					};
2751					csi20vin6: endpoint@6 {
2752						reg = <6>;
2753						remote-endpoint = <&vin6csi20>;
2754					};
2755					csi20vin7: endpoint@7 {
2756						reg = <7>;
2757						remote-endpoint = <&vin7csi20>;
2758					};
2759				};
2760			};
2761		};
2762
2763		csi40: csi2@feaa0000 {
2764			compatible = "renesas,r8a774e1-csi2";
2765			reg = <0 0xfeaa0000 0 0x10000>;
2766			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2767			clocks = <&cpg CPG_MOD 716>;
2768			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2769			resets = <&cpg 716>;
2770			status = "disabled";
2771
2772			ports {
2773				#address-cells = <1>;
2774				#size-cells = <0>;
2775
2776				port@0 {
2777					reg = <0>;
2778				};
2779
2780				port@1 {
2781					#address-cells = <1>;
2782					#size-cells = <0>;
2783
2784					reg = <1>;
2785
2786					csi40vin0: endpoint@0 {
2787						reg = <0>;
2788						remote-endpoint = <&vin0csi40>;
2789					};
2790					csi40vin1: endpoint@1 {
2791						reg = <1>;
2792						remote-endpoint = <&vin1csi40>;
2793					};
2794					csi40vin2: endpoint@2 {
2795						reg = <2>;
2796						remote-endpoint = <&vin2csi40>;
2797					};
2798					csi40vin3: endpoint@3 {
2799						reg = <3>;
2800						remote-endpoint = <&vin3csi40>;
2801					};
2802				};
2803			};
2804		};
2805
2806		hdmi0: hdmi@fead0000 {
2807			compatible = "renesas,r8a774e1-hdmi",
2808				     "renesas,rcar-gen3-hdmi";
2809			reg = <0 0xfead0000 0 0x10000>;
2810			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2811			clocks = <&cpg CPG_MOD 729>,
2812				 <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
2813			clock-names = "iahb", "isfr";
2814			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2815			resets = <&cpg 729>;
2816			status = "disabled";
2817
2818			ports {
2819				#address-cells = <1>;
2820				#size-cells = <0>;
2821
2822				port@0 {
2823					reg = <0>;
2824					dw_hdmi0_in: endpoint {
2825						remote-endpoint = <&du_out_hdmi0>;
2826					};
2827				};
2828				port@1 {
2829					reg = <1>;
2830				};
2831				port@2 {
2832					/* HDMI sound */
2833					reg = <2>;
2834				};
2835			};
2836		};
2837
2838		du: display@feb00000 {
2839			compatible = "renesas,du-r8a774e1";
2840			reg = <0 0xfeb00000 0 0x80000>;
2841			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2842				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2843				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
2844			clocks = <&cpg CPG_MOD 724>,
2845				 <&cpg CPG_MOD 723>,
2846				 <&cpg CPG_MOD 721>;
2847			clock-names = "du.0", "du.1", "du.3";
2848			resets = <&cpg 724>, <&cpg 722>;
2849			reset-names = "du.0", "du.3";
2850			status = "disabled";
2851
2852			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2853
2854			ports {
2855				#address-cells = <1>;
2856				#size-cells = <0>;
2857
2858				port@0 {
2859					reg = <0>;
2860					du_out_rgb: endpoint {
2861					};
2862				};
2863				port@1 {
2864					reg = <1>;
2865					du_out_hdmi0: endpoint {
2866						remote-endpoint = <&dw_hdmi0_in>;
2867					};
2868				};
2869				port@2 {
2870					reg = <2>;
2871					du_out_lvds0: endpoint {
2872						remote-endpoint = <&lvds0_in>;
2873					};
2874				};
2875			};
2876		};
2877
2878		lvds0: lvds@feb90000 {
2879			compatible = "renesas,r8a774e1-lvds";
2880			reg = <0 0xfeb90000 0 0x14>;
2881			clocks = <&cpg CPG_MOD 727>;
2882			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2883			resets = <&cpg 727>;
2884			status = "disabled";
2885
2886			ports {
2887				#address-cells = <1>;
2888				#size-cells = <0>;
2889
2890				port@0 {
2891					reg = <0>;
2892					lvds0_in: endpoint {
2893						remote-endpoint = <&du_out_lvds0>;
2894					};
2895				};
2896				port@1 {
2897					reg = <1>;
2898					lvds0_out: endpoint {
2899					};
2900				};
2901			};
2902		};
2903
2904		prr: chipid@fff00044 {
2905			compatible = "renesas,prr";
2906			reg = <0 0xfff00044 0 4>;
2907		};
2908	};
2909
2910	thermal-zones {
2911		sensor1_thermal: sensor1-thermal {
2912			polling-delay-passive = <250>;
2913			polling-delay = <1000>;
2914			thermal-sensors = <&tsc 0>;
2915			sustainable-power = <6313>;
2916
2917			trips {
2918				sensor1_crit: sensor1-crit {
2919					temperature = <120000>;
2920					hysteresis = <1000>;
2921					type = "critical";
2922				};
2923			};
2924		};
2925
2926		sensor2_thermal: sensor2-thermal {
2927			polling-delay-passive = <250>;
2928			polling-delay = <1000>;
2929			thermal-sensors = <&tsc 1>;
2930			sustainable-power = <6313>;
2931
2932			trips {
2933				sensor2_crit: sensor2-crit {
2934					temperature = <120000>;
2935					hysteresis = <1000>;
2936					type = "critical";
2937				};
2938			};
2939		};
2940
2941		sensor3_thermal: sensor3-thermal {
2942			polling-delay-passive = <250>;
2943			polling-delay = <1000>;
2944			thermal-sensors = <&tsc 2>;
2945			sustainable-power = <6313>;
2946
2947			trips {
2948				target: trip-point1 {
2949					temperature = <100000>;
2950					hysteresis = <1000>;
2951					type = "passive";
2952				};
2953
2954				sensor3_crit: sensor3-crit {
2955					temperature = <120000>;
2956					hysteresis = <1000>;
2957					type = "critical";
2958				};
2959			};
2960
2961			cooling-maps {
2962				map0 {
2963					trip = <&target>;
2964					cooling-device = <&a57_0 0 2>;
2965					contribution = <1024>;
2966				};
2967
2968				map1 {
2969					trip = <&target>;
2970					cooling-device = <&a53_0 0 2>;
2971					contribution = <1024>;
2972				};
2973			};
2974		};
2975	};
2976
2977	timer {
2978		compatible = "arm,armv8-timer";
2979		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2980				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2981				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2982				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2983	};
2984
2985	/* External USB clocks - can be overridden by the board */
2986	usb3s0_clk: usb3s0 {
2987		compatible = "fixed-clock";
2988		#clock-cells = <0>;
2989		clock-frequency = <0>;
2990	};
2991
2992	usb_extal_clk: usb_extal {
2993		compatible = "fixed-clock";
2994		#clock-cells = <0>;
2995		clock-frequency = <0>;
2996	};
2997};
2998