1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp_table10 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 opp-800000000 { 51 opp-hz = /bits/ 64 <800000000>; 52 opp-microvolt = <820000>; 53 clock-latency-ns = <300000>; 54 }; 55 opp-1000000000 { 56 opp-hz = /bits/ 64 <1000000000>; 57 opp-microvolt = <820000>; 58 clock-latency-ns = <300000>; 59 }; 60 opp-1200000000 { 61 opp-hz = /bits/ 64 <1200000000>; 62 opp-microvolt = <820000>; 63 clock-latency-ns = <300000>; 64 opp-suspend; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 a53_0: cpu@0 { 73 compatible = "arm,cortex-a53"; 74 reg = <0>; 75 device_type = "cpu"; 76 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 77 next-level-cache = <&L2_CA53>; 78 enable-method = "psci"; 79 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 80 operating-points-v2 = <&cluster1_opp>; 81 }; 82 83 a53_1: cpu@1 { 84 compatible = "arm,cortex-a53"; 85 reg = <1>; 86 device_type = "cpu"; 87 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 88 next-level-cache = <&L2_CA53>; 89 enable-method = "psci"; 90 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 91 operating-points-v2 = <&cluster1_opp>; 92 }; 93 94 L2_CA53: cache-controller-0 { 95 compatible = "cache"; 96 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 97 cache-unified; 98 cache-level = <2>; 99 }; 100 }; 101 102 extal_clk: extal { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 /* This value must be overridden by the board */ 106 clock-frequency = <0>; 107 }; 108 109 /* External PCIe clock - can be overridden by the board */ 110 pcie_bus_clk: pcie_bus { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <0>; 114 }; 115 116 pmu_a53 { 117 compatible = "arm,cortex-a53-pmu"; 118 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 119 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 120 interrupt-affinity = <&a53_0>, <&a53_1>; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0", "arm,psci-0.2"; 125 method = "smc"; 126 }; 127 128 /* External SCIF clock - to be overridden by boards that provide it */ 129 scif_clk: scif { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 clock-frequency = <0>; 133 }; 134 135 soc: soc { 136 compatible = "simple-bus"; 137 interrupt-parent = <&gic>; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 142 rwdt: watchdog@e6020000 { 143 compatible = "renesas,r8a774c0-wdt", 144 "renesas,rcar-gen3-wdt"; 145 reg = <0 0xe6020000 0 0x0c>; 146 clocks = <&cpg CPG_MOD 402>; 147 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 148 resets = <&cpg 402>; 149 status = "disabled"; 150 }; 151 152 gpio0: gpio@e6050000 { 153 compatible = "renesas,gpio-r8a774c0", 154 "renesas,rcar-gen3-gpio"; 155 reg = <0 0xe6050000 0 0x50>; 156 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 157 #gpio-cells = <2>; 158 gpio-controller; 159 gpio-ranges = <&pfc 0 0 18>; 160 #interrupt-cells = <2>; 161 interrupt-controller; 162 clocks = <&cpg CPG_MOD 912>; 163 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 164 resets = <&cpg 912>; 165 }; 166 167 gpio1: gpio@e6051000 { 168 compatible = "renesas,gpio-r8a774c0", 169 "renesas,rcar-gen3-gpio"; 170 reg = <0 0xe6051000 0 0x50>; 171 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 172 #gpio-cells = <2>; 173 gpio-controller; 174 gpio-ranges = <&pfc 0 32 23>; 175 #interrupt-cells = <2>; 176 interrupt-controller; 177 clocks = <&cpg CPG_MOD 911>; 178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 179 resets = <&cpg 911>; 180 }; 181 182 gpio2: gpio@e6052000 { 183 compatible = "renesas,gpio-r8a774c0", 184 "renesas,rcar-gen3-gpio"; 185 reg = <0 0xe6052000 0 0x50>; 186 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 187 #gpio-cells = <2>; 188 gpio-controller; 189 gpio-ranges = <&pfc 0 64 26>; 190 #interrupt-cells = <2>; 191 interrupt-controller; 192 clocks = <&cpg CPG_MOD 910>; 193 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 194 resets = <&cpg 910>; 195 }; 196 197 gpio3: gpio@e6053000 { 198 compatible = "renesas,gpio-r8a774c0", 199 "renesas,rcar-gen3-gpio"; 200 reg = <0 0xe6053000 0 0x50>; 201 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 202 #gpio-cells = <2>; 203 gpio-controller; 204 gpio-ranges = <&pfc 0 96 16>; 205 #interrupt-cells = <2>; 206 interrupt-controller; 207 clocks = <&cpg CPG_MOD 909>; 208 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 209 resets = <&cpg 909>; 210 }; 211 212 gpio4: gpio@e6054000 { 213 compatible = "renesas,gpio-r8a774c0", 214 "renesas,rcar-gen3-gpio"; 215 reg = <0 0xe6054000 0 0x50>; 216 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 217 #gpio-cells = <2>; 218 gpio-controller; 219 gpio-ranges = <&pfc 0 128 11>; 220 #interrupt-cells = <2>; 221 interrupt-controller; 222 clocks = <&cpg CPG_MOD 908>; 223 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 224 resets = <&cpg 908>; 225 }; 226 227 gpio5: gpio@e6055000 { 228 compatible = "renesas,gpio-r8a774c0", 229 "renesas,rcar-gen3-gpio"; 230 reg = <0 0xe6055000 0 0x50>; 231 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 232 #gpio-cells = <2>; 233 gpio-controller; 234 gpio-ranges = <&pfc 0 160 20>; 235 #interrupt-cells = <2>; 236 interrupt-controller; 237 clocks = <&cpg CPG_MOD 907>; 238 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 239 resets = <&cpg 907>; 240 }; 241 242 gpio6: gpio@e6055400 { 243 compatible = "renesas,gpio-r8a774c0", 244 "renesas,rcar-gen3-gpio"; 245 reg = <0 0xe6055400 0 0x50>; 246 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 247 #gpio-cells = <2>; 248 gpio-controller; 249 gpio-ranges = <&pfc 0 192 18>; 250 #interrupt-cells = <2>; 251 interrupt-controller; 252 clocks = <&cpg CPG_MOD 906>; 253 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 254 resets = <&cpg 906>; 255 }; 256 257 pfc: pin-controller@e6060000 { 258 compatible = "renesas,pfc-r8a774c0"; 259 reg = <0 0xe6060000 0 0x508>; 260 }; 261 262 cmt0: timer@e60f0000 { 263 compatible = "renesas,r8a774c0-cmt0", 264 "renesas,rcar-gen3-cmt0"; 265 reg = <0 0xe60f0000 0 0x1004>; 266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cpg CPG_MOD 303>; 269 clock-names = "fck"; 270 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 271 resets = <&cpg 303>; 272 status = "disabled"; 273 }; 274 275 cmt1: timer@e6130000 { 276 compatible = "renesas,r8a774c0-cmt1", 277 "renesas,rcar-gen3-cmt1"; 278 reg = <0 0xe6130000 0 0x1004>; 279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&cpg CPG_MOD 302>; 288 clock-names = "fck"; 289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 290 resets = <&cpg 302>; 291 status = "disabled"; 292 }; 293 294 cmt2: timer@e6140000 { 295 compatible = "renesas,r8a774c0-cmt1", 296 "renesas,rcar-gen3-cmt1"; 297 reg = <0 0xe6140000 0 0x1004>; 298 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&cpg CPG_MOD 301>; 307 clock-names = "fck"; 308 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 309 resets = <&cpg 301>; 310 status = "disabled"; 311 }; 312 313 cmt3: timer@e6148000 { 314 compatible = "renesas,r8a774c0-cmt1", 315 "renesas,rcar-gen3-cmt1"; 316 reg = <0 0xe6148000 0 0x1004>; 317 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cpg CPG_MOD 300>; 326 clock-names = "fck"; 327 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 328 resets = <&cpg 300>; 329 status = "disabled"; 330 }; 331 332 cpg: clock-controller@e6150000 { 333 compatible = "renesas,r8a774c0-cpg-mssr"; 334 reg = <0 0xe6150000 0 0x1000>; 335 clocks = <&extal_clk>; 336 clock-names = "extal"; 337 #clock-cells = <2>; 338 #power-domain-cells = <0>; 339 #reset-cells = <1>; 340 }; 341 342 rst: reset-controller@e6160000 { 343 compatible = "renesas,r8a774c0-rst"; 344 reg = <0 0xe6160000 0 0x0200>; 345 }; 346 347 sysc: system-controller@e6180000 { 348 compatible = "renesas,r8a774c0-sysc"; 349 reg = <0 0xe6180000 0 0x0400>; 350 #power-domain-cells = <1>; 351 }; 352 353 thermal: thermal@e6190000 { 354 compatible = "renesas,thermal-r8a774c0"; 355 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 356 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&cpg CPG_MOD 522>; 360 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 361 resets = <&cpg 522>; 362 #thermal-sensor-cells = <0>; 363 }; 364 365 intc_ex: interrupt-controller@e61c0000 { 366 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 reg = <0 0xe61c0000 0 0x200>; 370 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cpg CPG_MOD 407>; 377 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 378 resets = <&cpg 407>; 379 }; 380 381 tmu0: timer@e61e0000 { 382 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 383 reg = <0 0xe61e0000 0 0x30>; 384 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 125>; 388 clock-names = "fck"; 389 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 390 resets = <&cpg 125>; 391 status = "disabled"; 392 }; 393 394 tmu1: timer@e6fc0000 { 395 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 396 reg = <0 0xe6fc0000 0 0x30>; 397 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&cpg CPG_MOD 124>; 401 clock-names = "fck"; 402 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 403 resets = <&cpg 124>; 404 status = "disabled"; 405 }; 406 407 tmu2: timer@e6fd0000 { 408 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 409 reg = <0 0xe6fd0000 0 0x30>; 410 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cpg CPG_MOD 123>; 414 clock-names = "fck"; 415 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 416 resets = <&cpg 123>; 417 status = "disabled"; 418 }; 419 420 tmu3: timer@e6fe0000 { 421 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 422 reg = <0 0xe6fe0000 0 0x30>; 423 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&cpg CPG_MOD 122>; 427 clock-names = "fck"; 428 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 429 resets = <&cpg 122>; 430 status = "disabled"; 431 }; 432 433 tmu4: timer@ffc00000 { 434 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 435 reg = <0 0xffc00000 0 0x30>; 436 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 121>; 440 clock-names = "fck"; 441 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 442 resets = <&cpg 121>; 443 status = "disabled"; 444 }; 445 446 i2c0: i2c@e6500000 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "renesas,i2c-r8a774c0", 450 "renesas,rcar-gen3-i2c"; 451 reg = <0 0xe6500000 0 0x40>; 452 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 931>; 454 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 455 resets = <&cpg 931>; 456 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 457 <&dmac2 0x91>, <&dmac2 0x90>; 458 dma-names = "tx", "rx", "tx", "rx"; 459 i2c-scl-internal-delay-ns = <110>; 460 status = "disabled"; 461 }; 462 463 i2c1: i2c@e6508000 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 compatible = "renesas,i2c-r8a774c0", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe6508000 0 0x40>; 469 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 930>; 471 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 472 resets = <&cpg 930>; 473 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 474 <&dmac2 0x93>, <&dmac2 0x92>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 i2c-scl-internal-delay-ns = <6>; 477 status = "disabled"; 478 }; 479 480 i2c2: i2c@e6510000 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 compatible = "renesas,i2c-r8a774c0", 484 "renesas,rcar-gen3-i2c"; 485 reg = <0 0xe6510000 0 0x40>; 486 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 929>; 488 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 489 resets = <&cpg 929>; 490 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 491 <&dmac2 0x95>, <&dmac2 0x94>; 492 dma-names = "tx", "rx", "tx", "rx"; 493 i2c-scl-internal-delay-ns = <6>; 494 status = "disabled"; 495 }; 496 497 i2c3: i2c@e66d0000 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 compatible = "renesas,i2c-r8a774c0", 501 "renesas,rcar-gen3-i2c"; 502 reg = <0 0xe66d0000 0 0x40>; 503 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 928>; 505 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 506 resets = <&cpg 928>; 507 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 508 dma-names = "tx", "rx"; 509 i2c-scl-internal-delay-ns = <110>; 510 status = "disabled"; 511 }; 512 513 i2c4: i2c@e66d8000 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 compatible = "renesas,i2c-r8a774c0", 517 "renesas,rcar-gen3-i2c"; 518 reg = <0 0xe66d8000 0 0x40>; 519 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&cpg CPG_MOD 927>; 521 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 522 resets = <&cpg 927>; 523 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 524 dma-names = "tx", "rx"; 525 i2c-scl-internal-delay-ns = <6>; 526 status = "disabled"; 527 }; 528 529 i2c5: i2c@e66e0000 { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 compatible = "renesas,i2c-r8a774c0", 533 "renesas,rcar-gen3-i2c"; 534 reg = <0 0xe66e0000 0 0x40>; 535 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&cpg CPG_MOD 919>; 537 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 538 resets = <&cpg 919>; 539 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 540 dma-names = "tx", "rx"; 541 i2c-scl-internal-delay-ns = <6>; 542 status = "disabled"; 543 }; 544 545 i2c6: i2c@e66e8000 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 compatible = "renesas,i2c-r8a774c0", 549 "renesas,rcar-gen3-i2c"; 550 reg = <0 0xe66e8000 0 0x40>; 551 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cpg CPG_MOD 918>; 553 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 554 resets = <&cpg 918>; 555 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 556 dma-names = "tx", "rx"; 557 i2c-scl-internal-delay-ns = <6>; 558 status = "disabled"; 559 }; 560 561 i2c7: i2c@e6690000 { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 compatible = "renesas,i2c-r8a774c0", 565 "renesas,rcar-gen3-i2c"; 566 reg = <0 0xe6690000 0 0x40>; 567 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cpg CPG_MOD 1003>; 569 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 570 resets = <&cpg 1003>; 571 i2c-scl-internal-delay-ns = <6>; 572 status = "disabled"; 573 }; 574 575 i2c_dvfs: i2c@e60b0000 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "renesas,iic-r8a774c0"; 579 reg = <0 0xe60b0000 0 0x15>; 580 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 926>; 582 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 583 resets = <&cpg 926>; 584 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 585 dma-names = "tx", "rx"; 586 status = "disabled"; 587 }; 588 589 hscif0: serial@e6540000 { 590 compatible = "renesas,hscif-r8a774c0", 591 "renesas,rcar-gen3-hscif", 592 "renesas,hscif"; 593 reg = <0 0xe6540000 0 0x60>; 594 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 520>, 596 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 597 <&scif_clk>; 598 clock-names = "fck", "brg_int", "scif_clk"; 599 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 600 <&dmac2 0x31>, <&dmac2 0x30>; 601 dma-names = "tx", "rx", "tx", "rx"; 602 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 603 resets = <&cpg 520>; 604 status = "disabled"; 605 }; 606 607 hscif1: serial@e6550000 { 608 compatible = "renesas,hscif-r8a774c0", 609 "renesas,rcar-gen3-hscif", 610 "renesas,hscif"; 611 reg = <0 0xe6550000 0 0x60>; 612 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 519>, 614 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 615 <&scif_clk>; 616 clock-names = "fck", "brg_int", "scif_clk"; 617 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 618 <&dmac2 0x33>, <&dmac2 0x32>; 619 dma-names = "tx", "rx", "tx", "rx"; 620 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 621 resets = <&cpg 519>; 622 status = "disabled"; 623 }; 624 625 hscif2: serial@e6560000 { 626 compatible = "renesas,hscif-r8a774c0", 627 "renesas,rcar-gen3-hscif", 628 "renesas,hscif"; 629 reg = <0 0xe6560000 0 0x60>; 630 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cpg CPG_MOD 518>, 632 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 633 <&scif_clk>; 634 clock-names = "fck", "brg_int", "scif_clk"; 635 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 636 <&dmac2 0x35>, <&dmac2 0x34>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 639 resets = <&cpg 518>; 640 status = "disabled"; 641 }; 642 643 hscif3: serial@e66a0000 { 644 compatible = "renesas,hscif-r8a774c0", 645 "renesas,rcar-gen3-hscif", 646 "renesas,hscif"; 647 reg = <0 0xe66a0000 0 0x60>; 648 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&cpg CPG_MOD 517>, 650 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 651 <&scif_clk>; 652 clock-names = "fck", "brg_int", "scif_clk"; 653 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 654 dma-names = "tx", "rx"; 655 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 656 resets = <&cpg 517>; 657 status = "disabled"; 658 }; 659 660 hscif4: serial@e66b0000 { 661 compatible = "renesas,hscif-r8a774c0", 662 "renesas,rcar-gen3-hscif", 663 "renesas,hscif"; 664 reg = <0 0xe66b0000 0 0x60>; 665 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 516>, 667 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 668 <&scif_clk>; 669 clock-names = "fck", "brg_int", "scif_clk"; 670 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 671 dma-names = "tx", "rx"; 672 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 673 resets = <&cpg 516>; 674 status = "disabled"; 675 }; 676 677 hsusb: usb@e6590000 { 678 compatible = "renesas,usbhs-r8a774c0", 679 "renesas,rcar-gen3-usbhs"; 680 reg = <0 0xe6590000 0 0x200>; 681 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 683 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 684 <&usb_dmac1 0>, <&usb_dmac1 1>; 685 dma-names = "ch0", "ch1", "ch2", "ch3"; 686 renesas,buswait = <11>; 687 phys = <&usb2_phy0 3>; 688 phy-names = "usb"; 689 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 690 resets = <&cpg 704>, <&cpg 703>; 691 status = "disabled"; 692 }; 693 694 usb_dmac0: dma-controller@e65a0000 { 695 compatible = "renesas,r8a774c0-usb-dmac", 696 "renesas,usb-dmac"; 697 reg = <0 0xe65a0000 0 0x100>; 698 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "ch0", "ch1"; 701 clocks = <&cpg CPG_MOD 330>; 702 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 703 resets = <&cpg 330>; 704 #dma-cells = <1>; 705 dma-channels = <2>; 706 }; 707 708 usb_dmac1: dma-controller@e65b0000 { 709 compatible = "renesas,r8a774c0-usb-dmac", 710 "renesas,usb-dmac"; 711 reg = <0 0xe65b0000 0 0x100>; 712 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 713 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "ch0", "ch1"; 715 clocks = <&cpg CPG_MOD 331>; 716 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 717 resets = <&cpg 331>; 718 #dma-cells = <1>; 719 dma-channels = <2>; 720 }; 721 722 dmac0: dma-controller@e6700000 { 723 compatible = "renesas,dmac-r8a774c0", 724 "renesas,rcar-dmac"; 725 reg = <0 0xe6700000 0 0x10000>; 726 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 727 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 728 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 729 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 730 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 731 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 732 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 733 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 734 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 735 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 736 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 737 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 738 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 740 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 741 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 742 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 743 interrupt-names = "error", 744 "ch0", "ch1", "ch2", "ch3", 745 "ch4", "ch5", "ch6", "ch7", 746 "ch8", "ch9", "ch10", "ch11", 747 "ch12", "ch13", "ch14", "ch15"; 748 clocks = <&cpg CPG_MOD 219>; 749 clock-names = "fck"; 750 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 751 resets = <&cpg 219>; 752 #dma-cells = <1>; 753 dma-channels = <16>; 754 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 755 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 756 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 757 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 758 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 759 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 760 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 761 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 762 }; 763 764 dmac1: dma-controller@e7300000 { 765 compatible = "renesas,dmac-r8a774c0", 766 "renesas,rcar-dmac"; 767 reg = <0 0xe7300000 0 0x10000>; 768 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 769 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 770 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 771 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 772 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 773 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 774 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 775 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 776 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 777 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 778 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 779 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 780 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 781 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 782 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 783 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 784 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 785 interrupt-names = "error", 786 "ch0", "ch1", "ch2", "ch3", 787 "ch4", "ch5", "ch6", "ch7", 788 "ch8", "ch9", "ch10", "ch11", 789 "ch12", "ch13", "ch14", "ch15"; 790 clocks = <&cpg CPG_MOD 218>; 791 clock-names = "fck"; 792 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 793 resets = <&cpg 218>; 794 #dma-cells = <1>; 795 dma-channels = <16>; 796 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 797 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 798 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 799 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 800 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 801 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 802 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 803 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 804 }; 805 806 dmac2: dma-controller@e7310000 { 807 compatible = "renesas,dmac-r8a774c0", 808 "renesas,rcar-dmac"; 809 reg = <0 0xe7310000 0 0x10000>; 810 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 811 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 812 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 813 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 814 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 815 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 816 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 817 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 818 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 819 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 820 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 821 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 822 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 823 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 824 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 825 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 826 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 827 interrupt-names = "error", 828 "ch0", "ch1", "ch2", "ch3", 829 "ch4", "ch5", "ch6", "ch7", 830 "ch8", "ch9", "ch10", "ch11", 831 "ch12", "ch13", "ch14", "ch15"; 832 clocks = <&cpg CPG_MOD 217>; 833 clock-names = "fck"; 834 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 835 resets = <&cpg 217>; 836 #dma-cells = <1>; 837 dma-channels = <16>; 838 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 839 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 840 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 841 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 842 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 843 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 844 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 845 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 846 }; 847 848 ipmmu_ds0: mmu@e6740000 { 849 compatible = "renesas,ipmmu-r8a774c0"; 850 reg = <0 0xe6740000 0 0x1000>; 851 renesas,ipmmu-main = <&ipmmu_mm 0>; 852 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 853 #iommu-cells = <1>; 854 }; 855 856 ipmmu_ds1: mmu@e7740000 { 857 compatible = "renesas,ipmmu-r8a774c0"; 858 reg = <0 0xe7740000 0 0x1000>; 859 renesas,ipmmu-main = <&ipmmu_mm 1>; 860 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 861 #iommu-cells = <1>; 862 }; 863 864 ipmmu_hc: mmu@e6570000 { 865 compatible = "renesas,ipmmu-r8a774c0"; 866 reg = <0 0xe6570000 0 0x1000>; 867 renesas,ipmmu-main = <&ipmmu_mm 2>; 868 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 869 #iommu-cells = <1>; 870 }; 871 872 ipmmu_mm: mmu@e67b0000 { 873 compatible = "renesas,ipmmu-r8a774c0"; 874 reg = <0 0xe67b0000 0 0x1000>; 875 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 877 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 878 #iommu-cells = <1>; 879 }; 880 881 ipmmu_mp: mmu@ec670000 { 882 compatible = "renesas,ipmmu-r8a774c0"; 883 reg = <0 0xec670000 0 0x1000>; 884 renesas,ipmmu-main = <&ipmmu_mm 4>; 885 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 886 #iommu-cells = <1>; 887 }; 888 889 ipmmu_pv0: mmu@fd800000 { 890 compatible = "renesas,ipmmu-r8a774c0"; 891 reg = <0 0xfd800000 0 0x1000>; 892 renesas,ipmmu-main = <&ipmmu_mm 6>; 893 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 894 #iommu-cells = <1>; 895 }; 896 897 ipmmu_vc0: mmu@fe6b0000 { 898 compatible = "renesas,ipmmu-r8a774c0"; 899 reg = <0 0xfe6b0000 0 0x1000>; 900 renesas,ipmmu-main = <&ipmmu_mm 12>; 901 power-domains = <&sysc R8A774C0_PD_A3VC>; 902 #iommu-cells = <1>; 903 }; 904 905 ipmmu_vi0: mmu@febd0000 { 906 compatible = "renesas,ipmmu-r8a774c0"; 907 reg = <0 0xfebd0000 0 0x1000>; 908 renesas,ipmmu-main = <&ipmmu_mm 14>; 909 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 910 #iommu-cells = <1>; 911 }; 912 913 ipmmu_vp0: mmu@fe990000 { 914 compatible = "renesas,ipmmu-r8a774c0"; 915 reg = <0 0xfe990000 0 0x1000>; 916 renesas,ipmmu-main = <&ipmmu_mm 16>; 917 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 918 #iommu-cells = <1>; 919 }; 920 921 avb: ethernet@e6800000 { 922 compatible = "renesas,etheravb-r8a774c0", 923 "renesas,etheravb-rcar-gen3"; 924 reg = <0 0xe6800000 0 0x800>; 925 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "ch0", "ch1", "ch2", "ch3", 951 "ch4", "ch5", "ch6", "ch7", 952 "ch8", "ch9", "ch10", "ch11", 953 "ch12", "ch13", "ch14", "ch15", 954 "ch16", "ch17", "ch18", "ch19", 955 "ch20", "ch21", "ch22", "ch23", 956 "ch24"; 957 clocks = <&cpg CPG_MOD 812>; 958 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 959 resets = <&cpg 812>; 960 phy-mode = "rgmii"; 961 iommus = <&ipmmu_ds0 16>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 can0: can@e6c30000 { 968 compatible = "renesas,can-r8a774c0", 969 "renesas,rcar-gen3-can"; 970 reg = <0 0xe6c30000 0 0x1000>; 971 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cpg CPG_MOD 916>, 973 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 974 <&can_clk>; 975 clock-names = "clkp1", "clkp2", "can_clk"; 976 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 977 assigned-clock-rates = <40000000>; 978 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 979 resets = <&cpg 916>; 980 status = "disabled"; 981 }; 982 983 can1: can@e6c38000 { 984 compatible = "renesas,can-r8a774c0", 985 "renesas,rcar-gen3-can"; 986 reg = <0 0xe6c38000 0 0x1000>; 987 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&cpg CPG_MOD 915>, 989 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 990 <&can_clk>; 991 clock-names = "clkp1", "clkp2", "can_clk"; 992 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 993 assigned-clock-rates = <40000000>; 994 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 995 resets = <&cpg 915>; 996 status = "disabled"; 997 }; 998 999 canfd: can@e66c0000 { 1000 compatible = "renesas,r8a774c0-canfd", 1001 "renesas,rcar-gen3-canfd"; 1002 reg = <0 0xe66c0000 0 0x8000>; 1003 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cpg CPG_MOD 914>, 1006 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1007 <&can_clk>; 1008 clock-names = "fck", "canfd", "can_clk"; 1009 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1010 assigned-clock-rates = <40000000>; 1011 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1012 resets = <&cpg 914>; 1013 status = "disabled"; 1014 1015 channel0 { 1016 status = "disabled"; 1017 }; 1018 1019 channel1 { 1020 status = "disabled"; 1021 }; 1022 }; 1023 1024 pwm0: pwm@e6e30000 { 1025 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1026 reg = <0 0xe6e30000 0 0x8>; 1027 clocks = <&cpg CPG_MOD 523>; 1028 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1029 resets = <&cpg 523>; 1030 #pwm-cells = <2>; 1031 status = "disabled"; 1032 }; 1033 1034 pwm1: pwm@e6e31000 { 1035 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1036 reg = <0 0xe6e31000 0 0x8>; 1037 clocks = <&cpg CPG_MOD 523>; 1038 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1039 resets = <&cpg 523>; 1040 #pwm-cells = <2>; 1041 status = "disabled"; 1042 }; 1043 1044 pwm2: pwm@e6e32000 { 1045 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1046 reg = <0 0xe6e32000 0 0x8>; 1047 clocks = <&cpg CPG_MOD 523>; 1048 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1049 resets = <&cpg 523>; 1050 #pwm-cells = <2>; 1051 status = "disabled"; 1052 }; 1053 1054 pwm3: pwm@e6e33000 { 1055 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1056 reg = <0 0xe6e33000 0 0x8>; 1057 clocks = <&cpg CPG_MOD 523>; 1058 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1059 resets = <&cpg 523>; 1060 #pwm-cells = <2>; 1061 status = "disabled"; 1062 }; 1063 1064 pwm4: pwm@e6e34000 { 1065 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1066 reg = <0 0xe6e34000 0 0x8>; 1067 clocks = <&cpg CPG_MOD 523>; 1068 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1069 resets = <&cpg 523>; 1070 #pwm-cells = <2>; 1071 status = "disabled"; 1072 }; 1073 1074 pwm5: pwm@e6e35000 { 1075 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1076 reg = <0 0xe6e35000 0 0x8>; 1077 clocks = <&cpg CPG_MOD 523>; 1078 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1079 resets = <&cpg 523>; 1080 #pwm-cells = <2>; 1081 status = "disabled"; 1082 }; 1083 1084 pwm6: pwm@e6e36000 { 1085 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1086 reg = <0 0xe6e36000 0 0x8>; 1087 clocks = <&cpg CPG_MOD 523>; 1088 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1089 resets = <&cpg 523>; 1090 #pwm-cells = <2>; 1091 status = "disabled"; 1092 }; 1093 1094 scif0: serial@e6e60000 { 1095 compatible = "renesas,scif-r8a774c0", 1096 "renesas,rcar-gen3-scif", "renesas,scif"; 1097 reg = <0 0xe6e60000 0 64>; 1098 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cpg CPG_MOD 207>, 1100 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1101 <&scif_clk>; 1102 clock-names = "fck", "brg_int", "scif_clk"; 1103 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1104 <&dmac2 0x51>, <&dmac2 0x50>; 1105 dma-names = "tx", "rx", "tx", "rx"; 1106 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1107 resets = <&cpg 207>; 1108 status = "disabled"; 1109 }; 1110 1111 scif1: serial@e6e68000 { 1112 compatible = "renesas,scif-r8a774c0", 1113 "renesas,rcar-gen3-scif", "renesas,scif"; 1114 reg = <0 0xe6e68000 0 64>; 1115 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cpg CPG_MOD 206>, 1117 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1118 <&scif_clk>; 1119 clock-names = "fck", "brg_int", "scif_clk"; 1120 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1121 <&dmac2 0x53>, <&dmac2 0x52>; 1122 dma-names = "tx", "rx", "tx", "rx"; 1123 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1124 resets = <&cpg 206>; 1125 status = "disabled"; 1126 }; 1127 1128 scif2: serial@e6e88000 { 1129 compatible = "renesas,scif-r8a774c0", 1130 "renesas,rcar-gen3-scif", "renesas,scif"; 1131 reg = <0 0xe6e88000 0 64>; 1132 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&cpg CPG_MOD 310>, 1134 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1135 <&scif_clk>; 1136 clock-names = "fck", "brg_int", "scif_clk"; 1137 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1138 <&dmac2 0x13>, <&dmac2 0x12>; 1139 dma-names = "tx", "rx", "tx", "rx"; 1140 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1141 resets = <&cpg 310>; 1142 status = "disabled"; 1143 }; 1144 1145 scif3: serial@e6c50000 { 1146 compatible = "renesas,scif-r8a774c0", 1147 "renesas,rcar-gen3-scif", "renesas,scif"; 1148 reg = <0 0xe6c50000 0 64>; 1149 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&cpg CPG_MOD 204>, 1151 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1152 <&scif_clk>; 1153 clock-names = "fck", "brg_int", "scif_clk"; 1154 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1155 dma-names = "tx", "rx"; 1156 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1157 resets = <&cpg 204>; 1158 status = "disabled"; 1159 }; 1160 1161 scif4: serial@e6c40000 { 1162 compatible = "renesas,scif-r8a774c0", 1163 "renesas,rcar-gen3-scif", "renesas,scif"; 1164 reg = <0 0xe6c40000 0 64>; 1165 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&cpg CPG_MOD 203>, 1167 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1168 <&scif_clk>; 1169 clock-names = "fck", "brg_int", "scif_clk"; 1170 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1171 dma-names = "tx", "rx"; 1172 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1173 resets = <&cpg 203>; 1174 status = "disabled"; 1175 }; 1176 1177 scif5: serial@e6f30000 { 1178 compatible = "renesas,scif-r8a774c0", 1179 "renesas,rcar-gen3-scif", "renesas,scif"; 1180 reg = <0 0xe6f30000 0 64>; 1181 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&cpg CPG_MOD 202>, 1183 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1184 <&scif_clk>; 1185 clock-names = "fck", "brg_int", "scif_clk"; 1186 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1187 dma-names = "tx", "rx"; 1188 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1189 resets = <&cpg 202>; 1190 status = "disabled"; 1191 }; 1192 1193 msiof0: spi@e6e90000 { 1194 compatible = "renesas,msiof-r8a774c0", 1195 "renesas,rcar-gen3-msiof"; 1196 reg = <0 0xe6e90000 0 0x0064>; 1197 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cpg CPG_MOD 211>; 1199 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1200 <&dmac2 0x41>, <&dmac2 0x40>; 1201 dma-names = "tx", "rx", "tx", "rx"; 1202 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1203 resets = <&cpg 211>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 msiof1: spi@e6ea0000 { 1210 compatible = "renesas,msiof-r8a774c0", 1211 "renesas,rcar-gen3-msiof"; 1212 reg = <0 0xe6ea0000 0 0x0064>; 1213 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1214 clocks = <&cpg CPG_MOD 210>; 1215 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1216 <&dmac2 0x43>, <&dmac2 0x42>; 1217 dma-names = "tx", "rx", "tx", "rx"; 1218 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1219 resets = <&cpg 210>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 msiof2: spi@e6c00000 { 1226 compatible = "renesas,msiof-r8a774c0", 1227 "renesas,rcar-gen3-msiof"; 1228 reg = <0 0xe6c00000 0 0x0064>; 1229 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&cpg CPG_MOD 209>; 1231 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1232 dma-names = "tx", "rx"; 1233 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1234 resets = <&cpg 209>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 msiof3: spi@e6c10000 { 1241 compatible = "renesas,msiof-r8a774c0", 1242 "renesas,rcar-gen3-msiof"; 1243 reg = <0 0xe6c10000 0 0x0064>; 1244 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&cpg CPG_MOD 208>; 1246 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1247 dma-names = "tx", "rx"; 1248 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1249 resets = <&cpg 208>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 vin4: video@e6ef4000 { 1256 compatible = "renesas,vin-r8a774c0"; 1257 reg = <0 0xe6ef4000 0 0x1000>; 1258 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&cpg CPG_MOD 807>; 1260 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1261 resets = <&cpg 807>; 1262 renesas,id = <4>; 1263 status = "disabled"; 1264 1265 ports { 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 1269 port@1 { 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 1273 reg = <1>; 1274 1275 vin4csi40: endpoint@2 { 1276 reg = <2>; 1277 remote-endpoint= <&csi40vin4>; 1278 }; 1279 }; 1280 }; 1281 }; 1282 1283 vin5: video@e6ef5000 { 1284 compatible = "renesas,vin-r8a774c0"; 1285 reg = <0 0xe6ef5000 0 0x1000>; 1286 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&cpg CPG_MOD 806>; 1288 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1289 resets = <&cpg 806>; 1290 renesas,id = <5>; 1291 status = "disabled"; 1292 1293 ports { 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 1297 port@1 { 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 1301 reg = <1>; 1302 1303 vin5csi40: endpoint@2 { 1304 reg = <2>; 1305 remote-endpoint= <&csi40vin5>; 1306 }; 1307 }; 1308 }; 1309 }; 1310 1311 rcar_sound: sound@ec500000 { 1312 /* 1313 * #sound-dai-cells is required 1314 * 1315 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1316 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1317 */ 1318 /* 1319 * #clock-cells is required for audio_clkout0/1/2/3 1320 * 1321 * clkout : #clock-cells = <0>; <&rcar_sound>; 1322 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1323 */ 1324 compatible = "renesas,rcar_sound-r8a774c0", 1325 "renesas,rcar_sound-gen3"; 1326 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1327 <0 0xec5a0000 0 0x100>, /* ADG */ 1328 <0 0xec540000 0 0x1000>, /* SSIU */ 1329 <0 0xec541000 0 0x280>, /* SSI */ 1330 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1331 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1332 1333 clocks = <&cpg CPG_MOD 1005>, 1334 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1335 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1336 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1337 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1338 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1339 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1340 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1341 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1342 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1343 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1344 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1345 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1346 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1347 <&audio_clk_a>, <&audio_clk_b>, 1348 <&audio_clk_c>, 1349 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1350 clock-names = "ssi-all", 1351 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1352 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1353 "ssi.1", "ssi.0", 1354 "src.9", "src.8", "src.7", "src.6", 1355 "src.5", "src.4", "src.3", "src.2", 1356 "src.1", "src.0", 1357 "mix.1", "mix.0", 1358 "ctu.1", "ctu.0", 1359 "dvc.0", "dvc.1", 1360 "clk_a", "clk_b", "clk_c", "clk_i"; 1361 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1362 resets = <&cpg 1005>, 1363 <&cpg 1006>, <&cpg 1007>, 1364 <&cpg 1008>, <&cpg 1009>, 1365 <&cpg 1010>, <&cpg 1011>, 1366 <&cpg 1012>, <&cpg 1013>, 1367 <&cpg 1014>, <&cpg 1015>; 1368 reset-names = "ssi-all", 1369 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1370 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1371 "ssi.1", "ssi.0"; 1372 status = "disabled"; 1373 1374 rcar_sound,ctu { 1375 ctu00: ctu-0 { }; 1376 ctu01: ctu-1 { }; 1377 ctu02: ctu-2 { }; 1378 ctu03: ctu-3 { }; 1379 ctu10: ctu-4 { }; 1380 ctu11: ctu-5 { }; 1381 ctu12: ctu-6 { }; 1382 ctu13: ctu-7 { }; 1383 }; 1384 1385 rcar_sound,dvc { 1386 dvc0: dvc-0 { 1387 dmas = <&audma0 0xbc>; 1388 dma-names = "tx"; 1389 }; 1390 dvc1: dvc-1 { 1391 dmas = <&audma0 0xbe>; 1392 dma-names = "tx"; 1393 }; 1394 }; 1395 1396 rcar_sound,mix { 1397 mix0: mix-0 { }; 1398 mix1: mix-1 { }; 1399 }; 1400 1401 rcar_sound,src { 1402 src0: src-0 { 1403 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1404 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1405 dma-names = "rx", "tx"; 1406 }; 1407 src1: src-1 { 1408 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1409 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1410 dma-names = "rx", "tx"; 1411 }; 1412 src2: src-2 { 1413 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1415 dma-names = "rx", "tx"; 1416 }; 1417 src3: src-3 { 1418 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1419 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1420 dma-names = "rx", "tx"; 1421 }; 1422 src4: src-4 { 1423 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1424 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1425 dma-names = "rx", "tx"; 1426 }; 1427 src5: src-5 { 1428 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1429 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1430 dma-names = "rx", "tx"; 1431 }; 1432 src6: src-6 { 1433 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1434 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1435 dma-names = "rx", "tx"; 1436 }; 1437 src7: src-7 { 1438 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1439 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1440 dma-names = "rx", "tx"; 1441 }; 1442 src8: src-8 { 1443 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1444 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1445 dma-names = "rx", "tx"; 1446 }; 1447 src9: src-9 { 1448 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1449 dmas = <&audma0 0x97>, <&audma0 0xba>; 1450 dma-names = "rx", "tx"; 1451 }; 1452 }; 1453 1454 rcar_sound,ssi { 1455 ssi0: ssi-0 { 1456 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1457 dmas = <&audma0 0x01>, <&audma0 0x02>, 1458 <&audma0 0x15>, <&audma0 0x16>; 1459 dma-names = "rx", "tx", "rxu", "txu"; 1460 }; 1461 ssi1: ssi-1 { 1462 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1463 dmas = <&audma0 0x03>, <&audma0 0x04>, 1464 <&audma0 0x49>, <&audma0 0x4a>; 1465 dma-names = "rx", "tx", "rxu", "txu"; 1466 }; 1467 ssi2: ssi-2 { 1468 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1469 dmas = <&audma0 0x05>, <&audma0 0x06>, 1470 <&audma0 0x63>, <&audma0 0x64>; 1471 dma-names = "rx", "tx", "rxu", "txu"; 1472 }; 1473 ssi3: ssi-3 { 1474 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1475 dmas = <&audma0 0x07>, <&audma0 0x08>, 1476 <&audma0 0x6f>, <&audma0 0x70>; 1477 dma-names = "rx", "tx", "rxu", "txu"; 1478 }; 1479 ssi4: ssi-4 { 1480 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1482 <&audma0 0x71>, <&audma0 0x72>; 1483 dma-names = "rx", "tx", "rxu", "txu"; 1484 }; 1485 ssi5: ssi-5 { 1486 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1487 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1488 <&audma0 0x73>, <&audma0 0x74>; 1489 dma-names = "rx", "tx", "rxu", "txu"; 1490 }; 1491 ssi6: ssi-6 { 1492 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1493 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1494 <&audma0 0x75>, <&audma0 0x76>; 1495 dma-names = "rx", "tx", "rxu", "txu"; 1496 }; 1497 ssi7: ssi-7 { 1498 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1499 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1500 <&audma0 0x79>, <&audma0 0x7a>; 1501 dma-names = "rx", "tx", "rxu", "txu"; 1502 }; 1503 ssi8: ssi-8 { 1504 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1505 dmas = <&audma0 0x11>, <&audma0 0x12>, 1506 <&audma0 0x7b>, <&audma0 0x7c>; 1507 dma-names = "rx", "tx", "rxu", "txu"; 1508 }; 1509 ssi9: ssi-9 { 1510 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1511 dmas = <&audma0 0x13>, <&audma0 0x14>, 1512 <&audma0 0x7d>, <&audma0 0x7e>; 1513 dma-names = "rx", "tx", "rxu", "txu"; 1514 }; 1515 }; 1516 }; 1517 1518 audma0: dma-controller@ec700000 { 1519 compatible = "renesas,dmac-r8a774c0", 1520 "renesas,rcar-dmac"; 1521 reg = <0 0xec700000 0 0x10000>; 1522 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1523 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1524 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1525 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1526 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1527 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1528 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1529 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1530 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1531 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1532 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1533 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1534 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1535 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1536 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1537 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1538 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1539 interrupt-names = "error", 1540 "ch0", "ch1", "ch2", "ch3", 1541 "ch4", "ch5", "ch6", "ch7", 1542 "ch8", "ch9", "ch10", "ch11", 1543 "ch12", "ch13", "ch14", "ch15"; 1544 clocks = <&cpg CPG_MOD 502>; 1545 clock-names = "fck"; 1546 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1547 resets = <&cpg 502>; 1548 #dma-cells = <1>; 1549 dma-channels = <16>; 1550 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1551 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1552 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1553 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1554 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1555 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1556 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1557 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1558 }; 1559 1560 xhci0: usb@ee000000 { 1561 compatible = "renesas,xhci-r8a774c0", 1562 "renesas,rcar-gen3-xhci"; 1563 reg = <0 0xee000000 0 0xc00>; 1564 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cpg CPG_MOD 328>; 1566 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1567 resets = <&cpg 328>; 1568 status = "disabled"; 1569 }; 1570 1571 usb3_peri0: usb@ee020000 { 1572 compatible = "renesas,r8a774c0-usb3-peri", 1573 "renesas,rcar-gen3-usb3-peri"; 1574 reg = <0 0xee020000 0 0x400>; 1575 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1576 clocks = <&cpg CPG_MOD 328>; 1577 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1578 resets = <&cpg 328>; 1579 status = "disabled"; 1580 }; 1581 1582 ohci0: usb@ee080000 { 1583 compatible = "generic-ohci"; 1584 reg = <0 0xee080000 0 0x100>; 1585 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1586 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1587 phys = <&usb2_phy0 1>; 1588 phy-names = "usb"; 1589 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1590 resets = <&cpg 703>, <&cpg 704>; 1591 status = "disabled"; 1592 }; 1593 1594 ehci0: usb@ee080100 { 1595 compatible = "generic-ehci"; 1596 reg = <0 0xee080100 0 0x100>; 1597 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1599 phys = <&usb2_phy0 2>; 1600 phy-names = "usb"; 1601 companion = <&ohci0>; 1602 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1603 resets = <&cpg 703>, <&cpg 704>; 1604 status = "disabled"; 1605 }; 1606 1607 usb2_phy0: usb-phy@ee080200 { 1608 compatible = "renesas,usb2-phy-r8a774c0", 1609 "renesas,rcar-gen3-usb2-phy"; 1610 reg = <0 0xee080200 0 0x700>; 1611 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1612 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1613 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1614 resets = <&cpg 703>, <&cpg 704>; 1615 #phy-cells = <1>; 1616 status = "disabled"; 1617 }; 1618 1619 sdhi0: sd@ee100000 { 1620 compatible = "renesas,sdhi-r8a774c0", 1621 "renesas,rcar-gen3-sdhi"; 1622 reg = <0 0xee100000 0 0x2000>; 1623 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1624 clocks = <&cpg CPG_MOD 314>; 1625 max-frequency = <200000000>; 1626 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1627 resets = <&cpg 314>; 1628 status = "disabled"; 1629 }; 1630 1631 sdhi1: sd@ee120000 { 1632 compatible = "renesas,sdhi-r8a774c0", 1633 "renesas,rcar-gen3-sdhi"; 1634 reg = <0 0xee120000 0 0x2000>; 1635 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&cpg CPG_MOD 313>; 1637 max-frequency = <200000000>; 1638 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1639 resets = <&cpg 313>; 1640 status = "disabled"; 1641 }; 1642 1643 sdhi3: sd@ee160000 { 1644 compatible = "renesas,sdhi-r8a774c0", 1645 "renesas,rcar-gen3-sdhi"; 1646 reg = <0 0xee160000 0 0x2000>; 1647 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&cpg CPG_MOD 311>; 1649 max-frequency = <200000000>; 1650 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1651 resets = <&cpg 311>; 1652 status = "disabled"; 1653 }; 1654 1655 gic: interrupt-controller@f1010000 { 1656 compatible = "arm,gic-400"; 1657 #interrupt-cells = <3>; 1658 #address-cells = <0>; 1659 interrupt-controller; 1660 reg = <0x0 0xf1010000 0 0x1000>, 1661 <0x0 0xf1020000 0 0x20000>, 1662 <0x0 0xf1040000 0 0x20000>, 1663 <0x0 0xf1060000 0 0x20000>; 1664 interrupts = <GIC_PPI 9 1665 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1666 clocks = <&cpg CPG_MOD 408>; 1667 clock-names = "clk"; 1668 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1669 resets = <&cpg 408>; 1670 }; 1671 1672 pciec0: pcie@fe000000 { 1673 compatible = "renesas,pcie-r8a774c0", 1674 "renesas,pcie-rcar-gen3"; 1675 reg = <0 0xfe000000 0 0x80000>; 1676 #address-cells = <3>; 1677 #size-cells = <2>; 1678 bus-range = <0x00 0xff>; 1679 device_type = "pci"; 1680 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1681 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1682 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1683 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1684 /* Map all possible DDR as inbound ranges */ 1685 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1686 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1689 #interrupt-cells = <1>; 1690 interrupt-map-mask = <0 0 0 0>; 1691 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1692 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1693 clock-names = "pcie", "pcie_bus"; 1694 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1695 resets = <&cpg 319>; 1696 status = "disabled"; 1697 }; 1698 1699 vspb0: vsp@fe960000 { 1700 compatible = "renesas,vsp2"; 1701 reg = <0 0xfe960000 0 0x8000>; 1702 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1703 clocks = <&cpg CPG_MOD 626>; 1704 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1705 resets = <&cpg 626>; 1706 renesas,fcp = <&fcpvb0>; 1707 }; 1708 1709 vspd0: vsp@fea20000 { 1710 compatible = "renesas,vsp2"; 1711 reg = <0 0xfea20000 0 0x7000>; 1712 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1713 clocks = <&cpg CPG_MOD 623>; 1714 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1715 resets = <&cpg 623>; 1716 renesas,fcp = <&fcpvd0>; 1717 }; 1718 1719 vspd1: vsp@fea28000 { 1720 compatible = "renesas,vsp2"; 1721 reg = <0 0xfea28000 0 0x7000>; 1722 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1723 clocks = <&cpg CPG_MOD 622>; 1724 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1725 resets = <&cpg 622>; 1726 renesas,fcp = <&fcpvd1>; 1727 }; 1728 1729 vspi0: vsp@fe9a0000 { 1730 compatible = "renesas,vsp2"; 1731 reg = <0 0xfe9a0000 0 0x8000>; 1732 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&cpg CPG_MOD 631>; 1734 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1735 resets = <&cpg 631>; 1736 renesas,fcp = <&fcpvi0>; 1737 }; 1738 1739 fcpvb0: fcp@fe96f000 { 1740 compatible = "renesas,fcpv"; 1741 reg = <0 0xfe96f000 0 0x200>; 1742 clocks = <&cpg CPG_MOD 607>; 1743 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1744 resets = <&cpg 607>; 1745 iommus = <&ipmmu_vp0 5>; 1746 }; 1747 1748 fcpvd0: fcp@fea27000 { 1749 compatible = "renesas,fcpv"; 1750 reg = <0 0xfea27000 0 0x200>; 1751 clocks = <&cpg CPG_MOD 603>; 1752 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1753 resets = <&cpg 603>; 1754 iommus = <&ipmmu_vi0 8>; 1755 }; 1756 1757 fcpvd1: fcp@fea2f000 { 1758 compatible = "renesas,fcpv"; 1759 reg = <0 0xfea2f000 0 0x200>; 1760 clocks = <&cpg CPG_MOD 602>; 1761 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1762 resets = <&cpg 602>; 1763 iommus = <&ipmmu_vi0 9>; 1764 }; 1765 1766 fcpvi0: fcp@fe9af000 { 1767 compatible = "renesas,fcpv"; 1768 reg = <0 0xfe9af000 0 0x200>; 1769 clocks = <&cpg CPG_MOD 611>; 1770 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1771 resets = <&cpg 611>; 1772 iommus = <&ipmmu_vp0 8>; 1773 }; 1774 1775 csi40: csi2@feaa0000 { 1776 compatible = "renesas,r8a774c0-csi2"; 1777 reg = <0 0xfeaa0000 0 0x10000>; 1778 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1779 clocks = <&cpg CPG_MOD 716>; 1780 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1781 resets = <&cpg 716>; 1782 status = "disabled"; 1783 1784 ports { 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 1788 port@1 { 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 1792 reg = <1>; 1793 1794 csi40vin4: endpoint@0 { 1795 reg = <0>; 1796 remote-endpoint = <&vin4csi40>; 1797 }; 1798 csi40vin5: endpoint@1 { 1799 reg = <1>; 1800 remote-endpoint = <&vin5csi40>; 1801 }; 1802 }; 1803 }; 1804 }; 1805 1806 du: display@feb00000 { 1807 compatible = "renesas,du-r8a774c0"; 1808 reg = <0 0xfeb00000 0 0x40000>; 1809 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1811 clocks = <&cpg CPG_MOD 724>, 1812 <&cpg CPG_MOD 723>; 1813 clock-names = "du.0", "du.1"; 1814 vsps = <&vspd0 0 &vspd1 0>; 1815 status = "disabled"; 1816 1817 ports { 1818 #address-cells = <1>; 1819 #size-cells = <0>; 1820 1821 port@0 { 1822 reg = <0>; 1823 du_out_rgb: endpoint { 1824 }; 1825 }; 1826 1827 port@1 { 1828 reg = <1>; 1829 du_out_lvds0: endpoint { 1830 remote-endpoint = <&lvds0_in>; 1831 }; 1832 }; 1833 1834 port@2 { 1835 reg = <2>; 1836 du_out_lvds1: endpoint { 1837 remote-endpoint = <&lvds1_in>; 1838 }; 1839 }; 1840 }; 1841 }; 1842 1843 lvds0: lvds-encoder@feb90000 { 1844 compatible = "renesas,r8a774c0-lvds"; 1845 reg = <0 0xfeb90000 0 0x20>; 1846 clocks = <&cpg CPG_MOD 727>; 1847 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1848 resets = <&cpg 727>; 1849 status = "disabled"; 1850 1851 renesas,companion = <&lvds1>; 1852 1853 ports { 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 1857 port@0 { 1858 reg = <0>; 1859 lvds0_in: endpoint { 1860 remote-endpoint = <&du_out_lvds0>; 1861 }; 1862 }; 1863 1864 port@1 { 1865 reg = <1>; 1866 lvds0_out: endpoint { 1867 }; 1868 }; 1869 }; 1870 }; 1871 1872 lvds1: lvds-encoder@feb90100 { 1873 compatible = "renesas,r8a774c0-lvds"; 1874 reg = <0 0xfeb90100 0 0x20>; 1875 clocks = <&cpg CPG_MOD 727>; 1876 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1877 resets = <&cpg 726>; 1878 status = "disabled"; 1879 1880 ports { 1881 #address-cells = <1>; 1882 #size-cells = <0>; 1883 1884 port@0 { 1885 reg = <0>; 1886 lvds1_in: endpoint { 1887 remote-endpoint = <&du_out_lvds1>; 1888 }; 1889 }; 1890 1891 port@1 { 1892 reg = <1>; 1893 lvds1_out: endpoint { 1894 }; 1895 }; 1896 }; 1897 }; 1898 1899 prr: chipid@fff00044 { 1900 compatible = "renesas,prr"; 1901 reg = <0 0xfff00044 0 4>; 1902 }; 1903 }; 1904 1905 thermal-zones { 1906 cpu-thermal { 1907 polling-delay-passive = <250>; 1908 polling-delay = <1000>; 1909 thermal-sensors = <&thermal>; 1910 1911 cooling-maps { 1912 }; 1913 1914 trips { 1915 cpu-crit { 1916 temperature = <120000>; 1917 hysteresis = <2000>; 1918 type = "critical"; 1919 }; 1920 }; 1921 }; 1922 }; 1923 1924 timer { 1925 compatible = "arm,armv8-timer"; 1926 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1927 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1928 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1929 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1930 }; 1931 1932 /* External USB clocks - can be overridden by the board */ 1933 usb3s0_clk: usb3s0 { 1934 compatible = "fixed-clock"; 1935 #clock-cells = <0>; 1936 clock-frequency = <0>; 1937 }; 1938 1939 usb_extal_clk: usb_extal { 1940 compatible = "fixed-clock"; 1941 #clock-cells = <0>; 1942 clock-frequency = <0>; 1943 }; 1944}; 1945