1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp_table10 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 opp-800000000 { 51 opp-hz = /bits/ 64 <800000000>; 52 opp-microvolt = <820000>; 53 clock-latency-ns = <300000>; 54 }; 55 opp-1000000000 { 56 opp-hz = /bits/ 64 <1000000000>; 57 opp-microvolt = <820000>; 58 clock-latency-ns = <300000>; 59 }; 60 opp-1200000000 { 61 opp-hz = /bits/ 64 <1200000000>; 62 opp-microvolt = <820000>; 63 clock-latency-ns = <300000>; 64 opp-suspend; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 a53_0: cpu@0 { 73 compatible = "arm,cortex-a53"; 74 reg = <0>; 75 device_type = "cpu"; 76 #cooling-cells = <2>; 77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 78 next-level-cache = <&L2_CA53>; 79 enable-method = "psci"; 80 dynamic-power-coefficient = <277>; 81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 82 operating-points-v2 = <&cluster1_opp>; 83 }; 84 85 a53_1: cpu@1 { 86 compatible = "arm,cortex-a53"; 87 reg = <1>; 88 device_type = "cpu"; 89 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 90 next-level-cache = <&L2_CA53>; 91 enable-method = "psci"; 92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 93 operating-points-v2 = <&cluster1_opp>; 94 }; 95 96 L2_CA53: cache-controller-0 { 97 compatible = "cache"; 98 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 99 cache-unified; 100 cache-level = <2>; 101 }; 102 }; 103 104 extal_clk: extal { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 /* This value must be overridden by the board */ 108 clock-frequency = <0>; 109 }; 110 111 /* External PCIe clock - can be overridden by the board */ 112 pcie_bus_clk: pcie_bus { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 }; 117 118 pmu_a53 { 119 compatible = "arm,cortex-a53-pmu"; 120 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 121 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 122 interrupt-affinity = <&a53_0>, <&a53_1>; 123 }; 124 125 psci { 126 compatible = "arm,psci-1.0", "arm,psci-0.2"; 127 method = "smc"; 128 }; 129 130 /* External SCIF clock - to be overridden by boards that provide it */ 131 scif_clk: scif { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <0>; 135 }; 136 137 soc: soc { 138 compatible = "simple-bus"; 139 interrupt-parent = <&gic>; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 rwdt: watchdog@e6020000 { 145 compatible = "renesas,r8a774c0-wdt", 146 "renesas,rcar-gen3-wdt"; 147 reg = <0 0xe6020000 0 0x0c>; 148 clocks = <&cpg CPG_MOD 402>; 149 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 150 resets = <&cpg 402>; 151 status = "disabled"; 152 }; 153 154 gpio0: gpio@e6050000 { 155 compatible = "renesas,gpio-r8a774c0", 156 "renesas,rcar-gen3-gpio"; 157 reg = <0 0xe6050000 0 0x50>; 158 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 159 #gpio-cells = <2>; 160 gpio-controller; 161 gpio-ranges = <&pfc 0 0 18>; 162 #interrupt-cells = <2>; 163 interrupt-controller; 164 clocks = <&cpg CPG_MOD 912>; 165 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 166 resets = <&cpg 912>; 167 }; 168 169 gpio1: gpio@e6051000 { 170 compatible = "renesas,gpio-r8a774c0", 171 "renesas,rcar-gen3-gpio"; 172 reg = <0 0xe6051000 0 0x50>; 173 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 174 #gpio-cells = <2>; 175 gpio-controller; 176 gpio-ranges = <&pfc 0 32 23>; 177 #interrupt-cells = <2>; 178 interrupt-controller; 179 clocks = <&cpg CPG_MOD 911>; 180 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 181 resets = <&cpg 911>; 182 }; 183 184 gpio2: gpio@e6052000 { 185 compatible = "renesas,gpio-r8a774c0", 186 "renesas,rcar-gen3-gpio"; 187 reg = <0 0xe6052000 0 0x50>; 188 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 189 #gpio-cells = <2>; 190 gpio-controller; 191 gpio-ranges = <&pfc 0 64 26>; 192 #interrupt-cells = <2>; 193 interrupt-controller; 194 clocks = <&cpg CPG_MOD 910>; 195 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 196 resets = <&cpg 910>; 197 }; 198 199 gpio3: gpio@e6053000 { 200 compatible = "renesas,gpio-r8a774c0", 201 "renesas,rcar-gen3-gpio"; 202 reg = <0 0xe6053000 0 0x50>; 203 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 204 #gpio-cells = <2>; 205 gpio-controller; 206 gpio-ranges = <&pfc 0 96 16>; 207 #interrupt-cells = <2>; 208 interrupt-controller; 209 clocks = <&cpg CPG_MOD 909>; 210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 211 resets = <&cpg 909>; 212 }; 213 214 gpio4: gpio@e6054000 { 215 compatible = "renesas,gpio-r8a774c0", 216 "renesas,rcar-gen3-gpio"; 217 reg = <0 0xe6054000 0 0x50>; 218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 219 #gpio-cells = <2>; 220 gpio-controller; 221 gpio-ranges = <&pfc 0 128 11>; 222 #interrupt-cells = <2>; 223 interrupt-controller; 224 clocks = <&cpg CPG_MOD 908>; 225 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 226 resets = <&cpg 908>; 227 }; 228 229 gpio5: gpio@e6055000 { 230 compatible = "renesas,gpio-r8a774c0", 231 "renesas,rcar-gen3-gpio"; 232 reg = <0 0xe6055000 0 0x50>; 233 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 234 #gpio-cells = <2>; 235 gpio-controller; 236 gpio-ranges = <&pfc 0 160 20>; 237 #interrupt-cells = <2>; 238 interrupt-controller; 239 clocks = <&cpg CPG_MOD 907>; 240 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 241 resets = <&cpg 907>; 242 }; 243 244 gpio6: gpio@e6055400 { 245 compatible = "renesas,gpio-r8a774c0", 246 "renesas,rcar-gen3-gpio"; 247 reg = <0 0xe6055400 0 0x50>; 248 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 249 #gpio-cells = <2>; 250 gpio-controller; 251 gpio-ranges = <&pfc 0 192 18>; 252 #interrupt-cells = <2>; 253 interrupt-controller; 254 clocks = <&cpg CPG_MOD 906>; 255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 256 resets = <&cpg 906>; 257 }; 258 259 pfc: pin-controller@e6060000 { 260 compatible = "renesas,pfc-r8a774c0"; 261 reg = <0 0xe6060000 0 0x508>; 262 }; 263 264 cmt0: timer@e60f0000 { 265 compatible = "renesas,r8a774c0-cmt0", 266 "renesas,rcar-gen3-cmt0"; 267 reg = <0 0xe60f0000 0 0x1004>; 268 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cpg CPG_MOD 303>; 271 clock-names = "fck"; 272 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 273 resets = <&cpg 303>; 274 status = "disabled"; 275 }; 276 277 cmt1: timer@e6130000 { 278 compatible = "renesas,r8a774c0-cmt1", 279 "renesas,rcar-gen3-cmt1"; 280 reg = <0 0xe6130000 0 0x1004>; 281 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&cpg CPG_MOD 302>; 290 clock-names = "fck"; 291 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 292 resets = <&cpg 302>; 293 status = "disabled"; 294 }; 295 296 cmt2: timer@e6140000 { 297 compatible = "renesas,r8a774c0-cmt1", 298 "renesas,rcar-gen3-cmt1"; 299 reg = <0 0xe6140000 0 0x1004>; 300 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cpg CPG_MOD 301>; 309 clock-names = "fck"; 310 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 311 resets = <&cpg 301>; 312 status = "disabled"; 313 }; 314 315 cmt3: timer@e6148000 { 316 compatible = "renesas,r8a774c0-cmt1", 317 "renesas,rcar-gen3-cmt1"; 318 reg = <0 0xe6148000 0 0x1004>; 319 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 300>; 328 clock-names = "fck"; 329 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 330 resets = <&cpg 300>; 331 status = "disabled"; 332 }; 333 334 cpg: clock-controller@e6150000 { 335 compatible = "renesas,r8a774c0-cpg-mssr"; 336 reg = <0 0xe6150000 0 0x1000>; 337 clocks = <&extal_clk>; 338 clock-names = "extal"; 339 #clock-cells = <2>; 340 #power-domain-cells = <0>; 341 #reset-cells = <1>; 342 }; 343 344 rst: reset-controller@e6160000 { 345 compatible = "renesas,r8a774c0-rst"; 346 reg = <0 0xe6160000 0 0x0200>; 347 }; 348 349 sysc: system-controller@e6180000 { 350 compatible = "renesas,r8a774c0-sysc"; 351 reg = <0 0xe6180000 0 0x0400>; 352 #power-domain-cells = <1>; 353 }; 354 355 thermal: thermal@e6190000 { 356 compatible = "renesas,thermal-r8a774c0"; 357 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 358 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&cpg CPG_MOD 522>; 362 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 363 resets = <&cpg 522>; 364 #thermal-sensor-cells = <0>; 365 }; 366 367 intc_ex: interrupt-controller@e61c0000 { 368 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 reg = <0 0xe61c0000 0 0x200>; 372 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cpg CPG_MOD 407>; 379 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 380 resets = <&cpg 407>; 381 }; 382 383 tmu0: timer@e61e0000 { 384 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 385 reg = <0 0xe61e0000 0 0x30>; 386 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&cpg CPG_MOD 125>; 390 clock-names = "fck"; 391 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 392 resets = <&cpg 125>; 393 status = "disabled"; 394 }; 395 396 tmu1: timer@e6fc0000 { 397 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 398 reg = <0 0xe6fc0000 0 0x30>; 399 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cpg CPG_MOD 124>; 403 clock-names = "fck"; 404 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 405 resets = <&cpg 124>; 406 status = "disabled"; 407 }; 408 409 tmu2: timer@e6fd0000 { 410 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 411 reg = <0 0xe6fd0000 0 0x30>; 412 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&cpg CPG_MOD 123>; 416 clock-names = "fck"; 417 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 418 resets = <&cpg 123>; 419 status = "disabled"; 420 }; 421 422 tmu3: timer@e6fe0000 { 423 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 424 reg = <0 0xe6fe0000 0 0x30>; 425 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cpg CPG_MOD 122>; 429 clock-names = "fck"; 430 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 431 resets = <&cpg 122>; 432 status = "disabled"; 433 }; 434 435 tmu4: timer@ffc00000 { 436 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 437 reg = <0 0xffc00000 0 0x30>; 438 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cpg CPG_MOD 121>; 442 clock-names = "fck"; 443 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 444 resets = <&cpg 121>; 445 status = "disabled"; 446 }; 447 448 i2c0: i2c@e6500000 { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 compatible = "renesas,i2c-r8a774c0", 452 "renesas,rcar-gen3-i2c"; 453 reg = <0 0xe6500000 0 0x40>; 454 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cpg CPG_MOD 931>; 456 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 457 resets = <&cpg 931>; 458 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 459 <&dmac2 0x91>, <&dmac2 0x90>; 460 dma-names = "tx", "rx", "tx", "rx"; 461 i2c-scl-internal-delay-ns = <110>; 462 status = "disabled"; 463 }; 464 465 i2c1: i2c@e6508000 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 compatible = "renesas,i2c-r8a774c0", 469 "renesas,rcar-gen3-i2c"; 470 reg = <0 0xe6508000 0 0x40>; 471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cpg CPG_MOD 930>; 473 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 474 resets = <&cpg 930>; 475 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 476 <&dmac2 0x93>, <&dmac2 0x92>; 477 dma-names = "tx", "rx", "tx", "rx"; 478 i2c-scl-internal-delay-ns = <6>; 479 status = "disabled"; 480 }; 481 482 i2c2: i2c@e6510000 { 483 #address-cells = <1>; 484 #size-cells = <0>; 485 compatible = "renesas,i2c-r8a774c0", 486 "renesas,rcar-gen3-i2c"; 487 reg = <0 0xe6510000 0 0x40>; 488 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cpg CPG_MOD 929>; 490 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 491 resets = <&cpg 929>; 492 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 493 <&dmac2 0x95>, <&dmac2 0x94>; 494 dma-names = "tx", "rx", "tx", "rx"; 495 i2c-scl-internal-delay-ns = <6>; 496 status = "disabled"; 497 }; 498 499 i2c3: i2c@e66d0000 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 compatible = "renesas,i2c-r8a774c0", 503 "renesas,rcar-gen3-i2c"; 504 reg = <0 0xe66d0000 0 0x40>; 505 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 928>; 507 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 508 resets = <&cpg 928>; 509 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 510 dma-names = "tx", "rx"; 511 i2c-scl-internal-delay-ns = <110>; 512 status = "disabled"; 513 }; 514 515 i2c4: i2c@e66d8000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "renesas,i2c-r8a774c0", 519 "renesas,rcar-gen3-i2c"; 520 reg = <0 0xe66d8000 0 0x40>; 521 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 927>; 523 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 524 resets = <&cpg 927>; 525 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 526 dma-names = "tx", "rx"; 527 i2c-scl-internal-delay-ns = <6>; 528 status = "disabled"; 529 }; 530 531 i2c5: i2c@e66e0000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "renesas,i2c-r8a774c0", 535 "renesas,rcar-gen3-i2c"; 536 reg = <0 0xe66e0000 0 0x40>; 537 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&cpg CPG_MOD 919>; 539 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 540 resets = <&cpg 919>; 541 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 542 dma-names = "tx", "rx"; 543 i2c-scl-internal-delay-ns = <6>; 544 status = "disabled"; 545 }; 546 547 i2c6: i2c@e66e8000 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 compatible = "renesas,i2c-r8a774c0", 551 "renesas,rcar-gen3-i2c"; 552 reg = <0 0xe66e8000 0 0x40>; 553 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&cpg CPG_MOD 918>; 555 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 556 resets = <&cpg 918>; 557 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 558 dma-names = "tx", "rx"; 559 i2c-scl-internal-delay-ns = <6>; 560 status = "disabled"; 561 }; 562 563 i2c7: i2c@e6690000 { 564 #address-cells = <1>; 565 #size-cells = <0>; 566 compatible = "renesas,i2c-r8a774c0", 567 "renesas,rcar-gen3-i2c"; 568 reg = <0 0xe6690000 0 0x40>; 569 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 1003>; 571 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 572 resets = <&cpg 1003>; 573 i2c-scl-internal-delay-ns = <6>; 574 status = "disabled"; 575 }; 576 577 i2c_dvfs: i2c@e60b0000 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 compatible = "renesas,iic-r8a774c0"; 581 reg = <0 0xe60b0000 0 0x15>; 582 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cpg CPG_MOD 926>; 584 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 585 resets = <&cpg 926>; 586 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 587 dma-names = "tx", "rx"; 588 status = "disabled"; 589 }; 590 591 hscif0: serial@e6540000 { 592 compatible = "renesas,hscif-r8a774c0", 593 "renesas,rcar-gen3-hscif", 594 "renesas,hscif"; 595 reg = <0 0xe6540000 0 0x60>; 596 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 520>, 598 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 599 <&scif_clk>; 600 clock-names = "fck", "brg_int", "scif_clk"; 601 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 602 <&dmac2 0x31>, <&dmac2 0x30>; 603 dma-names = "tx", "rx", "tx", "rx"; 604 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 605 resets = <&cpg 520>; 606 status = "disabled"; 607 }; 608 609 hscif1: serial@e6550000 { 610 compatible = "renesas,hscif-r8a774c0", 611 "renesas,rcar-gen3-hscif", 612 "renesas,hscif"; 613 reg = <0 0xe6550000 0 0x60>; 614 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&cpg CPG_MOD 519>, 616 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 617 <&scif_clk>; 618 clock-names = "fck", "brg_int", "scif_clk"; 619 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 620 <&dmac2 0x33>, <&dmac2 0x32>; 621 dma-names = "tx", "rx", "tx", "rx"; 622 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 623 resets = <&cpg 519>; 624 status = "disabled"; 625 }; 626 627 hscif2: serial@e6560000 { 628 compatible = "renesas,hscif-r8a774c0", 629 "renesas,rcar-gen3-hscif", 630 "renesas,hscif"; 631 reg = <0 0xe6560000 0 0x60>; 632 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cpg CPG_MOD 518>, 634 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 635 <&scif_clk>; 636 clock-names = "fck", "brg_int", "scif_clk"; 637 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 638 <&dmac2 0x35>, <&dmac2 0x34>; 639 dma-names = "tx", "rx", "tx", "rx"; 640 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 641 resets = <&cpg 518>; 642 status = "disabled"; 643 }; 644 645 hscif3: serial@e66a0000 { 646 compatible = "renesas,hscif-r8a774c0", 647 "renesas,rcar-gen3-hscif", 648 "renesas,hscif"; 649 reg = <0 0xe66a0000 0 0x60>; 650 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cpg CPG_MOD 517>, 652 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 653 <&scif_clk>; 654 clock-names = "fck", "brg_int", "scif_clk"; 655 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 656 dma-names = "tx", "rx"; 657 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 658 resets = <&cpg 517>; 659 status = "disabled"; 660 }; 661 662 hscif4: serial@e66b0000 { 663 compatible = "renesas,hscif-r8a774c0", 664 "renesas,rcar-gen3-hscif", 665 "renesas,hscif"; 666 reg = <0 0xe66b0000 0 0x60>; 667 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&cpg CPG_MOD 516>, 669 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 670 <&scif_clk>; 671 clock-names = "fck", "brg_int", "scif_clk"; 672 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 673 dma-names = "tx", "rx"; 674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 675 resets = <&cpg 516>; 676 status = "disabled"; 677 }; 678 679 hsusb: usb@e6590000 { 680 compatible = "renesas,usbhs-r8a774c0", 681 "renesas,rcar-gen3-usbhs"; 682 reg = <0 0xe6590000 0 0x200>; 683 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 685 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 686 <&usb_dmac1 0>, <&usb_dmac1 1>; 687 dma-names = "ch0", "ch1", "ch2", "ch3"; 688 renesas,buswait = <11>; 689 phys = <&usb2_phy0 3>; 690 phy-names = "usb"; 691 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 692 resets = <&cpg 704>, <&cpg 703>; 693 status = "disabled"; 694 }; 695 696 usb_dmac0: dma-controller@e65a0000 { 697 compatible = "renesas,r8a774c0-usb-dmac", 698 "renesas,usb-dmac"; 699 reg = <0 0xe65a0000 0 0x100>; 700 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-names = "ch0", "ch1"; 703 clocks = <&cpg CPG_MOD 330>; 704 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 705 resets = <&cpg 330>; 706 #dma-cells = <1>; 707 dma-channels = <2>; 708 }; 709 710 usb_dmac1: dma-controller@e65b0000 { 711 compatible = "renesas,r8a774c0-usb-dmac", 712 "renesas,usb-dmac"; 713 reg = <0 0xe65b0000 0 0x100>; 714 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 716 interrupt-names = "ch0", "ch1"; 717 clocks = <&cpg CPG_MOD 331>; 718 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 719 resets = <&cpg 331>; 720 #dma-cells = <1>; 721 dma-channels = <2>; 722 }; 723 724 dmac0: dma-controller@e6700000 { 725 compatible = "renesas,dmac-r8a774c0", 726 "renesas,rcar-dmac"; 727 reg = <0 0xe6700000 0 0x10000>; 728 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 745 interrupt-names = "error", 746 "ch0", "ch1", "ch2", "ch3", 747 "ch4", "ch5", "ch6", "ch7", 748 "ch8", "ch9", "ch10", "ch11", 749 "ch12", "ch13", "ch14", "ch15"; 750 clocks = <&cpg CPG_MOD 219>; 751 clock-names = "fck"; 752 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 753 resets = <&cpg 219>; 754 #dma-cells = <1>; 755 dma-channels = <16>; 756 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 757 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 758 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 759 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 760 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 761 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 762 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 763 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 764 }; 765 766 dmac1: dma-controller@e7300000 { 767 compatible = "renesas,dmac-r8a774c0", 768 "renesas,rcar-dmac"; 769 reg = <0 0xe7300000 0 0x10000>; 770 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 787 interrupt-names = "error", 788 "ch0", "ch1", "ch2", "ch3", 789 "ch4", "ch5", "ch6", "ch7", 790 "ch8", "ch9", "ch10", "ch11", 791 "ch12", "ch13", "ch14", "ch15"; 792 clocks = <&cpg CPG_MOD 218>; 793 clock-names = "fck"; 794 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 795 resets = <&cpg 218>; 796 #dma-cells = <1>; 797 dma-channels = <16>; 798 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 799 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 800 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 801 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 802 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 803 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 804 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 805 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 806 }; 807 808 dmac2: dma-controller@e7310000 { 809 compatible = "renesas,dmac-r8a774c0", 810 "renesas,rcar-dmac"; 811 reg = <0 0xe7310000 0 0x10000>; 812 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 829 interrupt-names = "error", 830 "ch0", "ch1", "ch2", "ch3", 831 "ch4", "ch5", "ch6", "ch7", 832 "ch8", "ch9", "ch10", "ch11", 833 "ch12", "ch13", "ch14", "ch15"; 834 clocks = <&cpg CPG_MOD 217>; 835 clock-names = "fck"; 836 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 837 resets = <&cpg 217>; 838 #dma-cells = <1>; 839 dma-channels = <16>; 840 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 841 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 842 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 843 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 844 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 845 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 846 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 847 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 848 }; 849 850 ipmmu_ds0: mmu@e6740000 { 851 compatible = "renesas,ipmmu-r8a774c0"; 852 reg = <0 0xe6740000 0 0x1000>; 853 renesas,ipmmu-main = <&ipmmu_mm 0>; 854 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 855 #iommu-cells = <1>; 856 }; 857 858 ipmmu_ds1: mmu@e7740000 { 859 compatible = "renesas,ipmmu-r8a774c0"; 860 reg = <0 0xe7740000 0 0x1000>; 861 renesas,ipmmu-main = <&ipmmu_mm 1>; 862 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 863 #iommu-cells = <1>; 864 }; 865 866 ipmmu_hc: mmu@e6570000 { 867 compatible = "renesas,ipmmu-r8a774c0"; 868 reg = <0 0xe6570000 0 0x1000>; 869 renesas,ipmmu-main = <&ipmmu_mm 2>; 870 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 871 #iommu-cells = <1>; 872 }; 873 874 ipmmu_mm: mmu@e67b0000 { 875 compatible = "renesas,ipmmu-r8a774c0"; 876 reg = <0 0xe67b0000 0 0x1000>; 877 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 879 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 880 #iommu-cells = <1>; 881 }; 882 883 ipmmu_mp: mmu@ec670000 { 884 compatible = "renesas,ipmmu-r8a774c0"; 885 reg = <0 0xec670000 0 0x1000>; 886 renesas,ipmmu-main = <&ipmmu_mm 4>; 887 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 888 #iommu-cells = <1>; 889 }; 890 891 ipmmu_pv0: mmu@fd800000 { 892 compatible = "renesas,ipmmu-r8a774c0"; 893 reg = <0 0xfd800000 0 0x1000>; 894 renesas,ipmmu-main = <&ipmmu_mm 6>; 895 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 896 #iommu-cells = <1>; 897 }; 898 899 ipmmu_vc0: mmu@fe6b0000 { 900 compatible = "renesas,ipmmu-r8a774c0"; 901 reg = <0 0xfe6b0000 0 0x1000>; 902 renesas,ipmmu-main = <&ipmmu_mm 12>; 903 power-domains = <&sysc R8A774C0_PD_A3VC>; 904 #iommu-cells = <1>; 905 }; 906 907 ipmmu_vi0: mmu@febd0000 { 908 compatible = "renesas,ipmmu-r8a774c0"; 909 reg = <0 0xfebd0000 0 0x1000>; 910 renesas,ipmmu-main = <&ipmmu_mm 14>; 911 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 912 #iommu-cells = <1>; 913 }; 914 915 ipmmu_vp0: mmu@fe990000 { 916 compatible = "renesas,ipmmu-r8a774c0"; 917 reg = <0 0xfe990000 0 0x1000>; 918 renesas,ipmmu-main = <&ipmmu_mm 16>; 919 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 920 #iommu-cells = <1>; 921 }; 922 923 avb: ethernet@e6800000 { 924 compatible = "renesas,etheravb-r8a774c0", 925 "renesas,etheravb-rcar-gen3"; 926 reg = <0 0xe6800000 0 0x800>; 927 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 952 interrupt-names = "ch0", "ch1", "ch2", "ch3", 953 "ch4", "ch5", "ch6", "ch7", 954 "ch8", "ch9", "ch10", "ch11", 955 "ch12", "ch13", "ch14", "ch15", 956 "ch16", "ch17", "ch18", "ch19", 957 "ch20", "ch21", "ch22", "ch23", 958 "ch24"; 959 clocks = <&cpg CPG_MOD 812>; 960 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 961 resets = <&cpg 812>; 962 phy-mode = "rgmii"; 963 iommus = <&ipmmu_ds0 16>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 status = "disabled"; 967 }; 968 969 can0: can@e6c30000 { 970 compatible = "renesas,can-r8a774c0", 971 "renesas,rcar-gen3-can"; 972 reg = <0 0xe6c30000 0 0x1000>; 973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cpg CPG_MOD 916>, 975 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 976 <&can_clk>; 977 clock-names = "clkp1", "clkp2", "can_clk"; 978 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 979 assigned-clock-rates = <40000000>; 980 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 981 resets = <&cpg 916>; 982 status = "disabled"; 983 }; 984 985 can1: can@e6c38000 { 986 compatible = "renesas,can-r8a774c0", 987 "renesas,rcar-gen3-can"; 988 reg = <0 0xe6c38000 0 0x1000>; 989 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cpg CPG_MOD 915>, 991 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 992 <&can_clk>; 993 clock-names = "clkp1", "clkp2", "can_clk"; 994 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 995 assigned-clock-rates = <40000000>; 996 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 997 resets = <&cpg 915>; 998 status = "disabled"; 999 }; 1000 1001 canfd: can@e66c0000 { 1002 compatible = "renesas,r8a774c0-canfd", 1003 "renesas,rcar-gen3-canfd"; 1004 reg = <0 0xe66c0000 0 0x8000>; 1005 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&cpg CPG_MOD 914>, 1008 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1009 <&can_clk>; 1010 clock-names = "fck", "canfd", "can_clk"; 1011 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1012 assigned-clock-rates = <40000000>; 1013 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1014 resets = <&cpg 914>; 1015 status = "disabled"; 1016 1017 channel0 { 1018 status = "disabled"; 1019 }; 1020 1021 channel1 { 1022 status = "disabled"; 1023 }; 1024 }; 1025 1026 pwm0: pwm@e6e30000 { 1027 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1028 reg = <0 0xe6e30000 0 0x8>; 1029 clocks = <&cpg CPG_MOD 523>; 1030 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1031 resets = <&cpg 523>; 1032 #pwm-cells = <2>; 1033 status = "disabled"; 1034 }; 1035 1036 pwm1: pwm@e6e31000 { 1037 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1038 reg = <0 0xe6e31000 0 0x8>; 1039 clocks = <&cpg CPG_MOD 523>; 1040 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1041 resets = <&cpg 523>; 1042 #pwm-cells = <2>; 1043 status = "disabled"; 1044 }; 1045 1046 pwm2: pwm@e6e32000 { 1047 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1048 reg = <0 0xe6e32000 0 0x8>; 1049 clocks = <&cpg CPG_MOD 523>; 1050 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1051 resets = <&cpg 523>; 1052 #pwm-cells = <2>; 1053 status = "disabled"; 1054 }; 1055 1056 pwm3: pwm@e6e33000 { 1057 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1058 reg = <0 0xe6e33000 0 0x8>; 1059 clocks = <&cpg CPG_MOD 523>; 1060 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1061 resets = <&cpg 523>; 1062 #pwm-cells = <2>; 1063 status = "disabled"; 1064 }; 1065 1066 pwm4: pwm@e6e34000 { 1067 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1068 reg = <0 0xe6e34000 0 0x8>; 1069 clocks = <&cpg CPG_MOD 523>; 1070 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1071 resets = <&cpg 523>; 1072 #pwm-cells = <2>; 1073 status = "disabled"; 1074 }; 1075 1076 pwm5: pwm@e6e35000 { 1077 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1078 reg = <0 0xe6e35000 0 0x8>; 1079 clocks = <&cpg CPG_MOD 523>; 1080 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1081 resets = <&cpg 523>; 1082 #pwm-cells = <2>; 1083 status = "disabled"; 1084 }; 1085 1086 pwm6: pwm@e6e36000 { 1087 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1088 reg = <0 0xe6e36000 0 0x8>; 1089 clocks = <&cpg CPG_MOD 523>; 1090 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1091 resets = <&cpg 523>; 1092 #pwm-cells = <2>; 1093 status = "disabled"; 1094 }; 1095 1096 scif0: serial@e6e60000 { 1097 compatible = "renesas,scif-r8a774c0", 1098 "renesas,rcar-gen3-scif", "renesas,scif"; 1099 reg = <0 0xe6e60000 0 64>; 1100 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&cpg CPG_MOD 207>, 1102 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1103 <&scif_clk>; 1104 clock-names = "fck", "brg_int", "scif_clk"; 1105 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1106 <&dmac2 0x51>, <&dmac2 0x50>; 1107 dma-names = "tx", "rx", "tx", "rx"; 1108 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1109 resets = <&cpg 207>; 1110 status = "disabled"; 1111 }; 1112 1113 scif1: serial@e6e68000 { 1114 compatible = "renesas,scif-r8a774c0", 1115 "renesas,rcar-gen3-scif", "renesas,scif"; 1116 reg = <0 0xe6e68000 0 64>; 1117 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&cpg CPG_MOD 206>, 1119 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1120 <&scif_clk>; 1121 clock-names = "fck", "brg_int", "scif_clk"; 1122 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1123 <&dmac2 0x53>, <&dmac2 0x52>; 1124 dma-names = "tx", "rx", "tx", "rx"; 1125 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1126 resets = <&cpg 206>; 1127 status = "disabled"; 1128 }; 1129 1130 scif2: serial@e6e88000 { 1131 compatible = "renesas,scif-r8a774c0", 1132 "renesas,rcar-gen3-scif", "renesas,scif"; 1133 reg = <0 0xe6e88000 0 64>; 1134 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&cpg CPG_MOD 310>, 1136 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1137 <&scif_clk>; 1138 clock-names = "fck", "brg_int", "scif_clk"; 1139 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1140 <&dmac2 0x13>, <&dmac2 0x12>; 1141 dma-names = "tx", "rx", "tx", "rx"; 1142 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1143 resets = <&cpg 310>; 1144 status = "disabled"; 1145 }; 1146 1147 scif3: serial@e6c50000 { 1148 compatible = "renesas,scif-r8a774c0", 1149 "renesas,rcar-gen3-scif", "renesas,scif"; 1150 reg = <0 0xe6c50000 0 64>; 1151 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&cpg CPG_MOD 204>, 1153 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1154 <&scif_clk>; 1155 clock-names = "fck", "brg_int", "scif_clk"; 1156 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1157 dma-names = "tx", "rx"; 1158 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1159 resets = <&cpg 204>; 1160 status = "disabled"; 1161 }; 1162 1163 scif4: serial@e6c40000 { 1164 compatible = "renesas,scif-r8a774c0", 1165 "renesas,rcar-gen3-scif", "renesas,scif"; 1166 reg = <0 0xe6c40000 0 64>; 1167 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&cpg CPG_MOD 203>, 1169 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1170 <&scif_clk>; 1171 clock-names = "fck", "brg_int", "scif_clk"; 1172 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1173 dma-names = "tx", "rx"; 1174 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1175 resets = <&cpg 203>; 1176 status = "disabled"; 1177 }; 1178 1179 scif5: serial@e6f30000 { 1180 compatible = "renesas,scif-r8a774c0", 1181 "renesas,rcar-gen3-scif", "renesas,scif"; 1182 reg = <0 0xe6f30000 0 64>; 1183 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&cpg CPG_MOD 202>, 1185 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1186 <&scif_clk>; 1187 clock-names = "fck", "brg_int", "scif_clk"; 1188 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1189 dma-names = "tx", "rx"; 1190 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1191 resets = <&cpg 202>; 1192 status = "disabled"; 1193 }; 1194 1195 msiof0: spi@e6e90000 { 1196 compatible = "renesas,msiof-r8a774c0", 1197 "renesas,rcar-gen3-msiof"; 1198 reg = <0 0xe6e90000 0 0x0064>; 1199 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cpg CPG_MOD 211>; 1201 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1202 <&dmac2 0x41>, <&dmac2 0x40>; 1203 dma-names = "tx", "rx", "tx", "rx"; 1204 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1205 resets = <&cpg 211>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 msiof1: spi@e6ea0000 { 1212 compatible = "renesas,msiof-r8a774c0", 1213 "renesas,rcar-gen3-msiof"; 1214 reg = <0 0xe6ea0000 0 0x0064>; 1215 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&cpg CPG_MOD 210>; 1217 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1218 <&dmac2 0x43>, <&dmac2 0x42>; 1219 dma-names = "tx", "rx", "tx", "rx"; 1220 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1221 resets = <&cpg 210>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 msiof2: spi@e6c00000 { 1228 compatible = "renesas,msiof-r8a774c0", 1229 "renesas,rcar-gen3-msiof"; 1230 reg = <0 0xe6c00000 0 0x0064>; 1231 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&cpg CPG_MOD 209>; 1233 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1234 dma-names = "tx", "rx"; 1235 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1236 resets = <&cpg 209>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 msiof3: spi@e6c10000 { 1243 compatible = "renesas,msiof-r8a774c0", 1244 "renesas,rcar-gen3-msiof"; 1245 reg = <0 0xe6c10000 0 0x0064>; 1246 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&cpg CPG_MOD 208>; 1248 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1251 resets = <&cpg 208>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 vin4: video@e6ef4000 { 1258 compatible = "renesas,vin-r8a774c0"; 1259 reg = <0 0xe6ef4000 0 0x1000>; 1260 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&cpg CPG_MOD 807>; 1262 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1263 resets = <&cpg 807>; 1264 renesas,id = <4>; 1265 status = "disabled"; 1266 1267 ports { 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 1271 port@1 { 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 1275 reg = <1>; 1276 1277 vin4csi40: endpoint@2 { 1278 reg = <2>; 1279 remote-endpoint= <&csi40vin4>; 1280 }; 1281 }; 1282 }; 1283 }; 1284 1285 vin5: video@e6ef5000 { 1286 compatible = "renesas,vin-r8a774c0"; 1287 reg = <0 0xe6ef5000 0 0x1000>; 1288 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cpg CPG_MOD 806>; 1290 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1291 resets = <&cpg 806>; 1292 renesas,id = <5>; 1293 status = "disabled"; 1294 1295 ports { 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 1299 port@1 { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 1303 reg = <1>; 1304 1305 vin5csi40: endpoint@2 { 1306 reg = <2>; 1307 remote-endpoint= <&csi40vin5>; 1308 }; 1309 }; 1310 }; 1311 }; 1312 1313 rcar_sound: sound@ec500000 { 1314 /* 1315 * #sound-dai-cells is required 1316 * 1317 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1318 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1319 */ 1320 /* 1321 * #clock-cells is required for audio_clkout0/1/2/3 1322 * 1323 * clkout : #clock-cells = <0>; <&rcar_sound>; 1324 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1325 */ 1326 compatible = "renesas,rcar_sound-r8a774c0", 1327 "renesas,rcar_sound-gen3"; 1328 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1329 <0 0xec5a0000 0 0x100>, /* ADG */ 1330 <0 0xec540000 0 0x1000>, /* SSIU */ 1331 <0 0xec541000 0 0x280>, /* SSI */ 1332 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1333 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1334 1335 clocks = <&cpg CPG_MOD 1005>, 1336 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1337 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1338 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1339 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1340 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1341 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1342 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1343 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1344 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1345 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1346 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1347 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1348 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1349 <&audio_clk_a>, <&audio_clk_b>, 1350 <&audio_clk_c>, 1351 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1352 clock-names = "ssi-all", 1353 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1354 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1355 "ssi.1", "ssi.0", 1356 "src.9", "src.8", "src.7", "src.6", 1357 "src.5", "src.4", "src.3", "src.2", 1358 "src.1", "src.0", 1359 "mix.1", "mix.0", 1360 "ctu.1", "ctu.0", 1361 "dvc.0", "dvc.1", 1362 "clk_a", "clk_b", "clk_c", "clk_i"; 1363 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1364 resets = <&cpg 1005>, 1365 <&cpg 1006>, <&cpg 1007>, 1366 <&cpg 1008>, <&cpg 1009>, 1367 <&cpg 1010>, <&cpg 1011>, 1368 <&cpg 1012>, <&cpg 1013>, 1369 <&cpg 1014>, <&cpg 1015>; 1370 reset-names = "ssi-all", 1371 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1372 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1373 "ssi.1", "ssi.0"; 1374 status = "disabled"; 1375 1376 rcar_sound,ctu { 1377 ctu00: ctu-0 { }; 1378 ctu01: ctu-1 { }; 1379 ctu02: ctu-2 { }; 1380 ctu03: ctu-3 { }; 1381 ctu10: ctu-4 { }; 1382 ctu11: ctu-5 { }; 1383 ctu12: ctu-6 { }; 1384 ctu13: ctu-7 { }; 1385 }; 1386 1387 rcar_sound,dvc { 1388 dvc0: dvc-0 { 1389 dmas = <&audma0 0xbc>; 1390 dma-names = "tx"; 1391 }; 1392 dvc1: dvc-1 { 1393 dmas = <&audma0 0xbe>; 1394 dma-names = "tx"; 1395 }; 1396 }; 1397 1398 rcar_sound,mix { 1399 mix0: mix-0 { }; 1400 mix1: mix-1 { }; 1401 }; 1402 1403 rcar_sound,src { 1404 src0: src-0 { 1405 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1407 dma-names = "rx", "tx"; 1408 }; 1409 src1: src-1 { 1410 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1411 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1412 dma-names = "rx", "tx"; 1413 }; 1414 src2: src-2 { 1415 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1417 dma-names = "rx", "tx"; 1418 }; 1419 src3: src-3 { 1420 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1421 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1422 dma-names = "rx", "tx"; 1423 }; 1424 src4: src-4 { 1425 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1427 dma-names = "rx", "tx"; 1428 }; 1429 src5: src-5 { 1430 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1432 dma-names = "rx", "tx"; 1433 }; 1434 src6: src-6 { 1435 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1437 dma-names = "rx", "tx"; 1438 }; 1439 src7: src-7 { 1440 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1442 dma-names = "rx", "tx"; 1443 }; 1444 src8: src-8 { 1445 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1446 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1447 dma-names = "rx", "tx"; 1448 }; 1449 src9: src-9 { 1450 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1451 dmas = <&audma0 0x97>, <&audma0 0xba>; 1452 dma-names = "rx", "tx"; 1453 }; 1454 }; 1455 1456 rcar_sound,ssi { 1457 ssi0: ssi-0 { 1458 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1459 dmas = <&audma0 0x01>, <&audma0 0x02>, 1460 <&audma0 0x15>, <&audma0 0x16>; 1461 dma-names = "rx", "tx", "rxu", "txu"; 1462 }; 1463 ssi1: ssi-1 { 1464 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1465 dmas = <&audma0 0x03>, <&audma0 0x04>, 1466 <&audma0 0x49>, <&audma0 0x4a>; 1467 dma-names = "rx", "tx", "rxu", "txu"; 1468 }; 1469 ssi2: ssi-2 { 1470 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1471 dmas = <&audma0 0x05>, <&audma0 0x06>, 1472 <&audma0 0x63>, <&audma0 0x64>; 1473 dma-names = "rx", "tx", "rxu", "txu"; 1474 }; 1475 ssi3: ssi-3 { 1476 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1477 dmas = <&audma0 0x07>, <&audma0 0x08>, 1478 <&audma0 0x6f>, <&audma0 0x70>; 1479 dma-names = "rx", "tx", "rxu", "txu"; 1480 }; 1481 ssi4: ssi-4 { 1482 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1483 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1484 <&audma0 0x71>, <&audma0 0x72>; 1485 dma-names = "rx", "tx", "rxu", "txu"; 1486 }; 1487 ssi5: ssi-5 { 1488 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1489 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1490 <&audma0 0x73>, <&audma0 0x74>; 1491 dma-names = "rx", "tx", "rxu", "txu"; 1492 }; 1493 ssi6: ssi-6 { 1494 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1495 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1496 <&audma0 0x75>, <&audma0 0x76>; 1497 dma-names = "rx", "tx", "rxu", "txu"; 1498 }; 1499 ssi7: ssi-7 { 1500 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1501 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1502 <&audma0 0x79>, <&audma0 0x7a>; 1503 dma-names = "rx", "tx", "rxu", "txu"; 1504 }; 1505 ssi8: ssi-8 { 1506 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1507 dmas = <&audma0 0x11>, <&audma0 0x12>, 1508 <&audma0 0x7b>, <&audma0 0x7c>; 1509 dma-names = "rx", "tx", "rxu", "txu"; 1510 }; 1511 ssi9: ssi-9 { 1512 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1513 dmas = <&audma0 0x13>, <&audma0 0x14>, 1514 <&audma0 0x7d>, <&audma0 0x7e>; 1515 dma-names = "rx", "tx", "rxu", "txu"; 1516 }; 1517 }; 1518 }; 1519 1520 audma0: dma-controller@ec700000 { 1521 compatible = "renesas,dmac-r8a774c0", 1522 "renesas,rcar-dmac"; 1523 reg = <0 0xec700000 0 0x10000>; 1524 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1541 interrupt-names = "error", 1542 "ch0", "ch1", "ch2", "ch3", 1543 "ch4", "ch5", "ch6", "ch7", 1544 "ch8", "ch9", "ch10", "ch11", 1545 "ch12", "ch13", "ch14", "ch15"; 1546 clocks = <&cpg CPG_MOD 502>; 1547 clock-names = "fck"; 1548 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1549 resets = <&cpg 502>; 1550 #dma-cells = <1>; 1551 dma-channels = <16>; 1552 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1553 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1554 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1555 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1556 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1557 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1558 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1559 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1560 }; 1561 1562 xhci0: usb@ee000000 { 1563 compatible = "renesas,xhci-r8a774c0", 1564 "renesas,rcar-gen3-xhci"; 1565 reg = <0 0xee000000 0 0xc00>; 1566 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&cpg CPG_MOD 328>; 1568 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1569 resets = <&cpg 328>; 1570 status = "disabled"; 1571 }; 1572 1573 usb3_peri0: usb@ee020000 { 1574 compatible = "renesas,r8a774c0-usb3-peri", 1575 "renesas,rcar-gen3-usb3-peri"; 1576 reg = <0 0xee020000 0 0x400>; 1577 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&cpg CPG_MOD 328>; 1579 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1580 resets = <&cpg 328>; 1581 status = "disabled"; 1582 }; 1583 1584 ohci0: usb@ee080000 { 1585 compatible = "generic-ohci"; 1586 reg = <0 0xee080000 0 0x100>; 1587 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1588 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1589 phys = <&usb2_phy0 1>; 1590 phy-names = "usb"; 1591 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1592 resets = <&cpg 703>, <&cpg 704>; 1593 status = "disabled"; 1594 }; 1595 1596 ehci0: usb@ee080100 { 1597 compatible = "generic-ehci"; 1598 reg = <0 0xee080100 0 0x100>; 1599 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1601 phys = <&usb2_phy0 2>; 1602 phy-names = "usb"; 1603 companion = <&ohci0>; 1604 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1605 resets = <&cpg 703>, <&cpg 704>; 1606 status = "disabled"; 1607 }; 1608 1609 usb2_phy0: usb-phy@ee080200 { 1610 compatible = "renesas,usb2-phy-r8a774c0", 1611 "renesas,rcar-gen3-usb2-phy"; 1612 reg = <0 0xee080200 0 0x700>; 1613 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1615 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1616 resets = <&cpg 703>, <&cpg 704>; 1617 #phy-cells = <1>; 1618 status = "disabled"; 1619 }; 1620 1621 sdhi0: sd@ee100000 { 1622 compatible = "renesas,sdhi-r8a774c0", 1623 "renesas,rcar-gen3-sdhi"; 1624 reg = <0 0xee100000 0 0x2000>; 1625 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&cpg CPG_MOD 314>; 1627 max-frequency = <200000000>; 1628 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1629 resets = <&cpg 314>; 1630 status = "disabled"; 1631 }; 1632 1633 sdhi1: sd@ee120000 { 1634 compatible = "renesas,sdhi-r8a774c0", 1635 "renesas,rcar-gen3-sdhi"; 1636 reg = <0 0xee120000 0 0x2000>; 1637 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&cpg CPG_MOD 313>; 1639 max-frequency = <200000000>; 1640 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1641 resets = <&cpg 313>; 1642 status = "disabled"; 1643 }; 1644 1645 sdhi3: sd@ee160000 { 1646 compatible = "renesas,sdhi-r8a774c0", 1647 "renesas,rcar-gen3-sdhi"; 1648 reg = <0 0xee160000 0 0x2000>; 1649 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&cpg CPG_MOD 311>; 1651 max-frequency = <200000000>; 1652 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1653 resets = <&cpg 311>; 1654 status = "disabled"; 1655 }; 1656 1657 gic: interrupt-controller@f1010000 { 1658 compatible = "arm,gic-400"; 1659 #interrupt-cells = <3>; 1660 #address-cells = <0>; 1661 interrupt-controller; 1662 reg = <0x0 0xf1010000 0 0x1000>, 1663 <0x0 0xf1020000 0 0x20000>, 1664 <0x0 0xf1040000 0 0x20000>, 1665 <0x0 0xf1060000 0 0x20000>; 1666 interrupts = <GIC_PPI 9 1667 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1668 clocks = <&cpg CPG_MOD 408>; 1669 clock-names = "clk"; 1670 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1671 resets = <&cpg 408>; 1672 }; 1673 1674 pciec0: pcie@fe000000 { 1675 compatible = "renesas,pcie-r8a774c0", 1676 "renesas,pcie-rcar-gen3"; 1677 reg = <0 0xfe000000 0 0x80000>; 1678 #address-cells = <3>; 1679 #size-cells = <2>; 1680 bus-range = <0x00 0xff>; 1681 device_type = "pci"; 1682 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1683 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1684 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1685 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1686 /* Map all possible DDR as inbound ranges */ 1687 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1688 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1691 #interrupt-cells = <1>; 1692 interrupt-map-mask = <0 0 0 0>; 1693 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1695 clock-names = "pcie", "pcie_bus"; 1696 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1697 resets = <&cpg 319>; 1698 status = "disabled"; 1699 }; 1700 1701 vspb0: vsp@fe960000 { 1702 compatible = "renesas,vsp2"; 1703 reg = <0 0xfe960000 0 0x8000>; 1704 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1705 clocks = <&cpg CPG_MOD 626>; 1706 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1707 resets = <&cpg 626>; 1708 renesas,fcp = <&fcpvb0>; 1709 }; 1710 1711 vspd0: vsp@fea20000 { 1712 compatible = "renesas,vsp2"; 1713 reg = <0 0xfea20000 0 0x7000>; 1714 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1715 clocks = <&cpg CPG_MOD 623>; 1716 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1717 resets = <&cpg 623>; 1718 renesas,fcp = <&fcpvd0>; 1719 }; 1720 1721 vspd1: vsp@fea28000 { 1722 compatible = "renesas,vsp2"; 1723 reg = <0 0xfea28000 0 0x7000>; 1724 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1725 clocks = <&cpg CPG_MOD 622>; 1726 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1727 resets = <&cpg 622>; 1728 renesas,fcp = <&fcpvd1>; 1729 }; 1730 1731 vspi0: vsp@fe9a0000 { 1732 compatible = "renesas,vsp2"; 1733 reg = <0 0xfe9a0000 0 0x8000>; 1734 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&cpg CPG_MOD 631>; 1736 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1737 resets = <&cpg 631>; 1738 renesas,fcp = <&fcpvi0>; 1739 }; 1740 1741 fcpvb0: fcp@fe96f000 { 1742 compatible = "renesas,fcpv"; 1743 reg = <0 0xfe96f000 0 0x200>; 1744 clocks = <&cpg CPG_MOD 607>; 1745 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1746 resets = <&cpg 607>; 1747 iommus = <&ipmmu_vp0 5>; 1748 }; 1749 1750 fcpvd0: fcp@fea27000 { 1751 compatible = "renesas,fcpv"; 1752 reg = <0 0xfea27000 0 0x200>; 1753 clocks = <&cpg CPG_MOD 603>; 1754 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1755 resets = <&cpg 603>; 1756 iommus = <&ipmmu_vi0 8>; 1757 }; 1758 1759 fcpvd1: fcp@fea2f000 { 1760 compatible = "renesas,fcpv"; 1761 reg = <0 0xfea2f000 0 0x200>; 1762 clocks = <&cpg CPG_MOD 602>; 1763 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1764 resets = <&cpg 602>; 1765 iommus = <&ipmmu_vi0 9>; 1766 }; 1767 1768 fcpvi0: fcp@fe9af000 { 1769 compatible = "renesas,fcpv"; 1770 reg = <0 0xfe9af000 0 0x200>; 1771 clocks = <&cpg CPG_MOD 611>; 1772 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1773 resets = <&cpg 611>; 1774 iommus = <&ipmmu_vp0 8>; 1775 }; 1776 1777 csi40: csi2@feaa0000 { 1778 compatible = "renesas,r8a774c0-csi2"; 1779 reg = <0 0xfeaa0000 0 0x10000>; 1780 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1781 clocks = <&cpg CPG_MOD 716>; 1782 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1783 resets = <&cpg 716>; 1784 status = "disabled"; 1785 1786 ports { 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 1790 port@1 { 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 1794 reg = <1>; 1795 1796 csi40vin4: endpoint@0 { 1797 reg = <0>; 1798 remote-endpoint = <&vin4csi40>; 1799 }; 1800 csi40vin5: endpoint@1 { 1801 reg = <1>; 1802 remote-endpoint = <&vin5csi40>; 1803 }; 1804 }; 1805 }; 1806 }; 1807 1808 du: display@feb00000 { 1809 compatible = "renesas,du-r8a774c0"; 1810 reg = <0 0xfeb00000 0 0x40000>; 1811 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1813 clocks = <&cpg CPG_MOD 724>, 1814 <&cpg CPG_MOD 723>; 1815 clock-names = "du.0", "du.1"; 1816 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1817 1818 status = "disabled"; 1819 1820 ports { 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 1824 port@0 { 1825 reg = <0>; 1826 du_out_rgb: endpoint { 1827 }; 1828 }; 1829 1830 port@1 { 1831 reg = <1>; 1832 du_out_lvds0: endpoint { 1833 remote-endpoint = <&lvds0_in>; 1834 }; 1835 }; 1836 1837 port@2 { 1838 reg = <2>; 1839 du_out_lvds1: endpoint { 1840 remote-endpoint = <&lvds1_in>; 1841 }; 1842 }; 1843 }; 1844 }; 1845 1846 lvds0: lvds-encoder@feb90000 { 1847 compatible = "renesas,r8a774c0-lvds"; 1848 reg = <0 0xfeb90000 0 0x20>; 1849 clocks = <&cpg CPG_MOD 727>; 1850 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1851 resets = <&cpg 727>; 1852 status = "disabled"; 1853 1854 renesas,companion = <&lvds1>; 1855 1856 ports { 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 1860 port@0 { 1861 reg = <0>; 1862 lvds0_in: endpoint { 1863 remote-endpoint = <&du_out_lvds0>; 1864 }; 1865 }; 1866 1867 port@1 { 1868 reg = <1>; 1869 lvds0_out: endpoint { 1870 }; 1871 }; 1872 }; 1873 }; 1874 1875 lvds1: lvds-encoder@feb90100 { 1876 compatible = "renesas,r8a774c0-lvds"; 1877 reg = <0 0xfeb90100 0 0x20>; 1878 clocks = <&cpg CPG_MOD 727>; 1879 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1880 resets = <&cpg 726>; 1881 status = "disabled"; 1882 1883 ports { 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 1887 port@0 { 1888 reg = <0>; 1889 lvds1_in: endpoint { 1890 remote-endpoint = <&du_out_lvds1>; 1891 }; 1892 }; 1893 1894 port@1 { 1895 reg = <1>; 1896 lvds1_out: endpoint { 1897 }; 1898 }; 1899 }; 1900 }; 1901 1902 prr: chipid@fff00044 { 1903 compatible = "renesas,prr"; 1904 reg = <0 0xfff00044 0 4>; 1905 }; 1906 }; 1907 1908 thermal-zones { 1909 cpu-thermal { 1910 polling-delay-passive = <250>; 1911 polling-delay = <0>; 1912 thermal-sensors = <&thermal 0>; 1913 sustainable-power = <717>; 1914 1915 cooling-maps { 1916 map0 { 1917 trip = <&target>; 1918 cooling-device = <&a53_0 0 2>; 1919 contribution = <1024>; 1920 }; 1921 }; 1922 1923 trips { 1924 sensor1_crit: sensor1-crit { 1925 temperature = <120000>; 1926 hysteresis = <2000>; 1927 type = "critical"; 1928 }; 1929 1930 target: trip-point1 { 1931 temperature = <100000>; 1932 hysteresis = <2000>; 1933 type = "passive"; 1934 }; 1935 }; 1936 }; 1937 }; 1938 1939 timer { 1940 compatible = "arm,armv8-timer"; 1941 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1942 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1943 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1944 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1945 }; 1946 1947 /* External USB clocks - can be overridden by the board */ 1948 usb3s0_clk: usb3s0 { 1949 compatible = "fixed-clock"; 1950 #clock-cells = <0>; 1951 clock-frequency = <0>; 1952 }; 1953 1954 usb_extal_clk: usb_extal { 1955 compatible = "fixed-clock"; 1956 #clock-cells = <0>; 1957 clock-frequency = <0>; 1958 }; 1959}; 1960