1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
4 *
5 * Copyright (C) 2019 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include "r8a774c0.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
14	compatible = "si-linux,cat874", "renesas,r8a774c0";
15
16	aliases {
17		serial0 = &scif2;
18	};
19
20	chosen {
21		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
22		stdout-path = "serial0:115200n8";
23	};
24
25	leds {
26		compatible = "gpio-leds";
27
28		led0 {
29			gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
30			label = "LED0";
31		};
32
33		led1 {
34			gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
35			label = "LED1";
36		};
37
38		led2 {
39			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
40			label = "LED2";
41		};
42
43		led3 {
44			gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
45			label = "LED3";
46		};
47	};
48
49	memory@48000000 {
50		device_type = "memory";
51		/* first 128MB is reserved for secure area. */
52		reg = <0x0 0x48000000 0x0 0x78000000>;
53	};
54
55	vcc_sdhi0: regulator-vcc-sdhi0 {
56		compatible = "regulator-fixed";
57
58		regulator-name = "SDHI0 Vcc";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61		regulator-always-on;
62		regulator-boot-on;
63	};
64
65	vccq_sdhi0: regulator-vccq-sdhi0 {
66		compatible = "regulator-gpio";
67
68		regulator-name = "SDHI0 VccQ";
69		regulator-min-microvolt = <1800000>;
70		regulator-max-microvolt = <3300000>;
71
72		gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
73		gpios-states = <1>;
74		states = <3300000 1
75			  1800000 0>;
76	};
77};
78
79&ehci0 {
80	dr_mode = "host";
81	status = "okay";
82};
83
84&extal_clk {
85	clock-frequency = <48000000>;
86};
87
88&i2c1 {
89	pinctrl-0 = <&i2c1_pins>;
90	pinctrl-names = "default";
91
92	status = "okay";
93	clock-frequency = <400000>;
94
95	rtc@32 {
96		compatible = "epson,rx8571";
97		reg = <0x32>;
98	};
99};
100
101&ohci0 {
102	dr_mode = "host";
103	status = "okay";
104};
105
106&pcie_bus_clk {
107	clock-frequency = <100000000>;
108};
109
110&pciec0 {
111	/* Map all possible DDR as inbound ranges */
112	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
113};
114
115&pfc {
116	i2c1_pins: i2c1 {
117		groups = "i2c1_b";
118		function = "i2c1";
119	};
120
121	scif2_pins: scif2 {
122		groups = "scif2_data_a";
123		function = "scif2";
124	};
125
126	sdhi0_pins: sd0 {
127		groups = "sdhi0_data4", "sdhi0_ctrl";
128		function = "sdhi0";
129		power-source = <3300>;
130	};
131
132	sdhi0_pins_uhs: sd0_uhs {
133		groups = "sdhi0_data4", "sdhi0_ctrl";
134		function = "sdhi0";
135		power-source = <1800>;
136	};
137};
138
139&rwdt {
140	timeout-sec = <60>;
141	status = "okay";
142};
143
144&scif2 {
145	pinctrl-0 = <&scif2_pins>;
146	pinctrl-names = "default";
147
148	status = "okay";
149};
150
151&sdhi0 {
152	pinctrl-0 = <&sdhi0_pins>;
153	pinctrl-1 = <&sdhi0_pins_uhs>;
154	pinctrl-names = "default", "state_uhs";
155
156	vmmc-supply = <&vcc_sdhi0>;
157	vqmmc-supply = <&vccq_sdhi0>;
158	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
159	bus-width = <4>;
160	sd-uhs-sdr50;
161	sd-uhs-sdr104;
162	status = "okay";
163};
164
165&usb2_phy0 {
166	renesas,no-otg-pins;
167	status = "okay";
168};
169