1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11#include <dt-bindings/power/r8a774a1-sysc.h>
12
13/ {
14	compatible = "renesas,r8a774a1";
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		i2c0 = &i2c0;
20		i2c1 = &i2c1;
21		i2c2 = &i2c2;
22		i2c3 = &i2c3;
23		i2c4 = &i2c4;
24		i2c5 = &i2c5;
25		i2c6 = &i2c6;
26		i2c7 = &i2c_dvfs;
27	};
28
29	/*
30	 * The external audio clocks are configured as 0 Hz fixed frequency
31	 * clocks by default.
32	 * Boards that provide audio clocks should override them.
33	 */
34	audio_clk_a: audio_clk_a {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <0>;
38	};
39
40	audio_clk_b: audio_clk_b {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <0>;
44	};
45
46	audio_clk_c: audio_clk_c {
47		compatible = "fixed-clock";
48		#clock-cells = <0>;
49		clock-frequency = <0>;
50	};
51
52	/* External CAN clock - to be overridden by boards that provide it */
53	can_clk: can {
54		compatible = "fixed-clock";
55		#clock-cells = <0>;
56		clock-frequency = <0>;
57	};
58
59	cpus {
60		#address-cells = <1>;
61		#size-cells = <0>;
62
63		a57_0: cpu@0 {
64			compatible = "arm,cortex-a57", "arm,armv8";
65			reg = <0x0>;
66			device_type = "cpu";
67			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
68			next-level-cache = <&L2_CA57>;
69			enable-method = "psci";
70			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
71		};
72
73		a57_1: cpu@1 {
74			compatible = "arm,cortex-a57", "arm,armv8";
75			reg = <0x1>;
76			device_type = "cpu";
77			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
78			next-level-cache = <&L2_CA57>;
79			enable-method = "psci";
80			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
81		};
82
83		a53_0: cpu@100 {
84			compatible = "arm,cortex-a53", "arm,armv8";
85			reg = <0x100>;
86			device_type = "cpu";
87			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
88			next-level-cache = <&L2_CA53>;
89			enable-method = "psci";
90			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
91		};
92
93		a53_1: cpu@101 {
94			compatible = "arm,cortex-a53", "arm,armv8";
95			reg = <0x101>;
96			device_type = "cpu";
97			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
98			next-level-cache = <&L2_CA53>;
99			enable-method = "psci";
100			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
101		};
102
103		a53_2: cpu@102 {
104			compatible = "arm,cortex-a53", "arm,armv8";
105			reg = <0x102>;
106			device_type = "cpu";
107			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
108			next-level-cache = <&L2_CA53>;
109			enable-method = "psci";
110			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
111		};
112
113		a53_3: cpu@103 {
114			compatible = "arm,cortex-a53", "arm,armv8";
115			reg = <0x103>;
116			device_type = "cpu";
117			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
118			next-level-cache = <&L2_CA53>;
119			enable-method = "psci";
120			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
121		};
122
123		L2_CA57: cache-controller-0 {
124			compatible = "cache";
125			power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
126			cache-unified;
127			cache-level = <2>;
128		};
129
130		L2_CA53: cache-controller-1 {
131			compatible = "cache";
132			power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
133			cache-unified;
134			cache-level = <2>;
135		};
136	};
137
138	extal_clk: extal {
139		compatible = "fixed-clock";
140		#clock-cells = <0>;
141		/* This value must be overridden by the board */
142		clock-frequency = <0>;
143	};
144
145	extalr_clk: extalr {
146		compatible = "fixed-clock";
147		#clock-cells = <0>;
148		/* This value must be overridden by the board */
149		clock-frequency = <0>;
150	};
151
152	/* External PCIe clock - can be overridden by the board */
153	pcie_bus_clk: pcie_bus {
154		compatible = "fixed-clock";
155		#clock-cells = <0>;
156		clock-frequency = <0>;
157	};
158
159	pmu_a53 {
160		compatible = "arm,cortex-a53-pmu";
161		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
162				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
163				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
164				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
165		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
166	};
167
168	pmu_a57 {
169		compatible = "arm,cortex-a57-pmu";
170		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
171				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
172		interrupt-affinity = <&a57_0>, <&a57_1>;
173	};
174
175	psci {
176		compatible = "arm,psci-1.0", "arm,psci-0.2";
177		method = "smc";
178	};
179
180	/* External SCIF clock - to be overridden by boards that provide it */
181	scif_clk: scif {
182		compatible = "fixed-clock";
183		#clock-cells = <0>;
184		clock-frequency = <0>;
185	};
186
187	soc {
188		compatible = "simple-bus";
189		interrupt-parent = <&gic>;
190		#address-cells = <2>;
191		#size-cells = <2>;
192		ranges;
193
194		rwdt: watchdog@e6020000 {
195			compatible = "renesas,r8a774a1-wdt",
196				     "renesas,rcar-gen3-wdt";
197			reg = <0 0xe6020000 0 0x0c>;
198			clocks = <&cpg CPG_MOD 402>;
199			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
200			resets = <&cpg 402>;
201			status = "disabled";
202		};
203
204		gpio0: gpio@e6050000 {
205			compatible = "renesas,gpio-r8a774a1",
206				     "renesas,rcar-gen3-gpio";
207			reg = <0 0xe6050000 0 0x50>;
208			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
209			#gpio-cells = <2>;
210			gpio-controller;
211			gpio-ranges = <&pfc 0 0 16>;
212			#interrupt-cells = <2>;
213			interrupt-controller;
214			clocks = <&cpg CPG_MOD 912>;
215			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
216			resets = <&cpg 912>;
217		};
218
219		gpio1: gpio@e6051000 {
220			compatible = "renesas,gpio-r8a774a1",
221				     "renesas,rcar-gen3-gpio";
222			reg = <0 0xe6051000 0 0x50>;
223			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
224			#gpio-cells = <2>;
225			gpio-controller;
226			gpio-ranges = <&pfc 0 32 29>;
227			#interrupt-cells = <2>;
228			interrupt-controller;
229			clocks = <&cpg CPG_MOD 911>;
230			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
231			resets = <&cpg 911>;
232		};
233
234		gpio2: gpio@e6052000 {
235			compatible = "renesas,gpio-r8a774a1",
236				     "renesas,rcar-gen3-gpio";
237			reg = <0 0xe6052000 0 0x50>;
238			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
239			#gpio-cells = <2>;
240			gpio-controller;
241			gpio-ranges = <&pfc 0 64 15>;
242			#interrupt-cells = <2>;
243			interrupt-controller;
244			clocks = <&cpg CPG_MOD 910>;
245			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
246			resets = <&cpg 910>;
247		};
248
249		gpio3: gpio@e6053000 {
250			compatible = "renesas,gpio-r8a774a1",
251				     "renesas,rcar-gen3-gpio";
252			reg = <0 0xe6053000 0 0x50>;
253			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
254			#gpio-cells = <2>;
255			gpio-controller;
256			gpio-ranges = <&pfc 0 96 16>;
257			#interrupt-cells = <2>;
258			interrupt-controller;
259			clocks = <&cpg CPG_MOD 909>;
260			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
261			resets = <&cpg 909>;
262		};
263
264		gpio4: gpio@e6054000 {
265			compatible = "renesas,gpio-r8a774a1",
266				     "renesas,rcar-gen3-gpio";
267			reg = <0 0xe6054000 0 0x50>;
268			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
269			#gpio-cells = <2>;
270			gpio-controller;
271			gpio-ranges = <&pfc 0 128 18>;
272			#interrupt-cells = <2>;
273			interrupt-controller;
274			clocks = <&cpg CPG_MOD 908>;
275			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
276			resets = <&cpg 908>;
277		};
278
279		gpio5: gpio@e6055000 {
280			compatible = "renesas,gpio-r8a774a1",
281				     "renesas,rcar-gen3-gpio";
282			reg = <0 0xe6055000 0 0x50>;
283			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
284			#gpio-cells = <2>;
285			gpio-controller;
286			gpio-ranges = <&pfc 0 160 26>;
287			#interrupt-cells = <2>;
288			interrupt-controller;
289			clocks = <&cpg CPG_MOD 907>;
290			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
291			resets = <&cpg 907>;
292		};
293
294		gpio6: gpio@e6055400 {
295			compatible = "renesas,gpio-r8a774a1",
296				     "renesas,rcar-gen3-gpio";
297			reg = <0 0xe6055400 0 0x50>;
298			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
299			#gpio-cells = <2>;
300			gpio-controller;
301			gpio-ranges = <&pfc 0 192 32>;
302			#interrupt-cells = <2>;
303			interrupt-controller;
304			clocks = <&cpg CPG_MOD 906>;
305			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
306			resets = <&cpg 906>;
307		};
308
309		gpio7: gpio@e6055800 {
310			compatible = "renesas,gpio-r8a774a1",
311				     "renesas,rcar-gen3-gpio";
312			reg = <0 0xe6055800 0 0x50>;
313			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
314			#gpio-cells = <2>;
315			gpio-controller;
316			gpio-ranges = <&pfc 0 224 4>;
317			#interrupt-cells = <2>;
318			interrupt-controller;
319			clocks = <&cpg CPG_MOD 905>;
320			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
321			resets = <&cpg 905>;
322		};
323
324		pfc: pin-controller@e6060000 {
325			compatible = "renesas,pfc-r8a774a1";
326			reg = <0 0xe6060000 0 0x50c>;
327		};
328
329		cpg: clock-controller@e6150000 {
330			compatible = "renesas,r8a774a1-cpg-mssr";
331			reg = <0 0xe6150000 0 0x0bb0>;
332			clocks = <&extal_clk>, <&extalr_clk>;
333			clock-names = "extal", "extalr";
334			#clock-cells = <2>;
335			#power-domain-cells = <0>;
336			#reset-cells = <1>;
337		};
338
339		rst: reset-controller@e6160000 {
340			compatible = "renesas,r8a774a1-rst";
341			reg = <0 0xe6160000 0 0x018c>;
342		};
343
344		sysc: system-controller@e6180000 {
345			compatible = "renesas,r8a774a1-sysc";
346			reg = <0 0xe6180000 0 0x0400>;
347			#power-domain-cells = <1>;
348		};
349
350		tsc: thermal@e6198000 {
351			compatible = "renesas,r8a774a1-thermal";
352			reg = <0 0xe6198000 0 0x100>,
353			      <0 0xe61a0000 0 0x100>,
354			      <0 0xe61a8000 0 0x100>;
355			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
356				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
357				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
358			clocks = <&cpg CPG_MOD 522>;
359			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
360			resets = <&cpg 522>;
361			#thermal-sensor-cells = <1>;
362		};
363
364		intc_ex: interrupt-controller@e61c0000 {
365			compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
366			#interrupt-cells = <2>;
367			interrupt-controller;
368			reg = <0 0xe61c0000 0 0x200>;
369			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
370				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
371				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
372				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
373				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
374				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
375			clocks = <&cpg CPG_MOD 407>;
376			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
377			resets = <&cpg 407>;
378		};
379
380		i2c0: i2c@e6500000 {
381			#address-cells = <1>;
382			#size-cells = <0>;
383			compatible = "renesas,i2c-r8a774a1",
384				     "renesas,rcar-gen3-i2c";
385			reg = <0 0xe6500000 0 0x40>;
386			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
387			clocks = <&cpg CPG_MOD 931>;
388			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
389			resets = <&cpg 931>;
390			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
391			       <&dmac2 0x91>, <&dmac2 0x90>;
392			dma-names = "tx", "rx", "tx", "rx";
393			i2c-scl-internal-delay-ns = <110>;
394			status = "disabled";
395		};
396
397		i2c1: i2c@e6508000 {
398			#address-cells = <1>;
399			#size-cells = <0>;
400			compatible = "renesas,i2c-r8a774a1",
401				     "renesas,rcar-gen3-i2c";
402			reg = <0 0xe6508000 0 0x40>;
403			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
404			clocks = <&cpg CPG_MOD 930>;
405			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
406			resets = <&cpg 930>;
407			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
408			       <&dmac2 0x93>, <&dmac2 0x92>;
409			dma-names = "tx", "rx", "tx", "rx";
410			i2c-scl-internal-delay-ns = <6>;
411			status = "disabled";
412		};
413
414		i2c2: i2c@e6510000 {
415			#address-cells = <1>;
416			#size-cells = <0>;
417			compatible = "renesas,i2c-r8a774a1",
418				     "renesas,rcar-gen3-i2c";
419			reg = <0 0xe6510000 0 0x40>;
420			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
421			clocks = <&cpg CPG_MOD 929>;
422			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
423			resets = <&cpg 929>;
424			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
425			       <&dmac2 0x95>, <&dmac2 0x94>;
426			dma-names = "tx", "rx", "tx", "rx";
427			i2c-scl-internal-delay-ns = <6>;
428			status = "disabled";
429		};
430
431		i2c3: i2c@e66d0000 {
432			#address-cells = <1>;
433			#size-cells = <0>;
434			compatible = "renesas,i2c-r8a774a1",
435				     "renesas,rcar-gen3-i2c";
436			reg = <0 0xe66d0000 0 0x40>;
437			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
438			clocks = <&cpg CPG_MOD 928>;
439			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
440			resets = <&cpg 928>;
441			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
442			dma-names = "tx", "rx";
443			i2c-scl-internal-delay-ns = <110>;
444			status = "disabled";
445		};
446
447		i2c4: i2c@e66d8000 {
448			#address-cells = <1>;
449			#size-cells = <0>;
450			compatible = "renesas,i2c-r8a774a1",
451				     "renesas,rcar-gen3-i2c";
452			reg = <0 0xe66d8000 0 0x40>;
453			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
454			clocks = <&cpg CPG_MOD 927>;
455			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
456			resets = <&cpg 927>;
457			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
458			dma-names = "tx", "rx";
459			i2c-scl-internal-delay-ns = <110>;
460			status = "disabled";
461		};
462
463		i2c5: i2c@e66e0000 {
464			#address-cells = <1>;
465			#size-cells = <0>;
466			compatible = "renesas,i2c-r8a774a1",
467				     "renesas,rcar-gen3-i2c";
468			reg = <0 0xe66e0000 0 0x40>;
469			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
470			clocks = <&cpg CPG_MOD 919>;
471			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
472			resets = <&cpg 919>;
473			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
474			dma-names = "tx", "rx";
475			i2c-scl-internal-delay-ns = <110>;
476			status = "disabled";
477		};
478
479		i2c6: i2c@e66e8000 {
480			#address-cells = <1>;
481			#size-cells = <0>;
482			compatible = "renesas,i2c-r8a774a1",
483				     "renesas,rcar-gen3-i2c";
484			reg = <0 0xe66e8000 0 0x40>;
485			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
486			clocks = <&cpg CPG_MOD 918>;
487			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
488			resets = <&cpg 918>;
489			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
490			dma-names = "tx", "rx";
491			i2c-scl-internal-delay-ns = <6>;
492			status = "disabled";
493		};
494
495		i2c_dvfs: i2c@e60b0000 {
496			#address-cells = <1>;
497			#size-cells = <0>;
498			compatible = "renesas,iic-r8a774a1",
499				     "renesas,rcar-gen3-iic",
500				     "renesas,rmobile-iic";
501			reg = <0 0xe60b0000 0 0x425>;
502			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
503			clocks = <&cpg CPG_MOD 926>;
504			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
505			resets = <&cpg 926>;
506			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
507			dma-names = "tx", "rx";
508			status = "disabled";
509		};
510
511		hscif0: serial@e6540000 {
512			compatible = "renesas,hscif-r8a774a1",
513				     "renesas,rcar-gen3-hscif",
514				     "renesas,hscif";
515			reg = <0 0xe6540000 0 0x60>;
516			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
517			clocks = <&cpg CPG_MOD 520>,
518				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
519				 <&scif_clk>;
520			clock-names = "fck", "brg_int", "scif_clk";
521			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
522			       <&dmac2 0x31>, <&dmac2 0x30>;
523			dma-names = "tx", "rx", "tx", "rx";
524			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
525			resets = <&cpg 520>;
526			status = "disabled";
527		};
528
529		hscif1: serial@e6550000 {
530			compatible = "renesas,hscif-r8a774a1",
531				     "renesas,rcar-gen3-hscif",
532				     "renesas,hscif";
533			reg = <0 0xe6550000 0 0x60>;
534			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
535			clocks = <&cpg CPG_MOD 519>,
536				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
537				 <&scif_clk>;
538			clock-names = "fck", "brg_int", "scif_clk";
539			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
540			       <&dmac2 0x33>, <&dmac2 0x32>;
541			dma-names = "tx", "rx", "tx", "rx";
542			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
543			resets = <&cpg 519>;
544			status = "disabled";
545		};
546
547		hscif2: serial@e6560000 {
548			compatible = "renesas,hscif-r8a774a1",
549				     "renesas,rcar-gen3-hscif",
550				     "renesas,hscif";
551			reg = <0 0xe6560000 0 0x60>;
552			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
553			clocks = <&cpg CPG_MOD 518>,
554				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
555				 <&scif_clk>;
556			clock-names = "fck", "brg_int", "scif_clk";
557			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
558			       <&dmac2 0x35>, <&dmac2 0x34>;
559			dma-names = "tx", "rx", "tx", "rx";
560			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
561			resets = <&cpg 518>;
562			status = "disabled";
563		};
564
565		hscif3: serial@e66a0000 {
566			compatible = "renesas,hscif-r8a774a1",
567				     "renesas,rcar-gen3-hscif",
568				     "renesas,hscif";
569			reg = <0 0xe66a0000 0 0x60>;
570			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
571			clocks = <&cpg CPG_MOD 517>,
572				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
573				 <&scif_clk>;
574			clock-names = "fck", "brg_int", "scif_clk";
575			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
576			dma-names = "tx", "rx";
577			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
578			resets = <&cpg 517>;
579			status = "disabled";
580		};
581
582		hscif4: serial@e66b0000 {
583			compatible = "renesas,hscif-r8a774a1",
584				     "renesas,rcar-gen3-hscif",
585				     "renesas,hscif";
586			reg = <0 0xe66b0000 0 0x60>;
587			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
588			clocks = <&cpg CPG_MOD 516>,
589				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
590				 <&scif_clk>;
591			clock-names = "fck", "brg_int", "scif_clk";
592			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
593			dma-names = "tx", "rx";
594			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
595			resets = <&cpg 516>;
596			status = "disabled";
597		};
598
599		hsusb: usb@e6590000 {
600			compatible = "renesas,usbhs-r8a774a1",
601				     "renesas,rcar-gen3-usbhs";
602			reg = <0 0xe6590000 0 0x100>;
603			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
604			clocks = <&cpg CPG_MOD 704>;
605			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
606			       <&usb_dmac1 0>, <&usb_dmac1 1>;
607			dma-names = "ch0", "ch1", "ch2", "ch3";
608			renesas,buswait = <11>;
609			phys = <&usb2_phy0>;
610			phy-names = "usb";
611			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
612			resets = <&cpg 704>;
613			status = "disabled";
614		};
615
616		usb_dmac0: dma-controller@e65a0000 {
617			compatible = "renesas,r8a774a1-usb-dmac",
618				     "renesas,usb-dmac";
619			reg = <0 0xe65a0000 0 0x100>;
620			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
621				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
622			interrupt-names = "ch0", "ch1";
623			clocks = <&cpg CPG_MOD 330>;
624			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
625			resets = <&cpg 330>;
626			#dma-cells = <1>;
627			dma-channels = <2>;
628		};
629
630		usb_dmac1: dma-controller@e65b0000 {
631			compatible = "renesas,r8a774a1-usb-dmac",
632				     "renesas,usb-dmac";
633			reg = <0 0xe65b0000 0 0x100>;
634			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
635				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
636			interrupt-names = "ch0", "ch1";
637			clocks = <&cpg CPG_MOD 331>;
638			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
639			resets = <&cpg 331>;
640			#dma-cells = <1>;
641			dma-channels = <2>;
642		};
643
644		usb3_phy0: usb-phy@e65ee000 {
645			compatible = "renesas,r8a774a1-usb3-phy",
646				     "renesas,rcar-gen3-usb3-phy";
647			reg = <0 0xe65ee000 0 0x90>;
648			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
649				 <&usb_extal_clk>;
650			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
651			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
652			resets = <&cpg 328>;
653			#phy-cells = <0>;
654			status = "disabled";
655		};
656
657		dmac0: dma-controller@e6700000 {
658			compatible = "renesas,dmac-r8a774a1",
659				     "renesas,rcar-dmac";
660			reg = <0 0xe6700000 0 0x10000>;
661			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
662				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
663				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
664				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
665				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
666				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
667				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
668				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
669				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
670				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
671				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
672				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
673				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
674				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
675				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
676				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
677				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
678			interrupt-names = "error",
679					"ch0", "ch1", "ch2", "ch3",
680					"ch4", "ch5", "ch6", "ch7",
681					"ch8", "ch9", "ch10", "ch11",
682					"ch12", "ch13", "ch14", "ch15";
683			clocks = <&cpg CPG_MOD 219>;
684			clock-names = "fck";
685			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
686			resets = <&cpg 219>;
687			#dma-cells = <1>;
688			dma-channels = <16>;
689		};
690
691		dmac1: dma-controller@e7300000 {
692			compatible = "renesas,dmac-r8a774a1",
693				     "renesas,rcar-dmac";
694			reg = <0 0xe7300000 0 0x10000>;
695			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
696				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
697				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
698				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
699				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
700				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
701				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
702				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
703				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
704				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
705				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
706				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
707				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
708				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
709				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
710				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
711				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
712			interrupt-names = "error",
713					"ch0", "ch1", "ch2", "ch3",
714					"ch4", "ch5", "ch6", "ch7",
715					"ch8", "ch9", "ch10", "ch11",
716					"ch12", "ch13", "ch14", "ch15";
717			clocks = <&cpg CPG_MOD 218>;
718			clock-names = "fck";
719			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
720			resets = <&cpg 218>;
721			#dma-cells = <1>;
722			dma-channels = <16>;
723		};
724
725		dmac2: dma-controller@e7310000 {
726			compatible = "renesas,dmac-r8a774a1",
727				     "renesas,rcar-dmac";
728			reg = <0 0xe7310000 0 0x10000>;
729			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
730				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
731				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
732				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
733				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
734				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
735				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
736				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
737				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
738				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
739				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
740				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
741				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
742				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
743				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
744				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
745				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
746			interrupt-names = "error",
747					"ch0", "ch1", "ch2", "ch3",
748					"ch4", "ch5", "ch6", "ch7",
749					"ch8", "ch9", "ch10", "ch11",
750					"ch12", "ch13", "ch14", "ch15";
751			clocks = <&cpg CPG_MOD 217>;
752			clock-names = "fck";
753			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
754			resets = <&cpg 217>;
755			#dma-cells = <1>;
756			dma-channels = <16>;
757		};
758
759		ipmmu_ds0: mmu@e6740000 {
760			compatible = "renesas,ipmmu-r8a774a1";
761			reg = <0 0xe6740000 0 0x1000>;
762			renesas,ipmmu-main = <&ipmmu_mm 0>;
763			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
764			#iommu-cells = <1>;
765		};
766
767		ipmmu_ds1: mmu@e7740000 {
768			compatible = "renesas,ipmmu-r8a774a1";
769			reg = <0 0xe7740000 0 0x1000>;
770			renesas,ipmmu-main = <&ipmmu_mm 1>;
771			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
772			#iommu-cells = <1>;
773		};
774
775		ipmmu_hc: mmu@e6570000 {
776			compatible = "renesas,ipmmu-r8a774a1";
777			reg = <0 0xe6570000 0 0x1000>;
778			renesas,ipmmu-main = <&ipmmu_mm 2>;
779			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
780			#iommu-cells = <1>;
781		};
782
783		ipmmu_mm: mmu@e67b0000 {
784			compatible = "renesas,ipmmu-r8a774a1";
785			reg = <0 0xe67b0000 0 0x1000>;
786			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
787				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
788			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
789			#iommu-cells = <1>;
790		};
791
792		ipmmu_mp: mmu@ec670000 {
793			compatible = "renesas,ipmmu-r8a774a1";
794			reg = <0 0xec670000 0 0x1000>;
795			renesas,ipmmu-main = <&ipmmu_mm 4>;
796			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
797			#iommu-cells = <1>;
798		};
799
800		ipmmu_pv0: mmu@fd800000 {
801			compatible = "renesas,ipmmu-r8a774a1";
802			reg = <0 0xfd800000 0 0x1000>;
803			renesas,ipmmu-main = <&ipmmu_mm 5>;
804			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
805			#iommu-cells = <1>;
806		};
807
808		ipmmu_pv1: mmu@fd950000 {
809			compatible = "renesas,ipmmu-r8a774a1";
810			reg = <0 0xfd950000 0 0x1000>;
811			renesas,ipmmu-main = <&ipmmu_mm 6>;
812			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
813			#iommu-cells = <1>;
814		};
815
816		ipmmu_vc0: mmu@fe6b0000 {
817			compatible = "renesas,ipmmu-r8a774a1";
818			reg = <0 0xfe6b0000 0 0x1000>;
819			renesas,ipmmu-main = <&ipmmu_mm 8>;
820			power-domains = <&sysc R8A774A1_PD_A3VC>;
821			#iommu-cells = <1>;
822		};
823
824		ipmmu_vi0: mmu@febd0000 {
825			compatible = "renesas,ipmmu-r8a774a1";
826			reg = <0 0xfebd0000 0 0x1000>;
827			renesas,ipmmu-main = <&ipmmu_mm 9>;
828			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
829			#iommu-cells = <1>;
830		};
831
832		avb: ethernet@e6800000 {
833			compatible = "renesas,etheravb-r8a774a1",
834				     "renesas,etheravb-rcar-gen3";
835			reg = <0 0xe6800000 0 0x800>;
836			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
837				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
838				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
839				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
840				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
841				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
842				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
843				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
844				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
845				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
846				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
847				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
848				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
849				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
850				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
851				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
852				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
853				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
854				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
855				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
856				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
857				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
858				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
859				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
860				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
861			interrupt-names = "ch0", "ch1", "ch2", "ch3",
862					  "ch4", "ch5", "ch6", "ch7",
863					  "ch8", "ch9", "ch10", "ch11",
864					  "ch12", "ch13", "ch14", "ch15",
865					  "ch16", "ch17", "ch18", "ch19",
866					  "ch20", "ch21", "ch22", "ch23",
867					  "ch24";
868			clocks = <&cpg CPG_MOD 812>;
869			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
870			resets = <&cpg 812>;
871			phy-mode = "rgmii";
872			#address-cells = <1>;
873			#size-cells = <0>;
874			status = "disabled";
875		};
876
877		can0: can@e6c30000 {
878			compatible = "renesas,can-r8a774a1",
879				     "renesas,rcar-gen3-can";
880			reg = <0 0xe6c30000 0 0x1000>;
881			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
882			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
883			clock-names = "clkp1", "can_clk";
884			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
885			resets = <&cpg 916>;
886			status = "disabled";
887		};
888
889		can1: can@e6c38000 {
890			compatible = "renesas,can-r8a774a1",
891				     "renesas,rcar-gen3-can";
892			reg = <0 0xe6c38000 0 0x1000>;
893			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
894			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
895			clock-names = "clkp1", "can_clk";
896			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
897			resets = <&cpg 915>;
898			status = "disabled";
899		};
900
901		pwm0: pwm@e6e30000 {
902			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
903			reg = <0 0xe6e30000 0 0x8>;
904			#pwm-cells = <2>;
905			clocks = <&cpg CPG_MOD 523>;
906			resets = <&cpg 523>;
907			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
908			status = "disabled";
909		};
910
911		pwm1: pwm@e6e31000 {
912			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
913			reg = <0 0xe6e31000 0 0x8>;
914			#pwm-cells = <2>;
915			clocks = <&cpg CPG_MOD 523>;
916			resets = <&cpg 523>;
917			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
918			status = "disabled";
919		};
920
921		pwm2: pwm@e6e32000 {
922			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
923			reg = <0 0xe6e32000 0 0x8>;
924			#pwm-cells = <2>;
925			clocks = <&cpg CPG_MOD 523>;
926			resets = <&cpg 523>;
927			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
928			status = "disabled";
929		};
930
931		pwm3: pwm@e6e33000 {
932			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
933			reg = <0 0xe6e33000 0 0x8>;
934			#pwm-cells = <2>;
935			clocks = <&cpg CPG_MOD 523>;
936			resets = <&cpg 523>;
937			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
938			status = "disabled";
939		};
940
941		pwm4: pwm@e6e34000 {
942			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
943			reg = <0 0xe6e34000 0 0x8>;
944			#pwm-cells = <2>;
945			clocks = <&cpg CPG_MOD 523>;
946			resets = <&cpg 523>;
947			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
948			status = "disabled";
949		};
950
951		pwm5: pwm@e6e35000 {
952			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
953			reg = <0 0xe6e35000 0 0x8>;
954			#pwm-cells = <2>;
955			clocks = <&cpg CPG_MOD 523>;
956			resets = <&cpg 523>;
957			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
958			status = "disabled";
959		};
960
961		pwm6: pwm@e6e36000 {
962			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
963			reg = <0 0xe6e36000 0 0x8>;
964			#pwm-cells = <2>;
965			clocks = <&cpg CPG_MOD 523>;
966			resets = <&cpg 523>;
967			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
968			status = "disabled";
969		};
970
971		scif0: serial@e6e60000 {
972			compatible = "renesas,scif-r8a774a1",
973				     "renesas,rcar-gen3-scif", "renesas,scif";
974			reg = <0 0xe6e60000 0 0x40>;
975			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
976			clocks = <&cpg CPG_MOD 207>,
977				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
978				 <&scif_clk>;
979			clock-names = "fck", "brg_int", "scif_clk";
980			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
981			       <&dmac2 0x51>, <&dmac2 0x50>;
982			dma-names = "tx", "rx", "tx", "rx";
983			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
984			resets = <&cpg 207>;
985			status = "disabled";
986		};
987
988		scif1: serial@e6e68000 {
989			compatible = "renesas,scif-r8a774a1",
990				     "renesas,rcar-gen3-scif", "renesas,scif";
991			reg = <0 0xe6e68000 0 0x40>;
992			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
993			clocks = <&cpg CPG_MOD 206>,
994				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
995				 <&scif_clk>;
996			clock-names = "fck", "brg_int", "scif_clk";
997			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
998			       <&dmac2 0x53>, <&dmac2 0x52>;
999			dma-names = "tx", "rx", "tx", "rx";
1000			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1001			resets = <&cpg 206>;
1002			status = "disabled";
1003		};
1004
1005		scif2: serial@e6e88000 {
1006			compatible = "renesas,scif-r8a774a1",
1007				     "renesas,rcar-gen3-scif", "renesas,scif";
1008			reg = <0 0xe6e88000 0 0x40>;
1009			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1010			clocks = <&cpg CPG_MOD 310>,
1011				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1012				 <&scif_clk>;
1013			clock-names = "fck", "brg_int", "scif_clk";
1014			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1015			       <&dmac2 0x13>, <&dmac2 0x12>;
1016			dma-names = "tx", "rx", "tx", "rx";
1017			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1018			resets = <&cpg 310>;
1019			status = "disabled";
1020		};
1021
1022		scif3: serial@e6c50000 {
1023			compatible = "renesas,scif-r8a774a1",
1024				     "renesas,rcar-gen3-scif", "renesas,scif";
1025			reg = <0 0xe6c50000 0 0x40>;
1026			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1027			clocks = <&cpg CPG_MOD 204>,
1028				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1029				 <&scif_clk>;
1030			clock-names = "fck", "brg_int", "scif_clk";
1031			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1032			dma-names = "tx", "rx";
1033			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1034			resets = <&cpg 204>;
1035			status = "disabled";
1036		};
1037
1038		scif4: serial@e6c40000 {
1039			compatible = "renesas,scif-r8a774a1",
1040				     "renesas,rcar-gen3-scif", "renesas,scif";
1041			reg = <0 0xe6c40000 0 0x40>;
1042			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1043			clocks = <&cpg CPG_MOD 203>,
1044				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1045				 <&scif_clk>;
1046			clock-names = "fck", "brg_int", "scif_clk";
1047			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1048			dma-names = "tx", "rx";
1049			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1050			resets = <&cpg 203>;
1051			status = "disabled";
1052		};
1053
1054		scif5: serial@e6f30000 {
1055			compatible = "renesas,scif-r8a774a1",
1056				     "renesas,rcar-gen3-scif", "renesas,scif";
1057			reg = <0 0xe6f30000 0 0x40>;
1058			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1059			clocks = <&cpg CPG_MOD 202>,
1060				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1061				 <&scif_clk>;
1062			clock-names = "fck", "brg_int", "scif_clk";
1063			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1064			       <&dmac2 0x5b>, <&dmac2 0x5a>;
1065			dma-names = "tx", "rx", "tx", "rx";
1066			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1067			resets = <&cpg 202>;
1068			status = "disabled";
1069		};
1070
1071		msiof0: spi@e6e90000 {
1072			compatible = "renesas,msiof-r8a774a1",
1073				     "renesas,rcar-gen3-msiof";
1074			reg = <0 0xe6e90000 0 0x0064>;
1075			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1076			clocks = <&cpg CPG_MOD 211>;
1077			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1078			       <&dmac2 0x41>, <&dmac2 0x40>;
1079			dma-names = "tx", "rx", "tx", "rx";
1080			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1081			resets = <&cpg 211>;
1082			#address-cells = <1>;
1083			#size-cells = <0>;
1084			status = "disabled";
1085		};
1086
1087		msiof1: spi@e6ea0000 {
1088			compatible = "renesas,msiof-r8a774a1",
1089				     "renesas,rcar-gen3-msiof";
1090			reg = <0 0xe6ea0000 0 0x0064>;
1091			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1092			clocks = <&cpg CPG_MOD 210>;
1093			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1094			       <&dmac2 0x43>, <&dmac2 0x42>;
1095			dma-names = "tx", "rx", "tx", "rx";
1096			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1097			resets = <&cpg 210>;
1098			#address-cells = <1>;
1099			#size-cells = <0>;
1100			status = "disabled";
1101		};
1102
1103		msiof2: spi@e6c00000 {
1104			compatible = "renesas,msiof-r8a774a1",
1105				     "renesas,rcar-gen3-msiof";
1106			reg = <0 0xe6c00000 0 0x0064>;
1107			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1108			clocks = <&cpg CPG_MOD 209>;
1109			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1110			dma-names = "tx", "rx";
1111			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1112			resets = <&cpg 209>;
1113			#address-cells = <1>;
1114			#size-cells = <0>;
1115			status = "disabled";
1116		};
1117
1118		msiof3: spi@e6c10000 {
1119			compatible = "renesas,msiof-r8a774a1",
1120				     "renesas,rcar-gen3-msiof";
1121			reg = <0 0xe6c10000 0 0x0064>;
1122			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1123			clocks = <&cpg CPG_MOD 208>;
1124			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1125			dma-names = "tx", "rx";
1126			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1127			resets = <&cpg 208>;
1128			#address-cells = <1>;
1129			#size-cells = <0>;
1130			status = "disabled";
1131		};
1132
1133		vin0: video@e6ef0000 {
1134			compatible = "renesas,vin-r8a774a1";
1135			reg = <0 0xe6ef0000 0 0x1000>;
1136			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1137			clocks = <&cpg CPG_MOD 811>;
1138			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1139			resets = <&cpg 811>;
1140			renesas,id = <0>;
1141			status = "disabled";
1142
1143			ports {
1144				#address-cells = <1>;
1145				#size-cells = <0>;
1146
1147				port@1 {
1148					#address-cells = <1>;
1149					#size-cells = <0>;
1150
1151					reg = <1>;
1152
1153					vin0csi20: endpoint@0 {
1154						reg = <0>;
1155						remote-endpoint = <&csi20vin0>;
1156					};
1157					vin0csi40: endpoint@2 {
1158						reg = <2>;
1159						remote-endpoint = <&csi40vin0>;
1160					};
1161				};
1162			};
1163		};
1164
1165		vin1: video@e6ef1000 {
1166			compatible = "renesas,vin-r8a774a1";
1167			reg = <0 0xe6ef1000 0 0x1000>;
1168			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1169			clocks = <&cpg CPG_MOD 810>;
1170			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1171			resets = <&cpg 810>;
1172			renesas,id = <1>;
1173			status = "disabled";
1174
1175			ports {
1176				#address-cells = <1>;
1177				#size-cells = <0>;
1178
1179				port@1 {
1180					#address-cells = <1>;
1181					#size-cells = <0>;
1182
1183					reg = <1>;
1184
1185					vin1csi20: endpoint@0 {
1186						reg = <0>;
1187						remote-endpoint = <&csi20vin1>;
1188					};
1189					vin1csi40: endpoint@2 {
1190						reg = <2>;
1191						remote-endpoint = <&csi40vin1>;
1192					};
1193				};
1194			};
1195		};
1196
1197		vin2: video@e6ef2000 {
1198			compatible = "renesas,vin-r8a774a1";
1199			reg = <0 0xe6ef2000 0 0x1000>;
1200			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1201			clocks = <&cpg CPG_MOD 809>;
1202			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1203			resets = <&cpg 809>;
1204			renesas,id = <2>;
1205			status = "disabled";
1206
1207			ports {
1208				#address-cells = <1>;
1209				#size-cells = <0>;
1210
1211				port@1 {
1212					#address-cells = <1>;
1213					#size-cells = <0>;
1214
1215					reg = <1>;
1216
1217					vin2csi20: endpoint@0 {
1218						reg = <0>;
1219						remote-endpoint = <&csi20vin2>;
1220					};
1221					vin2csi40: endpoint@2 {
1222						reg = <2>;
1223						remote-endpoint = <&csi40vin2>;
1224					};
1225				};
1226			};
1227		};
1228
1229		vin3: video@e6ef3000 {
1230			compatible = "renesas,vin-r8a774a1";
1231			reg = <0 0xe6ef3000 0 0x1000>;
1232			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1233			clocks = <&cpg CPG_MOD 808>;
1234			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1235			resets = <&cpg 808>;
1236			renesas,id = <3>;
1237			status = "disabled";
1238
1239			ports {
1240				#address-cells = <1>;
1241				#size-cells = <0>;
1242
1243				port@1 {
1244					#address-cells = <1>;
1245					#size-cells = <0>;
1246
1247					reg = <1>;
1248
1249					vin3csi20: endpoint@0 {
1250						reg = <0>;
1251						remote-endpoint = <&csi20vin3>;
1252					};
1253					vin3csi40: endpoint@2 {
1254						reg = <2>;
1255						remote-endpoint = <&csi40vin3>;
1256					};
1257				};
1258			};
1259		};
1260
1261		vin4: video@e6ef4000 {
1262			compatible = "renesas,vin-r8a774a1";
1263			reg = <0 0xe6ef4000 0 0x1000>;
1264			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1265			clocks = <&cpg CPG_MOD 807>;
1266			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1267			resets = <&cpg 807>;
1268			renesas,id = <4>;
1269			status = "disabled";
1270
1271			ports {
1272				#address-cells = <1>;
1273				#size-cells = <0>;
1274
1275				port@1 {
1276					#address-cells = <1>;
1277					#size-cells = <0>;
1278
1279					reg = <1>;
1280
1281					vin4csi20: endpoint@0 {
1282						reg = <0>;
1283						remote-endpoint = <&csi20vin4>;
1284					};
1285					vin4csi40: endpoint@2 {
1286						reg = <2>;
1287						remote-endpoint = <&csi40vin4>;
1288					};
1289				};
1290			};
1291		};
1292
1293		vin5: video@e6ef5000 {
1294			compatible = "renesas,vin-r8a774a1";
1295			reg = <0 0xe6ef5000 0 0x1000>;
1296			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1297			clocks = <&cpg CPG_MOD 806>;
1298			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1299			resets = <&cpg 806>;
1300			renesas,id = <5>;
1301			status = "disabled";
1302
1303			ports {
1304				#address-cells = <1>;
1305				#size-cells = <0>;
1306
1307				port@1 {
1308					#address-cells = <1>;
1309					#size-cells = <0>;
1310
1311					reg = <1>;
1312
1313					vin5csi20: endpoint@0 {
1314						reg = <0>;
1315						remote-endpoint = <&csi20vin5>;
1316					};
1317					vin5csi40: endpoint@2 {
1318						reg = <2>;
1319						remote-endpoint = <&csi40vin5>;
1320					};
1321				};
1322			};
1323		};
1324
1325		vin6: video@e6ef6000 {
1326			compatible = "renesas,vin-r8a774a1";
1327			reg = <0 0xe6ef6000 0 0x1000>;
1328			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1329			clocks = <&cpg CPG_MOD 805>;
1330			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1331			resets = <&cpg 805>;
1332			renesas,id = <6>;
1333			status = "disabled";
1334
1335			ports {
1336				#address-cells = <1>;
1337				#size-cells = <0>;
1338
1339				port@1 {
1340					#address-cells = <1>;
1341					#size-cells = <0>;
1342
1343					reg = <1>;
1344
1345					vin6csi20: endpoint@0 {
1346						reg = <0>;
1347						remote-endpoint = <&csi20vin6>;
1348					};
1349					vin6csi40: endpoint@2 {
1350						reg = <2>;
1351						remote-endpoint = <&csi40vin6>;
1352					};
1353				};
1354			};
1355		};
1356
1357		vin7: video@e6ef7000 {
1358			compatible = "renesas,vin-r8a774a1";
1359			reg = <0 0xe6ef7000 0 0x1000>;
1360			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1361			clocks = <&cpg CPG_MOD 804>;
1362			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1363			resets = <&cpg 804>;
1364			renesas,id = <7>;
1365			status = "disabled";
1366
1367			ports {
1368				#address-cells = <1>;
1369				#size-cells = <0>;
1370
1371				port@1 {
1372					#address-cells = <1>;
1373					#size-cells = <0>;
1374
1375					reg = <1>;
1376
1377					vin7csi20: endpoint@0 {
1378						reg = <0>;
1379						remote-endpoint = <&csi20vin7>;
1380					};
1381					vin7csi40: endpoint@2 {
1382						reg = <2>;
1383						remote-endpoint = <&csi40vin7>;
1384					};
1385				};
1386			};
1387		};
1388
1389		rcar_sound: sound@ec500000 {
1390			/*
1391			 * #sound-dai-cells is required
1392			 *
1393			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
1394			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
1395			 */
1396			/*
1397			 * #clock-cells is required for audio_clkout0/1/2/3
1398			 *
1399			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
1400			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
1401			 */
1402			compatible =  "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1403			reg =	<0 0xec500000 0 0x1000>, /* SCU */
1404				<0 0xec5a0000 0 0x100>,  /* ADG */
1405				<0 0xec540000 0 0x1000>, /* SSIU */
1406				<0 0xec541000 0 0x280>,  /* SSI */
1407				<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1408			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1409
1410			clocks = <&cpg CPG_MOD 1005>,
1411				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1412				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1413				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1414				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1415				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1416				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1417				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1418				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1419				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1420				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1421				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1422				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1423				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1424				 <&audio_clk_a>, <&audio_clk_b>,
1425				 <&audio_clk_c>,
1426				 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
1427			clock-names = "ssi-all",
1428				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1429				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1430				      "ssi.1", "ssi.0",
1431				      "src.9", "src.8", "src.7", "src.6",
1432				      "src.5", "src.4", "src.3", "src.2",
1433				      "src.1", "src.0",
1434				      "mix.1", "mix.0",
1435				      "ctu.1", "ctu.0",
1436				      "dvc.0", "dvc.1",
1437				      "clk_a", "clk_b", "clk_c", "clk_i";
1438			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1439			resets = <&cpg 1005>,
1440				 <&cpg 1006>, <&cpg 1007>,
1441				 <&cpg 1008>, <&cpg 1009>,
1442				 <&cpg 1010>, <&cpg 1011>,
1443				 <&cpg 1012>, <&cpg 1013>,
1444				 <&cpg 1014>, <&cpg 1015>;
1445			reset-names = "ssi-all",
1446				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1447				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1448				      "ssi.1", "ssi.0";
1449			status = "disabled";
1450
1451			rcar_sound,dvc {
1452				dvc0: dvc-0 {
1453					dmas = <&audma1 0xbc>;
1454					dma-names = "tx";
1455				};
1456				dvc1: dvc-1 {
1457					dmas = <&audma1 0xbe>;
1458					dma-names = "tx";
1459				};
1460			};
1461
1462			rcar_sound,mix {
1463				mix0: mix-0 { };
1464				mix1: mix-1 { };
1465			};
1466
1467			rcar_sound,ctu {
1468				ctu00: ctu-0 { };
1469				ctu01: ctu-1 { };
1470				ctu02: ctu-2 { };
1471				ctu03: ctu-3 { };
1472				ctu10: ctu-4 { };
1473				ctu11: ctu-5 { };
1474				ctu12: ctu-6 { };
1475				ctu13: ctu-7 { };
1476			};
1477
1478			rcar_sound,src {
1479				src0: src-0 {
1480					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1481					dmas = <&audma0 0x85>, <&audma1 0x9a>;
1482					dma-names = "rx", "tx";
1483				};
1484				src1: src-1 {
1485					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1486					dmas = <&audma0 0x87>, <&audma1 0x9c>;
1487					dma-names = "rx", "tx";
1488				};
1489				src2: src-2 {
1490					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1491					dmas = <&audma0 0x89>, <&audma1 0x9e>;
1492					dma-names = "rx", "tx";
1493				};
1494				src3: src-3 {
1495					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1496					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1497					dma-names = "rx", "tx";
1498				};
1499				src4: src-4 {
1500					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1501					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1502					dma-names = "rx", "tx";
1503				};
1504				src5: src-5 {
1505					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1506					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1507					dma-names = "rx", "tx";
1508				};
1509				src6: src-6 {
1510					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1511					dmas = <&audma0 0x91>, <&audma1 0xb4>;
1512					dma-names = "rx", "tx";
1513				};
1514				src7: src-7 {
1515					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1516					dmas = <&audma0 0x93>, <&audma1 0xb6>;
1517					dma-names = "rx", "tx";
1518				};
1519				src8: src-8 {
1520					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1521					dmas = <&audma0 0x95>, <&audma1 0xb8>;
1522					dma-names = "rx", "tx";
1523				};
1524				src9: src-9 {
1525					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1526					dmas = <&audma0 0x97>, <&audma1 0xba>;
1527					dma-names = "rx", "tx";
1528				};
1529			};
1530
1531			rcar_sound,ssi {
1532				ssi0: ssi-0 {
1533					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1534					dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1535					dma-names = "rx", "tx", "rxu", "txu";
1536				};
1537				ssi1: ssi-1 {
1538					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1539					dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1540					dma-names = "rx", "tx", "rxu", "txu";
1541				};
1542				ssi2: ssi-2 {
1543					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1544					dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1545					dma-names = "rx", "tx", "rxu", "txu";
1546				};
1547				ssi3: ssi-3 {
1548					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1549					dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1550					dma-names = "rx", "tx", "rxu", "txu";
1551				};
1552				ssi4: ssi-4 {
1553					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1554					dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1555					dma-names = "rx", "tx", "rxu", "txu";
1556				};
1557				ssi5: ssi-5 {
1558					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1559					dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1560					dma-names = "rx", "tx", "rxu", "txu";
1561				};
1562				ssi6: ssi-6 {
1563					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1564					dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1565					dma-names = "rx", "tx", "rxu", "txu";
1566				};
1567				ssi7: ssi-7 {
1568					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1569					dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1570					dma-names = "rx", "tx", "rxu", "txu";
1571				};
1572				ssi8: ssi-8 {
1573					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1574					dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1575					dma-names = "rx", "tx", "rxu", "txu";
1576				};
1577				ssi9: ssi-9 {
1578					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1579					dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1580					dma-names = "rx", "tx", "rxu", "txu";
1581				};
1582			};
1583
1584			ports {
1585				#address-cells = <1>;
1586				#size-cells = <0>;
1587				port@0 {
1588					reg = <0>;
1589				};
1590				port@1 {
1591					reg = <1>;
1592				};
1593			};
1594		};
1595
1596		audma0: dma-controller@ec700000 {
1597			compatible = "renesas,dmac-r8a774a1",
1598				     "renesas,rcar-dmac";
1599			reg = <0 0xec700000 0 0x10000>;
1600			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1601				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1602				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1603				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1604				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1605				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1606				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1607				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1608				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1609				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1610				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1611				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1612				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1613				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1614				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1615				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1616				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1617			interrupt-names = "error",
1618					"ch0", "ch1", "ch2", "ch3",
1619					"ch4", "ch5", "ch6", "ch7",
1620					"ch8", "ch9", "ch10", "ch11",
1621					"ch12", "ch13", "ch14", "ch15";
1622			clocks = <&cpg CPG_MOD 502>;
1623			clock-names = "fck";
1624			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1625			resets = <&cpg 502>;
1626			#dma-cells = <1>;
1627			dma-channels = <16>;
1628		};
1629
1630		audma1: dma-controller@ec720000 {
1631			compatible = "renesas,dmac-r8a774a1",
1632				     "renesas,rcar-dmac";
1633			reg = <0 0xec720000 0 0x10000>;
1634			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
1635				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1636				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1637				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1638				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1639				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1640				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1641				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1642				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1643				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1644				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
1645				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1646				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1647				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
1648				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
1649				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
1650				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
1651			interrupt-names = "error",
1652					"ch0", "ch1", "ch2", "ch3",
1653					"ch4", "ch5", "ch6", "ch7",
1654					"ch8", "ch9", "ch10", "ch11",
1655					"ch12", "ch13", "ch14", "ch15";
1656			clocks = <&cpg CPG_MOD 501>;
1657			clock-names = "fck";
1658			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1659			resets = <&cpg 501>;
1660			#dma-cells = <1>;
1661			dma-channels = <16>;
1662		};
1663
1664		xhci0: usb@ee000000 {
1665			compatible = "renesas,xhci-r8a774a1",
1666				     "renesas,rcar-gen3-xhci";
1667			reg = <0 0xee000000 0 0xc00>;
1668			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1669			clocks = <&cpg CPG_MOD 328>;
1670			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1671			resets = <&cpg 328>;
1672			status = "disabled";
1673		};
1674
1675		usb3_peri0: usb@ee020000 {
1676			compatible = "renesas,r8a774a1-usb3-peri",
1677				     "renesas,rcar-gen3-usb3-peri";
1678			reg = <0 0xee020000 0 0x400>;
1679			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1680			clocks = <&cpg CPG_MOD 328>;
1681			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1682			resets = <&cpg 328>;
1683			status = "disabled";
1684		};
1685
1686		ohci0: usb@ee080000 {
1687			compatible = "generic-ohci";
1688			reg = <0 0xee080000 0 0x100>;
1689			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1690			clocks = <&cpg CPG_MOD 703>;
1691			phys = <&usb2_phy0>;
1692			phy-names = "usb";
1693			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1694			resets = <&cpg 703>;
1695			status = "disabled";
1696		};
1697
1698		ohci1: usb@ee0a0000 {
1699			compatible = "generic-ohci";
1700			reg = <0 0xee0a0000 0 0x100>;
1701			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1702			clocks = <&cpg CPG_MOD 702>;
1703			phys = <&usb2_phy1>;
1704			phy-names = "usb";
1705			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1706			resets = <&cpg 702>;
1707			status = "disabled";
1708		};
1709
1710		ehci0: usb@ee080100 {
1711			compatible = "generic-ehci";
1712			reg = <0 0xee080100 0 0x100>;
1713			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1714			clocks = <&cpg CPG_MOD 703>;
1715			phys = <&usb2_phy0>;
1716			phy-names = "usb";
1717			companion = <&ohci0>;
1718			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1719			resets = <&cpg 703>;
1720			status = "disabled";
1721		};
1722
1723		ehci1: usb@ee0a0100 {
1724			compatible = "generic-ehci";
1725			reg = <0 0xee0a0100 0 0x100>;
1726			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1727			clocks = <&cpg CPG_MOD 702>;
1728			phys = <&usb2_phy1>;
1729			phy-names = "usb";
1730			companion = <&ohci1>;
1731			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1732			resets = <&cpg 702>;
1733			status = "disabled";
1734		};
1735
1736		usb2_phy0: usb-phy@ee080200 {
1737			compatible = "renesas,usb2-phy-r8a774a1",
1738				     "renesas,rcar-gen3-usb2-phy";
1739			reg = <0 0xee080200 0 0x700>;
1740			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1741			clocks = <&cpg CPG_MOD 703>;
1742			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1743			resets = <&cpg 703>;
1744			#phy-cells = <0>;
1745			status = "disabled";
1746		};
1747
1748		usb2_phy1: usb-phy@ee0a0200 {
1749			compatible = "renesas,usb2-phy-r8a774a1",
1750				     "renesas,rcar-gen3-usb2-phy";
1751			reg = <0 0xee0a0200 0 0x700>;
1752			clocks = <&cpg CPG_MOD 702>;
1753			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1754			resets = <&cpg 702>;
1755			#phy-cells = <0>;
1756			status = "disabled";
1757		};
1758
1759		sdhi0: sd@ee100000 {
1760			compatible = "renesas,sdhi-r8a774a1",
1761				     "renesas,rcar-gen3-sdhi";
1762			reg = <0 0xee100000 0 0x2000>;
1763			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1764			clocks = <&cpg CPG_MOD 314>;
1765			max-frequency = <200000000>;
1766			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1767			resets = <&cpg 314>;
1768			status = "disabled";
1769		};
1770
1771		sdhi1: sd@ee120000 {
1772			compatible = "renesas,sdhi-r8a774a1",
1773				     "renesas,rcar-gen3-sdhi";
1774			reg = <0 0xee120000 0 0x2000>;
1775			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1776			clocks = <&cpg CPG_MOD 313>;
1777			max-frequency = <200000000>;
1778			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1779			resets = <&cpg 313>;
1780			status = "disabled";
1781		};
1782
1783		sdhi2: sd@ee140000 {
1784			compatible = "renesas,sdhi-r8a774a1",
1785				     "renesas,rcar-gen3-sdhi";
1786			reg = <0 0xee140000 0 0x2000>;
1787			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1788			clocks = <&cpg CPG_MOD 312>;
1789			max-frequency = <200000000>;
1790			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1791			resets = <&cpg 312>;
1792			status = "disabled";
1793		};
1794
1795		sdhi3: sd@ee160000 {
1796			compatible = "renesas,sdhi-r8a774a1",
1797				     "renesas,rcar-gen3-sdhi";
1798			reg = <0 0xee160000 0 0x2000>;
1799			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1800			clocks = <&cpg CPG_MOD 311>;
1801			max-frequency = <200000000>;
1802			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1803			resets = <&cpg 311>;
1804			status = "disabled";
1805		};
1806
1807		gic: interrupt-controller@f1010000 {
1808			compatible = "arm,gic-400";
1809			#interrupt-cells = <3>;
1810			#address-cells = <0>;
1811			interrupt-controller;
1812			reg = <0x0 0xf1010000 0 0x1000>,
1813			      <0x0 0xf1020000 0 0x20000>,
1814			      <0x0 0xf1040000 0 0x20000>,
1815			      <0x0 0xf1060000 0 0x20000>;
1816			interrupts = <GIC_PPI 9
1817					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1818			clocks = <&cpg CPG_MOD 408>;
1819			clock-names = "clk";
1820			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1821			resets = <&cpg 408>;
1822		};
1823
1824		fcpf0: fcp@fe950000 {
1825			compatible = "renesas,fcpf";
1826			reg = <0 0xfe950000 0 0x200>;
1827			clocks = <&cpg CPG_MOD 615>;
1828			power-domains = <&sysc R8A774A1_PD_A3VC>;
1829			resets = <&cpg 615>;
1830		};
1831
1832		fcpvb0: fcp@fe96f000 {
1833			compatible = "renesas,fcpv";
1834			reg = <0 0xfe96f000 0 0x200>;
1835			clocks = <&cpg CPG_MOD 607>;
1836			power-domains = <&sysc R8A774A1_PD_A3VC>;
1837			resets = <&cpg 607>;
1838		};
1839
1840		fcpvd0: fcp@fea27000 {
1841			compatible = "renesas,fcpv";
1842			reg = <0 0xfea27000 0 0x200>;
1843			clocks = <&cpg CPG_MOD 603>;
1844			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1845			resets = <&cpg 603>;
1846			iommus = <&ipmmu_vi0 8>;
1847		};
1848
1849		fcpvd1: fcp@fea2f000 {
1850			compatible = "renesas,fcpv";
1851			reg = <0 0xfea2f000 0 0x200>;
1852			clocks = <&cpg CPG_MOD 602>;
1853			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1854			resets = <&cpg 602>;
1855			iommus = <&ipmmu_vi0 9>;
1856		};
1857
1858		fcpvd2: fcp@fea37000 {
1859			compatible = "renesas,fcpv";
1860			reg = <0 0xfea37000 0 0x200>;
1861			clocks = <&cpg CPG_MOD 601>;
1862			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1863			resets = <&cpg 601>;
1864			iommus = <&ipmmu_vi0 10>;
1865		};
1866
1867		fcpvi0: fcp@fe9af000 {
1868			compatible = "renesas,fcpv";
1869			reg = <0 0xfe9af000 0 0x200>;
1870			clocks = <&cpg CPG_MOD 611>;
1871			power-domains = <&sysc R8A774A1_PD_A3VC>;
1872			resets = <&cpg 611>;
1873			iommus = <&ipmmu_vc0 19>;
1874		};
1875
1876		csi20: csi2@fea80000 {
1877			compatible = "renesas,r8a774a1-csi2";
1878			reg = <0 0xfea80000 0 0x10000>;
1879			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1880			clocks = <&cpg CPG_MOD 714>;
1881			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1882			resets = <&cpg 714>;
1883			status = "disabled";
1884
1885			ports {
1886				#address-cells = <1>;
1887				#size-cells = <0>;
1888
1889				port@1 {
1890					#address-cells = <1>;
1891					#size-cells = <0>;
1892
1893					reg = <1>;
1894
1895					csi20vin0: endpoint@0 {
1896						reg = <0>;
1897						remote-endpoint = <&vin0csi20>;
1898					};
1899					csi20vin1: endpoint@1 {
1900						reg = <1>;
1901						remote-endpoint = <&vin1csi20>;
1902					};
1903					csi20vin2: endpoint@2 {
1904						reg = <2>;
1905						remote-endpoint = <&vin2csi20>;
1906					};
1907					csi20vin3: endpoint@3 {
1908						reg = <3>;
1909						remote-endpoint = <&vin3csi20>;
1910					};
1911					csi20vin4: endpoint@4 {
1912						reg = <4>;
1913						remote-endpoint = <&vin4csi20>;
1914					};
1915					csi20vin5: endpoint@5 {
1916						reg = <5>;
1917						remote-endpoint = <&vin5csi20>;
1918					};
1919					csi20vin6: endpoint@6 {
1920						reg = <6>;
1921						remote-endpoint = <&vin6csi20>;
1922					};
1923					csi20vin7: endpoint@7 {
1924						reg = <7>;
1925						remote-endpoint = <&vin7csi20>;
1926					};
1927				};
1928			};
1929		};
1930
1931		csi40: csi2@feaa0000 {
1932			compatible = "renesas,r8a774a1-csi2";
1933			reg = <0 0xfeaa0000 0 0x10000>;
1934			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1935			clocks = <&cpg CPG_MOD 716>;
1936			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1937			resets = <&cpg 716>;
1938			status = "disabled";
1939
1940			ports {
1941				#address-cells = <1>;
1942				#size-cells = <0>;
1943
1944				port@1 {
1945					#address-cells = <1>;
1946					#size-cells = <0>;
1947
1948					reg = <1>;
1949
1950					csi40vin0: endpoint@0 {
1951						reg = <0>;
1952						remote-endpoint = <&vin0csi40>;
1953					};
1954					csi40vin1: endpoint@1 {
1955						reg = <1>;
1956						remote-endpoint = <&vin1csi40>;
1957					};
1958					csi40vin2: endpoint@2 {
1959						reg = <2>;
1960						remote-endpoint = <&vin2csi40>;
1961					};
1962					csi40vin3: endpoint@3 {
1963						reg = <3>;
1964						remote-endpoint = <&vin3csi40>;
1965					};
1966					csi40vin4: endpoint@4 {
1967						reg = <4>;
1968						remote-endpoint = <&vin4csi40>;
1969					};
1970					csi40vin5: endpoint@5 {
1971						reg = <5>;
1972						remote-endpoint = <&vin5csi40>;
1973					};
1974					csi40vin6: endpoint@6 {
1975						reg = <6>;
1976						remote-endpoint = <&vin6csi40>;
1977					};
1978					csi40vin7: endpoint@7 {
1979						reg = <7>;
1980						remote-endpoint = <&vin7csi40>;
1981					};
1982				};
1983
1984			};
1985		};
1986
1987		prr: chipid@fff00044 {
1988			compatible = "renesas,prr";
1989			reg = <0 0xfff00044 0 4>;
1990		};
1991	};
1992
1993	thermal-zones {
1994		sensor_thermal1: sensor-thermal1 {
1995			polling-delay-passive = <250>;
1996			polling-delay = <1000>;
1997			thermal-sensors = <&tsc 0>;
1998
1999			trips {
2000				sensor1_crit: sensor1-crit {
2001					temperature = <120000>;
2002					hysteresis = <1000>;
2003					type = "critical";
2004				};
2005			};
2006		};
2007
2008		sensor_thermal2: sensor-thermal2 {
2009			polling-delay-passive = <250>;
2010			polling-delay = <1000>;
2011			thermal-sensors = <&tsc 1>;
2012
2013			trips {
2014				sensor2_crit: sensor2-crit {
2015					temperature = <120000>;
2016					hysteresis = <1000>;
2017					type = "critical";
2018				};
2019			};
2020
2021		};
2022
2023		sensor_thermal3: sensor-thermal3 {
2024			polling-delay-passive = <250>;
2025			polling-delay = <1000>;
2026			thermal-sensors = <&tsc 2>;
2027
2028			trips {
2029				sensor3_crit: sensor3-crit {
2030					temperature = <120000>;
2031					hysteresis = <1000>;
2032					type = "critical";
2033				};
2034			};
2035		};
2036	};
2037
2038	timer {
2039		compatible = "arm,armv8-timer";
2040		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2041				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2042				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2043				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2044	};
2045
2046	/* External USB clocks - can be overridden by the board */
2047	usb3s0_clk: usb3s0 {
2048		compatible = "fixed-clock";
2049		#clock-cells = <0>;
2050		clock-frequency = <0>;
2051	};
2052
2053	usb_extal_clk: usb_extal {
2054		compatible = "fixed-clock";
2055		#clock-cells = <0>;
2056		clock-frequency = <0>;
2057	};
2058};
2059