1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11#include <dt-bindings/power/r8a774a1-sysc.h>
12
13#define CPG_AUDIO_CLK_I		R8A774A1_CLK_S0D4
14
15/ {
16	compatible = "renesas,r8a774a1";
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		i2c0 = &i2c0;
22		i2c1 = &i2c1;
23		i2c2 = &i2c2;
24		i2c3 = &i2c3;
25		i2c4 = &i2c4;
26		i2c5 = &i2c5;
27		i2c6 = &i2c6;
28		i2c7 = &i2c_dvfs;
29	};
30
31	/*
32	 * The external audio clocks are configured as 0 Hz fixed frequency
33	 * clocks by default.
34	 * Boards that provide audio clocks should override them.
35	 */
36	audio_clk_a: audio_clk_a {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-frequency = <0>;
40	};
41
42	audio_clk_b: audio_clk_b {
43		compatible = "fixed-clock";
44		#clock-cells = <0>;
45		clock-frequency = <0>;
46	};
47
48	audio_clk_c: audio_clk_c {
49		compatible = "fixed-clock";
50		#clock-cells = <0>;
51		clock-frequency = <0>;
52	};
53
54	/* External CAN clock - to be overridden by boards that provide it */
55	can_clk: can {
56		compatible = "fixed-clock";
57		#clock-cells = <0>;
58		clock-frequency = <0>;
59	};
60
61	cluster0_opp: opp_table0 {
62		compatible = "operating-points-v2";
63		opp-shared;
64
65		opp-500000000 {
66			opp-hz = /bits/ 64 <500000000>;
67			opp-microvolt = <820000>;
68			clock-latency-ns = <300000>;
69		};
70		opp-1000000000 {
71			opp-hz = /bits/ 64 <1000000000>;
72			opp-microvolt = <820000>;
73			clock-latency-ns = <300000>;
74		};
75		opp-1500000000 {
76			opp-hz = /bits/ 64 <1500000000>;
77			opp-microvolt = <820000>;
78			clock-latency-ns = <300000>;
79		};
80	};
81
82	cluster1_opp: opp_table1 {
83		compatible = "operating-points-v2";
84		opp-shared;
85
86		opp-800000000 {
87			opp-hz = /bits/ 64 <800000000>;
88			opp-microvolt = <820000>;
89			clock-latency-ns = <300000>;
90		};
91		opp-1000000000 {
92			opp-hz = /bits/ 64 <1000000000>;
93			opp-microvolt = <820000>;
94			clock-latency-ns = <300000>;
95		};
96		opp-1200000000 {
97			opp-hz = /bits/ 64 <1200000000>;
98			opp-microvolt = <820000>;
99			clock-latency-ns = <300000>;
100		};
101	};
102
103	cpus {
104		#address-cells = <1>;
105		#size-cells = <0>;
106
107		cpu-map {
108			cluster0 {
109				core0 {
110					cpu = <&a57_0>;
111				};
112				core1 {
113					cpu = <&a57_1>;
114				};
115			};
116
117			cluster1 {
118				core0 {
119					cpu = <&a53_0>;
120				};
121				core1 {
122					cpu = <&a53_1>;
123				};
124				core2 {
125					cpu = <&a53_2>;
126				};
127				core3 {
128					cpu = <&a53_3>;
129				};
130			};
131		};
132
133		a57_0: cpu@0 {
134			compatible = "arm,cortex-a57";
135			reg = <0x0>;
136			device_type = "cpu";
137			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
138			next-level-cache = <&L2_CA57>;
139			enable-method = "psci";
140			dynamic-power-coefficient = <854>;
141			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
142			operating-points-v2 = <&cluster0_opp>;
143			capacity-dmips-mhz = <1024>;
144			#cooling-cells = <2>;
145		};
146
147		a57_1: cpu@1 {
148			compatible = "arm,cortex-a57";
149			reg = <0x1>;
150			device_type = "cpu";
151			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
152			next-level-cache = <&L2_CA57>;
153			enable-method = "psci";
154			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
155			operating-points-v2 = <&cluster0_opp>;
156			capacity-dmips-mhz = <1024>;
157			#cooling-cells = <2>;
158		};
159
160		a53_0: cpu@100 {
161			compatible = "arm,cortex-a53";
162			reg = <0x100>;
163			device_type = "cpu";
164			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
165			next-level-cache = <&L2_CA53>;
166			enable-method = "psci";
167			#cooling-cells = <2>;
168			dynamic-power-coefficient = <277>;
169			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
170			operating-points-v2 = <&cluster1_opp>;
171			capacity-dmips-mhz = <560>;
172		};
173
174		a53_1: cpu@101 {
175			compatible = "arm,cortex-a53";
176			reg = <0x101>;
177			device_type = "cpu";
178			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
179			next-level-cache = <&L2_CA53>;
180			enable-method = "psci";
181			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
182			operating-points-v2 = <&cluster1_opp>;
183			capacity-dmips-mhz = <560>;
184		};
185
186		a53_2: cpu@102 {
187			compatible = "arm,cortex-a53";
188			reg = <0x102>;
189			device_type = "cpu";
190			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
191			next-level-cache = <&L2_CA53>;
192			enable-method = "psci";
193			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
194			operating-points-v2 = <&cluster1_opp>;
195			capacity-dmips-mhz = <560>;
196		};
197
198		a53_3: cpu@103 {
199			compatible = "arm,cortex-a53";
200			reg = <0x103>;
201			device_type = "cpu";
202			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
203			next-level-cache = <&L2_CA53>;
204			enable-method = "psci";
205			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
206			operating-points-v2 = <&cluster1_opp>;
207			capacity-dmips-mhz = <560>;
208		};
209
210		L2_CA57: cache-controller-0 {
211			compatible = "cache";
212			power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
213			cache-unified;
214			cache-level = <2>;
215		};
216
217		L2_CA53: cache-controller-1 {
218			compatible = "cache";
219			power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
220			cache-unified;
221			cache-level = <2>;
222		};
223	};
224
225	extal_clk: extal {
226		compatible = "fixed-clock";
227		#clock-cells = <0>;
228		/* This value must be overridden by the board */
229		clock-frequency = <0>;
230	};
231
232	extalr_clk: extalr {
233		compatible = "fixed-clock";
234		#clock-cells = <0>;
235		/* This value must be overridden by the board */
236		clock-frequency = <0>;
237	};
238
239	/* External PCIe clock - can be overridden by the board */
240	pcie_bus_clk: pcie_bus {
241		compatible = "fixed-clock";
242		#clock-cells = <0>;
243		clock-frequency = <0>;
244	};
245
246	pmu_a53 {
247		compatible = "arm,cortex-a53-pmu";
248		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
249				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
250				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
251				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
252		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
253	};
254
255	pmu_a57 {
256		compatible = "arm,cortex-a57-pmu";
257		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
258				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
259		interrupt-affinity = <&a57_0>, <&a57_1>;
260	};
261
262	psci {
263		compatible = "arm,psci-1.0", "arm,psci-0.2";
264		method = "smc";
265	};
266
267	/* External SCIF clock - to be overridden by boards that provide it */
268	scif_clk: scif {
269		compatible = "fixed-clock";
270		#clock-cells = <0>;
271		clock-frequency = <0>;
272	};
273
274	soc {
275		compatible = "simple-bus";
276		interrupt-parent = <&gic>;
277		#address-cells = <2>;
278		#size-cells = <2>;
279		ranges;
280
281		rwdt: watchdog@e6020000 {
282			compatible = "renesas,r8a774a1-wdt",
283				     "renesas,rcar-gen3-wdt";
284			reg = <0 0xe6020000 0 0x0c>;
285			clocks = <&cpg CPG_MOD 402>;
286			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
287			resets = <&cpg 402>;
288			status = "disabled";
289		};
290
291		gpio0: gpio@e6050000 {
292			compatible = "renesas,gpio-r8a774a1",
293				     "renesas,rcar-gen3-gpio";
294			reg = <0 0xe6050000 0 0x50>;
295			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
296			#gpio-cells = <2>;
297			gpio-controller;
298			gpio-ranges = <&pfc 0 0 16>;
299			#interrupt-cells = <2>;
300			interrupt-controller;
301			clocks = <&cpg CPG_MOD 912>;
302			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
303			resets = <&cpg 912>;
304		};
305
306		gpio1: gpio@e6051000 {
307			compatible = "renesas,gpio-r8a774a1",
308				     "renesas,rcar-gen3-gpio";
309			reg = <0 0xe6051000 0 0x50>;
310			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
311			#gpio-cells = <2>;
312			gpio-controller;
313			gpio-ranges = <&pfc 0 32 29>;
314			#interrupt-cells = <2>;
315			interrupt-controller;
316			clocks = <&cpg CPG_MOD 911>;
317			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
318			resets = <&cpg 911>;
319		};
320
321		gpio2: gpio@e6052000 {
322			compatible = "renesas,gpio-r8a774a1",
323				     "renesas,rcar-gen3-gpio";
324			reg = <0 0xe6052000 0 0x50>;
325			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
326			#gpio-cells = <2>;
327			gpio-controller;
328			gpio-ranges = <&pfc 0 64 15>;
329			#interrupt-cells = <2>;
330			interrupt-controller;
331			clocks = <&cpg CPG_MOD 910>;
332			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
333			resets = <&cpg 910>;
334		};
335
336		gpio3: gpio@e6053000 {
337			compatible = "renesas,gpio-r8a774a1",
338				     "renesas,rcar-gen3-gpio";
339			reg = <0 0xe6053000 0 0x50>;
340			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
341			#gpio-cells = <2>;
342			gpio-controller;
343			gpio-ranges = <&pfc 0 96 16>;
344			#interrupt-cells = <2>;
345			interrupt-controller;
346			clocks = <&cpg CPG_MOD 909>;
347			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
348			resets = <&cpg 909>;
349		};
350
351		gpio4: gpio@e6054000 {
352			compatible = "renesas,gpio-r8a774a1",
353				     "renesas,rcar-gen3-gpio";
354			reg = <0 0xe6054000 0 0x50>;
355			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
356			#gpio-cells = <2>;
357			gpio-controller;
358			gpio-ranges = <&pfc 0 128 18>;
359			#interrupt-cells = <2>;
360			interrupt-controller;
361			clocks = <&cpg CPG_MOD 908>;
362			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
363			resets = <&cpg 908>;
364		};
365
366		gpio5: gpio@e6055000 {
367			compatible = "renesas,gpio-r8a774a1",
368				     "renesas,rcar-gen3-gpio";
369			reg = <0 0xe6055000 0 0x50>;
370			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
371			#gpio-cells = <2>;
372			gpio-controller;
373			gpio-ranges = <&pfc 0 160 26>;
374			#interrupt-cells = <2>;
375			interrupt-controller;
376			clocks = <&cpg CPG_MOD 907>;
377			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
378			resets = <&cpg 907>;
379		};
380
381		gpio6: gpio@e6055400 {
382			compatible = "renesas,gpio-r8a774a1",
383				     "renesas,rcar-gen3-gpio";
384			reg = <0 0xe6055400 0 0x50>;
385			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
386			#gpio-cells = <2>;
387			gpio-controller;
388			gpio-ranges = <&pfc 0 192 32>;
389			#interrupt-cells = <2>;
390			interrupt-controller;
391			clocks = <&cpg CPG_MOD 906>;
392			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
393			resets = <&cpg 906>;
394		};
395
396		gpio7: gpio@e6055800 {
397			compatible = "renesas,gpio-r8a774a1",
398				     "renesas,rcar-gen3-gpio";
399			reg = <0 0xe6055800 0 0x50>;
400			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
401			#gpio-cells = <2>;
402			gpio-controller;
403			gpio-ranges = <&pfc 0 224 4>;
404			#interrupt-cells = <2>;
405			interrupt-controller;
406			clocks = <&cpg CPG_MOD 905>;
407			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
408			resets = <&cpg 905>;
409		};
410
411		pfc: pinctrl@e6060000 {
412			compatible = "renesas,pfc-r8a774a1";
413			reg = <0 0xe6060000 0 0x50c>;
414		};
415
416		cmt0: timer@e60f0000 {
417			compatible = "renesas,r8a774a1-cmt0",
418				     "renesas,rcar-gen3-cmt0";
419			reg = <0 0xe60f0000 0 0x1004>;
420			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
421				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
422			clocks = <&cpg CPG_MOD 303>;
423			clock-names = "fck";
424			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
425			resets = <&cpg 303>;
426			status = "disabled";
427		};
428
429		cmt1: timer@e6130000 {
430			compatible = "renesas,r8a774a1-cmt1",
431				     "renesas,rcar-gen3-cmt1";
432			reg = <0 0xe6130000 0 0x1004>;
433			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
434				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
435				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
436				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
437				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
438				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
439				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
440				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
441			clocks = <&cpg CPG_MOD 302>;
442			clock-names = "fck";
443			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
444			resets = <&cpg 302>;
445			status = "disabled";
446		};
447
448		cmt2: timer@e6140000 {
449			compatible = "renesas,r8a774a1-cmt1",
450				     "renesas,rcar-gen3-cmt1";
451			reg = <0 0xe6140000 0 0x1004>;
452			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
453				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
454				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
455				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
456				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
457				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
458				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
459				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
460			clocks = <&cpg CPG_MOD 301>;
461			clock-names = "fck";
462			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
463			resets = <&cpg 301>;
464			status = "disabled";
465		};
466
467		cmt3: timer@e6148000 {
468			compatible = "renesas,r8a774a1-cmt1",
469				     "renesas,rcar-gen3-cmt1";
470			reg = <0 0xe6148000 0 0x1004>;
471			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
472				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
473				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
474				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
475				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
476				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
477				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
478				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
479			clocks = <&cpg CPG_MOD 300>;
480			clock-names = "fck";
481			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
482			resets = <&cpg 300>;
483			status = "disabled";
484		};
485
486		cpg: clock-controller@e6150000 {
487			compatible = "renesas,r8a774a1-cpg-mssr";
488			reg = <0 0xe6150000 0 0x0bb0>;
489			clocks = <&extal_clk>, <&extalr_clk>;
490			clock-names = "extal", "extalr";
491			#clock-cells = <2>;
492			#power-domain-cells = <0>;
493			#reset-cells = <1>;
494		};
495
496		rst: reset-controller@e6160000 {
497			compatible = "renesas,r8a774a1-rst";
498			reg = <0 0xe6160000 0 0x018c>;
499		};
500
501		sysc: system-controller@e6180000 {
502			compatible = "renesas,r8a774a1-sysc";
503			reg = <0 0xe6180000 0 0x0400>;
504			#power-domain-cells = <1>;
505		};
506
507		tsc: thermal@e6198000 {
508			compatible = "renesas,r8a774a1-thermal";
509			reg = <0 0xe6198000 0 0x100>,
510			      <0 0xe61a0000 0 0x100>,
511			      <0 0xe61a8000 0 0x100>;
512			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
513				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
514				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
515			clocks = <&cpg CPG_MOD 522>;
516			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
517			resets = <&cpg 522>;
518			#thermal-sensor-cells = <1>;
519		};
520
521		intc_ex: interrupt-controller@e61c0000 {
522			compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
523			#interrupt-cells = <2>;
524			interrupt-controller;
525			reg = <0 0xe61c0000 0 0x200>;
526			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
527				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
528				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
529				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
530				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
531				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
532			clocks = <&cpg CPG_MOD 407>;
533			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
534			resets = <&cpg 407>;
535		};
536
537		tmu0: timer@e61e0000 {
538			compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
539			reg = <0 0xe61e0000 0 0x30>;
540			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
541				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
542				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
543			clocks = <&cpg CPG_MOD 125>;
544			clock-names = "fck";
545			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
546			resets = <&cpg 125>;
547			status = "disabled";
548		};
549
550		tmu1: timer@e6fc0000 {
551			compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
552			reg = <0 0xe6fc0000 0 0x30>;
553			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
554				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
555				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
556			clocks = <&cpg CPG_MOD 124>;
557			clock-names = "fck";
558			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
559			resets = <&cpg 124>;
560			status = "disabled";
561		};
562
563		tmu2: timer@e6fd0000 {
564			compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
565			reg = <0 0xe6fd0000 0 0x30>;
566			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
567				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
568				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
569			clocks = <&cpg CPG_MOD 123>;
570			clock-names = "fck";
571			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
572			resets = <&cpg 123>;
573			status = "disabled";
574		};
575
576		tmu3: timer@e6fe0000 {
577			compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
578			reg = <0 0xe6fe0000 0 0x30>;
579			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
580				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
581				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
582			clocks = <&cpg CPG_MOD 122>;
583			clock-names = "fck";
584			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
585			resets = <&cpg 122>;
586			status = "disabled";
587		};
588
589		tmu4: timer@ffc00000 {
590			compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
591			reg = <0 0xffc00000 0 0x30>;
592			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
593				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
594				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
595			clocks = <&cpg CPG_MOD 121>;
596			clock-names = "fck";
597			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
598			resets = <&cpg 121>;
599			status = "disabled";
600		};
601
602		i2c0: i2c@e6500000 {
603			#address-cells = <1>;
604			#size-cells = <0>;
605			compatible = "renesas,i2c-r8a774a1",
606				     "renesas,rcar-gen3-i2c";
607			reg = <0 0xe6500000 0 0x40>;
608			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
609			clocks = <&cpg CPG_MOD 931>;
610			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
611			resets = <&cpg 931>;
612			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
613			       <&dmac2 0x91>, <&dmac2 0x90>;
614			dma-names = "tx", "rx", "tx", "rx";
615			i2c-scl-internal-delay-ns = <110>;
616			status = "disabled";
617		};
618
619		i2c1: i2c@e6508000 {
620			#address-cells = <1>;
621			#size-cells = <0>;
622			compatible = "renesas,i2c-r8a774a1",
623				     "renesas,rcar-gen3-i2c";
624			reg = <0 0xe6508000 0 0x40>;
625			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
626			clocks = <&cpg CPG_MOD 930>;
627			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
628			resets = <&cpg 930>;
629			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
630			       <&dmac2 0x93>, <&dmac2 0x92>;
631			dma-names = "tx", "rx", "tx", "rx";
632			i2c-scl-internal-delay-ns = <6>;
633			status = "disabled";
634		};
635
636		i2c2: i2c@e6510000 {
637			#address-cells = <1>;
638			#size-cells = <0>;
639			compatible = "renesas,i2c-r8a774a1",
640				     "renesas,rcar-gen3-i2c";
641			reg = <0 0xe6510000 0 0x40>;
642			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
643			clocks = <&cpg CPG_MOD 929>;
644			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
645			resets = <&cpg 929>;
646			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
647			       <&dmac2 0x95>, <&dmac2 0x94>;
648			dma-names = "tx", "rx", "tx", "rx";
649			i2c-scl-internal-delay-ns = <6>;
650			status = "disabled";
651		};
652
653		i2c3: i2c@e66d0000 {
654			#address-cells = <1>;
655			#size-cells = <0>;
656			compatible = "renesas,i2c-r8a774a1",
657				     "renesas,rcar-gen3-i2c";
658			reg = <0 0xe66d0000 0 0x40>;
659			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
660			clocks = <&cpg CPG_MOD 928>;
661			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
662			resets = <&cpg 928>;
663			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
664			dma-names = "tx", "rx";
665			i2c-scl-internal-delay-ns = <110>;
666			status = "disabled";
667		};
668
669		i2c4: i2c@e66d8000 {
670			#address-cells = <1>;
671			#size-cells = <0>;
672			compatible = "renesas,i2c-r8a774a1",
673				     "renesas,rcar-gen3-i2c";
674			reg = <0 0xe66d8000 0 0x40>;
675			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
676			clocks = <&cpg CPG_MOD 927>;
677			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
678			resets = <&cpg 927>;
679			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
680			dma-names = "tx", "rx";
681			i2c-scl-internal-delay-ns = <110>;
682			status = "disabled";
683		};
684
685		i2c5: i2c@e66e0000 {
686			#address-cells = <1>;
687			#size-cells = <0>;
688			compatible = "renesas,i2c-r8a774a1",
689				     "renesas,rcar-gen3-i2c";
690			reg = <0 0xe66e0000 0 0x40>;
691			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
692			clocks = <&cpg CPG_MOD 919>;
693			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
694			resets = <&cpg 919>;
695			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
696			dma-names = "tx", "rx";
697			i2c-scl-internal-delay-ns = <110>;
698			status = "disabled";
699		};
700
701		i2c6: i2c@e66e8000 {
702			#address-cells = <1>;
703			#size-cells = <0>;
704			compatible = "renesas,i2c-r8a774a1",
705				     "renesas,rcar-gen3-i2c";
706			reg = <0 0xe66e8000 0 0x40>;
707			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
708			clocks = <&cpg CPG_MOD 918>;
709			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
710			resets = <&cpg 918>;
711			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
712			dma-names = "tx", "rx";
713			i2c-scl-internal-delay-ns = <6>;
714			status = "disabled";
715		};
716
717		i2c_dvfs: i2c@e60b0000 {
718			#address-cells = <1>;
719			#size-cells = <0>;
720			compatible = "renesas,iic-r8a774a1",
721				     "renesas,rcar-gen3-iic",
722				     "renesas,rmobile-iic";
723			reg = <0 0xe60b0000 0 0x425>;
724			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
725			clocks = <&cpg CPG_MOD 926>;
726			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
727			resets = <&cpg 926>;
728			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
729			dma-names = "tx", "rx";
730			status = "disabled";
731		};
732
733		hscif0: serial@e6540000 {
734			compatible = "renesas,hscif-r8a774a1",
735				     "renesas,rcar-gen3-hscif",
736				     "renesas,hscif";
737			reg = <0 0xe6540000 0 0x60>;
738			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
739			clocks = <&cpg CPG_MOD 520>,
740				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
741				 <&scif_clk>;
742			clock-names = "fck", "brg_int", "scif_clk";
743			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
744			       <&dmac2 0x31>, <&dmac2 0x30>;
745			dma-names = "tx", "rx", "tx", "rx";
746			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
747			resets = <&cpg 520>;
748			status = "disabled";
749		};
750
751		hscif1: serial@e6550000 {
752			compatible = "renesas,hscif-r8a774a1",
753				     "renesas,rcar-gen3-hscif",
754				     "renesas,hscif";
755			reg = <0 0xe6550000 0 0x60>;
756			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
757			clocks = <&cpg CPG_MOD 519>,
758				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
759				 <&scif_clk>;
760			clock-names = "fck", "brg_int", "scif_clk";
761			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
762			       <&dmac2 0x33>, <&dmac2 0x32>;
763			dma-names = "tx", "rx", "tx", "rx";
764			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
765			resets = <&cpg 519>;
766			status = "disabled";
767		};
768
769		hscif2: serial@e6560000 {
770			compatible = "renesas,hscif-r8a774a1",
771				     "renesas,rcar-gen3-hscif",
772				     "renesas,hscif";
773			reg = <0 0xe6560000 0 0x60>;
774			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
775			clocks = <&cpg CPG_MOD 518>,
776				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
777				 <&scif_clk>;
778			clock-names = "fck", "brg_int", "scif_clk";
779			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
780			       <&dmac2 0x35>, <&dmac2 0x34>;
781			dma-names = "tx", "rx", "tx", "rx";
782			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
783			resets = <&cpg 518>;
784			status = "disabled";
785		};
786
787		hscif3: serial@e66a0000 {
788			compatible = "renesas,hscif-r8a774a1",
789				     "renesas,rcar-gen3-hscif",
790				     "renesas,hscif";
791			reg = <0 0xe66a0000 0 0x60>;
792			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
793			clocks = <&cpg CPG_MOD 517>,
794				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
795				 <&scif_clk>;
796			clock-names = "fck", "brg_int", "scif_clk";
797			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
798			dma-names = "tx", "rx";
799			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
800			resets = <&cpg 517>;
801			status = "disabled";
802		};
803
804		hscif4: serial@e66b0000 {
805			compatible = "renesas,hscif-r8a774a1",
806				     "renesas,rcar-gen3-hscif",
807				     "renesas,hscif";
808			reg = <0 0xe66b0000 0 0x60>;
809			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
810			clocks = <&cpg CPG_MOD 516>,
811				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
812				 <&scif_clk>;
813			clock-names = "fck", "brg_int", "scif_clk";
814			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
815			dma-names = "tx", "rx";
816			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
817			resets = <&cpg 516>;
818			status = "disabled";
819		};
820
821		hsusb: usb@e6590000 {
822			compatible = "renesas,usbhs-r8a774a1",
823				     "renesas,rcar-gen3-usbhs";
824			reg = <0 0xe6590000 0 0x200>;
825			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
826			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
827			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
828			       <&usb_dmac1 0>, <&usb_dmac1 1>;
829			dma-names = "ch0", "ch1", "ch2", "ch3";
830			renesas,buswait = <11>;
831			phys = <&usb2_phy0 3>;
832			phy-names = "usb";
833			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
834			resets = <&cpg 704>, <&cpg 703>;
835			status = "disabled";
836		};
837
838		usb2_clksel: clock-controller@e6590630 {
839			compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
840				     "renesas,rcar-gen3-usb2-clock-sel";
841			reg = <0 0xe6590630 0 0x02>;
842			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
843				 <&usb_extal_clk>, <&usb3s0_clk>;
844			clock-names = "ehci_ohci", "hs-usb-if",
845				      "usb_extal", "usb_xtal";
846			#clock-cells = <0>;
847			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
848			resets = <&cpg 703>, <&cpg 704>;
849			reset-names = "ehci_ohci", "hs-usb-if";
850			status = "disabled";
851		};
852
853		usb_dmac0: dma-controller@e65a0000 {
854			compatible = "renesas,r8a774a1-usb-dmac",
855				     "renesas,usb-dmac";
856			reg = <0 0xe65a0000 0 0x100>;
857			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
858				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
859			interrupt-names = "ch0", "ch1";
860			clocks = <&cpg CPG_MOD 330>;
861			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
862			resets = <&cpg 330>;
863			#dma-cells = <1>;
864			dma-channels = <2>;
865		};
866
867		usb_dmac1: dma-controller@e65b0000 {
868			compatible = "renesas,r8a774a1-usb-dmac",
869				     "renesas,usb-dmac";
870			reg = <0 0xe65b0000 0 0x100>;
871			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
872				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
873			interrupt-names = "ch0", "ch1";
874			clocks = <&cpg CPG_MOD 331>;
875			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
876			resets = <&cpg 331>;
877			#dma-cells = <1>;
878			dma-channels = <2>;
879		};
880
881		usb3_phy0: usb-phy@e65ee000 {
882			compatible = "renesas,r8a774a1-usb3-phy",
883				     "renesas,rcar-gen3-usb3-phy";
884			reg = <0 0xe65ee000 0 0x90>;
885			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
886				 <&usb_extal_clk>;
887			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
888			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
889			resets = <&cpg 328>;
890			#phy-cells = <0>;
891			status = "disabled";
892		};
893
894		dmac0: dma-controller@e6700000 {
895			compatible = "renesas,dmac-r8a774a1",
896				     "renesas,rcar-dmac";
897			reg = <0 0xe6700000 0 0x10000>;
898			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
899				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
900				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
901				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
902				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
903				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
904				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
905				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
906				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
907				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
908				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
909				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
910				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
911				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
912				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
913				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
914				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
915			interrupt-names = "error",
916					"ch0", "ch1", "ch2", "ch3",
917					"ch4", "ch5", "ch6", "ch7",
918					"ch8", "ch9", "ch10", "ch11",
919					"ch12", "ch13", "ch14", "ch15";
920			clocks = <&cpg CPG_MOD 219>;
921			clock-names = "fck";
922			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
923			resets = <&cpg 219>;
924			#dma-cells = <1>;
925			dma-channels = <16>;
926			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
927			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
928			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
929			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
930			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
931			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
932			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
933			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
934		};
935
936		dmac1: dma-controller@e7300000 {
937			compatible = "renesas,dmac-r8a774a1",
938				     "renesas,rcar-dmac";
939			reg = <0 0xe7300000 0 0x10000>;
940			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
941				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
942				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
943				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
944				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
945				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
946				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
947				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
948				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
949				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
950				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
951				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
952				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
953				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
954				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
955				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
956				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
957			interrupt-names = "error",
958					"ch0", "ch1", "ch2", "ch3",
959					"ch4", "ch5", "ch6", "ch7",
960					"ch8", "ch9", "ch10", "ch11",
961					"ch12", "ch13", "ch14", "ch15";
962			clocks = <&cpg CPG_MOD 218>;
963			clock-names = "fck";
964			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
965			resets = <&cpg 218>;
966			#dma-cells = <1>;
967			dma-channels = <16>;
968			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
969			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
970			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
971			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
972			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
973			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
974			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
975			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
976		};
977
978		dmac2: dma-controller@e7310000 {
979			compatible = "renesas,dmac-r8a774a1",
980				     "renesas,rcar-dmac";
981			reg = <0 0xe7310000 0 0x10000>;
982			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
983				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
984				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
985				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
986				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
987				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
988				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
989				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
990				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
991				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
992				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
993				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
994				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
995				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
996				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
997				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
998				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
999			interrupt-names = "error",
1000					"ch0", "ch1", "ch2", "ch3",
1001					"ch4", "ch5", "ch6", "ch7",
1002					"ch8", "ch9", "ch10", "ch11",
1003					"ch12", "ch13", "ch14", "ch15";
1004			clocks = <&cpg CPG_MOD 217>;
1005			clock-names = "fck";
1006			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1007			resets = <&cpg 217>;
1008			#dma-cells = <1>;
1009			dma-channels = <16>;
1010			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1011			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1012			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1013			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1014			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1015			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1016			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1017			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1018		};
1019
1020		ipmmu_ds0: iommu@e6740000 {
1021			compatible = "renesas,ipmmu-r8a774a1";
1022			reg = <0 0xe6740000 0 0x1000>;
1023			renesas,ipmmu-main = <&ipmmu_mm 0>;
1024			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1025			#iommu-cells = <1>;
1026		};
1027
1028		ipmmu_ds1: iommu@e7740000 {
1029			compatible = "renesas,ipmmu-r8a774a1";
1030			reg = <0 0xe7740000 0 0x1000>;
1031			renesas,ipmmu-main = <&ipmmu_mm 1>;
1032			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1033			#iommu-cells = <1>;
1034		};
1035
1036		ipmmu_hc: iommu@e6570000 {
1037			compatible = "renesas,ipmmu-r8a774a1";
1038			reg = <0 0xe6570000 0 0x1000>;
1039			renesas,ipmmu-main = <&ipmmu_mm 2>;
1040			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1041			#iommu-cells = <1>;
1042		};
1043
1044		ipmmu_mm: iommu@e67b0000 {
1045			compatible = "renesas,ipmmu-r8a774a1";
1046			reg = <0 0xe67b0000 0 0x1000>;
1047			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1048				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1049			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1050			#iommu-cells = <1>;
1051		};
1052
1053		ipmmu_mp: iommu@ec670000 {
1054			compatible = "renesas,ipmmu-r8a774a1";
1055			reg = <0 0xec670000 0 0x1000>;
1056			renesas,ipmmu-main = <&ipmmu_mm 4>;
1057			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1058			#iommu-cells = <1>;
1059		};
1060
1061		ipmmu_pv0: iommu@fd800000 {
1062			compatible = "renesas,ipmmu-r8a774a1";
1063			reg = <0 0xfd800000 0 0x1000>;
1064			renesas,ipmmu-main = <&ipmmu_mm 5>;
1065			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1066			#iommu-cells = <1>;
1067		};
1068
1069		ipmmu_pv1: iommu@fd950000 {
1070			compatible = "renesas,ipmmu-r8a774a1";
1071			reg = <0 0xfd950000 0 0x1000>;
1072			renesas,ipmmu-main = <&ipmmu_mm 6>;
1073			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1074			#iommu-cells = <1>;
1075		};
1076
1077		ipmmu_vc0: iommu@fe6b0000 {
1078			compatible = "renesas,ipmmu-r8a774a1";
1079			reg = <0 0xfe6b0000 0 0x1000>;
1080			renesas,ipmmu-main = <&ipmmu_mm 8>;
1081			power-domains = <&sysc R8A774A1_PD_A3VC>;
1082			#iommu-cells = <1>;
1083		};
1084
1085		ipmmu_vi0: iommu@febd0000 {
1086			compatible = "renesas,ipmmu-r8a774a1";
1087			reg = <0 0xfebd0000 0 0x1000>;
1088			renesas,ipmmu-main = <&ipmmu_mm 9>;
1089			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1090			#iommu-cells = <1>;
1091		};
1092
1093		avb: ethernet@e6800000 {
1094			compatible = "renesas,etheravb-r8a774a1",
1095				     "renesas,etheravb-rcar-gen3";
1096			reg = <0 0xe6800000 0 0x800>;
1097			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1098				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1099				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1100				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1101				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1102				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1103				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1104				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1105				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1106				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1107				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1108				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1109				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1110				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1111				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1112				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1113				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1114				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1115				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1116				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1117				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1118				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1119				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1120				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1121				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1122			interrupt-names = "ch0", "ch1", "ch2", "ch3",
1123					  "ch4", "ch5", "ch6", "ch7",
1124					  "ch8", "ch9", "ch10", "ch11",
1125					  "ch12", "ch13", "ch14", "ch15",
1126					  "ch16", "ch17", "ch18", "ch19",
1127					  "ch20", "ch21", "ch22", "ch23",
1128					  "ch24";
1129			clocks = <&cpg CPG_MOD 812>;
1130			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1131			resets = <&cpg 812>;
1132			phy-mode = "rgmii";
1133			rx-internal-delay-ps = <0>;
1134			tx-internal-delay-ps = <0>;
1135			iommus = <&ipmmu_ds0 16>;
1136			#address-cells = <1>;
1137			#size-cells = <0>;
1138			status = "disabled";
1139		};
1140
1141		can0: can@e6c30000 {
1142			compatible = "renesas,can-r8a774a1",
1143				     "renesas,rcar-gen3-can";
1144			reg = <0 0xe6c30000 0 0x1000>;
1145			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1146			clocks = <&cpg CPG_MOD 916>,
1147				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1148				 <&can_clk>;
1149			clock-names = "clkp1", "clkp2", "can_clk";
1150			assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1151			assigned-clock-rates = <40000000>;
1152			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1153			resets = <&cpg 916>;
1154			status = "disabled";
1155		};
1156
1157		can1: can@e6c38000 {
1158			compatible = "renesas,can-r8a774a1",
1159				     "renesas,rcar-gen3-can";
1160			reg = <0 0xe6c38000 0 0x1000>;
1161			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1162			clocks = <&cpg CPG_MOD 915>,
1163				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1164				 <&can_clk>;
1165			clock-names = "clkp1", "clkp2", "can_clk";
1166			assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1167			assigned-clock-rates = <40000000>;
1168			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1169			resets = <&cpg 915>;
1170			status = "disabled";
1171		};
1172
1173		canfd: can@e66c0000 {
1174			compatible = "renesas,r8a774a1-canfd",
1175				     "renesas,rcar-gen3-canfd";
1176			reg = <0 0xe66c0000 0 0x8000>;
1177			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1178				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1179			clocks = <&cpg CPG_MOD 914>,
1180				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1181				 <&can_clk>;
1182			clock-names = "fck", "canfd", "can_clk";
1183			assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1184			assigned-clock-rates = <40000000>;
1185			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1186			resets = <&cpg 914>;
1187			status = "disabled";
1188
1189			channel0 {
1190				status = "disabled";
1191			};
1192
1193			channel1 {
1194				status = "disabled";
1195			};
1196		};
1197
1198		pwm0: pwm@e6e30000 {
1199			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1200			reg = <0 0xe6e30000 0 0x8>;
1201			#pwm-cells = <2>;
1202			clocks = <&cpg CPG_MOD 523>;
1203			resets = <&cpg 523>;
1204			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1205			status = "disabled";
1206		};
1207
1208		pwm1: pwm@e6e31000 {
1209			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1210			reg = <0 0xe6e31000 0 0x8>;
1211			#pwm-cells = <2>;
1212			clocks = <&cpg CPG_MOD 523>;
1213			resets = <&cpg 523>;
1214			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1215			status = "disabled";
1216		};
1217
1218		pwm2: pwm@e6e32000 {
1219			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1220			reg = <0 0xe6e32000 0 0x8>;
1221			#pwm-cells = <2>;
1222			clocks = <&cpg CPG_MOD 523>;
1223			resets = <&cpg 523>;
1224			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1225			status = "disabled";
1226		};
1227
1228		pwm3: pwm@e6e33000 {
1229			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1230			reg = <0 0xe6e33000 0 0x8>;
1231			#pwm-cells = <2>;
1232			clocks = <&cpg CPG_MOD 523>;
1233			resets = <&cpg 523>;
1234			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1235			status = "disabled";
1236		};
1237
1238		pwm4: pwm@e6e34000 {
1239			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1240			reg = <0 0xe6e34000 0 0x8>;
1241			#pwm-cells = <2>;
1242			clocks = <&cpg CPG_MOD 523>;
1243			resets = <&cpg 523>;
1244			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1245			status = "disabled";
1246		};
1247
1248		pwm5: pwm@e6e35000 {
1249			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1250			reg = <0 0xe6e35000 0 0x8>;
1251			#pwm-cells = <2>;
1252			clocks = <&cpg CPG_MOD 523>;
1253			resets = <&cpg 523>;
1254			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1255			status = "disabled";
1256		};
1257
1258		pwm6: pwm@e6e36000 {
1259			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1260			reg = <0 0xe6e36000 0 0x8>;
1261			#pwm-cells = <2>;
1262			clocks = <&cpg CPG_MOD 523>;
1263			resets = <&cpg 523>;
1264			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1265			status = "disabled";
1266		};
1267
1268		scif0: serial@e6e60000 {
1269			compatible = "renesas,scif-r8a774a1",
1270				     "renesas,rcar-gen3-scif", "renesas,scif";
1271			reg = <0 0xe6e60000 0 0x40>;
1272			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1273			clocks = <&cpg CPG_MOD 207>,
1274				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1275				 <&scif_clk>;
1276			clock-names = "fck", "brg_int", "scif_clk";
1277			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1278			       <&dmac2 0x51>, <&dmac2 0x50>;
1279			dma-names = "tx", "rx", "tx", "rx";
1280			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1281			resets = <&cpg 207>;
1282			status = "disabled";
1283		};
1284
1285		scif1: serial@e6e68000 {
1286			compatible = "renesas,scif-r8a774a1",
1287				     "renesas,rcar-gen3-scif", "renesas,scif";
1288			reg = <0 0xe6e68000 0 0x40>;
1289			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1290			clocks = <&cpg CPG_MOD 206>,
1291				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1292				 <&scif_clk>;
1293			clock-names = "fck", "brg_int", "scif_clk";
1294			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1295			       <&dmac2 0x53>, <&dmac2 0x52>;
1296			dma-names = "tx", "rx", "tx", "rx";
1297			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1298			resets = <&cpg 206>;
1299			status = "disabled";
1300		};
1301
1302		scif2: serial@e6e88000 {
1303			compatible = "renesas,scif-r8a774a1",
1304				     "renesas,rcar-gen3-scif", "renesas,scif";
1305			reg = <0 0xe6e88000 0 0x40>;
1306			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1307			clocks = <&cpg CPG_MOD 310>,
1308				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1309				 <&scif_clk>;
1310			clock-names = "fck", "brg_int", "scif_clk";
1311			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1312			       <&dmac2 0x13>, <&dmac2 0x12>;
1313			dma-names = "tx", "rx", "tx", "rx";
1314			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1315			resets = <&cpg 310>;
1316			status = "disabled";
1317		};
1318
1319		scif3: serial@e6c50000 {
1320			compatible = "renesas,scif-r8a774a1",
1321				     "renesas,rcar-gen3-scif", "renesas,scif";
1322			reg = <0 0xe6c50000 0 0x40>;
1323			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1324			clocks = <&cpg CPG_MOD 204>,
1325				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1326				 <&scif_clk>;
1327			clock-names = "fck", "brg_int", "scif_clk";
1328			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1329			dma-names = "tx", "rx";
1330			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1331			resets = <&cpg 204>;
1332			status = "disabled";
1333		};
1334
1335		scif4: serial@e6c40000 {
1336			compatible = "renesas,scif-r8a774a1",
1337				     "renesas,rcar-gen3-scif", "renesas,scif";
1338			reg = <0 0xe6c40000 0 0x40>;
1339			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1340			clocks = <&cpg CPG_MOD 203>,
1341				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1342				 <&scif_clk>;
1343			clock-names = "fck", "brg_int", "scif_clk";
1344			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1345			dma-names = "tx", "rx";
1346			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1347			resets = <&cpg 203>;
1348			status = "disabled";
1349		};
1350
1351		scif5: serial@e6f30000 {
1352			compatible = "renesas,scif-r8a774a1",
1353				     "renesas,rcar-gen3-scif", "renesas,scif";
1354			reg = <0 0xe6f30000 0 0x40>;
1355			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1356			clocks = <&cpg CPG_MOD 202>,
1357				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1358				 <&scif_clk>;
1359			clock-names = "fck", "brg_int", "scif_clk";
1360			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1361			       <&dmac2 0x5b>, <&dmac2 0x5a>;
1362			dma-names = "tx", "rx", "tx", "rx";
1363			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1364			resets = <&cpg 202>;
1365			status = "disabled";
1366		};
1367
1368		msiof0: spi@e6e90000 {
1369			compatible = "renesas,msiof-r8a774a1",
1370				     "renesas,rcar-gen3-msiof";
1371			reg = <0 0xe6e90000 0 0x0064>;
1372			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1373			clocks = <&cpg CPG_MOD 211>;
1374			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1375			       <&dmac2 0x41>, <&dmac2 0x40>;
1376			dma-names = "tx", "rx", "tx", "rx";
1377			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1378			resets = <&cpg 211>;
1379			#address-cells = <1>;
1380			#size-cells = <0>;
1381			status = "disabled";
1382		};
1383
1384		msiof1: spi@e6ea0000 {
1385			compatible = "renesas,msiof-r8a774a1",
1386				     "renesas,rcar-gen3-msiof";
1387			reg = <0 0xe6ea0000 0 0x0064>;
1388			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1389			clocks = <&cpg CPG_MOD 210>;
1390			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1391			       <&dmac2 0x43>, <&dmac2 0x42>;
1392			dma-names = "tx", "rx", "tx", "rx";
1393			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1394			resets = <&cpg 210>;
1395			#address-cells = <1>;
1396			#size-cells = <0>;
1397			status = "disabled";
1398		};
1399
1400		msiof2: spi@e6c00000 {
1401			compatible = "renesas,msiof-r8a774a1",
1402				     "renesas,rcar-gen3-msiof";
1403			reg = <0 0xe6c00000 0 0x0064>;
1404			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1405			clocks = <&cpg CPG_MOD 209>;
1406			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1407			dma-names = "tx", "rx";
1408			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1409			resets = <&cpg 209>;
1410			#address-cells = <1>;
1411			#size-cells = <0>;
1412			status = "disabled";
1413		};
1414
1415		msiof3: spi@e6c10000 {
1416			compatible = "renesas,msiof-r8a774a1",
1417				     "renesas,rcar-gen3-msiof";
1418			reg = <0 0xe6c10000 0 0x0064>;
1419			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1420			clocks = <&cpg CPG_MOD 208>;
1421			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1422			dma-names = "tx", "rx";
1423			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1424			resets = <&cpg 208>;
1425			#address-cells = <1>;
1426			#size-cells = <0>;
1427			status = "disabled";
1428		};
1429
1430		vin0: video@e6ef0000 {
1431			compatible = "renesas,vin-r8a774a1";
1432			reg = <0 0xe6ef0000 0 0x1000>;
1433			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1434			clocks = <&cpg CPG_MOD 811>;
1435			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1436			resets = <&cpg 811>;
1437			renesas,id = <0>;
1438			status = "disabled";
1439
1440			ports {
1441				#address-cells = <1>;
1442				#size-cells = <0>;
1443
1444				port@1 {
1445					#address-cells = <1>;
1446					#size-cells = <0>;
1447
1448					reg = <1>;
1449
1450					vin0csi20: endpoint@0 {
1451						reg = <0>;
1452						remote-endpoint = <&csi20vin0>;
1453					};
1454					vin0csi40: endpoint@2 {
1455						reg = <2>;
1456						remote-endpoint = <&csi40vin0>;
1457					};
1458				};
1459			};
1460		};
1461
1462		vin1: video@e6ef1000 {
1463			compatible = "renesas,vin-r8a774a1";
1464			reg = <0 0xe6ef1000 0 0x1000>;
1465			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1466			clocks = <&cpg CPG_MOD 810>;
1467			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1468			resets = <&cpg 810>;
1469			renesas,id = <1>;
1470			status = "disabled";
1471
1472			ports {
1473				#address-cells = <1>;
1474				#size-cells = <0>;
1475
1476				port@1 {
1477					#address-cells = <1>;
1478					#size-cells = <0>;
1479
1480					reg = <1>;
1481
1482					vin1csi20: endpoint@0 {
1483						reg = <0>;
1484						remote-endpoint = <&csi20vin1>;
1485					};
1486					vin1csi40: endpoint@2 {
1487						reg = <2>;
1488						remote-endpoint = <&csi40vin1>;
1489					};
1490				};
1491			};
1492		};
1493
1494		vin2: video@e6ef2000 {
1495			compatible = "renesas,vin-r8a774a1";
1496			reg = <0 0xe6ef2000 0 0x1000>;
1497			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1498			clocks = <&cpg CPG_MOD 809>;
1499			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1500			resets = <&cpg 809>;
1501			renesas,id = <2>;
1502			status = "disabled";
1503
1504			ports {
1505				#address-cells = <1>;
1506				#size-cells = <0>;
1507
1508				port@1 {
1509					#address-cells = <1>;
1510					#size-cells = <0>;
1511
1512					reg = <1>;
1513
1514					vin2csi20: endpoint@0 {
1515						reg = <0>;
1516						remote-endpoint = <&csi20vin2>;
1517					};
1518					vin2csi40: endpoint@2 {
1519						reg = <2>;
1520						remote-endpoint = <&csi40vin2>;
1521					};
1522				};
1523			};
1524		};
1525
1526		vin3: video@e6ef3000 {
1527			compatible = "renesas,vin-r8a774a1";
1528			reg = <0 0xe6ef3000 0 0x1000>;
1529			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1530			clocks = <&cpg CPG_MOD 808>;
1531			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1532			resets = <&cpg 808>;
1533			renesas,id = <3>;
1534			status = "disabled";
1535
1536			ports {
1537				#address-cells = <1>;
1538				#size-cells = <0>;
1539
1540				port@1 {
1541					#address-cells = <1>;
1542					#size-cells = <0>;
1543
1544					reg = <1>;
1545
1546					vin3csi20: endpoint@0 {
1547						reg = <0>;
1548						remote-endpoint = <&csi20vin3>;
1549					};
1550					vin3csi40: endpoint@2 {
1551						reg = <2>;
1552						remote-endpoint = <&csi40vin3>;
1553					};
1554				};
1555			};
1556		};
1557
1558		vin4: video@e6ef4000 {
1559			compatible = "renesas,vin-r8a774a1";
1560			reg = <0 0xe6ef4000 0 0x1000>;
1561			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1562			clocks = <&cpg CPG_MOD 807>;
1563			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1564			resets = <&cpg 807>;
1565			renesas,id = <4>;
1566			status = "disabled";
1567
1568			ports {
1569				#address-cells = <1>;
1570				#size-cells = <0>;
1571
1572				port@1 {
1573					#address-cells = <1>;
1574					#size-cells = <0>;
1575
1576					reg = <1>;
1577
1578					vin4csi20: endpoint@0 {
1579						reg = <0>;
1580						remote-endpoint = <&csi20vin4>;
1581					};
1582					vin4csi40: endpoint@2 {
1583						reg = <2>;
1584						remote-endpoint = <&csi40vin4>;
1585					};
1586				};
1587			};
1588		};
1589
1590		vin5: video@e6ef5000 {
1591			compatible = "renesas,vin-r8a774a1";
1592			reg = <0 0xe6ef5000 0 0x1000>;
1593			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1594			clocks = <&cpg CPG_MOD 806>;
1595			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1596			resets = <&cpg 806>;
1597			renesas,id = <5>;
1598			status = "disabled";
1599
1600			ports {
1601				#address-cells = <1>;
1602				#size-cells = <0>;
1603
1604				port@1 {
1605					#address-cells = <1>;
1606					#size-cells = <0>;
1607
1608					reg = <1>;
1609
1610					vin5csi20: endpoint@0 {
1611						reg = <0>;
1612						remote-endpoint = <&csi20vin5>;
1613					};
1614					vin5csi40: endpoint@2 {
1615						reg = <2>;
1616						remote-endpoint = <&csi40vin5>;
1617					};
1618				};
1619			};
1620		};
1621
1622		vin6: video@e6ef6000 {
1623			compatible = "renesas,vin-r8a774a1";
1624			reg = <0 0xe6ef6000 0 0x1000>;
1625			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1626			clocks = <&cpg CPG_MOD 805>;
1627			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1628			resets = <&cpg 805>;
1629			renesas,id = <6>;
1630			status = "disabled";
1631
1632			ports {
1633				#address-cells = <1>;
1634				#size-cells = <0>;
1635
1636				port@1 {
1637					#address-cells = <1>;
1638					#size-cells = <0>;
1639
1640					reg = <1>;
1641
1642					vin6csi20: endpoint@0 {
1643						reg = <0>;
1644						remote-endpoint = <&csi20vin6>;
1645					};
1646					vin6csi40: endpoint@2 {
1647						reg = <2>;
1648						remote-endpoint = <&csi40vin6>;
1649					};
1650				};
1651			};
1652		};
1653
1654		vin7: video@e6ef7000 {
1655			compatible = "renesas,vin-r8a774a1";
1656			reg = <0 0xe6ef7000 0 0x1000>;
1657			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1658			clocks = <&cpg CPG_MOD 804>;
1659			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1660			resets = <&cpg 804>;
1661			renesas,id = <7>;
1662			status = "disabled";
1663
1664			ports {
1665				#address-cells = <1>;
1666				#size-cells = <0>;
1667
1668				port@1 {
1669					#address-cells = <1>;
1670					#size-cells = <0>;
1671
1672					reg = <1>;
1673
1674					vin7csi20: endpoint@0 {
1675						reg = <0>;
1676						remote-endpoint = <&csi20vin7>;
1677					};
1678					vin7csi40: endpoint@2 {
1679						reg = <2>;
1680						remote-endpoint = <&csi40vin7>;
1681					};
1682				};
1683			};
1684		};
1685
1686		rcar_sound: sound@ec500000 {
1687			/*
1688			 * #sound-dai-cells is required
1689			 *
1690			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
1691			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
1692			 */
1693			/*
1694			 * #clock-cells is required for audio_clkout0/1/2/3
1695			 *
1696			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
1697			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
1698			 */
1699			compatible =  "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1700			reg =	<0 0xec500000 0 0x1000>, /* SCU */
1701				<0 0xec5a0000 0 0x100>,  /* ADG */
1702				<0 0xec540000 0 0x1000>, /* SSIU */
1703				<0 0xec541000 0 0x280>,  /* SSI */
1704				<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
1705			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1706
1707			clocks = <&cpg CPG_MOD 1005>,
1708				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1709				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1710				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1711				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1712				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1713				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1714				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1715				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1716				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1717				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1718				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1719				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1720				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1721				 <&audio_clk_a>, <&audio_clk_b>,
1722				 <&audio_clk_c>,
1723				 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
1724			clock-names = "ssi-all",
1725				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1726				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1727				      "ssi.1", "ssi.0",
1728				      "src.9", "src.8", "src.7", "src.6",
1729				      "src.5", "src.4", "src.3", "src.2",
1730				      "src.1", "src.0",
1731				      "mix.1", "mix.0",
1732				      "ctu.1", "ctu.0",
1733				      "dvc.0", "dvc.1",
1734				      "clk_a", "clk_b", "clk_c", "clk_i";
1735			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1736			resets = <&cpg 1005>,
1737				 <&cpg 1006>, <&cpg 1007>,
1738				 <&cpg 1008>, <&cpg 1009>,
1739				 <&cpg 1010>, <&cpg 1011>,
1740				 <&cpg 1012>, <&cpg 1013>,
1741				 <&cpg 1014>, <&cpg 1015>;
1742			reset-names = "ssi-all",
1743				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1744				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1745				      "ssi.1", "ssi.0";
1746			status = "disabled";
1747
1748			rcar_sound,ctu {
1749				ctu00: ctu-0 { };
1750				ctu01: ctu-1 { };
1751				ctu02: ctu-2 { };
1752				ctu03: ctu-3 { };
1753				ctu10: ctu-4 { };
1754				ctu11: ctu-5 { };
1755				ctu12: ctu-6 { };
1756				ctu13: ctu-7 { };
1757			};
1758
1759			rcar_sound,dvc {
1760				dvc0: dvc-0 {
1761					dmas = <&audma1 0xbc>;
1762					dma-names = "tx";
1763				};
1764				dvc1: dvc-1 {
1765					dmas = <&audma1 0xbe>;
1766					dma-names = "tx";
1767				};
1768			};
1769
1770			rcar_sound,mix {
1771				mix0: mix-0 { };
1772				mix1: mix-1 { };
1773			};
1774
1775			rcar_sound,src {
1776				src0: src-0 {
1777					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1778					dmas = <&audma0 0x85>, <&audma1 0x9a>;
1779					dma-names = "rx", "tx";
1780				};
1781				src1: src-1 {
1782					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1783					dmas = <&audma0 0x87>, <&audma1 0x9c>;
1784					dma-names = "rx", "tx";
1785				};
1786				src2: src-2 {
1787					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1788					dmas = <&audma0 0x89>, <&audma1 0x9e>;
1789					dma-names = "rx", "tx";
1790				};
1791				src3: src-3 {
1792					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1793					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1794					dma-names = "rx", "tx";
1795				};
1796				src4: src-4 {
1797					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1798					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1799					dma-names = "rx", "tx";
1800				};
1801				src5: src-5 {
1802					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1803					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1804					dma-names = "rx", "tx";
1805				};
1806				src6: src-6 {
1807					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1808					dmas = <&audma0 0x91>, <&audma1 0xb4>;
1809					dma-names = "rx", "tx";
1810				};
1811				src7: src-7 {
1812					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1813					dmas = <&audma0 0x93>, <&audma1 0xb6>;
1814					dma-names = "rx", "tx";
1815				};
1816				src8: src-8 {
1817					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1818					dmas = <&audma0 0x95>, <&audma1 0xb8>;
1819					dma-names = "rx", "tx";
1820				};
1821				src9: src-9 {
1822					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1823					dmas = <&audma0 0x97>, <&audma1 0xba>;
1824					dma-names = "rx", "tx";
1825				};
1826			};
1827
1828			rcar_sound,ssi {
1829				ssi0: ssi-0 {
1830					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1831					dmas = <&audma0 0x01>, <&audma1 0x02>;
1832					dma-names = "rx", "tx";
1833				};
1834				ssi1: ssi-1 {
1835					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1836					dmas = <&audma0 0x03>, <&audma1 0x04>;
1837					dma-names = "rx", "tx";
1838				};
1839				ssi2: ssi-2 {
1840					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1841					dmas = <&audma0 0x05>, <&audma1 0x06>;
1842					dma-names = "rx", "tx";
1843				};
1844				ssi3: ssi-3 {
1845					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1846					dmas = <&audma0 0x07>, <&audma1 0x08>;
1847					dma-names = "rx", "tx";
1848				};
1849				ssi4: ssi-4 {
1850					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1851					dmas = <&audma0 0x09>, <&audma1 0x0a>;
1852					dma-names = "rx", "tx";
1853				};
1854				ssi5: ssi-5 {
1855					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1856					dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1857					dma-names = "rx", "tx";
1858				};
1859				ssi6: ssi-6 {
1860					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1861					dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1862					dma-names = "rx", "tx";
1863				};
1864				ssi7: ssi-7 {
1865					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1866					dmas = <&audma0 0x0f>, <&audma1 0x10>;
1867					dma-names = "rx", "tx";
1868				};
1869				ssi8: ssi-8 {
1870					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1871					dmas = <&audma0 0x11>, <&audma1 0x12>;
1872					dma-names = "rx", "tx";
1873				};
1874				ssi9: ssi-9 {
1875					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1876					dmas = <&audma0 0x13>, <&audma1 0x14>;
1877					dma-names = "rx", "tx";
1878				};
1879			};
1880
1881			rcar_sound,ssiu {
1882				ssiu00: ssiu-0 {
1883					dmas = <&audma0 0x15>, <&audma1 0x16>;
1884					dma-names = "rx", "tx";
1885				};
1886				ssiu01: ssiu-1 {
1887					dmas = <&audma0 0x35>, <&audma1 0x36>;
1888					dma-names = "rx", "tx";
1889				};
1890				ssiu02: ssiu-2 {
1891					dmas = <&audma0 0x37>, <&audma1 0x38>;
1892					dma-names = "rx", "tx";
1893				};
1894				ssiu03: ssiu-3 {
1895					dmas = <&audma0 0x47>, <&audma1 0x48>;
1896					dma-names = "rx", "tx";
1897				};
1898				ssiu04: ssiu-4 {
1899					dmas = <&audma0 0x3F>, <&audma1 0x40>;
1900					dma-names = "rx", "tx";
1901				};
1902				ssiu05: ssiu-5 {
1903					dmas = <&audma0 0x43>, <&audma1 0x44>;
1904					dma-names = "rx", "tx";
1905				};
1906				ssiu06: ssiu-6 {
1907					dmas = <&audma0 0x4F>, <&audma1 0x50>;
1908					dma-names = "rx", "tx";
1909				};
1910				ssiu07: ssiu-7 {
1911					dmas = <&audma0 0x53>, <&audma1 0x54>;
1912					dma-names = "rx", "tx";
1913				};
1914				ssiu10: ssiu-8 {
1915					dmas = <&audma0 0x49>, <&audma1 0x4a>;
1916					dma-names = "rx", "tx";
1917				};
1918				ssiu11: ssiu-9 {
1919					dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1920					dma-names = "rx", "tx";
1921				};
1922				ssiu12: ssiu-10 {
1923					dmas = <&audma0 0x57>, <&audma1 0x58>;
1924					dma-names = "rx", "tx";
1925				};
1926				ssiu13: ssiu-11 {
1927					dmas = <&audma0 0x59>, <&audma1 0x5A>;
1928					dma-names = "rx", "tx";
1929				};
1930				ssiu14: ssiu-12 {
1931					dmas = <&audma0 0x5F>, <&audma1 0x60>;
1932					dma-names = "rx", "tx";
1933				};
1934				ssiu15: ssiu-13 {
1935					dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1936					dma-names = "rx", "tx";
1937				};
1938				ssiu16: ssiu-14 {
1939					dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1940					dma-names = "rx", "tx";
1941				};
1942				ssiu17: ssiu-15 {
1943					dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1944					dma-names = "rx", "tx";
1945				};
1946				ssiu20: ssiu-16 {
1947					dmas = <&audma0 0x63>, <&audma1 0x64>;
1948					dma-names = "rx", "tx";
1949				};
1950				ssiu21: ssiu-17 {
1951					dmas = <&audma0 0x67>, <&audma1 0x68>;
1952					dma-names = "rx", "tx";
1953				};
1954				ssiu22: ssiu-18 {
1955					dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1956					dma-names = "rx", "tx";
1957				};
1958				ssiu23: ssiu-19 {
1959					dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1960					dma-names = "rx", "tx";
1961				};
1962				ssiu24: ssiu-20 {
1963					dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1964					dma-names = "rx", "tx";
1965				};
1966				ssiu25: ssiu-21 {
1967					dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1968					dma-names = "rx", "tx";
1969				};
1970				ssiu26: ssiu-22 {
1971					dmas = <&audma0 0xED>, <&audma1 0xEE>;
1972					dma-names = "rx", "tx";
1973				};
1974				ssiu27: ssiu-23 {
1975					dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1976					dma-names = "rx", "tx";
1977				};
1978				ssiu30: ssiu-24 {
1979					dmas = <&audma0 0x6f>, <&audma1 0x70>;
1980					dma-names = "rx", "tx";
1981				};
1982				ssiu31: ssiu-25 {
1983					dmas = <&audma0 0x21>, <&audma1 0x22>;
1984					dma-names = "rx", "tx";
1985				};
1986				ssiu32: ssiu-26 {
1987					dmas = <&audma0 0x23>, <&audma1 0x24>;
1988					dma-names = "rx", "tx";
1989				};
1990				ssiu33: ssiu-27 {
1991					dmas = <&audma0 0x25>, <&audma1 0x26>;
1992					dma-names = "rx", "tx";
1993				};
1994				ssiu34: ssiu-28 {
1995					dmas = <&audma0 0x27>, <&audma1 0x28>;
1996					dma-names = "rx", "tx";
1997				};
1998				ssiu35: ssiu-29 {
1999					dmas = <&audma0 0x29>, <&audma1 0x2A>;
2000					dma-names = "rx", "tx";
2001				};
2002				ssiu36: ssiu-30 {
2003					dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2004					dma-names = "rx", "tx";
2005				};
2006				ssiu37: ssiu-31 {
2007					dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2008					dma-names = "rx", "tx";
2009				};
2010				ssiu40: ssiu-32 {
2011					dmas =	<&audma0 0x71>, <&audma1 0x72>;
2012					dma-names = "rx", "tx";
2013				};
2014				ssiu41: ssiu-33 {
2015					dmas = <&audma0 0x17>, <&audma1 0x18>;
2016					dma-names = "rx", "tx";
2017				};
2018				ssiu42: ssiu-34 {
2019					dmas = <&audma0 0x19>, <&audma1 0x1A>;
2020					dma-names = "rx", "tx";
2021				};
2022				ssiu43: ssiu-35 {
2023					dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2024					dma-names = "rx", "tx";
2025				};
2026				ssiu44: ssiu-36 {
2027					dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2028					dma-names = "rx", "tx";
2029				};
2030				ssiu45: ssiu-37 {
2031					dmas = <&audma0 0x1F>, <&audma1 0x20>;
2032					dma-names = "rx", "tx";
2033				};
2034				ssiu46: ssiu-38 {
2035					dmas = <&audma0 0x31>, <&audma1 0x32>;
2036					dma-names = "rx", "tx";
2037				};
2038				ssiu47: ssiu-39 {
2039					dmas = <&audma0 0x33>, <&audma1 0x34>;
2040					dma-names = "rx", "tx";
2041				};
2042				ssiu50: ssiu-40 {
2043					dmas = <&audma0 0x73>, <&audma1 0x74>;
2044					dma-names = "rx", "tx";
2045				};
2046				ssiu60: ssiu-41 {
2047					dmas = <&audma0 0x75>, <&audma1 0x76>;
2048					dma-names = "rx", "tx";
2049				};
2050				ssiu70: ssiu-42 {
2051					dmas = <&audma0 0x79>, <&audma1 0x7a>;
2052					dma-names = "rx", "tx";
2053				};
2054				ssiu80: ssiu-43 {
2055					dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2056					dma-names = "rx", "tx";
2057				};
2058				ssiu90: ssiu-44 {
2059					dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2060					dma-names = "rx", "tx";
2061				};
2062				ssiu91: ssiu-45 {
2063					dmas = <&audma0 0x7F>, <&audma1 0x80>;
2064					dma-names = "rx", "tx";
2065				};
2066				ssiu92: ssiu-46 {
2067					dmas = <&audma0 0x81>, <&audma1 0x82>;
2068					dma-names = "rx", "tx";
2069				};
2070				ssiu93: ssiu-47 {
2071					dmas = <&audma0 0x83>, <&audma1 0x84>;
2072					dma-names = "rx", "tx";
2073				};
2074				ssiu94: ssiu-48 {
2075					dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2076					dma-names = "rx", "tx";
2077				};
2078				ssiu95: ssiu-49 {
2079					dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2080					dma-names = "rx", "tx";
2081				};
2082				ssiu96: ssiu-50 {
2083					dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2084					dma-names = "rx", "tx";
2085				};
2086				ssiu97: ssiu-51 {
2087					dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2088					dma-names = "rx", "tx";
2089				};
2090			};
2091		};
2092
2093		audma0: dma-controller@ec700000 {
2094			compatible = "renesas,dmac-r8a774a1",
2095				     "renesas,rcar-dmac";
2096			reg = <0 0xec700000 0 0x10000>;
2097			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2098				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2099				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2100				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2101				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2102				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2103				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2104				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2105				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2106				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2107				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2108				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2109				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2110				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2111				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2112				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2113				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2114			interrupt-names = "error",
2115					"ch0", "ch1", "ch2", "ch3",
2116					"ch4", "ch5", "ch6", "ch7",
2117					"ch8", "ch9", "ch10", "ch11",
2118					"ch12", "ch13", "ch14", "ch15";
2119			clocks = <&cpg CPG_MOD 502>;
2120			clock-names = "fck";
2121			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2122			resets = <&cpg 502>;
2123			#dma-cells = <1>;
2124			dma-channels = <16>;
2125			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2126			       <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2127			       <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2128			       <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2129			       <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2130			       <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2131			       <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2132			       <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2133		};
2134
2135		audma1: dma-controller@ec720000 {
2136			compatible = "renesas,dmac-r8a774a1",
2137				     "renesas,rcar-dmac";
2138			reg = <0 0xec720000 0 0x10000>;
2139			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2140				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2141				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2142				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2143				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2144				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2145				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2146				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2147				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2148				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2149				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2150				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2151				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2152				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2153				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2154				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2155				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2156			interrupt-names = "error",
2157					"ch0", "ch1", "ch2", "ch3",
2158					"ch4", "ch5", "ch6", "ch7",
2159					"ch8", "ch9", "ch10", "ch11",
2160					"ch12", "ch13", "ch14", "ch15";
2161			clocks = <&cpg CPG_MOD 501>;
2162			clock-names = "fck";
2163			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2164			resets = <&cpg 501>;
2165			#dma-cells = <1>;
2166			dma-channels = <16>;
2167			iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2168			       <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2169			       <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2170			       <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2171			       <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2172			       <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2173			       <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2174			       <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2175		};
2176
2177		xhci0: usb@ee000000 {
2178			compatible = "renesas,xhci-r8a774a1",
2179				     "renesas,rcar-gen3-xhci";
2180			reg = <0 0xee000000 0 0xc00>;
2181			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2182			clocks = <&cpg CPG_MOD 328>;
2183			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2184			resets = <&cpg 328>;
2185			status = "disabled";
2186		};
2187
2188		usb3_peri0: usb@ee020000 {
2189			compatible = "renesas,r8a774a1-usb3-peri",
2190				     "renesas,rcar-gen3-usb3-peri";
2191			reg = <0 0xee020000 0 0x400>;
2192			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2193			clocks = <&cpg CPG_MOD 328>;
2194			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2195			resets = <&cpg 328>;
2196			status = "disabled";
2197		};
2198
2199		ohci0: usb@ee080000 {
2200			compatible = "generic-ohci";
2201			reg = <0 0xee080000 0 0x100>;
2202			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2203			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2204			phys = <&usb2_phy0 1>;
2205			phy-names = "usb";
2206			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2207			resets = <&cpg 703>, <&cpg 704>;
2208			status = "disabled";
2209		};
2210
2211		ohci1: usb@ee0a0000 {
2212			compatible = "generic-ohci";
2213			reg = <0 0xee0a0000 0 0x100>;
2214			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2215			clocks = <&cpg CPG_MOD 702>;
2216			phys = <&usb2_phy1 1>;
2217			phy-names = "usb";
2218			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2219			resets = <&cpg 702>;
2220			status = "disabled";
2221		};
2222
2223		ehci0: usb@ee080100 {
2224			compatible = "generic-ehci";
2225			reg = <0 0xee080100 0 0x100>;
2226			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2227			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2228			phys = <&usb2_phy0 2>;
2229			phy-names = "usb";
2230			companion = <&ohci0>;
2231			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2232			resets = <&cpg 703>, <&cpg 704>;
2233			status = "disabled";
2234		};
2235
2236		ehci1: usb@ee0a0100 {
2237			compatible = "generic-ehci";
2238			reg = <0 0xee0a0100 0 0x100>;
2239			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2240			clocks = <&cpg CPG_MOD 702>;
2241			phys = <&usb2_phy1 2>;
2242			phy-names = "usb";
2243			companion = <&ohci1>;
2244			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2245			resets = <&cpg 702>;
2246			status = "disabled";
2247		};
2248
2249		usb2_phy0: usb-phy@ee080200 {
2250			compatible = "renesas,usb2-phy-r8a774a1",
2251				     "renesas,rcar-gen3-usb2-phy";
2252			reg = <0 0xee080200 0 0x700>;
2253			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2254			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2255			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2256			resets = <&cpg 703>, <&cpg 704>;
2257			#phy-cells = <1>;
2258			status = "disabled";
2259		};
2260
2261		usb2_phy1: usb-phy@ee0a0200 {
2262			compatible = "renesas,usb2-phy-r8a774a1",
2263				     "renesas,rcar-gen3-usb2-phy";
2264			reg = <0 0xee0a0200 0 0x700>;
2265			clocks = <&cpg CPG_MOD 702>;
2266			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2267			resets = <&cpg 702>;
2268			#phy-cells = <1>;
2269			status = "disabled";
2270		};
2271
2272		sdhi0: mmc@ee100000 {
2273			compatible = "renesas,sdhi-r8a774a1",
2274				     "renesas,rcar-gen3-sdhi";
2275			reg = <0 0xee100000 0 0x2000>;
2276			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2277			clocks = <&cpg CPG_MOD 314>;
2278			max-frequency = <200000000>;
2279			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2280			resets = <&cpg 314>;
2281			status = "disabled";
2282		};
2283
2284		sdhi1: mmc@ee120000 {
2285			compatible = "renesas,sdhi-r8a774a1",
2286				     "renesas,rcar-gen3-sdhi";
2287			reg = <0 0xee120000 0 0x2000>;
2288			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2289			clocks = <&cpg CPG_MOD 313>;
2290			max-frequency = <200000000>;
2291			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2292			resets = <&cpg 313>;
2293			status = "disabled";
2294		};
2295
2296		sdhi2: mmc@ee140000 {
2297			compatible = "renesas,sdhi-r8a774a1",
2298				     "renesas,rcar-gen3-sdhi";
2299			reg = <0 0xee140000 0 0x2000>;
2300			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2301			clocks = <&cpg CPG_MOD 312>;
2302			max-frequency = <200000000>;
2303			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2304			resets = <&cpg 312>;
2305			status = "disabled";
2306		};
2307
2308		sdhi3: mmc@ee160000 {
2309			compatible = "renesas,sdhi-r8a774a1",
2310				     "renesas,rcar-gen3-sdhi";
2311			reg = <0 0xee160000 0 0x2000>;
2312			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2313			clocks = <&cpg CPG_MOD 311>;
2314			max-frequency = <200000000>;
2315			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2316			resets = <&cpg 311>;
2317			status = "disabled";
2318		};
2319
2320		rpc: spi@ee200000 {
2321			compatible = "renesas,r8a774a1-rpc-if",
2322				     "renesas,rcar-gen3-rpc-if";
2323			reg = <0 0xee200000 0 0x200>,
2324			      <0 0x08000000 0 0x4000000>,
2325			      <0 0xee208000 0 0x100>;
2326			reg-names = "regs", "dirmap", "wbuf";
2327			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2328			clocks = <&cpg CPG_MOD 917>;
2329			clock-names = "rpc";
2330			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2331			resets = <&cpg 917>;
2332			#address-cells = <1>;
2333			#size-cells = <0>;
2334			status = "disabled";
2335		};
2336
2337		gic: interrupt-controller@f1010000 {
2338			compatible = "arm,gic-400";
2339			#interrupt-cells = <3>;
2340			#address-cells = <0>;
2341			interrupt-controller;
2342			reg = <0x0 0xf1010000 0 0x1000>,
2343			      <0x0 0xf1020000 0 0x20000>,
2344			      <0x0 0xf1040000 0 0x20000>,
2345			      <0x0 0xf1060000 0 0x20000>;
2346			interrupts = <GIC_PPI 9
2347					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2348			clocks = <&cpg CPG_MOD 408>;
2349			clock-names = "clk";
2350			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2351			resets = <&cpg 408>;
2352		};
2353
2354		pciec0: pcie@fe000000 {
2355			compatible = "renesas,pcie-r8a774a1",
2356				     "renesas,pcie-rcar-gen3";
2357			reg = <0 0xfe000000 0 0x80000>;
2358			#address-cells = <3>;
2359			#size-cells = <2>;
2360			bus-range = <0x00 0xff>;
2361			device_type = "pci";
2362			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2363				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2364				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2365				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2366			/* Map all possible DDR as inbound ranges */
2367			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2368			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2369				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2370				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2371			#interrupt-cells = <1>;
2372			interrupt-map-mask = <0 0 0 0>;
2373			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2374			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2375			clock-names = "pcie", "pcie_bus";
2376			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2377			resets = <&cpg 319>;
2378			status = "disabled";
2379		};
2380
2381		pciec1: pcie@ee800000 {
2382			compatible = "renesas,pcie-r8a774a1",
2383				     "renesas,pcie-rcar-gen3";
2384			reg = <0 0xee800000 0 0x80000>;
2385			#address-cells = <3>;
2386			#size-cells = <2>;
2387			bus-range = <0x00 0xff>;
2388			device_type = "pci";
2389			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2390				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2391				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2392				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2393			/* Map all possible DDR as inbound ranges */
2394			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2395			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2396				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2397				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2398			#interrupt-cells = <1>;
2399			interrupt-map-mask = <0 0 0 0>;
2400			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2401			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2402			clock-names = "pcie", "pcie_bus";
2403			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2404			resets = <&cpg 318>;
2405			status = "disabled";
2406		};
2407
2408		pciec0_ep: pcie-ep@fe000000 {
2409			compatible = "renesas,r8a774a1-pcie-ep",
2410				     "renesas,rcar-gen3-pcie-ep";
2411			reg = <0x0 0xfe000000 0 0x80000>,
2412			      <0x0 0xfe100000 0 0x100000>,
2413			      <0x0 0xfe200000 0 0x200000>,
2414			      <0x0 0x30000000 0 0x8000000>,
2415			      <0x0 0x38000000 0 0x8000000>;
2416			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2417			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2418				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2419				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2420			clocks = <&cpg CPG_MOD 319>;
2421			clock-names = "pcie";
2422			resets = <&cpg 319>;
2423			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2424			status = "disabled";
2425		};
2426
2427		pciec1_ep: pcie-ep@ee800000 {
2428			compatible = "renesas,r8a774a1-pcie-ep",
2429				     "renesas,rcar-gen3-pcie-ep";
2430			reg = <0x0 0xee800000 0 0x80000>,
2431			      <0x0 0xee900000 0 0x100000>,
2432			      <0x0 0xeea00000 0 0x200000>,
2433			      <0x0 0xc0000000 0 0x8000000>,
2434			      <0x0 0xc8000000 0 0x8000000>;
2435			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2436			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2437				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2438				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2439			clocks = <&cpg CPG_MOD 318>;
2440			clock-names = "pcie";
2441			resets = <&cpg 318>;
2442			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2443			status = "disabled";
2444		};
2445
2446		fdp1@fe940000 {
2447			compatible = "renesas,fdp1";
2448			reg = <0 0xfe940000 0 0x2400>;
2449			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2450			clocks = <&cpg CPG_MOD 119>;
2451			power-domains = <&sysc R8A774A1_PD_A3VC>;
2452			resets = <&cpg 119>;
2453			renesas,fcp = <&fcpf0>;
2454		};
2455
2456		fcpf0: fcp@fe950000 {
2457			compatible = "renesas,fcpf";
2458			reg = <0 0xfe950000 0 0x200>;
2459			clocks = <&cpg CPG_MOD 615>;
2460			power-domains = <&sysc R8A774A1_PD_A3VC>;
2461			resets = <&cpg 615>;
2462		};
2463
2464		fcpvb0: fcp@fe96f000 {
2465			compatible = "renesas,fcpv";
2466			reg = <0 0xfe96f000 0 0x200>;
2467			clocks = <&cpg CPG_MOD 607>;
2468			power-domains = <&sysc R8A774A1_PD_A3VC>;
2469			resets = <&cpg 607>;
2470		};
2471
2472		fcpvd0: fcp@fea27000 {
2473			compatible = "renesas,fcpv";
2474			reg = <0 0xfea27000 0 0x200>;
2475			clocks = <&cpg CPG_MOD 603>;
2476			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2477			resets = <&cpg 603>;
2478			iommus = <&ipmmu_vi0 8>;
2479		};
2480
2481		fcpvd1: fcp@fea2f000 {
2482			compatible = "renesas,fcpv";
2483			reg = <0 0xfea2f000 0 0x200>;
2484			clocks = <&cpg CPG_MOD 602>;
2485			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2486			resets = <&cpg 602>;
2487			iommus = <&ipmmu_vi0 9>;
2488		};
2489
2490		fcpvd2: fcp@fea37000 {
2491			compatible = "renesas,fcpv";
2492			reg = <0 0xfea37000 0 0x200>;
2493			clocks = <&cpg CPG_MOD 601>;
2494			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2495			resets = <&cpg 601>;
2496			iommus = <&ipmmu_vi0 10>;
2497		};
2498
2499		fcpvi0: fcp@fe9af000 {
2500			compatible = "renesas,fcpv";
2501			reg = <0 0xfe9af000 0 0x200>;
2502			clocks = <&cpg CPG_MOD 611>;
2503			power-domains = <&sysc R8A774A1_PD_A3VC>;
2504			resets = <&cpg 611>;
2505			iommus = <&ipmmu_vc0 19>;
2506		};
2507
2508		vspb: vsp@fe960000 {
2509			compatible = "renesas,vsp2";
2510			reg = <0 0xfe960000 0 0x8000>;
2511			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2512			clocks = <&cpg CPG_MOD 626>;
2513			power-domains = <&sysc R8A774A1_PD_A3VC>;
2514			resets = <&cpg 626>;
2515
2516			renesas,fcp = <&fcpvb0>;
2517		};
2518
2519		vspd0: vsp@fea20000 {
2520			compatible = "renesas,vsp2";
2521			reg = <0 0xfea20000 0 0x5000>;
2522			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2523			clocks = <&cpg CPG_MOD 623>;
2524			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2525			resets = <&cpg 623>;
2526
2527			renesas,fcp = <&fcpvd0>;
2528		};
2529
2530		vspd1: vsp@fea28000 {
2531			compatible = "renesas,vsp2";
2532			reg = <0 0xfea28000 0 0x5000>;
2533			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2534			clocks = <&cpg CPG_MOD 622>;
2535			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2536			resets = <&cpg 622>;
2537
2538			renesas,fcp = <&fcpvd1>;
2539		};
2540
2541		vspd2: vsp@fea30000 {
2542			compatible = "renesas,vsp2";
2543			reg = <0 0xfea30000 0 0x5000>;
2544			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2545			clocks = <&cpg CPG_MOD 621>;
2546			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2547			resets = <&cpg 621>;
2548
2549			renesas,fcp = <&fcpvd2>;
2550		};
2551
2552		vspi0: vsp@fe9a0000 {
2553			compatible = "renesas,vsp2";
2554			reg = <0 0xfe9a0000 0 0x8000>;
2555			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2556			clocks = <&cpg CPG_MOD 631>;
2557			power-domains = <&sysc R8A774A1_PD_A3VC>;
2558			resets = <&cpg 631>;
2559
2560			renesas,fcp = <&fcpvi0>;
2561		};
2562
2563		csi20: csi2@fea80000 {
2564			compatible = "renesas,r8a774a1-csi2";
2565			reg = <0 0xfea80000 0 0x10000>;
2566			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2567			clocks = <&cpg CPG_MOD 714>;
2568			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2569			resets = <&cpg 714>;
2570			status = "disabled";
2571
2572			ports {
2573				#address-cells = <1>;
2574				#size-cells = <0>;
2575
2576				port@1 {
2577					#address-cells = <1>;
2578					#size-cells = <0>;
2579
2580					reg = <1>;
2581
2582					csi20vin0: endpoint@0 {
2583						reg = <0>;
2584						remote-endpoint = <&vin0csi20>;
2585					};
2586					csi20vin1: endpoint@1 {
2587						reg = <1>;
2588						remote-endpoint = <&vin1csi20>;
2589					};
2590					csi20vin2: endpoint@2 {
2591						reg = <2>;
2592						remote-endpoint = <&vin2csi20>;
2593					};
2594					csi20vin3: endpoint@3 {
2595						reg = <3>;
2596						remote-endpoint = <&vin3csi20>;
2597					};
2598					csi20vin4: endpoint@4 {
2599						reg = <4>;
2600						remote-endpoint = <&vin4csi20>;
2601					};
2602					csi20vin5: endpoint@5 {
2603						reg = <5>;
2604						remote-endpoint = <&vin5csi20>;
2605					};
2606					csi20vin6: endpoint@6 {
2607						reg = <6>;
2608						remote-endpoint = <&vin6csi20>;
2609					};
2610					csi20vin7: endpoint@7 {
2611						reg = <7>;
2612						remote-endpoint = <&vin7csi20>;
2613					};
2614				};
2615			};
2616		};
2617
2618		csi40: csi2@feaa0000 {
2619			compatible = "renesas,r8a774a1-csi2";
2620			reg = <0 0xfeaa0000 0 0x10000>;
2621			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2622			clocks = <&cpg CPG_MOD 716>;
2623			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2624			resets = <&cpg 716>;
2625			status = "disabled";
2626
2627			ports {
2628				#address-cells = <1>;
2629				#size-cells = <0>;
2630
2631				port@1 {
2632					#address-cells = <1>;
2633					#size-cells = <0>;
2634
2635					reg = <1>;
2636
2637					csi40vin0: endpoint@0 {
2638						reg = <0>;
2639						remote-endpoint = <&vin0csi40>;
2640					};
2641					csi40vin1: endpoint@1 {
2642						reg = <1>;
2643						remote-endpoint = <&vin1csi40>;
2644					};
2645					csi40vin2: endpoint@2 {
2646						reg = <2>;
2647						remote-endpoint = <&vin2csi40>;
2648					};
2649					csi40vin3: endpoint@3 {
2650						reg = <3>;
2651						remote-endpoint = <&vin3csi40>;
2652					};
2653					csi40vin4: endpoint@4 {
2654						reg = <4>;
2655						remote-endpoint = <&vin4csi40>;
2656					};
2657					csi40vin5: endpoint@5 {
2658						reg = <5>;
2659						remote-endpoint = <&vin5csi40>;
2660					};
2661					csi40vin6: endpoint@6 {
2662						reg = <6>;
2663						remote-endpoint = <&vin6csi40>;
2664					};
2665					csi40vin7: endpoint@7 {
2666						reg = <7>;
2667						remote-endpoint = <&vin7csi40>;
2668					};
2669				};
2670
2671			};
2672		};
2673
2674		hdmi0: hdmi@fead0000 {
2675			compatible = "renesas,r8a774a1-hdmi",
2676				     "renesas,rcar-gen3-hdmi";
2677			reg = <0 0xfead0000 0 0x10000>;
2678			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2679			clocks = <&cpg CPG_MOD 729>,
2680				 <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
2681			clock-names = "iahb", "isfr";
2682			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2683			resets = <&cpg 729>;
2684			status = "disabled";
2685
2686			ports {
2687				#address-cells = <1>;
2688				#size-cells = <0>;
2689				port@0 {
2690					reg = <0>;
2691					dw_hdmi0_in: endpoint {
2692						remote-endpoint = <&du_out_hdmi0>;
2693					};
2694				};
2695				port@1 {
2696					reg = <1>;
2697				};
2698				port@2 {
2699					/* HDMI sound */
2700					reg = <2>;
2701				};
2702			};
2703		};
2704
2705		du: display@feb00000 {
2706			compatible = "renesas,du-r8a774a1";
2707			reg = <0 0xfeb00000 0 0x70000>;
2708			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2709				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2710				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2711			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2712				 <&cpg CPG_MOD 722>;
2713			clock-names = "du.0", "du.1", "du.2";
2714			resets = <&cpg 724>, <&cpg 722>;
2715			reset-names = "du.0", "du.2";
2716			status = "disabled";
2717
2718			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2719
2720			ports {
2721				#address-cells = <1>;
2722				#size-cells = <0>;
2723
2724				port@0 {
2725					reg = <0>;
2726					du_out_rgb: endpoint {
2727					};
2728				};
2729				port@1 {
2730					reg = <1>;
2731					du_out_hdmi0: endpoint {
2732						remote-endpoint = <&dw_hdmi0_in>;
2733					};
2734				};
2735				port@2 {
2736					reg = <2>;
2737					du_out_lvds0: endpoint {
2738						remote-endpoint = <&lvds0_in>;
2739					};
2740				};
2741			};
2742		};
2743
2744		lvds0: lvds@feb90000 {
2745			compatible = "renesas,r8a774a1-lvds";
2746			reg = <0 0xfeb90000 0 0x14>;
2747			clocks = <&cpg CPG_MOD 727>;
2748			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2749			resets = <&cpg 727>;
2750			status = "disabled";
2751
2752			ports {
2753				#address-cells = <1>;
2754				#size-cells = <0>;
2755
2756				port@0 {
2757					reg = <0>;
2758					lvds0_in: endpoint {
2759						remote-endpoint = <&du_out_lvds0>;
2760					};
2761				};
2762				port@1 {
2763					reg = <1>;
2764					lvds0_out: endpoint {
2765					};
2766				};
2767			};
2768		};
2769
2770		prr: chipid@fff00044 {
2771			compatible = "renesas,prr";
2772			reg = <0 0xfff00044 0 4>;
2773		};
2774	};
2775
2776	thermal-zones {
2777		sensor_thermal1: sensor-thermal1 {
2778			polling-delay-passive = <250>;
2779			polling-delay = <1000>;
2780			thermal-sensors = <&tsc 0>;
2781			sustainable-power = <3874>;
2782
2783			trips {
2784				sensor1_crit: sensor1-crit {
2785					temperature = <120000>;
2786					hysteresis = <1000>;
2787					type = "critical";
2788				};
2789			};
2790		};
2791
2792		sensor_thermal2: sensor-thermal2 {
2793			polling-delay-passive = <250>;
2794			polling-delay = <1000>;
2795			thermal-sensors = <&tsc 1>;
2796			sustainable-power = <3874>;
2797
2798			trips {
2799				sensor2_crit: sensor2-crit {
2800					temperature = <120000>;
2801					hysteresis = <1000>;
2802					type = "critical";
2803				};
2804			};
2805		};
2806
2807		sensor_thermal3: sensor-thermal3 {
2808			polling-delay-passive = <250>;
2809			polling-delay = <1000>;
2810			thermal-sensors = <&tsc 2>;
2811			sustainable-power = <3874>;
2812
2813			cooling-maps {
2814				map0 {
2815					trip = <&target>;
2816					cooling-device = <&a57_0 0 2>;
2817					contribution = <1024>;
2818				};
2819				map1 {
2820					trip = <&target>;
2821					cooling-device = <&a53_0 0 2>;
2822					contribution = <1024>;
2823				};
2824			};
2825			trips {
2826				target: trip-point1 {
2827					temperature = <100000>;
2828					hysteresis = <1000>;
2829					type = "passive";
2830				};
2831
2832				sensor3_crit: sensor3-crit {
2833					temperature = <120000>;
2834					hysteresis = <1000>;
2835					type = "critical";
2836				};
2837			};
2838		};
2839	};
2840
2841	timer {
2842		compatible = "arm,armv8-timer";
2843		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2844				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2845				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2846				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2847	};
2848
2849	/* External USB clocks - can be overridden by the board */
2850	usb3s0_clk: usb3s0 {
2851		compatible = "fixed-clock";
2852		#clock-cells = <0>;
2853		clock-frequency = <0>;
2854	};
2855
2856	usb_extal_clk: usb_extal {
2857		compatible = "fixed-clock";
2858		#clock-cells = <0>;
2859		clock-frequency = <0>;
2860	};
2861};
2862