1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
4 * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
5 *
6 * Copyright (C) 2020 Renesas Electronics Corp.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include "hihope-common.dtsi"
11
12/ {
13	audio_clkout: audio-clkout {
14		/*
15		 * This is same as <&rcar_sound 0>
16		 * but needed to avoid cs2000/rcar_sound probe dead-lock
17		 */
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		clock-frequency = <12288000>;
21	};
22
23	wlan_en_reg: regulator-wlan_en {
24		compatible = "regulator-fixed";
25		regulator-name = "wlan-en-regulator";
26		regulator-min-microvolt = <1800000>;
27		regulator-max-microvolt = <1800000>;
28		startup-delay-us = <70000>;
29
30		gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
31		enable-active-high;
32	};
33
34	x1801_clk: x1801-clock {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <24576000>;
38	};
39};
40
41&hscif0 {
42	bluetooth {
43		compatible = "ti,wl1837-st";
44		enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
45	};
46};
47
48&i2c2 {
49	pinctrl-0 = <&i2c2_pins>;
50	pinctrl-names = "default";
51	status = "okay";
52
53	cs2000: clk_multiplier@4f {
54		#clock-cells = <0>;
55		compatible = "cirrus,cs2000-cp";
56		reg = <0x4f>;
57		clocks = <&audio_clkout>, <&x1801_clk>;
58		clock-names = "clk_in", "ref_clk";
59
60		assigned-clocks = <&cs2000>;
61		assigned-clock-rates = <24576000>; /* 1/1 divide */
62	};
63};
64
65&pfc {
66	i2c2_pins: i2c2 {
67		groups = "i2c2_a";
68		function = "i2c2";
69	};
70
71	sound_clk_pins: sound_clk {
72		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
73		function = "audio_clk";
74	};
75
76	sound_pins: sound {
77		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
78		function = "ssi";
79	};
80};
81
82&rcar_sound {
83	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
84	pinctrl-names = "default";
85	status = "okay";
86
87	/* audio_clkout0/1/2/3 */
88	#clock-cells = <1>;
89	clock-frequency = <12288000 11289600>;
90
91	/*
92	 * Update <audio_clk_b> to <cs2000>
93	 * Switch SW2404 should be at position 1 so that clock from
94	 * CS2000 is connected to AUDIO_CLKB_A
95	 */
96	clocks = <&cpg CPG_MOD 1005>,
97		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
98		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
99		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
100		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
101		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
102		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
103		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
104		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
105		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
106		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
107		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
108		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
109		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
110		 <&audio_clk_a>, <&cs2000>,
111		 <&audio_clk_c>,
112		 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
113
114	rsnd_port: port {
115		rsnd_endpoint: endpoint {
116			remote-endpoint = <&dw_hdmi0_snd_in>;
117
118			dai-format = "i2s";
119			bitclock-master = <&rsnd_endpoint>;
120			frame-master = <&rsnd_endpoint>;
121
122			playback = <&ssi2>;
123		};
124	};
125};
126