1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Draak board
4 *
5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11
12/ {
13	model = "Renesas Draak board";
14	compatible = "renesas,draak";
15
16	aliases {
17		serial0 = &scif2;
18		ethernet0 = &avb;
19	};
20
21	audio_clkout: audio-clkout {
22		/*
23		 * This is same as <&rcar_sound 0>
24		 * but needed to avoid cs2000/rcar_sound probe dead-lock
25		 */
26		compatible = "fixed-clock";
27		#clock-cells = <0>;
28		clock-frequency = <12288000>;
29	};
30
31	backlight: backlight {
32		compatible = "pwm-backlight";
33		pwms = <&pwm1 0 50000>;
34
35		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
36		default-brightness-level = <10>;
37
38		power-supply = <&reg_12p0v>;
39		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
40	};
41
42	chosen {
43		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
44		stdout-path = "serial0:115200n8";
45	};
46
47	composite-in {
48		compatible = "composite-video-connector";
49
50		port {
51			composite_con_in: endpoint {
52				remote-endpoint = <&adv7180_in>;
53			};
54		};
55	};
56
57	hdmi-in {
58		compatible = "hdmi-connector";
59		type = "a";
60
61		port {
62			hdmi_con_in: endpoint {
63				remote-endpoint = <&adv7612_in>;
64			};
65		};
66	};
67
68	hdmi-out {
69		compatible = "hdmi-connector";
70		type = "a";
71
72		port {
73			hdmi_con_out: endpoint {
74				remote-endpoint = <&adv7511_out>;
75			};
76		};
77	};
78
79	keys {
80		compatible = "gpio-keys";
81
82		pinctrl-0 = <&keys_pins>;
83		pinctrl-names = "default";
84
85		key-1 {
86			gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
87			linux,code = <KEY_1>;
88			label = "SW56-1";
89			wakeup-source;
90			debounce-interval = <20>;
91		};
92		key-2 {
93			gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
94			linux,code = <KEY_2>;
95			label = "SW56-2";
96			wakeup-source;
97			debounce-interval = <20>;
98		};
99		key-3 {
100			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
101			linux,code = <KEY_3>;
102			label = "SW56-3";
103			wakeup-source;
104			debounce-interval = <20>;
105		};
106		key-4 {
107			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
108			linux,code = <KEY_4>;
109			label = "SW56-4";
110			wakeup-source;
111			debounce-interval = <20>;
112		};
113	};
114
115	lvds-decoder {
116		compatible = "thine,thc63lvd1024";
117		vcc-supply = <&reg_3p3v>;
118
119		ports {
120			#address-cells = <1>;
121			#size-cells = <0>;
122
123			port@0 {
124				reg = <0>;
125				thc63lvd1024_in: endpoint {
126					remote-endpoint = <&lvds0_out>;
127				};
128			};
129
130			port@2 {
131				reg = <2>;
132				thc63lvd1024_out: endpoint {
133					remote-endpoint = <&adv7511_in>;
134				};
135			};
136		};
137	};
138
139	memory@48000000 {
140		device_type = "memory";
141		/* first 128MB is reserved for secure area. */
142		reg = <0x0 0x48000000 0x0 0x18000000>;
143	};
144
145	reg_1p8v: regulator-1p8v {
146		compatible = "regulator-fixed";
147		regulator-name = "fixed-1.8V";
148		regulator-min-microvolt = <1800000>;
149		regulator-max-microvolt = <1800000>;
150		regulator-boot-on;
151		regulator-always-on;
152	};
153
154	reg_3p3v: regulator-3p3v {
155		compatible = "regulator-fixed";
156		regulator-name = "fixed-3.3V";
157		regulator-min-microvolt = <3300000>;
158		regulator-max-microvolt = <3300000>;
159		regulator-boot-on;
160		regulator-always-on;
161	};
162
163	reg_12p0v: regulator-12p0v {
164		compatible = "regulator-fixed";
165		regulator-name = "D12.0V";
166		regulator-min-microvolt = <12000000>;
167		regulator-max-microvolt = <12000000>;
168		regulator-boot-on;
169		regulator-always-on;
170	};
171
172	sound_card: sound {
173		compatible = "audio-graph-card";
174
175		dais = <&rsnd_port0	/* ak4613 */
176			/* HDMI is not yet supported */
177		>;
178	};
179
180	vga {
181		compatible = "vga-connector";
182
183		port {
184			vga_in: endpoint {
185				remote-endpoint = <&adv7123_out>;
186			};
187		};
188	};
189
190	vga-encoder {
191		compatible = "adi,adv7123";
192
193		ports {
194			#address-cells = <1>;
195			#size-cells = <0>;
196
197			port@0 {
198				reg = <0>;
199				adv7123_in: endpoint {
200					remote-endpoint = <&du_out_rgb>;
201				};
202			};
203			port@1 {
204				reg = <1>;
205				adv7123_out: endpoint {
206					remote-endpoint = <&vga_in>;
207				};
208			};
209		};
210	};
211
212	x12_clk: x12 {
213		compatible = "fixed-clock";
214		#clock-cells = <0>;
215		clock-frequency = <74250000>;
216	};
217
218	x19_clk: x19 {
219		compatible = "fixed-clock";
220		#clock-cells = <0>;
221		clock-frequency = <24576000>;
222	};
223};
224
225&audio_clk_b {
226	/*
227	 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
228	 * and R-Car Sound uses AUDIO_CLKB.
229	 * Note is that schematic indicates VI4_FIELD conection only
230	 * not AUDIO_CLKB at SoC page.
231	 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
232	 * SW60 should be 1-2.
233	 */
234
235	clock-frequency = <22579200>;
236};
237
238&avb {
239	pinctrl-0 = <&avb0_pins>;
240	pinctrl-names = "default";
241	renesas,no-ether-link;
242	phy-handle = <&phy0>;
243	status = "okay";
244
245	phy0: ethernet-phy@0 {
246		rxc-skew-ps = <1500>;
247		reg = <0>;
248		interrupt-parent = <&gpio5>;
249		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
250		/*
251		 * TX clock internal delay mode is required for reliable
252		 * 1Gbps communication using the KSZ9031RNX phy present on
253		 * the Draak board, however, TX clock internal delay mode
254		 * isn't supported on R-Car D3(e).  Thus, limit speed to
255		 * 100Mbps for reliable communication.
256		 */
257		max-speed = <100>;
258	};
259};
260
261&can0 {
262	pinctrl-0 = <&can0_pins>;
263	pinctrl-names = "default";
264	status = "okay";
265};
266
267&can1 {
268	pinctrl-0 = <&can1_pins>;
269	pinctrl-names = "default";
270	status = "okay";
271};
272
273&du {
274	pinctrl-0 = <&du_pins>;
275	pinctrl-names = "default";
276	status = "okay";
277
278	clocks = <&cpg CPG_MOD 724>,
279		 <&cpg CPG_MOD 723>,
280		 <&x12_clk>;
281	clock-names = "du.0", "du.1", "dclkin.0";
282
283	ports {
284		port@0 {
285			endpoint {
286				remote-endpoint = <&adv7123_in>;
287			};
288		};
289	};
290};
291
292&ehci0 {
293	dr_mode = "host";
294	status = "okay";
295};
296
297&extal_clk {
298	clock-frequency = <48000000>;
299};
300
301&hsusb {
302	dr_mode = "host";
303	status = "okay";
304};
305
306&i2c0 {
307	pinctrl-0 = <&i2c0_pins>;
308	pinctrl-names = "default";
309	status = "okay";
310
311	ak4613: codec@10 {
312		compatible = "asahi-kasei,ak4613";
313		#sound-dai-cells = <0>;
314		reg = <0x10>;
315		clocks = <&rcar_sound 0>; /* audio_clkout */
316
317		asahi-kasei,in1-single-end;
318		asahi-kasei,in2-single-end;
319		asahi-kasei,out1-single-end;
320		asahi-kasei,out2-single-end;
321		asahi-kasei,out3-single-end;
322		asahi-kasei,out4-single-end;
323		asahi-kasei,out5-single-end;
324		asahi-kasei,out6-single-end;
325
326		port {
327			ak4613_endpoint: endpoint {
328				remote-endpoint = <&rsnd_for_ak4613>;
329			};
330		};
331	};
332
333	composite-in@20 {
334		compatible = "adi,adv7180cp";
335		reg = <0x20>;
336
337		ports {
338			#address-cells = <1>;
339			#size-cells = <0>;
340
341			port@0 {
342				reg = <0>;
343				adv7180_in: endpoint {
344					remote-endpoint = <&composite_con_in>;
345				};
346			};
347
348			port@3 {
349				reg = <3>;
350
351				/*
352				 * The VIN4 video input path is shared between
353				 * CVBS and HDMI inputs through SW[49-53]
354				 * switches.
355				 *
356				 * CVBS is the default selection, link it to
357				 * VIN4 here.
358				 */
359				adv7180_out: endpoint {
360					remote-endpoint = <&vin4_in>;
361				};
362			};
363		};
364
365	};
366
367	hdmi-encoder@39 {
368		compatible = "adi,adv7511w";
369		reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
370		reg-names = "main", "edid", "cec", "packet";
371		interrupt-parent = <&gpio1>;
372		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
373
374		adi,input-depth = <8>;
375		adi,input-colorspace = "rgb";
376		adi,input-clock = "1x";
377
378		ports {
379			#address-cells = <1>;
380			#size-cells = <0>;
381
382			port@0 {
383				reg = <0>;
384				adv7511_in: endpoint {
385					remote-endpoint = <&thc63lvd1024_out>;
386				};
387			};
388
389			port@1 {
390				reg = <1>;
391				adv7511_out: endpoint {
392					remote-endpoint = <&hdmi_con_out>;
393				};
394			};
395		};
396	};
397
398	hdmi-decoder@4c {
399		compatible = "adi,adv7612";
400		reg = <0x4c>;
401		default-input = <0>;
402
403		ports {
404			#address-cells = <1>;
405			#size-cells = <0>;
406
407			port@0 {
408				reg = <0>;
409
410				adv7612_in: endpoint {
411					remote-endpoint = <&hdmi_con_in>;
412				};
413			};
414
415			port@2 {
416				reg = <2>;
417
418				/*
419				 * The VIN4 video input path is shared between
420				 * CVBS and HDMI inputs through SW[49-53]
421				 * switches.
422				 *
423				 * CVBS is the default selection, leave HDMI
424				 * not connected here.
425				 */
426				adv7612_out: endpoint {
427					pclk-sample = <0>;
428					hsync-active = <0>;
429					vsync-active = <0>;
430				};
431			};
432		};
433	};
434
435	cs2000: clk-multiplier@4f {
436		#clock-cells = <0>;
437		compatible = "cirrus,cs2000-cp";
438		reg = <0x4f>;
439		clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
440		clock-names = "clk_in", "ref_clk";
441
442		assigned-clocks = <&cs2000>;
443		assigned-clock-rates = <24576000>; /* 1/1 divide */
444	};
445
446	eeprom@50 {
447		compatible = "rohm,br24t01", "atmel,24c01";
448		reg = <0x50>;
449		pagesize = <8>;
450	};
451};
452
453&i2c1 {
454	pinctrl-0 = <&i2c1_pins>;
455	pinctrl-names = "default";
456	status = "okay";
457};
458
459&lvds0 {
460	status = "okay";
461
462	clocks = <&cpg CPG_MOD 727>,
463		 <&x12_clk>,
464		 <&extal_clk>;
465	clock-names = "fck", "dclkin.0", "extal";
466
467	ports {
468		port@1 {
469			lvds0_out: endpoint {
470				remote-endpoint = <&thc63lvd1024_in>;
471			};
472		};
473	};
474};
475
476&lvds1 {
477	/*
478	 * Even though the LVDS1 output is not connected, the encoder must be
479	 * enabled to supply a pixel clock to the DU for the DPAD output when
480	 * LVDS0 is in use.
481	 */
482	status = "okay";
483
484	clocks = <&cpg CPG_MOD 727>,
485		 <&x12_clk>,
486		 <&extal_clk>;
487	clock-names = "fck", "dclkin.0", "extal";
488};
489
490&ohci0 {
491	dr_mode = "host";
492	status = "okay";
493};
494
495&pfc {
496	avb0_pins: avb {
497		groups = "avb0_link", "avb0_mdio", "avb0_mii";
498		function = "avb0";
499	};
500
501	can0_pins: can0 {
502		groups = "can0_data_a";
503		function = "can0";
504	};
505
506	can1_pins: can1 {
507		groups = "can1_data_a";
508		function = "can1";
509	};
510
511	du_pins: du {
512		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
513		function = "du";
514	};
515
516	i2c0_pins: i2c0 {
517		groups = "i2c0";
518		function = "i2c0";
519	};
520
521	i2c1_pins: i2c1 {
522		groups = "i2c1";
523		function = "i2c1";
524	};
525
526	keys_pins: keys {
527		pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
528		bias-pull-up;
529	};
530
531	pwm0_pins: pwm0 {
532		groups = "pwm0_c";
533		function = "pwm0";
534	};
535
536	pwm1_pins: pwm1 {
537		groups = "pwm1_c";
538		function = "pwm1";
539	};
540
541	scif2_pins: scif2 {
542		groups = "scif2_data";
543		function = "scif2";
544	};
545
546	sdhi2_pins: sd2 {
547		groups = "mmc_data8", "mmc_ctrl";
548		function = "mmc";
549		power-source = <1800>;
550	};
551
552	sdhi2_pins_uhs: sd2_uhs {
553		groups = "mmc_data8", "mmc_ctrl";
554		function = "mmc";
555		power-source = <1800>;
556	};
557
558	sound_pins: sound {
559		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
560		function = "ssi";
561	};
562
563	sound_clk_pins: sound-clk {
564		groups = "audio_clk_a", "audio_clk_b",
565			 "audio_clkout", "audio_clkout1";
566		function = "audio_clk";
567	};
568
569	usb0_pins: usb0 {
570		groups = "usb0";
571		function = "usb0";
572	};
573
574	vin4_pins_cvbs: vin4 {
575		groups = "vin4_data8", "vin4_sync", "vin4_clk";
576		function = "vin4";
577	};
578};
579
580&pwm0 {
581	pinctrl-0 = <&pwm0_pins>;
582	pinctrl-names = "default";
583
584	status = "okay";
585};
586
587&pwm1 {
588	pinctrl-0 = <&pwm1_pins>;
589	pinctrl-names = "default";
590
591	status = "okay";
592};
593
594&rcar_sound {
595	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
596	pinctrl-names = "default";
597
598	/* Single DAI */
599	#sound-dai-cells = <0>;
600
601	/* audio_clkout0/1 */
602	#clock-cells = <1>;
603	clock-frequency = <12288000 11289600>;
604
605	status = "okay";
606
607	clocks = <&cpg CPG_MOD 1005>,
608		 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
609		 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
610		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
611		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
612		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
613		 <&cs2000>, <&audio_clk_b>,
614		 <&cpg CPG_CORE R8A77995_CLK_ZA2>;
615
616	ports {
617		rsnd_port0: port {
618			rsnd_for_ak4613: endpoint {
619				remote-endpoint = <&ak4613_endpoint>;
620				dai-format = "left_j";
621				bitclock-master = <&rsnd_for_ak4613>;
622				frame-master = <&rsnd_for_ak4613>;
623				playback = <&ssi3>, <&src5>, <&dvc0>;
624				capture  = <&ssi4>, <&src6>, <&dvc1>;
625			};
626		};
627	};
628};
629
630&rwdt {
631	timeout-sec = <60>;
632	status = "okay";
633};
634
635&scif2 {
636	pinctrl-0 = <&scif2_pins>;
637	pinctrl-names = "default";
638
639	status = "okay";
640};
641
642&sdhi2 {
643	/* used for on-board eMMC */
644	pinctrl-0 = <&sdhi2_pins>;
645	pinctrl-1 = <&sdhi2_pins_uhs>;
646	pinctrl-names = "default", "state_uhs";
647
648	vmmc-supply = <&reg_3p3v>;
649	vqmmc-supply = <&reg_1p8v>;
650	bus-width = <8>;
651	mmc-hs200-1_8v;
652	no-sd;
653	no-sdio;
654	non-removable;
655	status = "okay";
656};
657
658&ssi4 {
659	shared-pin;
660};
661
662&usb2_phy0 {
663	pinctrl-0 = <&usb0_pins>;
664	pinctrl-names = "default";
665
666	renesas,no-otg-pins;
667	status = "okay";
668};
669
670&vin4 {
671	pinctrl-0 = <&vin4_pins_cvbs>;
672	pinctrl-names = "default";
673
674	status = "okay";
675
676	ports {
677		port {
678			vin4_in: endpoint {
679				remote-endpoint = <&adv7180_out>;
680			};
681		};
682	};
683};
684