1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2/*
3 * Realtek RTD16xx SoC family
4 *
5 * Copyright (c) 2019 Realtek Semiconductor Corp.
6 * Copyright (c) 2019 Andreas Färber
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	interrupt-parent = <&gic>;
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a55";
24			reg = <0x0>;
25			enable-method = "psci";
26			next-level-cache = <&l2>;
27		};
28
29		cpu1: cpu@100 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a55";
32			reg = <0x100>;
33			enable-method = "psci";
34			next-level-cache = <&l3>;
35		};
36
37		cpu2: cpu@200 {
38			device_type = "cpu";
39			compatible = "arm,cortex-a55";
40			reg = <0x200>;
41			enable-method = "psci";
42			next-level-cache = <&l3>;
43		};
44
45		cpu3: cpu@300 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a55";
48			reg = <0x300>;
49			enable-method = "psci";
50			next-level-cache = <&l3>;
51		};
52
53		cpu4: cpu@400 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a55";
56			reg = <0x400>;
57			enable-method = "psci";
58			next-level-cache = <&l3>;
59		};
60
61		cpu5: cpu@500 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a55";
64			reg = <0x500>;
65			enable-method = "psci";
66			next-level-cache = <&l3>;
67		};
68
69		l2: l2-cache {
70			compatible = "cache";
71			next-level-cache = <&l3>;
72
73		};
74
75		l3: l3-cache {
76			compatible = "cache";
77		};
78	};
79
80	timer {
81		compatible = "arm,armv8-timer";
82		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
83			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
84			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
85			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
86	};
87
88	arm_pmu: pmu {
89		compatible = "arm,armv8-pmuv3";
90		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
91		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
92			<&cpu3>, <&cpu4>, <&cpu5>;
93	};
94
95	psci {
96		compatible = "arm,psci-1.0";
97		method = "smc";
98	};
99
100	osc27M: osc {
101		compatible = "fixed-clock";
102		clock-frequency = <27000000>;
103		clock-output-names = "osc27M";
104		#clock-cells = <0>;
105	};
106
107	soc {
108		compatible = "simple-bus";
109		#address-cells = <1>;
110		#size-cells = <1>;
111		ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
112			 <0x98000000 0x98000000 0x68000000>;
113
114		rbus: bus@98000000 {
115			compatible = "simple-bus";
116			reg = <0x98000000 0x200000>;
117			#address-cells = <1>;
118			#size-cells = <1>;
119			ranges = <0x0 0x98000000 0x200000>;
120
121			uart0: serial0@7800 {
122				compatible = "snps,dw-apb-uart";
123				reg = <0x7800 0x400>;
124				reg-shift = <2>;
125				reg-io-width = <4>;
126				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
127				clock-frequency = <27000000>;
128				status = "disabled";
129			};
130
131			uart1: serial1@1b200 {
132				compatible = "snps,dw-apb-uart";
133				reg = <0x1b200 0x400>;
134				reg-shift = <2>;
135				reg-io-width = <4>;
136				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
137				clock-frequency = <432000000>;
138				status = "disabled";
139			};
140
141			uart2: serial2@1b400 {
142				compatible = "snps,dw-apb-uart";
143				reg = <0x1b400 0x400>;
144				reg-shift = <2>;
145				reg-io-width = <4>;
146				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
147				clock-frequency = <432000000>;
148				status = "disabled";
149			};
150		};
151
152		gic: interrupt-controller@ff100000 {
153			compatible = "arm,gic-v3";
154			reg = <0xff100000 0x10000>,
155			      <0xff140000 0xc0000>;
156			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
157			interrupt-controller;
158			#interrupt-cells = <3>;
159		};
160	};
161};
162