1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2/*
3 * Realtek RTD1293/RTD1295/RTD1296 SoC
4 *
5 * Copyright (c) 2016-2017 Andreas Färber
6 */
7
8/memreserve/	0x0000000000000000 0x0000000000030000;
9/memreserve/	0x000000000001f000 0x0000000000001000;
10/memreserve/	0x0000000000030000 0x00000000000d0000;
11/memreserve/	0x0000000001b00000 0x00000000004be000;
12/memreserve/	0x0000000001ffe000 0x0000000000004000;
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/reset/realtek,rtd1295.h>
16
17/ {
18	interrupt-parent = <&gic>;
19	#address-cells = <1>;
20	#size-cells = <1>;
21
22	arm_pmu: arm-pmu {
23		compatible = "arm,cortex-a53-pmu";
24		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
25	};
26
27	osc27M: osc {
28		compatible = "fixed-clock";
29		clock-frequency = <27000000>;
30		#clock-cells = <0>;
31		clock-output-names = "osc27M";
32	};
33
34	soc {
35		compatible = "simple-bus";
36		#address-cells = <1>;
37		#size-cells = <1>;
38		/* Exclude up to 2 GiB of RAM */
39		ranges = <0x80000000 0x80000000 0x80000000>;
40
41		reset1: reset-controller@98000000 {
42			compatible = "snps,dw-low-reset";
43			reg = <0x98000000 0x4>;
44			#reset-cells = <1>;
45		};
46
47		reset2: reset-controller@98000004 {
48			compatible = "snps,dw-low-reset";
49			reg = <0x98000004 0x4>;
50			#reset-cells = <1>;
51		};
52
53		reset3: reset-controller@98000008 {
54			compatible = "snps,dw-low-reset";
55			reg = <0x98000008 0x4>;
56			#reset-cells = <1>;
57		};
58
59		reset4: reset-controller@98000050 {
60			compatible = "snps,dw-low-reset";
61			reg = <0x98000050 0x4>;
62			#reset-cells = <1>;
63		};
64
65		iso_reset: reset-controller@98007088 {
66			compatible = "snps,dw-low-reset";
67			reg = <0x98007088 0x4>;
68			#reset-cells = <1>;
69		};
70
71		wdt: watchdog@98007680 {
72			compatible = "realtek,rtd1295-watchdog";
73			reg = <0x98007680 0x100>;
74			clocks = <&osc27M>;
75		};
76
77		uart0: serial@98007800 {
78			compatible = "snps,dw-apb-uart";
79			reg = <0x98007800 0x400>;
80			reg-shift = <2>;
81			reg-io-width = <4>;
82			clock-frequency = <27000000>;
83			resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
84			status = "disabled";
85		};
86
87		uart1: serial@9801b200 {
88			compatible = "snps,dw-apb-uart";
89			reg = <0x9801b200 0x100>;
90			reg-shift = <2>;
91			reg-io-width = <4>;
92			clock-frequency = <432000000>;
93			resets = <&reset2 RTD1295_RSTN_UR1>;
94			status = "disabled";
95		};
96
97		uart2: serial@9801b400 {
98			compatible = "snps,dw-apb-uart";
99			reg = <0x9801b400 0x100>;
100			reg-shift = <2>;
101			reg-io-width = <4>;
102			clock-frequency = <432000000>;
103			resets = <&reset2 RTD1295_RSTN_UR2>;
104			status = "disabled";
105		};
106
107		gic: interrupt-controller@ff011000 {
108			compatible = "arm,gic-400";
109			reg = <0xff011000 0x1000>,
110			      <0xff012000 0x2000>,
111			      <0xff014000 0x2000>,
112			      <0xff016000 0x2000>;
113			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
114			interrupt-controller;
115			#interrupt-cells = <3>;
116		};
117	};
118};
119