1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-gcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 bi_tcxo_div2: bi-tcxo-div2-clk { 44 #clock-cells = <0>; 45 compatible = "fixed-factor-clock"; 46 clocks = <&rpmhcc RPMH_CXO_CLK>; 47 clock-mult = <1>; 48 clock-div = <2>; 49 }; 50 51 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 52 #clock-cells = <0>; 53 compatible = "fixed-factor-clock"; 54 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 55 clock-mult = <1>; 56 clock-div = <2>; 57 }; 58 59 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 CPU0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&L2_0>; 76 power-domains = <&CPU_PD0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 #cooling-cells = <2>; 82 L2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&L3_0>; 87 L3_0: l3-cache { 88 compatible = "cache"; 89 cache-level = <3>; 90 cache-unified; 91 }; 92 }; 93 }; 94 95 CPU1: cpu@100 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a510"; 98 reg = <0 0x100>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_100>; 102 power-domains = <&CPU_PD1>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 #cooling-cells = <2>; 108 L2_100: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU2: cpu@200 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a510"; 119 reg = <0 0x200>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_200>; 123 power-domains = <&CPU_PD2>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 #cooling-cells = <2>; 129 L2_200: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a715"; 140 reg = <0 0x300>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&L2_300>; 144 power-domains = <&CPU_PD3>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 capacity-dmips-mhz = <1792>; 148 dynamic-power-coefficient = <270>; 149 #cooling-cells = <2>; 150 L2_300: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&L3_0>; 155 }; 156 }; 157 158 CPU4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a715"; 161 reg = <0 0x400>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&L2_400>; 165 power-domains = <&CPU_PD4>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 capacity-dmips-mhz = <1792>; 169 dynamic-power-coefficient = <270>; 170 #cooling-cells = <2>; 171 L2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 CPU5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a710"; 182 reg = <0 0x500>; 183 clocks = <&cpufreq_hw 1>; 184 enable-method = "psci"; 185 next-level-cache = <&L2_500>; 186 power-domains = <&CPU_PD5>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 1>; 189 capacity-dmips-mhz = <1792>; 190 dynamic-power-coefficient = <270>; 191 #cooling-cells = <2>; 192 L2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a710"; 203 reg = <0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 next-level-cache = <&L2_600>; 207 power-domains = <&CPU_PD6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <270>; 212 #cooling-cells = <2>; 213 L2_600: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-unified; 217 next-level-cache = <&L3_0>; 218 }; 219 }; 220 221 CPU7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "arm,cortex-x3"; 224 reg = <0 0x700>; 225 clocks = <&cpufreq_hw 2>; 226 enable-method = "psci"; 227 next-level-cache = <&L2_700>; 228 power-domains = <&CPU_PD7>; 229 power-domain-names = "psci"; 230 qcom,freq-domain = <&cpufreq_hw 2>; 231 capacity-dmips-mhz = <1894>; 232 dynamic-power-coefficient = <588>; 233 #cooling-cells = <2>; 234 L2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&CPU0>; 246 }; 247 248 core1 { 249 cpu = <&CPU1>; 250 }; 251 252 core2 { 253 cpu = <&CPU2>; 254 }; 255 256 core3 { 257 cpu = <&CPU3>; 258 }; 259 260 core4 { 261 cpu = <&CPU4>; 262 }; 263 264 core5 { 265 cpu = <&CPU5>; 266 }; 267 268 core6 { 269 cpu = <&CPU6>; 270 }; 271 272 core7 { 273 cpu = <&CPU7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "silver-rail-power-collapse"; 284 arm,psci-suspend-param = <0x40000004>; 285 entry-latency-us = <800>; 286 exit-latency-us = <750>; 287 min-residency-us = <4090>; 288 local-timer-stop; 289 }; 290 291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-rail-power-collapse"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <600>; 296 exit-latency-us = <1550>; 297 min-residency-us = <4791>; 298 local-timer-stop; 299 }; 300 }; 301 302 domain-idle-states { 303 CLUSTER_SLEEP_0: cluster-sleep-0 { 304 compatible = "domain-idle-state"; 305 arm,psci-suspend-param = <0x41000044>; 306 entry-latency-us = <1050>; 307 exit-latency-us = <2500>; 308 min-residency-us = <5309>; 309 }; 310 311 CLUSTER_SLEEP_1: cluster-sleep-1 { 312 compatible = "domain-idle-state"; 313 arm,psci-suspend-param = <0x4100c344>; 314 entry-latency-us = <2700>; 315 exit-latency-us = <3500>; 316 min-residency-us = <13959>; 317 }; 318 }; 319 }; 320 321 firmware { 322 scm: scm { 323 compatible = "qcom,scm-sm8550", "qcom,scm"; 324 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 325 }; 326 }; 327 328 clk_virt: interconnect-0 { 329 compatible = "qcom,sm8550-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 mc_virt: interconnect-1 { 335 compatible = "qcom,sm8550-mc-virt"; 336 #interconnect-cells = <2>; 337 qcom,bcm-voters = <&apps_bcm_voter>; 338 }; 339 340 memory@a0000000 { 341 device_type = "memory"; 342 /* We expect the bootloader to fill in the size */ 343 reg = <0 0xa0000000 0 0>; 344 }; 345 346 pmu { 347 compatible = "arm,armv8-pmuv3"; 348 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 349 }; 350 351 psci { 352 compatible = "arm,psci-1.0"; 353 method = "smc"; 354 355 CPU_PD0: power-domain-cpu0 { 356 #power-domain-cells = <0>; 357 power-domains = <&CLUSTER_PD>; 358 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 359 }; 360 361 CPU_PD1: power-domain-cpu1 { 362 #power-domain-cells = <0>; 363 power-domains = <&CLUSTER_PD>; 364 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 365 }; 366 367 CPU_PD2: power-domain-cpu2 { 368 #power-domain-cells = <0>; 369 power-domains = <&CLUSTER_PD>; 370 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 371 }; 372 373 CPU_PD3: power-domain-cpu3 { 374 #power-domain-cells = <0>; 375 power-domains = <&CLUSTER_PD>; 376 domain-idle-states = <&BIG_CPU_SLEEP_0>; 377 }; 378 379 CPU_PD4: power-domain-cpu4 { 380 #power-domain-cells = <0>; 381 power-domains = <&CLUSTER_PD>; 382 domain-idle-states = <&BIG_CPU_SLEEP_0>; 383 }; 384 385 CPU_PD5: power-domain-cpu5 { 386 #power-domain-cells = <0>; 387 power-domains = <&CLUSTER_PD>; 388 domain-idle-states = <&BIG_CPU_SLEEP_0>; 389 }; 390 391 CPU_PD6: power-domain-cpu6 { 392 #power-domain-cells = <0>; 393 power-domains = <&CLUSTER_PD>; 394 domain-idle-states = <&BIG_CPU_SLEEP_0>; 395 }; 396 397 CPU_PD7: power-domain-cpu7 { 398 #power-domain-cells = <0>; 399 power-domains = <&CLUSTER_PD>; 400 domain-idle-states = <&BIG_CPU_SLEEP_0>; 401 }; 402 403 CLUSTER_PD: power-domain-cluster { 404 #power-domain-cells = <0>; 405 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 406 }; 407 }; 408 409 reserved_memory: reserved-memory { 410 #address-cells = <2>; 411 #size-cells = <2>; 412 ranges; 413 414 hyp_mem: hyp-region@80000000 { 415 reg = <0 0x80000000 0 0xa00000>; 416 no-map; 417 }; 418 419 cpusys_vm_mem: cpusys-vm-region@80a00000 { 420 reg = <0 0x80a00000 0 0x400000>; 421 no-map; 422 }; 423 424 hyp_tags_mem: hyp-tags-region@80e00000 { 425 reg = <0 0x80e00000 0 0x3d0000>; 426 no-map; 427 }; 428 429 xbl_sc_mem: xbl-sc-region@d8100000 { 430 reg = <0 0xd8100000 0 0x40000>; 431 no-map; 432 }; 433 434 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 435 reg = <0 0x811d0000 0 0x30000>; 436 no-map; 437 }; 438 439 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 440 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 441 reg = <0 0x81a00000 0 0x260000>; 442 no-map; 443 }; 444 445 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 446 compatible = "qcom,cmd-db"; 447 reg = <0 0x81c60000 0 0x20000>; 448 no-map; 449 }; 450 451 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 452 aop_config_merged_mem: aop-config-merged-region@81c80000 { 453 reg = <0 0x81c80000 0 0x74000>; 454 no-map; 455 }; 456 457 /* secdata region can be reused by apps */ 458 smem: smem@81d00000 { 459 compatible = "qcom,smem"; 460 reg = <0 0x81d00000 0 0x200000>; 461 hwlocks = <&tcsr_mutex 3>; 462 no-map; 463 }; 464 465 adsp_mhi_mem: adsp-mhi-region@81f00000 { 466 reg = <0 0x81f00000 0 0x20000>; 467 no-map; 468 }; 469 470 global_sync_mem: global-sync-region@82600000 { 471 reg = <0 0x82600000 0 0x100000>; 472 no-map; 473 }; 474 475 tz_stat_mem: tz-stat-region@82700000 { 476 reg = <0 0x82700000 0 0x100000>; 477 no-map; 478 }; 479 480 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 481 reg = <0 0x82800000 0 0x4600000>; 482 no-map; 483 }; 484 485 mpss_mem: mpss-region@8a800000 { 486 reg = <0 0x8a800000 0 0x10800000>; 487 no-map; 488 }; 489 490 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 491 reg = <0 0x9b000000 0 0x80000>; 492 no-map; 493 }; 494 495 ipa_fw_mem: ipa-fw-region@9b080000 { 496 reg = <0 0x9b080000 0 0x10000>; 497 no-map; 498 }; 499 500 ipa_gsi_mem: ipa-gsi-region@9b090000 { 501 reg = <0 0x9b090000 0 0xa000>; 502 no-map; 503 }; 504 505 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 506 reg = <0 0x9b09a000 0 0x2000>; 507 no-map; 508 }; 509 510 spss_region_mem: spss-region@9b100000 { 511 reg = <0 0x9b100000 0 0x180000>; 512 no-map; 513 }; 514 515 /* First part of the "SPU secure shared memory" region */ 516 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 517 reg = <0 0x9b280000 0 0x60000>; 518 no-map; 519 }; 520 521 /* Second part of the "SPU secure shared memory" region */ 522 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 523 reg = <0 0x9b2e0000 0 0x20000>; 524 no-map; 525 }; 526 527 camera_mem: camera-region@9b300000 { 528 reg = <0 0x9b300000 0 0x800000>; 529 no-map; 530 }; 531 532 video_mem: video-region@9bb00000 { 533 reg = <0 0x9bb00000 0 0x700000>; 534 no-map; 535 }; 536 537 cvp_mem: cvp-region@9c200000 { 538 reg = <0 0x9c200000 0 0x700000>; 539 no-map; 540 }; 541 542 cdsp_mem: cdsp-region@9c900000 { 543 reg = <0 0x9c900000 0 0x2000000>; 544 no-map; 545 }; 546 547 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 548 reg = <0 0x9e900000 0 0x80000>; 549 no-map; 550 }; 551 552 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 553 reg = <0 0x9e980000 0 0x80000>; 554 no-map; 555 }; 556 557 adspslpi_mem: adspslpi-region@9ea00000 { 558 reg = <0 0x9ea00000 0 0x4080000>; 559 no-map; 560 }; 561 562 /* uefi region can be reused by apps */ 563 564 /* Linux kernel image is loaded at 0xa8000000 */ 565 566 rmtfs_mem: rmtfs-region@d4a80000 { 567 compatible = "qcom,rmtfs-mem"; 568 reg = <0x0 0xd4a80000 0x0 0x280000>; 569 no-map; 570 571 qcom,client-id = <1>; 572 qcom,vmid = <15>; 573 }; 574 575 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 576 reg = <0 0xd4d00000 0 0x3300000>; 577 no-map; 578 }; 579 580 tz_reserved_mem: tz-reserved-region@d8000000 { 581 reg = <0 0xd8000000 0 0x100000>; 582 no-map; 583 }; 584 585 cpucp_fw_mem: cpucp-fw-region@d8140000 { 586 reg = <0 0xd8140000 0 0x1c0000>; 587 no-map; 588 }; 589 590 qtee_mem: qtee-region@d8300000 { 591 reg = <0 0xd8300000 0 0x500000>; 592 no-map; 593 }; 594 595 ta_mem: ta-region@d8800000 { 596 reg = <0 0xd8800000 0 0x8a00000>; 597 no-map; 598 }; 599 600 tz_tags_mem: tz-tags-region@e1200000 { 601 reg = <0 0xe1200000 0 0x2740000>; 602 no-map; 603 }; 604 605 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 606 reg = <0 0xe6440000 0 0x279000>; 607 no-map; 608 }; 609 610 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 611 reg = <0 0xf3600000 0 0x4aee000>; 612 no-map; 613 }; 614 615 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 616 reg = <0 0xf80ee000 0 0x1000>; 617 no-map; 618 }; 619 620 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 621 reg = <0 0xf80ef000 0 0x9000>; 622 no-map; 623 }; 624 625 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 626 reg = <0 0xf80f8000 0 0x4000>; 627 no-map; 628 }; 629 630 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 631 reg = <0 0xf80fc000 0 0x4000>; 632 no-map; 633 }; 634 635 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 636 reg = <0 0xf8100000 0 0x100000>; 637 no-map; 638 }; 639 640 oem_vm_mem: oem-vm-region@f8400000 { 641 reg = <0 0xf8400000 0 0x4800000>; 642 no-map; 643 }; 644 645 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 646 reg = <0 0xfcc00000 0 0x4000>; 647 no-map; 648 }; 649 650 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 651 reg = <0 0xfcc04000 0 0x100000>; 652 no-map; 653 }; 654 655 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 656 reg = <0 0xfce00000 0 0x2900000>; 657 no-map; 658 }; 659 660 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 661 reg = <0 0xff700000 0 0x100000>; 662 no-map; 663 }; 664 }; 665 666 smp2p-adsp { 667 compatible = "qcom,smp2p"; 668 qcom,smem = <443>, <429>; 669 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 670 IPCC_MPROC_SIGNAL_SMP2P 671 IRQ_TYPE_EDGE_RISING>; 672 mboxes = <&ipcc IPCC_CLIENT_LPASS 673 IPCC_MPROC_SIGNAL_SMP2P>; 674 675 qcom,local-pid = <0>; 676 qcom,remote-pid = <2>; 677 678 smp2p_adsp_out: master-kernel { 679 qcom,entry-name = "master-kernel"; 680 #qcom,smem-state-cells = <1>; 681 }; 682 683 smp2p_adsp_in: slave-kernel { 684 qcom,entry-name = "slave-kernel"; 685 interrupt-controller; 686 #interrupt-cells = <2>; 687 }; 688 }; 689 690 smp2p-cdsp { 691 compatible = "qcom,smp2p"; 692 qcom,smem = <94>, <432>; 693 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 694 IPCC_MPROC_SIGNAL_SMP2P 695 IRQ_TYPE_EDGE_RISING>; 696 mboxes = <&ipcc IPCC_CLIENT_CDSP 697 IPCC_MPROC_SIGNAL_SMP2P>; 698 699 qcom,local-pid = <0>; 700 qcom,remote-pid = <5>; 701 702 smp2p_cdsp_out: master-kernel { 703 qcom,entry-name = "master-kernel"; 704 #qcom,smem-state-cells = <1>; 705 }; 706 707 smp2p_cdsp_in: slave-kernel { 708 qcom,entry-name = "slave-kernel"; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 }; 713 714 smp2p-modem { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <435>, <428>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_MPSS 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <1>; 725 726 smp2p_modem_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_modem_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 737 ipa_smp2p_out: ipa-ap-to-modem { 738 qcom,entry-name = "ipa"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 ipa_smp2p_in: ipa-modem-to-ap { 743 qcom,entry-name = "ipa"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 soc: soc@0 { 750 compatible = "simple-bus"; 751 ranges = <0 0 0 0 0x10 0>; 752 dma-ranges = <0 0 0 0 0x10 0>; 753 754 #address-cells = <2>; 755 #size-cells = <2>; 756 757 gcc: clock-controller@100000 { 758 compatible = "qcom,sm8550-gcc"; 759 reg = <0 0x00100000 0 0x1f4200>; 760 #clock-cells = <1>; 761 #reset-cells = <1>; 762 #power-domain-cells = <1>; 763 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 764 <&pcie0_phy>, 765 <&pcie1_phy>, 766 <&pcie_1_phy_aux_clk>, 767 <&ufs_mem_phy 0>, 768 <&ufs_mem_phy 1>, 769 <&ufs_mem_phy 2>, 770 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 771 }; 772 773 ipcc: mailbox@408000 { 774 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 775 reg = <0 0x00408000 0 0x1000>; 776 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-controller; 778 #interrupt-cells = <3>; 779 #mbox-cells = <2>; 780 }; 781 782 gpi_dma2: dma-controller@800000 { 783 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 784 #dma-cells = <3>; 785 reg = <0 0x00800000 0 0x60000>; 786 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 798 dma-channels = <12>; 799 dma-channel-mask = <0x3e>; 800 iommus = <&apps_smmu 0x436 0>; 801 status = "disabled"; 802 }; 803 804 qupv3_id_1: geniqup@8c0000 { 805 compatible = "qcom,geni-se-qup"; 806 reg = <0 0x008c0000 0 0x2000>; 807 ranges; 808 clock-names = "m-ahb", "s-ahb"; 809 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 810 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 811 iommus = <&apps_smmu 0x423 0>; 812 #address-cells = <2>; 813 #size-cells = <2>; 814 status = "disabled"; 815 816 i2c8: i2c@880000 { 817 compatible = "qcom,geni-i2c"; 818 reg = <0 0x00880000 0 0x4000>; 819 clock-names = "se"; 820 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_i2c8_data_clk>; 823 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 828 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 830 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 831 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 832 dma-names = "tx", "rx"; 833 status = "disabled"; 834 }; 835 836 spi8: spi@880000 { 837 compatible = "qcom,geni-spi"; 838 reg = <0 0x00880000 0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 841 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 844 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 845 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 846 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 847 interconnect-names = "qup-core", "qup-config", "qup-memory"; 848 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 849 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 850 dma-names = "tx", "rx"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 status = "disabled"; 854 }; 855 856 i2c9: i2c@884000 { 857 compatible = "qcom,geni-i2c"; 858 reg = <0 0x00884000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_i2c9_data_clk>; 863 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 868 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 869 interconnect-names = "qup-core", "qup-config", "qup-memory"; 870 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 871 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 872 dma-names = "tx", "rx"; 873 status = "disabled"; 874 }; 875 876 spi9: spi@884000 { 877 compatible = "qcom,geni-spi"; 878 reg = <0 0x00884000 0 0x4000>; 879 clock-names = "se"; 880 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 881 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 884 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 885 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 886 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 887 interconnect-names = "qup-core", "qup-config", "qup-memory"; 888 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 889 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 890 dma-names = "tx", "rx"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 }; 895 896 i2c10: i2c@888000 { 897 compatible = "qcom,geni-i2c"; 898 reg = <0 0x00888000 0 0x4000>; 899 clock-names = "se"; 900 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&qup_i2c10_data_clk>; 903 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 907 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 908 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 909 interconnect-names = "qup-core", "qup-config", "qup-memory"; 910 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 911 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 912 dma-names = "tx", "rx"; 913 status = "disabled"; 914 }; 915 916 spi10: spi@888000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00888000 0 0x4000>; 919 clock-names = "se"; 920 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 921 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 925 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 926 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 929 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 930 dma-names = "tx", "rx"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 status = "disabled"; 934 }; 935 936 i2c11: i2c@88c000 { 937 compatible = "qcom,geni-i2c"; 938 reg = <0 0x0088c000 0 0x4000>; 939 clock-names = "se"; 940 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&qup_i2c11_data_clk>; 943 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 947 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 948 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 949 interconnect-names = "qup-core", "qup-config", "qup-memory"; 950 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 951 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 952 dma-names = "tx", "rx"; 953 status = "disabled"; 954 }; 955 956 spi11: spi@88c000 { 957 compatible = "qcom,geni-spi"; 958 reg = <0 0x0088c000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 961 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 966 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 967 interconnect-names = "qup-core", "qup-config", "qup-memory"; 968 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 969 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 970 dma-names = "tx", "rx"; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 status = "disabled"; 974 }; 975 976 i2c12: i2c@890000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00890000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c12_data_clk>; 983 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 988 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", "qup-memory"; 990 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 991 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 status = "disabled"; 994 }; 995 996 spi12: spi@890000 { 997 compatible = "qcom,geni-spi"; 998 reg = <0 0x00890000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1001 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1006 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1008 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1009 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c13: i2c@894000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00894000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_i2c13_data_clk>; 1023 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1027 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1028 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1029 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1030 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1031 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 status = "disabled"; 1034 }; 1035 1036 spi13: spi@894000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00894000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1041 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1046 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1049 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c15: i2c@89c000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x0089c000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c15_data_clk>; 1063 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1071 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi15: spi@89c000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x0089c000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1081 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1084 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1086 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1087 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1088 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1089 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1090 dma-names = "tx", "rx"; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 status = "disabled"; 1094 }; 1095 }; 1096 1097 i2c_master_hub_0: geniqup@9c0000 { 1098 compatible = "qcom,geni-se-i2c-master-hub"; 1099 reg = <0x0 0x009c0000 0x0 0x2000>; 1100 clock-names = "s-ahb"; 1101 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1102 #address-cells = <2>; 1103 #size-cells = <2>; 1104 ranges; 1105 status = "disabled"; 1106 1107 i2c_hub_0: i2c@980000 { 1108 compatible = "qcom,geni-i2c-master-hub"; 1109 reg = <0x0 0x00980000 0x0 0x4000>; 1110 clock-names = "se", "core"; 1111 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1112 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&hub_i2c0_data_clk>; 1115 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1119 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1120 interconnect-names = "qup-core", "qup-config"; 1121 status = "disabled"; 1122 }; 1123 1124 i2c_hub_1: i2c@984000 { 1125 compatible = "qcom,geni-i2c-master-hub"; 1126 reg = <0x0 0x00984000 0x0 0x4000>; 1127 clock-names = "se", "core"; 1128 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1129 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&hub_i2c1_data_clk>; 1132 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1136 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1137 interconnect-names = "qup-core", "qup-config"; 1138 status = "disabled"; 1139 }; 1140 1141 i2c_hub_2: i2c@988000 { 1142 compatible = "qcom,geni-i2c-master-hub"; 1143 reg = <0x0 0x00988000 0x0 0x4000>; 1144 clock-names = "se", "core"; 1145 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1146 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&hub_i2c2_data_clk>; 1149 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1154 interconnect-names = "qup-core", "qup-config"; 1155 status = "disabled"; 1156 }; 1157 1158 i2c_hub_3: i2c@98c000 { 1159 compatible = "qcom,geni-i2c-master-hub"; 1160 reg = <0x0 0x0098c000 0x0 0x4000>; 1161 clock-names = "se", "core"; 1162 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1163 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&hub_i2c3_data_clk>; 1166 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1170 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 1175 i2c_hub_4: i2c@990000 { 1176 compatible = "qcom,geni-i2c-master-hub"; 1177 reg = <0x0 0x00990000 0x0 0x4000>; 1178 clock-names = "se", "core"; 1179 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1180 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&hub_i2c4_data_clk>; 1183 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c_hub_5: i2c@994000 { 1193 compatible = "qcom,geni-i2c-master-hub"; 1194 reg = <0 0x00994000 0 0x4000>; 1195 clock-names = "se", "core"; 1196 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1197 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&hub_i2c5_data_clk>; 1200 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 status = "disabled"; 1207 }; 1208 1209 i2c_hub_6: i2c@998000 { 1210 compatible = "qcom,geni-i2c-master-hub"; 1211 reg = <0 0x00998000 0 0x4000>; 1212 clock-names = "se", "core"; 1213 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1214 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&hub_i2c6_data_clk>; 1217 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 i2c_hub_7: i2c@99c000 { 1227 compatible = "qcom,geni-i2c-master-hub"; 1228 reg = <0 0x0099c000 0 0x4000>; 1229 clock-names = "se", "core"; 1230 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1231 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&hub_i2c7_data_clk>; 1234 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c_hub_8: i2c@9a0000 { 1244 compatible = "qcom,geni-i2c-master-hub"; 1245 reg = <0 0x009a0000 0 0x4000>; 1246 clock-names = "se", "core"; 1247 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1248 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&hub_i2c8_data_clk>; 1251 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1256 interconnect-names = "qup-core", "qup-config"; 1257 status = "disabled"; 1258 }; 1259 1260 i2c_hub_9: i2c@9a4000 { 1261 compatible = "qcom,geni-i2c-master-hub"; 1262 reg = <0 0x009a4000 0 0x4000>; 1263 clock-names = "se", "core"; 1264 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1265 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&hub_i2c9_data_clk>; 1268 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1273 interconnect-names = "qup-core", "qup-config"; 1274 status = "disabled"; 1275 }; 1276 }; 1277 1278 gpi_dma1: dma-controller@a00000 { 1279 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1280 #dma-cells = <3>; 1281 reg = <0 0x00a00000 0 0x60000>; 1282 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1294 dma-channels = <12>; 1295 dma-channel-mask = <0x1e>; 1296 iommus = <&apps_smmu 0xb6 0>; 1297 status = "disabled"; 1298 }; 1299 1300 qupv3_id_0: geniqup@ac0000 { 1301 compatible = "qcom,geni-se-qup"; 1302 reg = <0 0x00ac0000 0 0x2000>; 1303 ranges; 1304 clock-names = "m-ahb", "s-ahb"; 1305 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1306 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1307 iommus = <&apps_smmu 0xa3 0>; 1308 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1309 interconnect-names = "qup-core"; 1310 #address-cells = <2>; 1311 #size-cells = <2>; 1312 status = "disabled"; 1313 1314 i2c0: i2c@a80000 { 1315 compatible = "qcom,geni-i2c"; 1316 reg = <0 0x00a80000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_i2c0_data_clk>; 1321 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1326 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1327 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1328 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1329 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1330 dma-names = "tx", "rx"; 1331 status = "disabled"; 1332 }; 1333 1334 spi0: spi@a80000 { 1335 compatible = "qcom,geni-spi"; 1336 reg = <0 0x00a80000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1339 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1342 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1344 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1345 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1346 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1347 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1348 dma-names = "tx", "rx"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 status = "disabled"; 1352 }; 1353 1354 i2c1: i2c@a84000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a84000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c1_data_clk>; 1361 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1366 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1368 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1369 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1370 dma-names = "tx", "rx"; 1371 status = "disabled"; 1372 }; 1373 1374 spi1: spi@a84000 { 1375 compatible = "qcom,geni-spi"; 1376 reg = <0 0x00a84000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1379 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1384 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1385 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1386 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1387 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1388 dma-names = "tx", "rx"; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 i2c2: i2c@a88000 { 1395 compatible = "qcom,geni-i2c"; 1396 reg = <0 0x00a88000 0 0x4000>; 1397 clock-names = "se"; 1398 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1399 pinctrl-names = "default"; 1400 pinctrl-0 = <&qup_i2c2_data_clk>; 1401 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1405 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1406 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1407 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1408 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1409 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1410 dma-names = "tx", "rx"; 1411 status = "disabled"; 1412 }; 1413 1414 spi2: spi@a88000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00a88000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1419 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1424 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1426 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1427 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1428 dma-names = "tx", "rx"; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 status = "disabled"; 1432 }; 1433 1434 i2c3: i2c@a8c000 { 1435 compatible = "qcom,geni-i2c"; 1436 reg = <0 0x00a8c000 0 0x4000>; 1437 clock-names = "se"; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1439 pinctrl-names = "default"; 1440 pinctrl-0 = <&qup_i2c3_data_clk>; 1441 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1445 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1446 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1447 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1448 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1449 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1450 dma-names = "tx", "rx"; 1451 status = "disabled"; 1452 }; 1453 1454 spi3: spi@a8c000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00a8c000 0 0x4000>; 1457 clock-names = "se"; 1458 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1459 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1464 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1465 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1466 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1467 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1468 dma-names = "tx", "rx"; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 i2c4: i2c@a90000 { 1475 compatible = "qcom,geni-i2c"; 1476 reg = <0 0x00a90000 0 0x4000>; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_i2c4_data_clk>; 1481 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1485 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1486 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1487 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1488 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1489 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1490 dma-names = "tx", "rx"; 1491 status = "disabled"; 1492 }; 1493 1494 spi4: spi@a90000 { 1495 compatible = "qcom,geni-spi"; 1496 reg = <0 0x00a90000 0 0x4000>; 1497 clock-names = "se"; 1498 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1499 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1503 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1504 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1505 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1506 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1507 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1508 dma-names = "tx", "rx"; 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 status = "disabled"; 1512 }; 1513 1514 i2c5: i2c@a94000 { 1515 compatible = "qcom,geni-i2c"; 1516 reg = <0 0x00a94000 0 0x4000>; 1517 clock-names = "se"; 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&qup_i2c5_data_clk>; 1521 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1524 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 spi5: spi@a94000 { 1535 compatible = "qcom,geni-spi"; 1536 reg = <0 0x00a94000 0 0x4000>; 1537 clock-names = "se"; 1538 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1539 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1540 pinctrl-names = "default"; 1541 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1544 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1545 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1546 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1547 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 status = "disabled"; 1552 }; 1553 1554 i2c6: i2c@a98000 { 1555 compatible = "qcom,geni-i2c"; 1556 reg = <0 0x00a98000 0 0x4000>; 1557 clock-names = "se"; 1558 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1559 pinctrl-names = "default"; 1560 pinctrl-0 = <&qup_i2c6_data_clk>; 1561 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1564 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1565 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1566 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1567 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1568 dma-names = "tx", "rx"; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 status = "disabled"; 1572 }; 1573 1574 spi6: spi@a98000 { 1575 compatible = "qcom,geni-spi"; 1576 reg = <0 0x00a98000 0 0x4000>; 1577 clock-names = "se"; 1578 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1579 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1580 pinctrl-names = "default"; 1581 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1583 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1584 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1585 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1586 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1587 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1588 dma-names = "tx", "rx"; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 status = "disabled"; 1592 }; 1593 1594 uart7: serial@a9c000 { 1595 compatible = "qcom,geni-debug-uart"; 1596 reg = <0 0x00a9c000 0 0x4000>; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_uart7_default>; 1601 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1602 interconnect-names = "qup-core", "qup-config"; 1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1604 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1605 status = "disabled"; 1606 }; 1607 }; 1608 1609 cnoc_main: interconnect@1500000 { 1610 compatible = "qcom,sm8550-cnoc-main"; 1611 reg = <0 0x01500000 0 0x13080>; 1612 #interconnect-cells = <2>; 1613 qcom,bcm-voters = <&apps_bcm_voter>; 1614 }; 1615 1616 config_noc: interconnect@1600000 { 1617 compatible = "qcom,sm8550-config-noc"; 1618 reg = <0 0x01600000 0 0x6200>; 1619 #interconnect-cells = <2>; 1620 qcom,bcm-voters = <&apps_bcm_voter>; 1621 }; 1622 1623 system_noc: interconnect@1680000 { 1624 compatible = "qcom,sm8550-system-noc"; 1625 reg = <0 0x01680000 0 0x1d080>; 1626 #interconnect-cells = <2>; 1627 qcom,bcm-voters = <&apps_bcm_voter>; 1628 }; 1629 1630 pcie_noc: interconnect@16c0000 { 1631 compatible = "qcom,sm8550-pcie-anoc"; 1632 reg = <0 0x016c0000 0 0x12200>; 1633 #interconnect-cells = <2>; 1634 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1635 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1636 qcom,bcm-voters = <&apps_bcm_voter>; 1637 }; 1638 1639 aggre1_noc: interconnect@16e0000 { 1640 compatible = "qcom,sm8550-aggre1-noc"; 1641 reg = <0 0x016e0000 0 0x14400>; 1642 #interconnect-cells = <2>; 1643 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1644 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1645 qcom,bcm-voters = <&apps_bcm_voter>; 1646 }; 1647 1648 aggre2_noc: interconnect@1700000 { 1649 compatible = "qcom,sm8550-aggre2-noc"; 1650 reg = <0 0x01700000 0 0x1e400>; 1651 #interconnect-cells = <2>; 1652 clocks = <&rpmhcc RPMH_IPA_CLK>; 1653 qcom,bcm-voters = <&apps_bcm_voter>; 1654 }; 1655 1656 mmss_noc: interconnect@1780000 { 1657 compatible = "qcom,sm8550-mmss-noc"; 1658 reg = <0 0x01780000 0 0x5b800>; 1659 #interconnect-cells = <2>; 1660 qcom,bcm-voters = <&apps_bcm_voter>; 1661 }; 1662 1663 pcie0: pci@1c00000 { 1664 device_type = "pci"; 1665 compatible = "qcom,pcie-sm8550"; 1666 reg = <0 0x01c00000 0 0x3000>, 1667 <0 0x60000000 0 0xf1d>, 1668 <0 0x60000f20 0 0xa8>, 1669 <0 0x60001000 0 0x1000>, 1670 <0 0x60100000 0 0x100000>; 1671 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1672 #address-cells = <3>; 1673 #size-cells = <2>; 1674 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1675 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1676 bus-range = <0x00 0xff>; 1677 1678 dma-coherent; 1679 1680 linux,pci-domain = <0>; 1681 num-lanes = <2>; 1682 1683 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1684 interrupt-names = "msi"; 1685 1686 #interrupt-cells = <1>; 1687 interrupt-map-mask = <0 0 0 0x7>; 1688 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1689 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1690 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1691 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1692 1693 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1694 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1695 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1696 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1697 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1698 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1699 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1700 clock-names = "aux", 1701 "cfg", 1702 "bus_master", 1703 "bus_slave", 1704 "slave_q2a", 1705 "ddrss_sf_tbu", 1706 "noc_aggr"; 1707 1708 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1709 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1710 interconnect-names = "pcie-mem", "cpu-pcie"; 1711 1712 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1713 <0x100 &apps_smmu 0x1401 0x1>; 1714 1715 resets = <&gcc GCC_PCIE_0_BCR>; 1716 reset-names = "pci"; 1717 1718 power-domains = <&gcc PCIE_0_GDSC>; 1719 1720 phys = <&pcie0_phy>; 1721 phy-names = "pciephy"; 1722 1723 status = "disabled"; 1724 }; 1725 1726 pcie0_phy: phy@1c06000 { 1727 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1728 reg = <0 0x01c06000 0 0x2000>; 1729 1730 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1731 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1732 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1733 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1734 <&gcc GCC_PCIE_0_PIPE_CLK>; 1735 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1736 "pipe"; 1737 1738 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1739 reset-names = "phy"; 1740 1741 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1742 assigned-clock-rates = <100000000>; 1743 1744 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1745 1746 #clock-cells = <0>; 1747 clock-output-names = "pcie0_pipe_clk"; 1748 1749 #phy-cells = <0>; 1750 1751 status = "disabled"; 1752 }; 1753 1754 pcie1: pci@1c08000 { 1755 device_type = "pci"; 1756 compatible = "qcom,pcie-sm8550"; 1757 reg = <0x0 0x01c08000 0x0 0x3000>, 1758 <0x0 0x40000000 0x0 0xf1d>, 1759 <0x0 0x40000f20 0x0 0xa8>, 1760 <0x0 0x40001000 0x0 0x1000>, 1761 <0x0 0x40100000 0x0 0x100000>; 1762 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1763 #address-cells = <3>; 1764 #size-cells = <2>; 1765 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1766 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1767 bus-range = <0x00 0xff>; 1768 1769 dma-coherent; 1770 1771 linux,pci-domain = <1>; 1772 num-lanes = <2>; 1773 1774 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1775 interrupt-names = "msi"; 1776 1777 #interrupt-cells = <1>; 1778 interrupt-map-mask = <0 0 0 0x7>; 1779 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1780 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1781 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1782 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1783 1784 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1785 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1786 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1787 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1788 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1789 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1790 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1791 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1792 clock-names = "aux", 1793 "cfg", 1794 "bus_master", 1795 "bus_slave", 1796 "slave_q2a", 1797 "ddrss_sf_tbu", 1798 "noc_aggr", 1799 "cnoc_sf_axi"; 1800 1801 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1802 assigned-clock-rates = <19200000>; 1803 1804 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1805 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1806 interconnect-names = "pcie-mem", "cpu-pcie"; 1807 1808 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1809 <0x100 &apps_smmu 0x1481 0x1>; 1810 1811 resets = <&gcc GCC_PCIE_1_BCR>, 1812 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1813 reset-names = "pci", "link_down"; 1814 1815 power-domains = <&gcc PCIE_1_GDSC>; 1816 1817 phys = <&pcie1_phy>; 1818 phy-names = "pciephy"; 1819 1820 status = "disabled"; 1821 }; 1822 1823 pcie1_phy: phy@1c0e000 { 1824 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1825 reg = <0x0 0x01c0e000 0x0 0x2000>; 1826 1827 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1828 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1829 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1830 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1831 <&gcc GCC_PCIE_1_PIPE_CLK>; 1832 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1833 "pipe"; 1834 1835 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1836 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1837 reset-names = "phy", "phy_nocsr"; 1838 1839 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1840 assigned-clock-rates = <100000000>; 1841 1842 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1843 1844 #clock-cells = <0>; 1845 clock-output-names = "pcie1_pipe_clk"; 1846 1847 #phy-cells = <0>; 1848 1849 status = "disabled"; 1850 }; 1851 1852 cryptobam: dma-controller@1dc4000 { 1853 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1854 reg = <0x0 0x01dc4000 0x0 0x28000>; 1855 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1856 #dma-cells = <1>; 1857 qcom,ee = <0>; 1858 qcom,controlled-remotely; 1859 iommus = <&apps_smmu 0x480 0x0>, 1860 <&apps_smmu 0x481 0x0>; 1861 }; 1862 1863 crypto: crypto@1dfa000 { 1864 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1865 reg = <0x0 0x01dfa000 0x0 0x6000>; 1866 dmas = <&cryptobam 4>, <&cryptobam 5>; 1867 dma-names = "rx", "tx"; 1868 iommus = <&apps_smmu 0x480 0x0>, 1869 <&apps_smmu 0x481 0x0>; 1870 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "memory"; 1872 }; 1873 1874 ufs_mem_phy: phy@1d80000 { 1875 compatible = "qcom,sm8550-qmp-ufs-phy"; 1876 reg = <0x0 0x01d80000 0x0 0x2000>; 1877 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1878 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1879 clock-names = "ref", "ref_aux"; 1880 1881 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1882 1883 resets = <&ufs_mem_hc 0>; 1884 reset-names = "ufsphy"; 1885 1886 #clock-cells = <1>; 1887 #phy-cells = <0>; 1888 1889 status = "disabled"; 1890 }; 1891 1892 ufs_mem_hc: ufs@1d84000 { 1893 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1894 "jedec,ufs-2.0"; 1895 reg = <0x0 0x01d84000 0x0 0x3000>; 1896 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1897 phys = <&ufs_mem_phy>; 1898 phy-names = "ufsphy"; 1899 lanes-per-direction = <2>; 1900 #reset-cells = <1>; 1901 resets = <&gcc GCC_UFS_PHY_BCR>; 1902 reset-names = "rst"; 1903 1904 power-domains = <&gcc UFS_PHY_GDSC>; 1905 required-opps = <&rpmhpd_opp_nom>; 1906 1907 iommus = <&apps_smmu 0x60 0x0>; 1908 dma-coherent; 1909 1910 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1912 1913 interconnect-names = "ufs-ddr", "cpu-ufs"; 1914 clock-names = "core_clk", 1915 "bus_aggr_clk", 1916 "iface_clk", 1917 "core_clk_unipro", 1918 "ref_clk", 1919 "tx_lane0_sync_clk", 1920 "rx_lane0_sync_clk", 1921 "rx_lane1_sync_clk"; 1922 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1923 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1924 <&gcc GCC_UFS_PHY_AHB_CLK>, 1925 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1926 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1927 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1928 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1929 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1930 freq-table-hz = 1931 <75000000 300000000>, 1932 <0 0>, 1933 <0 0>, 1934 <75000000 300000000>, 1935 <100000000 403000000>, 1936 <0 0>, 1937 <0 0>, 1938 <0 0>; 1939 qcom,ice = <&ice>; 1940 1941 status = "disabled"; 1942 }; 1943 1944 ice: crypto@1d88000 { 1945 compatible = "qcom,sm8550-inline-crypto-engine", 1946 "qcom,inline-crypto-engine"; 1947 reg = <0 0x01d88000 0 0x8000>; 1948 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1949 }; 1950 1951 tcsr_mutex: hwlock@1f40000 { 1952 compatible = "qcom,tcsr-mutex"; 1953 reg = <0 0x01f40000 0 0x20000>; 1954 #hwlock-cells = <1>; 1955 }; 1956 1957 tcsr: clock-controller@1fc0000 { 1958 compatible = "qcom,sm8550-tcsr", "syscon"; 1959 reg = <0 0x01fc0000 0 0x30000>; 1960 clocks = <&rpmhcc RPMH_CXO_CLK>; 1961 #clock-cells = <1>; 1962 #reset-cells = <1>; 1963 }; 1964 1965 gpucc: clock-controller@3d90000 { 1966 compatible = "qcom,sm8550-gpucc"; 1967 reg = <0 0x03d90000 0 0xa000>; 1968 clocks = <&bi_tcxo_div2>, 1969 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1970 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1971 #clock-cells = <1>; 1972 #reset-cells = <1>; 1973 #power-domain-cells = <1>; 1974 }; 1975 1976 remoteproc_mpss: remoteproc@4080000 { 1977 compatible = "qcom,sm8550-mpss-pas"; 1978 reg = <0x0 0x04080000 0x0 0x4040>; 1979 1980 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1981 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1982 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1983 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1984 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1985 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1986 interrupt-names = "wdog", "fatal", "ready", "handover", 1987 "stop-ack", "shutdown-ack"; 1988 1989 clocks = <&rpmhcc RPMH_CXO_CLK>; 1990 clock-names = "xo"; 1991 1992 power-domains = <&rpmhpd SM8550_CX>, 1993 <&rpmhpd SM8550_MSS>; 1994 power-domain-names = "cx", "mss"; 1995 1996 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1997 1998 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 1999 2000 qcom,qmp = <&aoss_qmp>; 2001 2002 qcom,smem-states = <&smp2p_modem_out 0>; 2003 qcom,smem-state-names = "stop"; 2004 2005 status = "disabled"; 2006 2007 glink-edge { 2008 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2009 IPCC_MPROC_SIGNAL_GLINK_QMP 2010 IRQ_TYPE_EDGE_RISING>; 2011 mboxes = <&ipcc IPCC_CLIENT_MPSS 2012 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2013 label = "mpss"; 2014 qcom,remote-pid = <1>; 2015 }; 2016 }; 2017 2018 lpass_wsa2macro: codec@6aa0000 { 2019 compatible = "qcom,sm8550-lpass-wsa-macro"; 2020 reg = <0 0x06aa0000 0 0x1000>; 2021 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2022 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2023 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2024 <&lpass_vamacro>; 2025 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2026 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2027 assigned-clock-rates = <19200000>; 2028 2029 #clock-cells = <0>; 2030 clock-output-names = "wsa2-mclk"; 2031 pinctrl-names = "default"; 2032 pinctrl-0 = <&wsa2_swr_active>; 2033 #sound-dai-cells = <1>; 2034 }; 2035 2036 swr3: soundwire-controller@6ab0000 { 2037 compatible = "qcom,soundwire-v2.0.0"; 2038 reg = <0 0x06ab0000 0 0x10000>; 2039 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2040 clocks = <&lpass_wsa2macro>; 2041 clock-names = "iface"; 2042 label = "WSA2"; 2043 2044 qcom,din-ports = <4>; 2045 qcom,dout-ports = <9>; 2046 2047 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2048 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2049 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2050 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2051 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2052 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2053 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2054 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2055 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2056 2057 #address-cells = <2>; 2058 #size-cells = <0>; 2059 #sound-dai-cells = <1>; 2060 status = "disabled"; 2061 }; 2062 2063 lpass_rxmacro: codec@6ac0000 { 2064 compatible = "qcom,sm8550-lpass-rx-macro"; 2065 reg = <0 0x06ac0000 0 0x1000>; 2066 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2067 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2068 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2069 <&lpass_vamacro>; 2070 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2071 2072 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2073 assigned-clock-rates = <19200000>; 2074 2075 #clock-cells = <0>; 2076 clock-output-names = "mclk"; 2077 pinctrl-names = "default"; 2078 pinctrl-0 = <&rx_swr_active>; 2079 #sound-dai-cells = <1>; 2080 }; 2081 2082 swr1: soundwire-controller@6ad0000 { 2083 compatible = "qcom,soundwire-v2.0.0"; 2084 reg = <0 0x06ad0000 0 0x10000>; 2085 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2086 clocks = <&lpass_rxmacro>; 2087 clock-names = "iface"; 2088 label = "RX"; 2089 2090 qcom,din-ports = <0>; 2091 qcom,dout-ports = <10>; 2092 2093 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2094 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2095 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2096 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2097 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2098 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2099 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2100 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2101 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2102 2103 #address-cells = <2>; 2104 #size-cells = <0>; 2105 #sound-dai-cells = <1>; 2106 status = "disabled"; 2107 }; 2108 2109 lpass_txmacro: codec@6ae0000 { 2110 compatible = "qcom,sm8550-lpass-tx-macro"; 2111 reg = <0 0x06ae0000 0 0x1000>; 2112 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2113 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2114 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2115 <&lpass_vamacro>; 2116 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2117 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2118 2119 assigned-clock-rates = <19200000>; 2120 2121 #clock-cells = <0>; 2122 clock-output-names = "mclk"; 2123 pinctrl-names = "default"; 2124 pinctrl-0 = <&tx_swr_active>; 2125 #sound-dai-cells = <1>; 2126 }; 2127 2128 lpass_wsamacro: codec@6b00000 { 2129 compatible = "qcom,sm8550-lpass-wsa-macro"; 2130 reg = <0 0x06b00000 0 0x1000>; 2131 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2132 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2133 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2134 <&lpass_vamacro>; 2135 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2136 2137 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2138 assigned-clock-rates = <19200000>; 2139 2140 #clock-cells = <0>; 2141 clock-output-names = "mclk"; 2142 pinctrl-names = "default"; 2143 pinctrl-0 = <&wsa_swr_active>; 2144 #sound-dai-cells = <1>; 2145 }; 2146 2147 swr0: soundwire-controller@6b10000 { 2148 compatible = "qcom,soundwire-v2.0.0"; 2149 reg = <0 0x06b10000 0 0x10000>; 2150 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2151 clocks = <&lpass_wsamacro>; 2152 clock-names = "iface"; 2153 label = "WSA"; 2154 2155 qcom,din-ports = <4>; 2156 qcom,dout-ports = <9>; 2157 2158 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2159 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2160 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2161 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2162 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2163 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2164 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2165 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2166 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2167 2168 #address-cells = <2>; 2169 #size-cells = <0>; 2170 #sound-dai-cells = <1>; 2171 status = "disabled"; 2172 }; 2173 2174 swr2: soundwire-controller@6d30000 { 2175 compatible = "qcom,soundwire-v2.0.0"; 2176 reg = <0 0x06d30000 0 0x10000>; 2177 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2179 interrupt-names = "core", "wakeup"; 2180 clocks = <&lpass_vamacro>; 2181 clock-names = "iface"; 2182 label = "TX"; 2183 2184 qcom,din-ports = <4>; 2185 qcom,dout-ports = <0>; 2186 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2187 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2188 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2189 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2190 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2191 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2193 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2194 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2195 2196 #address-cells = <2>; 2197 #size-cells = <0>; 2198 #sound-dai-cells = <1>; 2199 status = "disabled"; 2200 }; 2201 2202 lpass_vamacro: codec@6d44000 { 2203 compatible = "qcom,sm8550-lpass-va-macro"; 2204 reg = <0 0x06d44000 0 0x1000>; 2205 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2206 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2207 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2208 clock-names = "mclk", "macro", "dcodec"; 2209 2210 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2211 assigned-clock-rates = <19200000>; 2212 2213 #clock-cells = <0>; 2214 clock-output-names = "fsgen"; 2215 #sound-dai-cells = <1>; 2216 }; 2217 2218 lpass_tlmm: pinctrl@6e80000 { 2219 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2220 reg = <0 0x06e80000 0 0x20000>, 2221 <0 0x07250000 0 0x10000>; 2222 gpio-controller; 2223 #gpio-cells = <2>; 2224 gpio-ranges = <&lpass_tlmm 0 0 23>; 2225 2226 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2227 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2228 clock-names = "core", "audio"; 2229 2230 tx_swr_active: tx-swr-active-state { 2231 clk-pins { 2232 pins = "gpio0"; 2233 function = "swr_tx_clk"; 2234 drive-strength = <2>; 2235 slew-rate = <1>; 2236 bias-disable; 2237 }; 2238 2239 data-pins { 2240 pins = "gpio1", "gpio2", "gpio14"; 2241 function = "swr_tx_data"; 2242 drive-strength = <2>; 2243 slew-rate = <1>; 2244 bias-bus-hold; 2245 }; 2246 }; 2247 2248 rx_swr_active: rx-swr-active-state { 2249 clk-pins { 2250 pins = "gpio3"; 2251 function = "swr_rx_clk"; 2252 drive-strength = <2>; 2253 slew-rate = <1>; 2254 bias-disable; 2255 }; 2256 2257 data-pins { 2258 pins = "gpio4", "gpio5"; 2259 function = "swr_rx_data"; 2260 drive-strength = <2>; 2261 slew-rate = <1>; 2262 bias-bus-hold; 2263 }; 2264 }; 2265 2266 dmic01_default: dmic01-default-state { 2267 clk-pins { 2268 pins = "gpio6"; 2269 function = "dmic1_clk"; 2270 drive-strength = <8>; 2271 output-high; 2272 }; 2273 2274 data-pins { 2275 pins = "gpio7"; 2276 function = "dmic1_data"; 2277 drive-strength = <8>; 2278 input-enable; 2279 }; 2280 }; 2281 2282 dmic02_default: dmic02-default-state { 2283 clk-pins { 2284 pins = "gpio8"; 2285 function = "dmic2_clk"; 2286 drive-strength = <8>; 2287 output-high; 2288 }; 2289 2290 data-pins { 2291 pins = "gpio9"; 2292 function = "dmic2_data"; 2293 drive-strength = <8>; 2294 input-enable; 2295 }; 2296 }; 2297 2298 wsa_swr_active: wsa-swr-active-state { 2299 clk-pins { 2300 pins = "gpio10"; 2301 function = "wsa_swr_clk"; 2302 drive-strength = <2>; 2303 slew-rate = <1>; 2304 bias-disable; 2305 }; 2306 2307 data-pins { 2308 pins = "gpio11"; 2309 function = "wsa_swr_data"; 2310 drive-strength = <2>; 2311 slew-rate = <1>; 2312 bias-bus-hold; 2313 }; 2314 }; 2315 2316 wsa2_swr_active: wsa2-swr-active-state { 2317 clk-pins { 2318 pins = "gpio15"; 2319 function = "wsa2_swr_clk"; 2320 drive-strength = <2>; 2321 slew-rate = <1>; 2322 bias-disable; 2323 }; 2324 2325 data-pins { 2326 pins = "gpio16"; 2327 function = "wsa2_swr_data"; 2328 drive-strength = <2>; 2329 slew-rate = <1>; 2330 bias-bus-hold; 2331 }; 2332 }; 2333 }; 2334 2335 lpass_lpiaon_noc: interconnect@7400000 { 2336 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2337 reg = <0 0x07400000 0 0x19080>; 2338 #interconnect-cells = <2>; 2339 qcom,bcm-voters = <&apps_bcm_voter>; 2340 }; 2341 2342 lpass_lpicx_noc: interconnect@7430000 { 2343 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2344 reg = <0 0x07430000 0 0x3a200>; 2345 #interconnect-cells = <2>; 2346 qcom,bcm-voters = <&apps_bcm_voter>; 2347 }; 2348 2349 lpass_ag_noc: interconnect@7e40000 { 2350 compatible = "qcom,sm8550-lpass-ag-noc"; 2351 reg = <0 0x07e40000 0 0xe080>; 2352 #interconnect-cells = <2>; 2353 qcom,bcm-voters = <&apps_bcm_voter>; 2354 }; 2355 2356 sdhc_2: mmc@8804000 { 2357 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2358 reg = <0 0x08804000 0 0x1000>; 2359 2360 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2362 interrupt-names = "hc_irq", "pwr_irq"; 2363 2364 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2365 <&gcc GCC_SDCC2_APPS_CLK>, 2366 <&rpmhcc RPMH_CXO_CLK>; 2367 clock-names = "iface", "core", "xo"; 2368 iommus = <&apps_smmu 0x540 0>; 2369 qcom,dll-config = <0x0007642c>; 2370 qcom,ddr-config = <0x80040868>; 2371 power-domains = <&rpmhpd SM8550_CX>; 2372 operating-points-v2 = <&sdhc2_opp_table>; 2373 2374 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2375 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2376 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2377 bus-width = <4>; 2378 dma-coherent; 2379 2380 /* Forbid SDR104/SDR50 - broken hw! */ 2381 sdhci-caps-mask = <0x3 0>; 2382 2383 status = "disabled"; 2384 2385 sdhc2_opp_table: opp-table { 2386 compatible = "operating-points-v2"; 2387 2388 opp-19200000 { 2389 opp-hz = /bits/ 64 <19200000>; 2390 required-opps = <&rpmhpd_opp_min_svs>; 2391 }; 2392 2393 opp-50000000 { 2394 opp-hz = /bits/ 64 <50000000>; 2395 required-opps = <&rpmhpd_opp_low_svs>; 2396 }; 2397 2398 opp-100000000 { 2399 opp-hz = /bits/ 64 <100000000>; 2400 required-opps = <&rpmhpd_opp_svs>; 2401 }; 2402 2403 opp-202000000 { 2404 opp-hz = /bits/ 64 <202000000>; 2405 required-opps = <&rpmhpd_opp_svs_l1>; 2406 }; 2407 }; 2408 }; 2409 2410 videocc: clock-controller@aaf0000 { 2411 compatible = "qcom,sm8550-videocc"; 2412 reg = <0 0x0aaf0000 0 0x10000>; 2413 clocks = <&bi_tcxo_div2>, 2414 <&gcc GCC_VIDEO_AHB_CLK>; 2415 power-domains = <&rpmhpd SM8550_MMCX>; 2416 required-opps = <&rpmhpd_opp_low_svs>; 2417 #clock-cells = <1>; 2418 #reset-cells = <1>; 2419 #power-domain-cells = <1>; 2420 }; 2421 2422 mdss: display-subsystem@ae00000 { 2423 compatible = "qcom,sm8550-mdss"; 2424 reg = <0 0x0ae00000 0 0x1000>; 2425 reg-names = "mdss"; 2426 2427 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2428 interrupt-controller; 2429 #interrupt-cells = <1>; 2430 2431 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2432 <&gcc GCC_DISP_AHB_CLK>, 2433 <&gcc GCC_DISP_HF_AXI_CLK>, 2434 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2435 2436 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2437 2438 power-domains = <&dispcc MDSS_GDSC>; 2439 2440 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2441 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2442 interconnect-names = "mdp0-mem", "mdp1-mem"; 2443 2444 iommus = <&apps_smmu 0x1c00 0x2>; 2445 2446 #address-cells = <2>; 2447 #size-cells = <2>; 2448 ranges; 2449 2450 status = "disabled"; 2451 2452 mdss_mdp: display-controller@ae01000 { 2453 compatible = "qcom,sm8550-dpu"; 2454 reg = <0 0x0ae01000 0 0x8f000>, 2455 <0 0x0aeb0000 0 0x2008>; 2456 reg-names = "mdp", "vbif"; 2457 2458 interrupt-parent = <&mdss>; 2459 interrupts = <0>; 2460 2461 clocks = <&gcc GCC_DISP_AHB_CLK>, 2462 <&gcc GCC_DISP_HF_AXI_CLK>, 2463 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2464 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2465 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2466 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2467 clock-names = "bus", 2468 "nrt_bus", 2469 "iface", 2470 "lut", 2471 "core", 2472 "vsync"; 2473 2474 power-domains = <&rpmhpd SM8550_MMCX>; 2475 2476 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2477 assigned-clock-rates = <19200000>; 2478 2479 operating-points-v2 = <&mdp_opp_table>; 2480 2481 ports { 2482 #address-cells = <1>; 2483 #size-cells = <0>; 2484 2485 port@0 { 2486 reg = <0>; 2487 dpu_intf1_out: endpoint { 2488 remote-endpoint = <&mdss_dsi0_in>; 2489 }; 2490 }; 2491 2492 port@1 { 2493 reg = <1>; 2494 dpu_intf2_out: endpoint { 2495 remote-endpoint = <&mdss_dsi1_in>; 2496 }; 2497 }; 2498 2499 port@2 { 2500 reg = <2>; 2501 dpu_intf0_out: endpoint { 2502 remote-endpoint = <&mdss_dp0_in>; 2503 }; 2504 }; 2505 }; 2506 2507 mdp_opp_table: opp-table { 2508 compatible = "operating-points-v2"; 2509 2510 opp-200000000 { 2511 opp-hz = /bits/ 64 <200000000>; 2512 required-opps = <&rpmhpd_opp_low_svs>; 2513 }; 2514 2515 opp-325000000 { 2516 opp-hz = /bits/ 64 <325000000>; 2517 required-opps = <&rpmhpd_opp_svs>; 2518 }; 2519 2520 opp-375000000 { 2521 opp-hz = /bits/ 64 <375000000>; 2522 required-opps = <&rpmhpd_opp_svs_l1>; 2523 }; 2524 2525 opp-514000000 { 2526 opp-hz = /bits/ 64 <514000000>; 2527 required-opps = <&rpmhpd_opp_nom>; 2528 }; 2529 }; 2530 }; 2531 2532 mdss_dp0: displayport-controller@ae90000 { 2533 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2534 reg = <0 0xae90000 0 0x200>, 2535 <0 0xae90200 0 0x200>, 2536 <0 0xae90400 0 0xc00>, 2537 <0 0xae91000 0 0x400>, 2538 <0 0xae91400 0 0x400>; 2539 interrupt-parent = <&mdss>; 2540 interrupts = <12>; 2541 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2542 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2543 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2544 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2545 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2546 clock-names = "core_iface", 2547 "core_aux", 2548 "ctrl_link", 2549 "ctrl_link_iface", 2550 "stream_pixel"; 2551 2552 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2553 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2554 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2555 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2556 2557 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2558 phy-names = "dp"; 2559 2560 #sound-dai-cells = <0>; 2561 2562 operating-points-v2 = <&dp_opp_table>; 2563 power-domains = <&rpmhpd SM8550_MMCX>; 2564 2565 status = "disabled"; 2566 2567 ports { 2568 #address-cells = <1>; 2569 #size-cells = <0>; 2570 2571 port@0 { 2572 reg = <0>; 2573 mdss_dp0_in: endpoint { 2574 remote-endpoint = <&dpu_intf0_out>; 2575 }; 2576 }; 2577 2578 port@1 { 2579 reg = <1>; 2580 mdss_dp0_out: endpoint { 2581 }; 2582 }; 2583 }; 2584 2585 dp_opp_table: opp-table { 2586 compatible = "operating-points-v2"; 2587 2588 opp-162000000 { 2589 opp-hz = /bits/ 64 <162000000>; 2590 required-opps = <&rpmhpd_opp_low_svs_d1>; 2591 }; 2592 2593 opp-270000000 { 2594 opp-hz = /bits/ 64 <270000000>; 2595 required-opps = <&rpmhpd_opp_low_svs>; 2596 }; 2597 2598 opp-540000000 { 2599 opp-hz = /bits/ 64 <540000000>; 2600 required-opps = <&rpmhpd_opp_svs_l1>; 2601 }; 2602 2603 opp-810000000 { 2604 opp-hz = /bits/ 64 <810000000>; 2605 required-opps = <&rpmhpd_opp_nom>; 2606 }; 2607 }; 2608 }; 2609 2610 mdss_dsi0: dsi@ae94000 { 2611 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2612 reg = <0 0x0ae94000 0 0x400>; 2613 reg-names = "dsi_ctrl"; 2614 2615 interrupt-parent = <&mdss>; 2616 interrupts = <4>; 2617 2618 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2619 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2620 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2621 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2622 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2623 <&gcc GCC_DISP_HF_AXI_CLK>; 2624 clock-names = "byte", 2625 "byte_intf", 2626 "pixel", 2627 "core", 2628 "iface", 2629 "bus"; 2630 2631 power-domains = <&rpmhpd SM8550_MMCX>; 2632 2633 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2634 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2635 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2636 <&mdss_dsi0_phy 1>; 2637 2638 operating-points-v2 = <&mdss_dsi_opp_table>; 2639 2640 phys = <&mdss_dsi0_phy>; 2641 phy-names = "dsi"; 2642 2643 #address-cells = <1>; 2644 #size-cells = <0>; 2645 2646 status = "disabled"; 2647 2648 ports { 2649 #address-cells = <1>; 2650 #size-cells = <0>; 2651 2652 port@0 { 2653 reg = <0>; 2654 mdss_dsi0_in: endpoint { 2655 remote-endpoint = <&dpu_intf1_out>; 2656 }; 2657 }; 2658 2659 port@1 { 2660 reg = <1>; 2661 mdss_dsi0_out: endpoint { 2662 }; 2663 }; 2664 }; 2665 2666 mdss_dsi_opp_table: opp-table { 2667 compatible = "operating-points-v2"; 2668 2669 opp-187500000 { 2670 opp-hz = /bits/ 64 <187500000>; 2671 required-opps = <&rpmhpd_opp_low_svs>; 2672 }; 2673 2674 opp-300000000 { 2675 opp-hz = /bits/ 64 <300000000>; 2676 required-opps = <&rpmhpd_opp_svs>; 2677 }; 2678 2679 opp-358000000 { 2680 opp-hz = /bits/ 64 <358000000>; 2681 required-opps = <&rpmhpd_opp_svs_l1>; 2682 }; 2683 }; 2684 }; 2685 2686 mdss_dsi0_phy: phy@ae95000 { 2687 compatible = "qcom,sm8550-dsi-phy-4nm"; 2688 reg = <0 0x0ae95000 0 0x200>, 2689 <0 0x0ae95200 0 0x280>, 2690 <0 0x0ae95500 0 0x400>; 2691 reg-names = "dsi_phy", 2692 "dsi_phy_lane", 2693 "dsi_pll"; 2694 2695 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2696 <&rpmhcc RPMH_CXO_CLK>; 2697 clock-names = "iface", "ref"; 2698 2699 #clock-cells = <1>; 2700 #phy-cells = <0>; 2701 2702 status = "disabled"; 2703 }; 2704 2705 mdss_dsi1: dsi@ae96000 { 2706 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2707 reg = <0 0x0ae96000 0 0x400>; 2708 reg-names = "dsi_ctrl"; 2709 2710 interrupt-parent = <&mdss>; 2711 interrupts = <5>; 2712 2713 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2714 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2715 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2716 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2717 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2718 <&gcc GCC_DISP_HF_AXI_CLK>; 2719 clock-names = "byte", 2720 "byte_intf", 2721 "pixel", 2722 "core", 2723 "iface", 2724 "bus"; 2725 2726 power-domains = <&rpmhpd SM8550_MMCX>; 2727 2728 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2729 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2730 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2731 <&mdss_dsi1_phy 1>; 2732 2733 operating-points-v2 = <&mdss_dsi_opp_table>; 2734 2735 phys = <&mdss_dsi1_phy>; 2736 phy-names = "dsi"; 2737 2738 #address-cells = <1>; 2739 #size-cells = <0>; 2740 2741 status = "disabled"; 2742 2743 ports { 2744 #address-cells = <1>; 2745 #size-cells = <0>; 2746 2747 port@0 { 2748 reg = <0>; 2749 mdss_dsi1_in: endpoint { 2750 remote-endpoint = <&dpu_intf2_out>; 2751 }; 2752 }; 2753 2754 port@1 { 2755 reg = <1>; 2756 mdss_dsi1_out: endpoint { 2757 }; 2758 }; 2759 }; 2760 }; 2761 2762 mdss_dsi1_phy: phy@ae97000 { 2763 compatible = "qcom,sm8550-dsi-phy-4nm"; 2764 reg = <0 0x0ae97000 0 0x200>, 2765 <0 0x0ae97200 0 0x280>, 2766 <0 0x0ae97500 0 0x400>; 2767 reg-names = "dsi_phy", 2768 "dsi_phy_lane", 2769 "dsi_pll"; 2770 2771 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2772 <&rpmhcc RPMH_CXO_CLK>; 2773 clock-names = "iface", "ref"; 2774 2775 #clock-cells = <1>; 2776 #phy-cells = <0>; 2777 2778 status = "disabled"; 2779 }; 2780 }; 2781 2782 dispcc: clock-controller@af00000 { 2783 compatible = "qcom,sm8550-dispcc"; 2784 reg = <0 0x0af00000 0 0x20000>; 2785 clocks = <&bi_tcxo_div2>, 2786 <&bi_tcxo_ao_div2>, 2787 <&gcc GCC_DISP_AHB_CLK>, 2788 <&sleep_clk>, 2789 <&mdss_dsi0_phy 0>, 2790 <&mdss_dsi0_phy 1>, 2791 <&mdss_dsi1_phy 0>, 2792 <&mdss_dsi1_phy 1>, 2793 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2794 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2795 <0>, /* dp1 */ 2796 <0>, 2797 <0>, /* dp2 */ 2798 <0>, 2799 <0>, /* dp3 */ 2800 <0>; 2801 power-domains = <&rpmhpd SM8550_MMCX>; 2802 required-opps = <&rpmhpd_opp_low_svs>; 2803 #clock-cells = <1>; 2804 #reset-cells = <1>; 2805 #power-domain-cells = <1>; 2806 }; 2807 2808 usb_1_hsphy: phy@88e3000 { 2809 compatible = "qcom,sm8550-snps-eusb2-phy"; 2810 reg = <0x0 0x088e3000 0x0 0x154>; 2811 #phy-cells = <0>; 2812 2813 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2814 clock-names = "ref"; 2815 2816 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2817 2818 status = "disabled"; 2819 }; 2820 2821 usb_dp_qmpphy: phy@88e8000 { 2822 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2823 reg = <0x0 0x088e8000 0x0 0x3000>; 2824 2825 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2826 <&rpmhcc RPMH_CXO_CLK>, 2827 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2828 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2829 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2830 2831 power-domains = <&gcc USB3_PHY_GDSC>; 2832 2833 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2834 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2835 reset-names = "phy", "common"; 2836 2837 #clock-cells = <1>; 2838 #phy-cells = <1>; 2839 2840 status = "disabled"; 2841 }; 2842 2843 usb_1: usb@a6f8800 { 2844 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2845 reg = <0x0 0x0a6f8800 0x0 0x400>; 2846 #address-cells = <2>; 2847 #size-cells = <2>; 2848 ranges; 2849 2850 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2851 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2852 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2853 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2854 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2855 <&tcsr TCSR_USB3_CLKREF_EN>; 2856 clock-names = "cfg_noc", 2857 "core", 2858 "iface", 2859 "sleep", 2860 "mock_utmi", 2861 "xo"; 2862 2863 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2864 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2865 assigned-clock-rates = <19200000>, <200000000>; 2866 2867 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2868 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2869 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2870 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2871 interrupt-names = "hs_phy_irq", 2872 "ss_phy_irq", 2873 "dm_hs_phy_irq", 2874 "dp_hs_phy_irq"; 2875 2876 power-domains = <&gcc USB30_PRIM_GDSC>; 2877 required-opps = <&rpmhpd_opp_nom>; 2878 2879 resets = <&gcc GCC_USB30_PRIM_BCR>; 2880 2881 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2882 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2883 interconnect-names = "usb-ddr", "apps-usb"; 2884 2885 status = "disabled"; 2886 2887 usb_1_dwc3: usb@a600000 { 2888 compatible = "snps,dwc3"; 2889 reg = <0x0 0x0a600000 0x0 0xcd00>; 2890 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2891 iommus = <&apps_smmu 0x40 0x0>; 2892 snps,dis_u2_susphy_quirk; 2893 snps,dis_enblslpm_quirk; 2894 snps,usb3_lpm_capable; 2895 phys = <&usb_1_hsphy>, 2896 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2897 phy-names = "usb2-phy", "usb3-phy"; 2898 2899 ports { 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 2903 port@0 { 2904 reg = <0>; 2905 2906 usb_1_dwc3_hs: endpoint { 2907 }; 2908 }; 2909 2910 port@1 { 2911 reg = <1>; 2912 2913 usb_1_dwc3_ss: endpoint { 2914 }; 2915 }; 2916 }; 2917 }; 2918 }; 2919 2920 pdc: interrupt-controller@b220000 { 2921 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2922 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2923 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2924 <125 63 1>, <126 716 12>, 2925 <138 251 5>; 2926 #interrupt-cells = <2>; 2927 interrupt-parent = <&intc>; 2928 interrupt-controller; 2929 }; 2930 2931 tsens0: thermal-sensor@c271000 { 2932 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2933 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2934 <0 0x0c222000 0 0x1000>; /* SROT */ 2935 #qcom,sensors = <16>; 2936 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2938 interrupt-names = "uplow", "critical"; 2939 #thermal-sensor-cells = <1>; 2940 }; 2941 2942 tsens1: thermal-sensor@c272000 { 2943 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2944 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2945 <0 0x0c223000 0 0x1000>; /* SROT */ 2946 #qcom,sensors = <16>; 2947 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2949 interrupt-names = "uplow", "critical"; 2950 #thermal-sensor-cells = <1>; 2951 }; 2952 2953 tsens2: thermal-sensor@c273000 { 2954 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2955 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2956 <0 0x0c224000 0 0x1000>; /* SROT */ 2957 #qcom,sensors = <16>; 2958 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2960 interrupt-names = "uplow", "critical"; 2961 #thermal-sensor-cells = <1>; 2962 }; 2963 2964 aoss_qmp: power-management@c300000 { 2965 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2966 reg = <0 0x0c300000 0 0x400>; 2967 interrupt-parent = <&ipcc>; 2968 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2969 IRQ_TYPE_EDGE_RISING>; 2970 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2971 2972 #clock-cells = <0>; 2973 }; 2974 2975 sram@c3f0000 { 2976 compatible = "qcom,rpmh-stats"; 2977 reg = <0 0x0c3f0000 0 0x400>; 2978 }; 2979 2980 spmi_bus: spmi@c400000 { 2981 compatible = "qcom,spmi-pmic-arb"; 2982 reg = <0 0x0c400000 0 0x3000>, 2983 <0 0x0c500000 0 0x4000000>, 2984 <0 0x0c440000 0 0x80000>, 2985 <0 0x0c4c0000 0 0x20000>, 2986 <0 0x0c42d000 0 0x4000>; 2987 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2988 interrupt-names = "periph_irq"; 2989 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2990 qcom,ee = <0>; 2991 qcom,channel = <0>; 2992 qcom,bus-id = <0>; 2993 #address-cells = <2>; 2994 #size-cells = <0>; 2995 interrupt-controller; 2996 #interrupt-cells = <4>; 2997 }; 2998 2999 tlmm: pinctrl@f100000 { 3000 compatible = "qcom,sm8550-tlmm"; 3001 reg = <0 0x0f100000 0 0x300000>; 3002 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3003 gpio-controller; 3004 #gpio-cells = <2>; 3005 interrupt-controller; 3006 #interrupt-cells = <2>; 3007 gpio-ranges = <&tlmm 0 0 211>; 3008 wakeup-parent = <&pdc>; 3009 3010 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3011 /* SDA, SCL */ 3012 pins = "gpio16", "gpio17"; 3013 function = "i2chub0_se0"; 3014 drive-strength = <2>; 3015 bias-pull-up; 3016 }; 3017 3018 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3019 /* SDA, SCL */ 3020 pins = "gpio18", "gpio19"; 3021 function = "i2chub0_se1"; 3022 drive-strength = <2>; 3023 bias-pull-up; 3024 }; 3025 3026 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3027 /* SDA, SCL */ 3028 pins = "gpio20", "gpio21"; 3029 function = "i2chub0_se2"; 3030 drive-strength = <2>; 3031 bias-pull-up; 3032 }; 3033 3034 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3035 /* SDA, SCL */ 3036 pins = "gpio22", "gpio23"; 3037 function = "i2chub0_se3"; 3038 drive-strength = <2>; 3039 bias-pull-up; 3040 }; 3041 3042 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3043 /* SDA, SCL */ 3044 pins = "gpio4", "gpio5"; 3045 function = "i2chub0_se4"; 3046 drive-strength = <2>; 3047 bias-pull-up; 3048 }; 3049 3050 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3051 /* SDA, SCL */ 3052 pins = "gpio6", "gpio7"; 3053 function = "i2chub0_se5"; 3054 drive-strength = <2>; 3055 bias-pull-up; 3056 }; 3057 3058 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3059 /* SDA, SCL */ 3060 pins = "gpio8", "gpio9"; 3061 function = "i2chub0_se6"; 3062 drive-strength = <2>; 3063 bias-pull-up; 3064 }; 3065 3066 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3067 /* SDA, SCL */ 3068 pins = "gpio10", "gpio11"; 3069 function = "i2chub0_se7"; 3070 drive-strength = <2>; 3071 bias-pull-up; 3072 }; 3073 3074 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3075 /* SDA, SCL */ 3076 pins = "gpio206", "gpio207"; 3077 function = "i2chub0_se8"; 3078 drive-strength = <2>; 3079 bias-pull-up; 3080 }; 3081 3082 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3083 /* SDA, SCL */ 3084 pins = "gpio84", "gpio85"; 3085 function = "i2chub0_se9"; 3086 drive-strength = <2>; 3087 bias-pull-up; 3088 }; 3089 3090 pcie0_default_state: pcie0-default-state { 3091 perst-pins { 3092 pins = "gpio94"; 3093 function = "gpio"; 3094 drive-strength = <2>; 3095 bias-pull-down; 3096 }; 3097 3098 clkreq-pins { 3099 pins = "gpio95"; 3100 function = "pcie0_clk_req_n"; 3101 drive-strength = <2>; 3102 bias-pull-up; 3103 }; 3104 3105 wake-pins { 3106 pins = "gpio96"; 3107 function = "gpio"; 3108 drive-strength = <2>; 3109 bias-pull-up; 3110 }; 3111 }; 3112 3113 pcie1_default_state: pcie1-default-state { 3114 perst-pins { 3115 pins = "gpio97"; 3116 function = "gpio"; 3117 drive-strength = <2>; 3118 bias-pull-down; 3119 }; 3120 3121 clkreq-pins { 3122 pins = "gpio98"; 3123 function = "pcie1_clk_req_n"; 3124 drive-strength = <2>; 3125 bias-pull-up; 3126 }; 3127 3128 wake-pins { 3129 pins = "gpio99"; 3130 function = "gpio"; 3131 drive-strength = <2>; 3132 bias-pull-up; 3133 }; 3134 }; 3135 3136 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3137 /* SDA, SCL */ 3138 pins = "gpio28", "gpio29"; 3139 function = "qup1_se0"; 3140 drive-strength = <2>; 3141 bias-pull-up = <2200>; 3142 }; 3143 3144 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3145 /* SDA, SCL */ 3146 pins = "gpio32", "gpio33"; 3147 function = "qup1_se1"; 3148 drive-strength = <2>; 3149 bias-pull-up = <2200>; 3150 }; 3151 3152 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3153 /* SDA, SCL */ 3154 pins = "gpio36", "gpio37"; 3155 function = "qup1_se2"; 3156 drive-strength = <2>; 3157 bias-pull-up = <2200>; 3158 }; 3159 3160 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3161 /* SDA, SCL */ 3162 pins = "gpio40", "gpio41"; 3163 function = "qup1_se3"; 3164 drive-strength = <2>; 3165 bias-pull-up = <2200>; 3166 }; 3167 3168 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3169 /* SDA, SCL */ 3170 pins = "gpio44", "gpio45"; 3171 function = "qup1_se4"; 3172 drive-strength = <2>; 3173 bias-pull-up = <2200>; 3174 }; 3175 3176 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3177 /* SDA, SCL */ 3178 pins = "gpio52", "gpio53"; 3179 function = "qup1_se5"; 3180 drive-strength = <2>; 3181 bias-pull-up = <2200>; 3182 }; 3183 3184 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3185 /* SDA, SCL */ 3186 pins = "gpio48", "gpio49"; 3187 function = "qup1_se6"; 3188 drive-strength = <2>; 3189 bias-pull-up = <2200>; 3190 }; 3191 3192 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3193 scl-pins { 3194 pins = "gpio57"; 3195 function = "qup2_se0_l1_mira"; 3196 drive-strength = <2>; 3197 bias-pull-up = <2200>; 3198 }; 3199 3200 sda-pins { 3201 pins = "gpio56"; 3202 function = "qup2_se0_l0_mira"; 3203 drive-strength = <2>; 3204 bias-pull-up = <2200>; 3205 }; 3206 }; 3207 3208 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3209 /* SDA, SCL */ 3210 pins = "gpio60", "gpio61"; 3211 function = "qup2_se1"; 3212 drive-strength = <2>; 3213 bias-pull-up = <2200>; 3214 }; 3215 3216 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3217 /* SDA, SCL */ 3218 pins = "gpio64", "gpio65"; 3219 function = "qup2_se2"; 3220 drive-strength = <2>; 3221 bias-pull-up = <2200>; 3222 }; 3223 3224 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3225 /* SDA, SCL */ 3226 pins = "gpio68", "gpio69"; 3227 function = "qup2_se3"; 3228 drive-strength = <2>; 3229 bias-pull-up = <2200>; 3230 }; 3231 3232 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3233 /* SDA, SCL */ 3234 pins = "gpio2", "gpio3"; 3235 function = "qup2_se4"; 3236 drive-strength = <2>; 3237 bias-pull-up = <2200>; 3238 }; 3239 3240 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3241 /* SDA, SCL */ 3242 pins = "gpio80", "gpio81"; 3243 function = "qup2_se5"; 3244 drive-strength = <2>; 3245 bias-pull-up = <2200>; 3246 }; 3247 3248 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3249 /* SDA, SCL */ 3250 pins = "gpio72", "gpio106"; 3251 function = "qup2_se7"; 3252 drive-strength = <2>; 3253 bias-pull-up = <2200>; 3254 }; 3255 3256 qup_spi0_cs: qup-spi0-cs-state { 3257 pins = "gpio31"; 3258 function = "qup1_se0"; 3259 drive-strength = <6>; 3260 bias-disable; 3261 }; 3262 3263 qup_spi0_data_clk: qup-spi0-data-clk-state { 3264 /* MISO, MOSI, CLK */ 3265 pins = "gpio28", "gpio29", "gpio30"; 3266 function = "qup1_se0"; 3267 drive-strength = <6>; 3268 bias-disable; 3269 }; 3270 3271 qup_spi1_cs: qup-spi1-cs-state { 3272 pins = "gpio35"; 3273 function = "qup1_se1"; 3274 drive-strength = <6>; 3275 bias-disable; 3276 }; 3277 3278 qup_spi1_data_clk: qup-spi1-data-clk-state { 3279 /* MISO, MOSI, CLK */ 3280 pins = "gpio32", "gpio33", "gpio34"; 3281 function = "qup1_se1"; 3282 drive-strength = <6>; 3283 bias-disable; 3284 }; 3285 3286 qup_spi2_cs: qup-spi2-cs-state { 3287 pins = "gpio39"; 3288 function = "qup1_se2"; 3289 drive-strength = <6>; 3290 bias-disable; 3291 }; 3292 3293 qup_spi2_data_clk: qup-spi2-data-clk-state { 3294 /* MISO, MOSI, CLK */ 3295 pins = "gpio36", "gpio37", "gpio38"; 3296 function = "qup1_se2"; 3297 drive-strength = <6>; 3298 bias-disable; 3299 }; 3300 3301 qup_spi3_cs: qup-spi3-cs-state { 3302 pins = "gpio43"; 3303 function = "qup1_se3"; 3304 drive-strength = <6>; 3305 bias-disable; 3306 }; 3307 3308 qup_spi3_data_clk: qup-spi3-data-clk-state { 3309 /* MISO, MOSI, CLK */ 3310 pins = "gpio40", "gpio41", "gpio42"; 3311 function = "qup1_se3"; 3312 drive-strength = <6>; 3313 bias-disable; 3314 }; 3315 3316 qup_spi4_cs: qup-spi4-cs-state { 3317 pins = "gpio47"; 3318 function = "qup1_se4"; 3319 drive-strength = <6>; 3320 bias-disable; 3321 }; 3322 3323 qup_spi4_data_clk: qup-spi4-data-clk-state { 3324 /* MISO, MOSI, CLK */ 3325 pins = "gpio44", "gpio45", "gpio46"; 3326 function = "qup1_se4"; 3327 drive-strength = <6>; 3328 bias-disable; 3329 }; 3330 3331 qup_spi5_cs: qup-spi5-cs-state { 3332 pins = "gpio55"; 3333 function = "qup1_se5"; 3334 drive-strength = <6>; 3335 bias-disable; 3336 }; 3337 3338 qup_spi5_data_clk: qup-spi5-data-clk-state { 3339 /* MISO, MOSI, CLK */ 3340 pins = "gpio52", "gpio53", "gpio54"; 3341 function = "qup1_se5"; 3342 drive-strength = <6>; 3343 bias-disable; 3344 }; 3345 3346 qup_spi6_cs: qup-spi6-cs-state { 3347 pins = "gpio51"; 3348 function = "qup1_se6"; 3349 drive-strength = <6>; 3350 bias-disable; 3351 }; 3352 3353 qup_spi6_data_clk: qup-spi6-data-clk-state { 3354 /* MISO, MOSI, CLK */ 3355 pins = "gpio48", "gpio49", "gpio50"; 3356 function = "qup1_se6"; 3357 drive-strength = <6>; 3358 bias-disable; 3359 }; 3360 3361 qup_spi8_cs: qup-spi8-cs-state { 3362 pins = "gpio59"; 3363 function = "qup2_se0_l3_mira"; 3364 drive-strength = <6>; 3365 bias-disable; 3366 }; 3367 3368 qup_spi8_data_clk: qup-spi8-data-clk-state { 3369 /* MISO, MOSI, CLK */ 3370 pins = "gpio56", "gpio57", "gpio58"; 3371 function = "qup2_se0_l2_mira"; 3372 drive-strength = <6>; 3373 bias-disable; 3374 }; 3375 3376 qup_spi9_cs: qup-spi9-cs-state { 3377 pins = "gpio63"; 3378 function = "qup2_se1"; 3379 drive-strength = <6>; 3380 bias-disable; 3381 }; 3382 3383 qup_spi9_data_clk: qup-spi9-data-clk-state { 3384 /* MISO, MOSI, CLK */ 3385 pins = "gpio60", "gpio61", "gpio62"; 3386 function = "qup2_se1"; 3387 drive-strength = <6>; 3388 bias-disable; 3389 }; 3390 3391 qup_spi10_cs: qup-spi10-cs-state { 3392 pins = "gpio67"; 3393 function = "qup2_se2"; 3394 drive-strength = <6>; 3395 bias-disable; 3396 }; 3397 3398 qup_spi10_data_clk: qup-spi10-data-clk-state { 3399 /* MISO, MOSI, CLK */ 3400 pins = "gpio64", "gpio65", "gpio66"; 3401 function = "qup2_se2"; 3402 drive-strength = <6>; 3403 bias-disable; 3404 }; 3405 3406 qup_spi11_cs: qup-spi11-cs-state { 3407 pins = "gpio71"; 3408 function = "qup2_se3"; 3409 drive-strength = <6>; 3410 bias-disable; 3411 }; 3412 3413 qup_spi11_data_clk: qup-spi11-data-clk-state { 3414 /* MISO, MOSI, CLK */ 3415 pins = "gpio68", "gpio69", "gpio70"; 3416 function = "qup2_se3"; 3417 drive-strength = <6>; 3418 bias-disable; 3419 }; 3420 3421 qup_spi12_cs: qup-spi12-cs-state { 3422 pins = "gpio119"; 3423 function = "qup2_se4"; 3424 drive-strength = <6>; 3425 bias-disable; 3426 }; 3427 3428 qup_spi12_data_clk: qup-spi12-data-clk-state { 3429 /* MISO, MOSI, CLK */ 3430 pins = "gpio2", "gpio3", "gpio118"; 3431 function = "qup2_se4"; 3432 drive-strength = <6>; 3433 bias-disable; 3434 }; 3435 3436 qup_spi13_cs: qup-spi13-cs-state { 3437 pins = "gpio83"; 3438 function = "qup2_se5"; 3439 drive-strength = <6>; 3440 bias-disable; 3441 }; 3442 3443 qup_spi13_data_clk: qup-spi13-data-clk-state { 3444 /* MISO, MOSI, CLK */ 3445 pins = "gpio80", "gpio81", "gpio82"; 3446 function = "qup2_se5"; 3447 drive-strength = <6>; 3448 bias-disable; 3449 }; 3450 3451 qup_spi15_cs: qup-spi15-cs-state { 3452 pins = "gpio75"; 3453 function = "qup2_se7"; 3454 drive-strength = <6>; 3455 bias-disable; 3456 }; 3457 3458 qup_spi15_data_clk: qup-spi15-data-clk-state { 3459 /* MISO, MOSI, CLK */ 3460 pins = "gpio72", "gpio106", "gpio74"; 3461 function = "qup2_se7"; 3462 drive-strength = <6>; 3463 bias-disable; 3464 }; 3465 3466 qup_uart7_default: qup-uart7-default-state { 3467 /* TX, RX */ 3468 pins = "gpio26", "gpio27"; 3469 function = "qup1_se7"; 3470 drive-strength = <2>; 3471 bias-disable; 3472 }; 3473 3474 sdc2_sleep: sdc2-sleep-state { 3475 clk-pins { 3476 pins = "sdc2_clk"; 3477 bias-disable; 3478 drive-strength = <2>; 3479 }; 3480 3481 cmd-pins { 3482 pins = "sdc2_cmd"; 3483 bias-pull-up; 3484 drive-strength = <2>; 3485 }; 3486 3487 data-pins { 3488 pins = "sdc2_data"; 3489 bias-pull-up; 3490 drive-strength = <2>; 3491 }; 3492 }; 3493 3494 sdc2_default: sdc2-default-state { 3495 clk-pins { 3496 pins = "sdc2_clk"; 3497 bias-disable; 3498 drive-strength = <16>; 3499 }; 3500 3501 cmd-pins { 3502 pins = "sdc2_cmd"; 3503 bias-pull-up; 3504 drive-strength = <10>; 3505 }; 3506 3507 data-pins { 3508 pins = "sdc2_data"; 3509 bias-pull-up; 3510 drive-strength = <10>; 3511 }; 3512 }; 3513 }; 3514 3515 apps_smmu: iommu@15000000 { 3516 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3517 reg = <0 0x15000000 0 0x100000>; 3518 #iommu-cells = <2>; 3519 #global-interrupts = <1>; 3520 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3557 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3558 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3617 }; 3618 3619 intc: interrupt-controller@17100000 { 3620 compatible = "arm,gic-v3"; 3621 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3622 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3623 ranges; 3624 #interrupt-cells = <3>; 3625 interrupt-controller; 3626 #redistributor-regions = <1>; 3627 redistributor-stride = <0 0x40000>; 3628 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3629 #address-cells = <2>; 3630 #size-cells = <2>; 3631 3632 gic_its: msi-controller@17140000 { 3633 compatible = "arm,gic-v3-its"; 3634 reg = <0 0x17140000 0 0x20000>; 3635 msi-controller; 3636 #msi-cells = <1>; 3637 }; 3638 }; 3639 3640 timer@17420000 { 3641 compatible = "arm,armv7-timer-mem"; 3642 reg = <0 0x17420000 0 0x1000>; 3643 ranges = <0 0 0 0x20000000>; 3644 #address-cells = <1>; 3645 #size-cells = <1>; 3646 3647 frame@17421000 { 3648 reg = <0x17421000 0x1000>, 3649 <0x17422000 0x1000>; 3650 frame-number = <0>; 3651 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3653 }; 3654 3655 frame@17423000 { 3656 reg = <0x17423000 0x1000>; 3657 frame-number = <1>; 3658 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3659 status = "disabled"; 3660 }; 3661 3662 frame@17425000 { 3663 reg = <0x17425000 0x1000>; 3664 frame-number = <2>; 3665 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3666 status = "disabled"; 3667 }; 3668 3669 frame@17427000 { 3670 reg = <0x17427000 0x1000>; 3671 frame-number = <3>; 3672 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3673 status = "disabled"; 3674 }; 3675 3676 frame@17429000 { 3677 reg = <0x17429000 0x1000>; 3678 frame-number = <4>; 3679 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3680 status = "disabled"; 3681 }; 3682 3683 frame@1742b000 { 3684 reg = <0x1742b000 0x1000>; 3685 frame-number = <5>; 3686 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3687 status = "disabled"; 3688 }; 3689 3690 frame@1742d000 { 3691 reg = <0x1742d000 0x1000>; 3692 frame-number = <6>; 3693 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3694 status = "disabled"; 3695 }; 3696 }; 3697 3698 apps_rsc: rsc@17a00000 { 3699 label = "apps_rsc"; 3700 compatible = "qcom,rpmh-rsc"; 3701 reg = <0 0x17a00000 0 0x10000>, 3702 <0 0x17a10000 0 0x10000>, 3703 <0 0x17a20000 0 0x10000>, 3704 <0 0x17a30000 0 0x10000>; 3705 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3706 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3709 qcom,tcs-offset = <0xd00>; 3710 qcom,drv-id = <2>; 3711 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3712 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3713 power-domains = <&CLUSTER_PD>; 3714 3715 apps_bcm_voter: bcm-voter { 3716 compatible = "qcom,bcm-voter"; 3717 }; 3718 3719 rpmhcc: clock-controller { 3720 compatible = "qcom,sm8550-rpmh-clk"; 3721 #clock-cells = <1>; 3722 clock-names = "xo"; 3723 clocks = <&xo_board>; 3724 }; 3725 3726 rpmhpd: power-controller { 3727 compatible = "qcom,sm8550-rpmhpd"; 3728 #power-domain-cells = <1>; 3729 operating-points-v2 = <&rpmhpd_opp_table>; 3730 3731 rpmhpd_opp_table: opp-table { 3732 compatible = "operating-points-v2"; 3733 3734 rpmhpd_opp_ret: opp-16 { 3735 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3736 }; 3737 3738 rpmhpd_opp_min_svs: opp-48 { 3739 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3740 }; 3741 3742 rpmhpd_opp_low_svs_d2: opp-52 { 3743 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3744 }; 3745 3746 rpmhpd_opp_low_svs_d1: opp-56 { 3747 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3748 }; 3749 3750 rpmhpd_opp_low_svs_d0: opp-60 { 3751 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3752 }; 3753 3754 rpmhpd_opp_low_svs: opp-64 { 3755 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3756 }; 3757 3758 rpmhpd_opp_low_svs_l1: opp-80 { 3759 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3760 }; 3761 3762 rpmhpd_opp_svs: opp-128 { 3763 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3764 }; 3765 3766 rpmhpd_opp_svs_l0: opp-144 { 3767 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3768 }; 3769 3770 rpmhpd_opp_svs_l1: opp-192 { 3771 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3772 }; 3773 3774 rpmhpd_opp_nom: opp-256 { 3775 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3776 }; 3777 3778 rpmhpd_opp_nom_l1: opp-320 { 3779 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3780 }; 3781 3782 rpmhpd_opp_nom_l2: opp-336 { 3783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3784 }; 3785 3786 rpmhpd_opp_turbo: opp-384 { 3787 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3788 }; 3789 3790 rpmhpd_opp_turbo_l1: opp-416 { 3791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3792 }; 3793 }; 3794 }; 3795 }; 3796 3797 cpufreq_hw: cpufreq@17d91000 { 3798 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3799 reg = <0 0x17d91000 0 0x1000>, 3800 <0 0x17d92000 0 0x1000>, 3801 <0 0x17d93000 0 0x1000>; 3802 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3803 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3804 clock-names = "xo", "alternate"; 3805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3808 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3809 #freq-domain-cells = <1>; 3810 #clock-cells = <1>; 3811 }; 3812 3813 pmu@24091000 { 3814 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3815 reg = <0 0x24091000 0 0x1000>; 3816 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3817 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3818 3819 operating-points-v2 = <&llcc_bwmon_opp_table>; 3820 3821 llcc_bwmon_opp_table: opp-table { 3822 compatible = "operating-points-v2"; 3823 3824 opp-0 { 3825 opp-peak-kBps = <2086000>; 3826 }; 3827 3828 opp-1 { 3829 opp-peak-kBps = <2929000>; 3830 }; 3831 3832 opp-2 { 3833 opp-peak-kBps = <5931000>; 3834 }; 3835 3836 opp-3 { 3837 opp-peak-kBps = <6515000>; 3838 }; 3839 3840 opp-4 { 3841 opp-peak-kBps = <7980000>; 3842 }; 3843 3844 opp-5 { 3845 opp-peak-kBps = <10437000>; 3846 }; 3847 3848 opp-6 { 3849 opp-peak-kBps = <12157000>; 3850 }; 3851 3852 opp-7 { 3853 opp-peak-kBps = <14060000>; 3854 }; 3855 3856 opp-8 { 3857 opp-peak-kBps = <16113000>; 3858 }; 3859 }; 3860 }; 3861 3862 pmu@240b6400 { 3863 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 3864 reg = <0 0x240b6400 0 0x600>; 3865 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3866 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3867 3868 operating-points-v2 = <&cpu_bwmon_opp_table>; 3869 3870 cpu_bwmon_opp_table: opp-table { 3871 compatible = "operating-points-v2"; 3872 3873 opp-0 { 3874 opp-peak-kBps = <4577000>; 3875 }; 3876 3877 opp-1 { 3878 opp-peak-kBps = <7110000>; 3879 }; 3880 3881 opp-2 { 3882 opp-peak-kBps = <9155000>; 3883 }; 3884 3885 opp-3 { 3886 opp-peak-kBps = <12298000>; 3887 }; 3888 3889 opp-4 { 3890 opp-peak-kBps = <14236000>; 3891 }; 3892 3893 opp-5 { 3894 opp-peak-kBps = <16265000>; 3895 }; 3896 }; 3897 }; 3898 3899 gem_noc: interconnect@24100000 { 3900 compatible = "qcom,sm8550-gem-noc"; 3901 reg = <0 0x24100000 0 0xbb800>; 3902 #interconnect-cells = <2>; 3903 qcom,bcm-voters = <&apps_bcm_voter>; 3904 }; 3905 3906 system-cache-controller@25000000 { 3907 compatible = "qcom,sm8550-llcc"; 3908 reg = <0 0x25000000 0 0x200000>, 3909 <0 0x25200000 0 0x200000>, 3910 <0 0x25400000 0 0x200000>, 3911 <0 0x25600000 0 0x200000>, 3912 <0 0x25800000 0 0x200000>; 3913 reg-names = "llcc0_base", 3914 "llcc1_base", 3915 "llcc2_base", 3916 "llcc3_base", 3917 "llcc_broadcast_base"; 3918 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3919 }; 3920 3921 remoteproc_adsp: remoteproc@30000000 { 3922 compatible = "qcom,sm8550-adsp-pas"; 3923 reg = <0x0 0x30000000 0x0 0x100>; 3924 3925 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3926 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3927 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3928 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3929 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3930 interrupt-names = "wdog", "fatal", "ready", 3931 "handover", "stop-ack"; 3932 3933 clocks = <&rpmhcc RPMH_CXO_CLK>; 3934 clock-names = "xo"; 3935 3936 power-domains = <&rpmhpd SM8550_LCX>, 3937 <&rpmhpd SM8550_LMX>; 3938 power-domain-names = "lcx", "lmx"; 3939 3940 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3941 3942 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3943 3944 qcom,qmp = <&aoss_qmp>; 3945 3946 qcom,smem-states = <&smp2p_adsp_out 0>; 3947 qcom,smem-state-names = "stop"; 3948 3949 status = "disabled"; 3950 3951 remoteproc_adsp_glink: glink-edge { 3952 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3953 IPCC_MPROC_SIGNAL_GLINK_QMP 3954 IRQ_TYPE_EDGE_RISING>; 3955 mboxes = <&ipcc IPCC_CLIENT_LPASS 3956 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3957 3958 label = "lpass"; 3959 qcom,remote-pid = <2>; 3960 3961 fastrpc { 3962 compatible = "qcom,fastrpc"; 3963 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3964 label = "adsp"; 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 3968 compute-cb@3 { 3969 compatible = "qcom,fastrpc-compute-cb"; 3970 reg = <3>; 3971 iommus = <&apps_smmu 0x1003 0x80>, 3972 <&apps_smmu 0x1063 0x0>; 3973 }; 3974 3975 compute-cb@4 { 3976 compatible = "qcom,fastrpc-compute-cb"; 3977 reg = <4>; 3978 iommus = <&apps_smmu 0x1004 0x80>, 3979 <&apps_smmu 0x1064 0x0>; 3980 }; 3981 3982 compute-cb@5 { 3983 compatible = "qcom,fastrpc-compute-cb"; 3984 reg = <5>; 3985 iommus = <&apps_smmu 0x1005 0x80>, 3986 <&apps_smmu 0x1065 0x0>; 3987 }; 3988 3989 compute-cb@6 { 3990 compatible = "qcom,fastrpc-compute-cb"; 3991 reg = <6>; 3992 iommus = <&apps_smmu 0x1006 0x80>, 3993 <&apps_smmu 0x1066 0x0>; 3994 }; 3995 3996 compute-cb@7 { 3997 compatible = "qcom,fastrpc-compute-cb"; 3998 reg = <7>; 3999 iommus = <&apps_smmu 0x1007 0x80>, 4000 <&apps_smmu 0x1067 0x0>; 4001 }; 4002 }; 4003 4004 gpr { 4005 compatible = "qcom,gpr"; 4006 qcom,glink-channels = "adsp_apps"; 4007 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4008 qcom,intents = <512 20>; 4009 #address-cells = <1>; 4010 #size-cells = <0>; 4011 4012 q6apm: service@1 { 4013 compatible = "qcom,q6apm"; 4014 reg = <GPR_APM_MODULE_IID>; 4015 #sound-dai-cells = <0>; 4016 qcom,protection-domain = "avs/audio", 4017 "msm/adsp/audio_pd"; 4018 4019 q6apmdai: dais { 4020 compatible = "qcom,q6apm-dais"; 4021 iommus = <&apps_smmu 0x1001 0x80>, 4022 <&apps_smmu 0x1061 0x0>; 4023 }; 4024 4025 q6apmbedai: bedais { 4026 compatible = "qcom,q6apm-lpass-dais"; 4027 #sound-dai-cells = <1>; 4028 }; 4029 }; 4030 4031 q6prm: service@2 { 4032 compatible = "qcom,q6prm"; 4033 reg = <GPR_PRM_MODULE_IID>; 4034 qcom,protection-domain = "avs/audio", 4035 "msm/adsp/audio_pd"; 4036 4037 q6prmcc: clock-controller { 4038 compatible = "qcom,q6prm-lpass-clocks"; 4039 #clock-cells = <2>; 4040 }; 4041 }; 4042 }; 4043 }; 4044 }; 4045 4046 nsp_noc: interconnect@320c0000 { 4047 compatible = "qcom,sm8550-nsp-noc"; 4048 reg = <0 0x320c0000 0 0xe080>; 4049 #interconnect-cells = <2>; 4050 qcom,bcm-voters = <&apps_bcm_voter>; 4051 }; 4052 4053 remoteproc_cdsp: remoteproc@32300000 { 4054 compatible = "qcom,sm8550-cdsp-pas"; 4055 reg = <0x0 0x32300000 0x0 0x1400000>; 4056 4057 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4058 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4059 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4060 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4061 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4062 interrupt-names = "wdog", "fatal", "ready", 4063 "handover", "stop-ack"; 4064 4065 clocks = <&rpmhcc RPMH_CXO_CLK>; 4066 clock-names = "xo"; 4067 4068 power-domains = <&rpmhpd SM8550_CX>, 4069 <&rpmhpd SM8550_MXC>, 4070 <&rpmhpd SM8550_NSP>; 4071 power-domain-names = "cx", "mxc", "nsp"; 4072 4073 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4074 4075 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4076 4077 qcom,qmp = <&aoss_qmp>; 4078 4079 qcom,smem-states = <&smp2p_cdsp_out 0>; 4080 qcom,smem-state-names = "stop"; 4081 4082 status = "disabled"; 4083 4084 glink-edge { 4085 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4086 IPCC_MPROC_SIGNAL_GLINK_QMP 4087 IRQ_TYPE_EDGE_RISING>; 4088 mboxes = <&ipcc IPCC_CLIENT_CDSP 4089 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4090 4091 label = "cdsp"; 4092 qcom,remote-pid = <5>; 4093 4094 fastrpc { 4095 compatible = "qcom,fastrpc"; 4096 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4097 label = "cdsp"; 4098 #address-cells = <1>; 4099 #size-cells = <0>; 4100 4101 compute-cb@1 { 4102 compatible = "qcom,fastrpc-compute-cb"; 4103 reg = <1>; 4104 iommus = <&apps_smmu 0x1961 0x0>, 4105 <&apps_smmu 0x0c01 0x20>, 4106 <&apps_smmu 0x19c1 0x10>; 4107 }; 4108 4109 compute-cb@2 { 4110 compatible = "qcom,fastrpc-compute-cb"; 4111 reg = <2>; 4112 iommus = <&apps_smmu 0x1962 0x0>, 4113 <&apps_smmu 0x0c02 0x20>, 4114 <&apps_smmu 0x19c2 0x10>; 4115 }; 4116 4117 compute-cb@3 { 4118 compatible = "qcom,fastrpc-compute-cb"; 4119 reg = <3>; 4120 iommus = <&apps_smmu 0x1963 0x0>, 4121 <&apps_smmu 0x0c03 0x20>, 4122 <&apps_smmu 0x19c3 0x10>; 4123 }; 4124 4125 compute-cb@4 { 4126 compatible = "qcom,fastrpc-compute-cb"; 4127 reg = <4>; 4128 iommus = <&apps_smmu 0x1964 0x0>, 4129 <&apps_smmu 0x0c04 0x20>, 4130 <&apps_smmu 0x19c4 0x10>; 4131 }; 4132 4133 compute-cb@5 { 4134 compatible = "qcom,fastrpc-compute-cb"; 4135 reg = <5>; 4136 iommus = <&apps_smmu 0x1965 0x0>, 4137 <&apps_smmu 0x0c05 0x20>, 4138 <&apps_smmu 0x19c5 0x10>; 4139 }; 4140 4141 compute-cb@6 { 4142 compatible = "qcom,fastrpc-compute-cb"; 4143 reg = <6>; 4144 iommus = <&apps_smmu 0x1966 0x0>, 4145 <&apps_smmu 0x0c06 0x20>, 4146 <&apps_smmu 0x19c6 0x10>; 4147 }; 4148 4149 compute-cb@7 { 4150 compatible = "qcom,fastrpc-compute-cb"; 4151 reg = <7>; 4152 iommus = <&apps_smmu 0x1967 0x0>, 4153 <&apps_smmu 0x0c07 0x20>, 4154 <&apps_smmu 0x19c7 0x10>; 4155 }; 4156 4157 compute-cb@8 { 4158 compatible = "qcom,fastrpc-compute-cb"; 4159 reg = <8>; 4160 iommus = <&apps_smmu 0x1968 0x0>, 4161 <&apps_smmu 0x0c08 0x20>, 4162 <&apps_smmu 0x19c8 0x10>; 4163 }; 4164 4165 /* note: secure cb9 in downstream */ 4166 }; 4167 }; 4168 }; 4169 }; 4170 4171 thermal-zones { 4172 aoss0-thermal { 4173 polling-delay-passive = <0>; 4174 polling-delay = <0>; 4175 thermal-sensors = <&tsens0 0>; 4176 4177 trips { 4178 thermal-engine-config { 4179 temperature = <125000>; 4180 hysteresis = <1000>; 4181 type = "passive"; 4182 }; 4183 4184 reset-mon-config { 4185 temperature = <115000>; 4186 hysteresis = <5000>; 4187 type = "passive"; 4188 }; 4189 }; 4190 }; 4191 4192 cpuss0-thermal { 4193 polling-delay-passive = <0>; 4194 polling-delay = <0>; 4195 thermal-sensors = <&tsens0 1>; 4196 4197 trips { 4198 thermal-engine-config { 4199 temperature = <125000>; 4200 hysteresis = <1000>; 4201 type = "passive"; 4202 }; 4203 4204 reset-mon-config { 4205 temperature = <115000>; 4206 hysteresis = <5000>; 4207 type = "passive"; 4208 }; 4209 }; 4210 }; 4211 4212 cpuss1-thermal { 4213 polling-delay-passive = <0>; 4214 polling-delay = <0>; 4215 thermal-sensors = <&tsens0 2>; 4216 4217 trips { 4218 thermal-engine-config { 4219 temperature = <125000>; 4220 hysteresis = <1000>; 4221 type = "passive"; 4222 }; 4223 4224 reset-mon-config { 4225 temperature = <115000>; 4226 hysteresis = <5000>; 4227 type = "passive"; 4228 }; 4229 }; 4230 }; 4231 4232 cpuss2-thermal { 4233 polling-delay-passive = <0>; 4234 polling-delay = <0>; 4235 thermal-sensors = <&tsens0 3>; 4236 4237 trips { 4238 thermal-engine-config { 4239 temperature = <125000>; 4240 hysteresis = <1000>; 4241 type = "passive"; 4242 }; 4243 4244 reset-mon-config { 4245 temperature = <115000>; 4246 hysteresis = <5000>; 4247 type = "passive"; 4248 }; 4249 }; 4250 }; 4251 4252 cpuss3-thermal { 4253 polling-delay-passive = <0>; 4254 polling-delay = <0>; 4255 thermal-sensors = <&tsens0 4>; 4256 4257 trips { 4258 thermal-engine-config { 4259 temperature = <125000>; 4260 hysteresis = <1000>; 4261 type = "passive"; 4262 }; 4263 4264 reset-mon-config { 4265 temperature = <115000>; 4266 hysteresis = <5000>; 4267 type = "passive"; 4268 }; 4269 }; 4270 }; 4271 4272 cpu3-top-thermal { 4273 polling-delay-passive = <0>; 4274 polling-delay = <0>; 4275 thermal-sensors = <&tsens0 5>; 4276 4277 trips { 4278 cpu3_top_alert0: trip-point0 { 4279 temperature = <90000>; 4280 hysteresis = <2000>; 4281 type = "passive"; 4282 }; 4283 4284 cpu3_top_alert1: trip-point1 { 4285 temperature = <95000>; 4286 hysteresis = <2000>; 4287 type = "passive"; 4288 }; 4289 4290 cpu3_top_crit: cpu-critical { 4291 temperature = <110000>; 4292 hysteresis = <1000>; 4293 type = "critical"; 4294 }; 4295 }; 4296 }; 4297 4298 cpu3-bottom-thermal { 4299 polling-delay-passive = <0>; 4300 polling-delay = <0>; 4301 thermal-sensors = <&tsens0 6>; 4302 4303 trips { 4304 cpu3_bottom_alert0: trip-point0 { 4305 temperature = <90000>; 4306 hysteresis = <2000>; 4307 type = "passive"; 4308 }; 4309 4310 cpu3_bottom_alert1: trip-point1 { 4311 temperature = <95000>; 4312 hysteresis = <2000>; 4313 type = "passive"; 4314 }; 4315 4316 cpu3_bottom_crit: cpu-critical { 4317 temperature = <110000>; 4318 hysteresis = <1000>; 4319 type = "critical"; 4320 }; 4321 }; 4322 }; 4323 4324 cpu4-top-thermal { 4325 polling-delay-passive = <0>; 4326 polling-delay = <0>; 4327 thermal-sensors = <&tsens0 7>; 4328 4329 trips { 4330 cpu4_top_alert0: trip-point0 { 4331 temperature = <90000>; 4332 hysteresis = <2000>; 4333 type = "passive"; 4334 }; 4335 4336 cpu4_top_alert1: trip-point1 { 4337 temperature = <95000>; 4338 hysteresis = <2000>; 4339 type = "passive"; 4340 }; 4341 4342 cpu4_top_crit: cpu-critical { 4343 temperature = <110000>; 4344 hysteresis = <1000>; 4345 type = "critical"; 4346 }; 4347 }; 4348 }; 4349 4350 cpu4-bottom-thermal { 4351 polling-delay-passive = <0>; 4352 polling-delay = <0>; 4353 thermal-sensors = <&tsens0 8>; 4354 4355 trips { 4356 cpu4_bottom_alert0: trip-point0 { 4357 temperature = <90000>; 4358 hysteresis = <2000>; 4359 type = "passive"; 4360 }; 4361 4362 cpu4_bottom_alert1: trip-point1 { 4363 temperature = <95000>; 4364 hysteresis = <2000>; 4365 type = "passive"; 4366 }; 4367 4368 cpu4_bottom_crit: cpu-critical { 4369 temperature = <110000>; 4370 hysteresis = <1000>; 4371 type = "critical"; 4372 }; 4373 }; 4374 }; 4375 4376 cpu5-top-thermal { 4377 polling-delay-passive = <0>; 4378 polling-delay = <0>; 4379 thermal-sensors = <&tsens0 9>; 4380 4381 trips { 4382 cpu5_top_alert0: trip-point0 { 4383 temperature = <90000>; 4384 hysteresis = <2000>; 4385 type = "passive"; 4386 }; 4387 4388 cpu5_top_alert1: trip-point1 { 4389 temperature = <95000>; 4390 hysteresis = <2000>; 4391 type = "passive"; 4392 }; 4393 4394 cpu5_top_crit: cpu-critical { 4395 temperature = <110000>; 4396 hysteresis = <1000>; 4397 type = "critical"; 4398 }; 4399 }; 4400 }; 4401 4402 cpu5-bottom-thermal { 4403 polling-delay-passive = <0>; 4404 polling-delay = <0>; 4405 thermal-sensors = <&tsens0 10>; 4406 4407 trips { 4408 cpu5_bottom_alert0: trip-point0 { 4409 temperature = <90000>; 4410 hysteresis = <2000>; 4411 type = "passive"; 4412 }; 4413 4414 cpu5_bottom_alert1: trip-point1 { 4415 temperature = <95000>; 4416 hysteresis = <2000>; 4417 type = "passive"; 4418 }; 4419 4420 cpu5_bottom_crit: cpu-critical { 4421 temperature = <110000>; 4422 hysteresis = <1000>; 4423 type = "critical"; 4424 }; 4425 }; 4426 }; 4427 4428 cpu6-top-thermal { 4429 polling-delay-passive = <0>; 4430 polling-delay = <0>; 4431 thermal-sensors = <&tsens0 11>; 4432 4433 trips { 4434 cpu6_top_alert0: trip-point0 { 4435 temperature = <90000>; 4436 hysteresis = <2000>; 4437 type = "passive"; 4438 }; 4439 4440 cpu6_top_alert1: trip-point1 { 4441 temperature = <95000>; 4442 hysteresis = <2000>; 4443 type = "passive"; 4444 }; 4445 4446 cpu6_top_crit: cpu-critical { 4447 temperature = <110000>; 4448 hysteresis = <1000>; 4449 type = "critical"; 4450 }; 4451 }; 4452 }; 4453 4454 cpu6-bottom-thermal { 4455 polling-delay-passive = <0>; 4456 polling-delay = <0>; 4457 thermal-sensors = <&tsens0 12>; 4458 4459 trips { 4460 cpu6_bottom_alert0: trip-point0 { 4461 temperature = <90000>; 4462 hysteresis = <2000>; 4463 type = "passive"; 4464 }; 4465 4466 cpu6_bottom_alert1: trip-point1 { 4467 temperature = <95000>; 4468 hysteresis = <2000>; 4469 type = "passive"; 4470 }; 4471 4472 cpu6_bottom_crit: cpu-critical { 4473 temperature = <110000>; 4474 hysteresis = <1000>; 4475 type = "critical"; 4476 }; 4477 }; 4478 }; 4479 4480 cpu7-top-thermal { 4481 polling-delay-passive = <0>; 4482 polling-delay = <0>; 4483 thermal-sensors = <&tsens0 13>; 4484 4485 trips { 4486 cpu7_top_alert0: trip-point0 { 4487 temperature = <90000>; 4488 hysteresis = <2000>; 4489 type = "passive"; 4490 }; 4491 4492 cpu7_top_alert1: trip-point1 { 4493 temperature = <95000>; 4494 hysteresis = <2000>; 4495 type = "passive"; 4496 }; 4497 4498 cpu7_top_crit: cpu-critical { 4499 temperature = <110000>; 4500 hysteresis = <1000>; 4501 type = "critical"; 4502 }; 4503 }; 4504 }; 4505 4506 cpu7-middle-thermal { 4507 polling-delay-passive = <0>; 4508 polling-delay = <0>; 4509 thermal-sensors = <&tsens0 14>; 4510 4511 trips { 4512 cpu7_middle_alert0: trip-point0 { 4513 temperature = <90000>; 4514 hysteresis = <2000>; 4515 type = "passive"; 4516 }; 4517 4518 cpu7_middle_alert1: trip-point1 { 4519 temperature = <95000>; 4520 hysteresis = <2000>; 4521 type = "passive"; 4522 }; 4523 4524 cpu7_middle_crit: cpu-critical { 4525 temperature = <110000>; 4526 hysteresis = <1000>; 4527 type = "critical"; 4528 }; 4529 }; 4530 }; 4531 4532 cpu7-bottom-thermal { 4533 polling-delay-passive = <0>; 4534 polling-delay = <0>; 4535 thermal-sensors = <&tsens0 15>; 4536 4537 trips { 4538 cpu7_bottom_alert0: trip-point0 { 4539 temperature = <90000>; 4540 hysteresis = <2000>; 4541 type = "passive"; 4542 }; 4543 4544 cpu7_bottom_alert1: trip-point1 { 4545 temperature = <95000>; 4546 hysteresis = <2000>; 4547 type = "passive"; 4548 }; 4549 4550 cpu7_bottom_crit: cpu-critical { 4551 temperature = <110000>; 4552 hysteresis = <1000>; 4553 type = "critical"; 4554 }; 4555 }; 4556 }; 4557 4558 aoss1-thermal { 4559 polling-delay-passive = <0>; 4560 polling-delay = <0>; 4561 thermal-sensors = <&tsens1 0>; 4562 4563 trips { 4564 thermal-engine-config { 4565 temperature = <125000>; 4566 hysteresis = <1000>; 4567 type = "passive"; 4568 }; 4569 4570 reset-mon-config { 4571 temperature = <115000>; 4572 hysteresis = <5000>; 4573 type = "passive"; 4574 }; 4575 }; 4576 }; 4577 4578 cpu0-thermal { 4579 polling-delay-passive = <0>; 4580 polling-delay = <0>; 4581 thermal-sensors = <&tsens1 1>; 4582 4583 trips { 4584 cpu0_alert0: trip-point0 { 4585 temperature = <90000>; 4586 hysteresis = <2000>; 4587 type = "passive"; 4588 }; 4589 4590 cpu0_alert1: trip-point1 { 4591 temperature = <95000>; 4592 hysteresis = <2000>; 4593 type = "passive"; 4594 }; 4595 4596 cpu0_crit: cpu-critical { 4597 temperature = <110000>; 4598 hysteresis = <1000>; 4599 type = "critical"; 4600 }; 4601 }; 4602 }; 4603 4604 cpu1-thermal { 4605 polling-delay-passive = <0>; 4606 polling-delay = <0>; 4607 thermal-sensors = <&tsens1 2>; 4608 4609 trips { 4610 cpu1_alert0: trip-point0 { 4611 temperature = <90000>; 4612 hysteresis = <2000>; 4613 type = "passive"; 4614 }; 4615 4616 cpu1_alert1: trip-point1 { 4617 temperature = <95000>; 4618 hysteresis = <2000>; 4619 type = "passive"; 4620 }; 4621 4622 cpu1_crit: cpu-critical { 4623 temperature = <110000>; 4624 hysteresis = <1000>; 4625 type = "critical"; 4626 }; 4627 }; 4628 }; 4629 4630 cpu2-thermal { 4631 polling-delay-passive = <0>; 4632 polling-delay = <0>; 4633 thermal-sensors = <&tsens1 3>; 4634 4635 trips { 4636 cpu2_alert0: trip-point0 { 4637 temperature = <90000>; 4638 hysteresis = <2000>; 4639 type = "passive"; 4640 }; 4641 4642 cpu2_alert1: trip-point1 { 4643 temperature = <95000>; 4644 hysteresis = <2000>; 4645 type = "passive"; 4646 }; 4647 4648 cpu2_crit: cpu-critical { 4649 temperature = <110000>; 4650 hysteresis = <1000>; 4651 type = "critical"; 4652 }; 4653 }; 4654 }; 4655 4656 cdsp0-thermal { 4657 polling-delay-passive = <10>; 4658 polling-delay = <0>; 4659 thermal-sensors = <&tsens2 4>; 4660 4661 trips { 4662 thermal-engine-config { 4663 temperature = <125000>; 4664 hysteresis = <1000>; 4665 type = "passive"; 4666 }; 4667 4668 thermal-hal-config { 4669 temperature = <125000>; 4670 hysteresis = <1000>; 4671 type = "passive"; 4672 }; 4673 4674 reset-mon-config { 4675 temperature = <115000>; 4676 hysteresis = <5000>; 4677 type = "passive"; 4678 }; 4679 4680 cdsp0_junction_config: junction-config { 4681 temperature = <95000>; 4682 hysteresis = <5000>; 4683 type = "passive"; 4684 }; 4685 }; 4686 }; 4687 4688 cdsp1-thermal { 4689 polling-delay-passive = <10>; 4690 polling-delay = <0>; 4691 thermal-sensors = <&tsens2 5>; 4692 4693 trips { 4694 thermal-engine-config { 4695 temperature = <125000>; 4696 hysteresis = <1000>; 4697 type = "passive"; 4698 }; 4699 4700 thermal-hal-config { 4701 temperature = <125000>; 4702 hysteresis = <1000>; 4703 type = "passive"; 4704 }; 4705 4706 reset-mon-config { 4707 temperature = <115000>; 4708 hysteresis = <5000>; 4709 type = "passive"; 4710 }; 4711 4712 cdsp1_junction_config: junction-config { 4713 temperature = <95000>; 4714 hysteresis = <5000>; 4715 type = "passive"; 4716 }; 4717 }; 4718 }; 4719 4720 cdsp2-thermal { 4721 polling-delay-passive = <10>; 4722 polling-delay = <0>; 4723 thermal-sensors = <&tsens2 6>; 4724 4725 trips { 4726 thermal-engine-config { 4727 temperature = <125000>; 4728 hysteresis = <1000>; 4729 type = "passive"; 4730 }; 4731 4732 thermal-hal-config { 4733 temperature = <125000>; 4734 hysteresis = <1000>; 4735 type = "passive"; 4736 }; 4737 4738 reset-mon-config { 4739 temperature = <115000>; 4740 hysteresis = <5000>; 4741 type = "passive"; 4742 }; 4743 4744 cdsp2_junction_config: junction-config { 4745 temperature = <95000>; 4746 hysteresis = <5000>; 4747 type = "passive"; 4748 }; 4749 }; 4750 }; 4751 4752 cdsp3-thermal { 4753 polling-delay-passive = <10>; 4754 polling-delay = <0>; 4755 thermal-sensors = <&tsens2 7>; 4756 4757 trips { 4758 thermal-engine-config { 4759 temperature = <125000>; 4760 hysteresis = <1000>; 4761 type = "passive"; 4762 }; 4763 4764 thermal-hal-config { 4765 temperature = <125000>; 4766 hysteresis = <1000>; 4767 type = "passive"; 4768 }; 4769 4770 reset-mon-config { 4771 temperature = <115000>; 4772 hysteresis = <5000>; 4773 type = "passive"; 4774 }; 4775 4776 cdsp3_junction_config: junction-config { 4777 temperature = <95000>; 4778 hysteresis = <5000>; 4779 type = "passive"; 4780 }; 4781 }; 4782 }; 4783 4784 video-thermal { 4785 polling-delay-passive = <0>; 4786 polling-delay = <0>; 4787 thermal-sensors = <&tsens1 8>; 4788 4789 trips { 4790 thermal-engine-config { 4791 temperature = <125000>; 4792 hysteresis = <1000>; 4793 type = "passive"; 4794 }; 4795 4796 reset-mon-config { 4797 temperature = <115000>; 4798 hysteresis = <5000>; 4799 type = "passive"; 4800 }; 4801 }; 4802 }; 4803 4804 mem-thermal { 4805 polling-delay-passive = <10>; 4806 polling-delay = <0>; 4807 thermal-sensors = <&tsens1 9>; 4808 4809 trips { 4810 thermal-engine-config { 4811 temperature = <125000>; 4812 hysteresis = <1000>; 4813 type = "passive"; 4814 }; 4815 4816 ddr_config0: ddr0-config { 4817 temperature = <90000>; 4818 hysteresis = <5000>; 4819 type = "passive"; 4820 }; 4821 4822 reset-mon-config { 4823 temperature = <115000>; 4824 hysteresis = <5000>; 4825 type = "passive"; 4826 }; 4827 }; 4828 }; 4829 4830 modem0-thermal { 4831 polling-delay-passive = <0>; 4832 polling-delay = <0>; 4833 thermal-sensors = <&tsens1 10>; 4834 4835 trips { 4836 thermal-engine-config { 4837 temperature = <125000>; 4838 hysteresis = <1000>; 4839 type = "passive"; 4840 }; 4841 4842 mdmss0_config0: mdmss0-config0 { 4843 temperature = <102000>; 4844 hysteresis = <3000>; 4845 type = "passive"; 4846 }; 4847 4848 mdmss0_config1: mdmss0-config1 { 4849 temperature = <105000>; 4850 hysteresis = <3000>; 4851 type = "passive"; 4852 }; 4853 4854 reset-mon-config { 4855 temperature = <115000>; 4856 hysteresis = <5000>; 4857 type = "passive"; 4858 }; 4859 }; 4860 }; 4861 4862 modem1-thermal { 4863 polling-delay-passive = <0>; 4864 polling-delay = <0>; 4865 thermal-sensors = <&tsens1 11>; 4866 4867 trips { 4868 thermal-engine-config { 4869 temperature = <125000>; 4870 hysteresis = <1000>; 4871 type = "passive"; 4872 }; 4873 4874 mdmss1_config0: mdmss1-config0 { 4875 temperature = <102000>; 4876 hysteresis = <3000>; 4877 type = "passive"; 4878 }; 4879 4880 mdmss1_config1: mdmss1-config1 { 4881 temperature = <105000>; 4882 hysteresis = <3000>; 4883 type = "passive"; 4884 }; 4885 4886 reset-mon-config { 4887 temperature = <115000>; 4888 hysteresis = <5000>; 4889 type = "passive"; 4890 }; 4891 }; 4892 }; 4893 4894 modem2-thermal { 4895 polling-delay-passive = <0>; 4896 polling-delay = <0>; 4897 thermal-sensors = <&tsens1 12>; 4898 4899 trips { 4900 thermal-engine-config { 4901 temperature = <125000>; 4902 hysteresis = <1000>; 4903 type = "passive"; 4904 }; 4905 4906 mdmss2_config0: mdmss2-config0 { 4907 temperature = <102000>; 4908 hysteresis = <3000>; 4909 type = "passive"; 4910 }; 4911 4912 mdmss2_config1: mdmss2-config1 { 4913 temperature = <105000>; 4914 hysteresis = <3000>; 4915 type = "passive"; 4916 }; 4917 4918 reset-mon-config { 4919 temperature = <115000>; 4920 hysteresis = <5000>; 4921 type = "passive"; 4922 }; 4923 }; 4924 }; 4925 4926 modem3-thermal { 4927 polling-delay-passive = <0>; 4928 polling-delay = <0>; 4929 thermal-sensors = <&tsens1 13>; 4930 4931 trips { 4932 thermal-engine-config { 4933 temperature = <125000>; 4934 hysteresis = <1000>; 4935 type = "passive"; 4936 }; 4937 4938 mdmss3_config0: mdmss3-config0 { 4939 temperature = <102000>; 4940 hysteresis = <3000>; 4941 type = "passive"; 4942 }; 4943 4944 mdmss3_config1: mdmss3-config1 { 4945 temperature = <105000>; 4946 hysteresis = <3000>; 4947 type = "passive"; 4948 }; 4949 4950 reset-mon-config { 4951 temperature = <115000>; 4952 hysteresis = <5000>; 4953 type = "passive"; 4954 }; 4955 }; 4956 }; 4957 4958 camera0-thermal { 4959 polling-delay-passive = <0>; 4960 polling-delay = <0>; 4961 thermal-sensors = <&tsens1 14>; 4962 4963 trips { 4964 thermal-engine-config { 4965 temperature = <125000>; 4966 hysteresis = <1000>; 4967 type = "passive"; 4968 }; 4969 4970 reset-mon-config { 4971 temperature = <115000>; 4972 hysteresis = <5000>; 4973 type = "passive"; 4974 }; 4975 }; 4976 }; 4977 4978 camera1-thermal { 4979 polling-delay-passive = <0>; 4980 polling-delay = <0>; 4981 thermal-sensors = <&tsens1 15>; 4982 4983 trips { 4984 thermal-engine-config { 4985 temperature = <125000>; 4986 hysteresis = <1000>; 4987 type = "passive"; 4988 }; 4989 4990 reset-mon-config { 4991 temperature = <115000>; 4992 hysteresis = <5000>; 4993 type = "passive"; 4994 }; 4995 }; 4996 }; 4997 4998 aoss2-thermal { 4999 polling-delay-passive = <0>; 5000 polling-delay = <0>; 5001 thermal-sensors = <&tsens2 0>; 5002 5003 trips { 5004 thermal-engine-config { 5005 temperature = <125000>; 5006 hysteresis = <1000>; 5007 type = "passive"; 5008 }; 5009 5010 reset-mon-config { 5011 temperature = <115000>; 5012 hysteresis = <5000>; 5013 type = "passive"; 5014 }; 5015 }; 5016 }; 5017 5018 gpuss-0-thermal { 5019 polling-delay-passive = <10>; 5020 polling-delay = <0>; 5021 thermal-sensors = <&tsens2 1>; 5022 5023 trips { 5024 thermal-engine-config { 5025 temperature = <125000>; 5026 hysteresis = <1000>; 5027 type = "passive"; 5028 }; 5029 5030 thermal-hal-config { 5031 temperature = <125000>; 5032 hysteresis = <1000>; 5033 type = "passive"; 5034 }; 5035 5036 reset-mon-config { 5037 temperature = <115000>; 5038 hysteresis = <5000>; 5039 type = "passive"; 5040 }; 5041 5042 gpu0_junction_config: junction-config { 5043 temperature = <95000>; 5044 hysteresis = <5000>; 5045 type = "passive"; 5046 }; 5047 }; 5048 }; 5049 5050 gpuss-1-thermal { 5051 polling-delay-passive = <10>; 5052 polling-delay = <0>; 5053 thermal-sensors = <&tsens2 2>; 5054 5055 trips { 5056 thermal-engine-config { 5057 temperature = <125000>; 5058 hysteresis = <1000>; 5059 type = "passive"; 5060 }; 5061 5062 thermal-hal-config { 5063 temperature = <125000>; 5064 hysteresis = <1000>; 5065 type = "passive"; 5066 }; 5067 5068 reset-mon-config { 5069 temperature = <115000>; 5070 hysteresis = <5000>; 5071 type = "passive"; 5072 }; 5073 5074 gpu1_junction_config: junction-config { 5075 temperature = <95000>; 5076 hysteresis = <5000>; 5077 type = "passive"; 5078 }; 5079 }; 5080 }; 5081 5082 gpuss-2-thermal { 5083 polling-delay-passive = <10>; 5084 polling-delay = <0>; 5085 thermal-sensors = <&tsens2 3>; 5086 5087 trips { 5088 thermal-engine-config { 5089 temperature = <125000>; 5090 hysteresis = <1000>; 5091 type = "passive"; 5092 }; 5093 5094 thermal-hal-config { 5095 temperature = <125000>; 5096 hysteresis = <1000>; 5097 type = "passive"; 5098 }; 5099 5100 reset-mon-config { 5101 temperature = <115000>; 5102 hysteresis = <5000>; 5103 type = "passive"; 5104 }; 5105 5106 gpu2_junction_config: junction-config { 5107 temperature = <95000>; 5108 hysteresis = <5000>; 5109 type = "passive"; 5110 }; 5111 }; 5112 }; 5113 5114 gpuss-3-thermal { 5115 polling-delay-passive = <10>; 5116 polling-delay = <0>; 5117 thermal-sensors = <&tsens2 4>; 5118 5119 trips { 5120 thermal-engine-config { 5121 temperature = <125000>; 5122 hysteresis = <1000>; 5123 type = "passive"; 5124 }; 5125 5126 thermal-hal-config { 5127 temperature = <125000>; 5128 hysteresis = <1000>; 5129 type = "passive"; 5130 }; 5131 5132 reset-mon-config { 5133 temperature = <115000>; 5134 hysteresis = <5000>; 5135 type = "passive"; 5136 }; 5137 5138 gpu3_junction_config: junction-config { 5139 temperature = <95000>; 5140 hysteresis = <5000>; 5141 type = "passive"; 5142 }; 5143 }; 5144 }; 5145 5146 gpuss-4-thermal { 5147 polling-delay-passive = <10>; 5148 polling-delay = <0>; 5149 thermal-sensors = <&tsens2 5>; 5150 5151 trips { 5152 thermal-engine-config { 5153 temperature = <125000>; 5154 hysteresis = <1000>; 5155 type = "passive"; 5156 }; 5157 5158 thermal-hal-config { 5159 temperature = <125000>; 5160 hysteresis = <1000>; 5161 type = "passive"; 5162 }; 5163 5164 reset-mon-config { 5165 temperature = <115000>; 5166 hysteresis = <5000>; 5167 type = "passive"; 5168 }; 5169 5170 gpu4_junction_config: junction-config { 5171 temperature = <95000>; 5172 hysteresis = <5000>; 5173 type = "passive"; 5174 }; 5175 }; 5176 }; 5177 5178 gpuss-5-thermal { 5179 polling-delay-passive = <10>; 5180 polling-delay = <0>; 5181 thermal-sensors = <&tsens2 6>; 5182 5183 trips { 5184 thermal-engine-config { 5185 temperature = <125000>; 5186 hysteresis = <1000>; 5187 type = "passive"; 5188 }; 5189 5190 thermal-hal-config { 5191 temperature = <125000>; 5192 hysteresis = <1000>; 5193 type = "passive"; 5194 }; 5195 5196 reset-mon-config { 5197 temperature = <115000>; 5198 hysteresis = <5000>; 5199 type = "passive"; 5200 }; 5201 5202 gpu5_junction_config: junction-config { 5203 temperature = <95000>; 5204 hysteresis = <5000>; 5205 type = "passive"; 5206 }; 5207 }; 5208 }; 5209 5210 gpuss-6-thermal { 5211 polling-delay-passive = <10>; 5212 polling-delay = <0>; 5213 thermal-sensors = <&tsens2 7>; 5214 5215 trips { 5216 thermal-engine-config { 5217 temperature = <125000>; 5218 hysteresis = <1000>; 5219 type = "passive"; 5220 }; 5221 5222 thermal-hal-config { 5223 temperature = <125000>; 5224 hysteresis = <1000>; 5225 type = "passive"; 5226 }; 5227 5228 reset-mon-config { 5229 temperature = <115000>; 5230 hysteresis = <5000>; 5231 type = "passive"; 5232 }; 5233 5234 gpu6_junction_config: junction-config { 5235 temperature = <95000>; 5236 hysteresis = <5000>; 5237 type = "passive"; 5238 }; 5239 }; 5240 }; 5241 5242 gpuss-7-thermal { 5243 polling-delay-passive = <10>; 5244 polling-delay = <0>; 5245 thermal-sensors = <&tsens2 8>; 5246 5247 trips { 5248 thermal-engine-config { 5249 temperature = <125000>; 5250 hysteresis = <1000>; 5251 type = "passive"; 5252 }; 5253 5254 thermal-hal-config { 5255 temperature = <125000>; 5256 hysteresis = <1000>; 5257 type = "passive"; 5258 }; 5259 5260 reset-mon-config { 5261 temperature = <115000>; 5262 hysteresis = <5000>; 5263 type = "passive"; 5264 }; 5265 5266 gpu7_junction_config: junction-config { 5267 temperature = <95000>; 5268 hysteresis = <5000>; 5269 type = "passive"; 5270 }; 5271 }; 5272 }; 5273 }; 5274 5275 timer { 5276 compatible = "arm,armv8-timer"; 5277 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5278 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5279 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5280 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5281 }; 5282}; 5283