1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8550-gcc.h> 8#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 9#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 }; 38 39 bi_tcxo_div2: bi-tcxo-div2-clk { 40 #clock-cells = <0>; 41 compatible = "fixed-factor-clock"; 42 clocks = <&rpmhcc RPMH_CXO_CLK>; 43 clock-mult = <1>; 44 clock-div = <2>; 45 }; 46 47 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 48 #clock-cells = <0>; 49 compatible = "fixed-factor-clock"; 50 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 }; 59 }; 60 61 cpus { 62 #address-cells = <2>; 63 #size-cells = <0>; 64 65 CPU0: cpu@0 { 66 device_type = "cpu"; 67 compatible = "qcom,kryo"; 68 reg = <0 0>; 69 enable-method = "psci"; 70 next-level-cache = <&L2_0>; 71 power-domains = <&CPU_PD0>; 72 power-domain-names = "psci"; 73 qcom,freq-domain = <&cpufreq_hw 0>; 74 capacity-dmips-mhz = <1024>; 75 dynamic-power-coefficient = <100>; 76 #cooling-cells = <2>; 77 L2_0: l2-cache { 78 compatible = "cache"; 79 cache-level = <2>; 80 next-level-cache = <&L3_0>; 81 L3_0: l3-cache { 82 compatible = "cache"; 83 cache-level = <3>; 84 }; 85 }; 86 }; 87 88 CPU1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0 0x100>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_100>; 94 power-domains = <&CPU_PD1>; 95 power-domain-names = "psci"; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 capacity-dmips-mhz = <1024>; 98 dynamic-power-coefficient = <100>; 99 #cooling-cells = <2>; 100 L2_100: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 next-level-cache = <&L3_0>; 104 }; 105 }; 106 107 CPU2: cpu@200 { 108 device_type = "cpu"; 109 compatible = "qcom,kryo"; 110 reg = <0 0x200>; 111 enable-method = "psci"; 112 next-level-cache = <&L2_200>; 113 power-domains = <&CPU_PD2>; 114 power-domain-names = "psci"; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 #cooling-cells = <2>; 119 L2_200: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo"; 129 reg = <0 0x300>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_300>; 132 power-domains = <&CPU_PD3>; 133 power-domain-names = "psci"; 134 qcom,freq-domain = <&cpufreq_hw 1>; 135 capacity-dmips-mhz = <1792>; 136 dynamic-power-coefficient = <270>; 137 #cooling-cells = <2>; 138 L2_300: l2-cache { 139 compatible = "cache"; 140 cache-level = <2>; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo"; 148 reg = <0 0x400>; 149 enable-method = "psci"; 150 next-level-cache = <&L2_400>; 151 power-domains = <&CPU_PD4>; 152 power-domain-names = "psci"; 153 qcom,freq-domain = <&cpufreq_hw 1>; 154 capacity-dmips-mhz = <1792>; 155 dynamic-power-coefficient = <270>; 156 #cooling-cells = <2>; 157 L2_400: l2-cache { 158 compatible = "cache"; 159 cache-level = <2>; 160 next-level-cache = <&L3_0>; 161 }; 162 }; 163 164 CPU5: cpu@500 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo"; 167 reg = <0 0x500>; 168 enable-method = "psci"; 169 next-level-cache = <&L2_500>; 170 power-domains = <&CPU_PD5>; 171 power-domain-names = "psci"; 172 qcom,freq-domain = <&cpufreq_hw 1>; 173 capacity-dmips-mhz = <1792>; 174 dynamic-power-coefficient = <270>; 175 #cooling-cells = <2>; 176 L2_500: l2-cache { 177 compatible = "cache"; 178 cache-level = <2>; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo"; 186 reg = <0 0x600>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_600>; 189 power-domains = <&CPU_PD6>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <270>; 194 #cooling-cells = <2>; 195 L2_600: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU7: cpu@700 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo"; 205 reg = <0 0x700>; 206 enable-method = "psci"; 207 next-level-cache = <&L2_700>; 208 power-domains = <&CPU_PD7>; 209 power-domain-names = "psci"; 210 qcom,freq-domain = <&cpufreq_hw 2>; 211 capacity-dmips-mhz = <1894>; 212 dynamic-power-coefficient = <588>; 213 #cooling-cells = <2>; 214 L2_700: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 next-level-cache = <&L3_0>; 218 }; 219 }; 220 221 cpu-map { 222 cluster0 { 223 core0 { 224 cpu = <&CPU0>; 225 }; 226 227 core1 { 228 cpu = <&CPU1>; 229 }; 230 231 core2 { 232 cpu = <&CPU2>; 233 }; 234 235 core3 { 236 cpu = <&CPU3>; 237 }; 238 239 core4 { 240 cpu = <&CPU4>; 241 }; 242 243 core5 { 244 cpu = <&CPU5>; 245 }; 246 247 core6 { 248 cpu = <&CPU6>; 249 }; 250 251 core7 { 252 cpu = <&CPU7>; 253 }; 254 }; 255 }; 256 257 idle-states { 258 entry-method = "psci"; 259 260 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "silver-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <800>; 265 exit-latency-us = <750>; 266 min-residency-us = <4090>; 267 local-timer-stop; 268 }; 269 270 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "gold-rail-power-collapse"; 273 arm,psci-suspend-param = <0x40000004>; 274 entry-latency-us = <600>; 275 exit-latency-us = <1550>; 276 min-residency-us = <4791>; 277 local-timer-stop; 278 }; 279 }; 280 281 domain-idle-states { 282 CLUSTER_SLEEP_0: cluster-sleep-0 { 283 compatible = "domain-idle-state"; 284 arm,psci-suspend-param = <0x41000044>; 285 entry-latency-us = <1050>; 286 exit-latency-us = <2500>; 287 min-residency-us = <5309>; 288 }; 289 290 CLUSTER_SLEEP_1: cluster-sleep-1 { 291 compatible = "domain-idle-state"; 292 arm,psci-suspend-param = <0x4100c344>; 293 entry-latency-us = <2700>; 294 exit-latency-us = <3500>; 295 min-residency-us = <13959>; 296 }; 297 }; 298 }; 299 300 firmware { 301 scm: scm { 302 compatible = "qcom,scm-sm8550", "qcom,scm"; 303 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 304 }; 305 }; 306 307 clk_virt: interconnect-0 { 308 compatible = "qcom,sm8550-clk-virt"; 309 #interconnect-cells = <2>; 310 qcom,bcm-voters = <&apps_bcm_voter>; 311 }; 312 313 mc_virt: interconnect-1 { 314 compatible = "qcom,sm8550-mc-virt"; 315 #interconnect-cells = <2>; 316 qcom,bcm-voters = <&apps_bcm_voter>; 317 }; 318 319 memory@a0000000 { 320 device_type = "memory"; 321 /* We expect the bootloader to fill in the size */ 322 reg = <0 0xa0000000 0 0>; 323 }; 324 325 pmu { 326 compatible = "arm,armv8-pmuv3"; 327 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 328 }; 329 330 psci { 331 compatible = "arm,psci-1.0"; 332 method = "smc"; 333 334 CPU_PD0: power-domain-cpu0 { 335 #power-domain-cells = <0>; 336 power-domains = <&CLUSTER_PD>; 337 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 338 }; 339 340 CPU_PD1: power-domain-cpu1 { 341 #power-domain-cells = <0>; 342 power-domains = <&CLUSTER_PD>; 343 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 344 }; 345 346 CPU_PD2: power-domain-cpu2 { 347 #power-domain-cells = <0>; 348 power-domains = <&CLUSTER_PD>; 349 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 350 }; 351 352 CPU_PD3: power-domain-cpu3 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD>; 355 domain-idle-states = <&BIG_CPU_SLEEP_0>; 356 }; 357 358 CPU_PD4: power-domain-cpu4 { 359 #power-domain-cells = <0>; 360 power-domains = <&CLUSTER_PD>; 361 domain-idle-states = <&BIG_CPU_SLEEP_0>; 362 }; 363 364 CPU_PD5: power-domain-cpu5 { 365 #power-domain-cells = <0>; 366 power-domains = <&CLUSTER_PD>; 367 domain-idle-states = <&BIG_CPU_SLEEP_0>; 368 }; 369 370 CPU_PD6: power-domain-cpu6 { 371 #power-domain-cells = <0>; 372 power-domains = <&CLUSTER_PD>; 373 domain-idle-states = <&BIG_CPU_SLEEP_0>; 374 }; 375 376 CPU_PD7: power-domain-cpu7 { 377 #power-domain-cells = <0>; 378 power-domains = <&CLUSTER_PD>; 379 domain-idle-states = <&BIG_CPU_SLEEP_0>; 380 }; 381 382 CLUSTER_PD: power-domain-cluster { 383 #power-domain-cells = <0>; 384 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 385 }; 386 }; 387 388 reserved_memory: reserved-memory { 389 #address-cells = <2>; 390 #size-cells = <2>; 391 ranges; 392 393 hyp_mem: hyp-region@80000000 { 394 reg = <0 0x80000000 0 0xa00000>; 395 no-map; 396 }; 397 398 cpusys_vm_mem: cpusys-vm-region@80a00000 { 399 reg = <0 0x80a00000 0 0x400000>; 400 no-map; 401 }; 402 403 hyp_tags_mem: hyp-tags-region@80e00000 { 404 reg = <0 0x80e00000 0 0x3d0000>; 405 no-map; 406 }; 407 408 xbl_sc_mem: xbl-sc-region@d8100000 { 409 reg = <0 0xd8100000 0 0x40000>; 410 no-map; 411 }; 412 413 414 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 415 reg = <0 0x811d0000 0 0x30000>; 416 no-map; 417 }; 418 419 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 420 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 421 reg = <0 0x81a00000 0 0x260000>; 422 no-map; 423 }; 424 425 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 426 compatible = "qcom,cmd-db"; 427 reg = <0 0x81c60000 0 0x20000>; 428 no-map; 429 }; 430 431 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 432 aop_config_merged_mem: aop-config-merged-region@81c80000 { 433 reg = <0 0x81c80000 0 0x74000>; 434 no-map; 435 }; 436 437 /* secdata region can be reused by apps */ 438 smem: smem@81d00000 { 439 compatible = "qcom,smem"; 440 reg = <0 0x81d00000 0 0x200000>; 441 hwlocks = <&tcsr_mutex 3>; 442 no-map; 443 }; 444 445 adsp_mhi_mem: adsp-mhi-region@81f00000 { 446 reg = <0 0x81f00000 0 0x20000>; 447 no-map; 448 }; 449 450 global_sync_mem: global-sync-region@82600000 { 451 reg = <0 0x82600000 0 0x100000>; 452 no-map; 453 }; 454 455 tz_stat_mem: tz-stat-region@82700000 { 456 reg = <0 0x82700000 0 0x100000>; 457 no-map; 458 }; 459 460 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 461 reg = <0 0x82800000 0 0x4600000>; 462 no-map; 463 }; 464 465 mpss_mem: mpss-region@8a800000 { 466 reg = <0 0x8a800000 0 0x10800000>; 467 no-map; 468 }; 469 470 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 471 reg = <0 0x9b000000 0 0x80000>; 472 no-map; 473 }; 474 475 ipa_fw_mem: ipa-fw-region@9b080000 { 476 reg = <0 0x9b080000 0 0x10000>; 477 no-map; 478 }; 479 480 ipa_gsi_mem: ipa-gsi-region@9b090000 { 481 reg = <0 0x9b090000 0 0xa000>; 482 no-map; 483 }; 484 485 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 486 reg = <0 0x9b09a000 0 0x2000>; 487 no-map; 488 }; 489 490 spss_region_mem: spss-region@9b100000 { 491 reg = <0 0x9b100000 0 0x180000>; 492 no-map; 493 }; 494 495 /* First part of the "SPU secure shared memory" region */ 496 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 497 reg = <0 0x9b280000 0 0x60000>; 498 no-map; 499 }; 500 501 /* Second part of the "SPU secure shared memory" region */ 502 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 503 reg = <0 0x9b2e0000 0 0x20000>; 504 no-map; 505 }; 506 507 camera_mem: camera-region@9b300000 { 508 reg = <0 0x9b300000 0 0x800000>; 509 no-map; 510 }; 511 512 video_mem: video-region@9bb00000 { 513 reg = <0 0x9bb00000 0 0x700000>; 514 no-map; 515 }; 516 517 cvp_mem: cvp-region@9c200000 { 518 reg = <0 0x9c200000 0 0x700000>; 519 no-map; 520 }; 521 522 cdsp_mem: cdsp-region@9c900000 { 523 reg = <0 0x9c900000 0 0x2000000>; 524 no-map; 525 }; 526 527 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 528 reg = <0 0x9e900000 0 0x80000>; 529 no-map; 530 }; 531 532 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 533 reg = <0 0x9e980000 0 0x80000>; 534 no-map; 535 }; 536 537 adspslpi_mem: adspslpi-region@9ea00000 { 538 reg = <0 0x9ea00000 0 0x4080000>; 539 no-map; 540 }; 541 542 /* uefi region can be reused by apps */ 543 544 /* Linux kernel image is loaded at 0xa8000000 */ 545 546 rmtfs_mem: rmtfs-region@d4a80000 { 547 compatible = "qcom,rmtfs-mem"; 548 reg = <0x0 0xd4a80000 0x0 0x280000>; 549 no-map; 550 551 qcom,client-id = <1>; 552 qcom,vmid = <15>; 553 }; 554 555 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 556 reg = <0 0xd4d00000 0 0x3300000>; 557 no-map; 558 }; 559 560 tz_reserved_mem: tz-reserved-region@d8000000 { 561 reg = <0 0xd8000000 0 0x100000>; 562 no-map; 563 }; 564 565 cpucp_fw_mem: cpucp-fw-region@d8140000 { 566 reg = <0 0xd8140000 0 0x1c0000>; 567 no-map; 568 }; 569 570 qtee_mem: qtee-region@d8300000 { 571 reg = <0 0xd8300000 0 0x500000>; 572 no-map; 573 }; 574 575 ta_mem: ta-region@d8800000 { 576 reg = <0 0xd8800000 0 0x8a00000>; 577 no-map; 578 }; 579 580 tz_tags_mem: tz-tags-region@e1200000 { 581 reg = <0 0xe1200000 0 0x2740000>; 582 no-map; 583 }; 584 585 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 586 reg = <0 0xe6440000 0 0x279000>; 587 no-map; 588 }; 589 590 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 591 reg = <0 0xf3600000 0 0x4aee000>; 592 no-map; 593 }; 594 595 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 596 reg = <0 0xf80ee000 0 0x1000>; 597 no-map; 598 }; 599 600 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 601 reg = <0 0xf80ef000 0 0x9000>; 602 no-map; 603 }; 604 605 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 606 reg = <0 0xf80f8000 0 0x4000>; 607 no-map; 608 }; 609 610 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 611 reg = <0 0xf80fc000 0 0x4000>; 612 no-map; 613 }; 614 615 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 616 reg = <0 0xf8100000 0 0x100000>; 617 no-map; 618 }; 619 620 oem_vm_mem: oem-vm-region@f8400000 { 621 reg = <0 0xf8400000 0 0x4800000>; 622 no-map; 623 }; 624 625 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 626 reg = <0 0xfcc00000 0 0x4000>; 627 no-map; 628 }; 629 630 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 631 reg = <0 0xfcc04000 0 0x100000>; 632 no-map; 633 }; 634 635 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 636 reg = <0 0xfce00000 0 0x2900000>; 637 no-map; 638 }; 639 640 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 641 reg = <0 0xff700000 0 0x100000>; 642 no-map; 643 }; 644 }; 645 646 smp2p-adsp { 647 compatible = "qcom,smp2p"; 648 qcom,smem = <443>, <429>; 649 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 650 IPCC_MPROC_SIGNAL_SMP2P 651 IRQ_TYPE_EDGE_RISING>; 652 mboxes = <&ipcc IPCC_CLIENT_LPASS 653 IPCC_MPROC_SIGNAL_SMP2P>; 654 655 qcom,local-pid = <0>; 656 qcom,remote-pid = <2>; 657 658 smp2p_adsp_out: master-kernel { 659 qcom,entry-name = "master-kernel"; 660 #qcom,smem-state-cells = <1>; 661 }; 662 663 smp2p_adsp_in: slave-kernel { 664 qcom,entry-name = "slave-kernel"; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 }; 668 }; 669 670 smp2p-cdsp { 671 compatible = "qcom,smp2p"; 672 qcom,smem = <94>, <432>; 673 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 674 IPCC_MPROC_SIGNAL_SMP2P 675 IRQ_TYPE_EDGE_RISING>; 676 mboxes = <&ipcc IPCC_CLIENT_CDSP 677 IPCC_MPROC_SIGNAL_SMP2P>; 678 679 qcom,local-pid = <0>; 680 qcom,remote-pid = <5>; 681 682 smp2p_cdsp_out: master-kernel { 683 qcom,entry-name = "master-kernel"; 684 #qcom,smem-state-cells = <1>; 685 }; 686 687 smp2p_cdsp_in: slave-kernel { 688 qcom,entry-name = "slave-kernel"; 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 }; 692 }; 693 694 smp2p-modem { 695 compatible = "qcom,smp2p"; 696 qcom,smem = <435>, <428>; 697 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 698 IPCC_MPROC_SIGNAL_SMP2P 699 IRQ_TYPE_EDGE_RISING>; 700 mboxes = <&ipcc IPCC_CLIENT_MPSS 701 IPCC_MPROC_SIGNAL_SMP2P>; 702 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <1>; 705 706 smp2p_modem_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 smp2p_modem_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 ipa_smp2p_out: ipa-ap-to-modem { 718 qcom,entry-name = "ipa"; 719 #qcom,smem-state-cells = <1>; 720 }; 721 722 ipa_smp2p_in: ipa-modem-to-ap { 723 qcom,entry-name = "ipa"; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 }; 728 729 soc: soc@0 { 730 compatible = "simple-bus"; 731 ranges = <0 0 0 0 0x10 0>; 732 dma-ranges = <0 0 0 0 0x10 0>; 733 734 #address-cells = <2>; 735 #size-cells = <2>; 736 737 gcc: clock-controller@100000 { 738 compatible = "qcom,sm8550-gcc"; 739 reg = <0 0x00100000 0 0x1f4200>; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 #power-domain-cells = <1>; 743 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 744 <&pcie0_phy>, 745 <&pcie1_phy>, 746 <&pcie_1_phy_aux_clk>, 747 <&ufs_mem_phy 0>, 748 <&ufs_mem_phy 1>, 749 <&ufs_mem_phy 2>, 750 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 751 }; 752 753 ipcc: mailbox@408000 { 754 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 755 reg = <0 0x00408000 0 0x1000>; 756 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 757 interrupt-controller; 758 #interrupt-cells = <3>; 759 #mbox-cells = <2>; 760 }; 761 762 gpi_dma2: dma-controller@800000 { 763 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 764 #dma-cells = <3>; 765 reg = <0 0x00800000 0 0x60000>; 766 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 778 dma-channels = <12>; 779 dma-channel-mask = <0x3e>; 780 iommus = <&apps_smmu 0x436 0>; 781 status = "disabled"; 782 }; 783 784 qupv3_id_1: geniqup@8c0000 { 785 compatible = "qcom,geni-se-qup"; 786 reg = <0 0x008c0000 0 0x2000>; 787 ranges; 788 clock-names = "m-ahb", "s-ahb"; 789 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 790 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 791 iommus = <&apps_smmu 0x423 0>; 792 #address-cells = <2>; 793 #size-cells = <2>; 794 status = "disabled"; 795 796 i2c8: i2c@880000 { 797 compatible = "qcom,geni-i2c"; 798 reg = <0 0x00880000 0 0x4000>; 799 clock-names = "se"; 800 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&qup_i2c8_data_clk>; 803 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 807 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 808 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 809 interconnect-names = "qup-core", "qup-config", "qup-memory"; 810 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 811 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 812 dma-names = "tx", "rx"; 813 status = "disabled"; 814 }; 815 816 spi8: spi@880000 { 817 compatible = "qcom,geni-spi"; 818 reg = <0 0x00880000 0 0x4000>; 819 clock-names = "se"; 820 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 821 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 824 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 825 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 826 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 827 interconnect-names = "qup-core", "qup-config", "qup-memory"; 828 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 829 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 830 dma-names = "tx", "rx"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 i2c9: i2c@884000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0 0x00884000 0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&qup_i2c9_data_clk>; 843 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 847 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 848 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 849 interconnect-names = "qup-core", "qup-config", "qup-memory"; 850 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 851 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 852 dma-names = "tx", "rx"; 853 status = "disabled"; 854 }; 855 856 spi9: spi@884000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x00884000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 861 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 864 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 865 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 866 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 867 interconnect-names = "qup-core", "qup-config", "qup-memory"; 868 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 869 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 870 dma-names = "tx", "rx"; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 status = "disabled"; 874 }; 875 876 i2c10: i2c@888000 { 877 compatible = "qcom,geni-i2c"; 878 reg = <0 0x00888000 0 0x4000>; 879 clock-names = "se"; 880 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&qup_i2c10_data_clk>; 883 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 887 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 888 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 890 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 891 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 892 dma-names = "tx", "rx"; 893 status = "disabled"; 894 }; 895 896 spi10: spi@888000 { 897 compatible = "qcom,geni-spi"; 898 reg = <0 0x00888000 0 0x4000>; 899 clock-names = "se"; 900 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 901 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 904 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 906 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 907 interconnect-names = "qup-core", "qup-config", "qup-memory"; 908 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 909 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 910 dma-names = "tx", "rx"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 status = "disabled"; 914 }; 915 916 i2c11: i2c@88c000 { 917 compatible = "qcom,geni-i2c"; 918 reg = <0 0x0088c000 0 0x4000>; 919 clock-names = "se"; 920 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_i2c11_data_clk>; 923 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 927 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 928 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 929 interconnect-names = "qup-core", "qup-config", "qup-memory"; 930 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 931 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 932 dma-names = "tx", "rx"; 933 status = "disabled"; 934 }; 935 936 spi11: spi@88c000 { 937 compatible = "qcom,geni-spi"; 938 reg = <0 0x0088c000 0 0x4000>; 939 clock-names = "se"; 940 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 941 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 944 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 945 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 946 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 947 interconnect-names = "qup-core", "qup-config", "qup-memory"; 948 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 949 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 950 dma-names = "tx", "rx"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 }; 955 956 i2c12: i2c@890000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00890000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&qup_i2c12_data_clk>; 963 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 967 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 968 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 969 interconnect-names = "qup-core", "qup-config", "qup-memory"; 970 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 971 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 972 dma-names = "tx", "rx"; 973 status = "disabled"; 974 }; 975 976 spi12: spi@890000 { 977 compatible = "qcom,geni-spi"; 978 reg = <0 0x00890000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 981 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 984 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 985 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 986 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 987 interconnect-names = "qup-core", "qup-config", "qup-memory"; 988 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 989 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 990 dma-names = "tx", "rx"; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 }; 995 996 i2c13: i2c@894000 { 997 compatible = "qcom,geni-i2c"; 998 reg = <0 0x00894000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_i2c13_data_clk>; 1003 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1008 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1009 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1010 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1011 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 status = "disabled"; 1014 }; 1015 1016 spi13: spi@894000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00894000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1021 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1024 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1026 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1027 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1028 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1029 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 i2c15: i2c@89c000 { 1037 compatible = "qcom,geni-i2c"; 1038 reg = <0 0x0089c000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_i2c15_data_clk>; 1043 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1044 #address-cells = <1>; 1045 #size-cells = <0>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1048 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1049 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1050 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1051 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1052 dma-names = "tx", "rx"; 1053 status = "disabled"; 1054 }; 1055 1056 spi15: spi@89c000 { 1057 compatible = "qcom,geni-spi"; 1058 reg = <0 0x0089c000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1061 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1066 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1067 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1068 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1069 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1070 dma-names = "tx", "rx"; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 }; 1076 1077 i2c_master_hub_0: geniqup@9c0000 { 1078 compatible = "qcom,geni-se-i2c-master-hub"; 1079 reg = <0x0 0x009c0000 0x0 0x2000>; 1080 clock-names = "s-ahb"; 1081 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1082 #address-cells = <2>; 1083 #size-cells = <2>; 1084 ranges; 1085 status = "disabled"; 1086 1087 i2c_hub_0: i2c@980000 { 1088 compatible = "qcom,geni-i2c-master-hub"; 1089 reg = <0x0 0x00980000 0x0 0x4000>; 1090 clock-names = "se", "core"; 1091 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1092 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&hub_i2c0_data_clk>; 1095 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1099 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1100 interconnect-names = "qup-core", "qup-config"; 1101 status = "disabled"; 1102 }; 1103 1104 i2c_hub_1: i2c@984000 { 1105 compatible = "qcom,geni-i2c-master-hub"; 1106 reg = <0x0 0x00984000 0x0 0x4000>; 1107 clock-names = "se", "core"; 1108 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1109 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&hub_i2c1_data_clk>; 1112 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1117 interconnect-names = "qup-core", "qup-config"; 1118 status = "disabled"; 1119 }; 1120 1121 i2c_hub_2: i2c@988000 { 1122 compatible = "qcom,geni-i2c-master-hub"; 1123 reg = <0x0 0x00988000 0x0 0x4000>; 1124 clock-names = "se", "core"; 1125 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1126 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&hub_i2c2_data_clk>; 1129 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1133 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1134 interconnect-names = "qup-core", "qup-config"; 1135 status = "disabled"; 1136 }; 1137 1138 i2c_hub_3: i2c@98c000 { 1139 compatible = "qcom,geni-i2c-master-hub"; 1140 reg = <0x0 0x0098c000 0x0 0x4000>; 1141 clock-names = "se", "core"; 1142 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1143 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&hub_i2c3_data_clk>; 1146 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1151 interconnect-names = "qup-core", "qup-config"; 1152 status = "disabled"; 1153 }; 1154 1155 i2c_hub_4: i2c@990000 { 1156 compatible = "qcom,geni-i2c-master-hub"; 1157 reg = <0x0 0x00990000 0x0 0x4000>; 1158 clock-names = "se", "core"; 1159 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1160 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&hub_i2c4_data_clk>; 1163 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1167 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1168 interconnect-names = "qup-core", "qup-config"; 1169 status = "disabled"; 1170 }; 1171 1172 i2c_hub_5: i2c@994000 { 1173 compatible = "qcom,geni-i2c-master-hub"; 1174 reg = <0 0x00994000 0 0x4000>; 1175 clock-names = "se", "core"; 1176 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1177 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&hub_i2c5_data_clk>; 1180 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1184 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1185 interconnect-names = "qup-core", "qup-config"; 1186 status = "disabled"; 1187 }; 1188 1189 i2c_hub_6: i2c@998000 { 1190 compatible = "qcom,geni-i2c-master-hub"; 1191 reg = <0 0x00998000 0 0x4000>; 1192 clock-names = "se", "core"; 1193 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1194 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&hub_i2c6_data_clk>; 1197 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 status = "disabled"; 1204 }; 1205 1206 i2c_hub_7: i2c@99c000 { 1207 compatible = "qcom,geni-i2c-master-hub"; 1208 reg = <0 0x0099c000 0 0x4000>; 1209 clock-names = "se", "core"; 1210 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1211 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&hub_i2c7_data_clk>; 1214 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c_hub_8: i2c@9a0000 { 1224 compatible = "qcom,geni-i2c-master-hub"; 1225 reg = <0 0x009a0000 0 0x4000>; 1226 clock-names = "se", "core"; 1227 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1228 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&hub_i2c8_data_clk>; 1231 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 i2c_hub_9: i2c@9a4000 { 1241 compatible = "qcom,geni-i2c-master-hub"; 1242 reg = <0 0x009a4000 0 0x4000>; 1243 clock-names = "se", "core"; 1244 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1245 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&hub_i2c9_data_clk>; 1248 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1253 interconnect-names = "qup-core", "qup-config"; 1254 status = "disabled"; 1255 }; 1256 }; 1257 1258 gpi_dma1: dma-controller@a00000 { 1259 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1260 #dma-cells = <3>; 1261 reg = <0 0x00a00000 0 0x60000>; 1262 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1274 dma-channels = <12>; 1275 dma-channel-mask = <0x1e>; 1276 iommus = <&apps_smmu 0xb6 0>; 1277 status = "disabled"; 1278 }; 1279 1280 qupv3_id_0: geniqup@ac0000 { 1281 compatible = "qcom,geni-se-qup"; 1282 reg = <0 0x00ac0000 0 0x2000>; 1283 ranges; 1284 clock-names = "m-ahb", "s-ahb"; 1285 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1286 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1287 iommus = <&apps_smmu 0xa3 0>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1289 interconnect-names = "qup-core"; 1290 #address-cells = <2>; 1291 #size-cells = <2>; 1292 status = "disabled"; 1293 1294 i2c0: i2c@a80000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x00a80000 0 0x4000>; 1297 clock-names = "se"; 1298 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1299 pinctrl-names = "default"; 1300 pinctrl-0 = <&qup_i2c0_data_clk>; 1301 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1306 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1308 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1309 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 status = "disabled"; 1312 }; 1313 1314 spi0: spi@a80000 { 1315 compatible = "qcom,geni-spi"; 1316 reg = <0 0x00a80000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1319 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1323 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1324 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1325 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1326 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1327 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1328 dma-names = "tx", "rx"; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c1: i2c@a84000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00a84000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c1_data_clk>; 1341 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1345 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1346 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1347 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1348 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1349 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1350 dma-names = "tx", "rx"; 1351 status = "disabled"; 1352 }; 1353 1354 spi1: spi@a84000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0 0x00a84000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1359 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1364 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1366 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1367 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1368 dma-names = "tx", "rx"; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 i2c2: i2c@a88000 { 1375 compatible = "qcom,geni-i2c"; 1376 reg = <0 0x00a88000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_i2c2_data_clk>; 1381 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1386 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1387 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1388 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1389 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1390 dma-names = "tx", "rx"; 1391 status = "disabled"; 1392 }; 1393 1394 spi2: spi@a88000 { 1395 compatible = "qcom,geni-spi"; 1396 reg = <0 0x00a88000 0 0x4000>; 1397 clock-names = "se"; 1398 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1399 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1403 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1404 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1405 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1406 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1407 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1408 dma-names = "tx", "rx"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 i2c3: i2c@a8c000 { 1415 compatible = "qcom,geni-i2c"; 1416 reg = <0 0x00a8c000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&qup_i2c3_data_clk>; 1421 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1425 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1426 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1427 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1428 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1429 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1430 dma-names = "tx", "rx"; 1431 status = "disabled"; 1432 }; 1433 1434 spi3: spi@a8c000 { 1435 compatible = "qcom,geni-spi"; 1436 reg = <0 0x00a8c000 0 0x4000>; 1437 clock-names = "se"; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1439 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1444 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1445 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1446 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1447 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1448 dma-names = "tx", "rx"; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 i2c4: i2c@a90000 { 1455 compatible = "qcom,geni-i2c"; 1456 reg = <0 0x00a90000 0 0x4000>; 1457 clock-names = "se"; 1458 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1459 pinctrl-names = "default"; 1460 pinctrl-0 = <&qup_i2c4_data_clk>; 1461 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1465 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1466 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1467 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1468 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1469 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1470 dma-names = "tx", "rx"; 1471 status = "disabled"; 1472 }; 1473 1474 spi4: spi@a90000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0 0x00a90000 0 0x4000>; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1479 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1483 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1484 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1485 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1486 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1487 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1488 dma-names = "tx", "rx"; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 status = "disabled"; 1492 }; 1493 1494 i2c5: i2c@a94000 { 1495 compatible = "qcom,geni-i2c"; 1496 reg = <0 0x00a94000 0 0x4000>; 1497 clock-names = "se"; 1498 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_i2c5_data_clk>; 1501 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1503 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1504 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1505 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1506 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1507 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1508 dma-names = "tx", "rx"; 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 status = "disabled"; 1512 }; 1513 1514 spi5: spi@a94000 { 1515 compatible = "qcom,geni-spi"; 1516 reg = <0 0x00a94000 0 0x4000>; 1517 clock-names = "se"; 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1519 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1524 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1527 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1528 dma-names = "tx", "rx"; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 i2c6: i2c@a98000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x00a98000 0 0x4000>; 1537 clock-names = "se"; 1538 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1539 pinctrl-names = "default"; 1540 pinctrl-0 = <&qup_i2c6_data_clk>; 1541 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1544 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1545 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1546 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1547 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1548 dma-names = "tx", "rx"; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 status = "disabled"; 1552 }; 1553 1554 spi6: spi@a98000 { 1555 compatible = "qcom,geni-spi"; 1556 reg = <0 0x00a98000 0 0x4000>; 1557 clock-names = "se"; 1558 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1559 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1560 pinctrl-names = "default"; 1561 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1564 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1565 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1566 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1567 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1568 dma-names = "tx", "rx"; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 status = "disabled"; 1572 }; 1573 1574 uart7: serial@a9c000 { 1575 compatible = "qcom,geni-debug-uart"; 1576 reg = <0 0x00a9c000 0 0x4000>; 1577 clock-names = "se"; 1578 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1579 pinctrl-names = "default"; 1580 pinctrl-0 = <&qup_uart7_default>; 1581 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1582 interconnect-names = "qup-core", "qup-config"; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1584 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 status = "disabled"; 1588 }; 1589 }; 1590 1591 cnoc_main: interconnect@1500000 { 1592 compatible = "qcom,sm8550-cnoc-main"; 1593 reg = <0 0x01500000 0 0x13080>; 1594 #interconnect-cells = <2>; 1595 qcom,bcm-voters = <&apps_bcm_voter>; 1596 }; 1597 1598 config_noc: interconnect@1600000 { 1599 compatible = "qcom,sm8550-config-noc"; 1600 reg = <0 0x01600000 0 0x6200>; 1601 #interconnect-cells = <2>; 1602 qcom,bcm-voters = <&apps_bcm_voter>; 1603 }; 1604 1605 system_noc: interconnect@1680000 { 1606 compatible = "qcom,sm8550-system-noc"; 1607 reg = <0 0x01680000 0 0x1d080>; 1608 #interconnect-cells = <2>; 1609 qcom,bcm-voters = <&apps_bcm_voter>; 1610 }; 1611 1612 pcie_noc: interconnect@16c0000 { 1613 compatible = "qcom,sm8550-pcie-anoc"; 1614 reg = <0 0x016c0000 0 0x12200>; 1615 #interconnect-cells = <2>; 1616 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1617 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1618 qcom,bcm-voters = <&apps_bcm_voter>; 1619 }; 1620 1621 aggre1_noc: interconnect@16e0000 { 1622 compatible = "qcom,sm8550-aggre1-noc"; 1623 reg = <0 0x016e0000 0 0x14400>; 1624 #interconnect-cells = <2>; 1625 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1626 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1627 qcom,bcm-voters = <&apps_bcm_voter>; 1628 }; 1629 1630 aggre2_noc: interconnect@1700000 { 1631 compatible = "qcom,sm8550-aggre2-noc"; 1632 reg = <0 0x01700000 0 0x1e400>; 1633 #interconnect-cells = <2>; 1634 clocks = <&rpmhcc RPMH_IPA_CLK>; 1635 qcom,bcm-voters = <&apps_bcm_voter>; 1636 }; 1637 1638 mmss_noc: interconnect@1780000 { 1639 compatible = "qcom,sm8550-mmss-noc"; 1640 reg = <0 0x01780000 0 0x5b800>; 1641 #interconnect-cells = <2>; 1642 qcom,bcm-voters = <&apps_bcm_voter>; 1643 }; 1644 1645 pcie0: pci@1c00000 { 1646 device_type = "pci"; 1647 compatible = "qcom,pcie-sm8550"; 1648 reg = <0 0x01c00000 0 0x3000>, 1649 <0 0x60000000 0 0xf1d>, 1650 <0 0x60000f20 0 0xa8>, 1651 <0 0x60001000 0 0x1000>, 1652 <0 0x60100000 0 0x100000>; 1653 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1654 #address-cells = <3>; 1655 #size-cells = <2>; 1656 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1657 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1658 bus-range = <0x00 0xff>; 1659 1660 dma-coherent; 1661 1662 linux,pci-domain = <0>; 1663 num-lanes = <2>; 1664 1665 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1666 interrupt-names = "msi"; 1667 1668 #interrupt-cells = <1>; 1669 interrupt-map-mask = <0 0 0 0x7>; 1670 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1671 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1672 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1673 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1674 1675 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1676 <&gcc GCC_PCIE_0_AUX_CLK>, 1677 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1678 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1679 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1680 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1681 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1682 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1683 clock-names = "pipe", 1684 "aux", 1685 "cfg", 1686 "bus_master", 1687 "bus_slave", 1688 "slave_q2a", 1689 "ddrss_sf_tbu", 1690 "aggre0"; 1691 1692 interconnect-names = "pcie-mem"; 1693 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; 1694 1695 iommus = <&apps_smmu 0x1400 0x7f>; 1696 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1697 <0x100 &apps_smmu 0x1401 0x1>; 1698 1699 resets = <&gcc GCC_PCIE_0_BCR>; 1700 reset-names = "pci"; 1701 1702 power-domains = <&gcc PCIE_0_GDSC>; 1703 1704 phys = <&pcie0_phy>; 1705 phy-names = "pciephy"; 1706 1707 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1708 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1709 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&pcie0_default_state>; 1712 1713 status = "disabled"; 1714 }; 1715 1716 pcie0_phy: phy@1c06000 { 1717 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1718 reg = <0 0x01c06000 0 0x2000>; 1719 1720 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1722 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1723 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1724 <&gcc GCC_PCIE_0_PIPE_CLK>; 1725 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1726 "pipe"; 1727 1728 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1729 reset-names = "phy"; 1730 1731 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1732 assigned-clock-rates = <100000000>; 1733 1734 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1735 1736 #clock-cells = <0>; 1737 clock-output-names = "pcie0_pipe_clk"; 1738 1739 #phy-cells = <0>; 1740 1741 status = "disabled"; 1742 }; 1743 1744 pcie1: pci@1c08000 { 1745 device_type = "pci"; 1746 compatible = "qcom,pcie-sm8550"; 1747 reg = <0x0 0x01c08000 0x0 0x3000>, 1748 <0x0 0x40000000 0x0 0xf1d>, 1749 <0x0 0x40000f20 0x0 0xa8>, 1750 <0x0 0x40001000 0x0 0x1000>, 1751 <0x0 0x40100000 0x0 0x100000>; 1752 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1753 #address-cells = <3>; 1754 #size-cells = <2>; 1755 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1756 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1757 bus-range = <0x00 0xff>; 1758 1759 dma-coherent; 1760 1761 linux,pci-domain = <1>; 1762 num-lanes = <2>; 1763 1764 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1765 interrupt-names = "msi"; 1766 1767 #interrupt-cells = <1>; 1768 interrupt-map-mask = <0 0 0 0x7>; 1769 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1770 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1771 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1772 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1773 1774 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1775 <&gcc GCC_PCIE_1_AUX_CLK>, 1776 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1777 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1778 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1779 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1780 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1781 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1782 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1783 clock-names = "pipe", 1784 "aux", 1785 "cfg", 1786 "bus_master", 1787 "bus_slave", 1788 "slave_q2a", 1789 "ddrss_sf_tbu", 1790 "aggre1", 1791 "cnoc_pcie_sf_axi"; 1792 1793 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1794 assigned-clock-rates = <19200000>; 1795 1796 interconnect-names = "pcie-mem"; 1797 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; 1798 1799 iommus = <&apps_smmu 0x1480 0x7f>; 1800 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1801 <0x100 &apps_smmu 0x1481 0x1>; 1802 1803 resets = <&gcc GCC_PCIE_1_BCR>, 1804 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1805 reset-names = "pci", 1806 "pcie_1_link_down_reset"; 1807 1808 power-domains = <&gcc PCIE_1_GDSC>; 1809 1810 phys = <&pcie1_phy>; 1811 phy-names = "pciephy"; 1812 1813 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1814 enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1815 1816 pinctrl-names = "default"; 1817 pinctrl-0 = <&pcie1_default_state>; 1818 1819 status = "disabled"; 1820 }; 1821 1822 pcie1_phy: phy@1c0e000 { 1823 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1824 reg = <0x0 0x01c0e000 0x0 0x2000>; 1825 1826 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1827 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1828 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1829 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1830 <&gcc GCC_PCIE_1_PIPE_CLK>, 1831 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 1832 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1833 "pipe", "aux_phy"; 1834 1835 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1836 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1837 reset-names = "phy", "nocsr"; 1838 1839 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1840 assigned-clock-rates = <100000000>; 1841 1842 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1843 1844 #clock-cells = <0>; 1845 clock-output-names = "pcie1_pipe_clk"; 1846 1847 #phy-cells = <0>; 1848 1849 status = "disabled"; 1850 }; 1851 1852 cryptobam: dma-controller@1dc4000 { 1853 compatible = "qcom,bam-v1.7.0"; 1854 reg = <0x0 0x01dc4000 0x0 0x28000>; 1855 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1856 #dma-cells = <1>; 1857 qcom,ee = <0>; 1858 qcom,controlled-remotely; 1859 iommus = <&apps_smmu 0x480 0x0>, 1860 <&apps_smmu 0x481 0x0>; 1861 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1862 interconnect-names = "memory"; 1863 }; 1864 1865 crypto: crypto@1de0000 { 1866 compatible = "qcom,sm8550-qce"; 1867 reg = <0x0 0x01dfa000 0x0 0x6000>; 1868 dmas = <&cryptobam 4>, <&cryptobam 5>; 1869 dma-names = "rx", "tx"; 1870 iommus = <&apps_smmu 0x480 0x0>, 1871 <&apps_smmu 0x481 0x0>; 1872 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "memory"; 1874 }; 1875 1876 ufs_mem_phy: phy@1d80000 { 1877 compatible = "qcom,sm8550-qmp-ufs-phy"; 1878 reg = <0x0 0x01d80000 0x0 0x2000>; 1879 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1880 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1881 clock-names = "ref", "ref_aux"; 1882 1883 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1884 1885 resets = <&ufs_mem_hc 0>; 1886 reset-names = "ufsphy"; 1887 1888 #clock-cells = <1>; 1889 #phy-cells = <0>; 1890 1891 status = "disabled"; 1892 }; 1893 1894 ufs_mem_hc: ufs@1d84000 { 1895 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1896 "jedec,ufs-2.0"; 1897 reg = <0x0 0x01d84000 0x0 0x3000>; 1898 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1899 phys = <&ufs_mem_phy>; 1900 phy-names = "ufsphy"; 1901 lanes-per-direction = <2>; 1902 #reset-cells = <1>; 1903 resets = <&gcc GCC_UFS_PHY_BCR>; 1904 reset-names = "rst"; 1905 1906 power-domains = <&gcc UFS_PHY_GDSC>; 1907 required-opps = <&rpmhpd_opp_nom>; 1908 1909 iommus = <&apps_smmu 0x60 0x0>; 1910 1911 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1913 1914 interconnect-names = "ufs-ddr", "cpu-ufs"; 1915 clock-names = "core_clk", 1916 "bus_aggr_clk", 1917 "iface_clk", 1918 "core_clk_unipro", 1919 "ref_clk", 1920 "tx_lane0_sync_clk", 1921 "rx_lane0_sync_clk", 1922 "rx_lane1_sync_clk"; 1923 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1924 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1925 <&gcc GCC_UFS_PHY_AHB_CLK>, 1926 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1927 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1928 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1929 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1930 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1931 freq-table-hz = 1932 <75000000 300000000>, 1933 <0 0>, 1934 <0 0>, 1935 <75000000 300000000>, 1936 <100000000 403000000>, 1937 <0 0>, 1938 <0 0>, 1939 <0 0>; 1940 status = "disabled"; 1941 }; 1942 1943 tcsr_mutex: hwlock@1f40000 { 1944 compatible = "qcom,tcsr-mutex"; 1945 reg = <0 0x01f40000 0 0x20000>; 1946 #hwlock-cells = <1>; 1947 }; 1948 1949 tcsr: clock-controller@1fc0000 { 1950 compatible = "qcom,sm8550-tcsr", "syscon"; 1951 reg = <0 0x01fc0000 0 0x30000>; 1952 clocks = <&rpmhcc RPMH_CXO_CLK>; 1953 #clock-cells = <1>; 1954 #reset-cells = <1>; 1955 }; 1956 1957 remoteproc_mpss: remoteproc@4080000 { 1958 compatible = "qcom,sm8550-mpss-pas"; 1959 reg = <0x0 0x04080000 0x0 0x4040>; 1960 1961 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1962 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1963 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1964 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1965 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1966 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1967 interrupt-names = "wdog", "fatal", "ready", "handover", 1968 "stop-ack", "shutdown-ack"; 1969 1970 clocks = <&rpmhcc RPMH_CXO_CLK>; 1971 clock-names = "xo"; 1972 1973 power-domains = <&rpmhpd SM8550_CX>, 1974 <&rpmhpd SM8550_MSS>; 1975 power-domain-names = "cx", "mss"; 1976 1977 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1978 1979 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 1980 1981 qcom,qmp = <&aoss_qmp>; 1982 1983 qcom,smem-states = <&smp2p_modem_out 0>; 1984 qcom,smem-state-names = "stop"; 1985 1986 status = "disabled"; 1987 1988 glink-edge { 1989 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1990 IPCC_MPROC_SIGNAL_GLINK_QMP 1991 IRQ_TYPE_EDGE_RISING>; 1992 mboxes = <&ipcc IPCC_CLIENT_MPSS 1993 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1994 label = "mpss"; 1995 qcom,remote-pid = <1>; 1996 }; 1997 }; 1998 1999 lpass_lpiaon_noc: interconnect@7400000 { 2000 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2001 reg = <0 0x07400000 0 0x19080>; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 }; 2005 2006 lpass_lpicx_noc: interconnect@7430000 { 2007 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2008 reg = <0 0x07430000 0 0x3a200>; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 lpass_ag_noc: interconnect@7e40000 { 2014 compatible = "qcom,sm8550-lpass-ag-noc"; 2015 reg = <0 0x07e40000 0 0xe080>; 2016 #interconnect-cells = <2>; 2017 qcom,bcm-voters = <&apps_bcm_voter>; 2018 }; 2019 2020 sdhc_2: mmc@8804000 { 2021 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2022 reg = <0 0x08804000 0 0x1000>; 2023 2024 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2026 interrupt-names = "hc_irq", "pwr_irq"; 2027 2028 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2029 <&gcc GCC_SDCC2_APPS_CLK>, 2030 <&rpmhcc RPMH_CXO_CLK>; 2031 clock-names = "iface", "core", "xo"; 2032 iommus = <&apps_smmu 0x540 0>; 2033 qcom,dll-config = <0x0007642c>; 2034 qcom,ddr-config = <0x80040868>; 2035 power-domains = <&rpmhpd SM8550_CX>; 2036 operating-points-v2 = <&sdhc2_opp_table>; 2037 2038 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2039 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2040 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2041 bus-width = <4>; 2042 dma-coherent; 2043 2044 /* Forbid SDR104/SDR50 - broken hw! */ 2045 sdhci-caps-mask = <0x3 0>; 2046 2047 status = "disabled"; 2048 2049 sdhc2_opp_table: opp-table { 2050 compatible = "operating-points-v2"; 2051 2052 opp-19200000 { 2053 opp-hz = /bits/ 64 <19200000>; 2054 required-opps = <&rpmhpd_opp_min_svs>; 2055 }; 2056 2057 opp-50000000 { 2058 opp-hz = /bits/ 64 <50000000>; 2059 required-opps = <&rpmhpd_opp_low_svs>; 2060 }; 2061 2062 opp-100000000 { 2063 opp-hz = /bits/ 64 <100000000>; 2064 required-opps = <&rpmhpd_opp_svs>; 2065 }; 2066 2067 opp-202000000 { 2068 opp-hz = /bits/ 64 <202000000>; 2069 required-opps = <&rpmhpd_opp_svs_l1>; 2070 }; 2071 }; 2072 }; 2073 2074 mdss: display-subsystem@ae00000 { 2075 compatible = "qcom,sm8550-mdss"; 2076 reg = <0 0x0ae00000 0 0x1000>; 2077 reg-names = "mdss"; 2078 2079 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2080 interrupt-controller; 2081 #interrupt-cells = <1>; 2082 2083 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2084 <&gcc GCC_DISP_AHB_CLK>, 2085 <&gcc GCC_DISP_HF_AXI_CLK>, 2086 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2087 2088 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2089 2090 power-domains = <&dispcc MDSS_GDSC>; 2091 2092 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2093 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2094 interconnect-names = "mdp0-mem", "mdp1-mem"; 2095 2096 iommus = <&apps_smmu 0x1c00 0x2>; 2097 2098 #address-cells = <2>; 2099 #size-cells = <2>; 2100 ranges; 2101 2102 status = "disabled"; 2103 2104 mdss_mdp: display-controller@ae01000 { 2105 compatible = "qcom,sm8550-dpu"; 2106 reg = <0 0x0ae01000 0 0x8f000>, 2107 <0 0x0aeb0000 0 0x2008>; 2108 reg-names = "mdp", "vbif"; 2109 2110 interrupt-parent = <&mdss>; 2111 interrupts = <0>; 2112 2113 clocks = <&gcc GCC_DISP_AHB_CLK>, 2114 <&gcc GCC_DISP_HF_AXI_CLK>, 2115 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2116 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2117 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2118 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2119 clock-names = "bus", 2120 "nrt_bus", 2121 "iface", 2122 "lut", 2123 "core", 2124 "vsync"; 2125 2126 power-domains = <&rpmhpd SM8550_MMCX>; 2127 2128 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2129 assigned-clock-rates = <19200000>; 2130 2131 operating-points-v2 = <&mdp_opp_table>; 2132 2133 ports { 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 2137 port@0 { 2138 reg = <0>; 2139 dpu_intf1_out: endpoint { 2140 remote-endpoint = <&mdss_dsi0_in>; 2141 }; 2142 }; 2143 2144 port@1 { 2145 reg = <1>; 2146 dpu_intf2_out: endpoint { 2147 remote-endpoint = <&mdss_dsi1_in>; 2148 }; 2149 }; 2150 }; 2151 2152 mdp_opp_table: opp-table { 2153 compatible = "operating-points-v2"; 2154 2155 opp-200000000 { 2156 opp-hz = /bits/ 64 <200000000>; 2157 required-opps = <&rpmhpd_opp_low_svs>; 2158 }; 2159 2160 opp-325000000 { 2161 opp-hz = /bits/ 64 <325000000>; 2162 required-opps = <&rpmhpd_opp_svs>; 2163 }; 2164 2165 opp-375000000 { 2166 opp-hz = /bits/ 64 <375000000>; 2167 required-opps = <&rpmhpd_opp_svs_l1>; 2168 }; 2169 2170 opp-514000000 { 2171 opp-hz = /bits/ 64 <514000000>; 2172 required-opps = <&rpmhpd_opp_nom>; 2173 }; 2174 }; 2175 }; 2176 2177 mdss_dsi0: dsi@ae94000 { 2178 compatible = "qcom,mdss-dsi-ctrl"; 2179 reg = <0 0x0ae94000 0 0x400>; 2180 reg-names = "dsi_ctrl"; 2181 2182 interrupt-parent = <&mdss>; 2183 interrupts = <4>; 2184 2185 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2186 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2187 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2188 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2189 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2190 <&gcc GCC_DISP_HF_AXI_CLK>; 2191 clock-names = "byte", 2192 "byte_intf", 2193 "pixel", 2194 "core", 2195 "iface", 2196 "bus"; 2197 2198 power-domains = <&rpmhpd SM8550_MMCX>; 2199 2200 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2201 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2202 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2203 2204 operating-points-v2 = <&mdss_dsi_opp_table>; 2205 2206 phys = <&mdss_dsi0_phy>; 2207 phy-names = "dsi"; 2208 2209 #address-cells = <1>; 2210 #size-cells = <0>; 2211 2212 status = "disabled"; 2213 2214 ports { 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 2218 port@0 { 2219 reg = <0>; 2220 mdss_dsi0_in: endpoint { 2221 remote-endpoint = <&dpu_intf1_out>; 2222 }; 2223 }; 2224 2225 port@1 { 2226 reg = <1>; 2227 mdss_dsi0_out: endpoint { 2228 }; 2229 }; 2230 }; 2231 2232 mdss_dsi_opp_table: opp-table { 2233 compatible = "operating-points-v2"; 2234 2235 opp-187500000 { 2236 opp-hz = /bits/ 64 <187500000>; 2237 required-opps = <&rpmhpd_opp_low_svs>; 2238 }; 2239 2240 opp-300000000 { 2241 opp-hz = /bits/ 64 <300000000>; 2242 required-opps = <&rpmhpd_opp_svs>; 2243 }; 2244 2245 opp-358000000 { 2246 opp-hz = /bits/ 64 <358000000>; 2247 required-opps = <&rpmhpd_opp_svs_l1>; 2248 }; 2249 }; 2250 }; 2251 2252 mdss_dsi0_phy: phy@ae95000 { 2253 compatible = "qcom,sm8550-dsi-phy-4nm"; 2254 reg = <0 0x0ae95000 0 0x200>, 2255 <0 0x0ae95200 0 0x280>, 2256 <0 0x0ae95500 0 0x400>; 2257 reg-names = "dsi_phy", 2258 "dsi_phy_lane", 2259 "dsi_pll"; 2260 2261 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2262 <&rpmhcc RPMH_CXO_CLK>; 2263 clock-names = "iface", "ref"; 2264 2265 #clock-cells = <1>; 2266 #phy-cells = <0>; 2267 2268 status = "disabled"; 2269 }; 2270 2271 mdss_dsi1: dsi@ae96000 { 2272 compatible = "qcom,mdss-dsi-ctrl"; 2273 reg = <0 0x0ae96000 0 0x400>; 2274 reg-names = "dsi_ctrl"; 2275 2276 interrupt-parent = <&mdss>; 2277 interrupts = <5>; 2278 2279 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2280 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2281 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2282 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2283 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2284 <&gcc GCC_DISP_HF_AXI_CLK>; 2285 clock-names = "byte", 2286 "byte_intf", 2287 "pixel", 2288 "core", 2289 "iface", 2290 "bus"; 2291 2292 power-domains = <&rpmhpd SM8550_MMCX>; 2293 2294 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2295 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2296 2297 operating-points-v2 = <&mdss_dsi_opp_table>; 2298 2299 phys = <&mdss_dsi1_phy>; 2300 phy-names = "dsi"; 2301 2302 #address-cells = <1>; 2303 #size-cells = <0>; 2304 2305 status = "disabled"; 2306 2307 ports { 2308 #address-cells = <1>; 2309 #size-cells = <0>; 2310 2311 port@0 { 2312 reg = <0>; 2313 mdss_dsi1_in: endpoint { 2314 remote-endpoint = <&dpu_intf2_out>; 2315 }; 2316 }; 2317 2318 port@1 { 2319 reg = <1>; 2320 mdss_dsi1_out: endpoint { 2321 }; 2322 }; 2323 }; 2324 }; 2325 2326 mdss_dsi1_phy: phy@ae97000 { 2327 compatible = "qcom,sm8550-dsi-phy-4nm"; 2328 reg = <0 0x0ae97000 0 0x200>, 2329 <0 0x0ae97200 0 0x280>, 2330 <0 0x0ae97500 0 0x400>; 2331 reg-names = "dsi_phy", 2332 "dsi_phy_lane", 2333 "dsi_pll"; 2334 2335 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2336 <&rpmhcc RPMH_CXO_CLK>; 2337 clock-names = "iface", "ref"; 2338 2339 #clock-cells = <1>; 2340 #phy-cells = <0>; 2341 2342 status = "disabled"; 2343 }; 2344 }; 2345 2346 dispcc: clock-controller@af00000 { 2347 compatible = "qcom,sm8550-dispcc"; 2348 reg = <0 0x0af00000 0 0x20000>; 2349 clocks = <&bi_tcxo_div2>, 2350 <&bi_tcxo_ao_div2>, 2351 <&gcc GCC_DISP_AHB_CLK>, 2352 <&sleep_clk>, 2353 <&mdss_dsi0_phy 0>, 2354 <&mdss_dsi0_phy 1>, 2355 <&mdss_dsi1_phy 0>, 2356 <&mdss_dsi1_phy 1>, 2357 <0>, /* dp0 */ 2358 <0>, 2359 <0>, /* dp1 */ 2360 <0>, 2361 <0>, /* dp2 */ 2362 <0>, 2363 <0>, /* dp3 */ 2364 <0>; 2365 power-domains = <&rpmhpd SM8550_MMCX>; 2366 required-opps = <&rpmhpd_opp_low_svs>; 2367 #clock-cells = <1>; 2368 #reset-cells = <1>; 2369 #power-domain-cells = <1>; 2370 status = "disabled"; 2371 }; 2372 2373 usb_1_hsphy: phy@88e3000 { 2374 compatible = "qcom,sm8550-snps-eusb2-phy"; 2375 reg = <0x0 0x088e3000 0x0 0x154>; 2376 #phy-cells = <0>; 2377 2378 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2379 clock-names = "ref"; 2380 2381 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2382 2383 status = "disabled"; 2384 }; 2385 2386 usb_dp_qmpphy: phy@88e8000 { 2387 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2388 reg = <0x0 0x088e8000 0x0 0x3000>; 2389 2390 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2391 <&rpmhcc RPMH_CXO_CLK>, 2392 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2393 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2394 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2395 2396 power-domains = <&gcc USB3_PHY_GDSC>; 2397 2398 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2399 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2400 reset-names = "phy", "common"; 2401 2402 #clock-cells = <1>; 2403 #phy-cells = <1>; 2404 2405 status = "disabled"; 2406 }; 2407 2408 usb_1: usb@a6f8800 { 2409 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2410 reg = <0x0 0x0a6f8800 0x0 0x400>; 2411 #address-cells = <2>; 2412 #size-cells = <2>; 2413 ranges; 2414 2415 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2416 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2417 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2418 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2419 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2420 <&tcsr TCSR_USB3_CLKREF_EN>; 2421 clock-names = "cfg_noc", 2422 "core", 2423 "iface", 2424 "sleep", 2425 "mock_utmi", 2426 "xo"; 2427 2428 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2429 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2430 assigned-clock-rates = <19200000>, <200000000>; 2431 2432 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2433 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2434 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2435 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2436 interrupt-names = "hs_phy_irq", 2437 "ss_phy_irq", 2438 "dm_hs_phy_irq", 2439 "dp_hs_phy_irq"; 2440 2441 power-domains = <&gcc USB30_PRIM_GDSC>; 2442 required-opps = <&rpmhpd_opp_nom>; 2443 2444 resets = <&gcc GCC_USB30_PRIM_BCR>; 2445 2446 status = "disabled"; 2447 2448 usb_1_dwc3: usb@a600000 { 2449 compatible = "snps,dwc3"; 2450 reg = <0x0 0x0a600000 0x0 0xcd00>; 2451 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2452 iommus = <&apps_smmu 0x40 0x0>; 2453 snps,dis_u2_susphy_quirk; 2454 snps,dis_enblslpm_quirk; 2455 snps,usb3_lpm_capable; 2456 phys = <&usb_1_hsphy>, 2457 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2458 phy-names = "usb2-phy", "usb3-phy"; 2459 }; 2460 }; 2461 2462 pdc: interrupt-controller@b220000 { 2463 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2464 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2465 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2466 <125 63 1>, <126 716 12>, 2467 <138 251 5>; 2468 #interrupt-cells = <2>; 2469 interrupt-parent = <&intc>; 2470 interrupt-controller; 2471 }; 2472 2473 tsens0: thermal-sensor@c271000 { 2474 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2475 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2476 <0 0x0c222000 0 0x1000>; /* SROT */ 2477 #qcom,sensors = <16>; 2478 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2480 interrupt-names = "uplow", "critical"; 2481 #thermal-sensor-cells = <1>; 2482 }; 2483 2484 tsens1: thermal-sensor@c272000 { 2485 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2486 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2487 <0 0x0c223000 0 0x1000>; /* SROT */ 2488 #qcom,sensors = <16>; 2489 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2491 interrupt-names = "uplow", "critical"; 2492 #thermal-sensor-cells = <1>; 2493 }; 2494 2495 tsens2: thermal-sensor@c273000 { 2496 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2497 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2498 <0 0x0c224000 0 0x1000>; /* SROT */ 2499 #qcom,sensors = <16>; 2500 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2502 interrupt-names = "uplow", "critical"; 2503 #thermal-sensor-cells = <1>; 2504 }; 2505 2506 aoss_qmp: power-controller@c300000 { 2507 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2508 reg = <0 0x0c300000 0 0x400>; 2509 interrupt-parent = <&ipcc>; 2510 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2511 IRQ_TYPE_EDGE_RISING>; 2512 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2513 2514 #clock-cells = <0>; 2515 }; 2516 2517 sram@c3f0000 { 2518 compatible = "qcom,rpmh-stats"; 2519 reg = <0 0x0c3f0000 0 0x400>; 2520 }; 2521 2522 spmi_bus: spmi@c400000 { 2523 compatible = "qcom,spmi-pmic-arb"; 2524 reg = <0 0x0c400000 0 0x3000>, 2525 <0 0x0c500000 0 0x4000000>, 2526 <0 0x0c440000 0 0x80000>, 2527 <0 0x0c4c0000 0 0x20000>, 2528 <0 0x0c42d000 0 0x4000>; 2529 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2530 interrupt-names = "periph_irq"; 2531 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2532 qcom,ee = <0>; 2533 qcom,channel = <0>; 2534 qcom,bus-id = <0>; 2535 #address-cells = <2>; 2536 #size-cells = <0>; 2537 interrupt-controller; 2538 #interrupt-cells = <4>; 2539 }; 2540 2541 tlmm: pinctrl@f000000 { 2542 compatible = "qcom,sm8550-tlmm"; 2543 reg = <0 0x0f100000 0 0x300000>; 2544 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2545 gpio-controller; 2546 #gpio-cells = <2>; 2547 interrupt-controller; 2548 #interrupt-cells = <2>; 2549 gpio-ranges = <&tlmm 0 0 211>; 2550 wakeup-parent = <&pdc>; 2551 2552 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2553 /* SDA, SCL */ 2554 pins = "gpio16", "gpio17"; 2555 function = "i2chub0_se0"; 2556 drive-strength = <2>; 2557 bias-pull-up; 2558 }; 2559 2560 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2561 /* SDA, SCL */ 2562 pins = "gpio18", "gpio19"; 2563 function = "i2chub0_se1"; 2564 drive-strength = <2>; 2565 bias-pull-up; 2566 }; 2567 2568 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2569 /* SDA, SCL */ 2570 pins = "gpio20", "gpio21"; 2571 function = "i2chub0_se2"; 2572 drive-strength = <2>; 2573 bias-pull-up; 2574 }; 2575 2576 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2577 /* SDA, SCL */ 2578 pins = "gpio22", "gpio23"; 2579 function = "i2chub0_se3"; 2580 drive-strength = <2>; 2581 bias-pull-up; 2582 }; 2583 2584 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2585 /* SDA, SCL */ 2586 pins = "gpio4", "gpio5"; 2587 function = "i2chub0_se4"; 2588 drive-strength = <2>; 2589 bias-pull-up; 2590 }; 2591 2592 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2593 /* SDA, SCL */ 2594 pins = "gpio6", "gpio7"; 2595 function = "i2chub0_se5"; 2596 drive-strength = <2>; 2597 bias-pull-up; 2598 }; 2599 2600 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2601 /* SDA, SCL */ 2602 pins = "gpio8", "gpio9"; 2603 function = "i2chub0_se6"; 2604 drive-strength = <2>; 2605 bias-pull-up; 2606 }; 2607 2608 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2609 /* SDA, SCL */ 2610 pins = "gpio10", "gpio11"; 2611 function = "i2chub0_se7"; 2612 drive-strength = <2>; 2613 bias-pull-up; 2614 }; 2615 2616 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2617 /* SDA, SCL */ 2618 pins = "gpio206", "gpio207"; 2619 function = "i2chub0_se8"; 2620 drive-strength = <2>; 2621 bias-pull-up; 2622 }; 2623 2624 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2625 /* SDA, SCL */ 2626 pins = "gpio84", "gpio85"; 2627 function = "i2chub0_se9"; 2628 drive-strength = <2>; 2629 bias-pull-up; 2630 }; 2631 2632 pcie0_default_state: pcie0-default-state { 2633 perst-pins { 2634 pins = "gpio94"; 2635 function = "gpio"; 2636 drive-strength = <2>; 2637 bias-pull-down; 2638 }; 2639 2640 clkreq-pins { 2641 pins = "gpio95"; 2642 function = "pcie0_clk_req_n"; 2643 drive-strength = <2>; 2644 bias-pull-up; 2645 }; 2646 2647 wake-pins { 2648 pins = "gpio96"; 2649 function = "gpio"; 2650 drive-strength = <2>; 2651 bias-pull-up; 2652 }; 2653 }; 2654 2655 pcie1_default_state: pcie1-default-state { 2656 perst-pins { 2657 pins = "gpio97"; 2658 function = "gpio"; 2659 drive-strength = <2>; 2660 bias-pull-down; 2661 }; 2662 2663 clkreq-pins { 2664 pins = "gpio98"; 2665 function = "pcie1_clk_req_n"; 2666 drive-strength = <2>; 2667 bias-pull-up; 2668 }; 2669 2670 wake-pins { 2671 pins = "gpio99"; 2672 function = "gpio"; 2673 drive-strength = <2>; 2674 bias-pull-up; 2675 }; 2676 }; 2677 2678 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2679 /* SDA, SCL */ 2680 pins = "gpio28", "gpio29"; 2681 function = "qup1_se0"; 2682 drive-strength = <2>; 2683 bias-pull-up; 2684 }; 2685 2686 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2687 /* SDA, SCL */ 2688 pins = "gpio32", "gpio33"; 2689 function = "qup1_se1"; 2690 drive-strength = <2>; 2691 bias-pull-up; 2692 }; 2693 2694 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2695 /* SDA, SCL */ 2696 pins = "gpio36", "gpio37"; 2697 function = "qup1_se2"; 2698 drive-strength = <2>; 2699 bias-pull-up; 2700 }; 2701 2702 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2703 /* SDA, SCL */ 2704 pins = "gpio40", "gpio41"; 2705 function = "qup1_se3"; 2706 drive-strength = <2>; 2707 bias-pull-up; 2708 }; 2709 2710 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2711 /* SDA, SCL */ 2712 pins = "gpio44", "gpio45"; 2713 function = "qup1_se4"; 2714 drive-strength = <2>; 2715 bias-pull-up; 2716 }; 2717 2718 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2719 /* SDA, SCL */ 2720 pins = "gpio52", "gpio53"; 2721 function = "qup1_se5"; 2722 drive-strength = <2>; 2723 bias-pull-up; 2724 }; 2725 2726 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2727 /* SDA, SCL */ 2728 pins = "gpio48", "gpio49"; 2729 function = "qup1_se6"; 2730 drive-strength = <2>; 2731 bias-pull-up; 2732 }; 2733 2734 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2735 scl-pins { 2736 pins = "gpio57"; 2737 function = "qup2_se0_l1_mira"; 2738 drive-strength = <2>; 2739 bias-pull-up; 2740 }; 2741 2742 sda-pins { 2743 pins = "gpio56"; 2744 function = "qup2_se0_l0_mira"; 2745 drive-strength = <2>; 2746 bias-pull-up; 2747 }; 2748 }; 2749 2750 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2751 /* SDA, SCL */ 2752 pins = "gpio60", "gpio61"; 2753 function = "qup2_se1"; 2754 drive-strength = <2>; 2755 bias-pull-up; 2756 }; 2757 2758 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2759 /* SDA, SCL */ 2760 pins = "gpio64", "gpio65"; 2761 function = "qup2_se2"; 2762 drive-strength = <2>; 2763 bias-pull-up; 2764 }; 2765 2766 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2767 /* SDA, SCL */ 2768 pins = "gpio68", "gpio69"; 2769 function = "qup2_se3"; 2770 drive-strength = <2>; 2771 bias-pull-up; 2772 }; 2773 2774 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2775 /* SDA, SCL */ 2776 pins = "gpio2", "gpio3"; 2777 function = "qup2_se4"; 2778 drive-strength = <2>; 2779 bias-pull-up; 2780 }; 2781 2782 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2783 /* SDA, SCL */ 2784 pins = "gpio80", "gpio81"; 2785 function = "qup2_se5"; 2786 drive-strength = <2>; 2787 bias-pull-up; 2788 }; 2789 2790 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2791 /* SDA, SCL */ 2792 pins = "gpio72", "gpio106"; 2793 function = "qup2_se7"; 2794 drive-strength = <2>; 2795 bias-pull-up; 2796 }; 2797 2798 qup_spi0_cs: qup-spi0-cs-state { 2799 cs-pins { 2800 pins = "gpio31"; 2801 function = "qup1_se0"; 2802 }; 2803 }; 2804 2805 qup_spi0_data_clk: qup-spi0-data-clk-state { 2806 /* MISO, MOSI, CLK */ 2807 pins = "gpio28", "gpio29", "gpio30"; 2808 function = "qup1_se0"; 2809 drive-strength = <6>; 2810 bias-disable; 2811 }; 2812 2813 qup_spi1_cs: qup-spi1-cs-state { 2814 pins = "gpio35"; 2815 function = "qup1_se1"; 2816 drive-strength = <6>; 2817 bias-disable; 2818 }; 2819 2820 qup_spi1_data_clk: qup-spi1-data-clk-state { 2821 /* MISO, MOSI, CLK */ 2822 pins = "gpio32", "gpio33", "gpio34"; 2823 function = "qup1_se1"; 2824 drive-strength = <6>; 2825 bias-disable; 2826 }; 2827 2828 qup_spi2_cs: qup-spi2-cs-state { 2829 pins = "gpio39"; 2830 function = "qup1_se2"; 2831 drive-strength = <6>; 2832 bias-disable; 2833 }; 2834 2835 qup_spi2_data_clk: qup-spi2-data-clk-state { 2836 /* MISO, MOSI, CLK */ 2837 pins = "gpio36", "gpio37", "gpio38"; 2838 function = "qup1_se2"; 2839 drive-strength = <6>; 2840 bias-disable; 2841 }; 2842 2843 qup_spi3_cs: qup-spi3-cs-state { 2844 pins = "gpio43"; 2845 function = "qup1_se3"; 2846 drive-strength = <6>; 2847 bias-disable; 2848 }; 2849 2850 qup_spi3_data_clk: qup-spi3-data-clk-state { 2851 /* MISO, MOSI, CLK */ 2852 pins = "gpio40", "gpio41", "gpio42"; 2853 function = "qup1_se3"; 2854 drive-strength = <6>; 2855 bias-disable; 2856 }; 2857 2858 qup_spi4_cs: qup-spi4-cs-state { 2859 pins = "gpio47"; 2860 function = "qup1_se4"; 2861 drive-strength = <6>; 2862 bias-disable; 2863 }; 2864 2865 qup_spi4_data_clk: qup-spi4-data-clk-state { 2866 /* MISO, MOSI, CLK */ 2867 pins = "gpio44", "gpio45", "gpio46"; 2868 function = "qup1_se4"; 2869 drive-strength = <6>; 2870 bias-disable; 2871 }; 2872 2873 qup_spi5_cs: qup-spi5-cs-state { 2874 pins = "gpio55"; 2875 function = "qup1_se5"; 2876 drive-strength = <6>; 2877 bias-disable; 2878 }; 2879 2880 qup_spi5_data_clk: qup-spi5-data-clk-state { 2881 /* MISO, MOSI, CLK */ 2882 pins = "gpio52", "gpio53", "gpio54"; 2883 function = "qup1_se5"; 2884 drive-strength = <6>; 2885 bias-disable; 2886 }; 2887 2888 qup_spi6_cs: qup-spi6-cs-state { 2889 pins = "gpio51"; 2890 function = "qup1_se6"; 2891 drive-strength = <6>; 2892 bias-disable; 2893 }; 2894 2895 qup_spi6_data_clk: qup-spi6-data-clk-state { 2896 /* MISO, MOSI, CLK */ 2897 pins = "gpio48", "gpio49", "gpio50"; 2898 function = "qup1_se6"; 2899 drive-strength = <6>; 2900 bias-disable; 2901 }; 2902 2903 qup_spi8_cs: qup-spi8-cs-state { 2904 pins = "gpio59"; 2905 function = "qup2_se0_l3_mira"; 2906 drive-strength = <6>; 2907 bias-disable; 2908 }; 2909 2910 qup_spi8_data_clk: qup-spi8-data-clk-state { 2911 /* MISO, MOSI, CLK */ 2912 pins = "gpio56", "gpio57", "gpio58"; 2913 function = "qup2_se0_l2_mira"; 2914 drive-strength = <6>; 2915 bias-disable; 2916 }; 2917 2918 qup_spi9_cs: qup-spi9-cs-state { 2919 pins = "gpio63"; 2920 function = "qup2_se1"; 2921 drive-strength = <6>; 2922 bias-disable; 2923 }; 2924 2925 qup_spi9_data_clk: qup-spi9-data-clk-state { 2926 /* MISO, MOSI, CLK */ 2927 pins = "gpio60", "gpio61", "gpio62"; 2928 function = "qup2_se1"; 2929 drive-strength = <6>; 2930 bias-disable; 2931 }; 2932 2933 qup_spi10_cs: qup-spi10-cs-state { 2934 pins = "gpio67"; 2935 function = "qup2_se2"; 2936 drive-strength = <6>; 2937 bias-disable; 2938 }; 2939 2940 qup_spi10_data_clk: qup-spi10-data-clk-state { 2941 /* MISO, MOSI, CLK */ 2942 pins = "gpio64", "gpio65", "gpio66"; 2943 function = "qup2_se2"; 2944 drive-strength = <6>; 2945 bias-disable; 2946 }; 2947 2948 qup_spi11_cs: qup-spi11-cs-state { 2949 pins = "gpio71"; 2950 function = "qup2_se3"; 2951 drive-strength = <6>; 2952 bias-disable; 2953 }; 2954 2955 qup_spi11_data_clk: qup-spi11-data-clk-state { 2956 /* MISO, MOSI, CLK */ 2957 pins = "gpio68", "gpio69", "gpio70"; 2958 function = "qup2_se3"; 2959 drive-strength = <6>; 2960 bias-disable; 2961 }; 2962 2963 qup_spi12_cs: qup-spi12-cs-state { 2964 pins = "gpio119"; 2965 function = "qup2_se4"; 2966 drive-strength = <6>; 2967 bias-disable; 2968 }; 2969 2970 qup_spi12_data_clk: qup-spi12-data-clk-state { 2971 /* MISO, MOSI, CLK */ 2972 pins = "gpio2", "gpio3", "gpio118"; 2973 function = "qup2_se4"; 2974 drive-strength = <6>; 2975 bias-disable; 2976 }; 2977 2978 qup_spi13_cs: qup-spi13-cs-state { 2979 pins = "gpio83"; 2980 function = "qup2_se5"; 2981 drive-strength = <6>; 2982 bias-disable; 2983 }; 2984 2985 qup_spi13_data_clk: qup-spi13-data-clk-state { 2986 /* MISO, MOSI, CLK */ 2987 pins = "gpio80", "gpio81", "gpio82"; 2988 function = "qup2_se5"; 2989 drive-strength = <6>; 2990 bias-disable; 2991 }; 2992 2993 qup_spi15_cs: qup-spi15-cs-state { 2994 pins = "gpio75"; 2995 function = "qup2_se7"; 2996 drive-strength = <6>; 2997 bias-disable; 2998 }; 2999 3000 qup_spi15_data_clk: qup-spi15-data-clk-state { 3001 /* MISO, MOSI, CLK */ 3002 pins = "gpio72", "gpio106", "gpio74"; 3003 function = "qup2_se7"; 3004 drive-strength = <6>; 3005 bias-disable; 3006 }; 3007 3008 qup_uart7_default: qup-uart7-default-state { 3009 /* TX, RX */ 3010 pins = "gpio26", "gpio27"; 3011 function = "qup1_se7"; 3012 drive-strength = <2>; 3013 bias-disable; 3014 }; 3015 3016 sdc2_sleep: sdc2-sleep-state { 3017 clk-pins { 3018 pins = "sdc2_clk"; 3019 bias-disable; 3020 drive-strength = <2>; 3021 }; 3022 3023 cmd-pins { 3024 pins = "sdc2_cmd"; 3025 bias-pull-up; 3026 drive-strength = <2>; 3027 }; 3028 3029 data-pins { 3030 pins = "sdc2_data"; 3031 bias-pull-up; 3032 drive-strength = <2>; 3033 }; 3034 }; 3035 3036 sdc2_default: sdc2-default-state { 3037 clk-pins { 3038 pins = "sdc2_clk"; 3039 bias-disable; 3040 drive-strength = <16>; 3041 }; 3042 3043 cmd-pins { 3044 pins = "sdc2_cmd"; 3045 bias-pull-up; 3046 drive-strength = <10>; 3047 }; 3048 3049 data-pins { 3050 pins = "sdc2_data"; 3051 bias-pull-up; 3052 drive-strength = <10>; 3053 }; 3054 }; 3055 }; 3056 3057 apps_smmu: iommu@15000000 { 3058 compatible = "qcom,smmu-500", "arm,mmu-500"; 3059 reg = <0 0x15000000 0 0x100000>; 3060 #iommu-cells = <2>; 3061 #global-interrupts = <1>; 3062 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3159 }; 3160 3161 intc: interrupt-controller@17100000 { 3162 compatible = "arm,gic-v3"; 3163 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3164 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3165 ranges; 3166 #interrupt-cells = <3>; 3167 interrupt-controller; 3168 #redistributor-regions = <1>; 3169 redistributor-stride = <0 0x40000>; 3170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3171 #address-cells = <2>; 3172 #size-cells = <2>; 3173 3174 gic_its: msi-controller@17140000 { 3175 compatible = "arm,gic-v3-its"; 3176 reg = <0 0x17140000 0 0x20000>; 3177 msi-controller; 3178 #msi-cells = <1>; 3179 }; 3180 }; 3181 3182 timer@17420000 { 3183 compatible = "arm,armv7-timer-mem"; 3184 reg = <0 0x17420000 0 0x1000>; 3185 ranges = <0 0 0 0x20000000>; 3186 #address-cells = <1>; 3187 #size-cells = <1>; 3188 3189 frame@17421000 { 3190 reg = <0x17421000 0x1000>, 3191 <0x17422000 0x1000>; 3192 frame-number = <0>; 3193 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3195 }; 3196 3197 frame@17423000 { 3198 reg = <0x17423000 0x1000>; 3199 frame-number = <1>; 3200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3201 status = "disabled"; 3202 }; 3203 3204 frame@17425000 { 3205 reg = <0x17425000 0x1000>; 3206 frame-number = <2>; 3207 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3208 status = "disabled"; 3209 }; 3210 3211 frame@17427000 { 3212 reg = <0x17427000 0x1000>; 3213 frame-number = <3>; 3214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3215 status = "disabled"; 3216 }; 3217 3218 frame@17429000 { 3219 reg = <0x17429000 0x1000>; 3220 frame-number = <4>; 3221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3222 status = "disabled"; 3223 }; 3224 3225 frame@1742b000 { 3226 reg = <0x1742b000 0x1000>; 3227 frame-number = <5>; 3228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3229 status = "disabled"; 3230 }; 3231 3232 frame@1742d000 { 3233 reg = <0x1742d000 0x1000>; 3234 frame-number = <6>; 3235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3236 status = "disabled"; 3237 }; 3238 }; 3239 3240 apps_rsc: rsc@17a00000 { 3241 label = "apps_rsc"; 3242 compatible = "qcom,rpmh-rsc"; 3243 reg = <0 0x17a00000 0 0x10000>, 3244 <0 0x17a10000 0 0x10000>, 3245 <0 0x17a20000 0 0x10000>, 3246 <0 0x17a30000 0 0x10000>; 3247 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3248 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3251 qcom,tcs-offset = <0xd00>; 3252 qcom,drv-id = <2>; 3253 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3254 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3255 3256 apps_bcm_voter: bcm-voter { 3257 compatible = "qcom,bcm-voter"; 3258 }; 3259 3260 rpmhcc: clock-controller { 3261 compatible = "qcom,sm8550-rpmh-clk"; 3262 #clock-cells = <1>; 3263 clock-names = "xo"; 3264 clocks = <&xo_board>; 3265 }; 3266 3267 rpmhpd: power-controller { 3268 compatible = "qcom,sm8550-rpmhpd"; 3269 #power-domain-cells = <1>; 3270 operating-points-v2 = <&rpmhpd_opp_table>; 3271 3272 rpmhpd_opp_table: opp-table { 3273 compatible = "operating-points-v2"; 3274 3275 rpmhpd_opp_ret: opp1 { 3276 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3277 }; 3278 3279 rpmhpd_opp_min_svs: opp2 { 3280 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3281 }; 3282 3283 rpmhpd_opp_low_svs: opp3 { 3284 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3285 }; 3286 3287 rpmhpd_opp_svs: opp4 { 3288 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3289 }; 3290 3291 rpmhpd_opp_svs_l1: opp5 { 3292 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3293 }; 3294 3295 rpmhpd_opp_nom: opp6 { 3296 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3297 }; 3298 3299 rpmhpd_opp_nom_l1: opp7 { 3300 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3301 }; 3302 3303 rpmhpd_opp_nom_l2: opp8 { 3304 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3305 }; 3306 3307 rpmhpd_opp_turbo: opp9 { 3308 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3309 }; 3310 3311 rpmhpd_opp_turbo_l1: opp10 { 3312 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3313 }; 3314 }; 3315 }; 3316 }; 3317 3318 cpufreq_hw: cpufreq@17d91000 { 3319 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3320 reg = <0 0x17d91000 0 0x1000>, 3321 <0 0x17d92000 0 0x1000>, 3322 <0 0x17d93000 0 0x1000>; 3323 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3324 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3325 clock-names = "xo", "alternate"; 3326 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3329 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3330 #freq-domain-cells = <1>; 3331 }; 3332 3333 pmu@24091000 { 3334 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3335 reg = <0 0x24091000 0 0x1000>; 3336 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3337 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3338 3339 operating-points-v2 = <&llcc_bwmon_opp_table>; 3340 3341 llcc_bwmon_opp_table: opp-table { 3342 compatible = "operating-points-v2"; 3343 3344 opp-0 { 3345 opp-peak-kBps = <2086000>; 3346 }; 3347 3348 opp-1 { 3349 opp-peak-kBps = <2929000>; 3350 }; 3351 3352 opp-2 { 3353 opp-peak-kBps = <5931000>; 3354 }; 3355 3356 opp-3 { 3357 opp-peak-kBps = <6515000>; 3358 }; 3359 3360 opp-4 { 3361 opp-peak-kBps = <7980000>; 3362 }; 3363 3364 opp-5 { 3365 opp-peak-kBps = <10437000>; 3366 }; 3367 3368 opp-6 { 3369 opp-peak-kBps = <12157000>; 3370 }; 3371 3372 opp-7 { 3373 opp-peak-kBps = <14060000>; 3374 }; 3375 3376 opp-8 { 3377 opp-peak-kBps = <16113000>; 3378 }; 3379 }; 3380 }; 3381 3382 pmu@240b6400 { 3383 compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; 3384 reg = <0 0x240b6400 0 0x600>; 3385 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3386 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3387 3388 operating-points-v2 = <&cpu_bwmon_opp_table>; 3389 3390 cpu_bwmon_opp_table: opp-table { 3391 compatible = "operating-points-v2"; 3392 3393 opp-0 { 3394 opp-peak-kBps = <4577000>; 3395 }; 3396 3397 opp-1 { 3398 opp-peak-kBps = <7110000>; 3399 }; 3400 3401 opp-2 { 3402 opp-peak-kBps = <9155000>; 3403 }; 3404 3405 opp-3 { 3406 opp-peak-kBps = <12298000>; 3407 }; 3408 3409 opp-4 { 3410 opp-peak-kBps = <14236000>; 3411 }; 3412 3413 opp-5 { 3414 opp-peak-kBps = <16265000>; 3415 }; 3416 }; 3417 }; 3418 3419 gem_noc: interconnect@24100000 { 3420 compatible = "qcom,sm8550-gem-noc"; 3421 reg = <0 0x24100000 0 0xbb800>; 3422 #interconnect-cells = <2>; 3423 qcom,bcm-voters = <&apps_bcm_voter>; 3424 }; 3425 3426 system-cache-controller@25000000 { 3427 compatible = "qcom,sm8550-llcc"; 3428 reg = <0 0x25000000 0 0x800000>, 3429 <0 0x25800000 0 0x200000>; 3430 reg-names = "llcc_base", "llcc_broadcast_base"; 3431 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3432 }; 3433 3434 remoteproc_adsp: remoteproc@30000000 { 3435 compatible = "qcom,sm8550-adsp-pas"; 3436 reg = <0x0 0x30000000 0x0 0x100>; 3437 3438 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3439 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3440 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3441 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3442 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3443 interrupt-names = "wdog", "fatal", "ready", 3444 "handover", "stop-ack"; 3445 3446 clocks = <&rpmhcc RPMH_CXO_CLK>; 3447 clock-names = "xo"; 3448 3449 power-domains = <&rpmhpd SM8550_LCX>, 3450 <&rpmhpd SM8550_LMX>; 3451 power-domain-names = "lcx", "lmx"; 3452 3453 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3454 3455 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3456 3457 qcom,qmp = <&aoss_qmp>; 3458 3459 qcom,smem-states = <&smp2p_adsp_out 0>; 3460 qcom,smem-state-names = "stop"; 3461 3462 status = "disabled"; 3463 3464 remoteproc_adsp_glink: glink-edge { 3465 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3466 IPCC_MPROC_SIGNAL_GLINK_QMP 3467 IRQ_TYPE_EDGE_RISING>; 3468 mboxes = <&ipcc IPCC_CLIENT_LPASS 3469 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3470 3471 label = "lpass"; 3472 qcom,remote-pid = <2>; 3473 3474 fastrpc { 3475 compatible = "qcom,fastrpc"; 3476 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3477 label = "adsp"; 3478 #address-cells = <1>; 3479 #size-cells = <0>; 3480 3481 compute-cb@3 { 3482 compatible = "qcom,fastrpc-compute-cb"; 3483 reg = <3>; 3484 iommus = <&apps_smmu 0x1003 0x80>, 3485 <&apps_smmu 0x1063 0x0>; 3486 }; 3487 3488 compute-cb@4 { 3489 compatible = "qcom,fastrpc-compute-cb"; 3490 reg = <4>; 3491 iommus = <&apps_smmu 0x1004 0x80>, 3492 <&apps_smmu 0x1064 0x0>; 3493 }; 3494 3495 compute-cb@5 { 3496 compatible = "qcom,fastrpc-compute-cb"; 3497 reg = <5>; 3498 iommus = <&apps_smmu 0x1005 0x80>, 3499 <&apps_smmu 0x1065 0x0>; 3500 }; 3501 3502 compute-cb@6 { 3503 compatible = "qcom,fastrpc-compute-cb"; 3504 reg = <6>; 3505 iommus = <&apps_smmu 0x1006 0x80>, 3506 <&apps_smmu 0x1066 0x0>; 3507 }; 3508 3509 compute-cb@7 { 3510 compatible = "qcom,fastrpc-compute-cb"; 3511 reg = <7>; 3512 iommus = <&apps_smmu 0x1007 0x80>, 3513 <&apps_smmu 0x1067 0x0>; 3514 }; 3515 }; 3516 }; 3517 }; 3518 3519 nsp_noc: interconnect@320c0000 { 3520 compatible = "qcom,sm8550-nsp-noc"; 3521 reg = <0 0x320c0000 0 0xe080>; 3522 #interconnect-cells = <2>; 3523 qcom,bcm-voters = <&apps_bcm_voter>; 3524 }; 3525 3526 remoteproc_cdsp: remoteproc@32300000 { 3527 compatible = "qcom,sm8550-cdsp-pas"; 3528 reg = <0x0 0x32300000 0x0 0x1400000>; 3529 3530 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3531 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3532 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3533 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3534 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3535 interrupt-names = "wdog", "fatal", "ready", 3536 "handover", "stop-ack"; 3537 3538 clocks = <&rpmhcc RPMH_CXO_CLK>; 3539 clock-names = "xo"; 3540 3541 power-domains = <&rpmhpd SM8550_CX>, 3542 <&rpmhpd SM8550_MXC>, 3543 <&rpmhpd SM8550_NSP>; 3544 power-domain-names = "cx", "mxc", "nsp"; 3545 3546 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3547 3548 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 3549 3550 qcom,qmp = <&aoss_qmp>; 3551 3552 qcom,smem-states = <&smp2p_cdsp_out 0>; 3553 qcom,smem-state-names = "stop"; 3554 3555 status = "disabled"; 3556 3557 glink-edge { 3558 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3559 IPCC_MPROC_SIGNAL_GLINK_QMP 3560 IRQ_TYPE_EDGE_RISING>; 3561 mboxes = <&ipcc IPCC_CLIENT_CDSP 3562 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3563 3564 label = "cdsp"; 3565 qcom,remote-pid = <5>; 3566 3567 fastrpc { 3568 compatible = "qcom,fastrpc"; 3569 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3570 label = "cdsp"; 3571 #address-cells = <1>; 3572 #size-cells = <0>; 3573 3574 compute-cb@1 { 3575 compatible = "qcom,fastrpc-compute-cb"; 3576 reg = <1>; 3577 iommus = <&apps_smmu 0x1961 0x0>, 3578 <&apps_smmu 0x0c01 0x20>, 3579 <&apps_smmu 0x19c1 0x10>; 3580 }; 3581 3582 compute-cb@2 { 3583 compatible = "qcom,fastrpc-compute-cb"; 3584 reg = <2>; 3585 iommus = <&apps_smmu 0x1962 0x0>, 3586 <&apps_smmu 0x0c02 0x20>, 3587 <&apps_smmu 0x19c2 0x10>; 3588 }; 3589 3590 compute-cb@3 { 3591 compatible = "qcom,fastrpc-compute-cb"; 3592 reg = <3>; 3593 iommus = <&apps_smmu 0x1963 0x0>, 3594 <&apps_smmu 0x0c03 0x20>, 3595 <&apps_smmu 0x19c3 0x10>; 3596 }; 3597 3598 compute-cb@4 { 3599 compatible = "qcom,fastrpc-compute-cb"; 3600 reg = <4>; 3601 iommus = <&apps_smmu 0x1964 0x0>, 3602 <&apps_smmu 0x0c04 0x20>, 3603 <&apps_smmu 0x19c4 0x10>; 3604 }; 3605 3606 compute-cb@5 { 3607 compatible = "qcom,fastrpc-compute-cb"; 3608 reg = <5>; 3609 iommus = <&apps_smmu 0x1965 0x0>, 3610 <&apps_smmu 0x0c05 0x20>, 3611 <&apps_smmu 0x19c5 0x10>; 3612 }; 3613 3614 compute-cb@6 { 3615 compatible = "qcom,fastrpc-compute-cb"; 3616 reg = <6>; 3617 iommus = <&apps_smmu 0x1966 0x0>, 3618 <&apps_smmu 0x0c06 0x20>, 3619 <&apps_smmu 0x19c6 0x10>; 3620 }; 3621 3622 compute-cb@7 { 3623 compatible = "qcom,fastrpc-compute-cb"; 3624 reg = <7>; 3625 iommus = <&apps_smmu 0x1967 0x0>, 3626 <&apps_smmu 0x0c07 0x20>, 3627 <&apps_smmu 0x19c7 0x10>; 3628 }; 3629 3630 compute-cb@8 { 3631 compatible = "qcom,fastrpc-compute-cb"; 3632 reg = <8>; 3633 iommus = <&apps_smmu 0x1968 0x0>, 3634 <&apps_smmu 0x0c08 0x20>, 3635 <&apps_smmu 0x19c8 0x10>; 3636 }; 3637 3638 /* note: secure cb9 in downstream */ 3639 }; 3640 }; 3641 }; 3642 }; 3643 3644 thermal-zones { 3645 aoss0-thermal { 3646 polling-delay-passive = <0>; 3647 polling-delay = <0>; 3648 thermal-sensors = <&tsens0 0>; 3649 3650 trips { 3651 thermal-engine-config { 3652 temperature = <125000>; 3653 hysteresis = <1000>; 3654 type = "passive"; 3655 }; 3656 3657 reset-mon-config { 3658 temperature = <115000>; 3659 hysteresis = <5000>; 3660 type = "passive"; 3661 }; 3662 }; 3663 }; 3664 3665 cpuss0-thermal { 3666 polling-delay-passive = <0>; 3667 polling-delay = <0>; 3668 thermal-sensors = <&tsens0 1>; 3669 3670 trips { 3671 thermal-engine-config { 3672 temperature = <125000>; 3673 hysteresis = <1000>; 3674 type = "passive"; 3675 }; 3676 3677 reset-mon-config { 3678 temperature = <115000>; 3679 hysteresis = <5000>; 3680 type = "passive"; 3681 }; 3682 }; 3683 }; 3684 3685 cpuss1-thermal { 3686 polling-delay-passive = <0>; 3687 polling-delay = <0>; 3688 thermal-sensors = <&tsens0 2>; 3689 3690 trips { 3691 thermal-engine-config { 3692 temperature = <125000>; 3693 hysteresis = <1000>; 3694 type = "passive"; 3695 }; 3696 3697 reset-mon-config { 3698 temperature = <115000>; 3699 hysteresis = <5000>; 3700 type = "passive"; 3701 }; 3702 }; 3703 }; 3704 3705 cpuss2-thermal { 3706 polling-delay-passive = <0>; 3707 polling-delay = <0>; 3708 thermal-sensors = <&tsens0 3>; 3709 3710 trips { 3711 thermal-engine-config { 3712 temperature = <125000>; 3713 hysteresis = <1000>; 3714 type = "passive"; 3715 }; 3716 3717 reset-mon-config { 3718 temperature = <115000>; 3719 hysteresis = <5000>; 3720 type = "passive"; 3721 }; 3722 }; 3723 }; 3724 3725 cpuss3-thermal { 3726 polling-delay-passive = <0>; 3727 polling-delay = <0>; 3728 thermal-sensors = <&tsens0 4>; 3729 3730 trips { 3731 thermal-engine-config { 3732 temperature = <125000>; 3733 hysteresis = <1000>; 3734 type = "passive"; 3735 }; 3736 3737 reset-mon-config { 3738 temperature = <115000>; 3739 hysteresis = <5000>; 3740 type = "passive"; 3741 }; 3742 }; 3743 }; 3744 3745 cpu3-top-thermal { 3746 polling-delay-passive = <0>; 3747 polling-delay = <0>; 3748 thermal-sensors = <&tsens0 5>; 3749 3750 trips { 3751 cpu3_top_alert0: trip-point0 { 3752 temperature = <90000>; 3753 hysteresis = <2000>; 3754 type = "passive"; 3755 }; 3756 3757 cpu3_top_alert1: trip-point1 { 3758 temperature = <95000>; 3759 hysteresis = <2000>; 3760 type = "passive"; 3761 }; 3762 3763 cpu3_top_crit: cpu-critical { 3764 temperature = <110000>; 3765 hysteresis = <1000>; 3766 type = "critical"; 3767 }; 3768 }; 3769 }; 3770 3771 cpu3-bottom-thermal { 3772 polling-delay-passive = <0>; 3773 polling-delay = <0>; 3774 thermal-sensors = <&tsens0 6>; 3775 3776 trips { 3777 cpu3_bottom_alert0: trip-point0 { 3778 temperature = <90000>; 3779 hysteresis = <2000>; 3780 type = "passive"; 3781 }; 3782 3783 cpu3_bottom_alert1: trip-point1 { 3784 temperature = <95000>; 3785 hysteresis = <2000>; 3786 type = "passive"; 3787 }; 3788 3789 cpu3_bottom_crit: cpu-critical { 3790 temperature = <110000>; 3791 hysteresis = <1000>; 3792 type = "critical"; 3793 }; 3794 }; 3795 }; 3796 3797 cpu4-top-thermal { 3798 polling-delay-passive = <0>; 3799 polling-delay = <0>; 3800 thermal-sensors = <&tsens0 7>; 3801 3802 trips { 3803 cpu4_top_alert0: trip-point0 { 3804 temperature = <90000>; 3805 hysteresis = <2000>; 3806 type = "passive"; 3807 }; 3808 3809 cpu4_top_alert1: trip-point1 { 3810 temperature = <95000>; 3811 hysteresis = <2000>; 3812 type = "passive"; 3813 }; 3814 3815 cpu4_top_crit: cpu-critical { 3816 temperature = <110000>; 3817 hysteresis = <1000>; 3818 type = "critical"; 3819 }; 3820 }; 3821 }; 3822 3823 cpu4-bottom-thermal { 3824 polling-delay-passive = <0>; 3825 polling-delay = <0>; 3826 thermal-sensors = <&tsens0 8>; 3827 3828 trips { 3829 cpu4_bottom_alert0: trip-point0 { 3830 temperature = <90000>; 3831 hysteresis = <2000>; 3832 type = "passive"; 3833 }; 3834 3835 cpu4_bottom_alert1: trip-point1 { 3836 temperature = <95000>; 3837 hysteresis = <2000>; 3838 type = "passive"; 3839 }; 3840 3841 cpu4_bottom_crit: cpu-critical { 3842 temperature = <110000>; 3843 hysteresis = <1000>; 3844 type = "critical"; 3845 }; 3846 }; 3847 }; 3848 3849 cpu5-top-thermal { 3850 polling-delay-passive = <0>; 3851 polling-delay = <0>; 3852 thermal-sensors = <&tsens0 9>; 3853 3854 trips { 3855 cpu5_top_alert0: trip-point0 { 3856 temperature = <90000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 cpu5_top_alert1: trip-point1 { 3862 temperature = <95000>; 3863 hysteresis = <2000>; 3864 type = "passive"; 3865 }; 3866 3867 cpu5_top_crit: cpu-critical { 3868 temperature = <110000>; 3869 hysteresis = <1000>; 3870 type = "critical"; 3871 }; 3872 }; 3873 }; 3874 3875 cpu5-bottom-thermal { 3876 polling-delay-passive = <0>; 3877 polling-delay = <0>; 3878 thermal-sensors = <&tsens0 10>; 3879 3880 trips { 3881 cpu5_bottom_alert0: trip-point0 { 3882 temperature = <90000>; 3883 hysteresis = <2000>; 3884 type = "passive"; 3885 }; 3886 3887 cpu5_bottom_alert1: trip-point1 { 3888 temperature = <95000>; 3889 hysteresis = <2000>; 3890 type = "passive"; 3891 }; 3892 3893 cpu5_bottom_crit: cpu-critical { 3894 temperature = <110000>; 3895 hysteresis = <1000>; 3896 type = "critical"; 3897 }; 3898 }; 3899 }; 3900 3901 cpu6-top-thermal { 3902 polling-delay-passive = <0>; 3903 polling-delay = <0>; 3904 thermal-sensors = <&tsens0 11>; 3905 3906 trips { 3907 cpu6_top_alert0: trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu6_top_alert1: trip-point1 { 3914 temperature = <95000>; 3915 hysteresis = <2000>; 3916 type = "passive"; 3917 }; 3918 3919 cpu6_top_crit: cpu-critical { 3920 temperature = <110000>; 3921 hysteresis = <1000>; 3922 type = "critical"; 3923 }; 3924 }; 3925 }; 3926 3927 cpu6-bottom-thermal { 3928 polling-delay-passive = <0>; 3929 polling-delay = <0>; 3930 thermal-sensors = <&tsens0 12>; 3931 3932 trips { 3933 cpu6_bottom_alert0: trip-point0 { 3934 temperature = <90000>; 3935 hysteresis = <2000>; 3936 type = "passive"; 3937 }; 3938 3939 cpu6_bottom_alert1: trip-point1 { 3940 temperature = <95000>; 3941 hysteresis = <2000>; 3942 type = "passive"; 3943 }; 3944 3945 cpu6_bottom_crit: cpu-critical { 3946 temperature = <110000>; 3947 hysteresis = <1000>; 3948 type = "critical"; 3949 }; 3950 }; 3951 }; 3952 3953 cpu7-top-thermal { 3954 polling-delay-passive = <0>; 3955 polling-delay = <0>; 3956 thermal-sensors = <&tsens0 13>; 3957 3958 trips { 3959 cpu7_top_alert0: trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "passive"; 3963 }; 3964 3965 cpu7_top_alert1: trip-point1 { 3966 temperature = <95000>; 3967 hysteresis = <2000>; 3968 type = "passive"; 3969 }; 3970 3971 cpu7_top_crit: cpu-critical { 3972 temperature = <110000>; 3973 hysteresis = <1000>; 3974 type = "critical"; 3975 }; 3976 }; 3977 }; 3978 3979 cpu7-middle-thermal { 3980 polling-delay-passive = <0>; 3981 polling-delay = <0>; 3982 thermal-sensors = <&tsens0 14>; 3983 3984 trips { 3985 cpu7_middle_alert0: trip-point0 { 3986 temperature = <90000>; 3987 hysteresis = <2000>; 3988 type = "passive"; 3989 }; 3990 3991 cpu7_middle_alert1: trip-point1 { 3992 temperature = <95000>; 3993 hysteresis = <2000>; 3994 type = "passive"; 3995 }; 3996 3997 cpu7_middle_crit: cpu-critical { 3998 temperature = <110000>; 3999 hysteresis = <1000>; 4000 type = "critical"; 4001 }; 4002 }; 4003 }; 4004 4005 cpu7-bottom-thermal { 4006 polling-delay-passive = <0>; 4007 polling-delay = <0>; 4008 thermal-sensors = <&tsens0 15>; 4009 4010 trips { 4011 cpu7_bottom_alert0: trip-point0 { 4012 temperature = <90000>; 4013 hysteresis = <2000>; 4014 type = "passive"; 4015 }; 4016 4017 cpu7_bottom_alert1: trip-point1 { 4018 temperature = <95000>; 4019 hysteresis = <2000>; 4020 type = "passive"; 4021 }; 4022 4023 cpu7_bottom_crit: cpu-critical { 4024 temperature = <110000>; 4025 hysteresis = <1000>; 4026 type = "critical"; 4027 }; 4028 }; 4029 }; 4030 4031 aoss1-thermal { 4032 polling-delay-passive = <0>; 4033 polling-delay = <0>; 4034 thermal-sensors = <&tsens1 0>; 4035 4036 trips { 4037 thermal-engine-config { 4038 temperature = <125000>; 4039 hysteresis = <1000>; 4040 type = "passive"; 4041 }; 4042 4043 reset-mon-config { 4044 temperature = <115000>; 4045 hysteresis = <5000>; 4046 type = "passive"; 4047 }; 4048 }; 4049 }; 4050 4051 cpu0-thermal { 4052 polling-delay-passive = <0>; 4053 polling-delay = <0>; 4054 thermal-sensors = <&tsens1 1>; 4055 4056 trips { 4057 cpu0_alert0: trip-point0 { 4058 temperature = <90000>; 4059 hysteresis = <2000>; 4060 type = "passive"; 4061 }; 4062 4063 cpu0_alert1: trip-point1 { 4064 temperature = <95000>; 4065 hysteresis = <2000>; 4066 type = "passive"; 4067 }; 4068 4069 cpu0_crit: cpu-critical { 4070 temperature = <110000>; 4071 hysteresis = <1000>; 4072 type = "critical"; 4073 }; 4074 }; 4075 }; 4076 4077 cpu1-thermal { 4078 polling-delay-passive = <0>; 4079 polling-delay = <0>; 4080 thermal-sensors = <&tsens1 2>; 4081 4082 trips { 4083 cpu1_alert0: trip-point0 { 4084 temperature = <90000>; 4085 hysteresis = <2000>; 4086 type = "passive"; 4087 }; 4088 4089 cpu1_alert1: trip-point1 { 4090 temperature = <95000>; 4091 hysteresis = <2000>; 4092 type = "passive"; 4093 }; 4094 4095 cpu1_crit: cpu-critical { 4096 temperature = <110000>; 4097 hysteresis = <1000>; 4098 type = "critical"; 4099 }; 4100 }; 4101 }; 4102 4103 cpu2-thermal { 4104 polling-delay-passive = <0>; 4105 polling-delay = <0>; 4106 thermal-sensors = <&tsens1 3>; 4107 4108 trips { 4109 cpu2_alert0: trip-point0 { 4110 temperature = <90000>; 4111 hysteresis = <2000>; 4112 type = "passive"; 4113 }; 4114 4115 cpu2_alert1: trip-point1 { 4116 temperature = <95000>; 4117 hysteresis = <2000>; 4118 type = "passive"; 4119 }; 4120 4121 cpu2_crit: cpu-critical { 4122 temperature = <110000>; 4123 hysteresis = <1000>; 4124 type = "critical"; 4125 }; 4126 }; 4127 }; 4128 4129 cdsp0-thermal { 4130 polling-delay-passive = <10>; 4131 polling-delay = <0>; 4132 thermal-sensors = <&tsens2 4>; 4133 4134 trips { 4135 thermal-engine-config { 4136 temperature = <125000>; 4137 hysteresis = <1000>; 4138 type = "passive"; 4139 }; 4140 4141 thermal-hal-config { 4142 temperature = <125000>; 4143 hysteresis = <1000>; 4144 type = "passive"; 4145 }; 4146 4147 reset-mon-config { 4148 temperature = <115000>; 4149 hysteresis = <5000>; 4150 type = "passive"; 4151 }; 4152 4153 cdsp0_junction_config: junction-config { 4154 temperature = <95000>; 4155 hysteresis = <5000>; 4156 type = "passive"; 4157 }; 4158 }; 4159 }; 4160 4161 cdsp1-thermal { 4162 polling-delay-passive = <10>; 4163 polling-delay = <0>; 4164 thermal-sensors = <&tsens2 5>; 4165 4166 trips { 4167 thermal-engine-config { 4168 temperature = <125000>; 4169 hysteresis = <1000>; 4170 type = "passive"; 4171 }; 4172 4173 thermal-hal-config { 4174 temperature = <125000>; 4175 hysteresis = <1000>; 4176 type = "passive"; 4177 }; 4178 4179 reset-mon-config { 4180 temperature = <115000>; 4181 hysteresis = <5000>; 4182 type = "passive"; 4183 }; 4184 4185 cdsp1_junction_config: junction-config { 4186 temperature = <95000>; 4187 hysteresis = <5000>; 4188 type = "passive"; 4189 }; 4190 }; 4191 }; 4192 4193 cdsp2-thermal { 4194 polling-delay-passive = <10>; 4195 polling-delay = <0>; 4196 thermal-sensors = <&tsens2 6>; 4197 4198 trips { 4199 thermal-engine-config { 4200 temperature = <125000>; 4201 hysteresis = <1000>; 4202 type = "passive"; 4203 }; 4204 4205 thermal-hal-config { 4206 temperature = <125000>; 4207 hysteresis = <1000>; 4208 type = "passive"; 4209 }; 4210 4211 reset-mon-config { 4212 temperature = <115000>; 4213 hysteresis = <5000>; 4214 type = "passive"; 4215 }; 4216 4217 cdsp2_junction_config: junction-config { 4218 temperature = <95000>; 4219 hysteresis = <5000>; 4220 type = "passive"; 4221 }; 4222 }; 4223 }; 4224 4225 cdsp3-thermal { 4226 polling-delay-passive = <10>; 4227 polling-delay = <0>; 4228 thermal-sensors = <&tsens2 7>; 4229 4230 trips { 4231 thermal-engine-config { 4232 temperature = <125000>; 4233 hysteresis = <1000>; 4234 type = "passive"; 4235 }; 4236 4237 thermal-hal-config { 4238 temperature = <125000>; 4239 hysteresis = <1000>; 4240 type = "passive"; 4241 }; 4242 4243 reset-mon-config { 4244 temperature = <115000>; 4245 hysteresis = <5000>; 4246 type = "passive"; 4247 }; 4248 4249 cdsp3_junction_config: junction-config { 4250 temperature = <95000>; 4251 hysteresis = <5000>; 4252 type = "passive"; 4253 }; 4254 }; 4255 }; 4256 4257 video-thermal { 4258 polling-delay-passive = <0>; 4259 polling-delay = <0>; 4260 thermal-sensors = <&tsens1 8>; 4261 4262 trips { 4263 thermal-engine-config { 4264 temperature = <125000>; 4265 hysteresis = <1000>; 4266 type = "passive"; 4267 }; 4268 4269 reset-mon-config { 4270 temperature = <115000>; 4271 hysteresis = <5000>; 4272 type = "passive"; 4273 }; 4274 }; 4275 }; 4276 4277 mem-thermal { 4278 polling-delay-passive = <10>; 4279 polling-delay = <0>; 4280 thermal-sensors = <&tsens1 9>; 4281 4282 trips { 4283 thermal-engine-config { 4284 temperature = <125000>; 4285 hysteresis = <1000>; 4286 type = "passive"; 4287 }; 4288 4289 ddr_config0: ddr0-config { 4290 temperature = <90000>; 4291 hysteresis = <5000>; 4292 type = "passive"; 4293 }; 4294 4295 reset-mon-config { 4296 temperature = <115000>; 4297 hysteresis = <5000>; 4298 type = "passive"; 4299 }; 4300 }; 4301 }; 4302 4303 modem0-thermal { 4304 polling-delay-passive = <0>; 4305 polling-delay = <0>; 4306 thermal-sensors = <&tsens1 10>; 4307 4308 trips { 4309 thermal-engine-config { 4310 temperature = <125000>; 4311 hysteresis = <1000>; 4312 type = "passive"; 4313 }; 4314 4315 mdmss0_config0: mdmss0-config0 { 4316 temperature = <102000>; 4317 hysteresis = <3000>; 4318 type = "passive"; 4319 }; 4320 4321 mdmss0_config1: mdmss0-config1 { 4322 temperature = <105000>; 4323 hysteresis = <3000>; 4324 type = "passive"; 4325 }; 4326 4327 reset-mon-config { 4328 temperature = <115000>; 4329 hysteresis = <5000>; 4330 type = "passive"; 4331 }; 4332 }; 4333 }; 4334 4335 modem1-thermal { 4336 polling-delay-passive = <0>; 4337 polling-delay = <0>; 4338 thermal-sensors = <&tsens1 11>; 4339 4340 trips { 4341 thermal-engine-config { 4342 temperature = <125000>; 4343 hysteresis = <1000>; 4344 type = "passive"; 4345 }; 4346 4347 mdmss1_config0: mdmss1-config0 { 4348 temperature = <102000>; 4349 hysteresis = <3000>; 4350 type = "passive"; 4351 }; 4352 4353 mdmss1_config1: mdmss1-config1 { 4354 temperature = <105000>; 4355 hysteresis = <3000>; 4356 type = "passive"; 4357 }; 4358 4359 reset-mon-config { 4360 temperature = <115000>; 4361 hysteresis = <5000>; 4362 type = "passive"; 4363 }; 4364 }; 4365 }; 4366 4367 modem2-thermal { 4368 polling-delay-passive = <0>; 4369 polling-delay = <0>; 4370 thermal-sensors = <&tsens1 12>; 4371 4372 trips { 4373 thermal-engine-config { 4374 temperature = <125000>; 4375 hysteresis = <1000>; 4376 type = "passive"; 4377 }; 4378 4379 mdmss2_config0: mdmss2-config0 { 4380 temperature = <102000>; 4381 hysteresis = <3000>; 4382 type = "passive"; 4383 }; 4384 4385 mdmss2_config1: mdmss2-config1 { 4386 temperature = <105000>; 4387 hysteresis = <3000>; 4388 type = "passive"; 4389 }; 4390 4391 reset-mon-config { 4392 temperature = <115000>; 4393 hysteresis = <5000>; 4394 type = "passive"; 4395 }; 4396 }; 4397 }; 4398 4399 modem3-thermal { 4400 polling-delay-passive = <0>; 4401 polling-delay = <0>; 4402 thermal-sensors = <&tsens1 13>; 4403 4404 trips { 4405 thermal-engine-config { 4406 temperature = <125000>; 4407 hysteresis = <1000>; 4408 type = "passive"; 4409 }; 4410 4411 mdmss3_config0: mdmss3-config0 { 4412 temperature = <102000>; 4413 hysteresis = <3000>; 4414 type = "passive"; 4415 }; 4416 4417 mdmss3_config1: mdmss3-config1 { 4418 temperature = <105000>; 4419 hysteresis = <3000>; 4420 type = "passive"; 4421 }; 4422 4423 reset-mon-config { 4424 temperature = <115000>; 4425 hysteresis = <5000>; 4426 type = "passive"; 4427 }; 4428 }; 4429 }; 4430 4431 camera0-thermal { 4432 polling-delay-passive = <0>; 4433 polling-delay = <0>; 4434 thermal-sensors = <&tsens1 14>; 4435 4436 trips { 4437 thermal-engine-config { 4438 temperature = <125000>; 4439 hysteresis = <1000>; 4440 type = "passive"; 4441 }; 4442 4443 reset-mon-config { 4444 temperature = <115000>; 4445 hysteresis = <5000>; 4446 type = "passive"; 4447 }; 4448 }; 4449 }; 4450 4451 camera1-thermal { 4452 polling-delay-passive = <0>; 4453 polling-delay = <0>; 4454 thermal-sensors = <&tsens1 15>; 4455 4456 trips { 4457 thermal-engine-config { 4458 temperature = <125000>; 4459 hysteresis = <1000>; 4460 type = "passive"; 4461 }; 4462 4463 reset-mon-config { 4464 temperature = <115000>; 4465 hysteresis = <5000>; 4466 type = "passive"; 4467 }; 4468 }; 4469 }; 4470 4471 aoss2-thermal { 4472 polling-delay-passive = <0>; 4473 polling-delay = <0>; 4474 thermal-sensors = <&tsens2 0>; 4475 4476 trips { 4477 thermal-engine-config { 4478 temperature = <125000>; 4479 hysteresis = <1000>; 4480 type = "passive"; 4481 }; 4482 4483 reset-mon-config { 4484 temperature = <115000>; 4485 hysteresis = <5000>; 4486 type = "passive"; 4487 }; 4488 }; 4489 }; 4490 4491 gpuss-0-thermal { 4492 polling-delay-passive = <10>; 4493 polling-delay = <0>; 4494 thermal-sensors = <&tsens2 1>; 4495 4496 trips { 4497 thermal-engine-config { 4498 temperature = <125000>; 4499 hysteresis = <1000>; 4500 type = "passive"; 4501 }; 4502 4503 thermal-hal-config { 4504 temperature = <125000>; 4505 hysteresis = <1000>; 4506 type = "passive"; 4507 }; 4508 4509 reset-mon-config { 4510 temperature = <115000>; 4511 hysteresis = <5000>; 4512 type = "passive"; 4513 }; 4514 4515 gpu0_junction_config: junction-config { 4516 temperature = <95000>; 4517 hysteresis = <5000>; 4518 type = "passive"; 4519 }; 4520 }; 4521 }; 4522 4523 gpuss-1-thermal { 4524 polling-delay-passive = <10>; 4525 polling-delay = <0>; 4526 thermal-sensors = <&tsens2 2>; 4527 4528 trips { 4529 thermal-engine-config { 4530 temperature = <125000>; 4531 hysteresis = <1000>; 4532 type = "passive"; 4533 }; 4534 4535 thermal-hal-config { 4536 temperature = <125000>; 4537 hysteresis = <1000>; 4538 type = "passive"; 4539 }; 4540 4541 reset-mon-config { 4542 temperature = <115000>; 4543 hysteresis = <5000>; 4544 type = "passive"; 4545 }; 4546 4547 gpu1_junction_config: junction-config { 4548 temperature = <95000>; 4549 hysteresis = <5000>; 4550 type = "passive"; 4551 }; 4552 }; 4553 }; 4554 4555 gpuss-2-thermal { 4556 polling-delay-passive = <10>; 4557 polling-delay = <0>; 4558 thermal-sensors = <&tsens2 3>; 4559 4560 trips { 4561 thermal-engine-config { 4562 temperature = <125000>; 4563 hysteresis = <1000>; 4564 type = "passive"; 4565 }; 4566 4567 thermal-hal-config { 4568 temperature = <125000>; 4569 hysteresis = <1000>; 4570 type = "passive"; 4571 }; 4572 4573 reset-mon-config { 4574 temperature = <115000>; 4575 hysteresis = <5000>; 4576 type = "passive"; 4577 }; 4578 4579 gpu2_junction_config: junction-config { 4580 temperature = <95000>; 4581 hysteresis = <5000>; 4582 type = "passive"; 4583 }; 4584 }; 4585 }; 4586 4587 gpuss-3-thermal { 4588 polling-delay-passive = <10>; 4589 polling-delay = <0>; 4590 thermal-sensors = <&tsens2 4>; 4591 4592 trips { 4593 thermal-engine-config { 4594 temperature = <125000>; 4595 hysteresis = <1000>; 4596 type = "passive"; 4597 }; 4598 4599 thermal-hal-config { 4600 temperature = <125000>; 4601 hysteresis = <1000>; 4602 type = "passive"; 4603 }; 4604 4605 reset-mon-config { 4606 temperature = <115000>; 4607 hysteresis = <5000>; 4608 type = "passive"; 4609 }; 4610 4611 gpu3_junction_config: junction-config { 4612 temperature = <95000>; 4613 hysteresis = <5000>; 4614 type = "passive"; 4615 }; 4616 }; 4617 }; 4618 4619 gpuss-4-thermal { 4620 polling-delay-passive = <10>; 4621 polling-delay = <0>; 4622 thermal-sensors = <&tsens2 5>; 4623 4624 trips { 4625 thermal-engine-config { 4626 temperature = <125000>; 4627 hysteresis = <1000>; 4628 type = "passive"; 4629 }; 4630 4631 thermal-hal-config { 4632 temperature = <125000>; 4633 hysteresis = <1000>; 4634 type = "passive"; 4635 }; 4636 4637 reset-mon-config { 4638 temperature = <115000>; 4639 hysteresis = <5000>; 4640 type = "passive"; 4641 }; 4642 4643 gpu4_junction_config: junction-config { 4644 temperature = <95000>; 4645 hysteresis = <5000>; 4646 type = "passive"; 4647 }; 4648 }; 4649 }; 4650 4651 gpuss-5-thermal { 4652 polling-delay-passive = <10>; 4653 polling-delay = <0>; 4654 thermal-sensors = <&tsens2 6>; 4655 4656 trips { 4657 thermal-engine-config { 4658 temperature = <125000>; 4659 hysteresis = <1000>; 4660 type = "passive"; 4661 }; 4662 4663 thermal-hal-config { 4664 temperature = <125000>; 4665 hysteresis = <1000>; 4666 type = "passive"; 4667 }; 4668 4669 reset-mon-config { 4670 temperature = <115000>; 4671 hysteresis = <5000>; 4672 type = "passive"; 4673 }; 4674 4675 gpu5_junction_config: junction-config { 4676 temperature = <95000>; 4677 hysteresis = <5000>; 4678 type = "passive"; 4679 }; 4680 }; 4681 }; 4682 4683 gpuss-6-thermal { 4684 polling-delay-passive = <10>; 4685 polling-delay = <0>; 4686 thermal-sensors = <&tsens2 7>; 4687 4688 trips { 4689 thermal-engine-config { 4690 temperature = <125000>; 4691 hysteresis = <1000>; 4692 type = "passive"; 4693 }; 4694 4695 thermal-hal-config { 4696 temperature = <125000>; 4697 hysteresis = <1000>; 4698 type = "passive"; 4699 }; 4700 4701 reset-mon-config { 4702 temperature = <115000>; 4703 hysteresis = <5000>; 4704 type = "passive"; 4705 }; 4706 4707 gpu6_junction_config: junction-config { 4708 temperature = <95000>; 4709 hysteresis = <5000>; 4710 type = "passive"; 4711 }; 4712 }; 4713 }; 4714 4715 gpuss-7-thermal { 4716 polling-delay-passive = <10>; 4717 polling-delay = <0>; 4718 thermal-sensors = <&tsens2 8>; 4719 4720 trips { 4721 thermal-engine-config { 4722 temperature = <125000>; 4723 hysteresis = <1000>; 4724 type = "passive"; 4725 }; 4726 4727 thermal-hal-config { 4728 temperature = <125000>; 4729 hysteresis = <1000>; 4730 type = "passive"; 4731 }; 4732 4733 reset-mon-config { 4734 temperature = <115000>; 4735 hysteresis = <5000>; 4736 type = "passive"; 4737 }; 4738 4739 gpu7_junction_config: junction-config { 4740 temperature = <95000>; 4741 hysteresis = <5000>; 4742 type = "passive"; 4743 }; 4744 }; 4745 }; 4746 }; 4747 4748 timer { 4749 compatible = "arm,armv8-timer"; 4750 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4751 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4752 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4753 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4754 }; 4755}; 4756