1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8550-gcc.h> 8#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 9#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 bi_tcxo_div2: bi-tcxo-div2-clk { 42 #clock-cells = <0>; 43 compatible = "fixed-factor-clock"; 44 clocks = <&rpmhcc RPMH_CXO_CLK>; 45 clock-mult = <1>; 46 clock-div = <2>; 47 }; 48 49 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 50 #clock-cells = <0>; 51 compatible = "fixed-factor-clock"; 52 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 53 clock-mult = <1>; 54 clock-div = <2>; 55 }; 56 57 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 cpus { 64 #address-cells = <2>; 65 #size-cells = <0>; 66 67 CPU0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a510"; 70 reg = <0 0>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_0>; 73 power-domains = <&CPU_PD0>; 74 power-domain-names = "psci"; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 capacity-dmips-mhz = <1024>; 77 dynamic-power-coefficient = <100>; 78 #cooling-cells = <2>; 79 L2_0: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 next-level-cache = <&L3_0>; 83 L3_0: l3-cache { 84 compatible = "cache"; 85 cache-level = <3>; 86 }; 87 }; 88 }; 89 90 CPU1: cpu@100 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a510"; 93 reg = <0 0x100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_100>; 96 power-domains = <&CPU_PD1>; 97 power-domain-names = "psci"; 98 qcom,freq-domain = <&cpufreq_hw 0>; 99 capacity-dmips-mhz = <1024>; 100 dynamic-power-coefficient = <100>; 101 #cooling-cells = <2>; 102 L2_100: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU2: cpu@200 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a510"; 112 reg = <0 0x200>; 113 enable-method = "psci"; 114 next-level-cache = <&L2_200>; 115 power-domains = <&CPU_PD2>; 116 power-domain-names = "psci"; 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 capacity-dmips-mhz = <1024>; 119 dynamic-power-coefficient = <100>; 120 #cooling-cells = <2>; 121 L2_200: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a715"; 131 reg = <0 0x300>; 132 enable-method = "psci"; 133 next-level-cache = <&L2_300>; 134 power-domains = <&CPU_PD3>; 135 power-domain-names = "psci"; 136 qcom,freq-domain = <&cpufreq_hw 1>; 137 capacity-dmips-mhz = <1792>; 138 dynamic-power-coefficient = <270>; 139 #cooling-cells = <2>; 140 L2_300: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 CPU4: cpu@400 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a715"; 150 reg = <0 0x400>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_400>; 153 power-domains = <&CPU_PD4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 capacity-dmips-mhz = <1792>; 157 dynamic-power-coefficient = <270>; 158 #cooling-cells = <2>; 159 L2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a710"; 169 reg = <0 0x500>; 170 enable-method = "psci"; 171 next-level-cache = <&L2_500>; 172 power-domains = <&CPU_PD5>; 173 power-domain-names = "psci"; 174 qcom,freq-domain = <&cpufreq_hw 1>; 175 capacity-dmips-mhz = <1792>; 176 dynamic-power-coefficient = <270>; 177 #cooling-cells = <2>; 178 L2_500: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 next-level-cache = <&L3_0>; 182 }; 183 }; 184 185 CPU6: cpu@600 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a710"; 188 reg = <0 0x600>; 189 enable-method = "psci"; 190 next-level-cache = <&L2_600>; 191 power-domains = <&CPU_PD6>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 capacity-dmips-mhz = <1792>; 195 dynamic-power-coefficient = <270>; 196 #cooling-cells = <2>; 197 L2_600: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 CPU7: cpu@700 { 205 device_type = "cpu"; 206 compatible = "arm,cortex-x3"; 207 reg = <0 0x700>; 208 enable-method = "psci"; 209 next-level-cache = <&L2_700>; 210 power-domains = <&CPU_PD7>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 2>; 213 capacity-dmips-mhz = <1894>; 214 dynamic-power-coefficient = <588>; 215 #cooling-cells = <2>; 216 L2_700: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 cpu-map { 224 cluster0 { 225 core0 { 226 cpu = <&CPU0>; 227 }; 228 229 core1 { 230 cpu = <&CPU1>; 231 }; 232 233 core2 { 234 cpu = <&CPU2>; 235 }; 236 237 core3 { 238 cpu = <&CPU3>; 239 }; 240 241 core4 { 242 cpu = <&CPU4>; 243 }; 244 245 core5 { 246 cpu = <&CPU5>; 247 }; 248 249 core6 { 250 cpu = <&CPU6>; 251 }; 252 253 core7 { 254 cpu = <&CPU7>; 255 }; 256 }; 257 }; 258 259 idle-states { 260 entry-method = "psci"; 261 262 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 263 compatible = "arm,idle-state"; 264 idle-state-name = "silver-rail-power-collapse"; 265 arm,psci-suspend-param = <0x40000004>; 266 entry-latency-us = <800>; 267 exit-latency-us = <750>; 268 min-residency-us = <4090>; 269 local-timer-stop; 270 }; 271 272 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 273 compatible = "arm,idle-state"; 274 idle-state-name = "gold-rail-power-collapse"; 275 arm,psci-suspend-param = <0x40000004>; 276 entry-latency-us = <600>; 277 exit-latency-us = <1550>; 278 min-residency-us = <4791>; 279 local-timer-stop; 280 }; 281 }; 282 283 domain-idle-states { 284 CLUSTER_SLEEP_0: cluster-sleep-0 { 285 compatible = "domain-idle-state"; 286 arm,psci-suspend-param = <0x41000044>; 287 entry-latency-us = <1050>; 288 exit-latency-us = <2500>; 289 min-residency-us = <5309>; 290 }; 291 292 CLUSTER_SLEEP_1: cluster-sleep-1 { 293 compatible = "domain-idle-state"; 294 arm,psci-suspend-param = <0x4100c344>; 295 entry-latency-us = <2700>; 296 exit-latency-us = <3500>; 297 min-residency-us = <13959>; 298 }; 299 }; 300 }; 301 302 firmware { 303 scm: scm { 304 compatible = "qcom,scm-sm8550", "qcom,scm"; 305 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 306 }; 307 }; 308 309 clk_virt: interconnect-0 { 310 compatible = "qcom,sm8550-clk-virt"; 311 #interconnect-cells = <2>; 312 qcom,bcm-voters = <&apps_bcm_voter>; 313 }; 314 315 mc_virt: interconnect-1 { 316 compatible = "qcom,sm8550-mc-virt"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 memory@a0000000 { 322 device_type = "memory"; 323 /* We expect the bootloader to fill in the size */ 324 reg = <0 0xa0000000 0 0>; 325 }; 326 327 pmu { 328 compatible = "arm,armv8-pmuv3"; 329 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 330 }; 331 332 psci { 333 compatible = "arm,psci-1.0"; 334 method = "smc"; 335 336 CPU_PD0: power-domain-cpu0 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 340 }; 341 342 CPU_PD1: power-domain-cpu1 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 346 }; 347 348 CPU_PD2: power-domain-cpu2 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 352 }; 353 354 CPU_PD3: power-domain-cpu3 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0>; 358 }; 359 360 CPU_PD4: power-domain-cpu4 { 361 #power-domain-cells = <0>; 362 power-domains = <&CLUSTER_PD>; 363 domain-idle-states = <&BIG_CPU_SLEEP_0>; 364 }; 365 366 CPU_PD5: power-domain-cpu5 { 367 #power-domain-cells = <0>; 368 power-domains = <&CLUSTER_PD>; 369 domain-idle-states = <&BIG_CPU_SLEEP_0>; 370 }; 371 372 CPU_PD6: power-domain-cpu6 { 373 #power-domain-cells = <0>; 374 power-domains = <&CLUSTER_PD>; 375 domain-idle-states = <&BIG_CPU_SLEEP_0>; 376 }; 377 378 CPU_PD7: power-domain-cpu7 { 379 #power-domain-cells = <0>; 380 power-domains = <&CLUSTER_PD>; 381 domain-idle-states = <&BIG_CPU_SLEEP_0>; 382 }; 383 384 CLUSTER_PD: power-domain-cluster { 385 #power-domain-cells = <0>; 386 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 387 }; 388 }; 389 390 reserved_memory: reserved-memory { 391 #address-cells = <2>; 392 #size-cells = <2>; 393 ranges; 394 395 hyp_mem: hyp-region@80000000 { 396 reg = <0 0x80000000 0 0xa00000>; 397 no-map; 398 }; 399 400 cpusys_vm_mem: cpusys-vm-region@80a00000 { 401 reg = <0 0x80a00000 0 0x400000>; 402 no-map; 403 }; 404 405 hyp_tags_mem: hyp-tags-region@80e00000 { 406 reg = <0 0x80e00000 0 0x3d0000>; 407 no-map; 408 }; 409 410 xbl_sc_mem: xbl-sc-region@d8100000 { 411 reg = <0 0xd8100000 0 0x40000>; 412 no-map; 413 }; 414 415 416 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 417 reg = <0 0x811d0000 0 0x30000>; 418 no-map; 419 }; 420 421 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 422 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 423 reg = <0 0x81a00000 0 0x260000>; 424 no-map; 425 }; 426 427 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 428 compatible = "qcom,cmd-db"; 429 reg = <0 0x81c60000 0 0x20000>; 430 no-map; 431 }; 432 433 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 434 aop_config_merged_mem: aop-config-merged-region@81c80000 { 435 reg = <0 0x81c80000 0 0x74000>; 436 no-map; 437 }; 438 439 /* secdata region can be reused by apps */ 440 smem: smem@81d00000 { 441 compatible = "qcom,smem"; 442 reg = <0 0x81d00000 0 0x200000>; 443 hwlocks = <&tcsr_mutex 3>; 444 no-map; 445 }; 446 447 adsp_mhi_mem: adsp-mhi-region@81f00000 { 448 reg = <0 0x81f00000 0 0x20000>; 449 no-map; 450 }; 451 452 global_sync_mem: global-sync-region@82600000 { 453 reg = <0 0x82600000 0 0x100000>; 454 no-map; 455 }; 456 457 tz_stat_mem: tz-stat-region@82700000 { 458 reg = <0 0x82700000 0 0x100000>; 459 no-map; 460 }; 461 462 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 463 reg = <0 0x82800000 0 0x4600000>; 464 no-map; 465 }; 466 467 mpss_mem: mpss-region@8a800000 { 468 reg = <0 0x8a800000 0 0x10800000>; 469 no-map; 470 }; 471 472 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 473 reg = <0 0x9b000000 0 0x80000>; 474 no-map; 475 }; 476 477 ipa_fw_mem: ipa-fw-region@9b080000 { 478 reg = <0 0x9b080000 0 0x10000>; 479 no-map; 480 }; 481 482 ipa_gsi_mem: ipa-gsi-region@9b090000 { 483 reg = <0 0x9b090000 0 0xa000>; 484 no-map; 485 }; 486 487 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 488 reg = <0 0x9b09a000 0 0x2000>; 489 no-map; 490 }; 491 492 spss_region_mem: spss-region@9b100000 { 493 reg = <0 0x9b100000 0 0x180000>; 494 no-map; 495 }; 496 497 /* First part of the "SPU secure shared memory" region */ 498 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 499 reg = <0 0x9b280000 0 0x60000>; 500 no-map; 501 }; 502 503 /* Second part of the "SPU secure shared memory" region */ 504 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 505 reg = <0 0x9b2e0000 0 0x20000>; 506 no-map; 507 }; 508 509 camera_mem: camera-region@9b300000 { 510 reg = <0 0x9b300000 0 0x800000>; 511 no-map; 512 }; 513 514 video_mem: video-region@9bb00000 { 515 reg = <0 0x9bb00000 0 0x700000>; 516 no-map; 517 }; 518 519 cvp_mem: cvp-region@9c200000 { 520 reg = <0 0x9c200000 0 0x700000>; 521 no-map; 522 }; 523 524 cdsp_mem: cdsp-region@9c900000 { 525 reg = <0 0x9c900000 0 0x2000000>; 526 no-map; 527 }; 528 529 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 530 reg = <0 0x9e900000 0 0x80000>; 531 no-map; 532 }; 533 534 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 535 reg = <0 0x9e980000 0 0x80000>; 536 no-map; 537 }; 538 539 adspslpi_mem: adspslpi-region@9ea00000 { 540 reg = <0 0x9ea00000 0 0x4080000>; 541 no-map; 542 }; 543 544 /* uefi region can be reused by apps */ 545 546 /* Linux kernel image is loaded at 0xa8000000 */ 547 548 rmtfs_mem: rmtfs-region@d4a80000 { 549 compatible = "qcom,rmtfs-mem"; 550 reg = <0x0 0xd4a80000 0x0 0x280000>; 551 no-map; 552 553 qcom,client-id = <1>; 554 qcom,vmid = <15>; 555 }; 556 557 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 558 reg = <0 0xd4d00000 0 0x3300000>; 559 no-map; 560 }; 561 562 tz_reserved_mem: tz-reserved-region@d8000000 { 563 reg = <0 0xd8000000 0 0x100000>; 564 no-map; 565 }; 566 567 cpucp_fw_mem: cpucp-fw-region@d8140000 { 568 reg = <0 0xd8140000 0 0x1c0000>; 569 no-map; 570 }; 571 572 qtee_mem: qtee-region@d8300000 { 573 reg = <0 0xd8300000 0 0x500000>; 574 no-map; 575 }; 576 577 ta_mem: ta-region@d8800000 { 578 reg = <0 0xd8800000 0 0x8a00000>; 579 no-map; 580 }; 581 582 tz_tags_mem: tz-tags-region@e1200000 { 583 reg = <0 0xe1200000 0 0x2740000>; 584 no-map; 585 }; 586 587 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 588 reg = <0 0xe6440000 0 0x279000>; 589 no-map; 590 }; 591 592 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 593 reg = <0 0xf3600000 0 0x4aee000>; 594 no-map; 595 }; 596 597 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 598 reg = <0 0xf80ee000 0 0x1000>; 599 no-map; 600 }; 601 602 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 603 reg = <0 0xf80ef000 0 0x9000>; 604 no-map; 605 }; 606 607 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 608 reg = <0 0xf80f8000 0 0x4000>; 609 no-map; 610 }; 611 612 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 613 reg = <0 0xf80fc000 0 0x4000>; 614 no-map; 615 }; 616 617 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 618 reg = <0 0xf8100000 0 0x100000>; 619 no-map; 620 }; 621 622 oem_vm_mem: oem-vm-region@f8400000 { 623 reg = <0 0xf8400000 0 0x4800000>; 624 no-map; 625 }; 626 627 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 628 reg = <0 0xfcc00000 0 0x4000>; 629 no-map; 630 }; 631 632 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 633 reg = <0 0xfcc04000 0 0x100000>; 634 no-map; 635 }; 636 637 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 638 reg = <0 0xfce00000 0 0x2900000>; 639 no-map; 640 }; 641 642 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 643 reg = <0 0xff700000 0 0x100000>; 644 no-map; 645 }; 646 }; 647 648 smp2p-adsp { 649 compatible = "qcom,smp2p"; 650 qcom,smem = <443>, <429>; 651 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 652 IPCC_MPROC_SIGNAL_SMP2P 653 IRQ_TYPE_EDGE_RISING>; 654 mboxes = <&ipcc IPCC_CLIENT_LPASS 655 IPCC_MPROC_SIGNAL_SMP2P>; 656 657 qcom,local-pid = <0>; 658 qcom,remote-pid = <2>; 659 660 smp2p_adsp_out: master-kernel { 661 qcom,entry-name = "master-kernel"; 662 #qcom,smem-state-cells = <1>; 663 }; 664 665 smp2p_adsp_in: slave-kernel { 666 qcom,entry-name = "slave-kernel"; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 }; 670 }; 671 672 smp2p-cdsp { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <94>, <432>; 675 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 676 IPCC_MPROC_SIGNAL_SMP2P 677 IRQ_TYPE_EDGE_RISING>; 678 mboxes = <&ipcc IPCC_CLIENT_CDSP 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,local-pid = <0>; 682 qcom,remote-pid = <5>; 683 684 smp2p_cdsp_out: master-kernel { 685 qcom,entry-name = "master-kernel"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 smp2p_cdsp_in: slave-kernel { 690 qcom,entry-name = "slave-kernel"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-modem { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <435>, <428>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_MPSS 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <1>; 707 708 smp2p_modem_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 smp2p_modem_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 ipa_smp2p_out: ipa-ap-to-modem { 720 qcom,entry-name = "ipa"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 ipa_smp2p_in: ipa-modem-to-ap { 725 qcom,entry-name = "ipa"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 }; 730 731 soc: soc@0 { 732 compatible = "simple-bus"; 733 ranges = <0 0 0 0 0x10 0>; 734 dma-ranges = <0 0 0 0 0x10 0>; 735 736 #address-cells = <2>; 737 #size-cells = <2>; 738 739 gcc: clock-controller@100000 { 740 compatible = "qcom,sm8550-gcc"; 741 reg = <0 0x00100000 0 0x1f4200>; 742 #clock-cells = <1>; 743 #reset-cells = <1>; 744 #power-domain-cells = <1>; 745 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 746 <&pcie0_phy>, 747 <&pcie1_phy>, 748 <&pcie_1_phy_aux_clk>, 749 <&ufs_mem_phy 0>, 750 <&ufs_mem_phy 1>, 751 <&ufs_mem_phy 2>, 752 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 753 }; 754 755 ipcc: mailbox@408000 { 756 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 757 reg = <0 0x00408000 0 0x1000>; 758 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 759 interrupt-controller; 760 #interrupt-cells = <3>; 761 #mbox-cells = <2>; 762 }; 763 764 gpi_dma2: dma-controller@800000 { 765 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 766 #dma-cells = <3>; 767 reg = <0 0x00800000 0 0x60000>; 768 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 780 dma-channels = <12>; 781 dma-channel-mask = <0x3e>; 782 iommus = <&apps_smmu 0x436 0>; 783 status = "disabled"; 784 }; 785 786 qupv3_id_1: geniqup@8c0000 { 787 compatible = "qcom,geni-se-qup"; 788 reg = <0 0x008c0000 0 0x2000>; 789 ranges; 790 clock-names = "m-ahb", "s-ahb"; 791 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 792 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 793 iommus = <&apps_smmu 0x423 0>; 794 #address-cells = <2>; 795 #size-cells = <2>; 796 status = "disabled"; 797 798 i2c8: i2c@880000 { 799 compatible = "qcom,geni-i2c"; 800 reg = <0 0x00880000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_i2c8_data_clk>; 805 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 809 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 810 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 811 interconnect-names = "qup-core", "qup-config", "qup-memory"; 812 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 813 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 814 dma-names = "tx", "rx"; 815 status = "disabled"; 816 }; 817 818 spi8: spi@880000 { 819 compatible = "qcom,geni-spi"; 820 reg = <0 0x00880000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 823 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 826 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 828 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 830 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 831 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c9: i2c@884000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x00884000 0 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c9_data_clk>; 845 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 849 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 850 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 851 interconnect-names = "qup-core", "qup-config", "qup-memory"; 852 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 853 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 854 dma-names = "tx", "rx"; 855 status = "disabled"; 856 }; 857 858 spi9: spi@884000 { 859 compatible = "qcom,geni-spi"; 860 reg = <0 0x00884000 0 0x4000>; 861 clock-names = "se"; 862 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 863 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 866 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 868 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 869 interconnect-names = "qup-core", "qup-config", "qup-memory"; 870 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 871 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 872 dma-names = "tx", "rx"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 i2c10: i2c@888000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00888000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_i2c10_data_clk>; 885 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 889 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 890 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 891 interconnect-names = "qup-core", "qup-config", "qup-memory"; 892 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 893 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 894 dma-names = "tx", "rx"; 895 status = "disabled"; 896 }; 897 898 spi10: spi@888000 { 899 compatible = "qcom,geni-spi"; 900 reg = <0 0x00888000 0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 903 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 906 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 907 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 908 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 909 interconnect-names = "qup-core", "qup-config", "qup-memory"; 910 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 911 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 912 dma-names = "tx", "rx"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 i2c11: i2c@88c000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0 0x0088c000 0 0x4000>; 921 clock-names = "se"; 922 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_i2c11_data_clk>; 925 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 929 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 930 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 931 interconnect-names = "qup-core", "qup-config", "qup-memory"; 932 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 933 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 934 dma-names = "tx", "rx"; 935 status = "disabled"; 936 }; 937 938 spi11: spi@88c000 { 939 compatible = "qcom,geni-spi"; 940 reg = <0 0x0088c000 0 0x4000>; 941 clock-names = "se"; 942 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 943 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 946 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 947 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 948 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 949 interconnect-names = "qup-core", "qup-config", "qup-memory"; 950 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 951 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 952 dma-names = "tx", "rx"; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c12: i2c@890000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00890000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c12_data_clk>; 965 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 969 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 970 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 971 interconnect-names = "qup-core", "qup-config", "qup-memory"; 972 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 973 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 974 dma-names = "tx", "rx"; 975 status = "disabled"; 976 }; 977 978 spi12: spi@890000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0 0x00890000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 983 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 988 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", "qup-memory"; 990 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 991 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 998 i2c13: i2c@894000 { 999 compatible = "qcom,geni-i2c"; 1000 reg = <0 0x00894000 0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c13_data_clk>; 1005 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1009 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1010 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1011 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1012 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1013 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1014 dma-names = "tx", "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 spi13: spi@894000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00894000 0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1023 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1026 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1027 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1028 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1029 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1030 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1031 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1032 dma-names = "tx", "rx"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c15: i2c@89c000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0 0x0089c000 0 0x4000>; 1041 clock-names = "se"; 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_i2c15_data_clk>; 1045 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1050 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1051 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1052 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1053 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1054 dma-names = "tx", "rx"; 1055 status = "disabled"; 1056 }; 1057 1058 spi15: spi@89c000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x0089c000 0 0x4000>; 1061 clock-names = "se"; 1062 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1063 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1071 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1072 dma-names = "tx", "rx"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 }; 1078 1079 i2c_master_hub_0: geniqup@9c0000 { 1080 compatible = "qcom,geni-se-i2c-master-hub"; 1081 reg = <0x0 0x009c0000 0x0 0x2000>; 1082 clock-names = "s-ahb"; 1083 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1084 #address-cells = <2>; 1085 #size-cells = <2>; 1086 ranges; 1087 status = "disabled"; 1088 1089 i2c_hub_0: i2c@980000 { 1090 compatible = "qcom,geni-i2c-master-hub"; 1091 reg = <0x0 0x00980000 0x0 0x4000>; 1092 clock-names = "se", "core"; 1093 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1094 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&hub_i2c0_data_clk>; 1097 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1102 interconnect-names = "qup-core", "qup-config"; 1103 status = "disabled"; 1104 }; 1105 1106 i2c_hub_1: i2c@984000 { 1107 compatible = "qcom,geni-i2c-master-hub"; 1108 reg = <0x0 0x00984000 0x0 0x4000>; 1109 clock-names = "se", "core"; 1110 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1111 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&hub_i2c1_data_clk>; 1114 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1119 interconnect-names = "qup-core", "qup-config"; 1120 status = "disabled"; 1121 }; 1122 1123 i2c_hub_2: i2c@988000 { 1124 compatible = "qcom,geni-i2c-master-hub"; 1125 reg = <0x0 0x00988000 0x0 0x4000>; 1126 clock-names = "se", "core"; 1127 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1128 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&hub_i2c2_data_clk>; 1131 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1136 interconnect-names = "qup-core", "qup-config"; 1137 status = "disabled"; 1138 }; 1139 1140 i2c_hub_3: i2c@98c000 { 1141 compatible = "qcom,geni-i2c-master-hub"; 1142 reg = <0x0 0x0098c000 0x0 0x4000>; 1143 clock-names = "se", "core"; 1144 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1145 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&hub_i2c3_data_clk>; 1148 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1153 interconnect-names = "qup-core", "qup-config"; 1154 status = "disabled"; 1155 }; 1156 1157 i2c_hub_4: i2c@990000 { 1158 compatible = "qcom,geni-i2c-master-hub"; 1159 reg = <0x0 0x00990000 0x0 0x4000>; 1160 clock-names = "se", "core"; 1161 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1162 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&hub_i2c4_data_clk>; 1165 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 1174 i2c_hub_5: i2c@994000 { 1175 compatible = "qcom,geni-i2c-master-hub"; 1176 reg = <0 0x00994000 0 0x4000>; 1177 clock-names = "se", "core"; 1178 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1179 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&hub_i2c5_data_clk>; 1182 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1186 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1187 interconnect-names = "qup-core", "qup-config"; 1188 status = "disabled"; 1189 }; 1190 1191 i2c_hub_6: i2c@998000 { 1192 compatible = "qcom,geni-i2c-master-hub"; 1193 reg = <0 0x00998000 0 0x4000>; 1194 clock-names = "se", "core"; 1195 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1196 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&hub_i2c6_data_clk>; 1199 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 status = "disabled"; 1206 }; 1207 1208 i2c_hub_7: i2c@99c000 { 1209 compatible = "qcom,geni-i2c-master-hub"; 1210 reg = <0 0x0099c000 0 0x4000>; 1211 clock-names = "se", "core"; 1212 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1213 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&hub_i2c7_data_clk>; 1216 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 status = "disabled"; 1223 }; 1224 1225 i2c_hub_8: i2c@9a0000 { 1226 compatible = "qcom,geni-i2c-master-hub"; 1227 reg = <0 0x009a0000 0 0x4000>; 1228 clock-names = "se", "core"; 1229 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1230 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&hub_i2c8_data_clk>; 1233 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c_hub_9: i2c@9a4000 { 1243 compatible = "qcom,geni-i2c-master-hub"; 1244 reg = <0 0x009a4000 0 0x4000>; 1245 clock-names = "se", "core"; 1246 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1247 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&hub_i2c9_data_clk>; 1250 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 status = "disabled"; 1257 }; 1258 }; 1259 1260 gpi_dma1: dma-controller@a00000 { 1261 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1262 #dma-cells = <3>; 1263 reg = <0 0x00a00000 0 0x60000>; 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1276 dma-channels = <12>; 1277 dma-channel-mask = <0x1e>; 1278 iommus = <&apps_smmu 0xb6 0>; 1279 status = "disabled"; 1280 }; 1281 1282 qupv3_id_0: geniqup@ac0000 { 1283 compatible = "qcom,geni-se-qup"; 1284 reg = <0 0x00ac0000 0 0x2000>; 1285 ranges; 1286 clock-names = "m-ahb", "s-ahb"; 1287 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1288 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1289 iommus = <&apps_smmu 0xa3 0>; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1291 interconnect-names = "qup-core"; 1292 #address-cells = <2>; 1293 #size-cells = <2>; 1294 status = "disabled"; 1295 1296 i2c0: i2c@a80000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00a80000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_i2c0_data_clk>; 1303 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1307 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1308 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1309 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1310 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1311 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 spi0: spi@a80000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00a80000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1321 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1324 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1326 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1327 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1328 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1329 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1330 dma-names = "tx", "rx"; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 i2c1: i2c@a84000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0 0x00a84000 0 0x4000>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c1_data_clk>; 1343 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1348 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1351 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi1: spi@a84000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00a84000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1361 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1366 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1368 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1369 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 i2c2: i2c@a88000 { 1377 compatible = "qcom,geni-i2c"; 1378 reg = <0 0x00a88000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_i2c2_data_clk>; 1383 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1387 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1388 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1389 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1390 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1391 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1392 dma-names = "tx", "rx"; 1393 status = "disabled"; 1394 }; 1395 1396 spi2: spi@a88000 { 1397 compatible = "qcom,geni-spi"; 1398 reg = <0 0x00a88000 0 0x4000>; 1399 clock-names = "se"; 1400 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1401 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1404 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1405 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1406 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1407 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1408 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1409 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1410 dma-names = "tx", "rx"; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 status = "disabled"; 1414 }; 1415 1416 i2c3: i2c@a8c000 { 1417 compatible = "qcom,geni-i2c"; 1418 reg = <0 0x00a8c000 0 0x4000>; 1419 clock-names = "se"; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1421 pinctrl-names = "default"; 1422 pinctrl-0 = <&qup_i2c3_data_clk>; 1423 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1428 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1429 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1430 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1431 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1432 dma-names = "tx", "rx"; 1433 status = "disabled"; 1434 }; 1435 1436 spi3: spi@a8c000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00a8c000 0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1441 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1444 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1445 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1446 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1447 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1448 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1449 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1450 dma-names = "tx", "rx"; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 1456 i2c4: i2c@a90000 { 1457 compatible = "qcom,geni-i2c"; 1458 reg = <0 0x00a90000 0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c4_data_clk>; 1463 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1468 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1469 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1470 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1471 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1472 dma-names = "tx", "rx"; 1473 status = "disabled"; 1474 }; 1475 1476 spi4: spi@a90000 { 1477 compatible = "qcom,geni-spi"; 1478 reg = <0 0x00a90000 0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1481 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1482 pinctrl-names = "default"; 1483 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1485 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1486 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1487 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1488 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1489 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1490 dma-names = "tx", "rx"; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 i2c5: i2c@a94000 { 1497 compatible = "qcom,geni-i2c"; 1498 reg = <0 0x00a94000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_i2c5_data_clk>; 1503 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1509 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1510 dma-names = "tx", "rx"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 spi5: spi@a94000 { 1517 compatible = "qcom,geni-spi"; 1518 reg = <0 0x00a94000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1521 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1524 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1525 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1526 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1527 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1528 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1529 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1530 dma-names = "tx", "rx"; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 i2c6: i2c@a98000 { 1537 compatible = "qcom,geni-i2c"; 1538 reg = <0 0x00a98000 0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_i2c6_data_clk>; 1543 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1546 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1547 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1548 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1549 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1550 dma-names = "tx", "rx"; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 status = "disabled"; 1554 }; 1555 1556 spi6: spi@a98000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x00a98000 0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1561 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1566 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1567 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1568 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1569 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1570 dma-names = "tx", "rx"; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 uart7: serial@a9c000 { 1577 compatible = "qcom,geni-debug-uart"; 1578 reg = <0 0x00a9c000 0 0x4000>; 1579 clock-names = "se"; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_uart7_default>; 1583 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1584 interconnect-names = "qup-core", "qup-config"; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1587 status = "disabled"; 1588 }; 1589 }; 1590 1591 cnoc_main: interconnect@1500000 { 1592 compatible = "qcom,sm8550-cnoc-main"; 1593 reg = <0 0x01500000 0 0x13080>; 1594 #interconnect-cells = <2>; 1595 qcom,bcm-voters = <&apps_bcm_voter>; 1596 }; 1597 1598 config_noc: interconnect@1600000 { 1599 compatible = "qcom,sm8550-config-noc"; 1600 reg = <0 0x01600000 0 0x6200>; 1601 #interconnect-cells = <2>; 1602 qcom,bcm-voters = <&apps_bcm_voter>; 1603 }; 1604 1605 system_noc: interconnect@1680000 { 1606 compatible = "qcom,sm8550-system-noc"; 1607 reg = <0 0x01680000 0 0x1d080>; 1608 #interconnect-cells = <2>; 1609 qcom,bcm-voters = <&apps_bcm_voter>; 1610 }; 1611 1612 pcie_noc: interconnect@16c0000 { 1613 compatible = "qcom,sm8550-pcie-anoc"; 1614 reg = <0 0x016c0000 0 0x12200>; 1615 #interconnect-cells = <2>; 1616 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1617 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1618 qcom,bcm-voters = <&apps_bcm_voter>; 1619 }; 1620 1621 aggre1_noc: interconnect@16e0000 { 1622 compatible = "qcom,sm8550-aggre1-noc"; 1623 reg = <0 0x016e0000 0 0x14400>; 1624 #interconnect-cells = <2>; 1625 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1626 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1627 qcom,bcm-voters = <&apps_bcm_voter>; 1628 }; 1629 1630 aggre2_noc: interconnect@1700000 { 1631 compatible = "qcom,sm8550-aggre2-noc"; 1632 reg = <0 0x01700000 0 0x1e400>; 1633 #interconnect-cells = <2>; 1634 clocks = <&rpmhcc RPMH_IPA_CLK>; 1635 qcom,bcm-voters = <&apps_bcm_voter>; 1636 }; 1637 1638 mmss_noc: interconnect@1780000 { 1639 compatible = "qcom,sm8550-mmss-noc"; 1640 reg = <0 0x01780000 0 0x5b800>; 1641 #interconnect-cells = <2>; 1642 qcom,bcm-voters = <&apps_bcm_voter>; 1643 }; 1644 1645 pcie0: pci@1c00000 { 1646 device_type = "pci"; 1647 compatible = "qcom,pcie-sm8550"; 1648 reg = <0 0x01c00000 0 0x3000>, 1649 <0 0x60000000 0 0xf1d>, 1650 <0 0x60000f20 0 0xa8>, 1651 <0 0x60001000 0 0x1000>, 1652 <0 0x60100000 0 0x100000>; 1653 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1654 #address-cells = <3>; 1655 #size-cells = <2>; 1656 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1657 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1658 bus-range = <0x00 0xff>; 1659 1660 dma-coherent; 1661 1662 linux,pci-domain = <0>; 1663 num-lanes = <2>; 1664 1665 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1666 interrupt-names = "msi"; 1667 1668 #interrupt-cells = <1>; 1669 interrupt-map-mask = <0 0 0 0x7>; 1670 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1671 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1672 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1673 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1674 1675 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1676 <&gcc GCC_PCIE_0_AUX_CLK>, 1677 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1678 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1679 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1680 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1681 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1682 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1683 clock-names = "pipe", 1684 "aux", 1685 "cfg", 1686 "bus_master", 1687 "bus_slave", 1688 "slave_q2a", 1689 "ddrss_sf_tbu", 1690 "aggre0"; 1691 1692 interconnect-names = "pcie-mem"; 1693 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; 1694 1695 iommus = <&apps_smmu 0x1400 0x7f>; 1696 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1697 <0x100 &apps_smmu 0x1401 0x1>; 1698 1699 resets = <&gcc GCC_PCIE_0_BCR>; 1700 reset-names = "pci"; 1701 1702 power-domains = <&gcc PCIE_0_GDSC>; 1703 1704 phys = <&pcie0_phy>; 1705 phy-names = "pciephy"; 1706 1707 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1708 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1709 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&pcie0_default_state>; 1712 1713 status = "disabled"; 1714 }; 1715 1716 pcie0_phy: phy@1c06000 { 1717 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1718 reg = <0 0x01c06000 0 0x2000>; 1719 1720 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1722 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1723 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1724 <&gcc GCC_PCIE_0_PIPE_CLK>; 1725 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1726 "pipe"; 1727 1728 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1729 reset-names = "phy"; 1730 1731 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1732 assigned-clock-rates = <100000000>; 1733 1734 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1735 1736 #clock-cells = <0>; 1737 clock-output-names = "pcie0_pipe_clk"; 1738 1739 #phy-cells = <0>; 1740 1741 status = "disabled"; 1742 }; 1743 1744 pcie1: pci@1c08000 { 1745 device_type = "pci"; 1746 compatible = "qcom,pcie-sm8550"; 1747 reg = <0x0 0x01c08000 0x0 0x3000>, 1748 <0x0 0x40000000 0x0 0xf1d>, 1749 <0x0 0x40000f20 0x0 0xa8>, 1750 <0x0 0x40001000 0x0 0x1000>, 1751 <0x0 0x40100000 0x0 0x100000>; 1752 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1753 #address-cells = <3>; 1754 #size-cells = <2>; 1755 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1756 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1757 bus-range = <0x00 0xff>; 1758 1759 dma-coherent; 1760 1761 linux,pci-domain = <1>; 1762 num-lanes = <2>; 1763 1764 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1765 interrupt-names = "msi"; 1766 1767 #interrupt-cells = <1>; 1768 interrupt-map-mask = <0 0 0 0x7>; 1769 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1770 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1771 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1772 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1773 1774 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1775 <&gcc GCC_PCIE_1_AUX_CLK>, 1776 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1777 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1778 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1779 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1780 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1781 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1782 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1783 clock-names = "pipe", 1784 "aux", 1785 "cfg", 1786 "bus_master", 1787 "bus_slave", 1788 "slave_q2a", 1789 "ddrss_sf_tbu", 1790 "aggre1", 1791 "cnoc_pcie_sf_axi"; 1792 1793 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1794 assigned-clock-rates = <19200000>; 1795 1796 interconnect-names = "pcie-mem"; 1797 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; 1798 1799 iommus = <&apps_smmu 0x1480 0x7f>; 1800 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1801 <0x100 &apps_smmu 0x1481 0x1>; 1802 1803 resets = <&gcc GCC_PCIE_1_BCR>, 1804 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1805 reset-names = "pci", 1806 "pcie_1_link_down_reset"; 1807 1808 power-domains = <&gcc PCIE_1_GDSC>; 1809 1810 phys = <&pcie1_phy>; 1811 phy-names = "pciephy"; 1812 1813 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1814 enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1815 1816 pinctrl-names = "default"; 1817 pinctrl-0 = <&pcie1_default_state>; 1818 1819 status = "disabled"; 1820 }; 1821 1822 pcie1_phy: phy@1c0e000 { 1823 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1824 reg = <0x0 0x01c0e000 0x0 0x2000>; 1825 1826 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1827 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1828 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1829 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1830 <&gcc GCC_PCIE_1_PIPE_CLK>, 1831 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 1832 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1833 "pipe", "aux_phy"; 1834 1835 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1836 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1837 reset-names = "phy", "nocsr"; 1838 1839 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1840 assigned-clock-rates = <100000000>; 1841 1842 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1843 1844 #clock-cells = <0>; 1845 clock-output-names = "pcie1_pipe_clk"; 1846 1847 #phy-cells = <0>; 1848 1849 status = "disabled"; 1850 }; 1851 1852 cryptobam: dma-controller@1dc4000 { 1853 compatible = "qcom,bam-v1.7.0"; 1854 reg = <0x0 0x01dc4000 0x0 0x28000>; 1855 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1856 #dma-cells = <1>; 1857 qcom,ee = <0>; 1858 qcom,controlled-remotely; 1859 iommus = <&apps_smmu 0x480 0x0>, 1860 <&apps_smmu 0x481 0x0>; 1861 }; 1862 1863 crypto: crypto@1de0000 { 1864 compatible = "qcom,sm8550-qce"; 1865 reg = <0x0 0x01dfa000 0x0 0x6000>; 1866 dmas = <&cryptobam 4>, <&cryptobam 5>; 1867 dma-names = "rx", "tx"; 1868 iommus = <&apps_smmu 0x480 0x0>, 1869 <&apps_smmu 0x481 0x0>; 1870 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "memory"; 1872 }; 1873 1874 ufs_mem_phy: phy@1d80000 { 1875 compatible = "qcom,sm8550-qmp-ufs-phy"; 1876 reg = <0x0 0x01d80000 0x0 0x2000>; 1877 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1878 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1879 clock-names = "ref", "ref_aux"; 1880 1881 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1882 1883 resets = <&ufs_mem_hc 0>; 1884 reset-names = "ufsphy"; 1885 1886 #clock-cells = <1>; 1887 #phy-cells = <0>; 1888 1889 status = "disabled"; 1890 }; 1891 1892 ufs_mem_hc: ufs@1d84000 { 1893 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1894 "jedec,ufs-2.0"; 1895 reg = <0x0 0x01d84000 0x0 0x3000>; 1896 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1897 phys = <&ufs_mem_phy>; 1898 phy-names = "ufsphy"; 1899 lanes-per-direction = <2>; 1900 #reset-cells = <1>; 1901 resets = <&gcc GCC_UFS_PHY_BCR>; 1902 reset-names = "rst"; 1903 1904 power-domains = <&gcc UFS_PHY_GDSC>; 1905 required-opps = <&rpmhpd_opp_nom>; 1906 1907 iommus = <&apps_smmu 0x60 0x0>; 1908 dma-coherent; 1909 1910 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1912 1913 interconnect-names = "ufs-ddr", "cpu-ufs"; 1914 clock-names = "core_clk", 1915 "bus_aggr_clk", 1916 "iface_clk", 1917 "core_clk_unipro", 1918 "ref_clk", 1919 "tx_lane0_sync_clk", 1920 "rx_lane0_sync_clk", 1921 "rx_lane1_sync_clk"; 1922 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1923 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1924 <&gcc GCC_UFS_PHY_AHB_CLK>, 1925 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1926 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1927 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1928 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1929 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1930 freq-table-hz = 1931 <75000000 300000000>, 1932 <0 0>, 1933 <0 0>, 1934 <75000000 300000000>, 1935 <100000000 403000000>, 1936 <0 0>, 1937 <0 0>, 1938 <0 0>; 1939 status = "disabled"; 1940 }; 1941 1942 tcsr_mutex: hwlock@1f40000 { 1943 compatible = "qcom,tcsr-mutex"; 1944 reg = <0 0x01f40000 0 0x20000>; 1945 #hwlock-cells = <1>; 1946 }; 1947 1948 tcsr: clock-controller@1fc0000 { 1949 compatible = "qcom,sm8550-tcsr", "syscon"; 1950 reg = <0 0x01fc0000 0 0x30000>; 1951 clocks = <&rpmhcc RPMH_CXO_CLK>; 1952 #clock-cells = <1>; 1953 #reset-cells = <1>; 1954 }; 1955 1956 remoteproc_mpss: remoteproc@4080000 { 1957 compatible = "qcom,sm8550-mpss-pas"; 1958 reg = <0x0 0x04080000 0x0 0x4040>; 1959 1960 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1961 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1962 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1963 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1964 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1965 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1966 interrupt-names = "wdog", "fatal", "ready", "handover", 1967 "stop-ack", "shutdown-ack"; 1968 1969 clocks = <&rpmhcc RPMH_CXO_CLK>; 1970 clock-names = "xo"; 1971 1972 power-domains = <&rpmhpd SM8550_CX>, 1973 <&rpmhpd SM8550_MSS>; 1974 power-domain-names = "cx", "mss"; 1975 1976 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1977 1978 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 1979 1980 qcom,qmp = <&aoss_qmp>; 1981 1982 qcom,smem-states = <&smp2p_modem_out 0>; 1983 qcom,smem-state-names = "stop"; 1984 1985 status = "disabled"; 1986 1987 glink-edge { 1988 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1989 IPCC_MPROC_SIGNAL_GLINK_QMP 1990 IRQ_TYPE_EDGE_RISING>; 1991 mboxes = <&ipcc IPCC_CLIENT_MPSS 1992 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1993 label = "mpss"; 1994 qcom,remote-pid = <1>; 1995 }; 1996 }; 1997 1998 lpass_tlmm: pinctrl@6e80000 { 1999 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2000 reg = <0 0x06e80000 0 0x20000>, 2001 <0 0x07250000 0 0x10000>; 2002 gpio-controller; 2003 #gpio-cells = <2>; 2004 gpio-ranges = <&lpass_tlmm 0 0 23>; 2005 2006 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2007 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2008 clock-names = "core", "audio"; 2009 }; 2010 2011 lpass_lpiaon_noc: interconnect@7400000 { 2012 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2013 reg = <0 0x07400000 0 0x19080>; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 lpass_lpicx_noc: interconnect@7430000 { 2019 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2020 reg = <0 0x07430000 0 0x3a200>; 2021 #interconnect-cells = <2>; 2022 qcom,bcm-voters = <&apps_bcm_voter>; 2023 }; 2024 2025 lpass_ag_noc: interconnect@7e40000 { 2026 compatible = "qcom,sm8550-lpass-ag-noc"; 2027 reg = <0 0x07e40000 0 0xe080>; 2028 #interconnect-cells = <2>; 2029 qcom,bcm-voters = <&apps_bcm_voter>; 2030 }; 2031 2032 sdhc_2: mmc@8804000 { 2033 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2034 reg = <0 0x08804000 0 0x1000>; 2035 2036 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "hc_irq", "pwr_irq"; 2039 2040 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2041 <&gcc GCC_SDCC2_APPS_CLK>, 2042 <&rpmhcc RPMH_CXO_CLK>; 2043 clock-names = "iface", "core", "xo"; 2044 iommus = <&apps_smmu 0x540 0>; 2045 qcom,dll-config = <0x0007642c>; 2046 qcom,ddr-config = <0x80040868>; 2047 power-domains = <&rpmhpd SM8550_CX>; 2048 operating-points-v2 = <&sdhc2_opp_table>; 2049 2050 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2051 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2052 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2053 bus-width = <4>; 2054 dma-coherent; 2055 2056 /* Forbid SDR104/SDR50 - broken hw! */ 2057 sdhci-caps-mask = <0x3 0>; 2058 2059 status = "disabled"; 2060 2061 sdhc2_opp_table: opp-table { 2062 compatible = "operating-points-v2"; 2063 2064 opp-19200000 { 2065 opp-hz = /bits/ 64 <19200000>; 2066 required-opps = <&rpmhpd_opp_min_svs>; 2067 }; 2068 2069 opp-50000000 { 2070 opp-hz = /bits/ 64 <50000000>; 2071 required-opps = <&rpmhpd_opp_low_svs>; 2072 }; 2073 2074 opp-100000000 { 2075 opp-hz = /bits/ 64 <100000000>; 2076 required-opps = <&rpmhpd_opp_svs>; 2077 }; 2078 2079 opp-202000000 { 2080 opp-hz = /bits/ 64 <202000000>; 2081 required-opps = <&rpmhpd_opp_svs_l1>; 2082 }; 2083 }; 2084 }; 2085 2086 mdss: display-subsystem@ae00000 { 2087 compatible = "qcom,sm8550-mdss"; 2088 reg = <0 0x0ae00000 0 0x1000>; 2089 reg-names = "mdss"; 2090 2091 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2092 interrupt-controller; 2093 #interrupt-cells = <1>; 2094 2095 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2096 <&gcc GCC_DISP_AHB_CLK>, 2097 <&gcc GCC_DISP_HF_AXI_CLK>, 2098 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2099 2100 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2101 2102 power-domains = <&dispcc MDSS_GDSC>; 2103 2104 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2105 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2106 interconnect-names = "mdp0-mem", "mdp1-mem"; 2107 2108 iommus = <&apps_smmu 0x1c00 0x2>; 2109 2110 #address-cells = <2>; 2111 #size-cells = <2>; 2112 ranges; 2113 2114 status = "disabled"; 2115 2116 mdss_mdp: display-controller@ae01000 { 2117 compatible = "qcom,sm8550-dpu"; 2118 reg = <0 0x0ae01000 0 0x8f000>, 2119 <0 0x0aeb0000 0 0x2008>; 2120 reg-names = "mdp", "vbif"; 2121 2122 interrupt-parent = <&mdss>; 2123 interrupts = <0>; 2124 2125 clocks = <&gcc GCC_DISP_AHB_CLK>, 2126 <&gcc GCC_DISP_HF_AXI_CLK>, 2127 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2128 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2129 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2131 clock-names = "bus", 2132 "nrt_bus", 2133 "iface", 2134 "lut", 2135 "core", 2136 "vsync"; 2137 2138 power-domains = <&rpmhpd SM8550_MMCX>; 2139 2140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2141 assigned-clock-rates = <19200000>; 2142 2143 operating-points-v2 = <&mdp_opp_table>; 2144 2145 ports { 2146 #address-cells = <1>; 2147 #size-cells = <0>; 2148 2149 port@0 { 2150 reg = <0>; 2151 dpu_intf1_out: endpoint { 2152 remote-endpoint = <&mdss_dsi0_in>; 2153 }; 2154 }; 2155 2156 port@1 { 2157 reg = <1>; 2158 dpu_intf2_out: endpoint { 2159 remote-endpoint = <&mdss_dsi1_in>; 2160 }; 2161 }; 2162 }; 2163 2164 mdp_opp_table: opp-table { 2165 compatible = "operating-points-v2"; 2166 2167 opp-200000000 { 2168 opp-hz = /bits/ 64 <200000000>; 2169 required-opps = <&rpmhpd_opp_low_svs>; 2170 }; 2171 2172 opp-325000000 { 2173 opp-hz = /bits/ 64 <325000000>; 2174 required-opps = <&rpmhpd_opp_svs>; 2175 }; 2176 2177 opp-375000000 { 2178 opp-hz = /bits/ 64 <375000000>; 2179 required-opps = <&rpmhpd_opp_svs_l1>; 2180 }; 2181 2182 opp-514000000 { 2183 opp-hz = /bits/ 64 <514000000>; 2184 required-opps = <&rpmhpd_opp_nom>; 2185 }; 2186 }; 2187 }; 2188 2189 mdss_dsi0: dsi@ae94000 { 2190 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2191 reg = <0 0x0ae94000 0 0x400>; 2192 reg-names = "dsi_ctrl"; 2193 2194 interrupt-parent = <&mdss>; 2195 interrupts = <4>; 2196 2197 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2198 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2199 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2200 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2201 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2202 <&gcc GCC_DISP_HF_AXI_CLK>; 2203 clock-names = "byte", 2204 "byte_intf", 2205 "pixel", 2206 "core", 2207 "iface", 2208 "bus"; 2209 2210 power-domains = <&rpmhpd SM8550_MMCX>; 2211 2212 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2213 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2214 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2215 2216 operating-points-v2 = <&mdss_dsi_opp_table>; 2217 2218 phys = <&mdss_dsi0_phy>; 2219 phy-names = "dsi"; 2220 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 2224 status = "disabled"; 2225 2226 ports { 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 2230 port@0 { 2231 reg = <0>; 2232 mdss_dsi0_in: endpoint { 2233 remote-endpoint = <&dpu_intf1_out>; 2234 }; 2235 }; 2236 2237 port@1 { 2238 reg = <1>; 2239 mdss_dsi0_out: endpoint { 2240 }; 2241 }; 2242 }; 2243 2244 mdss_dsi_opp_table: opp-table { 2245 compatible = "operating-points-v2"; 2246 2247 opp-187500000 { 2248 opp-hz = /bits/ 64 <187500000>; 2249 required-opps = <&rpmhpd_opp_low_svs>; 2250 }; 2251 2252 opp-300000000 { 2253 opp-hz = /bits/ 64 <300000000>; 2254 required-opps = <&rpmhpd_opp_svs>; 2255 }; 2256 2257 opp-358000000 { 2258 opp-hz = /bits/ 64 <358000000>; 2259 required-opps = <&rpmhpd_opp_svs_l1>; 2260 }; 2261 }; 2262 }; 2263 2264 mdss_dsi0_phy: phy@ae95000 { 2265 compatible = "qcom,sm8550-dsi-phy-4nm"; 2266 reg = <0 0x0ae95000 0 0x200>, 2267 <0 0x0ae95200 0 0x280>, 2268 <0 0x0ae95500 0 0x400>; 2269 reg-names = "dsi_phy", 2270 "dsi_phy_lane", 2271 "dsi_pll"; 2272 2273 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2274 <&rpmhcc RPMH_CXO_CLK>; 2275 clock-names = "iface", "ref"; 2276 2277 #clock-cells = <1>; 2278 #phy-cells = <0>; 2279 2280 status = "disabled"; 2281 }; 2282 2283 mdss_dsi1: dsi@ae96000 { 2284 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2285 reg = <0 0x0ae96000 0 0x400>; 2286 reg-names = "dsi_ctrl"; 2287 2288 interrupt-parent = <&mdss>; 2289 interrupts = <5>; 2290 2291 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2292 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2293 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2294 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2295 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2296 <&gcc GCC_DISP_HF_AXI_CLK>; 2297 clock-names = "byte", 2298 "byte_intf", 2299 "pixel", 2300 "core", 2301 "iface", 2302 "bus"; 2303 2304 power-domains = <&rpmhpd SM8550_MMCX>; 2305 2306 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2307 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2308 2309 operating-points-v2 = <&mdss_dsi_opp_table>; 2310 2311 phys = <&mdss_dsi1_phy>; 2312 phy-names = "dsi"; 2313 2314 #address-cells = <1>; 2315 #size-cells = <0>; 2316 2317 status = "disabled"; 2318 2319 ports { 2320 #address-cells = <1>; 2321 #size-cells = <0>; 2322 2323 port@0 { 2324 reg = <0>; 2325 mdss_dsi1_in: endpoint { 2326 remote-endpoint = <&dpu_intf2_out>; 2327 }; 2328 }; 2329 2330 port@1 { 2331 reg = <1>; 2332 mdss_dsi1_out: endpoint { 2333 }; 2334 }; 2335 }; 2336 }; 2337 2338 mdss_dsi1_phy: phy@ae97000 { 2339 compatible = "qcom,sm8550-dsi-phy-4nm"; 2340 reg = <0 0x0ae97000 0 0x200>, 2341 <0 0x0ae97200 0 0x280>, 2342 <0 0x0ae97500 0 0x400>; 2343 reg-names = "dsi_phy", 2344 "dsi_phy_lane", 2345 "dsi_pll"; 2346 2347 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2348 <&rpmhcc RPMH_CXO_CLK>; 2349 clock-names = "iface", "ref"; 2350 2351 #clock-cells = <1>; 2352 #phy-cells = <0>; 2353 2354 status = "disabled"; 2355 }; 2356 }; 2357 2358 dispcc: clock-controller@af00000 { 2359 compatible = "qcom,sm8550-dispcc"; 2360 reg = <0 0x0af00000 0 0x20000>; 2361 clocks = <&bi_tcxo_div2>, 2362 <&bi_tcxo_ao_div2>, 2363 <&gcc GCC_DISP_AHB_CLK>, 2364 <&sleep_clk>, 2365 <&mdss_dsi0_phy 0>, 2366 <&mdss_dsi0_phy 1>, 2367 <&mdss_dsi1_phy 0>, 2368 <&mdss_dsi1_phy 1>, 2369 <0>, /* dp0 */ 2370 <0>, 2371 <0>, /* dp1 */ 2372 <0>, 2373 <0>, /* dp2 */ 2374 <0>, 2375 <0>, /* dp3 */ 2376 <0>; 2377 power-domains = <&rpmhpd SM8550_MMCX>; 2378 required-opps = <&rpmhpd_opp_low_svs>; 2379 #clock-cells = <1>; 2380 #reset-cells = <1>; 2381 #power-domain-cells = <1>; 2382 status = "disabled"; 2383 }; 2384 2385 usb_1_hsphy: phy@88e3000 { 2386 compatible = "qcom,sm8550-snps-eusb2-phy"; 2387 reg = <0x0 0x088e3000 0x0 0x154>; 2388 #phy-cells = <0>; 2389 2390 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2391 clock-names = "ref"; 2392 2393 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2394 2395 status = "disabled"; 2396 }; 2397 2398 usb_dp_qmpphy: phy@88e8000 { 2399 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2400 reg = <0x0 0x088e8000 0x0 0x3000>; 2401 2402 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2403 <&rpmhcc RPMH_CXO_CLK>, 2404 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2405 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2406 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2407 2408 power-domains = <&gcc USB3_PHY_GDSC>; 2409 2410 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2411 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2412 reset-names = "phy", "common"; 2413 2414 #clock-cells = <1>; 2415 #phy-cells = <1>; 2416 2417 status = "disabled"; 2418 }; 2419 2420 usb_1: usb@a6f8800 { 2421 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2422 reg = <0x0 0x0a6f8800 0x0 0x400>; 2423 #address-cells = <2>; 2424 #size-cells = <2>; 2425 ranges; 2426 2427 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2428 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2429 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2430 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2431 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2432 <&tcsr TCSR_USB3_CLKREF_EN>; 2433 clock-names = "cfg_noc", 2434 "core", 2435 "iface", 2436 "sleep", 2437 "mock_utmi", 2438 "xo"; 2439 2440 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2441 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2442 assigned-clock-rates = <19200000>, <200000000>; 2443 2444 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2445 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2446 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2447 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2448 interrupt-names = "hs_phy_irq", 2449 "ss_phy_irq", 2450 "dm_hs_phy_irq", 2451 "dp_hs_phy_irq"; 2452 2453 power-domains = <&gcc USB30_PRIM_GDSC>; 2454 required-opps = <&rpmhpd_opp_nom>; 2455 2456 resets = <&gcc GCC_USB30_PRIM_BCR>; 2457 2458 status = "disabled"; 2459 2460 usb_1_dwc3: usb@a600000 { 2461 compatible = "snps,dwc3"; 2462 reg = <0x0 0x0a600000 0x0 0xcd00>; 2463 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2464 iommus = <&apps_smmu 0x40 0x0>; 2465 snps,dis_u2_susphy_quirk; 2466 snps,dis_enblslpm_quirk; 2467 snps,usb3_lpm_capable; 2468 phys = <&usb_1_hsphy>, 2469 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2470 phy-names = "usb2-phy", "usb3-phy"; 2471 }; 2472 }; 2473 2474 pdc: interrupt-controller@b220000 { 2475 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2476 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2477 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2478 <125 63 1>, <126 716 12>, 2479 <138 251 5>; 2480 #interrupt-cells = <2>; 2481 interrupt-parent = <&intc>; 2482 interrupt-controller; 2483 }; 2484 2485 tsens0: thermal-sensor@c271000 { 2486 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2487 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2488 <0 0x0c222000 0 0x1000>; /* SROT */ 2489 #qcom,sensors = <16>; 2490 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2492 interrupt-names = "uplow", "critical"; 2493 #thermal-sensor-cells = <1>; 2494 }; 2495 2496 tsens1: thermal-sensor@c272000 { 2497 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2498 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2499 <0 0x0c223000 0 0x1000>; /* SROT */ 2500 #qcom,sensors = <16>; 2501 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2503 interrupt-names = "uplow", "critical"; 2504 #thermal-sensor-cells = <1>; 2505 }; 2506 2507 tsens2: thermal-sensor@c273000 { 2508 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2509 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2510 <0 0x0c224000 0 0x1000>; /* SROT */ 2511 #qcom,sensors = <16>; 2512 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2514 interrupt-names = "uplow", "critical"; 2515 #thermal-sensor-cells = <1>; 2516 }; 2517 2518 aoss_qmp: power-management@c300000 { 2519 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2520 reg = <0 0x0c300000 0 0x400>; 2521 interrupt-parent = <&ipcc>; 2522 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2523 IRQ_TYPE_EDGE_RISING>; 2524 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2525 2526 #clock-cells = <0>; 2527 }; 2528 2529 sram@c3f0000 { 2530 compatible = "qcom,rpmh-stats"; 2531 reg = <0 0x0c3f0000 0 0x400>; 2532 }; 2533 2534 spmi_bus: spmi@c400000 { 2535 compatible = "qcom,spmi-pmic-arb"; 2536 reg = <0 0x0c400000 0 0x3000>, 2537 <0 0x0c500000 0 0x4000000>, 2538 <0 0x0c440000 0 0x80000>, 2539 <0 0x0c4c0000 0 0x20000>, 2540 <0 0x0c42d000 0 0x4000>; 2541 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2542 interrupt-names = "periph_irq"; 2543 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2544 qcom,ee = <0>; 2545 qcom,channel = <0>; 2546 qcom,bus-id = <0>; 2547 #address-cells = <2>; 2548 #size-cells = <0>; 2549 interrupt-controller; 2550 #interrupt-cells = <4>; 2551 }; 2552 2553 tlmm: pinctrl@f000000 { 2554 compatible = "qcom,sm8550-tlmm"; 2555 reg = <0 0x0f100000 0 0x300000>; 2556 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2557 gpio-controller; 2558 #gpio-cells = <2>; 2559 interrupt-controller; 2560 #interrupt-cells = <2>; 2561 gpio-ranges = <&tlmm 0 0 211>; 2562 wakeup-parent = <&pdc>; 2563 2564 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2565 /* SDA, SCL */ 2566 pins = "gpio16", "gpio17"; 2567 function = "i2chub0_se0"; 2568 drive-strength = <2>; 2569 bias-pull-up; 2570 }; 2571 2572 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2573 /* SDA, SCL */ 2574 pins = "gpio18", "gpio19"; 2575 function = "i2chub0_se1"; 2576 drive-strength = <2>; 2577 bias-pull-up; 2578 }; 2579 2580 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2581 /* SDA, SCL */ 2582 pins = "gpio20", "gpio21"; 2583 function = "i2chub0_se2"; 2584 drive-strength = <2>; 2585 bias-pull-up; 2586 }; 2587 2588 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2589 /* SDA, SCL */ 2590 pins = "gpio22", "gpio23"; 2591 function = "i2chub0_se3"; 2592 drive-strength = <2>; 2593 bias-pull-up; 2594 }; 2595 2596 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2597 /* SDA, SCL */ 2598 pins = "gpio4", "gpio5"; 2599 function = "i2chub0_se4"; 2600 drive-strength = <2>; 2601 bias-pull-up; 2602 }; 2603 2604 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2605 /* SDA, SCL */ 2606 pins = "gpio6", "gpio7"; 2607 function = "i2chub0_se5"; 2608 drive-strength = <2>; 2609 bias-pull-up; 2610 }; 2611 2612 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2613 /* SDA, SCL */ 2614 pins = "gpio8", "gpio9"; 2615 function = "i2chub0_se6"; 2616 drive-strength = <2>; 2617 bias-pull-up; 2618 }; 2619 2620 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2621 /* SDA, SCL */ 2622 pins = "gpio10", "gpio11"; 2623 function = "i2chub0_se7"; 2624 drive-strength = <2>; 2625 bias-pull-up; 2626 }; 2627 2628 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2629 /* SDA, SCL */ 2630 pins = "gpio206", "gpio207"; 2631 function = "i2chub0_se8"; 2632 drive-strength = <2>; 2633 bias-pull-up; 2634 }; 2635 2636 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2637 /* SDA, SCL */ 2638 pins = "gpio84", "gpio85"; 2639 function = "i2chub0_se9"; 2640 drive-strength = <2>; 2641 bias-pull-up; 2642 }; 2643 2644 pcie0_default_state: pcie0-default-state { 2645 perst-pins { 2646 pins = "gpio94"; 2647 function = "gpio"; 2648 drive-strength = <2>; 2649 bias-pull-down; 2650 }; 2651 2652 clkreq-pins { 2653 pins = "gpio95"; 2654 function = "pcie0_clk_req_n"; 2655 drive-strength = <2>; 2656 bias-pull-up; 2657 }; 2658 2659 wake-pins { 2660 pins = "gpio96"; 2661 function = "gpio"; 2662 drive-strength = <2>; 2663 bias-pull-up; 2664 }; 2665 }; 2666 2667 pcie1_default_state: pcie1-default-state { 2668 perst-pins { 2669 pins = "gpio97"; 2670 function = "gpio"; 2671 drive-strength = <2>; 2672 bias-pull-down; 2673 }; 2674 2675 clkreq-pins { 2676 pins = "gpio98"; 2677 function = "pcie1_clk_req_n"; 2678 drive-strength = <2>; 2679 bias-pull-up; 2680 }; 2681 2682 wake-pins { 2683 pins = "gpio99"; 2684 function = "gpio"; 2685 drive-strength = <2>; 2686 bias-pull-up; 2687 }; 2688 }; 2689 2690 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2691 /* SDA, SCL */ 2692 pins = "gpio28", "gpio29"; 2693 function = "qup1_se0"; 2694 drive-strength = <2>; 2695 bias-pull-up = <2200>; 2696 }; 2697 2698 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2699 /* SDA, SCL */ 2700 pins = "gpio32", "gpio33"; 2701 function = "qup1_se1"; 2702 drive-strength = <2>; 2703 bias-pull-up = <2200>; 2704 }; 2705 2706 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2707 /* SDA, SCL */ 2708 pins = "gpio36", "gpio37"; 2709 function = "qup1_se2"; 2710 drive-strength = <2>; 2711 bias-pull-up = <2200>; 2712 }; 2713 2714 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2715 /* SDA, SCL */ 2716 pins = "gpio40", "gpio41"; 2717 function = "qup1_se3"; 2718 drive-strength = <2>; 2719 bias-pull-up = <2200>; 2720 }; 2721 2722 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2723 /* SDA, SCL */ 2724 pins = "gpio44", "gpio45"; 2725 function = "qup1_se4"; 2726 drive-strength = <2>; 2727 bias-pull-up = <2200>; 2728 }; 2729 2730 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2731 /* SDA, SCL */ 2732 pins = "gpio52", "gpio53"; 2733 function = "qup1_se5"; 2734 drive-strength = <2>; 2735 bias-pull-up = <2200>; 2736 }; 2737 2738 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2739 /* SDA, SCL */ 2740 pins = "gpio48", "gpio49"; 2741 function = "qup1_se6"; 2742 drive-strength = <2>; 2743 bias-pull-up = <2200>; 2744 }; 2745 2746 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2747 scl-pins { 2748 pins = "gpio57"; 2749 function = "qup2_se0_l1_mira"; 2750 drive-strength = <2>; 2751 bias-pull-up = <2200>; 2752 }; 2753 2754 sda-pins { 2755 pins = "gpio56"; 2756 function = "qup2_se0_l0_mira"; 2757 drive-strength = <2>; 2758 bias-pull-up = <2200>; 2759 }; 2760 }; 2761 2762 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2763 /* SDA, SCL */ 2764 pins = "gpio60", "gpio61"; 2765 function = "qup2_se1"; 2766 drive-strength = <2>; 2767 bias-pull-up = <2200>; 2768 }; 2769 2770 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2771 /* SDA, SCL */ 2772 pins = "gpio64", "gpio65"; 2773 function = "qup2_se2"; 2774 drive-strength = <2>; 2775 bias-pull-up = <2200>; 2776 }; 2777 2778 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2779 /* SDA, SCL */ 2780 pins = "gpio68", "gpio69"; 2781 function = "qup2_se3"; 2782 drive-strength = <2>; 2783 bias-pull-up = <2200>; 2784 }; 2785 2786 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2787 /* SDA, SCL */ 2788 pins = "gpio2", "gpio3"; 2789 function = "qup2_se4"; 2790 drive-strength = <2>; 2791 bias-pull-up = <2200>; 2792 }; 2793 2794 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2795 /* SDA, SCL */ 2796 pins = "gpio80", "gpio81"; 2797 function = "qup2_se5"; 2798 drive-strength = <2>; 2799 bias-pull-up = <2200>; 2800 }; 2801 2802 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2803 /* SDA, SCL */ 2804 pins = "gpio72", "gpio106"; 2805 function = "qup2_se7"; 2806 drive-strength = <2>; 2807 bias-pull-up = <2200>; 2808 }; 2809 2810 qup_spi0_cs: qup-spi0-cs-state { 2811 cs-pins { 2812 pins = "gpio31"; 2813 function = "qup1_se0"; 2814 }; 2815 }; 2816 2817 qup_spi0_data_clk: qup-spi0-data-clk-state { 2818 /* MISO, MOSI, CLK */ 2819 pins = "gpio28", "gpio29", "gpio30"; 2820 function = "qup1_se0"; 2821 drive-strength = <6>; 2822 bias-disable; 2823 }; 2824 2825 qup_spi1_cs: qup-spi1-cs-state { 2826 pins = "gpio35"; 2827 function = "qup1_se1"; 2828 drive-strength = <6>; 2829 bias-disable; 2830 }; 2831 2832 qup_spi1_data_clk: qup-spi1-data-clk-state { 2833 /* MISO, MOSI, CLK */ 2834 pins = "gpio32", "gpio33", "gpio34"; 2835 function = "qup1_se1"; 2836 drive-strength = <6>; 2837 bias-disable; 2838 }; 2839 2840 qup_spi2_cs: qup-spi2-cs-state { 2841 pins = "gpio39"; 2842 function = "qup1_se2"; 2843 drive-strength = <6>; 2844 bias-disable; 2845 }; 2846 2847 qup_spi2_data_clk: qup-spi2-data-clk-state { 2848 /* MISO, MOSI, CLK */ 2849 pins = "gpio36", "gpio37", "gpio38"; 2850 function = "qup1_se2"; 2851 drive-strength = <6>; 2852 bias-disable; 2853 }; 2854 2855 qup_spi3_cs: qup-spi3-cs-state { 2856 pins = "gpio43"; 2857 function = "qup1_se3"; 2858 drive-strength = <6>; 2859 bias-disable; 2860 }; 2861 2862 qup_spi3_data_clk: qup-spi3-data-clk-state { 2863 /* MISO, MOSI, CLK */ 2864 pins = "gpio40", "gpio41", "gpio42"; 2865 function = "qup1_se3"; 2866 drive-strength = <6>; 2867 bias-disable; 2868 }; 2869 2870 qup_spi4_cs: qup-spi4-cs-state { 2871 pins = "gpio47"; 2872 function = "qup1_se4"; 2873 drive-strength = <6>; 2874 bias-disable; 2875 }; 2876 2877 qup_spi4_data_clk: qup-spi4-data-clk-state { 2878 /* MISO, MOSI, CLK */ 2879 pins = "gpio44", "gpio45", "gpio46"; 2880 function = "qup1_se4"; 2881 drive-strength = <6>; 2882 bias-disable; 2883 }; 2884 2885 qup_spi5_cs: qup-spi5-cs-state { 2886 pins = "gpio55"; 2887 function = "qup1_se5"; 2888 drive-strength = <6>; 2889 bias-disable; 2890 }; 2891 2892 qup_spi5_data_clk: qup-spi5-data-clk-state { 2893 /* MISO, MOSI, CLK */ 2894 pins = "gpio52", "gpio53", "gpio54"; 2895 function = "qup1_se5"; 2896 drive-strength = <6>; 2897 bias-disable; 2898 }; 2899 2900 qup_spi6_cs: qup-spi6-cs-state { 2901 pins = "gpio51"; 2902 function = "qup1_se6"; 2903 drive-strength = <6>; 2904 bias-disable; 2905 }; 2906 2907 qup_spi6_data_clk: qup-spi6-data-clk-state { 2908 /* MISO, MOSI, CLK */ 2909 pins = "gpio48", "gpio49", "gpio50"; 2910 function = "qup1_se6"; 2911 drive-strength = <6>; 2912 bias-disable; 2913 }; 2914 2915 qup_spi8_cs: qup-spi8-cs-state { 2916 pins = "gpio59"; 2917 function = "qup2_se0_l3_mira"; 2918 drive-strength = <6>; 2919 bias-disable; 2920 }; 2921 2922 qup_spi8_data_clk: qup-spi8-data-clk-state { 2923 /* MISO, MOSI, CLK */ 2924 pins = "gpio56", "gpio57", "gpio58"; 2925 function = "qup2_se0_l2_mira"; 2926 drive-strength = <6>; 2927 bias-disable; 2928 }; 2929 2930 qup_spi9_cs: qup-spi9-cs-state { 2931 pins = "gpio63"; 2932 function = "qup2_se1"; 2933 drive-strength = <6>; 2934 bias-disable; 2935 }; 2936 2937 qup_spi9_data_clk: qup-spi9-data-clk-state { 2938 /* MISO, MOSI, CLK */ 2939 pins = "gpio60", "gpio61", "gpio62"; 2940 function = "qup2_se1"; 2941 drive-strength = <6>; 2942 bias-disable; 2943 }; 2944 2945 qup_spi10_cs: qup-spi10-cs-state { 2946 pins = "gpio67"; 2947 function = "qup2_se2"; 2948 drive-strength = <6>; 2949 bias-disable; 2950 }; 2951 2952 qup_spi10_data_clk: qup-spi10-data-clk-state { 2953 /* MISO, MOSI, CLK */ 2954 pins = "gpio64", "gpio65", "gpio66"; 2955 function = "qup2_se2"; 2956 drive-strength = <6>; 2957 bias-disable; 2958 }; 2959 2960 qup_spi11_cs: qup-spi11-cs-state { 2961 pins = "gpio71"; 2962 function = "qup2_se3"; 2963 drive-strength = <6>; 2964 bias-disable; 2965 }; 2966 2967 qup_spi11_data_clk: qup-spi11-data-clk-state { 2968 /* MISO, MOSI, CLK */ 2969 pins = "gpio68", "gpio69", "gpio70"; 2970 function = "qup2_se3"; 2971 drive-strength = <6>; 2972 bias-disable; 2973 }; 2974 2975 qup_spi12_cs: qup-spi12-cs-state { 2976 pins = "gpio119"; 2977 function = "qup2_se4"; 2978 drive-strength = <6>; 2979 bias-disable; 2980 }; 2981 2982 qup_spi12_data_clk: qup-spi12-data-clk-state { 2983 /* MISO, MOSI, CLK */ 2984 pins = "gpio2", "gpio3", "gpio118"; 2985 function = "qup2_se4"; 2986 drive-strength = <6>; 2987 bias-disable; 2988 }; 2989 2990 qup_spi13_cs: qup-spi13-cs-state { 2991 pins = "gpio83"; 2992 function = "qup2_se5"; 2993 drive-strength = <6>; 2994 bias-disable; 2995 }; 2996 2997 qup_spi13_data_clk: qup-spi13-data-clk-state { 2998 /* MISO, MOSI, CLK */ 2999 pins = "gpio80", "gpio81", "gpio82"; 3000 function = "qup2_se5"; 3001 drive-strength = <6>; 3002 bias-disable; 3003 }; 3004 3005 qup_spi15_cs: qup-spi15-cs-state { 3006 pins = "gpio75"; 3007 function = "qup2_se7"; 3008 drive-strength = <6>; 3009 bias-disable; 3010 }; 3011 3012 qup_spi15_data_clk: qup-spi15-data-clk-state { 3013 /* MISO, MOSI, CLK */ 3014 pins = "gpio72", "gpio106", "gpio74"; 3015 function = "qup2_se7"; 3016 drive-strength = <6>; 3017 bias-disable; 3018 }; 3019 3020 qup_uart7_default: qup-uart7-default-state { 3021 /* TX, RX */ 3022 pins = "gpio26", "gpio27"; 3023 function = "qup1_se7"; 3024 drive-strength = <2>; 3025 bias-disable; 3026 }; 3027 3028 sdc2_sleep: sdc2-sleep-state { 3029 clk-pins { 3030 pins = "sdc2_clk"; 3031 bias-disable; 3032 drive-strength = <2>; 3033 }; 3034 3035 cmd-pins { 3036 pins = "sdc2_cmd"; 3037 bias-pull-up; 3038 drive-strength = <2>; 3039 }; 3040 3041 data-pins { 3042 pins = "sdc2_data"; 3043 bias-pull-up; 3044 drive-strength = <2>; 3045 }; 3046 }; 3047 3048 sdc2_default: sdc2-default-state { 3049 clk-pins { 3050 pins = "sdc2_clk"; 3051 bias-disable; 3052 drive-strength = <16>; 3053 }; 3054 3055 cmd-pins { 3056 pins = "sdc2_cmd"; 3057 bias-pull-up; 3058 drive-strength = <10>; 3059 }; 3060 3061 data-pins { 3062 pins = "sdc2_data"; 3063 bias-pull-up; 3064 drive-strength = <10>; 3065 }; 3066 }; 3067 }; 3068 3069 apps_smmu: iommu@15000000 { 3070 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3071 reg = <0 0x15000000 0 0x100000>; 3072 #iommu-cells = <2>; 3073 #global-interrupts = <1>; 3074 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3171 }; 3172 3173 intc: interrupt-controller@17100000 { 3174 compatible = "arm,gic-v3"; 3175 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3176 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3177 ranges; 3178 #interrupt-cells = <3>; 3179 interrupt-controller; 3180 #redistributor-regions = <1>; 3181 redistributor-stride = <0 0x40000>; 3182 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3183 #address-cells = <2>; 3184 #size-cells = <2>; 3185 3186 gic_its: msi-controller@17140000 { 3187 compatible = "arm,gic-v3-its"; 3188 reg = <0 0x17140000 0 0x20000>; 3189 msi-controller; 3190 #msi-cells = <1>; 3191 }; 3192 }; 3193 3194 timer@17420000 { 3195 compatible = "arm,armv7-timer-mem"; 3196 reg = <0 0x17420000 0 0x1000>; 3197 ranges = <0 0 0 0x20000000>; 3198 #address-cells = <1>; 3199 #size-cells = <1>; 3200 3201 frame@17421000 { 3202 reg = <0x17421000 0x1000>, 3203 <0x17422000 0x1000>; 3204 frame-number = <0>; 3205 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3207 }; 3208 3209 frame@17423000 { 3210 reg = <0x17423000 0x1000>; 3211 frame-number = <1>; 3212 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3213 status = "disabled"; 3214 }; 3215 3216 frame@17425000 { 3217 reg = <0x17425000 0x1000>; 3218 frame-number = <2>; 3219 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3220 status = "disabled"; 3221 }; 3222 3223 frame@17427000 { 3224 reg = <0x17427000 0x1000>; 3225 frame-number = <3>; 3226 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3227 status = "disabled"; 3228 }; 3229 3230 frame@17429000 { 3231 reg = <0x17429000 0x1000>; 3232 frame-number = <4>; 3233 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3234 status = "disabled"; 3235 }; 3236 3237 frame@1742b000 { 3238 reg = <0x1742b000 0x1000>; 3239 frame-number = <5>; 3240 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3241 status = "disabled"; 3242 }; 3243 3244 frame@1742d000 { 3245 reg = <0x1742d000 0x1000>; 3246 frame-number = <6>; 3247 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3248 status = "disabled"; 3249 }; 3250 }; 3251 3252 apps_rsc: rsc@17a00000 { 3253 label = "apps_rsc"; 3254 compatible = "qcom,rpmh-rsc"; 3255 reg = <0 0x17a00000 0 0x10000>, 3256 <0 0x17a10000 0 0x10000>, 3257 <0 0x17a20000 0 0x10000>, 3258 <0 0x17a30000 0 0x10000>; 3259 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3260 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3263 qcom,tcs-offset = <0xd00>; 3264 qcom,drv-id = <2>; 3265 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3266 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3267 3268 apps_bcm_voter: bcm-voter { 3269 compatible = "qcom,bcm-voter"; 3270 }; 3271 3272 rpmhcc: clock-controller { 3273 compatible = "qcom,sm8550-rpmh-clk"; 3274 #clock-cells = <1>; 3275 clock-names = "xo"; 3276 clocks = <&xo_board>; 3277 }; 3278 3279 rpmhpd: power-controller { 3280 compatible = "qcom,sm8550-rpmhpd"; 3281 #power-domain-cells = <1>; 3282 operating-points-v2 = <&rpmhpd_opp_table>; 3283 3284 rpmhpd_opp_table: opp-table { 3285 compatible = "operating-points-v2"; 3286 3287 rpmhpd_opp_ret: opp1 { 3288 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3289 }; 3290 3291 rpmhpd_opp_min_svs: opp2 { 3292 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3293 }; 3294 3295 rpmhpd_opp_low_svs: opp3 { 3296 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3297 }; 3298 3299 rpmhpd_opp_svs: opp4 { 3300 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3301 }; 3302 3303 rpmhpd_opp_svs_l1: opp5 { 3304 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3305 }; 3306 3307 rpmhpd_opp_nom: opp6 { 3308 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3309 }; 3310 3311 rpmhpd_opp_nom_l1: opp7 { 3312 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3313 }; 3314 3315 rpmhpd_opp_nom_l2: opp8 { 3316 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3317 }; 3318 3319 rpmhpd_opp_turbo: opp9 { 3320 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3321 }; 3322 3323 rpmhpd_opp_turbo_l1: opp10 { 3324 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3325 }; 3326 }; 3327 }; 3328 }; 3329 3330 cpufreq_hw: cpufreq@17d91000 { 3331 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3332 reg = <0 0x17d91000 0 0x1000>, 3333 <0 0x17d92000 0 0x1000>, 3334 <0 0x17d93000 0 0x1000>; 3335 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3336 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3337 clock-names = "xo", "alternate"; 3338 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3341 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3342 #freq-domain-cells = <1>; 3343 }; 3344 3345 pmu@24091000 { 3346 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3347 reg = <0 0x24091000 0 0x1000>; 3348 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3349 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3350 3351 operating-points-v2 = <&llcc_bwmon_opp_table>; 3352 3353 llcc_bwmon_opp_table: opp-table { 3354 compatible = "operating-points-v2"; 3355 3356 opp-0 { 3357 opp-peak-kBps = <2086000>; 3358 }; 3359 3360 opp-1 { 3361 opp-peak-kBps = <2929000>; 3362 }; 3363 3364 opp-2 { 3365 opp-peak-kBps = <5931000>; 3366 }; 3367 3368 opp-3 { 3369 opp-peak-kBps = <6515000>; 3370 }; 3371 3372 opp-4 { 3373 opp-peak-kBps = <7980000>; 3374 }; 3375 3376 opp-5 { 3377 opp-peak-kBps = <10437000>; 3378 }; 3379 3380 opp-6 { 3381 opp-peak-kBps = <12157000>; 3382 }; 3383 3384 opp-7 { 3385 opp-peak-kBps = <14060000>; 3386 }; 3387 3388 opp-8 { 3389 opp-peak-kBps = <16113000>; 3390 }; 3391 }; 3392 }; 3393 3394 pmu@240b6400 { 3395 compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; 3396 reg = <0 0x240b6400 0 0x600>; 3397 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3398 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3399 3400 operating-points-v2 = <&cpu_bwmon_opp_table>; 3401 3402 cpu_bwmon_opp_table: opp-table { 3403 compatible = "operating-points-v2"; 3404 3405 opp-0 { 3406 opp-peak-kBps = <4577000>; 3407 }; 3408 3409 opp-1 { 3410 opp-peak-kBps = <7110000>; 3411 }; 3412 3413 opp-2 { 3414 opp-peak-kBps = <9155000>; 3415 }; 3416 3417 opp-3 { 3418 opp-peak-kBps = <12298000>; 3419 }; 3420 3421 opp-4 { 3422 opp-peak-kBps = <14236000>; 3423 }; 3424 3425 opp-5 { 3426 opp-peak-kBps = <16265000>; 3427 }; 3428 }; 3429 }; 3430 3431 gem_noc: interconnect@24100000 { 3432 compatible = "qcom,sm8550-gem-noc"; 3433 reg = <0 0x24100000 0 0xbb800>; 3434 #interconnect-cells = <2>; 3435 qcom,bcm-voters = <&apps_bcm_voter>; 3436 }; 3437 3438 system-cache-controller@25000000 { 3439 compatible = "qcom,sm8550-llcc"; 3440 reg = <0 0x25000000 0 0x800000>, 3441 <0 0x25800000 0 0x200000>; 3442 reg-names = "llcc_base", "llcc_broadcast_base"; 3443 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3444 }; 3445 3446 remoteproc_adsp: remoteproc@30000000 { 3447 compatible = "qcom,sm8550-adsp-pas"; 3448 reg = <0x0 0x30000000 0x0 0x100>; 3449 3450 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3451 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3452 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3453 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3454 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3455 interrupt-names = "wdog", "fatal", "ready", 3456 "handover", "stop-ack"; 3457 3458 clocks = <&rpmhcc RPMH_CXO_CLK>; 3459 clock-names = "xo"; 3460 3461 power-domains = <&rpmhpd SM8550_LCX>, 3462 <&rpmhpd SM8550_LMX>; 3463 power-domain-names = "lcx", "lmx"; 3464 3465 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3466 3467 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3468 3469 qcom,qmp = <&aoss_qmp>; 3470 3471 qcom,smem-states = <&smp2p_adsp_out 0>; 3472 qcom,smem-state-names = "stop"; 3473 3474 status = "disabled"; 3475 3476 remoteproc_adsp_glink: glink-edge { 3477 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3478 IPCC_MPROC_SIGNAL_GLINK_QMP 3479 IRQ_TYPE_EDGE_RISING>; 3480 mboxes = <&ipcc IPCC_CLIENT_LPASS 3481 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3482 3483 label = "lpass"; 3484 qcom,remote-pid = <2>; 3485 3486 fastrpc { 3487 compatible = "qcom,fastrpc"; 3488 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3489 label = "adsp"; 3490 #address-cells = <1>; 3491 #size-cells = <0>; 3492 3493 compute-cb@3 { 3494 compatible = "qcom,fastrpc-compute-cb"; 3495 reg = <3>; 3496 iommus = <&apps_smmu 0x1003 0x80>, 3497 <&apps_smmu 0x1063 0x0>; 3498 }; 3499 3500 compute-cb@4 { 3501 compatible = "qcom,fastrpc-compute-cb"; 3502 reg = <4>; 3503 iommus = <&apps_smmu 0x1004 0x80>, 3504 <&apps_smmu 0x1064 0x0>; 3505 }; 3506 3507 compute-cb@5 { 3508 compatible = "qcom,fastrpc-compute-cb"; 3509 reg = <5>; 3510 iommus = <&apps_smmu 0x1005 0x80>, 3511 <&apps_smmu 0x1065 0x0>; 3512 }; 3513 3514 compute-cb@6 { 3515 compatible = "qcom,fastrpc-compute-cb"; 3516 reg = <6>; 3517 iommus = <&apps_smmu 0x1006 0x80>, 3518 <&apps_smmu 0x1066 0x0>; 3519 }; 3520 3521 compute-cb@7 { 3522 compatible = "qcom,fastrpc-compute-cb"; 3523 reg = <7>; 3524 iommus = <&apps_smmu 0x1007 0x80>, 3525 <&apps_smmu 0x1067 0x0>; 3526 }; 3527 }; 3528 3529 gpr { 3530 compatible = "qcom,gpr"; 3531 qcom,glink-channels = "adsp_apps"; 3532 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3533 qcom,intents = <512 20>; 3534 #address-cells = <1>; 3535 #size-cells = <0>; 3536 3537 q6apm: service@1 { 3538 compatible = "qcom,q6apm"; 3539 reg = <GPR_APM_MODULE_IID>; 3540 #sound-dai-cells = <0>; 3541 qcom,protection-domain = "avs/audio", 3542 "msm/adsp/audio_pd"; 3543 3544 q6apmdai: dais { 3545 compatible = "qcom,q6apm-dais"; 3546 iommus = <&apps_smmu 0x1001 0x80>, 3547 <&apps_smmu 0x1061 0x0>; 3548 }; 3549 3550 q6apmbedai: bedais { 3551 compatible = "qcom,q6apm-lpass-dais"; 3552 #sound-dai-cells = <1>; 3553 }; 3554 }; 3555 3556 q6prm: service@2 { 3557 compatible = "qcom,q6prm"; 3558 reg = <GPR_PRM_MODULE_IID>; 3559 qcom,protection-domain = "avs/audio", 3560 "msm/adsp/audio_pd"; 3561 3562 q6prmcc: clock-controller { 3563 compatible = "qcom,q6prm-lpass-clocks"; 3564 #clock-cells = <2>; 3565 }; 3566 }; 3567 }; 3568 }; 3569 }; 3570 3571 nsp_noc: interconnect@320c0000 { 3572 compatible = "qcom,sm8550-nsp-noc"; 3573 reg = <0 0x320c0000 0 0xe080>; 3574 #interconnect-cells = <2>; 3575 qcom,bcm-voters = <&apps_bcm_voter>; 3576 }; 3577 3578 remoteproc_cdsp: remoteproc@32300000 { 3579 compatible = "qcom,sm8550-cdsp-pas"; 3580 reg = <0x0 0x32300000 0x0 0x1400000>; 3581 3582 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3583 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3584 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3585 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3586 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3587 interrupt-names = "wdog", "fatal", "ready", 3588 "handover", "stop-ack"; 3589 3590 clocks = <&rpmhcc RPMH_CXO_CLK>; 3591 clock-names = "xo"; 3592 3593 power-domains = <&rpmhpd SM8550_CX>, 3594 <&rpmhpd SM8550_MXC>, 3595 <&rpmhpd SM8550_NSP>; 3596 power-domain-names = "cx", "mxc", "nsp"; 3597 3598 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3599 3600 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 3601 3602 qcom,qmp = <&aoss_qmp>; 3603 3604 qcom,smem-states = <&smp2p_cdsp_out 0>; 3605 qcom,smem-state-names = "stop"; 3606 3607 status = "disabled"; 3608 3609 glink-edge { 3610 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3611 IPCC_MPROC_SIGNAL_GLINK_QMP 3612 IRQ_TYPE_EDGE_RISING>; 3613 mboxes = <&ipcc IPCC_CLIENT_CDSP 3614 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3615 3616 label = "cdsp"; 3617 qcom,remote-pid = <5>; 3618 3619 fastrpc { 3620 compatible = "qcom,fastrpc"; 3621 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3622 label = "cdsp"; 3623 #address-cells = <1>; 3624 #size-cells = <0>; 3625 3626 compute-cb@1 { 3627 compatible = "qcom,fastrpc-compute-cb"; 3628 reg = <1>; 3629 iommus = <&apps_smmu 0x1961 0x0>, 3630 <&apps_smmu 0x0c01 0x20>, 3631 <&apps_smmu 0x19c1 0x10>; 3632 }; 3633 3634 compute-cb@2 { 3635 compatible = "qcom,fastrpc-compute-cb"; 3636 reg = <2>; 3637 iommus = <&apps_smmu 0x1962 0x0>, 3638 <&apps_smmu 0x0c02 0x20>, 3639 <&apps_smmu 0x19c2 0x10>; 3640 }; 3641 3642 compute-cb@3 { 3643 compatible = "qcom,fastrpc-compute-cb"; 3644 reg = <3>; 3645 iommus = <&apps_smmu 0x1963 0x0>, 3646 <&apps_smmu 0x0c03 0x20>, 3647 <&apps_smmu 0x19c3 0x10>; 3648 }; 3649 3650 compute-cb@4 { 3651 compatible = "qcom,fastrpc-compute-cb"; 3652 reg = <4>; 3653 iommus = <&apps_smmu 0x1964 0x0>, 3654 <&apps_smmu 0x0c04 0x20>, 3655 <&apps_smmu 0x19c4 0x10>; 3656 }; 3657 3658 compute-cb@5 { 3659 compatible = "qcom,fastrpc-compute-cb"; 3660 reg = <5>; 3661 iommus = <&apps_smmu 0x1965 0x0>, 3662 <&apps_smmu 0x0c05 0x20>, 3663 <&apps_smmu 0x19c5 0x10>; 3664 }; 3665 3666 compute-cb@6 { 3667 compatible = "qcom,fastrpc-compute-cb"; 3668 reg = <6>; 3669 iommus = <&apps_smmu 0x1966 0x0>, 3670 <&apps_smmu 0x0c06 0x20>, 3671 <&apps_smmu 0x19c6 0x10>; 3672 }; 3673 3674 compute-cb@7 { 3675 compatible = "qcom,fastrpc-compute-cb"; 3676 reg = <7>; 3677 iommus = <&apps_smmu 0x1967 0x0>, 3678 <&apps_smmu 0x0c07 0x20>, 3679 <&apps_smmu 0x19c7 0x10>; 3680 }; 3681 3682 compute-cb@8 { 3683 compatible = "qcom,fastrpc-compute-cb"; 3684 reg = <8>; 3685 iommus = <&apps_smmu 0x1968 0x0>, 3686 <&apps_smmu 0x0c08 0x20>, 3687 <&apps_smmu 0x19c8 0x10>; 3688 }; 3689 3690 /* note: secure cb9 in downstream */ 3691 }; 3692 }; 3693 }; 3694 }; 3695 3696 thermal-zones { 3697 aoss0-thermal { 3698 polling-delay-passive = <0>; 3699 polling-delay = <0>; 3700 thermal-sensors = <&tsens0 0>; 3701 3702 trips { 3703 thermal-engine-config { 3704 temperature = <125000>; 3705 hysteresis = <1000>; 3706 type = "passive"; 3707 }; 3708 3709 reset-mon-config { 3710 temperature = <115000>; 3711 hysteresis = <5000>; 3712 type = "passive"; 3713 }; 3714 }; 3715 }; 3716 3717 cpuss0-thermal { 3718 polling-delay-passive = <0>; 3719 polling-delay = <0>; 3720 thermal-sensors = <&tsens0 1>; 3721 3722 trips { 3723 thermal-engine-config { 3724 temperature = <125000>; 3725 hysteresis = <1000>; 3726 type = "passive"; 3727 }; 3728 3729 reset-mon-config { 3730 temperature = <115000>; 3731 hysteresis = <5000>; 3732 type = "passive"; 3733 }; 3734 }; 3735 }; 3736 3737 cpuss1-thermal { 3738 polling-delay-passive = <0>; 3739 polling-delay = <0>; 3740 thermal-sensors = <&tsens0 2>; 3741 3742 trips { 3743 thermal-engine-config { 3744 temperature = <125000>; 3745 hysteresis = <1000>; 3746 type = "passive"; 3747 }; 3748 3749 reset-mon-config { 3750 temperature = <115000>; 3751 hysteresis = <5000>; 3752 type = "passive"; 3753 }; 3754 }; 3755 }; 3756 3757 cpuss2-thermal { 3758 polling-delay-passive = <0>; 3759 polling-delay = <0>; 3760 thermal-sensors = <&tsens0 3>; 3761 3762 trips { 3763 thermal-engine-config { 3764 temperature = <125000>; 3765 hysteresis = <1000>; 3766 type = "passive"; 3767 }; 3768 3769 reset-mon-config { 3770 temperature = <115000>; 3771 hysteresis = <5000>; 3772 type = "passive"; 3773 }; 3774 }; 3775 }; 3776 3777 cpuss3-thermal { 3778 polling-delay-passive = <0>; 3779 polling-delay = <0>; 3780 thermal-sensors = <&tsens0 4>; 3781 3782 trips { 3783 thermal-engine-config { 3784 temperature = <125000>; 3785 hysteresis = <1000>; 3786 type = "passive"; 3787 }; 3788 3789 reset-mon-config { 3790 temperature = <115000>; 3791 hysteresis = <5000>; 3792 type = "passive"; 3793 }; 3794 }; 3795 }; 3796 3797 cpu3-top-thermal { 3798 polling-delay-passive = <0>; 3799 polling-delay = <0>; 3800 thermal-sensors = <&tsens0 5>; 3801 3802 trips { 3803 cpu3_top_alert0: trip-point0 { 3804 temperature = <90000>; 3805 hysteresis = <2000>; 3806 type = "passive"; 3807 }; 3808 3809 cpu3_top_alert1: trip-point1 { 3810 temperature = <95000>; 3811 hysteresis = <2000>; 3812 type = "passive"; 3813 }; 3814 3815 cpu3_top_crit: cpu-critical { 3816 temperature = <110000>; 3817 hysteresis = <1000>; 3818 type = "critical"; 3819 }; 3820 }; 3821 }; 3822 3823 cpu3-bottom-thermal { 3824 polling-delay-passive = <0>; 3825 polling-delay = <0>; 3826 thermal-sensors = <&tsens0 6>; 3827 3828 trips { 3829 cpu3_bottom_alert0: trip-point0 { 3830 temperature = <90000>; 3831 hysteresis = <2000>; 3832 type = "passive"; 3833 }; 3834 3835 cpu3_bottom_alert1: trip-point1 { 3836 temperature = <95000>; 3837 hysteresis = <2000>; 3838 type = "passive"; 3839 }; 3840 3841 cpu3_bottom_crit: cpu-critical { 3842 temperature = <110000>; 3843 hysteresis = <1000>; 3844 type = "critical"; 3845 }; 3846 }; 3847 }; 3848 3849 cpu4-top-thermal { 3850 polling-delay-passive = <0>; 3851 polling-delay = <0>; 3852 thermal-sensors = <&tsens0 7>; 3853 3854 trips { 3855 cpu4_top_alert0: trip-point0 { 3856 temperature = <90000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 cpu4_top_alert1: trip-point1 { 3862 temperature = <95000>; 3863 hysteresis = <2000>; 3864 type = "passive"; 3865 }; 3866 3867 cpu4_top_crit: cpu-critical { 3868 temperature = <110000>; 3869 hysteresis = <1000>; 3870 type = "critical"; 3871 }; 3872 }; 3873 }; 3874 3875 cpu4-bottom-thermal { 3876 polling-delay-passive = <0>; 3877 polling-delay = <0>; 3878 thermal-sensors = <&tsens0 8>; 3879 3880 trips { 3881 cpu4_bottom_alert0: trip-point0 { 3882 temperature = <90000>; 3883 hysteresis = <2000>; 3884 type = "passive"; 3885 }; 3886 3887 cpu4_bottom_alert1: trip-point1 { 3888 temperature = <95000>; 3889 hysteresis = <2000>; 3890 type = "passive"; 3891 }; 3892 3893 cpu4_bottom_crit: cpu-critical { 3894 temperature = <110000>; 3895 hysteresis = <1000>; 3896 type = "critical"; 3897 }; 3898 }; 3899 }; 3900 3901 cpu5-top-thermal { 3902 polling-delay-passive = <0>; 3903 polling-delay = <0>; 3904 thermal-sensors = <&tsens0 9>; 3905 3906 trips { 3907 cpu5_top_alert0: trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu5_top_alert1: trip-point1 { 3914 temperature = <95000>; 3915 hysteresis = <2000>; 3916 type = "passive"; 3917 }; 3918 3919 cpu5_top_crit: cpu-critical { 3920 temperature = <110000>; 3921 hysteresis = <1000>; 3922 type = "critical"; 3923 }; 3924 }; 3925 }; 3926 3927 cpu5-bottom-thermal { 3928 polling-delay-passive = <0>; 3929 polling-delay = <0>; 3930 thermal-sensors = <&tsens0 10>; 3931 3932 trips { 3933 cpu5_bottom_alert0: trip-point0 { 3934 temperature = <90000>; 3935 hysteresis = <2000>; 3936 type = "passive"; 3937 }; 3938 3939 cpu5_bottom_alert1: trip-point1 { 3940 temperature = <95000>; 3941 hysteresis = <2000>; 3942 type = "passive"; 3943 }; 3944 3945 cpu5_bottom_crit: cpu-critical { 3946 temperature = <110000>; 3947 hysteresis = <1000>; 3948 type = "critical"; 3949 }; 3950 }; 3951 }; 3952 3953 cpu6-top-thermal { 3954 polling-delay-passive = <0>; 3955 polling-delay = <0>; 3956 thermal-sensors = <&tsens0 11>; 3957 3958 trips { 3959 cpu6_top_alert0: trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "passive"; 3963 }; 3964 3965 cpu6_top_alert1: trip-point1 { 3966 temperature = <95000>; 3967 hysteresis = <2000>; 3968 type = "passive"; 3969 }; 3970 3971 cpu6_top_crit: cpu-critical { 3972 temperature = <110000>; 3973 hysteresis = <1000>; 3974 type = "critical"; 3975 }; 3976 }; 3977 }; 3978 3979 cpu6-bottom-thermal { 3980 polling-delay-passive = <0>; 3981 polling-delay = <0>; 3982 thermal-sensors = <&tsens0 12>; 3983 3984 trips { 3985 cpu6_bottom_alert0: trip-point0 { 3986 temperature = <90000>; 3987 hysteresis = <2000>; 3988 type = "passive"; 3989 }; 3990 3991 cpu6_bottom_alert1: trip-point1 { 3992 temperature = <95000>; 3993 hysteresis = <2000>; 3994 type = "passive"; 3995 }; 3996 3997 cpu6_bottom_crit: cpu-critical { 3998 temperature = <110000>; 3999 hysteresis = <1000>; 4000 type = "critical"; 4001 }; 4002 }; 4003 }; 4004 4005 cpu7-top-thermal { 4006 polling-delay-passive = <0>; 4007 polling-delay = <0>; 4008 thermal-sensors = <&tsens0 13>; 4009 4010 trips { 4011 cpu7_top_alert0: trip-point0 { 4012 temperature = <90000>; 4013 hysteresis = <2000>; 4014 type = "passive"; 4015 }; 4016 4017 cpu7_top_alert1: trip-point1 { 4018 temperature = <95000>; 4019 hysteresis = <2000>; 4020 type = "passive"; 4021 }; 4022 4023 cpu7_top_crit: cpu-critical { 4024 temperature = <110000>; 4025 hysteresis = <1000>; 4026 type = "critical"; 4027 }; 4028 }; 4029 }; 4030 4031 cpu7-middle-thermal { 4032 polling-delay-passive = <0>; 4033 polling-delay = <0>; 4034 thermal-sensors = <&tsens0 14>; 4035 4036 trips { 4037 cpu7_middle_alert0: trip-point0 { 4038 temperature = <90000>; 4039 hysteresis = <2000>; 4040 type = "passive"; 4041 }; 4042 4043 cpu7_middle_alert1: trip-point1 { 4044 temperature = <95000>; 4045 hysteresis = <2000>; 4046 type = "passive"; 4047 }; 4048 4049 cpu7_middle_crit: cpu-critical { 4050 temperature = <110000>; 4051 hysteresis = <1000>; 4052 type = "critical"; 4053 }; 4054 }; 4055 }; 4056 4057 cpu7-bottom-thermal { 4058 polling-delay-passive = <0>; 4059 polling-delay = <0>; 4060 thermal-sensors = <&tsens0 15>; 4061 4062 trips { 4063 cpu7_bottom_alert0: trip-point0 { 4064 temperature = <90000>; 4065 hysteresis = <2000>; 4066 type = "passive"; 4067 }; 4068 4069 cpu7_bottom_alert1: trip-point1 { 4070 temperature = <95000>; 4071 hysteresis = <2000>; 4072 type = "passive"; 4073 }; 4074 4075 cpu7_bottom_crit: cpu-critical { 4076 temperature = <110000>; 4077 hysteresis = <1000>; 4078 type = "critical"; 4079 }; 4080 }; 4081 }; 4082 4083 aoss1-thermal { 4084 polling-delay-passive = <0>; 4085 polling-delay = <0>; 4086 thermal-sensors = <&tsens1 0>; 4087 4088 trips { 4089 thermal-engine-config { 4090 temperature = <125000>; 4091 hysteresis = <1000>; 4092 type = "passive"; 4093 }; 4094 4095 reset-mon-config { 4096 temperature = <115000>; 4097 hysteresis = <5000>; 4098 type = "passive"; 4099 }; 4100 }; 4101 }; 4102 4103 cpu0-thermal { 4104 polling-delay-passive = <0>; 4105 polling-delay = <0>; 4106 thermal-sensors = <&tsens1 1>; 4107 4108 trips { 4109 cpu0_alert0: trip-point0 { 4110 temperature = <90000>; 4111 hysteresis = <2000>; 4112 type = "passive"; 4113 }; 4114 4115 cpu0_alert1: trip-point1 { 4116 temperature = <95000>; 4117 hysteresis = <2000>; 4118 type = "passive"; 4119 }; 4120 4121 cpu0_crit: cpu-critical { 4122 temperature = <110000>; 4123 hysteresis = <1000>; 4124 type = "critical"; 4125 }; 4126 }; 4127 }; 4128 4129 cpu1-thermal { 4130 polling-delay-passive = <0>; 4131 polling-delay = <0>; 4132 thermal-sensors = <&tsens1 2>; 4133 4134 trips { 4135 cpu1_alert0: trip-point0 { 4136 temperature = <90000>; 4137 hysteresis = <2000>; 4138 type = "passive"; 4139 }; 4140 4141 cpu1_alert1: trip-point1 { 4142 temperature = <95000>; 4143 hysteresis = <2000>; 4144 type = "passive"; 4145 }; 4146 4147 cpu1_crit: cpu-critical { 4148 temperature = <110000>; 4149 hysteresis = <1000>; 4150 type = "critical"; 4151 }; 4152 }; 4153 }; 4154 4155 cpu2-thermal { 4156 polling-delay-passive = <0>; 4157 polling-delay = <0>; 4158 thermal-sensors = <&tsens1 3>; 4159 4160 trips { 4161 cpu2_alert0: trip-point0 { 4162 temperature = <90000>; 4163 hysteresis = <2000>; 4164 type = "passive"; 4165 }; 4166 4167 cpu2_alert1: trip-point1 { 4168 temperature = <95000>; 4169 hysteresis = <2000>; 4170 type = "passive"; 4171 }; 4172 4173 cpu2_crit: cpu-critical { 4174 temperature = <110000>; 4175 hysteresis = <1000>; 4176 type = "critical"; 4177 }; 4178 }; 4179 }; 4180 4181 cdsp0-thermal { 4182 polling-delay-passive = <10>; 4183 polling-delay = <0>; 4184 thermal-sensors = <&tsens2 4>; 4185 4186 trips { 4187 thermal-engine-config { 4188 temperature = <125000>; 4189 hysteresis = <1000>; 4190 type = "passive"; 4191 }; 4192 4193 thermal-hal-config { 4194 temperature = <125000>; 4195 hysteresis = <1000>; 4196 type = "passive"; 4197 }; 4198 4199 reset-mon-config { 4200 temperature = <115000>; 4201 hysteresis = <5000>; 4202 type = "passive"; 4203 }; 4204 4205 cdsp0_junction_config: junction-config { 4206 temperature = <95000>; 4207 hysteresis = <5000>; 4208 type = "passive"; 4209 }; 4210 }; 4211 }; 4212 4213 cdsp1-thermal { 4214 polling-delay-passive = <10>; 4215 polling-delay = <0>; 4216 thermal-sensors = <&tsens2 5>; 4217 4218 trips { 4219 thermal-engine-config { 4220 temperature = <125000>; 4221 hysteresis = <1000>; 4222 type = "passive"; 4223 }; 4224 4225 thermal-hal-config { 4226 temperature = <125000>; 4227 hysteresis = <1000>; 4228 type = "passive"; 4229 }; 4230 4231 reset-mon-config { 4232 temperature = <115000>; 4233 hysteresis = <5000>; 4234 type = "passive"; 4235 }; 4236 4237 cdsp1_junction_config: junction-config { 4238 temperature = <95000>; 4239 hysteresis = <5000>; 4240 type = "passive"; 4241 }; 4242 }; 4243 }; 4244 4245 cdsp2-thermal { 4246 polling-delay-passive = <10>; 4247 polling-delay = <0>; 4248 thermal-sensors = <&tsens2 6>; 4249 4250 trips { 4251 thermal-engine-config { 4252 temperature = <125000>; 4253 hysteresis = <1000>; 4254 type = "passive"; 4255 }; 4256 4257 thermal-hal-config { 4258 temperature = <125000>; 4259 hysteresis = <1000>; 4260 type = "passive"; 4261 }; 4262 4263 reset-mon-config { 4264 temperature = <115000>; 4265 hysteresis = <5000>; 4266 type = "passive"; 4267 }; 4268 4269 cdsp2_junction_config: junction-config { 4270 temperature = <95000>; 4271 hysteresis = <5000>; 4272 type = "passive"; 4273 }; 4274 }; 4275 }; 4276 4277 cdsp3-thermal { 4278 polling-delay-passive = <10>; 4279 polling-delay = <0>; 4280 thermal-sensors = <&tsens2 7>; 4281 4282 trips { 4283 thermal-engine-config { 4284 temperature = <125000>; 4285 hysteresis = <1000>; 4286 type = "passive"; 4287 }; 4288 4289 thermal-hal-config { 4290 temperature = <125000>; 4291 hysteresis = <1000>; 4292 type = "passive"; 4293 }; 4294 4295 reset-mon-config { 4296 temperature = <115000>; 4297 hysteresis = <5000>; 4298 type = "passive"; 4299 }; 4300 4301 cdsp3_junction_config: junction-config { 4302 temperature = <95000>; 4303 hysteresis = <5000>; 4304 type = "passive"; 4305 }; 4306 }; 4307 }; 4308 4309 video-thermal { 4310 polling-delay-passive = <0>; 4311 polling-delay = <0>; 4312 thermal-sensors = <&tsens1 8>; 4313 4314 trips { 4315 thermal-engine-config { 4316 temperature = <125000>; 4317 hysteresis = <1000>; 4318 type = "passive"; 4319 }; 4320 4321 reset-mon-config { 4322 temperature = <115000>; 4323 hysteresis = <5000>; 4324 type = "passive"; 4325 }; 4326 }; 4327 }; 4328 4329 mem-thermal { 4330 polling-delay-passive = <10>; 4331 polling-delay = <0>; 4332 thermal-sensors = <&tsens1 9>; 4333 4334 trips { 4335 thermal-engine-config { 4336 temperature = <125000>; 4337 hysteresis = <1000>; 4338 type = "passive"; 4339 }; 4340 4341 ddr_config0: ddr0-config { 4342 temperature = <90000>; 4343 hysteresis = <5000>; 4344 type = "passive"; 4345 }; 4346 4347 reset-mon-config { 4348 temperature = <115000>; 4349 hysteresis = <5000>; 4350 type = "passive"; 4351 }; 4352 }; 4353 }; 4354 4355 modem0-thermal { 4356 polling-delay-passive = <0>; 4357 polling-delay = <0>; 4358 thermal-sensors = <&tsens1 10>; 4359 4360 trips { 4361 thermal-engine-config { 4362 temperature = <125000>; 4363 hysteresis = <1000>; 4364 type = "passive"; 4365 }; 4366 4367 mdmss0_config0: mdmss0-config0 { 4368 temperature = <102000>; 4369 hysteresis = <3000>; 4370 type = "passive"; 4371 }; 4372 4373 mdmss0_config1: mdmss0-config1 { 4374 temperature = <105000>; 4375 hysteresis = <3000>; 4376 type = "passive"; 4377 }; 4378 4379 reset-mon-config { 4380 temperature = <115000>; 4381 hysteresis = <5000>; 4382 type = "passive"; 4383 }; 4384 }; 4385 }; 4386 4387 modem1-thermal { 4388 polling-delay-passive = <0>; 4389 polling-delay = <0>; 4390 thermal-sensors = <&tsens1 11>; 4391 4392 trips { 4393 thermal-engine-config { 4394 temperature = <125000>; 4395 hysteresis = <1000>; 4396 type = "passive"; 4397 }; 4398 4399 mdmss1_config0: mdmss1-config0 { 4400 temperature = <102000>; 4401 hysteresis = <3000>; 4402 type = "passive"; 4403 }; 4404 4405 mdmss1_config1: mdmss1-config1 { 4406 temperature = <105000>; 4407 hysteresis = <3000>; 4408 type = "passive"; 4409 }; 4410 4411 reset-mon-config { 4412 temperature = <115000>; 4413 hysteresis = <5000>; 4414 type = "passive"; 4415 }; 4416 }; 4417 }; 4418 4419 modem2-thermal { 4420 polling-delay-passive = <0>; 4421 polling-delay = <0>; 4422 thermal-sensors = <&tsens1 12>; 4423 4424 trips { 4425 thermal-engine-config { 4426 temperature = <125000>; 4427 hysteresis = <1000>; 4428 type = "passive"; 4429 }; 4430 4431 mdmss2_config0: mdmss2-config0 { 4432 temperature = <102000>; 4433 hysteresis = <3000>; 4434 type = "passive"; 4435 }; 4436 4437 mdmss2_config1: mdmss2-config1 { 4438 temperature = <105000>; 4439 hysteresis = <3000>; 4440 type = "passive"; 4441 }; 4442 4443 reset-mon-config { 4444 temperature = <115000>; 4445 hysteresis = <5000>; 4446 type = "passive"; 4447 }; 4448 }; 4449 }; 4450 4451 modem3-thermal { 4452 polling-delay-passive = <0>; 4453 polling-delay = <0>; 4454 thermal-sensors = <&tsens1 13>; 4455 4456 trips { 4457 thermal-engine-config { 4458 temperature = <125000>; 4459 hysteresis = <1000>; 4460 type = "passive"; 4461 }; 4462 4463 mdmss3_config0: mdmss3-config0 { 4464 temperature = <102000>; 4465 hysteresis = <3000>; 4466 type = "passive"; 4467 }; 4468 4469 mdmss3_config1: mdmss3-config1 { 4470 temperature = <105000>; 4471 hysteresis = <3000>; 4472 type = "passive"; 4473 }; 4474 4475 reset-mon-config { 4476 temperature = <115000>; 4477 hysteresis = <5000>; 4478 type = "passive"; 4479 }; 4480 }; 4481 }; 4482 4483 camera0-thermal { 4484 polling-delay-passive = <0>; 4485 polling-delay = <0>; 4486 thermal-sensors = <&tsens1 14>; 4487 4488 trips { 4489 thermal-engine-config { 4490 temperature = <125000>; 4491 hysteresis = <1000>; 4492 type = "passive"; 4493 }; 4494 4495 reset-mon-config { 4496 temperature = <115000>; 4497 hysteresis = <5000>; 4498 type = "passive"; 4499 }; 4500 }; 4501 }; 4502 4503 camera1-thermal { 4504 polling-delay-passive = <0>; 4505 polling-delay = <0>; 4506 thermal-sensors = <&tsens1 15>; 4507 4508 trips { 4509 thermal-engine-config { 4510 temperature = <125000>; 4511 hysteresis = <1000>; 4512 type = "passive"; 4513 }; 4514 4515 reset-mon-config { 4516 temperature = <115000>; 4517 hysteresis = <5000>; 4518 type = "passive"; 4519 }; 4520 }; 4521 }; 4522 4523 aoss2-thermal { 4524 polling-delay-passive = <0>; 4525 polling-delay = <0>; 4526 thermal-sensors = <&tsens2 0>; 4527 4528 trips { 4529 thermal-engine-config { 4530 temperature = <125000>; 4531 hysteresis = <1000>; 4532 type = "passive"; 4533 }; 4534 4535 reset-mon-config { 4536 temperature = <115000>; 4537 hysteresis = <5000>; 4538 type = "passive"; 4539 }; 4540 }; 4541 }; 4542 4543 gpuss-0-thermal { 4544 polling-delay-passive = <10>; 4545 polling-delay = <0>; 4546 thermal-sensors = <&tsens2 1>; 4547 4548 trips { 4549 thermal-engine-config { 4550 temperature = <125000>; 4551 hysteresis = <1000>; 4552 type = "passive"; 4553 }; 4554 4555 thermal-hal-config { 4556 temperature = <125000>; 4557 hysteresis = <1000>; 4558 type = "passive"; 4559 }; 4560 4561 reset-mon-config { 4562 temperature = <115000>; 4563 hysteresis = <5000>; 4564 type = "passive"; 4565 }; 4566 4567 gpu0_junction_config: junction-config { 4568 temperature = <95000>; 4569 hysteresis = <5000>; 4570 type = "passive"; 4571 }; 4572 }; 4573 }; 4574 4575 gpuss-1-thermal { 4576 polling-delay-passive = <10>; 4577 polling-delay = <0>; 4578 thermal-sensors = <&tsens2 2>; 4579 4580 trips { 4581 thermal-engine-config { 4582 temperature = <125000>; 4583 hysteresis = <1000>; 4584 type = "passive"; 4585 }; 4586 4587 thermal-hal-config { 4588 temperature = <125000>; 4589 hysteresis = <1000>; 4590 type = "passive"; 4591 }; 4592 4593 reset-mon-config { 4594 temperature = <115000>; 4595 hysteresis = <5000>; 4596 type = "passive"; 4597 }; 4598 4599 gpu1_junction_config: junction-config { 4600 temperature = <95000>; 4601 hysteresis = <5000>; 4602 type = "passive"; 4603 }; 4604 }; 4605 }; 4606 4607 gpuss-2-thermal { 4608 polling-delay-passive = <10>; 4609 polling-delay = <0>; 4610 thermal-sensors = <&tsens2 3>; 4611 4612 trips { 4613 thermal-engine-config { 4614 temperature = <125000>; 4615 hysteresis = <1000>; 4616 type = "passive"; 4617 }; 4618 4619 thermal-hal-config { 4620 temperature = <125000>; 4621 hysteresis = <1000>; 4622 type = "passive"; 4623 }; 4624 4625 reset-mon-config { 4626 temperature = <115000>; 4627 hysteresis = <5000>; 4628 type = "passive"; 4629 }; 4630 4631 gpu2_junction_config: junction-config { 4632 temperature = <95000>; 4633 hysteresis = <5000>; 4634 type = "passive"; 4635 }; 4636 }; 4637 }; 4638 4639 gpuss-3-thermal { 4640 polling-delay-passive = <10>; 4641 polling-delay = <0>; 4642 thermal-sensors = <&tsens2 4>; 4643 4644 trips { 4645 thermal-engine-config { 4646 temperature = <125000>; 4647 hysteresis = <1000>; 4648 type = "passive"; 4649 }; 4650 4651 thermal-hal-config { 4652 temperature = <125000>; 4653 hysteresis = <1000>; 4654 type = "passive"; 4655 }; 4656 4657 reset-mon-config { 4658 temperature = <115000>; 4659 hysteresis = <5000>; 4660 type = "passive"; 4661 }; 4662 4663 gpu3_junction_config: junction-config { 4664 temperature = <95000>; 4665 hysteresis = <5000>; 4666 type = "passive"; 4667 }; 4668 }; 4669 }; 4670 4671 gpuss-4-thermal { 4672 polling-delay-passive = <10>; 4673 polling-delay = <0>; 4674 thermal-sensors = <&tsens2 5>; 4675 4676 trips { 4677 thermal-engine-config { 4678 temperature = <125000>; 4679 hysteresis = <1000>; 4680 type = "passive"; 4681 }; 4682 4683 thermal-hal-config { 4684 temperature = <125000>; 4685 hysteresis = <1000>; 4686 type = "passive"; 4687 }; 4688 4689 reset-mon-config { 4690 temperature = <115000>; 4691 hysteresis = <5000>; 4692 type = "passive"; 4693 }; 4694 4695 gpu4_junction_config: junction-config { 4696 temperature = <95000>; 4697 hysteresis = <5000>; 4698 type = "passive"; 4699 }; 4700 }; 4701 }; 4702 4703 gpuss-5-thermal { 4704 polling-delay-passive = <10>; 4705 polling-delay = <0>; 4706 thermal-sensors = <&tsens2 6>; 4707 4708 trips { 4709 thermal-engine-config { 4710 temperature = <125000>; 4711 hysteresis = <1000>; 4712 type = "passive"; 4713 }; 4714 4715 thermal-hal-config { 4716 temperature = <125000>; 4717 hysteresis = <1000>; 4718 type = "passive"; 4719 }; 4720 4721 reset-mon-config { 4722 temperature = <115000>; 4723 hysteresis = <5000>; 4724 type = "passive"; 4725 }; 4726 4727 gpu5_junction_config: junction-config { 4728 temperature = <95000>; 4729 hysteresis = <5000>; 4730 type = "passive"; 4731 }; 4732 }; 4733 }; 4734 4735 gpuss-6-thermal { 4736 polling-delay-passive = <10>; 4737 polling-delay = <0>; 4738 thermal-sensors = <&tsens2 7>; 4739 4740 trips { 4741 thermal-engine-config { 4742 temperature = <125000>; 4743 hysteresis = <1000>; 4744 type = "passive"; 4745 }; 4746 4747 thermal-hal-config { 4748 temperature = <125000>; 4749 hysteresis = <1000>; 4750 type = "passive"; 4751 }; 4752 4753 reset-mon-config { 4754 temperature = <115000>; 4755 hysteresis = <5000>; 4756 type = "passive"; 4757 }; 4758 4759 gpu6_junction_config: junction-config { 4760 temperature = <95000>; 4761 hysteresis = <5000>; 4762 type = "passive"; 4763 }; 4764 }; 4765 }; 4766 4767 gpuss-7-thermal { 4768 polling-delay-passive = <10>; 4769 polling-delay = <0>; 4770 thermal-sensors = <&tsens2 8>; 4771 4772 trips { 4773 thermal-engine-config { 4774 temperature = <125000>; 4775 hysteresis = <1000>; 4776 type = "passive"; 4777 }; 4778 4779 thermal-hal-config { 4780 temperature = <125000>; 4781 hysteresis = <1000>; 4782 type = "passive"; 4783 }; 4784 4785 reset-mon-config { 4786 temperature = <115000>; 4787 hysteresis = <5000>; 4788 type = "passive"; 4789 }; 4790 4791 gpu7_junction_config: junction-config { 4792 temperature = <95000>; 4793 hysteresis = <5000>; 4794 type = "passive"; 4795 }; 4796 }; 4797 }; 4798 }; 4799 4800 timer { 4801 compatible = "arm,armv8-timer"; 4802 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4803 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4804 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4805 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4806 }; 4807}; 4808