1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-gcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 }; 43 44 bi_tcxo_div2: bi-tcxo-div2-clk { 45 #clock-cells = <0>; 46 compatible = "fixed-factor-clock"; 47 clocks = <&rpmhcc RPMH_CXO_CLK>; 48 clock-mult = <1>; 49 clock-div = <2>; 50 }; 51 52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 53 #clock-cells = <0>; 54 compatible = "fixed-factor-clock"; 55 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 56 clock-mult = <1>; 57 clock-div = <2>; 58 }; 59 60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 CPU0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a510"; 73 reg = <0 0>; 74 clocks = <&cpufreq_hw 0>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_0>; 77 power-domains = <&CPU_PD0>; 78 power-domain-names = "psci"; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 capacity-dmips-mhz = <1024>; 81 dynamic-power-coefficient = <100>; 82 #cooling-cells = <2>; 83 L2_0: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 next-level-cache = <&L3_0>; 88 L3_0: l3-cache { 89 compatible = "cache"; 90 cache-level = <3>; 91 cache-unified; 92 }; 93 }; 94 }; 95 96 CPU1: cpu@100 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a510"; 99 reg = <0 0x100>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_100>; 103 power-domains = <&CPU_PD1>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 capacity-dmips-mhz = <1024>; 107 dynamic-power-coefficient = <100>; 108 #cooling-cells = <2>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU2: cpu@200 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a510"; 120 reg = <0 0x200>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 next-level-cache = <&L2_200>; 124 power-domains = <&CPU_PD2>; 125 power-domain-names = "psci"; 126 qcom,freq-domain = <&cpufreq_hw 0>; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 #cooling-cells = <2>; 130 L2_200: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 next-level-cache = <&L3_0>; 135 }; 136 }; 137 138 CPU3: cpu@300 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a715"; 141 reg = <0 0x300>; 142 clocks = <&cpufreq_hw 1>; 143 enable-method = "psci"; 144 next-level-cache = <&L2_300>; 145 power-domains = <&CPU_PD3>; 146 power-domain-names = "psci"; 147 qcom,freq-domain = <&cpufreq_hw 1>; 148 capacity-dmips-mhz = <1792>; 149 dynamic-power-coefficient = <270>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU4: cpu@400 { 160 device_type = "cpu"; 161 compatible = "arm,cortex-a715"; 162 reg = <0 0x400>; 163 clocks = <&cpufreq_hw 1>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_400>; 166 power-domains = <&CPU_PD4>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 capacity-dmips-mhz = <1792>; 170 dynamic-power-coefficient = <270>; 171 #cooling-cells = <2>; 172 L2_400: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU5: cpu@500 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a710"; 183 reg = <0 0x500>; 184 clocks = <&cpufreq_hw 1>; 185 enable-method = "psci"; 186 next-level-cache = <&L2_500>; 187 power-domains = <&CPU_PD5>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 1>; 190 capacity-dmips-mhz = <1792>; 191 dynamic-power-coefficient = <270>; 192 #cooling-cells = <2>; 193 L2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a710"; 204 reg = <0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 next-level-cache = <&L2_600>; 208 power-domains = <&CPU_PD6>; 209 power-domain-names = "psci"; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 capacity-dmips-mhz = <1792>; 212 dynamic-power-coefficient = <270>; 213 #cooling-cells = <2>; 214 L2_600: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,cortex-x3"; 225 reg = <0 0x700>; 226 clocks = <&cpufreq_hw 2>; 227 enable-method = "psci"; 228 next-level-cache = <&L2_700>; 229 power-domains = <&CPU_PD7>; 230 power-domain-names = "psci"; 231 qcom,freq-domain = <&cpufreq_hw 2>; 232 capacity-dmips-mhz = <1894>; 233 dynamic-power-coefficient = <588>; 234 #cooling-cells = <2>; 235 L2_700: l2-cache { 236 compatible = "cache"; 237 cache-level = <2>; 238 cache-unified; 239 next-level-cache = <&L3_0>; 240 }; 241 }; 242 243 cpu-map { 244 cluster0 { 245 core0 { 246 cpu = <&CPU0>; 247 }; 248 249 core1 { 250 cpu = <&CPU1>; 251 }; 252 253 core2 { 254 cpu = <&CPU2>; 255 }; 256 257 core3 { 258 cpu = <&CPU3>; 259 }; 260 261 core4 { 262 cpu = <&CPU4>; 263 }; 264 265 core5 { 266 cpu = <&CPU5>; 267 }; 268 269 core6 { 270 cpu = <&CPU6>; 271 }; 272 273 core7 { 274 cpu = <&CPU7>; 275 }; 276 }; 277 }; 278 279 idle-states { 280 entry-method = "psci"; 281 282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "silver-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <800>; 287 exit-latency-us = <750>; 288 min-residency-us = <4090>; 289 local-timer-stop; 290 }; 291 292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "gold-rail-power-collapse"; 295 arm,psci-suspend-param = <0x40000004>; 296 entry-latency-us = <600>; 297 exit-latency-us = <1550>; 298 min-residency-us = <4791>; 299 local-timer-stop; 300 }; 301 }; 302 303 domain-idle-states { 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "domain-idle-state"; 306 arm,psci-suspend-param = <0x41000044>; 307 entry-latency-us = <1050>; 308 exit-latency-us = <2500>; 309 min-residency-us = <5309>; 310 }; 311 312 CLUSTER_SLEEP_1: cluster-sleep-1 { 313 compatible = "domain-idle-state"; 314 arm,psci-suspend-param = <0x4100c344>; 315 entry-latency-us = <2700>; 316 exit-latency-us = <3500>; 317 min-residency-us = <13959>; 318 }; 319 }; 320 }; 321 322 firmware { 323 scm: scm { 324 compatible = "qcom,scm-sm8550", "qcom,scm"; 325 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 326 }; 327 }; 328 329 clk_virt: interconnect-0 { 330 compatible = "qcom,sm8550-clk-virt"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 mc_virt: interconnect-1 { 336 compatible = "qcom,sm8550-mc-virt"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 memory@a0000000 { 342 device_type = "memory"; 343 /* We expect the bootloader to fill in the size */ 344 reg = <0 0xa0000000 0 0>; 345 }; 346 347 pmu { 348 compatible = "arm,armv8-pmuv3"; 349 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 350 }; 351 352 psci { 353 compatible = "arm,psci-1.0"; 354 method = "smc"; 355 356 CPU_PD0: power-domain-cpu0 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD>; 359 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 360 }; 361 362 CPU_PD1: power-domain-cpu1 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD>; 365 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 366 }; 367 368 CPU_PD2: power-domain-cpu2 { 369 #power-domain-cells = <0>; 370 power-domains = <&CLUSTER_PD>; 371 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 372 }; 373 374 CPU_PD3: power-domain-cpu3 { 375 #power-domain-cells = <0>; 376 power-domains = <&CLUSTER_PD>; 377 domain-idle-states = <&BIG_CPU_SLEEP_0>; 378 }; 379 380 CPU_PD4: power-domain-cpu4 { 381 #power-domain-cells = <0>; 382 power-domains = <&CLUSTER_PD>; 383 domain-idle-states = <&BIG_CPU_SLEEP_0>; 384 }; 385 386 CPU_PD5: power-domain-cpu5 { 387 #power-domain-cells = <0>; 388 power-domains = <&CLUSTER_PD>; 389 domain-idle-states = <&BIG_CPU_SLEEP_0>; 390 }; 391 392 CPU_PD6: power-domain-cpu6 { 393 #power-domain-cells = <0>; 394 power-domains = <&CLUSTER_PD>; 395 domain-idle-states = <&BIG_CPU_SLEEP_0>; 396 }; 397 398 CPU_PD7: power-domain-cpu7 { 399 #power-domain-cells = <0>; 400 power-domains = <&CLUSTER_PD>; 401 domain-idle-states = <&BIG_CPU_SLEEP_0>; 402 }; 403 404 CLUSTER_PD: power-domain-cluster { 405 #power-domain-cells = <0>; 406 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 407 }; 408 }; 409 410 reserved_memory: reserved-memory { 411 #address-cells = <2>; 412 #size-cells = <2>; 413 ranges; 414 415 hyp_mem: hyp-region@80000000 { 416 reg = <0 0x80000000 0 0xa00000>; 417 no-map; 418 }; 419 420 cpusys_vm_mem: cpusys-vm-region@80a00000 { 421 reg = <0 0x80a00000 0 0x400000>; 422 no-map; 423 }; 424 425 hyp_tags_mem: hyp-tags-region@80e00000 { 426 reg = <0 0x80e00000 0 0x3d0000>; 427 no-map; 428 }; 429 430 xbl_sc_mem: xbl-sc-region@d8100000 { 431 reg = <0 0xd8100000 0 0x40000>; 432 no-map; 433 }; 434 435 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 436 reg = <0 0x811d0000 0 0x30000>; 437 no-map; 438 }; 439 440 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 441 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 442 reg = <0 0x81a00000 0 0x260000>; 443 no-map; 444 }; 445 446 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 447 compatible = "qcom,cmd-db"; 448 reg = <0 0x81c60000 0 0x20000>; 449 no-map; 450 }; 451 452 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 453 aop_config_merged_mem: aop-config-merged-region@81c80000 { 454 reg = <0 0x81c80000 0 0x74000>; 455 no-map; 456 }; 457 458 /* secdata region can be reused by apps */ 459 smem: smem@81d00000 { 460 compatible = "qcom,smem"; 461 reg = <0 0x81d00000 0 0x200000>; 462 hwlocks = <&tcsr_mutex 3>; 463 no-map; 464 }; 465 466 adsp_mhi_mem: adsp-mhi-region@81f00000 { 467 reg = <0 0x81f00000 0 0x20000>; 468 no-map; 469 }; 470 471 global_sync_mem: global-sync-region@82600000 { 472 reg = <0 0x82600000 0 0x100000>; 473 no-map; 474 }; 475 476 tz_stat_mem: tz-stat-region@82700000 { 477 reg = <0 0x82700000 0 0x100000>; 478 no-map; 479 }; 480 481 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 482 reg = <0 0x82800000 0 0x4600000>; 483 no-map; 484 }; 485 486 mpss_mem: mpss-region@8a800000 { 487 reg = <0 0x8a800000 0 0x10800000>; 488 no-map; 489 }; 490 491 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 492 reg = <0 0x9b000000 0 0x80000>; 493 no-map; 494 }; 495 496 ipa_fw_mem: ipa-fw-region@9b080000 { 497 reg = <0 0x9b080000 0 0x10000>; 498 no-map; 499 }; 500 501 ipa_gsi_mem: ipa-gsi-region@9b090000 { 502 reg = <0 0x9b090000 0 0xa000>; 503 no-map; 504 }; 505 506 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 507 reg = <0 0x9b09a000 0 0x2000>; 508 no-map; 509 }; 510 511 spss_region_mem: spss-region@9b100000 { 512 reg = <0 0x9b100000 0 0x180000>; 513 no-map; 514 }; 515 516 /* First part of the "SPU secure shared memory" region */ 517 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 518 reg = <0 0x9b280000 0 0x60000>; 519 no-map; 520 }; 521 522 /* Second part of the "SPU secure shared memory" region */ 523 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 524 reg = <0 0x9b2e0000 0 0x20000>; 525 no-map; 526 }; 527 528 camera_mem: camera-region@9b300000 { 529 reg = <0 0x9b300000 0 0x800000>; 530 no-map; 531 }; 532 533 video_mem: video-region@9bb00000 { 534 reg = <0 0x9bb00000 0 0x700000>; 535 no-map; 536 }; 537 538 cvp_mem: cvp-region@9c200000 { 539 reg = <0 0x9c200000 0 0x700000>; 540 no-map; 541 }; 542 543 cdsp_mem: cdsp-region@9c900000 { 544 reg = <0 0x9c900000 0 0x2000000>; 545 no-map; 546 }; 547 548 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 549 reg = <0 0x9e900000 0 0x80000>; 550 no-map; 551 }; 552 553 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 554 reg = <0 0x9e980000 0 0x80000>; 555 no-map; 556 }; 557 558 adspslpi_mem: adspslpi-region@9ea00000 { 559 reg = <0 0x9ea00000 0 0x4080000>; 560 no-map; 561 }; 562 563 /* uefi region can be reused by apps */ 564 565 /* Linux kernel image is loaded at 0xa8000000 */ 566 567 rmtfs_mem: rmtfs-region@d4a80000 { 568 compatible = "qcom,rmtfs-mem"; 569 reg = <0x0 0xd4a80000 0x0 0x280000>; 570 no-map; 571 572 qcom,client-id = <1>; 573 qcom,vmid = <15>; 574 }; 575 576 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 577 reg = <0 0xd4d00000 0 0x3300000>; 578 no-map; 579 }; 580 581 tz_reserved_mem: tz-reserved-region@d8000000 { 582 reg = <0 0xd8000000 0 0x100000>; 583 no-map; 584 }; 585 586 cpucp_fw_mem: cpucp-fw-region@d8140000 { 587 reg = <0 0xd8140000 0 0x1c0000>; 588 no-map; 589 }; 590 591 qtee_mem: qtee-region@d8300000 { 592 reg = <0 0xd8300000 0 0x500000>; 593 no-map; 594 }; 595 596 ta_mem: ta-region@d8800000 { 597 reg = <0 0xd8800000 0 0x8a00000>; 598 no-map; 599 }; 600 601 tz_tags_mem: tz-tags-region@e1200000 { 602 reg = <0 0xe1200000 0 0x2740000>; 603 no-map; 604 }; 605 606 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 607 reg = <0 0xe6440000 0 0x279000>; 608 no-map; 609 }; 610 611 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 612 reg = <0 0xf3600000 0 0x4aee000>; 613 no-map; 614 }; 615 616 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 617 reg = <0 0xf80ee000 0 0x1000>; 618 no-map; 619 }; 620 621 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 622 reg = <0 0xf80ef000 0 0x9000>; 623 no-map; 624 }; 625 626 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 627 reg = <0 0xf80f8000 0 0x4000>; 628 no-map; 629 }; 630 631 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 632 reg = <0 0xf80fc000 0 0x4000>; 633 no-map; 634 }; 635 636 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 637 reg = <0 0xf8100000 0 0x100000>; 638 no-map; 639 }; 640 641 oem_vm_mem: oem-vm-region@f8400000 { 642 reg = <0 0xf8400000 0 0x4800000>; 643 no-map; 644 }; 645 646 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 647 reg = <0 0xfcc00000 0 0x4000>; 648 no-map; 649 }; 650 651 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 652 reg = <0 0xfcc04000 0 0x100000>; 653 no-map; 654 }; 655 656 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 657 reg = <0 0xfce00000 0 0x2900000>; 658 no-map; 659 }; 660 661 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 662 reg = <0 0xff700000 0 0x100000>; 663 no-map; 664 }; 665 }; 666 667 smp2p-adsp { 668 compatible = "qcom,smp2p"; 669 qcom,smem = <443>, <429>; 670 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 671 IPCC_MPROC_SIGNAL_SMP2P 672 IRQ_TYPE_EDGE_RISING>; 673 mboxes = <&ipcc IPCC_CLIENT_LPASS 674 IPCC_MPROC_SIGNAL_SMP2P>; 675 676 qcom,local-pid = <0>; 677 qcom,remote-pid = <2>; 678 679 smp2p_adsp_out: master-kernel { 680 qcom,entry-name = "master-kernel"; 681 #qcom,smem-state-cells = <1>; 682 }; 683 684 smp2p_adsp_in: slave-kernel { 685 qcom,entry-name = "slave-kernel"; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 }; 690 691 smp2p-cdsp { 692 compatible = "qcom,smp2p"; 693 qcom,smem = <94>, <432>; 694 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 695 IPCC_MPROC_SIGNAL_SMP2P 696 IRQ_TYPE_EDGE_RISING>; 697 mboxes = <&ipcc IPCC_CLIENT_CDSP 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,local-pid = <0>; 701 qcom,remote-pid = <5>; 702 703 smp2p_cdsp_out: master-kernel { 704 qcom,entry-name = "master-kernel"; 705 #qcom,smem-state-cells = <1>; 706 }; 707 708 smp2p_cdsp_in: slave-kernel { 709 qcom,entry-name = "slave-kernel"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 }; 714 715 smp2p-modem { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <435>, <428>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_MPSS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <1>; 726 727 smp2p_modem_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 smp2p_modem_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 738 ipa_smp2p_out: ipa-ap-to-modem { 739 qcom,entry-name = "ipa"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 ipa_smp2p_in: ipa-modem-to-ap { 744 qcom,entry-name = "ipa"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 soc: soc@0 { 751 compatible = "simple-bus"; 752 ranges = <0 0 0 0 0x10 0>; 753 dma-ranges = <0 0 0 0 0x10 0>; 754 755 #address-cells = <2>; 756 #size-cells = <2>; 757 758 gcc: clock-controller@100000 { 759 compatible = "qcom,sm8550-gcc"; 760 reg = <0 0x00100000 0 0x1f4200>; 761 #clock-cells = <1>; 762 #reset-cells = <1>; 763 #power-domain-cells = <1>; 764 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 765 <&pcie0_phy>, 766 <&pcie1_phy>, 767 <&pcie_1_phy_aux_clk>, 768 <&ufs_mem_phy 0>, 769 <&ufs_mem_phy 1>, 770 <&ufs_mem_phy 2>, 771 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 772 }; 773 774 ipcc: mailbox@408000 { 775 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 776 reg = <0 0x00408000 0 0x1000>; 777 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-controller; 779 #interrupt-cells = <3>; 780 #mbox-cells = <2>; 781 }; 782 783 gpi_dma2: dma-controller@800000 { 784 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 785 #dma-cells = <3>; 786 reg = <0 0x00800000 0 0x60000>; 787 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 799 dma-channels = <12>; 800 dma-channel-mask = <0x3e>; 801 iommus = <&apps_smmu 0x436 0>; 802 status = "disabled"; 803 }; 804 805 qupv3_id_1: geniqup@8c0000 { 806 compatible = "qcom,geni-se-qup"; 807 reg = <0 0x008c0000 0 0x2000>; 808 ranges; 809 clock-names = "m-ahb", "s-ahb"; 810 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 811 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 812 iommus = <&apps_smmu 0x423 0>; 813 #address-cells = <2>; 814 #size-cells = <2>; 815 status = "disabled"; 816 817 i2c8: i2c@880000 { 818 compatible = "qcom,geni-i2c"; 819 reg = <0 0x00880000 0 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&qup_i2c8_data_clk>; 824 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 828 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 829 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 830 interconnect-names = "qup-core", "qup-config", "qup-memory"; 831 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 832 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 833 dma-names = "tx", "rx"; 834 status = "disabled"; 835 }; 836 837 spi8: spi@880000 { 838 compatible = "qcom,geni-spi"; 839 reg = <0 0x00880000 0 0x4000>; 840 clock-names = "se"; 841 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 842 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 845 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 846 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 847 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 848 interconnect-names = "qup-core", "qup-config", "qup-memory"; 849 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 850 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 i2c9: i2c@884000 { 858 compatible = "qcom,geni-i2c"; 859 reg = <0 0x00884000 0 0x4000>; 860 clock-names = "se"; 861 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_i2c9_data_clk>; 864 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 868 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 869 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 870 interconnect-names = "qup-core", "qup-config", "qup-memory"; 871 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 872 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 873 dma-names = "tx", "rx"; 874 status = "disabled"; 875 }; 876 877 spi9: spi@884000 { 878 compatible = "qcom,geni-spi"; 879 reg = <0 0x00884000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 882 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 885 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 886 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 887 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 888 interconnect-names = "qup-core", "qup-config", "qup-memory"; 889 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 890 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 891 dma-names = "tx", "rx"; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 status = "disabled"; 895 }; 896 897 i2c10: i2c@888000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0 0x00888000 0 0x4000>; 900 clock-names = "se"; 901 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_i2c10_data_clk>; 904 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 908 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 909 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 910 interconnect-names = "qup-core", "qup-config", "qup-memory"; 911 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 912 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 913 dma-names = "tx", "rx"; 914 status = "disabled"; 915 }; 916 917 spi10: spi@888000 { 918 compatible = "qcom,geni-spi"; 919 reg = <0 0x00888000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 922 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 927 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 928 interconnect-names = "qup-core", "qup-config", "qup-memory"; 929 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 930 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 931 dma-names = "tx", "rx"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 i2c11: i2c@88c000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x0088c000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c11_data_clk>; 944 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 949 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 951 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 952 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 status = "disabled"; 955 }; 956 957 spi11: spi@88c000 { 958 compatible = "qcom,geni-spi"; 959 reg = <0 0x0088c000 0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 962 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 967 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", "qup-memory"; 969 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 970 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 971 dma-names = "tx", "rx"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 i2c12: i2c@890000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00890000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c12_data_clk>; 984 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 989 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 992 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 993 dma-names = "tx", "rx"; 994 status = "disabled"; 995 }; 996 997 spi12: spi@890000 { 998 compatible = "qcom,geni-spi"; 999 reg = <0 0x00890000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1002 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1007 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1009 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1010 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1011 dma-names = "tx", "rx"; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 status = "disabled"; 1015 }; 1016 1017 i2c13: i2c@894000 { 1018 compatible = "qcom,geni-i2c"; 1019 reg = <0 0x00894000 0 0x4000>; 1020 clock-names = "se"; 1021 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_i2c13_data_clk>; 1024 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1028 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1029 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1030 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1031 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1032 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1033 dma-names = "tx", "rx"; 1034 status = "disabled"; 1035 }; 1036 1037 spi13: spi@894000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00894000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1042 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1047 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1049 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1050 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1051 dma-names = "tx", "rx"; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 status = "disabled"; 1055 }; 1056 1057 i2c15: i2c@89c000 { 1058 compatible = "qcom,geni-i2c"; 1059 reg = <0 0x0089c000 0 0x4000>; 1060 clock-names = "se"; 1061 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_i2c15_data_clk>; 1064 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1069 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1070 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1071 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1072 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1073 dma-names = "tx", "rx"; 1074 status = "disabled"; 1075 }; 1076 1077 spi15: spi@89c000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x0089c000 0 0x4000>; 1080 clock-names = "se"; 1081 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1082 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1085 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1087 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1088 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1089 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1090 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 }; 1097 1098 i2c_master_hub_0: geniqup@9c0000 { 1099 compatible = "qcom,geni-se-i2c-master-hub"; 1100 reg = <0x0 0x009c0000 0x0 0x2000>; 1101 clock-names = "s-ahb"; 1102 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1103 #address-cells = <2>; 1104 #size-cells = <2>; 1105 ranges; 1106 status = "disabled"; 1107 1108 i2c_hub_0: i2c@980000 { 1109 compatible = "qcom,geni-i2c-master-hub"; 1110 reg = <0x0 0x00980000 0x0 0x4000>; 1111 clock-names = "se", "core"; 1112 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1113 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&hub_i2c0_data_clk>; 1116 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1120 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1121 interconnect-names = "qup-core", "qup-config"; 1122 status = "disabled"; 1123 }; 1124 1125 i2c_hub_1: i2c@984000 { 1126 compatible = "qcom,geni-i2c-master-hub"; 1127 reg = <0x0 0x00984000 0x0 0x4000>; 1128 clock-names = "se", "core"; 1129 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1130 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&hub_i2c1_data_clk>; 1133 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1137 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1138 interconnect-names = "qup-core", "qup-config"; 1139 status = "disabled"; 1140 }; 1141 1142 i2c_hub_2: i2c@988000 { 1143 compatible = "qcom,geni-i2c-master-hub"; 1144 reg = <0x0 0x00988000 0x0 0x4000>; 1145 clock-names = "se", "core"; 1146 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1147 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&hub_i2c2_data_clk>; 1150 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1155 interconnect-names = "qup-core", "qup-config"; 1156 status = "disabled"; 1157 }; 1158 1159 i2c_hub_3: i2c@98c000 { 1160 compatible = "qcom,geni-i2c-master-hub"; 1161 reg = <0x0 0x0098c000 0x0 0x4000>; 1162 clock-names = "se", "core"; 1163 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1164 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&hub_i2c3_data_clk>; 1167 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 status = "disabled"; 1174 }; 1175 1176 i2c_hub_4: i2c@990000 { 1177 compatible = "qcom,geni-i2c-master-hub"; 1178 reg = <0x0 0x00990000 0x0 0x4000>; 1179 clock-names = "se", "core"; 1180 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1181 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&hub_i2c4_data_clk>; 1184 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1189 interconnect-names = "qup-core", "qup-config"; 1190 status = "disabled"; 1191 }; 1192 1193 i2c_hub_5: i2c@994000 { 1194 compatible = "qcom,geni-i2c-master-hub"; 1195 reg = <0 0x00994000 0 0x4000>; 1196 clock-names = "se", "core"; 1197 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1198 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&hub_i2c5_data_clk>; 1201 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1206 interconnect-names = "qup-core", "qup-config"; 1207 status = "disabled"; 1208 }; 1209 1210 i2c_hub_6: i2c@998000 { 1211 compatible = "qcom,geni-i2c-master-hub"; 1212 reg = <0 0x00998000 0 0x4000>; 1213 clock-names = "se", "core"; 1214 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1215 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&hub_i2c6_data_clk>; 1218 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1222 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1223 interconnect-names = "qup-core", "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c_hub_7: i2c@99c000 { 1228 compatible = "qcom,geni-i2c-master-hub"; 1229 reg = <0 0x0099c000 0 0x4000>; 1230 clock-names = "se", "core"; 1231 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1232 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&hub_i2c7_data_clk>; 1235 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1239 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1240 interconnect-names = "qup-core", "qup-config"; 1241 status = "disabled"; 1242 }; 1243 1244 i2c_hub_8: i2c@9a0000 { 1245 compatible = "qcom,geni-i2c-master-hub"; 1246 reg = <0 0x009a0000 0 0x4000>; 1247 clock-names = "se", "core"; 1248 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1249 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&hub_i2c8_data_clk>; 1252 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1257 interconnect-names = "qup-core", "qup-config"; 1258 status = "disabled"; 1259 }; 1260 1261 i2c_hub_9: i2c@9a4000 { 1262 compatible = "qcom,geni-i2c-master-hub"; 1263 reg = <0 0x009a4000 0 0x4000>; 1264 clock-names = "se", "core"; 1265 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1266 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&hub_i2c9_data_clk>; 1269 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 }; 1278 1279 gpi_dma1: dma-controller@a00000 { 1280 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1281 #dma-cells = <3>; 1282 reg = <0 0x00a00000 0 0x60000>; 1283 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1295 dma-channels = <12>; 1296 dma-channel-mask = <0x1e>; 1297 iommus = <&apps_smmu 0xb6 0>; 1298 status = "disabled"; 1299 }; 1300 1301 qupv3_id_0: geniqup@ac0000 { 1302 compatible = "qcom,geni-se-qup"; 1303 reg = <0 0x00ac0000 0 0x2000>; 1304 ranges; 1305 clock-names = "m-ahb", "s-ahb"; 1306 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1307 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1308 iommus = <&apps_smmu 0xa3 0>; 1309 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1310 interconnect-names = "qup-core"; 1311 #address-cells = <2>; 1312 #size-cells = <2>; 1313 status = "disabled"; 1314 1315 i2c0: i2c@a80000 { 1316 compatible = "qcom,geni-i2c"; 1317 reg = <0 0x00a80000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_i2c0_data_clk>; 1322 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1327 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1328 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1329 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1330 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1331 dma-names = "tx", "rx"; 1332 status = "disabled"; 1333 }; 1334 1335 spi0: spi@a80000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0 0x00a80000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1340 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1344 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1345 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1346 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1347 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1348 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1349 dma-names = "tx", "rx"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 status = "disabled"; 1353 }; 1354 1355 i2c1: i2c@a84000 { 1356 compatible = "qcom,geni-i2c"; 1357 reg = <0 0x00a84000 0 0x4000>; 1358 clock-names = "se"; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_i2c1_data_clk>; 1362 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1366 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1367 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1368 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1369 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1370 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 spi1: spi@a84000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x00a84000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1380 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1383 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1384 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1385 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1386 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1387 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1388 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1389 dma-names = "tx", "rx"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 i2c2: i2c@a88000 { 1396 compatible = "qcom,geni-i2c"; 1397 reg = <0 0x00a88000 0 0x4000>; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_i2c2_data_clk>; 1402 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1406 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1407 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1408 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1409 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1411 dma-names = "tx", "rx"; 1412 status = "disabled"; 1413 }; 1414 1415 spi2: spi@a88000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0 0x00a88000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1420 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1421 pinctrl-names = "default"; 1422 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1423 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1424 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1425 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1426 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1427 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1428 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1429 dma-names = "tx", "rx"; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 status = "disabled"; 1433 }; 1434 1435 i2c3: i2c@a8c000 { 1436 compatible = "qcom,geni-i2c"; 1437 reg = <0 0x00a8c000 0 0x4000>; 1438 clock-names = "se"; 1439 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_i2c3_data_clk>; 1442 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1446 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1447 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1448 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1449 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1450 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1451 dma-names = "tx", "rx"; 1452 status = "disabled"; 1453 }; 1454 1455 spi3: spi@a8c000 { 1456 compatible = "qcom,geni-spi"; 1457 reg = <0 0x00a8c000 0 0x4000>; 1458 clock-names = "se"; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1460 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1465 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1467 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1468 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1469 dma-names = "tx", "rx"; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 i2c4: i2c@a90000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00a90000 0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c4_data_clk>; 1482 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1487 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1489 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1490 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1491 dma-names = "tx", "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 spi4: spi@a90000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0 0x00a90000 0 0x4000>; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1500 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1504 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1505 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1506 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1507 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1508 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1509 dma-names = "tx", "rx"; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 status = "disabled"; 1513 }; 1514 1515 i2c5: i2c@a94000 { 1516 compatible = "qcom,geni-i2c"; 1517 reg = <0 0x00a94000 0 0x4000>; 1518 clock-names = "se"; 1519 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_i2c5_data_clk>; 1522 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1524 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1525 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1526 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1527 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1528 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1529 dma-names = "tx", "rx"; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 spi5: spi@a94000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0 0x00a94000 0 0x4000>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1540 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 i2c6: i2c@a98000 { 1556 compatible = "qcom,geni-i2c"; 1557 reg = <0 0x00a98000 0 0x4000>; 1558 clock-names = "se"; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1560 pinctrl-names = "default"; 1561 pinctrl-0 = <&qup_i2c6_data_clk>; 1562 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1565 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1566 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1567 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1568 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1569 dma-names = "tx", "rx"; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 status = "disabled"; 1573 }; 1574 1575 spi6: spi@a98000 { 1576 compatible = "qcom,geni-spi"; 1577 reg = <0 0x00a98000 0 0x4000>; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1580 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1584 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1585 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1586 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1587 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1588 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1589 dma-names = "tx", "rx"; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 uart7: serial@a9c000 { 1596 compatible = "qcom,geni-debug-uart"; 1597 reg = <0 0x00a9c000 0 0x4000>; 1598 clock-names = "se"; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_uart7_default>; 1602 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1603 interconnect-names = "qup-core", "qup-config"; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1606 status = "disabled"; 1607 }; 1608 }; 1609 1610 cnoc_main: interconnect@1500000 { 1611 compatible = "qcom,sm8550-cnoc-main"; 1612 reg = <0 0x01500000 0 0x13080>; 1613 #interconnect-cells = <2>; 1614 qcom,bcm-voters = <&apps_bcm_voter>; 1615 }; 1616 1617 config_noc: interconnect@1600000 { 1618 compatible = "qcom,sm8550-config-noc"; 1619 reg = <0 0x01600000 0 0x6200>; 1620 #interconnect-cells = <2>; 1621 qcom,bcm-voters = <&apps_bcm_voter>; 1622 }; 1623 1624 system_noc: interconnect@1680000 { 1625 compatible = "qcom,sm8550-system-noc"; 1626 reg = <0 0x01680000 0 0x1d080>; 1627 #interconnect-cells = <2>; 1628 qcom,bcm-voters = <&apps_bcm_voter>; 1629 }; 1630 1631 pcie_noc: interconnect@16c0000 { 1632 compatible = "qcom,sm8550-pcie-anoc"; 1633 reg = <0 0x016c0000 0 0x12200>; 1634 #interconnect-cells = <2>; 1635 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1636 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1637 qcom,bcm-voters = <&apps_bcm_voter>; 1638 }; 1639 1640 aggre1_noc: interconnect@16e0000 { 1641 compatible = "qcom,sm8550-aggre1-noc"; 1642 reg = <0 0x016e0000 0 0x14400>; 1643 #interconnect-cells = <2>; 1644 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1645 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1646 qcom,bcm-voters = <&apps_bcm_voter>; 1647 }; 1648 1649 aggre2_noc: interconnect@1700000 { 1650 compatible = "qcom,sm8550-aggre2-noc"; 1651 reg = <0 0x01700000 0 0x1e400>; 1652 #interconnect-cells = <2>; 1653 clocks = <&rpmhcc RPMH_IPA_CLK>; 1654 qcom,bcm-voters = <&apps_bcm_voter>; 1655 }; 1656 1657 mmss_noc: interconnect@1780000 { 1658 compatible = "qcom,sm8550-mmss-noc"; 1659 reg = <0 0x01780000 0 0x5b800>; 1660 #interconnect-cells = <2>; 1661 qcom,bcm-voters = <&apps_bcm_voter>; 1662 }; 1663 1664 pcie0: pci@1c00000 { 1665 device_type = "pci"; 1666 compatible = "qcom,pcie-sm8550"; 1667 reg = <0 0x01c00000 0 0x3000>, 1668 <0 0x60000000 0 0xf1d>, 1669 <0 0x60000f20 0 0xa8>, 1670 <0 0x60001000 0 0x1000>, 1671 <0 0x60100000 0 0x100000>; 1672 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1673 #address-cells = <3>; 1674 #size-cells = <2>; 1675 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1676 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1677 bus-range = <0x00 0xff>; 1678 1679 dma-coherent; 1680 1681 linux,pci-domain = <0>; 1682 num-lanes = <2>; 1683 1684 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1685 interrupt-names = "msi"; 1686 1687 #interrupt-cells = <1>; 1688 interrupt-map-mask = <0 0 0 0x7>; 1689 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1690 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1691 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1692 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1693 1694 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1695 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1696 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1697 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1698 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1699 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1700 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1701 clock-names = "aux", 1702 "cfg", 1703 "bus_master", 1704 "bus_slave", 1705 "slave_q2a", 1706 "ddrss_sf_tbu", 1707 "noc_aggr"; 1708 1709 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1710 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1711 interconnect-names = "pcie-mem", "cpu-pcie"; 1712 1713 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1714 <0x100 &apps_smmu 0x1401 0x1>; 1715 1716 resets = <&gcc GCC_PCIE_0_BCR>; 1717 reset-names = "pci"; 1718 1719 power-domains = <&gcc PCIE_0_GDSC>; 1720 1721 phys = <&pcie0_phy>; 1722 phy-names = "pciephy"; 1723 1724 status = "disabled"; 1725 }; 1726 1727 pcie0_phy: phy@1c06000 { 1728 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1729 reg = <0 0x01c06000 0 0x2000>; 1730 1731 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1732 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1733 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1734 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1735 <&gcc GCC_PCIE_0_PIPE_CLK>; 1736 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1737 "pipe"; 1738 1739 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1740 reset-names = "phy"; 1741 1742 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1743 assigned-clock-rates = <100000000>; 1744 1745 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1746 1747 #clock-cells = <0>; 1748 clock-output-names = "pcie0_pipe_clk"; 1749 1750 #phy-cells = <0>; 1751 1752 status = "disabled"; 1753 }; 1754 1755 pcie1: pci@1c08000 { 1756 device_type = "pci"; 1757 compatible = "qcom,pcie-sm8550"; 1758 reg = <0x0 0x01c08000 0x0 0x3000>, 1759 <0x0 0x40000000 0x0 0xf1d>, 1760 <0x0 0x40000f20 0x0 0xa8>, 1761 <0x0 0x40001000 0x0 0x1000>, 1762 <0x0 0x40100000 0x0 0x100000>; 1763 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1764 #address-cells = <3>; 1765 #size-cells = <2>; 1766 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1767 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1768 bus-range = <0x00 0xff>; 1769 1770 dma-coherent; 1771 1772 linux,pci-domain = <1>; 1773 num-lanes = <2>; 1774 1775 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1776 interrupt-names = "msi"; 1777 1778 #interrupt-cells = <1>; 1779 interrupt-map-mask = <0 0 0 0x7>; 1780 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1781 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1782 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1783 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1784 1785 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1786 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1787 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1788 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1789 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1790 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1791 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1792 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1793 clock-names = "aux", 1794 "cfg", 1795 "bus_master", 1796 "bus_slave", 1797 "slave_q2a", 1798 "ddrss_sf_tbu", 1799 "noc_aggr", 1800 "cnoc_sf_axi"; 1801 1802 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1803 assigned-clock-rates = <19200000>; 1804 1805 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1807 interconnect-names = "pcie-mem", "cpu-pcie"; 1808 1809 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1810 <0x100 &apps_smmu 0x1481 0x1>; 1811 1812 resets = <&gcc GCC_PCIE_1_BCR>, 1813 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1814 reset-names = "pci", "link_down"; 1815 1816 power-domains = <&gcc PCIE_1_GDSC>; 1817 1818 phys = <&pcie1_phy>; 1819 phy-names = "pciephy"; 1820 1821 status = "disabled"; 1822 }; 1823 1824 pcie1_phy: phy@1c0e000 { 1825 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1826 reg = <0x0 0x01c0e000 0x0 0x2000>; 1827 1828 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1829 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1830 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1831 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1832 <&gcc GCC_PCIE_1_PIPE_CLK>; 1833 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1834 "pipe"; 1835 1836 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1837 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1838 reset-names = "phy", "phy_nocsr"; 1839 1840 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1841 assigned-clock-rates = <100000000>; 1842 1843 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1844 1845 #clock-cells = <0>; 1846 clock-output-names = "pcie1_pipe_clk"; 1847 1848 #phy-cells = <0>; 1849 1850 status = "disabled"; 1851 }; 1852 1853 cryptobam: dma-controller@1dc4000 { 1854 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1855 reg = <0x0 0x01dc4000 0x0 0x28000>; 1856 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1857 #dma-cells = <1>; 1858 qcom,ee = <0>; 1859 qcom,controlled-remotely; 1860 iommus = <&apps_smmu 0x480 0x0>, 1861 <&apps_smmu 0x481 0x0>; 1862 }; 1863 1864 crypto: crypto@1dfa000 { 1865 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1866 reg = <0x0 0x01dfa000 0x0 0x6000>; 1867 dmas = <&cryptobam 4>, <&cryptobam 5>; 1868 dma-names = "rx", "tx"; 1869 iommus = <&apps_smmu 0x480 0x0>, 1870 <&apps_smmu 0x481 0x0>; 1871 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1872 interconnect-names = "memory"; 1873 }; 1874 1875 ufs_mem_phy: phy@1d80000 { 1876 compatible = "qcom,sm8550-qmp-ufs-phy"; 1877 reg = <0x0 0x01d80000 0x0 0x2000>; 1878 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1879 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1880 clock-names = "ref", "ref_aux"; 1881 1882 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1883 1884 resets = <&ufs_mem_hc 0>; 1885 reset-names = "ufsphy"; 1886 1887 #clock-cells = <1>; 1888 #phy-cells = <0>; 1889 1890 status = "disabled"; 1891 }; 1892 1893 ufs_mem_hc: ufs@1d84000 { 1894 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1895 "jedec,ufs-2.0"; 1896 reg = <0x0 0x01d84000 0x0 0x3000>; 1897 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1898 phys = <&ufs_mem_phy>; 1899 phy-names = "ufsphy"; 1900 lanes-per-direction = <2>; 1901 #reset-cells = <1>; 1902 resets = <&gcc GCC_UFS_PHY_BCR>; 1903 reset-names = "rst"; 1904 1905 power-domains = <&gcc UFS_PHY_GDSC>; 1906 required-opps = <&rpmhpd_opp_nom>; 1907 1908 iommus = <&apps_smmu 0x60 0x0>; 1909 dma-coherent; 1910 1911 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1913 1914 interconnect-names = "ufs-ddr", "cpu-ufs"; 1915 clock-names = "core_clk", 1916 "bus_aggr_clk", 1917 "iface_clk", 1918 "core_clk_unipro", 1919 "ref_clk", 1920 "tx_lane0_sync_clk", 1921 "rx_lane0_sync_clk", 1922 "rx_lane1_sync_clk"; 1923 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1924 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1925 <&gcc GCC_UFS_PHY_AHB_CLK>, 1926 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1927 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1928 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1929 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1930 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1931 freq-table-hz = 1932 <75000000 300000000>, 1933 <0 0>, 1934 <0 0>, 1935 <75000000 300000000>, 1936 <100000000 403000000>, 1937 <0 0>, 1938 <0 0>, 1939 <0 0>; 1940 qcom,ice = <&ice>; 1941 1942 status = "disabled"; 1943 }; 1944 1945 ice: crypto@1d88000 { 1946 compatible = "qcom,sm8550-inline-crypto-engine", 1947 "qcom,inline-crypto-engine"; 1948 reg = <0 0x01d88000 0 0x8000>; 1949 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1950 }; 1951 1952 tcsr_mutex: hwlock@1f40000 { 1953 compatible = "qcom,tcsr-mutex"; 1954 reg = <0 0x01f40000 0 0x20000>; 1955 #hwlock-cells = <1>; 1956 }; 1957 1958 tcsr: clock-controller@1fc0000 { 1959 compatible = "qcom,sm8550-tcsr", "syscon"; 1960 reg = <0 0x01fc0000 0 0x30000>; 1961 clocks = <&rpmhcc RPMH_CXO_CLK>; 1962 #clock-cells = <1>; 1963 #reset-cells = <1>; 1964 }; 1965 1966 gpucc: clock-controller@3d90000 { 1967 compatible = "qcom,sm8550-gpucc"; 1968 reg = <0 0x03d90000 0 0xa000>; 1969 clocks = <&bi_tcxo_div2>, 1970 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1971 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1972 #clock-cells = <1>; 1973 #reset-cells = <1>; 1974 #power-domain-cells = <1>; 1975 }; 1976 1977 remoteproc_mpss: remoteproc@4080000 { 1978 compatible = "qcom,sm8550-mpss-pas"; 1979 reg = <0x0 0x04080000 0x0 0x4040>; 1980 1981 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1982 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1983 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1984 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1985 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1986 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1987 interrupt-names = "wdog", "fatal", "ready", "handover", 1988 "stop-ack", "shutdown-ack"; 1989 1990 clocks = <&rpmhcc RPMH_CXO_CLK>; 1991 clock-names = "xo"; 1992 1993 power-domains = <&rpmhpd RPMHPD_CX>, 1994 <&rpmhpd RPMHPD_MSS>; 1995 power-domain-names = "cx", "mss"; 1996 1997 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1998 1999 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2000 2001 qcom,qmp = <&aoss_qmp>; 2002 2003 qcom,smem-states = <&smp2p_modem_out 0>; 2004 qcom,smem-state-names = "stop"; 2005 2006 status = "disabled"; 2007 2008 glink-edge { 2009 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2010 IPCC_MPROC_SIGNAL_GLINK_QMP 2011 IRQ_TYPE_EDGE_RISING>; 2012 mboxes = <&ipcc IPCC_CLIENT_MPSS 2013 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2014 label = "mpss"; 2015 qcom,remote-pid = <1>; 2016 }; 2017 }; 2018 2019 lpass_wsa2macro: codec@6aa0000 { 2020 compatible = "qcom,sm8550-lpass-wsa-macro"; 2021 reg = <0 0x06aa0000 0 0x1000>; 2022 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2023 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2024 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2025 <&lpass_vamacro>; 2026 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2027 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2028 assigned-clock-rates = <19200000>; 2029 2030 #clock-cells = <0>; 2031 clock-output-names = "wsa2-mclk"; 2032 pinctrl-names = "default"; 2033 pinctrl-0 = <&wsa2_swr_active>; 2034 #sound-dai-cells = <1>; 2035 }; 2036 2037 swr3: soundwire-controller@6ab0000 { 2038 compatible = "qcom,soundwire-v2.0.0"; 2039 reg = <0 0x06ab0000 0 0x10000>; 2040 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2041 clocks = <&lpass_wsa2macro>; 2042 clock-names = "iface"; 2043 label = "WSA2"; 2044 2045 qcom,din-ports = <4>; 2046 qcom,dout-ports = <9>; 2047 2048 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2049 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2050 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2051 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2052 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2053 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2054 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2055 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2056 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2057 2058 #address-cells = <2>; 2059 #size-cells = <0>; 2060 #sound-dai-cells = <1>; 2061 status = "disabled"; 2062 }; 2063 2064 lpass_rxmacro: codec@6ac0000 { 2065 compatible = "qcom,sm8550-lpass-rx-macro"; 2066 reg = <0 0x06ac0000 0 0x1000>; 2067 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2068 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2069 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2070 <&lpass_vamacro>; 2071 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2072 2073 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2074 assigned-clock-rates = <19200000>; 2075 2076 #clock-cells = <0>; 2077 clock-output-names = "mclk"; 2078 pinctrl-names = "default"; 2079 pinctrl-0 = <&rx_swr_active>; 2080 #sound-dai-cells = <1>; 2081 }; 2082 2083 swr1: soundwire-controller@6ad0000 { 2084 compatible = "qcom,soundwire-v2.0.0"; 2085 reg = <0 0x06ad0000 0 0x10000>; 2086 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2087 clocks = <&lpass_rxmacro>; 2088 clock-names = "iface"; 2089 label = "RX"; 2090 2091 qcom,din-ports = <0>; 2092 qcom,dout-ports = <10>; 2093 2094 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2095 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2096 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2097 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2098 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2099 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2100 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2101 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2102 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2103 2104 #address-cells = <2>; 2105 #size-cells = <0>; 2106 #sound-dai-cells = <1>; 2107 status = "disabled"; 2108 }; 2109 2110 lpass_txmacro: codec@6ae0000 { 2111 compatible = "qcom,sm8550-lpass-tx-macro"; 2112 reg = <0 0x06ae0000 0 0x1000>; 2113 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2114 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2115 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2116 <&lpass_vamacro>; 2117 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2118 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2119 2120 assigned-clock-rates = <19200000>; 2121 2122 #clock-cells = <0>; 2123 clock-output-names = "mclk"; 2124 pinctrl-names = "default"; 2125 pinctrl-0 = <&tx_swr_active>; 2126 #sound-dai-cells = <1>; 2127 }; 2128 2129 lpass_wsamacro: codec@6b00000 { 2130 compatible = "qcom,sm8550-lpass-wsa-macro"; 2131 reg = <0 0x06b00000 0 0x1000>; 2132 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2133 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2134 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2135 <&lpass_vamacro>; 2136 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2137 2138 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2139 assigned-clock-rates = <19200000>; 2140 2141 #clock-cells = <0>; 2142 clock-output-names = "mclk"; 2143 pinctrl-names = "default"; 2144 pinctrl-0 = <&wsa_swr_active>; 2145 #sound-dai-cells = <1>; 2146 }; 2147 2148 swr0: soundwire-controller@6b10000 { 2149 compatible = "qcom,soundwire-v2.0.0"; 2150 reg = <0 0x06b10000 0 0x10000>; 2151 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2152 clocks = <&lpass_wsamacro>; 2153 clock-names = "iface"; 2154 label = "WSA"; 2155 2156 qcom,din-ports = <4>; 2157 qcom,dout-ports = <9>; 2158 2159 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2160 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2161 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2162 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2163 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2164 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2165 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2166 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2167 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2168 2169 #address-cells = <2>; 2170 #size-cells = <0>; 2171 #sound-dai-cells = <1>; 2172 status = "disabled"; 2173 }; 2174 2175 swr2: soundwire-controller@6d30000 { 2176 compatible = "qcom,soundwire-v2.0.0"; 2177 reg = <0 0x06d30000 0 0x10000>; 2178 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2180 interrupt-names = "core", "wakeup"; 2181 clocks = <&lpass_vamacro>; 2182 clock-names = "iface"; 2183 label = "TX"; 2184 2185 qcom,din-ports = <4>; 2186 qcom,dout-ports = <0>; 2187 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2188 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2189 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2190 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2191 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2192 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2193 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2194 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2195 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2196 2197 #address-cells = <2>; 2198 #size-cells = <0>; 2199 #sound-dai-cells = <1>; 2200 status = "disabled"; 2201 }; 2202 2203 lpass_vamacro: codec@6d44000 { 2204 compatible = "qcom,sm8550-lpass-va-macro"; 2205 reg = <0 0x06d44000 0 0x1000>; 2206 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2207 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2208 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2209 clock-names = "mclk", "macro", "dcodec"; 2210 2211 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2212 assigned-clock-rates = <19200000>; 2213 2214 #clock-cells = <0>; 2215 clock-output-names = "fsgen"; 2216 #sound-dai-cells = <1>; 2217 }; 2218 2219 lpass_tlmm: pinctrl@6e80000 { 2220 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2221 reg = <0 0x06e80000 0 0x20000>, 2222 <0 0x07250000 0 0x10000>; 2223 gpio-controller; 2224 #gpio-cells = <2>; 2225 gpio-ranges = <&lpass_tlmm 0 0 23>; 2226 2227 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2228 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2229 clock-names = "core", "audio"; 2230 2231 tx_swr_active: tx-swr-active-state { 2232 clk-pins { 2233 pins = "gpio0"; 2234 function = "swr_tx_clk"; 2235 drive-strength = <2>; 2236 slew-rate = <1>; 2237 bias-disable; 2238 }; 2239 2240 data-pins { 2241 pins = "gpio1", "gpio2", "gpio14"; 2242 function = "swr_tx_data"; 2243 drive-strength = <2>; 2244 slew-rate = <1>; 2245 bias-bus-hold; 2246 }; 2247 }; 2248 2249 rx_swr_active: rx-swr-active-state { 2250 clk-pins { 2251 pins = "gpio3"; 2252 function = "swr_rx_clk"; 2253 drive-strength = <2>; 2254 slew-rate = <1>; 2255 bias-disable; 2256 }; 2257 2258 data-pins { 2259 pins = "gpio4", "gpio5"; 2260 function = "swr_rx_data"; 2261 drive-strength = <2>; 2262 slew-rate = <1>; 2263 bias-bus-hold; 2264 }; 2265 }; 2266 2267 dmic01_default: dmic01-default-state { 2268 clk-pins { 2269 pins = "gpio6"; 2270 function = "dmic1_clk"; 2271 drive-strength = <8>; 2272 output-high; 2273 }; 2274 2275 data-pins { 2276 pins = "gpio7"; 2277 function = "dmic1_data"; 2278 drive-strength = <8>; 2279 input-enable; 2280 }; 2281 }; 2282 2283 dmic02_default: dmic02-default-state { 2284 clk-pins { 2285 pins = "gpio8"; 2286 function = "dmic2_clk"; 2287 drive-strength = <8>; 2288 output-high; 2289 }; 2290 2291 data-pins { 2292 pins = "gpio9"; 2293 function = "dmic2_data"; 2294 drive-strength = <8>; 2295 input-enable; 2296 }; 2297 }; 2298 2299 wsa_swr_active: wsa-swr-active-state { 2300 clk-pins { 2301 pins = "gpio10"; 2302 function = "wsa_swr_clk"; 2303 drive-strength = <2>; 2304 slew-rate = <1>; 2305 bias-disable; 2306 }; 2307 2308 data-pins { 2309 pins = "gpio11"; 2310 function = "wsa_swr_data"; 2311 drive-strength = <2>; 2312 slew-rate = <1>; 2313 bias-bus-hold; 2314 }; 2315 }; 2316 2317 wsa2_swr_active: wsa2-swr-active-state { 2318 clk-pins { 2319 pins = "gpio15"; 2320 function = "wsa2_swr_clk"; 2321 drive-strength = <2>; 2322 slew-rate = <1>; 2323 bias-disable; 2324 }; 2325 2326 data-pins { 2327 pins = "gpio16"; 2328 function = "wsa2_swr_data"; 2329 drive-strength = <2>; 2330 slew-rate = <1>; 2331 bias-bus-hold; 2332 }; 2333 }; 2334 }; 2335 2336 lpass_lpiaon_noc: interconnect@7400000 { 2337 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2338 reg = <0 0x07400000 0 0x19080>; 2339 #interconnect-cells = <2>; 2340 qcom,bcm-voters = <&apps_bcm_voter>; 2341 }; 2342 2343 lpass_lpicx_noc: interconnect@7430000 { 2344 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2345 reg = <0 0x07430000 0 0x3a200>; 2346 #interconnect-cells = <2>; 2347 qcom,bcm-voters = <&apps_bcm_voter>; 2348 }; 2349 2350 lpass_ag_noc: interconnect@7e40000 { 2351 compatible = "qcom,sm8550-lpass-ag-noc"; 2352 reg = <0 0x07e40000 0 0xe080>; 2353 #interconnect-cells = <2>; 2354 qcom,bcm-voters = <&apps_bcm_voter>; 2355 }; 2356 2357 sdhc_2: mmc@8804000 { 2358 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2359 reg = <0 0x08804000 0 0x1000>; 2360 2361 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2363 interrupt-names = "hc_irq", "pwr_irq"; 2364 2365 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2366 <&gcc GCC_SDCC2_APPS_CLK>, 2367 <&rpmhcc RPMH_CXO_CLK>; 2368 clock-names = "iface", "core", "xo"; 2369 iommus = <&apps_smmu 0x540 0>; 2370 qcom,dll-config = <0x0007642c>; 2371 qcom,ddr-config = <0x80040868>; 2372 power-domains = <&rpmhpd RPMHPD_CX>; 2373 operating-points-v2 = <&sdhc2_opp_table>; 2374 2375 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2376 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2377 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2378 bus-width = <4>; 2379 dma-coherent; 2380 2381 /* Forbid SDR104/SDR50 - broken hw! */ 2382 sdhci-caps-mask = <0x3 0>; 2383 2384 status = "disabled"; 2385 2386 sdhc2_opp_table: opp-table { 2387 compatible = "operating-points-v2"; 2388 2389 opp-19200000 { 2390 opp-hz = /bits/ 64 <19200000>; 2391 required-opps = <&rpmhpd_opp_min_svs>; 2392 }; 2393 2394 opp-50000000 { 2395 opp-hz = /bits/ 64 <50000000>; 2396 required-opps = <&rpmhpd_opp_low_svs>; 2397 }; 2398 2399 opp-100000000 { 2400 opp-hz = /bits/ 64 <100000000>; 2401 required-opps = <&rpmhpd_opp_svs>; 2402 }; 2403 2404 opp-202000000 { 2405 opp-hz = /bits/ 64 <202000000>; 2406 required-opps = <&rpmhpd_opp_svs_l1>; 2407 }; 2408 }; 2409 }; 2410 2411 videocc: clock-controller@aaf0000 { 2412 compatible = "qcom,sm8550-videocc"; 2413 reg = <0 0x0aaf0000 0 0x10000>; 2414 clocks = <&bi_tcxo_div2>, 2415 <&gcc GCC_VIDEO_AHB_CLK>; 2416 power-domains = <&rpmhpd RPMHPD_MMCX>; 2417 required-opps = <&rpmhpd_opp_low_svs>; 2418 #clock-cells = <1>; 2419 #reset-cells = <1>; 2420 #power-domain-cells = <1>; 2421 }; 2422 2423 mdss: display-subsystem@ae00000 { 2424 compatible = "qcom,sm8550-mdss"; 2425 reg = <0 0x0ae00000 0 0x1000>; 2426 reg-names = "mdss"; 2427 2428 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2429 interrupt-controller; 2430 #interrupt-cells = <1>; 2431 2432 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2433 <&gcc GCC_DISP_AHB_CLK>, 2434 <&gcc GCC_DISP_HF_AXI_CLK>, 2435 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2436 2437 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2438 2439 power-domains = <&dispcc MDSS_GDSC>; 2440 2441 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2442 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2443 interconnect-names = "mdp0-mem", "mdp1-mem"; 2444 2445 iommus = <&apps_smmu 0x1c00 0x2>; 2446 2447 #address-cells = <2>; 2448 #size-cells = <2>; 2449 ranges; 2450 2451 status = "disabled"; 2452 2453 mdss_mdp: display-controller@ae01000 { 2454 compatible = "qcom,sm8550-dpu"; 2455 reg = <0 0x0ae01000 0 0x8f000>, 2456 <0 0x0aeb0000 0 0x2008>; 2457 reg-names = "mdp", "vbif"; 2458 2459 interrupt-parent = <&mdss>; 2460 interrupts = <0>; 2461 2462 clocks = <&gcc GCC_DISP_AHB_CLK>, 2463 <&gcc GCC_DISP_HF_AXI_CLK>, 2464 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2465 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2466 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2467 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2468 clock-names = "bus", 2469 "nrt_bus", 2470 "iface", 2471 "lut", 2472 "core", 2473 "vsync"; 2474 2475 power-domains = <&rpmhpd RPMHPD_MMCX>; 2476 2477 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2478 assigned-clock-rates = <19200000>; 2479 2480 operating-points-v2 = <&mdp_opp_table>; 2481 2482 ports { 2483 #address-cells = <1>; 2484 #size-cells = <0>; 2485 2486 port@0 { 2487 reg = <0>; 2488 dpu_intf1_out: endpoint { 2489 remote-endpoint = <&mdss_dsi0_in>; 2490 }; 2491 }; 2492 2493 port@1 { 2494 reg = <1>; 2495 dpu_intf2_out: endpoint { 2496 remote-endpoint = <&mdss_dsi1_in>; 2497 }; 2498 }; 2499 2500 port@2 { 2501 reg = <2>; 2502 dpu_intf0_out: endpoint { 2503 remote-endpoint = <&mdss_dp0_in>; 2504 }; 2505 }; 2506 }; 2507 2508 mdp_opp_table: opp-table { 2509 compatible = "operating-points-v2"; 2510 2511 opp-200000000 { 2512 opp-hz = /bits/ 64 <200000000>; 2513 required-opps = <&rpmhpd_opp_low_svs>; 2514 }; 2515 2516 opp-325000000 { 2517 opp-hz = /bits/ 64 <325000000>; 2518 required-opps = <&rpmhpd_opp_svs>; 2519 }; 2520 2521 opp-375000000 { 2522 opp-hz = /bits/ 64 <375000000>; 2523 required-opps = <&rpmhpd_opp_svs_l1>; 2524 }; 2525 2526 opp-514000000 { 2527 opp-hz = /bits/ 64 <514000000>; 2528 required-opps = <&rpmhpd_opp_nom>; 2529 }; 2530 }; 2531 }; 2532 2533 mdss_dp0: displayport-controller@ae90000 { 2534 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2535 reg = <0 0xae90000 0 0x200>, 2536 <0 0xae90200 0 0x200>, 2537 <0 0xae90400 0 0xc00>, 2538 <0 0xae91000 0 0x400>, 2539 <0 0xae91400 0 0x400>; 2540 interrupt-parent = <&mdss>; 2541 interrupts = <12>; 2542 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2543 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2544 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2545 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2546 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2547 clock-names = "core_iface", 2548 "core_aux", 2549 "ctrl_link", 2550 "ctrl_link_iface", 2551 "stream_pixel"; 2552 2553 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2554 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2555 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2556 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2557 2558 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2559 phy-names = "dp"; 2560 2561 #sound-dai-cells = <0>; 2562 2563 operating-points-v2 = <&dp_opp_table>; 2564 power-domains = <&rpmhpd RPMHPD_MMCX>; 2565 2566 status = "disabled"; 2567 2568 ports { 2569 #address-cells = <1>; 2570 #size-cells = <0>; 2571 2572 port@0 { 2573 reg = <0>; 2574 mdss_dp0_in: endpoint { 2575 remote-endpoint = <&dpu_intf0_out>; 2576 }; 2577 }; 2578 2579 port@1 { 2580 reg = <1>; 2581 mdss_dp0_out: endpoint { 2582 }; 2583 }; 2584 }; 2585 2586 dp_opp_table: opp-table { 2587 compatible = "operating-points-v2"; 2588 2589 opp-162000000 { 2590 opp-hz = /bits/ 64 <162000000>; 2591 required-opps = <&rpmhpd_opp_low_svs_d1>; 2592 }; 2593 2594 opp-270000000 { 2595 opp-hz = /bits/ 64 <270000000>; 2596 required-opps = <&rpmhpd_opp_low_svs>; 2597 }; 2598 2599 opp-540000000 { 2600 opp-hz = /bits/ 64 <540000000>; 2601 required-opps = <&rpmhpd_opp_svs_l1>; 2602 }; 2603 2604 opp-810000000 { 2605 opp-hz = /bits/ 64 <810000000>; 2606 required-opps = <&rpmhpd_opp_nom>; 2607 }; 2608 }; 2609 }; 2610 2611 mdss_dsi0: dsi@ae94000 { 2612 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2613 reg = <0 0x0ae94000 0 0x400>; 2614 reg-names = "dsi_ctrl"; 2615 2616 interrupt-parent = <&mdss>; 2617 interrupts = <4>; 2618 2619 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2620 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2621 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2622 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2623 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2624 <&gcc GCC_DISP_HF_AXI_CLK>; 2625 clock-names = "byte", 2626 "byte_intf", 2627 "pixel", 2628 "core", 2629 "iface", 2630 "bus"; 2631 2632 power-domains = <&rpmhpd RPMHPD_MMCX>; 2633 2634 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2635 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2636 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2637 <&mdss_dsi0_phy 1>; 2638 2639 operating-points-v2 = <&mdss_dsi_opp_table>; 2640 2641 phys = <&mdss_dsi0_phy>; 2642 phy-names = "dsi"; 2643 2644 #address-cells = <1>; 2645 #size-cells = <0>; 2646 2647 status = "disabled"; 2648 2649 ports { 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 2653 port@0 { 2654 reg = <0>; 2655 mdss_dsi0_in: endpoint { 2656 remote-endpoint = <&dpu_intf1_out>; 2657 }; 2658 }; 2659 2660 port@1 { 2661 reg = <1>; 2662 mdss_dsi0_out: endpoint { 2663 }; 2664 }; 2665 }; 2666 2667 mdss_dsi_opp_table: opp-table { 2668 compatible = "operating-points-v2"; 2669 2670 opp-187500000 { 2671 opp-hz = /bits/ 64 <187500000>; 2672 required-opps = <&rpmhpd_opp_low_svs>; 2673 }; 2674 2675 opp-300000000 { 2676 opp-hz = /bits/ 64 <300000000>; 2677 required-opps = <&rpmhpd_opp_svs>; 2678 }; 2679 2680 opp-358000000 { 2681 opp-hz = /bits/ 64 <358000000>; 2682 required-opps = <&rpmhpd_opp_svs_l1>; 2683 }; 2684 }; 2685 }; 2686 2687 mdss_dsi0_phy: phy@ae95000 { 2688 compatible = "qcom,sm8550-dsi-phy-4nm"; 2689 reg = <0 0x0ae95000 0 0x200>, 2690 <0 0x0ae95200 0 0x280>, 2691 <0 0x0ae95500 0 0x400>; 2692 reg-names = "dsi_phy", 2693 "dsi_phy_lane", 2694 "dsi_pll"; 2695 2696 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2697 <&rpmhcc RPMH_CXO_CLK>; 2698 clock-names = "iface", "ref"; 2699 2700 #clock-cells = <1>; 2701 #phy-cells = <0>; 2702 2703 status = "disabled"; 2704 }; 2705 2706 mdss_dsi1: dsi@ae96000 { 2707 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2708 reg = <0 0x0ae96000 0 0x400>; 2709 reg-names = "dsi_ctrl"; 2710 2711 interrupt-parent = <&mdss>; 2712 interrupts = <5>; 2713 2714 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2715 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2716 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2717 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2718 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2719 <&gcc GCC_DISP_HF_AXI_CLK>; 2720 clock-names = "byte", 2721 "byte_intf", 2722 "pixel", 2723 "core", 2724 "iface", 2725 "bus"; 2726 2727 power-domains = <&rpmhpd RPMHPD_MMCX>; 2728 2729 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2730 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2731 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2732 <&mdss_dsi1_phy 1>; 2733 2734 operating-points-v2 = <&mdss_dsi_opp_table>; 2735 2736 phys = <&mdss_dsi1_phy>; 2737 phy-names = "dsi"; 2738 2739 #address-cells = <1>; 2740 #size-cells = <0>; 2741 2742 status = "disabled"; 2743 2744 ports { 2745 #address-cells = <1>; 2746 #size-cells = <0>; 2747 2748 port@0 { 2749 reg = <0>; 2750 mdss_dsi1_in: endpoint { 2751 remote-endpoint = <&dpu_intf2_out>; 2752 }; 2753 }; 2754 2755 port@1 { 2756 reg = <1>; 2757 mdss_dsi1_out: endpoint { 2758 }; 2759 }; 2760 }; 2761 }; 2762 2763 mdss_dsi1_phy: phy@ae97000 { 2764 compatible = "qcom,sm8550-dsi-phy-4nm"; 2765 reg = <0 0x0ae97000 0 0x200>, 2766 <0 0x0ae97200 0 0x280>, 2767 <0 0x0ae97500 0 0x400>; 2768 reg-names = "dsi_phy", 2769 "dsi_phy_lane", 2770 "dsi_pll"; 2771 2772 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2773 <&rpmhcc RPMH_CXO_CLK>; 2774 clock-names = "iface", "ref"; 2775 2776 #clock-cells = <1>; 2777 #phy-cells = <0>; 2778 2779 status = "disabled"; 2780 }; 2781 }; 2782 2783 dispcc: clock-controller@af00000 { 2784 compatible = "qcom,sm8550-dispcc"; 2785 reg = <0 0x0af00000 0 0x20000>; 2786 clocks = <&bi_tcxo_div2>, 2787 <&bi_tcxo_ao_div2>, 2788 <&gcc GCC_DISP_AHB_CLK>, 2789 <&sleep_clk>, 2790 <&mdss_dsi0_phy 0>, 2791 <&mdss_dsi0_phy 1>, 2792 <&mdss_dsi1_phy 0>, 2793 <&mdss_dsi1_phy 1>, 2794 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2795 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2796 <0>, /* dp1 */ 2797 <0>, 2798 <0>, /* dp2 */ 2799 <0>, 2800 <0>, /* dp3 */ 2801 <0>; 2802 power-domains = <&rpmhpd RPMHPD_MMCX>; 2803 required-opps = <&rpmhpd_opp_low_svs>; 2804 #clock-cells = <1>; 2805 #reset-cells = <1>; 2806 #power-domain-cells = <1>; 2807 }; 2808 2809 usb_1_hsphy: phy@88e3000 { 2810 compatible = "qcom,sm8550-snps-eusb2-phy"; 2811 reg = <0x0 0x088e3000 0x0 0x154>; 2812 #phy-cells = <0>; 2813 2814 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2815 clock-names = "ref"; 2816 2817 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2818 2819 status = "disabled"; 2820 }; 2821 2822 usb_dp_qmpphy: phy@88e8000 { 2823 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2824 reg = <0x0 0x088e8000 0x0 0x3000>; 2825 2826 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2827 <&rpmhcc RPMH_CXO_CLK>, 2828 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2829 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2830 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2831 2832 power-domains = <&gcc USB3_PHY_GDSC>; 2833 2834 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2835 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2836 reset-names = "phy", "common"; 2837 2838 #clock-cells = <1>; 2839 #phy-cells = <1>; 2840 2841 status = "disabled"; 2842 2843 ports { 2844 #address-cells = <1>; 2845 #size-cells = <0>; 2846 2847 port@0 { 2848 reg = <0>; 2849 2850 usb_dp_qmpphy_out: endpoint { 2851 }; 2852 }; 2853 2854 port@1 { 2855 reg = <1>; 2856 2857 usb_dp_qmpphy_usb_ss_in: endpoint { 2858 }; 2859 }; 2860 2861 port@2 { 2862 reg = <2>; 2863 2864 usb_dp_qmpphy_dp_in: endpoint { 2865 }; 2866 }; 2867 }; 2868 }; 2869 2870 usb_1: usb@a6f8800 { 2871 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2872 reg = <0x0 0x0a6f8800 0x0 0x400>; 2873 #address-cells = <2>; 2874 #size-cells = <2>; 2875 ranges; 2876 2877 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2878 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2879 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2880 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2881 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2882 <&tcsr TCSR_USB3_CLKREF_EN>; 2883 clock-names = "cfg_noc", 2884 "core", 2885 "iface", 2886 "sleep", 2887 "mock_utmi", 2888 "xo"; 2889 2890 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2891 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2892 assigned-clock-rates = <19200000>, <200000000>; 2893 2894 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2895 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2896 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2897 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2898 interrupt-names = "hs_phy_irq", 2899 "ss_phy_irq", 2900 "dm_hs_phy_irq", 2901 "dp_hs_phy_irq"; 2902 2903 power-domains = <&gcc USB30_PRIM_GDSC>; 2904 required-opps = <&rpmhpd_opp_nom>; 2905 2906 resets = <&gcc GCC_USB30_PRIM_BCR>; 2907 2908 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2909 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2910 interconnect-names = "usb-ddr", "apps-usb"; 2911 2912 status = "disabled"; 2913 2914 usb_1_dwc3: usb@a600000 { 2915 compatible = "snps,dwc3"; 2916 reg = <0x0 0x0a600000 0x0 0xcd00>; 2917 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2918 iommus = <&apps_smmu 0x40 0x0>; 2919 snps,dis_u2_susphy_quirk; 2920 snps,dis_enblslpm_quirk; 2921 snps,usb3_lpm_capable; 2922 phys = <&usb_1_hsphy>, 2923 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2924 phy-names = "usb2-phy", "usb3-phy"; 2925 2926 ports { 2927 #address-cells = <1>; 2928 #size-cells = <0>; 2929 2930 port@0 { 2931 reg = <0>; 2932 2933 usb_1_dwc3_hs: endpoint { 2934 }; 2935 }; 2936 2937 port@1 { 2938 reg = <1>; 2939 2940 usb_1_dwc3_ss: endpoint { 2941 }; 2942 }; 2943 }; 2944 }; 2945 }; 2946 2947 pdc: interrupt-controller@b220000 { 2948 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2949 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2950 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2951 <125 63 1>, <126 716 12>, 2952 <138 251 5>; 2953 #interrupt-cells = <2>; 2954 interrupt-parent = <&intc>; 2955 interrupt-controller; 2956 }; 2957 2958 tsens0: thermal-sensor@c271000 { 2959 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2960 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2961 <0 0x0c222000 0 0x1000>; /* SROT */ 2962 #qcom,sensors = <16>; 2963 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2965 interrupt-names = "uplow", "critical"; 2966 #thermal-sensor-cells = <1>; 2967 }; 2968 2969 tsens1: thermal-sensor@c272000 { 2970 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2971 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2972 <0 0x0c223000 0 0x1000>; /* SROT */ 2973 #qcom,sensors = <16>; 2974 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2976 interrupt-names = "uplow", "critical"; 2977 #thermal-sensor-cells = <1>; 2978 }; 2979 2980 tsens2: thermal-sensor@c273000 { 2981 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2982 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2983 <0 0x0c224000 0 0x1000>; /* SROT */ 2984 #qcom,sensors = <16>; 2985 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2986 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2987 interrupt-names = "uplow", "critical"; 2988 #thermal-sensor-cells = <1>; 2989 }; 2990 2991 aoss_qmp: power-management@c300000 { 2992 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2993 reg = <0 0x0c300000 0 0x400>; 2994 interrupt-parent = <&ipcc>; 2995 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2996 IRQ_TYPE_EDGE_RISING>; 2997 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2998 2999 #clock-cells = <0>; 3000 }; 3001 3002 sram@c3f0000 { 3003 compatible = "qcom,rpmh-stats"; 3004 reg = <0 0x0c3f0000 0 0x400>; 3005 }; 3006 3007 spmi_bus: spmi@c400000 { 3008 compatible = "qcom,spmi-pmic-arb"; 3009 reg = <0 0x0c400000 0 0x3000>, 3010 <0 0x0c500000 0 0x4000000>, 3011 <0 0x0c440000 0 0x80000>, 3012 <0 0x0c4c0000 0 0x20000>, 3013 <0 0x0c42d000 0 0x4000>; 3014 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3015 interrupt-names = "periph_irq"; 3016 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3017 qcom,ee = <0>; 3018 qcom,channel = <0>; 3019 qcom,bus-id = <0>; 3020 #address-cells = <2>; 3021 #size-cells = <0>; 3022 interrupt-controller; 3023 #interrupt-cells = <4>; 3024 }; 3025 3026 tlmm: pinctrl@f100000 { 3027 compatible = "qcom,sm8550-tlmm"; 3028 reg = <0 0x0f100000 0 0x300000>; 3029 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3030 gpio-controller; 3031 #gpio-cells = <2>; 3032 interrupt-controller; 3033 #interrupt-cells = <2>; 3034 gpio-ranges = <&tlmm 0 0 211>; 3035 wakeup-parent = <&pdc>; 3036 3037 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3038 /* SDA, SCL */ 3039 pins = "gpio16", "gpio17"; 3040 function = "i2chub0_se0"; 3041 drive-strength = <2>; 3042 bias-pull-up; 3043 }; 3044 3045 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3046 /* SDA, SCL */ 3047 pins = "gpio18", "gpio19"; 3048 function = "i2chub0_se1"; 3049 drive-strength = <2>; 3050 bias-pull-up; 3051 }; 3052 3053 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3054 /* SDA, SCL */ 3055 pins = "gpio20", "gpio21"; 3056 function = "i2chub0_se2"; 3057 drive-strength = <2>; 3058 bias-pull-up; 3059 }; 3060 3061 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3062 /* SDA, SCL */ 3063 pins = "gpio22", "gpio23"; 3064 function = "i2chub0_se3"; 3065 drive-strength = <2>; 3066 bias-pull-up; 3067 }; 3068 3069 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3070 /* SDA, SCL */ 3071 pins = "gpio4", "gpio5"; 3072 function = "i2chub0_se4"; 3073 drive-strength = <2>; 3074 bias-pull-up; 3075 }; 3076 3077 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3078 /* SDA, SCL */ 3079 pins = "gpio6", "gpio7"; 3080 function = "i2chub0_se5"; 3081 drive-strength = <2>; 3082 bias-pull-up; 3083 }; 3084 3085 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3086 /* SDA, SCL */ 3087 pins = "gpio8", "gpio9"; 3088 function = "i2chub0_se6"; 3089 drive-strength = <2>; 3090 bias-pull-up; 3091 }; 3092 3093 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3094 /* SDA, SCL */ 3095 pins = "gpio10", "gpio11"; 3096 function = "i2chub0_se7"; 3097 drive-strength = <2>; 3098 bias-pull-up; 3099 }; 3100 3101 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3102 /* SDA, SCL */ 3103 pins = "gpio206", "gpio207"; 3104 function = "i2chub0_se8"; 3105 drive-strength = <2>; 3106 bias-pull-up; 3107 }; 3108 3109 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3110 /* SDA, SCL */ 3111 pins = "gpio84", "gpio85"; 3112 function = "i2chub0_se9"; 3113 drive-strength = <2>; 3114 bias-pull-up; 3115 }; 3116 3117 pcie0_default_state: pcie0-default-state { 3118 perst-pins { 3119 pins = "gpio94"; 3120 function = "gpio"; 3121 drive-strength = <2>; 3122 bias-pull-down; 3123 }; 3124 3125 clkreq-pins { 3126 pins = "gpio95"; 3127 function = "pcie0_clk_req_n"; 3128 drive-strength = <2>; 3129 bias-pull-up; 3130 }; 3131 3132 wake-pins { 3133 pins = "gpio96"; 3134 function = "gpio"; 3135 drive-strength = <2>; 3136 bias-pull-up; 3137 }; 3138 }; 3139 3140 pcie1_default_state: pcie1-default-state { 3141 perst-pins { 3142 pins = "gpio97"; 3143 function = "gpio"; 3144 drive-strength = <2>; 3145 bias-pull-down; 3146 }; 3147 3148 clkreq-pins { 3149 pins = "gpio98"; 3150 function = "pcie1_clk_req_n"; 3151 drive-strength = <2>; 3152 bias-pull-up; 3153 }; 3154 3155 wake-pins { 3156 pins = "gpio99"; 3157 function = "gpio"; 3158 drive-strength = <2>; 3159 bias-pull-up; 3160 }; 3161 }; 3162 3163 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3164 /* SDA, SCL */ 3165 pins = "gpio28", "gpio29"; 3166 function = "qup1_se0"; 3167 drive-strength = <2>; 3168 bias-pull-up = <2200>; 3169 }; 3170 3171 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3172 /* SDA, SCL */ 3173 pins = "gpio32", "gpio33"; 3174 function = "qup1_se1"; 3175 drive-strength = <2>; 3176 bias-pull-up = <2200>; 3177 }; 3178 3179 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3180 /* SDA, SCL */ 3181 pins = "gpio36", "gpio37"; 3182 function = "qup1_se2"; 3183 drive-strength = <2>; 3184 bias-pull-up = <2200>; 3185 }; 3186 3187 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3188 /* SDA, SCL */ 3189 pins = "gpio40", "gpio41"; 3190 function = "qup1_se3"; 3191 drive-strength = <2>; 3192 bias-pull-up = <2200>; 3193 }; 3194 3195 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3196 /* SDA, SCL */ 3197 pins = "gpio44", "gpio45"; 3198 function = "qup1_se4"; 3199 drive-strength = <2>; 3200 bias-pull-up = <2200>; 3201 }; 3202 3203 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3204 /* SDA, SCL */ 3205 pins = "gpio52", "gpio53"; 3206 function = "qup1_se5"; 3207 drive-strength = <2>; 3208 bias-pull-up = <2200>; 3209 }; 3210 3211 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3212 /* SDA, SCL */ 3213 pins = "gpio48", "gpio49"; 3214 function = "qup1_se6"; 3215 drive-strength = <2>; 3216 bias-pull-up = <2200>; 3217 }; 3218 3219 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3220 scl-pins { 3221 pins = "gpio57"; 3222 function = "qup2_se0_l1_mira"; 3223 drive-strength = <2>; 3224 bias-pull-up = <2200>; 3225 }; 3226 3227 sda-pins { 3228 pins = "gpio56"; 3229 function = "qup2_se0_l0_mira"; 3230 drive-strength = <2>; 3231 bias-pull-up = <2200>; 3232 }; 3233 }; 3234 3235 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3236 /* SDA, SCL */ 3237 pins = "gpio60", "gpio61"; 3238 function = "qup2_se1"; 3239 drive-strength = <2>; 3240 bias-pull-up = <2200>; 3241 }; 3242 3243 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3244 /* SDA, SCL */ 3245 pins = "gpio64", "gpio65"; 3246 function = "qup2_se2"; 3247 drive-strength = <2>; 3248 bias-pull-up = <2200>; 3249 }; 3250 3251 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3252 /* SDA, SCL */ 3253 pins = "gpio68", "gpio69"; 3254 function = "qup2_se3"; 3255 drive-strength = <2>; 3256 bias-pull-up = <2200>; 3257 }; 3258 3259 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3260 /* SDA, SCL */ 3261 pins = "gpio2", "gpio3"; 3262 function = "qup2_se4"; 3263 drive-strength = <2>; 3264 bias-pull-up = <2200>; 3265 }; 3266 3267 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3268 /* SDA, SCL */ 3269 pins = "gpio80", "gpio81"; 3270 function = "qup2_se5"; 3271 drive-strength = <2>; 3272 bias-pull-up = <2200>; 3273 }; 3274 3275 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3276 /* SDA, SCL */ 3277 pins = "gpio72", "gpio106"; 3278 function = "qup2_se7"; 3279 drive-strength = <2>; 3280 bias-pull-up = <2200>; 3281 }; 3282 3283 qup_spi0_cs: qup-spi0-cs-state { 3284 pins = "gpio31"; 3285 function = "qup1_se0"; 3286 drive-strength = <6>; 3287 bias-disable; 3288 }; 3289 3290 qup_spi0_data_clk: qup-spi0-data-clk-state { 3291 /* MISO, MOSI, CLK */ 3292 pins = "gpio28", "gpio29", "gpio30"; 3293 function = "qup1_se0"; 3294 drive-strength = <6>; 3295 bias-disable; 3296 }; 3297 3298 qup_spi1_cs: qup-spi1-cs-state { 3299 pins = "gpio35"; 3300 function = "qup1_se1"; 3301 drive-strength = <6>; 3302 bias-disable; 3303 }; 3304 3305 qup_spi1_data_clk: qup-spi1-data-clk-state { 3306 /* MISO, MOSI, CLK */ 3307 pins = "gpio32", "gpio33", "gpio34"; 3308 function = "qup1_se1"; 3309 drive-strength = <6>; 3310 bias-disable; 3311 }; 3312 3313 qup_spi2_cs: qup-spi2-cs-state { 3314 pins = "gpio39"; 3315 function = "qup1_se2"; 3316 drive-strength = <6>; 3317 bias-disable; 3318 }; 3319 3320 qup_spi2_data_clk: qup-spi2-data-clk-state { 3321 /* MISO, MOSI, CLK */ 3322 pins = "gpio36", "gpio37", "gpio38"; 3323 function = "qup1_se2"; 3324 drive-strength = <6>; 3325 bias-disable; 3326 }; 3327 3328 qup_spi3_cs: qup-spi3-cs-state { 3329 pins = "gpio43"; 3330 function = "qup1_se3"; 3331 drive-strength = <6>; 3332 bias-disable; 3333 }; 3334 3335 qup_spi3_data_clk: qup-spi3-data-clk-state { 3336 /* MISO, MOSI, CLK */ 3337 pins = "gpio40", "gpio41", "gpio42"; 3338 function = "qup1_se3"; 3339 drive-strength = <6>; 3340 bias-disable; 3341 }; 3342 3343 qup_spi4_cs: qup-spi4-cs-state { 3344 pins = "gpio47"; 3345 function = "qup1_se4"; 3346 drive-strength = <6>; 3347 bias-disable; 3348 }; 3349 3350 qup_spi4_data_clk: qup-spi4-data-clk-state { 3351 /* MISO, MOSI, CLK */ 3352 pins = "gpio44", "gpio45", "gpio46"; 3353 function = "qup1_se4"; 3354 drive-strength = <6>; 3355 bias-disable; 3356 }; 3357 3358 qup_spi5_cs: qup-spi5-cs-state { 3359 pins = "gpio55"; 3360 function = "qup1_se5"; 3361 drive-strength = <6>; 3362 bias-disable; 3363 }; 3364 3365 qup_spi5_data_clk: qup-spi5-data-clk-state { 3366 /* MISO, MOSI, CLK */ 3367 pins = "gpio52", "gpio53", "gpio54"; 3368 function = "qup1_se5"; 3369 drive-strength = <6>; 3370 bias-disable; 3371 }; 3372 3373 qup_spi6_cs: qup-spi6-cs-state { 3374 pins = "gpio51"; 3375 function = "qup1_se6"; 3376 drive-strength = <6>; 3377 bias-disable; 3378 }; 3379 3380 qup_spi6_data_clk: qup-spi6-data-clk-state { 3381 /* MISO, MOSI, CLK */ 3382 pins = "gpio48", "gpio49", "gpio50"; 3383 function = "qup1_se6"; 3384 drive-strength = <6>; 3385 bias-disable; 3386 }; 3387 3388 qup_spi8_cs: qup-spi8-cs-state { 3389 pins = "gpio59"; 3390 function = "qup2_se0_l3_mira"; 3391 drive-strength = <6>; 3392 bias-disable; 3393 }; 3394 3395 qup_spi8_data_clk: qup-spi8-data-clk-state { 3396 /* MISO, MOSI, CLK */ 3397 pins = "gpio56", "gpio57", "gpio58"; 3398 function = "qup2_se0_l2_mira"; 3399 drive-strength = <6>; 3400 bias-disable; 3401 }; 3402 3403 qup_spi9_cs: qup-spi9-cs-state { 3404 pins = "gpio63"; 3405 function = "qup2_se1"; 3406 drive-strength = <6>; 3407 bias-disable; 3408 }; 3409 3410 qup_spi9_data_clk: qup-spi9-data-clk-state { 3411 /* MISO, MOSI, CLK */ 3412 pins = "gpio60", "gpio61", "gpio62"; 3413 function = "qup2_se1"; 3414 drive-strength = <6>; 3415 bias-disable; 3416 }; 3417 3418 qup_spi10_cs: qup-spi10-cs-state { 3419 pins = "gpio67"; 3420 function = "qup2_se2"; 3421 drive-strength = <6>; 3422 bias-disable; 3423 }; 3424 3425 qup_spi10_data_clk: qup-spi10-data-clk-state { 3426 /* MISO, MOSI, CLK */ 3427 pins = "gpio64", "gpio65", "gpio66"; 3428 function = "qup2_se2"; 3429 drive-strength = <6>; 3430 bias-disable; 3431 }; 3432 3433 qup_spi11_cs: qup-spi11-cs-state { 3434 pins = "gpio71"; 3435 function = "qup2_se3"; 3436 drive-strength = <6>; 3437 bias-disable; 3438 }; 3439 3440 qup_spi11_data_clk: qup-spi11-data-clk-state { 3441 /* MISO, MOSI, CLK */ 3442 pins = "gpio68", "gpio69", "gpio70"; 3443 function = "qup2_se3"; 3444 drive-strength = <6>; 3445 bias-disable; 3446 }; 3447 3448 qup_spi12_cs: qup-spi12-cs-state { 3449 pins = "gpio119"; 3450 function = "qup2_se4"; 3451 drive-strength = <6>; 3452 bias-disable; 3453 }; 3454 3455 qup_spi12_data_clk: qup-spi12-data-clk-state { 3456 /* MISO, MOSI, CLK */ 3457 pins = "gpio2", "gpio3", "gpio118"; 3458 function = "qup2_se4"; 3459 drive-strength = <6>; 3460 bias-disable; 3461 }; 3462 3463 qup_spi13_cs: qup-spi13-cs-state { 3464 pins = "gpio83"; 3465 function = "qup2_se5"; 3466 drive-strength = <6>; 3467 bias-disable; 3468 }; 3469 3470 qup_spi13_data_clk: qup-spi13-data-clk-state { 3471 /* MISO, MOSI, CLK */ 3472 pins = "gpio80", "gpio81", "gpio82"; 3473 function = "qup2_se5"; 3474 drive-strength = <6>; 3475 bias-disable; 3476 }; 3477 3478 qup_spi15_cs: qup-spi15-cs-state { 3479 pins = "gpio75"; 3480 function = "qup2_se7"; 3481 drive-strength = <6>; 3482 bias-disable; 3483 }; 3484 3485 qup_spi15_data_clk: qup-spi15-data-clk-state { 3486 /* MISO, MOSI, CLK */ 3487 pins = "gpio72", "gpio106", "gpio74"; 3488 function = "qup2_se7"; 3489 drive-strength = <6>; 3490 bias-disable; 3491 }; 3492 3493 qup_uart7_default: qup-uart7-default-state { 3494 /* TX, RX */ 3495 pins = "gpio26", "gpio27"; 3496 function = "qup1_se7"; 3497 drive-strength = <2>; 3498 bias-disable; 3499 }; 3500 3501 sdc2_sleep: sdc2-sleep-state { 3502 clk-pins { 3503 pins = "sdc2_clk"; 3504 bias-disable; 3505 drive-strength = <2>; 3506 }; 3507 3508 cmd-pins { 3509 pins = "sdc2_cmd"; 3510 bias-pull-up; 3511 drive-strength = <2>; 3512 }; 3513 3514 data-pins { 3515 pins = "sdc2_data"; 3516 bias-pull-up; 3517 drive-strength = <2>; 3518 }; 3519 }; 3520 3521 sdc2_default: sdc2-default-state { 3522 clk-pins { 3523 pins = "sdc2_clk"; 3524 bias-disable; 3525 drive-strength = <16>; 3526 }; 3527 3528 cmd-pins { 3529 pins = "sdc2_cmd"; 3530 bias-pull-up; 3531 drive-strength = <10>; 3532 }; 3533 3534 data-pins { 3535 pins = "sdc2_data"; 3536 bias-pull-up; 3537 drive-strength = <10>; 3538 }; 3539 }; 3540 }; 3541 3542 apps_smmu: iommu@15000000 { 3543 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3544 reg = <0 0x15000000 0 0x100000>; 3545 #iommu-cells = <2>; 3546 #global-interrupts = <1>; 3547 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3557 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3558 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3644 }; 3645 3646 intc: interrupt-controller@17100000 { 3647 compatible = "arm,gic-v3"; 3648 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3649 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3650 ranges; 3651 #interrupt-cells = <3>; 3652 interrupt-controller; 3653 #redistributor-regions = <1>; 3654 redistributor-stride = <0 0x40000>; 3655 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3656 #address-cells = <2>; 3657 #size-cells = <2>; 3658 3659 gic_its: msi-controller@17140000 { 3660 compatible = "arm,gic-v3-its"; 3661 reg = <0 0x17140000 0 0x20000>; 3662 msi-controller; 3663 #msi-cells = <1>; 3664 }; 3665 }; 3666 3667 timer@17420000 { 3668 compatible = "arm,armv7-timer-mem"; 3669 reg = <0 0x17420000 0 0x1000>; 3670 ranges = <0 0 0 0x20000000>; 3671 #address-cells = <1>; 3672 #size-cells = <1>; 3673 3674 frame@17421000 { 3675 reg = <0x17421000 0x1000>, 3676 <0x17422000 0x1000>; 3677 frame-number = <0>; 3678 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3680 }; 3681 3682 frame@17423000 { 3683 reg = <0x17423000 0x1000>; 3684 frame-number = <1>; 3685 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3686 status = "disabled"; 3687 }; 3688 3689 frame@17425000 { 3690 reg = <0x17425000 0x1000>; 3691 frame-number = <2>; 3692 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3693 status = "disabled"; 3694 }; 3695 3696 frame@17427000 { 3697 reg = <0x17427000 0x1000>; 3698 frame-number = <3>; 3699 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3700 status = "disabled"; 3701 }; 3702 3703 frame@17429000 { 3704 reg = <0x17429000 0x1000>; 3705 frame-number = <4>; 3706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3707 status = "disabled"; 3708 }; 3709 3710 frame@1742b000 { 3711 reg = <0x1742b000 0x1000>; 3712 frame-number = <5>; 3713 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3714 status = "disabled"; 3715 }; 3716 3717 frame@1742d000 { 3718 reg = <0x1742d000 0x1000>; 3719 frame-number = <6>; 3720 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3721 status = "disabled"; 3722 }; 3723 }; 3724 3725 apps_rsc: rsc@17a00000 { 3726 label = "apps_rsc"; 3727 compatible = "qcom,rpmh-rsc"; 3728 reg = <0 0x17a00000 0 0x10000>, 3729 <0 0x17a10000 0 0x10000>, 3730 <0 0x17a20000 0 0x10000>, 3731 <0 0x17a30000 0 0x10000>; 3732 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3733 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3736 qcom,tcs-offset = <0xd00>; 3737 qcom,drv-id = <2>; 3738 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3739 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3740 power-domains = <&CLUSTER_PD>; 3741 3742 apps_bcm_voter: bcm-voter { 3743 compatible = "qcom,bcm-voter"; 3744 }; 3745 3746 rpmhcc: clock-controller { 3747 compatible = "qcom,sm8550-rpmh-clk"; 3748 #clock-cells = <1>; 3749 clock-names = "xo"; 3750 clocks = <&xo_board>; 3751 }; 3752 3753 rpmhpd: power-controller { 3754 compatible = "qcom,sm8550-rpmhpd"; 3755 #power-domain-cells = <1>; 3756 operating-points-v2 = <&rpmhpd_opp_table>; 3757 3758 rpmhpd_opp_table: opp-table { 3759 compatible = "operating-points-v2"; 3760 3761 rpmhpd_opp_ret: opp-16 { 3762 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3763 }; 3764 3765 rpmhpd_opp_min_svs: opp-48 { 3766 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3767 }; 3768 3769 rpmhpd_opp_low_svs_d2: opp-52 { 3770 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3771 }; 3772 3773 rpmhpd_opp_low_svs_d1: opp-56 { 3774 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3775 }; 3776 3777 rpmhpd_opp_low_svs_d0: opp-60 { 3778 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3779 }; 3780 3781 rpmhpd_opp_low_svs: opp-64 { 3782 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3783 }; 3784 3785 rpmhpd_opp_low_svs_l1: opp-80 { 3786 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3787 }; 3788 3789 rpmhpd_opp_svs: opp-128 { 3790 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3791 }; 3792 3793 rpmhpd_opp_svs_l0: opp-144 { 3794 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3795 }; 3796 3797 rpmhpd_opp_svs_l1: opp-192 { 3798 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3799 }; 3800 3801 rpmhpd_opp_nom: opp-256 { 3802 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3803 }; 3804 3805 rpmhpd_opp_nom_l1: opp-320 { 3806 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3807 }; 3808 3809 rpmhpd_opp_nom_l2: opp-336 { 3810 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3811 }; 3812 3813 rpmhpd_opp_turbo: opp-384 { 3814 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3815 }; 3816 3817 rpmhpd_opp_turbo_l1: opp-416 { 3818 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3819 }; 3820 }; 3821 }; 3822 }; 3823 3824 cpufreq_hw: cpufreq@17d91000 { 3825 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3826 reg = <0 0x17d91000 0 0x1000>, 3827 <0 0x17d92000 0 0x1000>, 3828 <0 0x17d93000 0 0x1000>; 3829 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3830 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3831 clock-names = "xo", "alternate"; 3832 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3835 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3836 #freq-domain-cells = <1>; 3837 #clock-cells = <1>; 3838 }; 3839 3840 pmu@24091000 { 3841 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3842 reg = <0 0x24091000 0 0x1000>; 3843 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3844 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3845 3846 operating-points-v2 = <&llcc_bwmon_opp_table>; 3847 3848 llcc_bwmon_opp_table: opp-table { 3849 compatible = "operating-points-v2"; 3850 3851 opp-0 { 3852 opp-peak-kBps = <2086000>; 3853 }; 3854 3855 opp-1 { 3856 opp-peak-kBps = <2929000>; 3857 }; 3858 3859 opp-2 { 3860 opp-peak-kBps = <5931000>; 3861 }; 3862 3863 opp-3 { 3864 opp-peak-kBps = <6515000>; 3865 }; 3866 3867 opp-4 { 3868 opp-peak-kBps = <7980000>; 3869 }; 3870 3871 opp-5 { 3872 opp-peak-kBps = <10437000>; 3873 }; 3874 3875 opp-6 { 3876 opp-peak-kBps = <12157000>; 3877 }; 3878 3879 opp-7 { 3880 opp-peak-kBps = <14060000>; 3881 }; 3882 3883 opp-8 { 3884 opp-peak-kBps = <16113000>; 3885 }; 3886 }; 3887 }; 3888 3889 pmu@240b6400 { 3890 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 3891 reg = <0 0x240b6400 0 0x600>; 3892 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3893 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3894 3895 operating-points-v2 = <&cpu_bwmon_opp_table>; 3896 3897 cpu_bwmon_opp_table: opp-table { 3898 compatible = "operating-points-v2"; 3899 3900 opp-0 { 3901 opp-peak-kBps = <4577000>; 3902 }; 3903 3904 opp-1 { 3905 opp-peak-kBps = <7110000>; 3906 }; 3907 3908 opp-2 { 3909 opp-peak-kBps = <9155000>; 3910 }; 3911 3912 opp-3 { 3913 opp-peak-kBps = <12298000>; 3914 }; 3915 3916 opp-4 { 3917 opp-peak-kBps = <14236000>; 3918 }; 3919 3920 opp-5 { 3921 opp-peak-kBps = <16265000>; 3922 }; 3923 }; 3924 }; 3925 3926 gem_noc: interconnect@24100000 { 3927 compatible = "qcom,sm8550-gem-noc"; 3928 reg = <0 0x24100000 0 0xbb800>; 3929 #interconnect-cells = <2>; 3930 qcom,bcm-voters = <&apps_bcm_voter>; 3931 }; 3932 3933 system-cache-controller@25000000 { 3934 compatible = "qcom,sm8550-llcc"; 3935 reg = <0 0x25000000 0 0x200000>, 3936 <0 0x25200000 0 0x200000>, 3937 <0 0x25400000 0 0x200000>, 3938 <0 0x25600000 0 0x200000>, 3939 <0 0x25800000 0 0x200000>; 3940 reg-names = "llcc0_base", 3941 "llcc1_base", 3942 "llcc2_base", 3943 "llcc3_base", 3944 "llcc_broadcast_base"; 3945 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3946 }; 3947 3948 remoteproc_adsp: remoteproc@30000000 { 3949 compatible = "qcom,sm8550-adsp-pas"; 3950 reg = <0x0 0x30000000 0x0 0x100>; 3951 3952 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3953 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3954 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3955 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3956 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3957 interrupt-names = "wdog", "fatal", "ready", 3958 "handover", "stop-ack"; 3959 3960 clocks = <&rpmhcc RPMH_CXO_CLK>; 3961 clock-names = "xo"; 3962 3963 power-domains = <&rpmhpd RPMHPD_LCX>, 3964 <&rpmhpd RPMHPD_LMX>; 3965 power-domain-names = "lcx", "lmx"; 3966 3967 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3968 3969 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3970 3971 qcom,qmp = <&aoss_qmp>; 3972 3973 qcom,smem-states = <&smp2p_adsp_out 0>; 3974 qcom,smem-state-names = "stop"; 3975 3976 status = "disabled"; 3977 3978 remoteproc_adsp_glink: glink-edge { 3979 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3980 IPCC_MPROC_SIGNAL_GLINK_QMP 3981 IRQ_TYPE_EDGE_RISING>; 3982 mboxes = <&ipcc IPCC_CLIENT_LPASS 3983 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3984 3985 label = "lpass"; 3986 qcom,remote-pid = <2>; 3987 3988 fastrpc { 3989 compatible = "qcom,fastrpc"; 3990 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3991 label = "adsp"; 3992 #address-cells = <1>; 3993 #size-cells = <0>; 3994 3995 compute-cb@3 { 3996 compatible = "qcom,fastrpc-compute-cb"; 3997 reg = <3>; 3998 iommus = <&apps_smmu 0x1003 0x80>, 3999 <&apps_smmu 0x1063 0x0>; 4000 }; 4001 4002 compute-cb@4 { 4003 compatible = "qcom,fastrpc-compute-cb"; 4004 reg = <4>; 4005 iommus = <&apps_smmu 0x1004 0x80>, 4006 <&apps_smmu 0x1064 0x0>; 4007 }; 4008 4009 compute-cb@5 { 4010 compatible = "qcom,fastrpc-compute-cb"; 4011 reg = <5>; 4012 iommus = <&apps_smmu 0x1005 0x80>, 4013 <&apps_smmu 0x1065 0x0>; 4014 }; 4015 4016 compute-cb@6 { 4017 compatible = "qcom,fastrpc-compute-cb"; 4018 reg = <6>; 4019 iommus = <&apps_smmu 0x1006 0x80>, 4020 <&apps_smmu 0x1066 0x0>; 4021 }; 4022 4023 compute-cb@7 { 4024 compatible = "qcom,fastrpc-compute-cb"; 4025 reg = <7>; 4026 iommus = <&apps_smmu 0x1007 0x80>, 4027 <&apps_smmu 0x1067 0x0>; 4028 }; 4029 }; 4030 4031 gpr { 4032 compatible = "qcom,gpr"; 4033 qcom,glink-channels = "adsp_apps"; 4034 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4035 qcom,intents = <512 20>; 4036 #address-cells = <1>; 4037 #size-cells = <0>; 4038 4039 q6apm: service@1 { 4040 compatible = "qcom,q6apm"; 4041 reg = <GPR_APM_MODULE_IID>; 4042 #sound-dai-cells = <0>; 4043 qcom,protection-domain = "avs/audio", 4044 "msm/adsp/audio_pd"; 4045 4046 q6apmdai: dais { 4047 compatible = "qcom,q6apm-dais"; 4048 iommus = <&apps_smmu 0x1001 0x80>, 4049 <&apps_smmu 0x1061 0x0>; 4050 }; 4051 4052 q6apmbedai: bedais { 4053 compatible = "qcom,q6apm-lpass-dais"; 4054 #sound-dai-cells = <1>; 4055 }; 4056 }; 4057 4058 q6prm: service@2 { 4059 compatible = "qcom,q6prm"; 4060 reg = <GPR_PRM_MODULE_IID>; 4061 qcom,protection-domain = "avs/audio", 4062 "msm/adsp/audio_pd"; 4063 4064 q6prmcc: clock-controller { 4065 compatible = "qcom,q6prm-lpass-clocks"; 4066 #clock-cells = <2>; 4067 }; 4068 }; 4069 }; 4070 }; 4071 }; 4072 4073 nsp_noc: interconnect@320c0000 { 4074 compatible = "qcom,sm8550-nsp-noc"; 4075 reg = <0 0x320c0000 0 0xe080>; 4076 #interconnect-cells = <2>; 4077 qcom,bcm-voters = <&apps_bcm_voter>; 4078 }; 4079 4080 remoteproc_cdsp: remoteproc@32300000 { 4081 compatible = "qcom,sm8550-cdsp-pas"; 4082 reg = <0x0 0x32300000 0x0 0x1400000>; 4083 4084 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4085 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4086 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4087 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4088 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4089 interrupt-names = "wdog", "fatal", "ready", 4090 "handover", "stop-ack"; 4091 4092 clocks = <&rpmhcc RPMH_CXO_CLK>; 4093 clock-names = "xo"; 4094 4095 power-domains = <&rpmhpd RPMHPD_CX>, 4096 <&rpmhpd RPMHPD_MXC>, 4097 <&rpmhpd RPMHPD_NSP>; 4098 power-domain-names = "cx", "mxc", "nsp"; 4099 4100 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4101 4102 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4103 4104 qcom,qmp = <&aoss_qmp>; 4105 4106 qcom,smem-states = <&smp2p_cdsp_out 0>; 4107 qcom,smem-state-names = "stop"; 4108 4109 status = "disabled"; 4110 4111 glink-edge { 4112 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4113 IPCC_MPROC_SIGNAL_GLINK_QMP 4114 IRQ_TYPE_EDGE_RISING>; 4115 mboxes = <&ipcc IPCC_CLIENT_CDSP 4116 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4117 4118 label = "cdsp"; 4119 qcom,remote-pid = <5>; 4120 4121 fastrpc { 4122 compatible = "qcom,fastrpc"; 4123 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4124 label = "cdsp"; 4125 #address-cells = <1>; 4126 #size-cells = <0>; 4127 4128 compute-cb@1 { 4129 compatible = "qcom,fastrpc-compute-cb"; 4130 reg = <1>; 4131 iommus = <&apps_smmu 0x1961 0x0>, 4132 <&apps_smmu 0x0c01 0x20>, 4133 <&apps_smmu 0x19c1 0x10>; 4134 }; 4135 4136 compute-cb@2 { 4137 compatible = "qcom,fastrpc-compute-cb"; 4138 reg = <2>; 4139 iommus = <&apps_smmu 0x1962 0x0>, 4140 <&apps_smmu 0x0c02 0x20>, 4141 <&apps_smmu 0x19c2 0x10>; 4142 }; 4143 4144 compute-cb@3 { 4145 compatible = "qcom,fastrpc-compute-cb"; 4146 reg = <3>; 4147 iommus = <&apps_smmu 0x1963 0x0>, 4148 <&apps_smmu 0x0c03 0x20>, 4149 <&apps_smmu 0x19c3 0x10>; 4150 }; 4151 4152 compute-cb@4 { 4153 compatible = "qcom,fastrpc-compute-cb"; 4154 reg = <4>; 4155 iommus = <&apps_smmu 0x1964 0x0>, 4156 <&apps_smmu 0x0c04 0x20>, 4157 <&apps_smmu 0x19c4 0x10>; 4158 }; 4159 4160 compute-cb@5 { 4161 compatible = "qcom,fastrpc-compute-cb"; 4162 reg = <5>; 4163 iommus = <&apps_smmu 0x1965 0x0>, 4164 <&apps_smmu 0x0c05 0x20>, 4165 <&apps_smmu 0x19c5 0x10>; 4166 }; 4167 4168 compute-cb@6 { 4169 compatible = "qcom,fastrpc-compute-cb"; 4170 reg = <6>; 4171 iommus = <&apps_smmu 0x1966 0x0>, 4172 <&apps_smmu 0x0c06 0x20>, 4173 <&apps_smmu 0x19c6 0x10>; 4174 }; 4175 4176 compute-cb@7 { 4177 compatible = "qcom,fastrpc-compute-cb"; 4178 reg = <7>; 4179 iommus = <&apps_smmu 0x1967 0x0>, 4180 <&apps_smmu 0x0c07 0x20>, 4181 <&apps_smmu 0x19c7 0x10>; 4182 }; 4183 4184 compute-cb@8 { 4185 compatible = "qcom,fastrpc-compute-cb"; 4186 reg = <8>; 4187 iommus = <&apps_smmu 0x1968 0x0>, 4188 <&apps_smmu 0x0c08 0x20>, 4189 <&apps_smmu 0x19c8 0x10>; 4190 }; 4191 4192 /* note: secure cb9 in downstream */ 4193 }; 4194 }; 4195 }; 4196 }; 4197 4198 thermal-zones { 4199 aoss0-thermal { 4200 polling-delay-passive = <0>; 4201 polling-delay = <0>; 4202 thermal-sensors = <&tsens0 0>; 4203 4204 trips { 4205 thermal-engine-config { 4206 temperature = <125000>; 4207 hysteresis = <1000>; 4208 type = "passive"; 4209 }; 4210 4211 reset-mon-config { 4212 temperature = <115000>; 4213 hysteresis = <5000>; 4214 type = "passive"; 4215 }; 4216 }; 4217 }; 4218 4219 cpuss0-thermal { 4220 polling-delay-passive = <0>; 4221 polling-delay = <0>; 4222 thermal-sensors = <&tsens0 1>; 4223 4224 trips { 4225 thermal-engine-config { 4226 temperature = <125000>; 4227 hysteresis = <1000>; 4228 type = "passive"; 4229 }; 4230 4231 reset-mon-config { 4232 temperature = <115000>; 4233 hysteresis = <5000>; 4234 type = "passive"; 4235 }; 4236 }; 4237 }; 4238 4239 cpuss1-thermal { 4240 polling-delay-passive = <0>; 4241 polling-delay = <0>; 4242 thermal-sensors = <&tsens0 2>; 4243 4244 trips { 4245 thermal-engine-config { 4246 temperature = <125000>; 4247 hysteresis = <1000>; 4248 type = "passive"; 4249 }; 4250 4251 reset-mon-config { 4252 temperature = <115000>; 4253 hysteresis = <5000>; 4254 type = "passive"; 4255 }; 4256 }; 4257 }; 4258 4259 cpuss2-thermal { 4260 polling-delay-passive = <0>; 4261 polling-delay = <0>; 4262 thermal-sensors = <&tsens0 3>; 4263 4264 trips { 4265 thermal-engine-config { 4266 temperature = <125000>; 4267 hysteresis = <1000>; 4268 type = "passive"; 4269 }; 4270 4271 reset-mon-config { 4272 temperature = <115000>; 4273 hysteresis = <5000>; 4274 type = "passive"; 4275 }; 4276 }; 4277 }; 4278 4279 cpuss3-thermal { 4280 polling-delay-passive = <0>; 4281 polling-delay = <0>; 4282 thermal-sensors = <&tsens0 4>; 4283 4284 trips { 4285 thermal-engine-config { 4286 temperature = <125000>; 4287 hysteresis = <1000>; 4288 type = "passive"; 4289 }; 4290 4291 reset-mon-config { 4292 temperature = <115000>; 4293 hysteresis = <5000>; 4294 type = "passive"; 4295 }; 4296 }; 4297 }; 4298 4299 cpu3-top-thermal { 4300 polling-delay-passive = <0>; 4301 polling-delay = <0>; 4302 thermal-sensors = <&tsens0 5>; 4303 4304 trips { 4305 cpu3_top_alert0: trip-point0 { 4306 temperature = <90000>; 4307 hysteresis = <2000>; 4308 type = "passive"; 4309 }; 4310 4311 cpu3_top_alert1: trip-point1 { 4312 temperature = <95000>; 4313 hysteresis = <2000>; 4314 type = "passive"; 4315 }; 4316 4317 cpu3_top_crit: cpu-critical { 4318 temperature = <110000>; 4319 hysteresis = <1000>; 4320 type = "critical"; 4321 }; 4322 }; 4323 }; 4324 4325 cpu3-bottom-thermal { 4326 polling-delay-passive = <0>; 4327 polling-delay = <0>; 4328 thermal-sensors = <&tsens0 6>; 4329 4330 trips { 4331 cpu3_bottom_alert0: trip-point0 { 4332 temperature = <90000>; 4333 hysteresis = <2000>; 4334 type = "passive"; 4335 }; 4336 4337 cpu3_bottom_alert1: trip-point1 { 4338 temperature = <95000>; 4339 hysteresis = <2000>; 4340 type = "passive"; 4341 }; 4342 4343 cpu3_bottom_crit: cpu-critical { 4344 temperature = <110000>; 4345 hysteresis = <1000>; 4346 type = "critical"; 4347 }; 4348 }; 4349 }; 4350 4351 cpu4-top-thermal { 4352 polling-delay-passive = <0>; 4353 polling-delay = <0>; 4354 thermal-sensors = <&tsens0 7>; 4355 4356 trips { 4357 cpu4_top_alert0: trip-point0 { 4358 temperature = <90000>; 4359 hysteresis = <2000>; 4360 type = "passive"; 4361 }; 4362 4363 cpu4_top_alert1: trip-point1 { 4364 temperature = <95000>; 4365 hysteresis = <2000>; 4366 type = "passive"; 4367 }; 4368 4369 cpu4_top_crit: cpu-critical { 4370 temperature = <110000>; 4371 hysteresis = <1000>; 4372 type = "critical"; 4373 }; 4374 }; 4375 }; 4376 4377 cpu4-bottom-thermal { 4378 polling-delay-passive = <0>; 4379 polling-delay = <0>; 4380 thermal-sensors = <&tsens0 8>; 4381 4382 trips { 4383 cpu4_bottom_alert0: trip-point0 { 4384 temperature = <90000>; 4385 hysteresis = <2000>; 4386 type = "passive"; 4387 }; 4388 4389 cpu4_bottom_alert1: trip-point1 { 4390 temperature = <95000>; 4391 hysteresis = <2000>; 4392 type = "passive"; 4393 }; 4394 4395 cpu4_bottom_crit: cpu-critical { 4396 temperature = <110000>; 4397 hysteresis = <1000>; 4398 type = "critical"; 4399 }; 4400 }; 4401 }; 4402 4403 cpu5-top-thermal { 4404 polling-delay-passive = <0>; 4405 polling-delay = <0>; 4406 thermal-sensors = <&tsens0 9>; 4407 4408 trips { 4409 cpu5_top_alert0: trip-point0 { 4410 temperature = <90000>; 4411 hysteresis = <2000>; 4412 type = "passive"; 4413 }; 4414 4415 cpu5_top_alert1: trip-point1 { 4416 temperature = <95000>; 4417 hysteresis = <2000>; 4418 type = "passive"; 4419 }; 4420 4421 cpu5_top_crit: cpu-critical { 4422 temperature = <110000>; 4423 hysteresis = <1000>; 4424 type = "critical"; 4425 }; 4426 }; 4427 }; 4428 4429 cpu5-bottom-thermal { 4430 polling-delay-passive = <0>; 4431 polling-delay = <0>; 4432 thermal-sensors = <&tsens0 10>; 4433 4434 trips { 4435 cpu5_bottom_alert0: trip-point0 { 4436 temperature = <90000>; 4437 hysteresis = <2000>; 4438 type = "passive"; 4439 }; 4440 4441 cpu5_bottom_alert1: trip-point1 { 4442 temperature = <95000>; 4443 hysteresis = <2000>; 4444 type = "passive"; 4445 }; 4446 4447 cpu5_bottom_crit: cpu-critical { 4448 temperature = <110000>; 4449 hysteresis = <1000>; 4450 type = "critical"; 4451 }; 4452 }; 4453 }; 4454 4455 cpu6-top-thermal { 4456 polling-delay-passive = <0>; 4457 polling-delay = <0>; 4458 thermal-sensors = <&tsens0 11>; 4459 4460 trips { 4461 cpu6_top_alert0: trip-point0 { 4462 temperature = <90000>; 4463 hysteresis = <2000>; 4464 type = "passive"; 4465 }; 4466 4467 cpu6_top_alert1: trip-point1 { 4468 temperature = <95000>; 4469 hysteresis = <2000>; 4470 type = "passive"; 4471 }; 4472 4473 cpu6_top_crit: cpu-critical { 4474 temperature = <110000>; 4475 hysteresis = <1000>; 4476 type = "critical"; 4477 }; 4478 }; 4479 }; 4480 4481 cpu6-bottom-thermal { 4482 polling-delay-passive = <0>; 4483 polling-delay = <0>; 4484 thermal-sensors = <&tsens0 12>; 4485 4486 trips { 4487 cpu6_bottom_alert0: trip-point0 { 4488 temperature = <90000>; 4489 hysteresis = <2000>; 4490 type = "passive"; 4491 }; 4492 4493 cpu6_bottom_alert1: trip-point1 { 4494 temperature = <95000>; 4495 hysteresis = <2000>; 4496 type = "passive"; 4497 }; 4498 4499 cpu6_bottom_crit: cpu-critical { 4500 temperature = <110000>; 4501 hysteresis = <1000>; 4502 type = "critical"; 4503 }; 4504 }; 4505 }; 4506 4507 cpu7-top-thermal { 4508 polling-delay-passive = <0>; 4509 polling-delay = <0>; 4510 thermal-sensors = <&tsens0 13>; 4511 4512 trips { 4513 cpu7_top_alert0: trip-point0 { 4514 temperature = <90000>; 4515 hysteresis = <2000>; 4516 type = "passive"; 4517 }; 4518 4519 cpu7_top_alert1: trip-point1 { 4520 temperature = <95000>; 4521 hysteresis = <2000>; 4522 type = "passive"; 4523 }; 4524 4525 cpu7_top_crit: cpu-critical { 4526 temperature = <110000>; 4527 hysteresis = <1000>; 4528 type = "critical"; 4529 }; 4530 }; 4531 }; 4532 4533 cpu7-middle-thermal { 4534 polling-delay-passive = <0>; 4535 polling-delay = <0>; 4536 thermal-sensors = <&tsens0 14>; 4537 4538 trips { 4539 cpu7_middle_alert0: trip-point0 { 4540 temperature = <90000>; 4541 hysteresis = <2000>; 4542 type = "passive"; 4543 }; 4544 4545 cpu7_middle_alert1: trip-point1 { 4546 temperature = <95000>; 4547 hysteresis = <2000>; 4548 type = "passive"; 4549 }; 4550 4551 cpu7_middle_crit: cpu-critical { 4552 temperature = <110000>; 4553 hysteresis = <1000>; 4554 type = "critical"; 4555 }; 4556 }; 4557 }; 4558 4559 cpu7-bottom-thermal { 4560 polling-delay-passive = <0>; 4561 polling-delay = <0>; 4562 thermal-sensors = <&tsens0 15>; 4563 4564 trips { 4565 cpu7_bottom_alert0: trip-point0 { 4566 temperature = <90000>; 4567 hysteresis = <2000>; 4568 type = "passive"; 4569 }; 4570 4571 cpu7_bottom_alert1: trip-point1 { 4572 temperature = <95000>; 4573 hysteresis = <2000>; 4574 type = "passive"; 4575 }; 4576 4577 cpu7_bottom_crit: cpu-critical { 4578 temperature = <110000>; 4579 hysteresis = <1000>; 4580 type = "critical"; 4581 }; 4582 }; 4583 }; 4584 4585 aoss1-thermal { 4586 polling-delay-passive = <0>; 4587 polling-delay = <0>; 4588 thermal-sensors = <&tsens1 0>; 4589 4590 trips { 4591 thermal-engine-config { 4592 temperature = <125000>; 4593 hysteresis = <1000>; 4594 type = "passive"; 4595 }; 4596 4597 reset-mon-config { 4598 temperature = <115000>; 4599 hysteresis = <5000>; 4600 type = "passive"; 4601 }; 4602 }; 4603 }; 4604 4605 cpu0-thermal { 4606 polling-delay-passive = <0>; 4607 polling-delay = <0>; 4608 thermal-sensors = <&tsens1 1>; 4609 4610 trips { 4611 cpu0_alert0: trip-point0 { 4612 temperature = <90000>; 4613 hysteresis = <2000>; 4614 type = "passive"; 4615 }; 4616 4617 cpu0_alert1: trip-point1 { 4618 temperature = <95000>; 4619 hysteresis = <2000>; 4620 type = "passive"; 4621 }; 4622 4623 cpu0_crit: cpu-critical { 4624 temperature = <110000>; 4625 hysteresis = <1000>; 4626 type = "critical"; 4627 }; 4628 }; 4629 }; 4630 4631 cpu1-thermal { 4632 polling-delay-passive = <0>; 4633 polling-delay = <0>; 4634 thermal-sensors = <&tsens1 2>; 4635 4636 trips { 4637 cpu1_alert0: trip-point0 { 4638 temperature = <90000>; 4639 hysteresis = <2000>; 4640 type = "passive"; 4641 }; 4642 4643 cpu1_alert1: trip-point1 { 4644 temperature = <95000>; 4645 hysteresis = <2000>; 4646 type = "passive"; 4647 }; 4648 4649 cpu1_crit: cpu-critical { 4650 temperature = <110000>; 4651 hysteresis = <1000>; 4652 type = "critical"; 4653 }; 4654 }; 4655 }; 4656 4657 cpu2-thermal { 4658 polling-delay-passive = <0>; 4659 polling-delay = <0>; 4660 thermal-sensors = <&tsens1 3>; 4661 4662 trips { 4663 cpu2_alert0: trip-point0 { 4664 temperature = <90000>; 4665 hysteresis = <2000>; 4666 type = "passive"; 4667 }; 4668 4669 cpu2_alert1: trip-point1 { 4670 temperature = <95000>; 4671 hysteresis = <2000>; 4672 type = "passive"; 4673 }; 4674 4675 cpu2_crit: cpu-critical { 4676 temperature = <110000>; 4677 hysteresis = <1000>; 4678 type = "critical"; 4679 }; 4680 }; 4681 }; 4682 4683 cdsp0-thermal { 4684 polling-delay-passive = <10>; 4685 polling-delay = <0>; 4686 thermal-sensors = <&tsens2 4>; 4687 4688 trips { 4689 thermal-engine-config { 4690 temperature = <125000>; 4691 hysteresis = <1000>; 4692 type = "passive"; 4693 }; 4694 4695 thermal-hal-config { 4696 temperature = <125000>; 4697 hysteresis = <1000>; 4698 type = "passive"; 4699 }; 4700 4701 reset-mon-config { 4702 temperature = <115000>; 4703 hysteresis = <5000>; 4704 type = "passive"; 4705 }; 4706 4707 cdsp0_junction_config: junction-config { 4708 temperature = <95000>; 4709 hysteresis = <5000>; 4710 type = "passive"; 4711 }; 4712 }; 4713 }; 4714 4715 cdsp1-thermal { 4716 polling-delay-passive = <10>; 4717 polling-delay = <0>; 4718 thermal-sensors = <&tsens2 5>; 4719 4720 trips { 4721 thermal-engine-config { 4722 temperature = <125000>; 4723 hysteresis = <1000>; 4724 type = "passive"; 4725 }; 4726 4727 thermal-hal-config { 4728 temperature = <125000>; 4729 hysteresis = <1000>; 4730 type = "passive"; 4731 }; 4732 4733 reset-mon-config { 4734 temperature = <115000>; 4735 hysteresis = <5000>; 4736 type = "passive"; 4737 }; 4738 4739 cdsp1_junction_config: junction-config { 4740 temperature = <95000>; 4741 hysteresis = <5000>; 4742 type = "passive"; 4743 }; 4744 }; 4745 }; 4746 4747 cdsp2-thermal { 4748 polling-delay-passive = <10>; 4749 polling-delay = <0>; 4750 thermal-sensors = <&tsens2 6>; 4751 4752 trips { 4753 thermal-engine-config { 4754 temperature = <125000>; 4755 hysteresis = <1000>; 4756 type = "passive"; 4757 }; 4758 4759 thermal-hal-config { 4760 temperature = <125000>; 4761 hysteresis = <1000>; 4762 type = "passive"; 4763 }; 4764 4765 reset-mon-config { 4766 temperature = <115000>; 4767 hysteresis = <5000>; 4768 type = "passive"; 4769 }; 4770 4771 cdsp2_junction_config: junction-config { 4772 temperature = <95000>; 4773 hysteresis = <5000>; 4774 type = "passive"; 4775 }; 4776 }; 4777 }; 4778 4779 cdsp3-thermal { 4780 polling-delay-passive = <10>; 4781 polling-delay = <0>; 4782 thermal-sensors = <&tsens2 7>; 4783 4784 trips { 4785 thermal-engine-config { 4786 temperature = <125000>; 4787 hysteresis = <1000>; 4788 type = "passive"; 4789 }; 4790 4791 thermal-hal-config { 4792 temperature = <125000>; 4793 hysteresis = <1000>; 4794 type = "passive"; 4795 }; 4796 4797 reset-mon-config { 4798 temperature = <115000>; 4799 hysteresis = <5000>; 4800 type = "passive"; 4801 }; 4802 4803 cdsp3_junction_config: junction-config { 4804 temperature = <95000>; 4805 hysteresis = <5000>; 4806 type = "passive"; 4807 }; 4808 }; 4809 }; 4810 4811 video-thermal { 4812 polling-delay-passive = <0>; 4813 polling-delay = <0>; 4814 thermal-sensors = <&tsens1 8>; 4815 4816 trips { 4817 thermal-engine-config { 4818 temperature = <125000>; 4819 hysteresis = <1000>; 4820 type = "passive"; 4821 }; 4822 4823 reset-mon-config { 4824 temperature = <115000>; 4825 hysteresis = <5000>; 4826 type = "passive"; 4827 }; 4828 }; 4829 }; 4830 4831 mem-thermal { 4832 polling-delay-passive = <10>; 4833 polling-delay = <0>; 4834 thermal-sensors = <&tsens1 9>; 4835 4836 trips { 4837 thermal-engine-config { 4838 temperature = <125000>; 4839 hysteresis = <1000>; 4840 type = "passive"; 4841 }; 4842 4843 ddr_config0: ddr0-config { 4844 temperature = <90000>; 4845 hysteresis = <5000>; 4846 type = "passive"; 4847 }; 4848 4849 reset-mon-config { 4850 temperature = <115000>; 4851 hysteresis = <5000>; 4852 type = "passive"; 4853 }; 4854 }; 4855 }; 4856 4857 modem0-thermal { 4858 polling-delay-passive = <0>; 4859 polling-delay = <0>; 4860 thermal-sensors = <&tsens1 10>; 4861 4862 trips { 4863 thermal-engine-config { 4864 temperature = <125000>; 4865 hysteresis = <1000>; 4866 type = "passive"; 4867 }; 4868 4869 mdmss0_config0: mdmss0-config0 { 4870 temperature = <102000>; 4871 hysteresis = <3000>; 4872 type = "passive"; 4873 }; 4874 4875 mdmss0_config1: mdmss0-config1 { 4876 temperature = <105000>; 4877 hysteresis = <3000>; 4878 type = "passive"; 4879 }; 4880 4881 reset-mon-config { 4882 temperature = <115000>; 4883 hysteresis = <5000>; 4884 type = "passive"; 4885 }; 4886 }; 4887 }; 4888 4889 modem1-thermal { 4890 polling-delay-passive = <0>; 4891 polling-delay = <0>; 4892 thermal-sensors = <&tsens1 11>; 4893 4894 trips { 4895 thermal-engine-config { 4896 temperature = <125000>; 4897 hysteresis = <1000>; 4898 type = "passive"; 4899 }; 4900 4901 mdmss1_config0: mdmss1-config0 { 4902 temperature = <102000>; 4903 hysteresis = <3000>; 4904 type = "passive"; 4905 }; 4906 4907 mdmss1_config1: mdmss1-config1 { 4908 temperature = <105000>; 4909 hysteresis = <3000>; 4910 type = "passive"; 4911 }; 4912 4913 reset-mon-config { 4914 temperature = <115000>; 4915 hysteresis = <5000>; 4916 type = "passive"; 4917 }; 4918 }; 4919 }; 4920 4921 modem2-thermal { 4922 polling-delay-passive = <0>; 4923 polling-delay = <0>; 4924 thermal-sensors = <&tsens1 12>; 4925 4926 trips { 4927 thermal-engine-config { 4928 temperature = <125000>; 4929 hysteresis = <1000>; 4930 type = "passive"; 4931 }; 4932 4933 mdmss2_config0: mdmss2-config0 { 4934 temperature = <102000>; 4935 hysteresis = <3000>; 4936 type = "passive"; 4937 }; 4938 4939 mdmss2_config1: mdmss2-config1 { 4940 temperature = <105000>; 4941 hysteresis = <3000>; 4942 type = "passive"; 4943 }; 4944 4945 reset-mon-config { 4946 temperature = <115000>; 4947 hysteresis = <5000>; 4948 type = "passive"; 4949 }; 4950 }; 4951 }; 4952 4953 modem3-thermal { 4954 polling-delay-passive = <0>; 4955 polling-delay = <0>; 4956 thermal-sensors = <&tsens1 13>; 4957 4958 trips { 4959 thermal-engine-config { 4960 temperature = <125000>; 4961 hysteresis = <1000>; 4962 type = "passive"; 4963 }; 4964 4965 mdmss3_config0: mdmss3-config0 { 4966 temperature = <102000>; 4967 hysteresis = <3000>; 4968 type = "passive"; 4969 }; 4970 4971 mdmss3_config1: mdmss3-config1 { 4972 temperature = <105000>; 4973 hysteresis = <3000>; 4974 type = "passive"; 4975 }; 4976 4977 reset-mon-config { 4978 temperature = <115000>; 4979 hysteresis = <5000>; 4980 type = "passive"; 4981 }; 4982 }; 4983 }; 4984 4985 camera0-thermal { 4986 polling-delay-passive = <0>; 4987 polling-delay = <0>; 4988 thermal-sensors = <&tsens1 14>; 4989 4990 trips { 4991 thermal-engine-config { 4992 temperature = <125000>; 4993 hysteresis = <1000>; 4994 type = "passive"; 4995 }; 4996 4997 reset-mon-config { 4998 temperature = <115000>; 4999 hysteresis = <5000>; 5000 type = "passive"; 5001 }; 5002 }; 5003 }; 5004 5005 camera1-thermal { 5006 polling-delay-passive = <0>; 5007 polling-delay = <0>; 5008 thermal-sensors = <&tsens1 15>; 5009 5010 trips { 5011 thermal-engine-config { 5012 temperature = <125000>; 5013 hysteresis = <1000>; 5014 type = "passive"; 5015 }; 5016 5017 reset-mon-config { 5018 temperature = <115000>; 5019 hysteresis = <5000>; 5020 type = "passive"; 5021 }; 5022 }; 5023 }; 5024 5025 aoss2-thermal { 5026 polling-delay-passive = <0>; 5027 polling-delay = <0>; 5028 thermal-sensors = <&tsens2 0>; 5029 5030 trips { 5031 thermal-engine-config { 5032 temperature = <125000>; 5033 hysteresis = <1000>; 5034 type = "passive"; 5035 }; 5036 5037 reset-mon-config { 5038 temperature = <115000>; 5039 hysteresis = <5000>; 5040 type = "passive"; 5041 }; 5042 }; 5043 }; 5044 5045 gpuss-0-thermal { 5046 polling-delay-passive = <10>; 5047 polling-delay = <0>; 5048 thermal-sensors = <&tsens2 1>; 5049 5050 trips { 5051 thermal-engine-config { 5052 temperature = <125000>; 5053 hysteresis = <1000>; 5054 type = "passive"; 5055 }; 5056 5057 thermal-hal-config { 5058 temperature = <125000>; 5059 hysteresis = <1000>; 5060 type = "passive"; 5061 }; 5062 5063 reset-mon-config { 5064 temperature = <115000>; 5065 hysteresis = <5000>; 5066 type = "passive"; 5067 }; 5068 5069 gpu0_junction_config: junction-config { 5070 temperature = <95000>; 5071 hysteresis = <5000>; 5072 type = "passive"; 5073 }; 5074 }; 5075 }; 5076 5077 gpuss-1-thermal { 5078 polling-delay-passive = <10>; 5079 polling-delay = <0>; 5080 thermal-sensors = <&tsens2 2>; 5081 5082 trips { 5083 thermal-engine-config { 5084 temperature = <125000>; 5085 hysteresis = <1000>; 5086 type = "passive"; 5087 }; 5088 5089 thermal-hal-config { 5090 temperature = <125000>; 5091 hysteresis = <1000>; 5092 type = "passive"; 5093 }; 5094 5095 reset-mon-config { 5096 temperature = <115000>; 5097 hysteresis = <5000>; 5098 type = "passive"; 5099 }; 5100 5101 gpu1_junction_config: junction-config { 5102 temperature = <95000>; 5103 hysteresis = <5000>; 5104 type = "passive"; 5105 }; 5106 }; 5107 }; 5108 5109 gpuss-2-thermal { 5110 polling-delay-passive = <10>; 5111 polling-delay = <0>; 5112 thermal-sensors = <&tsens2 3>; 5113 5114 trips { 5115 thermal-engine-config { 5116 temperature = <125000>; 5117 hysteresis = <1000>; 5118 type = "passive"; 5119 }; 5120 5121 thermal-hal-config { 5122 temperature = <125000>; 5123 hysteresis = <1000>; 5124 type = "passive"; 5125 }; 5126 5127 reset-mon-config { 5128 temperature = <115000>; 5129 hysteresis = <5000>; 5130 type = "passive"; 5131 }; 5132 5133 gpu2_junction_config: junction-config { 5134 temperature = <95000>; 5135 hysteresis = <5000>; 5136 type = "passive"; 5137 }; 5138 }; 5139 }; 5140 5141 gpuss-3-thermal { 5142 polling-delay-passive = <10>; 5143 polling-delay = <0>; 5144 thermal-sensors = <&tsens2 4>; 5145 5146 trips { 5147 thermal-engine-config { 5148 temperature = <125000>; 5149 hysteresis = <1000>; 5150 type = "passive"; 5151 }; 5152 5153 thermal-hal-config { 5154 temperature = <125000>; 5155 hysteresis = <1000>; 5156 type = "passive"; 5157 }; 5158 5159 reset-mon-config { 5160 temperature = <115000>; 5161 hysteresis = <5000>; 5162 type = "passive"; 5163 }; 5164 5165 gpu3_junction_config: junction-config { 5166 temperature = <95000>; 5167 hysteresis = <5000>; 5168 type = "passive"; 5169 }; 5170 }; 5171 }; 5172 5173 gpuss-4-thermal { 5174 polling-delay-passive = <10>; 5175 polling-delay = <0>; 5176 thermal-sensors = <&tsens2 5>; 5177 5178 trips { 5179 thermal-engine-config { 5180 temperature = <125000>; 5181 hysteresis = <1000>; 5182 type = "passive"; 5183 }; 5184 5185 thermal-hal-config { 5186 temperature = <125000>; 5187 hysteresis = <1000>; 5188 type = "passive"; 5189 }; 5190 5191 reset-mon-config { 5192 temperature = <115000>; 5193 hysteresis = <5000>; 5194 type = "passive"; 5195 }; 5196 5197 gpu4_junction_config: junction-config { 5198 temperature = <95000>; 5199 hysteresis = <5000>; 5200 type = "passive"; 5201 }; 5202 }; 5203 }; 5204 5205 gpuss-5-thermal { 5206 polling-delay-passive = <10>; 5207 polling-delay = <0>; 5208 thermal-sensors = <&tsens2 6>; 5209 5210 trips { 5211 thermal-engine-config { 5212 temperature = <125000>; 5213 hysteresis = <1000>; 5214 type = "passive"; 5215 }; 5216 5217 thermal-hal-config { 5218 temperature = <125000>; 5219 hysteresis = <1000>; 5220 type = "passive"; 5221 }; 5222 5223 reset-mon-config { 5224 temperature = <115000>; 5225 hysteresis = <5000>; 5226 type = "passive"; 5227 }; 5228 5229 gpu5_junction_config: junction-config { 5230 temperature = <95000>; 5231 hysteresis = <5000>; 5232 type = "passive"; 5233 }; 5234 }; 5235 }; 5236 5237 gpuss-6-thermal { 5238 polling-delay-passive = <10>; 5239 polling-delay = <0>; 5240 thermal-sensors = <&tsens2 7>; 5241 5242 trips { 5243 thermal-engine-config { 5244 temperature = <125000>; 5245 hysteresis = <1000>; 5246 type = "passive"; 5247 }; 5248 5249 thermal-hal-config { 5250 temperature = <125000>; 5251 hysteresis = <1000>; 5252 type = "passive"; 5253 }; 5254 5255 reset-mon-config { 5256 temperature = <115000>; 5257 hysteresis = <5000>; 5258 type = "passive"; 5259 }; 5260 5261 gpu6_junction_config: junction-config { 5262 temperature = <95000>; 5263 hysteresis = <5000>; 5264 type = "passive"; 5265 }; 5266 }; 5267 }; 5268 5269 gpuss-7-thermal { 5270 polling-delay-passive = <10>; 5271 polling-delay = <0>; 5272 thermal-sensors = <&tsens2 8>; 5273 5274 trips { 5275 thermal-engine-config { 5276 temperature = <125000>; 5277 hysteresis = <1000>; 5278 type = "passive"; 5279 }; 5280 5281 thermal-hal-config { 5282 temperature = <125000>; 5283 hysteresis = <1000>; 5284 type = "passive"; 5285 }; 5286 5287 reset-mon-config { 5288 temperature = <115000>; 5289 hysteresis = <5000>; 5290 type = "passive"; 5291 }; 5292 5293 gpu7_junction_config: junction-config { 5294 temperature = <95000>; 5295 hysteresis = <5000>; 5296 type = "passive"; 5297 }; 5298 }; 5299 }; 5300 }; 5301 5302 timer { 5303 compatible = "arm,armv8-timer"; 5304 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5305 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5306 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5307 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5308 }; 5309}; 5310