1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8550-gcc.h> 8#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 9#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 bi_tcxo_div2: bi-tcxo-div2-clk { 42 #clock-cells = <0>; 43 compatible = "fixed-factor-clock"; 44 clocks = <&rpmhcc RPMH_CXO_CLK>; 45 clock-mult = <1>; 46 clock-div = <2>; 47 }; 48 49 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 50 #clock-cells = <0>; 51 compatible = "fixed-factor-clock"; 52 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 53 clock-mult = <1>; 54 clock-div = <2>; 55 }; 56 57 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 cpus { 64 #address-cells = <2>; 65 #size-cells = <0>; 66 67 CPU0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a510"; 70 reg = <0 0>; 71 clocks = <&cpufreq_hw 0>; 72 enable-method = "psci"; 73 next-level-cache = <&L2_0>; 74 power-domains = <&CPU_PD0>; 75 power-domain-names = "psci"; 76 qcom,freq-domain = <&cpufreq_hw 0>; 77 capacity-dmips-mhz = <1024>; 78 dynamic-power-coefficient = <100>; 79 #cooling-cells = <2>; 80 L2_0: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 next-level-cache = <&L3_0>; 84 L3_0: l3-cache { 85 compatible = "cache"; 86 cache-level = <3>; 87 }; 88 }; 89 }; 90 91 CPU1: cpu@100 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a510"; 94 reg = <0 0x100>; 95 clocks = <&cpufreq_hw 0>; 96 enable-method = "psci"; 97 next-level-cache = <&L2_100>; 98 power-domains = <&CPU_PD1>; 99 power-domain-names = "psci"; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 capacity-dmips-mhz = <1024>; 102 dynamic-power-coefficient = <100>; 103 #cooling-cells = <2>; 104 L2_100: l2-cache { 105 compatible = "cache"; 106 cache-level = <2>; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU2: cpu@200 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a510"; 114 reg = <0 0x200>; 115 clocks = <&cpufreq_hw 0>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_200>; 118 power-domains = <&CPU_PD2>; 119 power-domain-names = "psci"; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 capacity-dmips-mhz = <1024>; 122 dynamic-power-coefficient = <100>; 123 #cooling-cells = <2>; 124 L2_200: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 next-level-cache = <&L3_0>; 128 }; 129 }; 130 131 CPU3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a715"; 134 reg = <0 0x300>; 135 clocks = <&cpufreq_hw 1>; 136 enable-method = "psci"; 137 next-level-cache = <&L2_300>; 138 power-domains = <&CPU_PD3>; 139 power-domain-names = "psci"; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 capacity-dmips-mhz = <1792>; 142 dynamic-power-coefficient = <270>; 143 #cooling-cells = <2>; 144 L2_300: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU4: cpu@400 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a715"; 154 reg = <0 0x400>; 155 clocks = <&cpufreq_hw 1>; 156 enable-method = "psci"; 157 next-level-cache = <&L2_400>; 158 power-domains = <&CPU_PD4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 capacity-dmips-mhz = <1792>; 162 dynamic-power-coefficient = <270>; 163 #cooling-cells = <2>; 164 L2_400: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU5: cpu@500 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a710"; 174 reg = <0 0x500>; 175 clocks = <&cpufreq_hw 1>; 176 enable-method = "psci"; 177 next-level-cache = <&L2_500>; 178 power-domains = <&CPU_PD5>; 179 power-domain-names = "psci"; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 capacity-dmips-mhz = <1792>; 182 dynamic-power-coefficient = <270>; 183 #cooling-cells = <2>; 184 L2_500: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-a710"; 194 reg = <0 0x600>; 195 clocks = <&cpufreq_hw 1>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_600>; 198 power-domains = <&CPU_PD6>; 199 power-domain-names = "psci"; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 capacity-dmips-mhz = <1792>; 202 dynamic-power-coefficient = <270>; 203 #cooling-cells = <2>; 204 L2_600: l2-cache { 205 compatible = "cache"; 206 cache-level = <2>; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 CPU7: cpu@700 { 212 device_type = "cpu"; 213 compatible = "arm,cortex-x3"; 214 reg = <0 0x700>; 215 clocks = <&cpufreq_hw 2>; 216 enable-method = "psci"; 217 next-level-cache = <&L2_700>; 218 power-domains = <&CPU_PD7>; 219 power-domain-names = "psci"; 220 qcom,freq-domain = <&cpufreq_hw 2>; 221 capacity-dmips-mhz = <1894>; 222 dynamic-power-coefficient = <588>; 223 #cooling-cells = <2>; 224 L2_700: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 next-level-cache = <&L3_0>; 228 }; 229 }; 230 231 cpu-map { 232 cluster0 { 233 core0 { 234 cpu = <&CPU0>; 235 }; 236 237 core1 { 238 cpu = <&CPU1>; 239 }; 240 241 core2 { 242 cpu = <&CPU2>; 243 }; 244 245 core3 { 246 cpu = <&CPU3>; 247 }; 248 249 core4 { 250 cpu = <&CPU4>; 251 }; 252 253 core5 { 254 cpu = <&CPU5>; 255 }; 256 257 core6 { 258 cpu = <&CPU6>; 259 }; 260 261 core7 { 262 cpu = <&CPU7>; 263 }; 264 }; 265 }; 266 267 idle-states { 268 entry-method = "psci"; 269 270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "silver-rail-power-collapse"; 273 arm,psci-suspend-param = <0x40000004>; 274 entry-latency-us = <800>; 275 exit-latency-us = <750>; 276 min-residency-us = <4090>; 277 local-timer-stop; 278 }; 279 280 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "gold-rail-power-collapse"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <600>; 285 exit-latency-us = <1550>; 286 min-residency-us = <4791>; 287 local-timer-stop; 288 }; 289 }; 290 291 domain-idle-states { 292 CLUSTER_SLEEP_0: cluster-sleep-0 { 293 compatible = "domain-idle-state"; 294 arm,psci-suspend-param = <0x41000044>; 295 entry-latency-us = <1050>; 296 exit-latency-us = <2500>; 297 min-residency-us = <5309>; 298 }; 299 300 CLUSTER_SLEEP_1: cluster-sleep-1 { 301 compatible = "domain-idle-state"; 302 arm,psci-suspend-param = <0x4100c344>; 303 entry-latency-us = <2700>; 304 exit-latency-us = <3500>; 305 min-residency-us = <13959>; 306 }; 307 }; 308 }; 309 310 firmware { 311 scm: scm { 312 compatible = "qcom,scm-sm8550", "qcom,scm"; 313 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 314 }; 315 }; 316 317 clk_virt: interconnect-0 { 318 compatible = "qcom,sm8550-clk-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 mc_virt: interconnect-1 { 324 compatible = "qcom,sm8550-mc-virt"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 memory@a0000000 { 330 device_type = "memory"; 331 /* We expect the bootloader to fill in the size */ 332 reg = <0 0xa0000000 0 0>; 333 }; 334 335 pmu { 336 compatible = "arm,armv8-pmuv3"; 337 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 338 }; 339 340 psci { 341 compatible = "arm,psci-1.0"; 342 method = "smc"; 343 344 CPU_PD0: power-domain-cpu0 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_PD>; 347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 348 }; 349 350 CPU_PD1: power-domain-cpu1 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_PD>; 353 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 354 }; 355 356 CPU_PD2: power-domain-cpu2 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD>; 359 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 360 }; 361 362 CPU_PD3: power-domain-cpu3 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD>; 365 domain-idle-states = <&BIG_CPU_SLEEP_0>; 366 }; 367 368 CPU_PD4: power-domain-cpu4 { 369 #power-domain-cells = <0>; 370 power-domains = <&CLUSTER_PD>; 371 domain-idle-states = <&BIG_CPU_SLEEP_0>; 372 }; 373 374 CPU_PD5: power-domain-cpu5 { 375 #power-domain-cells = <0>; 376 power-domains = <&CLUSTER_PD>; 377 domain-idle-states = <&BIG_CPU_SLEEP_0>; 378 }; 379 380 CPU_PD6: power-domain-cpu6 { 381 #power-domain-cells = <0>; 382 power-domains = <&CLUSTER_PD>; 383 domain-idle-states = <&BIG_CPU_SLEEP_0>; 384 }; 385 386 CPU_PD7: power-domain-cpu7 { 387 #power-domain-cells = <0>; 388 power-domains = <&CLUSTER_PD>; 389 domain-idle-states = <&BIG_CPU_SLEEP_0>; 390 }; 391 392 CLUSTER_PD: power-domain-cluster { 393 #power-domain-cells = <0>; 394 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 395 }; 396 }; 397 398 reserved_memory: reserved-memory { 399 #address-cells = <2>; 400 #size-cells = <2>; 401 ranges; 402 403 hyp_mem: hyp-region@80000000 { 404 reg = <0 0x80000000 0 0xa00000>; 405 no-map; 406 }; 407 408 cpusys_vm_mem: cpusys-vm-region@80a00000 { 409 reg = <0 0x80a00000 0 0x400000>; 410 no-map; 411 }; 412 413 hyp_tags_mem: hyp-tags-region@80e00000 { 414 reg = <0 0x80e00000 0 0x3d0000>; 415 no-map; 416 }; 417 418 xbl_sc_mem: xbl-sc-region@d8100000 { 419 reg = <0 0xd8100000 0 0x40000>; 420 no-map; 421 }; 422 423 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 424 reg = <0 0x811d0000 0 0x30000>; 425 no-map; 426 }; 427 428 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 429 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 430 reg = <0 0x81a00000 0 0x260000>; 431 no-map; 432 }; 433 434 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 435 compatible = "qcom,cmd-db"; 436 reg = <0 0x81c60000 0 0x20000>; 437 no-map; 438 }; 439 440 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 441 aop_config_merged_mem: aop-config-merged-region@81c80000 { 442 reg = <0 0x81c80000 0 0x74000>; 443 no-map; 444 }; 445 446 /* secdata region can be reused by apps */ 447 smem: smem@81d00000 { 448 compatible = "qcom,smem"; 449 reg = <0 0x81d00000 0 0x200000>; 450 hwlocks = <&tcsr_mutex 3>; 451 no-map; 452 }; 453 454 adsp_mhi_mem: adsp-mhi-region@81f00000 { 455 reg = <0 0x81f00000 0 0x20000>; 456 no-map; 457 }; 458 459 global_sync_mem: global-sync-region@82600000 { 460 reg = <0 0x82600000 0 0x100000>; 461 no-map; 462 }; 463 464 tz_stat_mem: tz-stat-region@82700000 { 465 reg = <0 0x82700000 0 0x100000>; 466 no-map; 467 }; 468 469 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 470 reg = <0 0x82800000 0 0x4600000>; 471 no-map; 472 }; 473 474 mpss_mem: mpss-region@8a800000 { 475 reg = <0 0x8a800000 0 0x10800000>; 476 no-map; 477 }; 478 479 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 480 reg = <0 0x9b000000 0 0x80000>; 481 no-map; 482 }; 483 484 ipa_fw_mem: ipa-fw-region@9b080000 { 485 reg = <0 0x9b080000 0 0x10000>; 486 no-map; 487 }; 488 489 ipa_gsi_mem: ipa-gsi-region@9b090000 { 490 reg = <0 0x9b090000 0 0xa000>; 491 no-map; 492 }; 493 494 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 495 reg = <0 0x9b09a000 0 0x2000>; 496 no-map; 497 }; 498 499 spss_region_mem: spss-region@9b100000 { 500 reg = <0 0x9b100000 0 0x180000>; 501 no-map; 502 }; 503 504 /* First part of the "SPU secure shared memory" region */ 505 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 506 reg = <0 0x9b280000 0 0x60000>; 507 no-map; 508 }; 509 510 /* Second part of the "SPU secure shared memory" region */ 511 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 512 reg = <0 0x9b2e0000 0 0x20000>; 513 no-map; 514 }; 515 516 camera_mem: camera-region@9b300000 { 517 reg = <0 0x9b300000 0 0x800000>; 518 no-map; 519 }; 520 521 video_mem: video-region@9bb00000 { 522 reg = <0 0x9bb00000 0 0x700000>; 523 no-map; 524 }; 525 526 cvp_mem: cvp-region@9c200000 { 527 reg = <0 0x9c200000 0 0x700000>; 528 no-map; 529 }; 530 531 cdsp_mem: cdsp-region@9c900000 { 532 reg = <0 0x9c900000 0 0x2000000>; 533 no-map; 534 }; 535 536 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 537 reg = <0 0x9e900000 0 0x80000>; 538 no-map; 539 }; 540 541 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 542 reg = <0 0x9e980000 0 0x80000>; 543 no-map; 544 }; 545 546 adspslpi_mem: adspslpi-region@9ea00000 { 547 reg = <0 0x9ea00000 0 0x4080000>; 548 no-map; 549 }; 550 551 /* uefi region can be reused by apps */ 552 553 /* Linux kernel image is loaded at 0xa8000000 */ 554 555 rmtfs_mem: rmtfs-region@d4a80000 { 556 compatible = "qcom,rmtfs-mem"; 557 reg = <0x0 0xd4a80000 0x0 0x280000>; 558 no-map; 559 560 qcom,client-id = <1>; 561 qcom,vmid = <15>; 562 }; 563 564 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 565 reg = <0 0xd4d00000 0 0x3300000>; 566 no-map; 567 }; 568 569 tz_reserved_mem: tz-reserved-region@d8000000 { 570 reg = <0 0xd8000000 0 0x100000>; 571 no-map; 572 }; 573 574 cpucp_fw_mem: cpucp-fw-region@d8140000 { 575 reg = <0 0xd8140000 0 0x1c0000>; 576 no-map; 577 }; 578 579 qtee_mem: qtee-region@d8300000 { 580 reg = <0 0xd8300000 0 0x500000>; 581 no-map; 582 }; 583 584 ta_mem: ta-region@d8800000 { 585 reg = <0 0xd8800000 0 0x8a00000>; 586 no-map; 587 }; 588 589 tz_tags_mem: tz-tags-region@e1200000 { 590 reg = <0 0xe1200000 0 0x2740000>; 591 no-map; 592 }; 593 594 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 595 reg = <0 0xe6440000 0 0x279000>; 596 no-map; 597 }; 598 599 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 600 reg = <0 0xf3600000 0 0x4aee000>; 601 no-map; 602 }; 603 604 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 605 reg = <0 0xf80ee000 0 0x1000>; 606 no-map; 607 }; 608 609 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 610 reg = <0 0xf80ef000 0 0x9000>; 611 no-map; 612 }; 613 614 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 615 reg = <0 0xf80f8000 0 0x4000>; 616 no-map; 617 }; 618 619 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 620 reg = <0 0xf80fc000 0 0x4000>; 621 no-map; 622 }; 623 624 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 625 reg = <0 0xf8100000 0 0x100000>; 626 no-map; 627 }; 628 629 oem_vm_mem: oem-vm-region@f8400000 { 630 reg = <0 0xf8400000 0 0x4800000>; 631 no-map; 632 }; 633 634 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 635 reg = <0 0xfcc00000 0 0x4000>; 636 no-map; 637 }; 638 639 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 640 reg = <0 0xfcc04000 0 0x100000>; 641 no-map; 642 }; 643 644 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 645 reg = <0 0xfce00000 0 0x2900000>; 646 no-map; 647 }; 648 649 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 650 reg = <0 0xff700000 0 0x100000>; 651 no-map; 652 }; 653 }; 654 655 smp2p-adsp { 656 compatible = "qcom,smp2p"; 657 qcom,smem = <443>, <429>; 658 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 659 IPCC_MPROC_SIGNAL_SMP2P 660 IRQ_TYPE_EDGE_RISING>; 661 mboxes = <&ipcc IPCC_CLIENT_LPASS 662 IPCC_MPROC_SIGNAL_SMP2P>; 663 664 qcom,local-pid = <0>; 665 qcom,remote-pid = <2>; 666 667 smp2p_adsp_out: master-kernel { 668 qcom,entry-name = "master-kernel"; 669 #qcom,smem-state-cells = <1>; 670 }; 671 672 smp2p_adsp_in: slave-kernel { 673 qcom,entry-name = "slave-kernel"; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 }; 677 }; 678 679 smp2p-cdsp { 680 compatible = "qcom,smp2p"; 681 qcom,smem = <94>, <432>; 682 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&ipcc IPCC_CLIENT_CDSP 686 IPCC_MPROC_SIGNAL_SMP2P>; 687 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <5>; 690 691 smp2p_cdsp_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 smp2p_cdsp_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 }; 702 703 smp2p-modem { 704 compatible = "qcom,smp2p"; 705 qcom,smem = <435>, <428>; 706 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 mboxes = <&ipcc IPCC_CLIENT_MPSS 710 IPCC_MPROC_SIGNAL_SMP2P>; 711 712 qcom,local-pid = <0>; 713 qcom,remote-pid = <1>; 714 715 smp2p_modem_out: master-kernel { 716 qcom,entry-name = "master-kernel"; 717 #qcom,smem-state-cells = <1>; 718 }; 719 720 smp2p_modem_in: slave-kernel { 721 qcom,entry-name = "slave-kernel"; 722 interrupt-controller; 723 #interrupt-cells = <2>; 724 }; 725 726 ipa_smp2p_out: ipa-ap-to-modem { 727 qcom,entry-name = "ipa"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 ipa_smp2p_in: ipa-modem-to-ap { 732 qcom,entry-name = "ipa"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 soc: soc@0 { 739 compatible = "simple-bus"; 740 ranges = <0 0 0 0 0x10 0>; 741 dma-ranges = <0 0 0 0 0x10 0>; 742 743 #address-cells = <2>; 744 #size-cells = <2>; 745 746 gcc: clock-controller@100000 { 747 compatible = "qcom,sm8550-gcc"; 748 reg = <0 0x00100000 0 0x1f4200>; 749 #clock-cells = <1>; 750 #reset-cells = <1>; 751 #power-domain-cells = <1>; 752 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 753 <&pcie0_phy>, 754 <&pcie1_phy>, 755 <&pcie_1_phy_aux_clk>, 756 <&ufs_mem_phy 0>, 757 <&ufs_mem_phy 1>, 758 <&ufs_mem_phy 2>, 759 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 760 }; 761 762 ipcc: mailbox@408000 { 763 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 764 reg = <0 0x00408000 0 0x1000>; 765 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-controller; 767 #interrupt-cells = <3>; 768 #mbox-cells = <2>; 769 }; 770 771 gpi_dma2: dma-controller@800000 { 772 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 773 #dma-cells = <3>; 774 reg = <0 0x00800000 0 0x60000>; 775 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 787 dma-channels = <12>; 788 dma-channel-mask = <0x3e>; 789 iommus = <&apps_smmu 0x436 0>; 790 status = "disabled"; 791 }; 792 793 qupv3_id_1: geniqup@8c0000 { 794 compatible = "qcom,geni-se-qup"; 795 reg = <0 0x008c0000 0 0x2000>; 796 ranges; 797 clock-names = "m-ahb", "s-ahb"; 798 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 799 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 800 iommus = <&apps_smmu 0x423 0>; 801 #address-cells = <2>; 802 #size-cells = <2>; 803 status = "disabled"; 804 805 i2c8: i2c@880000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0 0x00880000 0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_i2c8_data_clk>; 812 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 816 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 818 interconnect-names = "qup-core", "qup-config", "qup-memory"; 819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 820 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 821 dma-names = "tx", "rx"; 822 status = "disabled"; 823 }; 824 825 spi8: spi@880000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0 0x00880000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 834 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 835 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 836 interconnect-names = "qup-core", "qup-config", "qup-memory"; 837 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 838 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 839 dma-names = "tx", "rx"; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 i2c9: i2c@884000 { 846 compatible = "qcom,geni-i2c"; 847 reg = <0 0x00884000 0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_i2c9_data_clk>; 852 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 857 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 858 interconnect-names = "qup-core", "qup-config", "qup-memory"; 859 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 860 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 861 dma-names = "tx", "rx"; 862 status = "disabled"; 863 }; 864 865 spi9: spi@884000 { 866 compatible = "qcom,geni-spi"; 867 reg = <0 0x00884000 0 0x4000>; 868 clock-names = "se"; 869 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 870 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 874 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 875 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 876 interconnect-names = "qup-core", "qup-config", "qup-memory"; 877 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 878 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 879 dma-names = "tx", "rx"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 i2c10: i2c@888000 { 886 compatible = "qcom,geni-i2c"; 887 reg = <0 0x00888000 0 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&qup_i2c10_data_clk>; 892 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 897 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 898 interconnect-names = "qup-core", "qup-config", "qup-memory"; 899 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 900 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 901 dma-names = "tx", "rx"; 902 status = "disabled"; 903 }; 904 905 spi10: spi@888000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0 0x00888000 0 0x4000>; 908 clock-names = "se"; 909 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 910 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 913 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 914 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 915 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 916 interconnect-names = "qup-core", "qup-config", "qup-memory"; 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 i2c11: i2c@88c000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0 0x0088c000 0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_i2c11_data_clk>; 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 941 dma-names = "tx", "rx"; 942 status = "disabled"; 943 }; 944 945 spi11: spi@88c000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 954 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 955 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 956 interconnect-names = "qup-core", "qup-config", "qup-memory"; 957 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 958 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 959 dma-names = "tx", "rx"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 status = "disabled"; 963 }; 964 965 i2c12: i2c@890000 { 966 compatible = "qcom,geni-i2c"; 967 reg = <0 0x00890000 0 0x4000>; 968 clock-names = "se"; 969 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&qup_i2c12_data_clk>; 972 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 977 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 978 interconnect-names = "qup-core", "qup-config", "qup-memory"; 979 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 980 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 981 dma-names = "tx", "rx"; 982 status = "disabled"; 983 }; 984 985 spi12: spi@890000 { 986 compatible = "qcom,geni-spi"; 987 reg = <0 0x00890000 0 0x4000>; 988 clock-names = "se"; 989 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 990 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 995 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", "qup-memory"; 997 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 998 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 i2c13: i2c@894000 { 1006 compatible = "qcom,geni-i2c"; 1007 reg = <0 0x00894000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_i2c13_data_clk>; 1012 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1016 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1017 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1018 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1019 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1020 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1021 dma-names = "tx", "rx"; 1022 status = "disabled"; 1023 }; 1024 1025 spi13: spi@894000 { 1026 compatible = "qcom,geni-spi"; 1027 reg = <0 0x00894000 0 0x4000>; 1028 clock-names = "se"; 1029 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1034 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1035 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1037 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1038 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1039 dma-names = "tx", "rx"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c15: i2c@89c000 { 1046 compatible = "qcom,geni-i2c"; 1047 reg = <0 0x0089c000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_i2c15_data_clk>; 1052 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1057 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1058 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1059 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1060 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1061 dma-names = "tx", "rx"; 1062 status = "disabled"; 1063 }; 1064 1065 spi15: spi@89c000 { 1066 compatible = "qcom,geni-spi"; 1067 reg = <0 0x0089c000 0 0x4000>; 1068 clock-names = "se"; 1069 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1070 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1074 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1075 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1078 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1079 dma-names = "tx", "rx"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 }; 1085 1086 i2c_master_hub_0: geniqup@9c0000 { 1087 compatible = "qcom,geni-se-i2c-master-hub"; 1088 reg = <0x0 0x009c0000 0x0 0x2000>; 1089 clock-names = "s-ahb"; 1090 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1091 #address-cells = <2>; 1092 #size-cells = <2>; 1093 ranges; 1094 status = "disabled"; 1095 1096 i2c_hub_0: i2c@980000 { 1097 compatible = "qcom,geni-i2c-master-hub"; 1098 reg = <0x0 0x00980000 0x0 0x4000>; 1099 clock-names = "se", "core"; 1100 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1101 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&hub_i2c0_data_clk>; 1104 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1108 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1109 interconnect-names = "qup-core", "qup-config"; 1110 status = "disabled"; 1111 }; 1112 1113 i2c_hub_1: i2c@984000 { 1114 compatible = "qcom,geni-i2c-master-hub"; 1115 reg = <0x0 0x00984000 0x0 0x4000>; 1116 clock-names = "se", "core"; 1117 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1118 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&hub_i2c1_data_clk>; 1121 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1125 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1126 interconnect-names = "qup-core", "qup-config"; 1127 status = "disabled"; 1128 }; 1129 1130 i2c_hub_2: i2c@988000 { 1131 compatible = "qcom,geni-i2c-master-hub"; 1132 reg = <0x0 0x00988000 0x0 0x4000>; 1133 clock-names = "se", "core"; 1134 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1135 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&hub_i2c2_data_clk>; 1138 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1143 interconnect-names = "qup-core", "qup-config"; 1144 status = "disabled"; 1145 }; 1146 1147 i2c_hub_3: i2c@98c000 { 1148 compatible = "qcom,geni-i2c-master-hub"; 1149 reg = <0x0 0x0098c000 0x0 0x4000>; 1150 clock-names = "se", "core"; 1151 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1152 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&hub_i2c3_data_clk>; 1155 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 status = "disabled"; 1162 }; 1163 1164 i2c_hub_4: i2c@990000 { 1165 compatible = "qcom,geni-i2c-master-hub"; 1166 reg = <0x0 0x00990000 0x0 0x4000>; 1167 clock-names = "se", "core"; 1168 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1169 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&hub_i2c4_data_clk>; 1172 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1176 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1177 interconnect-names = "qup-core", "qup-config"; 1178 status = "disabled"; 1179 }; 1180 1181 i2c_hub_5: i2c@994000 { 1182 compatible = "qcom,geni-i2c-master-hub"; 1183 reg = <0 0x00994000 0 0x4000>; 1184 clock-names = "se", "core"; 1185 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1186 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1187 pinctrl-names = "default"; 1188 pinctrl-0 = <&hub_i2c5_data_clk>; 1189 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1193 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1194 interconnect-names = "qup-core", "qup-config"; 1195 status = "disabled"; 1196 }; 1197 1198 i2c_hub_6: i2c@998000 { 1199 compatible = "qcom,geni-i2c-master-hub"; 1200 reg = <0 0x00998000 0 0x4000>; 1201 clock-names = "se", "core"; 1202 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1203 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&hub_i2c6_data_clk>; 1206 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c_hub_7: i2c@99c000 { 1216 compatible = "qcom,geni-i2c-master-hub"; 1217 reg = <0 0x0099c000 0 0x4000>; 1218 clock-names = "se", "core"; 1219 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1220 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&hub_i2c7_data_clk>; 1223 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1228 interconnect-names = "qup-core", "qup-config"; 1229 status = "disabled"; 1230 }; 1231 1232 i2c_hub_8: i2c@9a0000 { 1233 compatible = "qcom,geni-i2c-master-hub"; 1234 reg = <0 0x009a0000 0 0x4000>; 1235 clock-names = "se", "core"; 1236 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1237 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&hub_i2c8_data_clk>; 1240 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1245 interconnect-names = "qup-core", "qup-config"; 1246 status = "disabled"; 1247 }; 1248 1249 i2c_hub_9: i2c@9a4000 { 1250 compatible = "qcom,geni-i2c-master-hub"; 1251 reg = <0 0x009a4000 0 0x4000>; 1252 clock-names = "se", "core"; 1253 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1254 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&hub_i2c9_data_clk>; 1257 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 }; 1266 1267 gpi_dma1: dma-controller@a00000 { 1268 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1269 #dma-cells = <3>; 1270 reg = <0 0x00a00000 0 0x60000>; 1271 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1283 dma-channels = <12>; 1284 dma-channel-mask = <0x1e>; 1285 iommus = <&apps_smmu 0xb6 0>; 1286 status = "disabled"; 1287 }; 1288 1289 qupv3_id_0: geniqup@ac0000 { 1290 compatible = "qcom,geni-se-qup"; 1291 reg = <0 0x00ac0000 0 0x2000>; 1292 ranges; 1293 clock-names = "m-ahb", "s-ahb"; 1294 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1295 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1296 iommus = <&apps_smmu 0xa3 0>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1298 interconnect-names = "qup-core"; 1299 #address-cells = <2>; 1300 #size-cells = <2>; 1301 status = "disabled"; 1302 1303 i2c0: i2c@a80000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a80000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c0_data_clk>; 1310 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1315 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1317 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1318 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1319 dma-names = "tx", "rx"; 1320 status = "disabled"; 1321 }; 1322 1323 spi0: spi@a80000 { 1324 compatible = "qcom,geni-spi"; 1325 reg = <0 0x00a80000 0 0x4000>; 1326 clock-names = "se"; 1327 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1328 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1331 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1333 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1334 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1335 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1336 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1337 dma-names = "tx", "rx"; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 i2c1: i2c@a84000 { 1344 compatible = "qcom,geni-i2c"; 1345 reg = <0 0x00a84000 0 0x4000>; 1346 clock-names = "se"; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_i2c1_data_clk>; 1350 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1355 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1356 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1357 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1358 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1359 dma-names = "tx", "rx"; 1360 status = "disabled"; 1361 }; 1362 1363 spi1: spi@a84000 { 1364 compatible = "qcom,geni-spi"; 1365 reg = <0 0x00a84000 0 0x4000>; 1366 clock-names = "se"; 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1368 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1371 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1372 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1373 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1374 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1375 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1376 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1377 dma-names = "tx", "rx"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 i2c2: i2c@a88000 { 1384 compatible = "qcom,geni-i2c"; 1385 reg = <0 0x00a88000 0 0x4000>; 1386 clock-names = "se"; 1387 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&qup_i2c2_data_clk>; 1390 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1395 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1396 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1398 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1399 dma-names = "tx", "rx"; 1400 status = "disabled"; 1401 }; 1402 1403 spi2: spi@a88000 { 1404 compatible = "qcom,geni-spi"; 1405 reg = <0 0x00a88000 0 0x4000>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1408 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1413 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1414 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1415 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1416 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1417 dma-names = "tx", "rx"; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 i2c3: i2c@a8c000 { 1424 compatible = "qcom,geni-i2c"; 1425 reg = <0 0x00a8c000 0 0x4000>; 1426 clock-names = "se"; 1427 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&qup_i2c3_data_clk>; 1430 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1435 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1437 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1438 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1439 dma-names = "tx", "rx"; 1440 status = "disabled"; 1441 }; 1442 1443 spi3: spi@a8c000 { 1444 compatible = "qcom,geni-spi"; 1445 reg = <0 0x00a8c000 0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1448 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1451 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1452 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1453 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1454 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1455 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1456 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1457 dma-names = "tx", "rx"; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 1463 i2c4: i2c@a90000 { 1464 compatible = "qcom,geni-i2c"; 1465 reg = <0 0x00a90000 0 0x4000>; 1466 clock-names = "se"; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&qup_i2c4_data_clk>; 1470 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1478 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1479 dma-names = "tx", "rx"; 1480 status = "disabled"; 1481 }; 1482 1483 spi4: spi@a90000 { 1484 compatible = "qcom,geni-spi"; 1485 reg = <0 0x00a90000 0 0x4000>; 1486 clock-names = "se"; 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1488 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1489 pinctrl-names = "default"; 1490 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1492 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1493 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1495 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1496 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1497 dma-names = "tx", "rx"; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 1503 i2c5: i2c@a94000 { 1504 compatible = "qcom,geni-i2c"; 1505 reg = <0 0x00a94000 0 0x4000>; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1508 pinctrl-names = "default"; 1509 pinctrl-0 = <&qup_i2c5_data_clk>; 1510 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1513 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1514 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1515 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1516 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1517 dma-names = "tx", "rx"; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 spi5: spi@a94000 { 1524 compatible = "qcom,geni-spi"; 1525 reg = <0 0x00a94000 0 0x4000>; 1526 clock-names = "se"; 1527 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1528 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1531 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1532 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1533 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1534 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1535 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1536 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1537 dma-names = "tx", "rx"; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 1543 i2c6: i2c@a98000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0 0x00a98000 0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1548 pinctrl-names = "default"; 1549 pinctrl-0 = <&qup_i2c6_data_clk>; 1550 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1553 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1554 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1555 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1556 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1557 dma-names = "tx", "rx"; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 status = "disabled"; 1561 }; 1562 1563 spi6: spi@a98000 { 1564 compatible = "qcom,geni-spi"; 1565 reg = <0 0x00a98000 0 0x4000>; 1566 clock-names = "se"; 1567 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1568 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1571 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1572 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1573 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1574 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1575 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1576 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1577 dma-names = "tx", "rx"; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 status = "disabled"; 1581 }; 1582 1583 uart7: serial@a9c000 { 1584 compatible = "qcom,geni-debug-uart"; 1585 reg = <0 0x00a9c000 0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1588 pinctrl-names = "default"; 1589 pinctrl-0 = <&qup_uart7_default>; 1590 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1591 interconnect-names = "qup-core", "qup-config"; 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1593 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1594 status = "disabled"; 1595 }; 1596 }; 1597 1598 cnoc_main: interconnect@1500000 { 1599 compatible = "qcom,sm8550-cnoc-main"; 1600 reg = <0 0x01500000 0 0x13080>; 1601 #interconnect-cells = <2>; 1602 qcom,bcm-voters = <&apps_bcm_voter>; 1603 }; 1604 1605 config_noc: interconnect@1600000 { 1606 compatible = "qcom,sm8550-config-noc"; 1607 reg = <0 0x01600000 0 0x6200>; 1608 #interconnect-cells = <2>; 1609 qcom,bcm-voters = <&apps_bcm_voter>; 1610 }; 1611 1612 system_noc: interconnect@1680000 { 1613 compatible = "qcom,sm8550-system-noc"; 1614 reg = <0 0x01680000 0 0x1d080>; 1615 #interconnect-cells = <2>; 1616 qcom,bcm-voters = <&apps_bcm_voter>; 1617 }; 1618 1619 pcie_noc: interconnect@16c0000 { 1620 compatible = "qcom,sm8550-pcie-anoc"; 1621 reg = <0 0x016c0000 0 0x12200>; 1622 #interconnect-cells = <2>; 1623 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1624 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1625 qcom,bcm-voters = <&apps_bcm_voter>; 1626 }; 1627 1628 aggre1_noc: interconnect@16e0000 { 1629 compatible = "qcom,sm8550-aggre1-noc"; 1630 reg = <0 0x016e0000 0 0x14400>; 1631 #interconnect-cells = <2>; 1632 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1633 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1634 qcom,bcm-voters = <&apps_bcm_voter>; 1635 }; 1636 1637 aggre2_noc: interconnect@1700000 { 1638 compatible = "qcom,sm8550-aggre2-noc"; 1639 reg = <0 0x01700000 0 0x1e400>; 1640 #interconnect-cells = <2>; 1641 clocks = <&rpmhcc RPMH_IPA_CLK>; 1642 qcom,bcm-voters = <&apps_bcm_voter>; 1643 }; 1644 1645 mmss_noc: interconnect@1780000 { 1646 compatible = "qcom,sm8550-mmss-noc"; 1647 reg = <0 0x01780000 0 0x5b800>; 1648 #interconnect-cells = <2>; 1649 qcom,bcm-voters = <&apps_bcm_voter>; 1650 }; 1651 1652 pcie0: pci@1c00000 { 1653 device_type = "pci"; 1654 compatible = "qcom,pcie-sm8550"; 1655 reg = <0 0x01c00000 0 0x3000>, 1656 <0 0x60000000 0 0xf1d>, 1657 <0 0x60000f20 0 0xa8>, 1658 <0 0x60001000 0 0x1000>, 1659 <0 0x60100000 0 0x100000>; 1660 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1661 #address-cells = <3>; 1662 #size-cells = <2>; 1663 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1664 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1665 bus-range = <0x00 0xff>; 1666 1667 dma-coherent; 1668 1669 linux,pci-domain = <0>; 1670 num-lanes = <2>; 1671 1672 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1673 interrupt-names = "msi"; 1674 1675 #interrupt-cells = <1>; 1676 interrupt-map-mask = <0 0 0 0x7>; 1677 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1678 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1679 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1680 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1681 1682 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1683 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1684 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1685 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1686 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1687 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1688 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1689 clock-names = "aux", 1690 "cfg", 1691 "bus_master", 1692 "bus_slave", 1693 "slave_q2a", 1694 "ddrss_sf_tbu", 1695 "noc_aggr"; 1696 1697 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1699 interconnect-names = "pcie-mem", "cpu-pcie"; 1700 1701 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1702 <0x100 &apps_smmu 0x1401 0x1>; 1703 1704 resets = <&gcc GCC_PCIE_0_BCR>; 1705 reset-names = "pci"; 1706 1707 power-domains = <&gcc PCIE_0_GDSC>; 1708 1709 phys = <&pcie0_phy>; 1710 phy-names = "pciephy"; 1711 1712 status = "disabled"; 1713 }; 1714 1715 pcie0_phy: phy@1c06000 { 1716 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1717 reg = <0 0x01c06000 0 0x2000>; 1718 1719 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1720 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1721 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1722 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1723 <&gcc GCC_PCIE_0_PIPE_CLK>; 1724 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1725 "pipe"; 1726 1727 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1728 reset-names = "phy"; 1729 1730 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1731 assigned-clock-rates = <100000000>; 1732 1733 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1734 1735 #clock-cells = <0>; 1736 clock-output-names = "pcie0_pipe_clk"; 1737 1738 #phy-cells = <0>; 1739 1740 status = "disabled"; 1741 }; 1742 1743 pcie1: pci@1c08000 { 1744 device_type = "pci"; 1745 compatible = "qcom,pcie-sm8550"; 1746 reg = <0x0 0x01c08000 0x0 0x3000>, 1747 <0x0 0x40000000 0x0 0xf1d>, 1748 <0x0 0x40000f20 0x0 0xa8>, 1749 <0x0 0x40001000 0x0 0x1000>, 1750 <0x0 0x40100000 0x0 0x100000>; 1751 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1752 #address-cells = <3>; 1753 #size-cells = <2>; 1754 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1755 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1756 bus-range = <0x00 0xff>; 1757 1758 dma-coherent; 1759 1760 linux,pci-domain = <1>; 1761 num-lanes = <2>; 1762 1763 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1764 interrupt-names = "msi"; 1765 1766 #interrupt-cells = <1>; 1767 interrupt-map-mask = <0 0 0 0x7>; 1768 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1769 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1770 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1771 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1772 1773 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1774 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1775 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1776 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1777 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1778 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1779 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1780 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1781 clock-names = "aux", 1782 "cfg", 1783 "bus_master", 1784 "bus_slave", 1785 "slave_q2a", 1786 "ddrss_sf_tbu", 1787 "noc_aggr", 1788 "cnoc_sf_axi"; 1789 1790 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1791 assigned-clock-rates = <19200000>; 1792 1793 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1794 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1795 interconnect-names = "pcie-mem", "cpu-pcie"; 1796 1797 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1798 <0x100 &apps_smmu 0x1481 0x1>; 1799 1800 resets = <&gcc GCC_PCIE_1_BCR>, 1801 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1802 reset-names = "pci", "link_down"; 1803 1804 power-domains = <&gcc PCIE_1_GDSC>; 1805 1806 phys = <&pcie1_phy>; 1807 phy-names = "pciephy"; 1808 1809 status = "disabled"; 1810 }; 1811 1812 pcie1_phy: phy@1c0e000 { 1813 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1814 reg = <0x0 0x01c0e000 0x0 0x2000>; 1815 1816 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1817 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1818 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1819 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1820 <&gcc GCC_PCIE_1_PIPE_CLK>; 1821 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1822 "pipe"; 1823 1824 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1825 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1826 reset-names = "phy", "phy_nocsr"; 1827 1828 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1829 assigned-clock-rates = <100000000>; 1830 1831 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1832 1833 #clock-cells = <0>; 1834 clock-output-names = "pcie1_pipe_clk"; 1835 1836 #phy-cells = <0>; 1837 1838 status = "disabled"; 1839 }; 1840 1841 cryptobam: dma-controller@1dc4000 { 1842 compatible = "qcom,bam-v1.7.0"; 1843 reg = <0x0 0x01dc4000 0x0 0x28000>; 1844 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1845 #dma-cells = <1>; 1846 qcom,ee = <0>; 1847 qcom,controlled-remotely; 1848 iommus = <&apps_smmu 0x480 0x0>, 1849 <&apps_smmu 0x481 0x0>; 1850 }; 1851 1852 crypto: crypto@1de0000 { 1853 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1854 reg = <0x0 0x01dfa000 0x0 0x6000>; 1855 dmas = <&cryptobam 4>, <&cryptobam 5>; 1856 dma-names = "rx", "tx"; 1857 iommus = <&apps_smmu 0x480 0x0>, 1858 <&apps_smmu 0x481 0x0>; 1859 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1860 interconnect-names = "memory"; 1861 }; 1862 1863 ufs_mem_phy: phy@1d80000 { 1864 compatible = "qcom,sm8550-qmp-ufs-phy"; 1865 reg = <0x0 0x01d80000 0x0 0x2000>; 1866 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1867 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1868 clock-names = "ref", "ref_aux"; 1869 1870 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1871 1872 resets = <&ufs_mem_hc 0>; 1873 reset-names = "ufsphy"; 1874 1875 #clock-cells = <1>; 1876 #phy-cells = <0>; 1877 1878 status = "disabled"; 1879 }; 1880 1881 ufs_mem_hc: ufs@1d84000 { 1882 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1883 "jedec,ufs-2.0"; 1884 reg = <0x0 0x01d84000 0x0 0x3000>; 1885 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1886 phys = <&ufs_mem_phy>; 1887 phy-names = "ufsphy"; 1888 lanes-per-direction = <2>; 1889 #reset-cells = <1>; 1890 resets = <&gcc GCC_UFS_PHY_BCR>; 1891 reset-names = "rst"; 1892 1893 power-domains = <&gcc UFS_PHY_GDSC>; 1894 required-opps = <&rpmhpd_opp_nom>; 1895 1896 iommus = <&apps_smmu 0x60 0x0>; 1897 dma-coherent; 1898 1899 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1900 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1901 1902 interconnect-names = "ufs-ddr", "cpu-ufs"; 1903 clock-names = "core_clk", 1904 "bus_aggr_clk", 1905 "iface_clk", 1906 "core_clk_unipro", 1907 "ref_clk", 1908 "tx_lane0_sync_clk", 1909 "rx_lane0_sync_clk", 1910 "rx_lane1_sync_clk"; 1911 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1912 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1913 <&gcc GCC_UFS_PHY_AHB_CLK>, 1914 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1915 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1916 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1917 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1918 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1919 freq-table-hz = 1920 <75000000 300000000>, 1921 <0 0>, 1922 <0 0>, 1923 <75000000 300000000>, 1924 <100000000 403000000>, 1925 <0 0>, 1926 <0 0>, 1927 <0 0>; 1928 qcom,ice = <&ice>; 1929 1930 status = "disabled"; 1931 }; 1932 1933 ice: crypto@1d88000 { 1934 compatible = "qcom,sm8550-inline-crypto-engine", 1935 "qcom,inline-crypto-engine"; 1936 reg = <0 0x01d88000 0 0x8000>; 1937 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1938 }; 1939 1940 tcsr_mutex: hwlock@1f40000 { 1941 compatible = "qcom,tcsr-mutex"; 1942 reg = <0 0x01f40000 0 0x20000>; 1943 #hwlock-cells = <1>; 1944 }; 1945 1946 tcsr: clock-controller@1fc0000 { 1947 compatible = "qcom,sm8550-tcsr", "syscon"; 1948 reg = <0 0x01fc0000 0 0x30000>; 1949 clocks = <&rpmhcc RPMH_CXO_CLK>; 1950 #clock-cells = <1>; 1951 #reset-cells = <1>; 1952 }; 1953 1954 remoteproc_mpss: remoteproc@4080000 { 1955 compatible = "qcom,sm8550-mpss-pas"; 1956 reg = <0x0 0x04080000 0x0 0x4040>; 1957 1958 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1959 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1960 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1961 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1962 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1963 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1964 interrupt-names = "wdog", "fatal", "ready", "handover", 1965 "stop-ack", "shutdown-ack"; 1966 1967 clocks = <&rpmhcc RPMH_CXO_CLK>; 1968 clock-names = "xo"; 1969 1970 power-domains = <&rpmhpd SM8550_CX>, 1971 <&rpmhpd SM8550_MSS>; 1972 power-domain-names = "cx", "mss"; 1973 1974 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1975 1976 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 1977 1978 qcom,qmp = <&aoss_qmp>; 1979 1980 qcom,smem-states = <&smp2p_modem_out 0>; 1981 qcom,smem-state-names = "stop"; 1982 1983 status = "disabled"; 1984 1985 glink-edge { 1986 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1987 IPCC_MPROC_SIGNAL_GLINK_QMP 1988 IRQ_TYPE_EDGE_RISING>; 1989 mboxes = <&ipcc IPCC_CLIENT_MPSS 1990 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1991 label = "mpss"; 1992 qcom,remote-pid = <1>; 1993 }; 1994 }; 1995 1996 lpass_wsa2macro: codec@6aa0000 { 1997 compatible = "qcom,sm8550-lpass-wsa-macro"; 1998 reg = <0 0x06aa0000 0 0x1000>; 1999 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2000 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2001 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2002 <&lpass_vamacro>; 2003 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2004 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2005 assigned-clock-rates = <19200000>; 2006 2007 #clock-cells = <0>; 2008 clock-output-names = "wsa2-mclk"; 2009 pinctrl-names = "default"; 2010 pinctrl-0 = <&wsa2_swr_active>; 2011 #sound-dai-cells = <1>; 2012 }; 2013 2014 swr3: soundwire-controller@6ab0000 { 2015 compatible = "qcom,soundwire-v2.0.0"; 2016 reg = <0 0x06ab0000 0 0x10000>; 2017 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2018 clocks = <&lpass_wsa2macro>; 2019 clock-names = "iface"; 2020 label = "WSA2"; 2021 2022 qcom,din-ports = <4>; 2023 qcom,dout-ports = <9>; 2024 2025 qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2026 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2027 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2028 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2029 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2030 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2031 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2032 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2033 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2034 2035 #address-cells = <2>; 2036 #size-cells = <0>; 2037 #sound-dai-cells = <1>; 2038 status = "disabled"; 2039 }; 2040 2041 lpass_rxmacro: codec@6ac0000 { 2042 compatible = "qcom,sm8550-lpass-rx-macro"; 2043 reg = <0 0x06ac0000 0 0x1000>; 2044 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2045 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2046 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2047 <&lpass_vamacro>; 2048 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2049 2050 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2051 assigned-clock-rates = <19200000>; 2052 2053 #clock-cells = <0>; 2054 clock-output-names = "mclk"; 2055 pinctrl-names = "default"; 2056 pinctrl-0 = <&rx_swr_active>; 2057 #sound-dai-cells = <1>; 2058 }; 2059 2060 swr1: soundwire-controller@6ad0000 { 2061 compatible = "qcom,soundwire-v2.0.0"; 2062 reg = <0 0x06ad0000 0 0x10000>; 2063 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2064 clocks = <&lpass_rxmacro>; 2065 clock-names = "iface"; 2066 label = "RX"; 2067 2068 qcom,din-ports = <0>; 2069 qcom,dout-ports = <10>; 2070 2071 qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2072 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2073 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2074 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2075 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2076 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2077 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2078 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2079 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2080 2081 #address-cells = <2>; 2082 #size-cells = <0>; 2083 #sound-dai-cells = <1>; 2084 status = "disabled"; 2085 }; 2086 2087 lpass_txmacro: codec@6ae0000 { 2088 compatible = "qcom,sm8550-lpass-tx-macro"; 2089 reg = <0 0x06ae0000 0 0x1000>; 2090 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2091 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2092 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2093 <&lpass_vamacro>; 2094 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2095 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2096 2097 assigned-clock-rates = <19200000>; 2098 2099 #clock-cells = <0>; 2100 clock-output-names = "mclk"; 2101 pinctrl-names = "default"; 2102 pinctrl-0 = <&tx_swr_active>; 2103 #sound-dai-cells = <1>; 2104 }; 2105 2106 lpass_wsamacro: codec@6b00000 { 2107 compatible = "qcom,sm8550-lpass-wsa-macro"; 2108 reg = <0 0x06b00000 0 0x1000>; 2109 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2110 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2111 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2112 <&lpass_vamacro>; 2113 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2114 2115 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2116 assigned-clock-rates = <19200000>; 2117 2118 #clock-cells = <0>; 2119 clock-output-names = "mclk"; 2120 pinctrl-names = "default"; 2121 pinctrl-0 = <&wsa_swr_active>; 2122 #sound-dai-cells = <1>; 2123 }; 2124 2125 swr0: soundwire-controller@6b10000 { 2126 compatible = "qcom,soundwire-v2.0.0"; 2127 reg = <0 0x06b10000 0 0x10000>; 2128 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2129 clocks = <&lpass_wsamacro>; 2130 clock-names = "iface"; 2131 label = "WSA"; 2132 2133 qcom,din-ports = <4>; 2134 qcom,dout-ports = <9>; 2135 2136 qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2137 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2138 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2139 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2140 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2141 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2142 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2143 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2144 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2145 2146 #address-cells = <2>; 2147 #size-cells = <0>; 2148 #sound-dai-cells = <1>; 2149 status = "disabled"; 2150 }; 2151 2152 swr2: soundwire-controller@6d30000 { 2153 compatible = "qcom,soundwire-v2.0.0"; 2154 reg = <0 0x06d30000 0 0x10000>; 2155 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2157 interrupt-names = "core", "wakeup"; 2158 clocks = <&lpass_vamacro>; 2159 clock-names = "iface"; 2160 label = "TX"; 2161 2162 qcom,din-ports = <4>; 2163 qcom,dout-ports = <0>; 2164 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2165 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2166 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2167 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2168 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2169 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2170 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2171 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2172 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2173 2174 #address-cells = <2>; 2175 #size-cells = <0>; 2176 #sound-dai-cells = <1>; 2177 status = "disabled"; 2178 }; 2179 2180 lpass_vamacro: codec@6d44000 { 2181 compatible = "qcom,sm8550-lpass-va-macro"; 2182 reg = <0 0x06d44000 0 0x1000>; 2183 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2184 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2185 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2186 clock-names = "mclk", "macro", "dcodec"; 2187 2188 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2189 assigned-clock-rates = <19200000>; 2190 2191 #clock-cells = <0>; 2192 clock-output-names = "fsgen"; 2193 #sound-dai-cells = <1>; 2194 }; 2195 2196 lpass_tlmm: pinctrl@6e80000 { 2197 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2198 reg = <0 0x06e80000 0 0x20000>, 2199 <0 0x07250000 0 0x10000>; 2200 gpio-controller; 2201 #gpio-cells = <2>; 2202 gpio-ranges = <&lpass_tlmm 0 0 23>; 2203 2204 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2205 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2206 clock-names = "core", "audio"; 2207 2208 tx_swr_active: tx-swr-active-state { 2209 clk-pins { 2210 pins = "gpio0"; 2211 function = "swr_tx_clk"; 2212 drive-strength = <2>; 2213 slew-rate = <1>; 2214 bias-disable; 2215 }; 2216 2217 data-pins { 2218 pins = "gpio1", "gpio2", "gpio14"; 2219 function = "swr_tx_data"; 2220 drive-strength = <2>; 2221 slew-rate = <1>; 2222 bias-bus-hold; 2223 }; 2224 }; 2225 2226 rx_swr_active: rx-swr-active-state { 2227 clk-pins { 2228 pins = "gpio3"; 2229 function = "swr_rx_clk"; 2230 drive-strength = <2>; 2231 slew-rate = <1>; 2232 bias-disable; 2233 }; 2234 2235 data-pins { 2236 pins = "gpio4", "gpio5"; 2237 function = "swr_rx_data"; 2238 drive-strength = <2>; 2239 slew-rate = <1>; 2240 bias-bus-hold; 2241 }; 2242 }; 2243 2244 dmic01_default: dmic01-default-state { 2245 clk-pins { 2246 pins = "gpio6"; 2247 function = "dmic1_clk"; 2248 drive-strength = <8>; 2249 output-high; 2250 }; 2251 2252 data-pins { 2253 pins = "gpio7"; 2254 function = "dmic1_data"; 2255 drive-strength = <8>; 2256 input-enable; 2257 }; 2258 }; 2259 2260 dmic02_default: dmic02-default-state { 2261 clk-pins { 2262 pins = "gpio8"; 2263 function = "dmic2_clk"; 2264 drive-strength = <8>; 2265 output-high; 2266 }; 2267 2268 data-pins { 2269 pins = "gpio9"; 2270 function = "dmic2_data"; 2271 drive-strength = <8>; 2272 input-enable; 2273 }; 2274 }; 2275 2276 wsa_swr_active: wsa-swr-active-state { 2277 clk-pins { 2278 pins = "gpio10"; 2279 function = "wsa_swr_clk"; 2280 drive-strength = <2>; 2281 slew-rate = <1>; 2282 bias-disable; 2283 }; 2284 2285 data-pins { 2286 pins = "gpio11"; 2287 function = "wsa_swr_data"; 2288 drive-strength = <2>; 2289 slew-rate = <1>; 2290 bias-bus-hold; 2291 }; 2292 }; 2293 2294 wsa2_swr_active: wsa2-swr-active-state { 2295 clk-pins { 2296 pins = "gpio15"; 2297 function = "wsa2_swr_clk"; 2298 drive-strength = <2>; 2299 slew-rate = <1>; 2300 bias-disable; 2301 }; 2302 2303 data-pins { 2304 pins = "gpio16"; 2305 function = "wsa2_swr_data"; 2306 drive-strength = <2>; 2307 slew-rate = <1>; 2308 bias-bus-hold; 2309 }; 2310 }; 2311 }; 2312 2313 lpass_lpiaon_noc: interconnect@7400000 { 2314 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2315 reg = <0 0x07400000 0 0x19080>; 2316 #interconnect-cells = <2>; 2317 qcom,bcm-voters = <&apps_bcm_voter>; 2318 }; 2319 2320 lpass_lpicx_noc: interconnect@7430000 { 2321 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2322 reg = <0 0x07430000 0 0x3a200>; 2323 #interconnect-cells = <2>; 2324 qcom,bcm-voters = <&apps_bcm_voter>; 2325 }; 2326 2327 lpass_ag_noc: interconnect@7e40000 { 2328 compatible = "qcom,sm8550-lpass-ag-noc"; 2329 reg = <0 0x07e40000 0 0xe080>; 2330 #interconnect-cells = <2>; 2331 qcom,bcm-voters = <&apps_bcm_voter>; 2332 }; 2333 2334 sdhc_2: mmc@8804000 { 2335 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2336 reg = <0 0x08804000 0 0x1000>; 2337 2338 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2340 interrupt-names = "hc_irq", "pwr_irq"; 2341 2342 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2343 <&gcc GCC_SDCC2_APPS_CLK>, 2344 <&rpmhcc RPMH_CXO_CLK>; 2345 clock-names = "iface", "core", "xo"; 2346 iommus = <&apps_smmu 0x540 0>; 2347 qcom,dll-config = <0x0007642c>; 2348 qcom,ddr-config = <0x80040868>; 2349 power-domains = <&rpmhpd SM8550_CX>; 2350 operating-points-v2 = <&sdhc2_opp_table>; 2351 2352 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2354 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2355 bus-width = <4>; 2356 dma-coherent; 2357 2358 /* Forbid SDR104/SDR50 - broken hw! */ 2359 sdhci-caps-mask = <0x3 0>; 2360 2361 status = "disabled"; 2362 2363 sdhc2_opp_table: opp-table { 2364 compatible = "operating-points-v2"; 2365 2366 opp-19200000 { 2367 opp-hz = /bits/ 64 <19200000>; 2368 required-opps = <&rpmhpd_opp_min_svs>; 2369 }; 2370 2371 opp-50000000 { 2372 opp-hz = /bits/ 64 <50000000>; 2373 required-opps = <&rpmhpd_opp_low_svs>; 2374 }; 2375 2376 opp-100000000 { 2377 opp-hz = /bits/ 64 <100000000>; 2378 required-opps = <&rpmhpd_opp_svs>; 2379 }; 2380 2381 opp-202000000 { 2382 opp-hz = /bits/ 64 <202000000>; 2383 required-opps = <&rpmhpd_opp_svs_l1>; 2384 }; 2385 }; 2386 }; 2387 2388 mdss: display-subsystem@ae00000 { 2389 compatible = "qcom,sm8550-mdss"; 2390 reg = <0 0x0ae00000 0 0x1000>; 2391 reg-names = "mdss"; 2392 2393 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2394 interrupt-controller; 2395 #interrupt-cells = <1>; 2396 2397 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2398 <&gcc GCC_DISP_AHB_CLK>, 2399 <&gcc GCC_DISP_HF_AXI_CLK>, 2400 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2401 2402 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2403 2404 power-domains = <&dispcc MDSS_GDSC>; 2405 2406 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2407 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2408 interconnect-names = "mdp0-mem", "mdp1-mem"; 2409 2410 iommus = <&apps_smmu 0x1c00 0x2>; 2411 2412 #address-cells = <2>; 2413 #size-cells = <2>; 2414 ranges; 2415 2416 status = "disabled"; 2417 2418 mdss_mdp: display-controller@ae01000 { 2419 compatible = "qcom,sm8550-dpu"; 2420 reg = <0 0x0ae01000 0 0x8f000>, 2421 <0 0x0aeb0000 0 0x2008>; 2422 reg-names = "mdp", "vbif"; 2423 2424 interrupt-parent = <&mdss>; 2425 interrupts = <0>; 2426 2427 clocks = <&gcc GCC_DISP_AHB_CLK>, 2428 <&gcc GCC_DISP_HF_AXI_CLK>, 2429 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2430 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2431 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2432 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2433 clock-names = "bus", 2434 "nrt_bus", 2435 "iface", 2436 "lut", 2437 "core", 2438 "vsync"; 2439 2440 power-domains = <&rpmhpd SM8550_MMCX>; 2441 2442 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2443 assigned-clock-rates = <19200000>; 2444 2445 operating-points-v2 = <&mdp_opp_table>; 2446 2447 ports { 2448 #address-cells = <1>; 2449 #size-cells = <0>; 2450 2451 port@0 { 2452 reg = <0>; 2453 dpu_intf1_out: endpoint { 2454 remote-endpoint = <&mdss_dsi0_in>; 2455 }; 2456 }; 2457 2458 port@1 { 2459 reg = <1>; 2460 dpu_intf2_out: endpoint { 2461 remote-endpoint = <&mdss_dsi1_in>; 2462 }; 2463 }; 2464 }; 2465 2466 mdp_opp_table: opp-table { 2467 compatible = "operating-points-v2"; 2468 2469 opp-200000000 { 2470 opp-hz = /bits/ 64 <200000000>; 2471 required-opps = <&rpmhpd_opp_low_svs>; 2472 }; 2473 2474 opp-325000000 { 2475 opp-hz = /bits/ 64 <325000000>; 2476 required-opps = <&rpmhpd_opp_svs>; 2477 }; 2478 2479 opp-375000000 { 2480 opp-hz = /bits/ 64 <375000000>; 2481 required-opps = <&rpmhpd_opp_svs_l1>; 2482 }; 2483 2484 opp-514000000 { 2485 opp-hz = /bits/ 64 <514000000>; 2486 required-opps = <&rpmhpd_opp_nom>; 2487 }; 2488 }; 2489 }; 2490 2491 mdss_dsi0: dsi@ae94000 { 2492 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2493 reg = <0 0x0ae94000 0 0x400>; 2494 reg-names = "dsi_ctrl"; 2495 2496 interrupt-parent = <&mdss>; 2497 interrupts = <4>; 2498 2499 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2500 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2501 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2502 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2503 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2504 <&gcc GCC_DISP_HF_AXI_CLK>; 2505 clock-names = "byte", 2506 "byte_intf", 2507 "pixel", 2508 "core", 2509 "iface", 2510 "bus"; 2511 2512 power-domains = <&rpmhpd SM8550_MMCX>; 2513 2514 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2515 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2516 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2517 <&mdss_dsi0_phy 1>; 2518 2519 operating-points-v2 = <&mdss_dsi_opp_table>; 2520 2521 phys = <&mdss_dsi0_phy>; 2522 phy-names = "dsi"; 2523 2524 #address-cells = <1>; 2525 #size-cells = <0>; 2526 2527 status = "disabled"; 2528 2529 ports { 2530 #address-cells = <1>; 2531 #size-cells = <0>; 2532 2533 port@0 { 2534 reg = <0>; 2535 mdss_dsi0_in: endpoint { 2536 remote-endpoint = <&dpu_intf1_out>; 2537 }; 2538 }; 2539 2540 port@1 { 2541 reg = <1>; 2542 mdss_dsi0_out: endpoint { 2543 }; 2544 }; 2545 }; 2546 2547 mdss_dsi_opp_table: opp-table { 2548 compatible = "operating-points-v2"; 2549 2550 opp-187500000 { 2551 opp-hz = /bits/ 64 <187500000>; 2552 required-opps = <&rpmhpd_opp_low_svs>; 2553 }; 2554 2555 opp-300000000 { 2556 opp-hz = /bits/ 64 <300000000>; 2557 required-opps = <&rpmhpd_opp_svs>; 2558 }; 2559 2560 opp-358000000 { 2561 opp-hz = /bits/ 64 <358000000>; 2562 required-opps = <&rpmhpd_opp_svs_l1>; 2563 }; 2564 }; 2565 }; 2566 2567 mdss_dsi0_phy: phy@ae95000 { 2568 compatible = "qcom,sm8550-dsi-phy-4nm"; 2569 reg = <0 0x0ae95000 0 0x200>, 2570 <0 0x0ae95200 0 0x280>, 2571 <0 0x0ae95500 0 0x400>; 2572 reg-names = "dsi_phy", 2573 "dsi_phy_lane", 2574 "dsi_pll"; 2575 2576 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2577 <&rpmhcc RPMH_CXO_CLK>; 2578 clock-names = "iface", "ref"; 2579 2580 #clock-cells = <1>; 2581 #phy-cells = <0>; 2582 2583 status = "disabled"; 2584 }; 2585 2586 mdss_dsi1: dsi@ae96000 { 2587 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2588 reg = <0 0x0ae96000 0 0x400>; 2589 reg-names = "dsi_ctrl"; 2590 2591 interrupt-parent = <&mdss>; 2592 interrupts = <5>; 2593 2594 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2595 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2596 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2597 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2598 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2599 <&gcc GCC_DISP_HF_AXI_CLK>; 2600 clock-names = "byte", 2601 "byte_intf", 2602 "pixel", 2603 "core", 2604 "iface", 2605 "bus"; 2606 2607 power-domains = <&rpmhpd SM8550_MMCX>; 2608 2609 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2610 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2611 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2612 <&mdss_dsi1_phy 1>; 2613 2614 operating-points-v2 = <&mdss_dsi_opp_table>; 2615 2616 phys = <&mdss_dsi1_phy>; 2617 phy-names = "dsi"; 2618 2619 #address-cells = <1>; 2620 #size-cells = <0>; 2621 2622 status = "disabled"; 2623 2624 ports { 2625 #address-cells = <1>; 2626 #size-cells = <0>; 2627 2628 port@0 { 2629 reg = <0>; 2630 mdss_dsi1_in: endpoint { 2631 remote-endpoint = <&dpu_intf2_out>; 2632 }; 2633 }; 2634 2635 port@1 { 2636 reg = <1>; 2637 mdss_dsi1_out: endpoint { 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 mdss_dsi1_phy: phy@ae97000 { 2644 compatible = "qcom,sm8550-dsi-phy-4nm"; 2645 reg = <0 0x0ae97000 0 0x200>, 2646 <0 0x0ae97200 0 0x280>, 2647 <0 0x0ae97500 0 0x400>; 2648 reg-names = "dsi_phy", 2649 "dsi_phy_lane", 2650 "dsi_pll"; 2651 2652 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2653 <&rpmhcc RPMH_CXO_CLK>; 2654 clock-names = "iface", "ref"; 2655 2656 #clock-cells = <1>; 2657 #phy-cells = <0>; 2658 2659 status = "disabled"; 2660 }; 2661 }; 2662 2663 dispcc: clock-controller@af00000 { 2664 compatible = "qcom,sm8550-dispcc"; 2665 reg = <0 0x0af00000 0 0x20000>; 2666 clocks = <&bi_tcxo_div2>, 2667 <&bi_tcxo_ao_div2>, 2668 <&gcc GCC_DISP_AHB_CLK>, 2669 <&sleep_clk>, 2670 <&mdss_dsi0_phy 0>, 2671 <&mdss_dsi0_phy 1>, 2672 <&mdss_dsi1_phy 0>, 2673 <&mdss_dsi1_phy 1>, 2674 <0>, /* dp0 */ 2675 <0>, 2676 <0>, /* dp1 */ 2677 <0>, 2678 <0>, /* dp2 */ 2679 <0>, 2680 <0>, /* dp3 */ 2681 <0>; 2682 power-domains = <&rpmhpd SM8550_MMCX>; 2683 required-opps = <&rpmhpd_opp_low_svs>; 2684 #clock-cells = <1>; 2685 #reset-cells = <1>; 2686 #power-domain-cells = <1>; 2687 status = "disabled"; 2688 }; 2689 2690 usb_1_hsphy: phy@88e3000 { 2691 compatible = "qcom,sm8550-snps-eusb2-phy"; 2692 reg = <0x0 0x088e3000 0x0 0x154>; 2693 #phy-cells = <0>; 2694 2695 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2696 clock-names = "ref"; 2697 2698 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2699 2700 status = "disabled"; 2701 }; 2702 2703 usb_dp_qmpphy: phy@88e8000 { 2704 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2705 reg = <0x0 0x088e8000 0x0 0x3000>; 2706 2707 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2708 <&rpmhcc RPMH_CXO_CLK>, 2709 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2710 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2711 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2712 2713 power-domains = <&gcc USB3_PHY_GDSC>; 2714 2715 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2716 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2717 reset-names = "phy", "common"; 2718 2719 #clock-cells = <1>; 2720 #phy-cells = <1>; 2721 2722 status = "disabled"; 2723 }; 2724 2725 usb_1: usb@a6f8800 { 2726 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2727 reg = <0x0 0x0a6f8800 0x0 0x400>; 2728 #address-cells = <2>; 2729 #size-cells = <2>; 2730 ranges; 2731 2732 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2733 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2734 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2735 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2736 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2737 <&tcsr TCSR_USB3_CLKREF_EN>; 2738 clock-names = "cfg_noc", 2739 "core", 2740 "iface", 2741 "sleep", 2742 "mock_utmi", 2743 "xo"; 2744 2745 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2746 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2747 assigned-clock-rates = <19200000>, <200000000>; 2748 2749 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2750 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2751 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2752 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2753 interrupt-names = "hs_phy_irq", 2754 "ss_phy_irq", 2755 "dm_hs_phy_irq", 2756 "dp_hs_phy_irq"; 2757 2758 power-domains = <&gcc USB30_PRIM_GDSC>; 2759 required-opps = <&rpmhpd_opp_nom>; 2760 2761 resets = <&gcc GCC_USB30_PRIM_BCR>; 2762 2763 status = "disabled"; 2764 2765 usb_1_dwc3: usb@a600000 { 2766 compatible = "snps,dwc3"; 2767 reg = <0x0 0x0a600000 0x0 0xcd00>; 2768 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2769 iommus = <&apps_smmu 0x40 0x0>; 2770 snps,dis_u2_susphy_quirk; 2771 snps,dis_enblslpm_quirk; 2772 snps,usb3_lpm_capable; 2773 phys = <&usb_1_hsphy>, 2774 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2775 phy-names = "usb2-phy", "usb3-phy"; 2776 2777 ports { 2778 #address-cells = <1>; 2779 #size-cells = <0>; 2780 2781 port@0 { 2782 reg = <0>; 2783 2784 usb_1_dwc3_hs: endpoint { 2785 }; 2786 }; 2787 2788 port@1 { 2789 reg = <1>; 2790 2791 usb_1_dwc3_ss: endpoint { 2792 }; 2793 }; 2794 }; 2795 }; 2796 }; 2797 2798 pdc: interrupt-controller@b220000 { 2799 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2800 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2801 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2802 <125 63 1>, <126 716 12>, 2803 <138 251 5>; 2804 #interrupt-cells = <2>; 2805 interrupt-parent = <&intc>; 2806 interrupt-controller; 2807 }; 2808 2809 tsens0: thermal-sensor@c271000 { 2810 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2811 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2812 <0 0x0c222000 0 0x1000>; /* SROT */ 2813 #qcom,sensors = <16>; 2814 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2816 interrupt-names = "uplow", "critical"; 2817 #thermal-sensor-cells = <1>; 2818 }; 2819 2820 tsens1: thermal-sensor@c272000 { 2821 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2822 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2823 <0 0x0c223000 0 0x1000>; /* SROT */ 2824 #qcom,sensors = <16>; 2825 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2826 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2827 interrupt-names = "uplow", "critical"; 2828 #thermal-sensor-cells = <1>; 2829 }; 2830 2831 tsens2: thermal-sensor@c273000 { 2832 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2833 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2834 <0 0x0c224000 0 0x1000>; /* SROT */ 2835 #qcom,sensors = <16>; 2836 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2838 interrupt-names = "uplow", "critical"; 2839 #thermal-sensor-cells = <1>; 2840 }; 2841 2842 aoss_qmp: power-management@c300000 { 2843 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2844 reg = <0 0x0c300000 0 0x400>; 2845 interrupt-parent = <&ipcc>; 2846 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2847 IRQ_TYPE_EDGE_RISING>; 2848 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2849 2850 #clock-cells = <0>; 2851 }; 2852 2853 sram@c3f0000 { 2854 compatible = "qcom,rpmh-stats"; 2855 reg = <0 0x0c3f0000 0 0x400>; 2856 }; 2857 2858 spmi_bus: spmi@c400000 { 2859 compatible = "qcom,spmi-pmic-arb"; 2860 reg = <0 0x0c400000 0 0x3000>, 2861 <0 0x0c500000 0 0x4000000>, 2862 <0 0x0c440000 0 0x80000>, 2863 <0 0x0c4c0000 0 0x20000>, 2864 <0 0x0c42d000 0 0x4000>; 2865 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2866 interrupt-names = "periph_irq"; 2867 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2868 qcom,ee = <0>; 2869 qcom,channel = <0>; 2870 qcom,bus-id = <0>; 2871 #address-cells = <2>; 2872 #size-cells = <0>; 2873 interrupt-controller; 2874 #interrupt-cells = <4>; 2875 }; 2876 2877 tlmm: pinctrl@f000000 { 2878 compatible = "qcom,sm8550-tlmm"; 2879 reg = <0 0x0f100000 0 0x300000>; 2880 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2881 gpio-controller; 2882 #gpio-cells = <2>; 2883 interrupt-controller; 2884 #interrupt-cells = <2>; 2885 gpio-ranges = <&tlmm 0 0 211>; 2886 wakeup-parent = <&pdc>; 2887 2888 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2889 /* SDA, SCL */ 2890 pins = "gpio16", "gpio17"; 2891 function = "i2chub0_se0"; 2892 drive-strength = <2>; 2893 bias-pull-up; 2894 }; 2895 2896 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2897 /* SDA, SCL */ 2898 pins = "gpio18", "gpio19"; 2899 function = "i2chub0_se1"; 2900 drive-strength = <2>; 2901 bias-pull-up; 2902 }; 2903 2904 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2905 /* SDA, SCL */ 2906 pins = "gpio20", "gpio21"; 2907 function = "i2chub0_se2"; 2908 drive-strength = <2>; 2909 bias-pull-up; 2910 }; 2911 2912 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2913 /* SDA, SCL */ 2914 pins = "gpio22", "gpio23"; 2915 function = "i2chub0_se3"; 2916 drive-strength = <2>; 2917 bias-pull-up; 2918 }; 2919 2920 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2921 /* SDA, SCL */ 2922 pins = "gpio4", "gpio5"; 2923 function = "i2chub0_se4"; 2924 drive-strength = <2>; 2925 bias-pull-up; 2926 }; 2927 2928 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2929 /* SDA, SCL */ 2930 pins = "gpio6", "gpio7"; 2931 function = "i2chub0_se5"; 2932 drive-strength = <2>; 2933 bias-pull-up; 2934 }; 2935 2936 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2937 /* SDA, SCL */ 2938 pins = "gpio8", "gpio9"; 2939 function = "i2chub0_se6"; 2940 drive-strength = <2>; 2941 bias-pull-up; 2942 }; 2943 2944 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2945 /* SDA, SCL */ 2946 pins = "gpio10", "gpio11"; 2947 function = "i2chub0_se7"; 2948 drive-strength = <2>; 2949 bias-pull-up; 2950 }; 2951 2952 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2953 /* SDA, SCL */ 2954 pins = "gpio206", "gpio207"; 2955 function = "i2chub0_se8"; 2956 drive-strength = <2>; 2957 bias-pull-up; 2958 }; 2959 2960 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2961 /* SDA, SCL */ 2962 pins = "gpio84", "gpio85"; 2963 function = "i2chub0_se9"; 2964 drive-strength = <2>; 2965 bias-pull-up; 2966 }; 2967 2968 pcie0_default_state: pcie0-default-state { 2969 perst-pins { 2970 pins = "gpio94"; 2971 function = "gpio"; 2972 drive-strength = <2>; 2973 bias-pull-down; 2974 }; 2975 2976 clkreq-pins { 2977 pins = "gpio95"; 2978 function = "pcie0_clk_req_n"; 2979 drive-strength = <2>; 2980 bias-pull-up; 2981 }; 2982 2983 wake-pins { 2984 pins = "gpio96"; 2985 function = "gpio"; 2986 drive-strength = <2>; 2987 bias-pull-up; 2988 }; 2989 }; 2990 2991 pcie1_default_state: pcie1-default-state { 2992 perst-pins { 2993 pins = "gpio97"; 2994 function = "gpio"; 2995 drive-strength = <2>; 2996 bias-pull-down; 2997 }; 2998 2999 clkreq-pins { 3000 pins = "gpio98"; 3001 function = "pcie1_clk_req_n"; 3002 drive-strength = <2>; 3003 bias-pull-up; 3004 }; 3005 3006 wake-pins { 3007 pins = "gpio99"; 3008 function = "gpio"; 3009 drive-strength = <2>; 3010 bias-pull-up; 3011 }; 3012 }; 3013 3014 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3015 /* SDA, SCL */ 3016 pins = "gpio28", "gpio29"; 3017 function = "qup1_se0"; 3018 drive-strength = <2>; 3019 bias-pull-up = <2200>; 3020 }; 3021 3022 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3023 /* SDA, SCL */ 3024 pins = "gpio32", "gpio33"; 3025 function = "qup1_se1"; 3026 drive-strength = <2>; 3027 bias-pull-up = <2200>; 3028 }; 3029 3030 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3031 /* SDA, SCL */ 3032 pins = "gpio36", "gpio37"; 3033 function = "qup1_se2"; 3034 drive-strength = <2>; 3035 bias-pull-up = <2200>; 3036 }; 3037 3038 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3039 /* SDA, SCL */ 3040 pins = "gpio40", "gpio41"; 3041 function = "qup1_se3"; 3042 drive-strength = <2>; 3043 bias-pull-up = <2200>; 3044 }; 3045 3046 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3047 /* SDA, SCL */ 3048 pins = "gpio44", "gpio45"; 3049 function = "qup1_se4"; 3050 drive-strength = <2>; 3051 bias-pull-up = <2200>; 3052 }; 3053 3054 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3055 /* SDA, SCL */ 3056 pins = "gpio52", "gpio53"; 3057 function = "qup1_se5"; 3058 drive-strength = <2>; 3059 bias-pull-up = <2200>; 3060 }; 3061 3062 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3063 /* SDA, SCL */ 3064 pins = "gpio48", "gpio49"; 3065 function = "qup1_se6"; 3066 drive-strength = <2>; 3067 bias-pull-up = <2200>; 3068 }; 3069 3070 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3071 scl-pins { 3072 pins = "gpio57"; 3073 function = "qup2_se0_l1_mira"; 3074 drive-strength = <2>; 3075 bias-pull-up = <2200>; 3076 }; 3077 3078 sda-pins { 3079 pins = "gpio56"; 3080 function = "qup2_se0_l0_mira"; 3081 drive-strength = <2>; 3082 bias-pull-up = <2200>; 3083 }; 3084 }; 3085 3086 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3087 /* SDA, SCL */ 3088 pins = "gpio60", "gpio61"; 3089 function = "qup2_se1"; 3090 drive-strength = <2>; 3091 bias-pull-up = <2200>; 3092 }; 3093 3094 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3095 /* SDA, SCL */ 3096 pins = "gpio64", "gpio65"; 3097 function = "qup2_se2"; 3098 drive-strength = <2>; 3099 bias-pull-up = <2200>; 3100 }; 3101 3102 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3103 /* SDA, SCL */ 3104 pins = "gpio68", "gpio69"; 3105 function = "qup2_se3"; 3106 drive-strength = <2>; 3107 bias-pull-up = <2200>; 3108 }; 3109 3110 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3111 /* SDA, SCL */ 3112 pins = "gpio2", "gpio3"; 3113 function = "qup2_se4"; 3114 drive-strength = <2>; 3115 bias-pull-up = <2200>; 3116 }; 3117 3118 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3119 /* SDA, SCL */ 3120 pins = "gpio80", "gpio81"; 3121 function = "qup2_se5"; 3122 drive-strength = <2>; 3123 bias-pull-up = <2200>; 3124 }; 3125 3126 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3127 /* SDA, SCL */ 3128 pins = "gpio72", "gpio106"; 3129 function = "qup2_se7"; 3130 drive-strength = <2>; 3131 bias-pull-up = <2200>; 3132 }; 3133 3134 qup_spi0_cs: qup-spi0-cs-state { 3135 pins = "gpio31"; 3136 function = "qup1_se0"; 3137 drive-strength = <6>; 3138 bias-disable; 3139 }; 3140 3141 qup_spi0_data_clk: qup-spi0-data-clk-state { 3142 /* MISO, MOSI, CLK */ 3143 pins = "gpio28", "gpio29", "gpio30"; 3144 function = "qup1_se0"; 3145 drive-strength = <6>; 3146 bias-disable; 3147 }; 3148 3149 qup_spi1_cs: qup-spi1-cs-state { 3150 pins = "gpio35"; 3151 function = "qup1_se1"; 3152 drive-strength = <6>; 3153 bias-disable; 3154 }; 3155 3156 qup_spi1_data_clk: qup-spi1-data-clk-state { 3157 /* MISO, MOSI, CLK */ 3158 pins = "gpio32", "gpio33", "gpio34"; 3159 function = "qup1_se1"; 3160 drive-strength = <6>; 3161 bias-disable; 3162 }; 3163 3164 qup_spi2_cs: qup-spi2-cs-state { 3165 pins = "gpio39"; 3166 function = "qup1_se2"; 3167 drive-strength = <6>; 3168 bias-disable; 3169 }; 3170 3171 qup_spi2_data_clk: qup-spi2-data-clk-state { 3172 /* MISO, MOSI, CLK */ 3173 pins = "gpio36", "gpio37", "gpio38"; 3174 function = "qup1_se2"; 3175 drive-strength = <6>; 3176 bias-disable; 3177 }; 3178 3179 qup_spi3_cs: qup-spi3-cs-state { 3180 pins = "gpio43"; 3181 function = "qup1_se3"; 3182 drive-strength = <6>; 3183 bias-disable; 3184 }; 3185 3186 qup_spi3_data_clk: qup-spi3-data-clk-state { 3187 /* MISO, MOSI, CLK */ 3188 pins = "gpio40", "gpio41", "gpio42"; 3189 function = "qup1_se3"; 3190 drive-strength = <6>; 3191 bias-disable; 3192 }; 3193 3194 qup_spi4_cs: qup-spi4-cs-state { 3195 pins = "gpio47"; 3196 function = "qup1_se4"; 3197 drive-strength = <6>; 3198 bias-disable; 3199 }; 3200 3201 qup_spi4_data_clk: qup-spi4-data-clk-state { 3202 /* MISO, MOSI, CLK */ 3203 pins = "gpio44", "gpio45", "gpio46"; 3204 function = "qup1_se4"; 3205 drive-strength = <6>; 3206 bias-disable; 3207 }; 3208 3209 qup_spi5_cs: qup-spi5-cs-state { 3210 pins = "gpio55"; 3211 function = "qup1_se5"; 3212 drive-strength = <6>; 3213 bias-disable; 3214 }; 3215 3216 qup_spi5_data_clk: qup-spi5-data-clk-state { 3217 /* MISO, MOSI, CLK */ 3218 pins = "gpio52", "gpio53", "gpio54"; 3219 function = "qup1_se5"; 3220 drive-strength = <6>; 3221 bias-disable; 3222 }; 3223 3224 qup_spi6_cs: qup-spi6-cs-state { 3225 pins = "gpio51"; 3226 function = "qup1_se6"; 3227 drive-strength = <6>; 3228 bias-disable; 3229 }; 3230 3231 qup_spi6_data_clk: qup-spi6-data-clk-state { 3232 /* MISO, MOSI, CLK */ 3233 pins = "gpio48", "gpio49", "gpio50"; 3234 function = "qup1_se6"; 3235 drive-strength = <6>; 3236 bias-disable; 3237 }; 3238 3239 qup_spi8_cs: qup-spi8-cs-state { 3240 pins = "gpio59"; 3241 function = "qup2_se0_l3_mira"; 3242 drive-strength = <6>; 3243 bias-disable; 3244 }; 3245 3246 qup_spi8_data_clk: qup-spi8-data-clk-state { 3247 /* MISO, MOSI, CLK */ 3248 pins = "gpio56", "gpio57", "gpio58"; 3249 function = "qup2_se0_l2_mira"; 3250 drive-strength = <6>; 3251 bias-disable; 3252 }; 3253 3254 qup_spi9_cs: qup-spi9-cs-state { 3255 pins = "gpio63"; 3256 function = "qup2_se1"; 3257 drive-strength = <6>; 3258 bias-disable; 3259 }; 3260 3261 qup_spi9_data_clk: qup-spi9-data-clk-state { 3262 /* MISO, MOSI, CLK */ 3263 pins = "gpio60", "gpio61", "gpio62"; 3264 function = "qup2_se1"; 3265 drive-strength = <6>; 3266 bias-disable; 3267 }; 3268 3269 qup_spi10_cs: qup-spi10-cs-state { 3270 pins = "gpio67"; 3271 function = "qup2_se2"; 3272 drive-strength = <6>; 3273 bias-disable; 3274 }; 3275 3276 qup_spi10_data_clk: qup-spi10-data-clk-state { 3277 /* MISO, MOSI, CLK */ 3278 pins = "gpio64", "gpio65", "gpio66"; 3279 function = "qup2_se2"; 3280 drive-strength = <6>; 3281 bias-disable; 3282 }; 3283 3284 qup_spi11_cs: qup-spi11-cs-state { 3285 pins = "gpio71"; 3286 function = "qup2_se3"; 3287 drive-strength = <6>; 3288 bias-disable; 3289 }; 3290 3291 qup_spi11_data_clk: qup-spi11-data-clk-state { 3292 /* MISO, MOSI, CLK */ 3293 pins = "gpio68", "gpio69", "gpio70"; 3294 function = "qup2_se3"; 3295 drive-strength = <6>; 3296 bias-disable; 3297 }; 3298 3299 qup_spi12_cs: qup-spi12-cs-state { 3300 pins = "gpio119"; 3301 function = "qup2_se4"; 3302 drive-strength = <6>; 3303 bias-disable; 3304 }; 3305 3306 qup_spi12_data_clk: qup-spi12-data-clk-state { 3307 /* MISO, MOSI, CLK */ 3308 pins = "gpio2", "gpio3", "gpio118"; 3309 function = "qup2_se4"; 3310 drive-strength = <6>; 3311 bias-disable; 3312 }; 3313 3314 qup_spi13_cs: qup-spi13-cs-state { 3315 pins = "gpio83"; 3316 function = "qup2_se5"; 3317 drive-strength = <6>; 3318 bias-disable; 3319 }; 3320 3321 qup_spi13_data_clk: qup-spi13-data-clk-state { 3322 /* MISO, MOSI, CLK */ 3323 pins = "gpio80", "gpio81", "gpio82"; 3324 function = "qup2_se5"; 3325 drive-strength = <6>; 3326 bias-disable; 3327 }; 3328 3329 qup_spi15_cs: qup-spi15-cs-state { 3330 pins = "gpio75"; 3331 function = "qup2_se7"; 3332 drive-strength = <6>; 3333 bias-disable; 3334 }; 3335 3336 qup_spi15_data_clk: qup-spi15-data-clk-state { 3337 /* MISO, MOSI, CLK */ 3338 pins = "gpio72", "gpio106", "gpio74"; 3339 function = "qup2_se7"; 3340 drive-strength = <6>; 3341 bias-disable; 3342 }; 3343 3344 qup_uart7_default: qup-uart7-default-state { 3345 /* TX, RX */ 3346 pins = "gpio26", "gpio27"; 3347 function = "qup1_se7"; 3348 drive-strength = <2>; 3349 bias-disable; 3350 }; 3351 3352 sdc2_sleep: sdc2-sleep-state { 3353 clk-pins { 3354 pins = "sdc2_clk"; 3355 bias-disable; 3356 drive-strength = <2>; 3357 }; 3358 3359 cmd-pins { 3360 pins = "sdc2_cmd"; 3361 bias-pull-up; 3362 drive-strength = <2>; 3363 }; 3364 3365 data-pins { 3366 pins = "sdc2_data"; 3367 bias-pull-up; 3368 drive-strength = <2>; 3369 }; 3370 }; 3371 3372 sdc2_default: sdc2-default-state { 3373 clk-pins { 3374 pins = "sdc2_clk"; 3375 bias-disable; 3376 drive-strength = <16>; 3377 }; 3378 3379 cmd-pins { 3380 pins = "sdc2_cmd"; 3381 bias-pull-up; 3382 drive-strength = <10>; 3383 }; 3384 3385 data-pins { 3386 pins = "sdc2_data"; 3387 bias-pull-up; 3388 drive-strength = <10>; 3389 }; 3390 }; 3391 }; 3392 3393 apps_smmu: iommu@15000000 { 3394 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3395 reg = <0 0x15000000 0 0x100000>; 3396 #iommu-cells = <2>; 3397 #global-interrupts = <1>; 3398 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3495 }; 3496 3497 intc: interrupt-controller@17100000 { 3498 compatible = "arm,gic-v3"; 3499 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3500 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3501 ranges; 3502 #interrupt-cells = <3>; 3503 interrupt-controller; 3504 #redistributor-regions = <1>; 3505 redistributor-stride = <0 0x40000>; 3506 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3507 #address-cells = <2>; 3508 #size-cells = <2>; 3509 3510 gic_its: msi-controller@17140000 { 3511 compatible = "arm,gic-v3-its"; 3512 reg = <0 0x17140000 0 0x20000>; 3513 msi-controller; 3514 #msi-cells = <1>; 3515 }; 3516 }; 3517 3518 timer@17420000 { 3519 compatible = "arm,armv7-timer-mem"; 3520 reg = <0 0x17420000 0 0x1000>; 3521 ranges = <0 0 0 0x20000000>; 3522 #address-cells = <1>; 3523 #size-cells = <1>; 3524 3525 frame@17421000 { 3526 reg = <0x17421000 0x1000>, 3527 <0x17422000 0x1000>; 3528 frame-number = <0>; 3529 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3531 }; 3532 3533 frame@17423000 { 3534 reg = <0x17423000 0x1000>; 3535 frame-number = <1>; 3536 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3537 status = "disabled"; 3538 }; 3539 3540 frame@17425000 { 3541 reg = <0x17425000 0x1000>; 3542 frame-number = <2>; 3543 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3544 status = "disabled"; 3545 }; 3546 3547 frame@17427000 { 3548 reg = <0x17427000 0x1000>; 3549 frame-number = <3>; 3550 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3551 status = "disabled"; 3552 }; 3553 3554 frame@17429000 { 3555 reg = <0x17429000 0x1000>; 3556 frame-number = <4>; 3557 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3558 status = "disabled"; 3559 }; 3560 3561 frame@1742b000 { 3562 reg = <0x1742b000 0x1000>; 3563 frame-number = <5>; 3564 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3565 status = "disabled"; 3566 }; 3567 3568 frame@1742d000 { 3569 reg = <0x1742d000 0x1000>; 3570 frame-number = <6>; 3571 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3572 status = "disabled"; 3573 }; 3574 }; 3575 3576 apps_rsc: rsc@17a00000 { 3577 label = "apps_rsc"; 3578 compatible = "qcom,rpmh-rsc"; 3579 reg = <0 0x17a00000 0 0x10000>, 3580 <0 0x17a10000 0 0x10000>, 3581 <0 0x17a20000 0 0x10000>, 3582 <0 0x17a30000 0 0x10000>; 3583 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3584 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3587 qcom,tcs-offset = <0xd00>; 3588 qcom,drv-id = <2>; 3589 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3590 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3591 3592 apps_bcm_voter: bcm-voter { 3593 compatible = "qcom,bcm-voter"; 3594 }; 3595 3596 rpmhcc: clock-controller { 3597 compatible = "qcom,sm8550-rpmh-clk"; 3598 #clock-cells = <1>; 3599 clock-names = "xo"; 3600 clocks = <&xo_board>; 3601 }; 3602 3603 rpmhpd: power-controller { 3604 compatible = "qcom,sm8550-rpmhpd"; 3605 #power-domain-cells = <1>; 3606 operating-points-v2 = <&rpmhpd_opp_table>; 3607 3608 rpmhpd_opp_table: opp-table { 3609 compatible = "operating-points-v2"; 3610 3611 rpmhpd_opp_ret: opp1 { 3612 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3613 }; 3614 3615 rpmhpd_opp_min_svs: opp2 { 3616 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3617 }; 3618 3619 rpmhpd_opp_low_svs: opp3 { 3620 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3621 }; 3622 3623 rpmhpd_opp_svs: opp4 { 3624 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3625 }; 3626 3627 rpmhpd_opp_svs_l1: opp5 { 3628 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3629 }; 3630 3631 rpmhpd_opp_nom: opp6 { 3632 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3633 }; 3634 3635 rpmhpd_opp_nom_l1: opp7 { 3636 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3637 }; 3638 3639 rpmhpd_opp_nom_l2: opp8 { 3640 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3641 }; 3642 3643 rpmhpd_opp_turbo: opp9 { 3644 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3645 }; 3646 3647 rpmhpd_opp_turbo_l1: opp10 { 3648 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3649 }; 3650 }; 3651 }; 3652 }; 3653 3654 cpufreq_hw: cpufreq@17d91000 { 3655 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3656 reg = <0 0x17d91000 0 0x1000>, 3657 <0 0x17d92000 0 0x1000>, 3658 <0 0x17d93000 0 0x1000>; 3659 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3660 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3661 clock-names = "xo", "alternate"; 3662 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3665 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3666 #freq-domain-cells = <1>; 3667 #clock-cells = <1>; 3668 }; 3669 3670 pmu@24091000 { 3671 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3672 reg = <0 0x24091000 0 0x1000>; 3673 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3674 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3675 3676 operating-points-v2 = <&llcc_bwmon_opp_table>; 3677 3678 llcc_bwmon_opp_table: opp-table { 3679 compatible = "operating-points-v2"; 3680 3681 opp-0 { 3682 opp-peak-kBps = <2086000>; 3683 }; 3684 3685 opp-1 { 3686 opp-peak-kBps = <2929000>; 3687 }; 3688 3689 opp-2 { 3690 opp-peak-kBps = <5931000>; 3691 }; 3692 3693 opp-3 { 3694 opp-peak-kBps = <6515000>; 3695 }; 3696 3697 opp-4 { 3698 opp-peak-kBps = <7980000>; 3699 }; 3700 3701 opp-5 { 3702 opp-peak-kBps = <10437000>; 3703 }; 3704 3705 opp-6 { 3706 opp-peak-kBps = <12157000>; 3707 }; 3708 3709 opp-7 { 3710 opp-peak-kBps = <14060000>; 3711 }; 3712 3713 opp-8 { 3714 opp-peak-kBps = <16113000>; 3715 }; 3716 }; 3717 }; 3718 3719 pmu@240b6400 { 3720 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 3721 reg = <0 0x240b6400 0 0x600>; 3722 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3723 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3724 3725 operating-points-v2 = <&cpu_bwmon_opp_table>; 3726 3727 cpu_bwmon_opp_table: opp-table { 3728 compatible = "operating-points-v2"; 3729 3730 opp-0 { 3731 opp-peak-kBps = <4577000>; 3732 }; 3733 3734 opp-1 { 3735 opp-peak-kBps = <7110000>; 3736 }; 3737 3738 opp-2 { 3739 opp-peak-kBps = <9155000>; 3740 }; 3741 3742 opp-3 { 3743 opp-peak-kBps = <12298000>; 3744 }; 3745 3746 opp-4 { 3747 opp-peak-kBps = <14236000>; 3748 }; 3749 3750 opp-5 { 3751 opp-peak-kBps = <16265000>; 3752 }; 3753 }; 3754 }; 3755 3756 gem_noc: interconnect@24100000 { 3757 compatible = "qcom,sm8550-gem-noc"; 3758 reg = <0 0x24100000 0 0xbb800>; 3759 #interconnect-cells = <2>; 3760 qcom,bcm-voters = <&apps_bcm_voter>; 3761 }; 3762 3763 system-cache-controller@25000000 { 3764 compatible = "qcom,sm8550-llcc"; 3765 reg = <0 0x25000000 0 0x800000>, 3766 <0 0x25800000 0 0x200000>; 3767 reg-names = "llcc_base", "llcc_broadcast_base"; 3768 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3769 }; 3770 3771 remoteproc_adsp: remoteproc@30000000 { 3772 compatible = "qcom,sm8550-adsp-pas"; 3773 reg = <0x0 0x30000000 0x0 0x100>; 3774 3775 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3776 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3777 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3778 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3779 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3780 interrupt-names = "wdog", "fatal", "ready", 3781 "handover", "stop-ack"; 3782 3783 clocks = <&rpmhcc RPMH_CXO_CLK>; 3784 clock-names = "xo"; 3785 3786 power-domains = <&rpmhpd SM8550_LCX>, 3787 <&rpmhpd SM8550_LMX>; 3788 power-domain-names = "lcx", "lmx"; 3789 3790 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3791 3792 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3793 3794 qcom,qmp = <&aoss_qmp>; 3795 3796 qcom,smem-states = <&smp2p_adsp_out 0>; 3797 qcom,smem-state-names = "stop"; 3798 3799 status = "disabled"; 3800 3801 remoteproc_adsp_glink: glink-edge { 3802 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3803 IPCC_MPROC_SIGNAL_GLINK_QMP 3804 IRQ_TYPE_EDGE_RISING>; 3805 mboxes = <&ipcc IPCC_CLIENT_LPASS 3806 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3807 3808 label = "lpass"; 3809 qcom,remote-pid = <2>; 3810 3811 fastrpc { 3812 compatible = "qcom,fastrpc"; 3813 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3814 label = "adsp"; 3815 #address-cells = <1>; 3816 #size-cells = <0>; 3817 3818 compute-cb@3 { 3819 compatible = "qcom,fastrpc-compute-cb"; 3820 reg = <3>; 3821 iommus = <&apps_smmu 0x1003 0x80>, 3822 <&apps_smmu 0x1063 0x0>; 3823 }; 3824 3825 compute-cb@4 { 3826 compatible = "qcom,fastrpc-compute-cb"; 3827 reg = <4>; 3828 iommus = <&apps_smmu 0x1004 0x80>, 3829 <&apps_smmu 0x1064 0x0>; 3830 }; 3831 3832 compute-cb@5 { 3833 compatible = "qcom,fastrpc-compute-cb"; 3834 reg = <5>; 3835 iommus = <&apps_smmu 0x1005 0x80>, 3836 <&apps_smmu 0x1065 0x0>; 3837 }; 3838 3839 compute-cb@6 { 3840 compatible = "qcom,fastrpc-compute-cb"; 3841 reg = <6>; 3842 iommus = <&apps_smmu 0x1006 0x80>, 3843 <&apps_smmu 0x1066 0x0>; 3844 }; 3845 3846 compute-cb@7 { 3847 compatible = "qcom,fastrpc-compute-cb"; 3848 reg = <7>; 3849 iommus = <&apps_smmu 0x1007 0x80>, 3850 <&apps_smmu 0x1067 0x0>; 3851 }; 3852 }; 3853 3854 gpr { 3855 compatible = "qcom,gpr"; 3856 qcom,glink-channels = "adsp_apps"; 3857 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3858 qcom,intents = <512 20>; 3859 #address-cells = <1>; 3860 #size-cells = <0>; 3861 3862 q6apm: service@1 { 3863 compatible = "qcom,q6apm"; 3864 reg = <GPR_APM_MODULE_IID>; 3865 #sound-dai-cells = <0>; 3866 qcom,protection-domain = "avs/audio", 3867 "msm/adsp/audio_pd"; 3868 3869 q6apmdai: dais { 3870 compatible = "qcom,q6apm-dais"; 3871 iommus = <&apps_smmu 0x1001 0x80>, 3872 <&apps_smmu 0x1061 0x0>; 3873 }; 3874 3875 q6apmbedai: bedais { 3876 compatible = "qcom,q6apm-lpass-dais"; 3877 #sound-dai-cells = <1>; 3878 }; 3879 }; 3880 3881 q6prm: service@2 { 3882 compatible = "qcom,q6prm"; 3883 reg = <GPR_PRM_MODULE_IID>; 3884 qcom,protection-domain = "avs/audio", 3885 "msm/adsp/audio_pd"; 3886 3887 q6prmcc: clock-controller { 3888 compatible = "qcom,q6prm-lpass-clocks"; 3889 #clock-cells = <2>; 3890 }; 3891 }; 3892 }; 3893 }; 3894 }; 3895 3896 nsp_noc: interconnect@320c0000 { 3897 compatible = "qcom,sm8550-nsp-noc"; 3898 reg = <0 0x320c0000 0 0xe080>; 3899 #interconnect-cells = <2>; 3900 qcom,bcm-voters = <&apps_bcm_voter>; 3901 }; 3902 3903 remoteproc_cdsp: remoteproc@32300000 { 3904 compatible = "qcom,sm8550-cdsp-pas"; 3905 reg = <0x0 0x32300000 0x0 0x1400000>; 3906 3907 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3908 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3909 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3910 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3911 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3912 interrupt-names = "wdog", "fatal", "ready", 3913 "handover", "stop-ack"; 3914 3915 clocks = <&rpmhcc RPMH_CXO_CLK>; 3916 clock-names = "xo"; 3917 3918 power-domains = <&rpmhpd SM8550_CX>, 3919 <&rpmhpd SM8550_MXC>, 3920 <&rpmhpd SM8550_NSP>; 3921 power-domain-names = "cx", "mxc", "nsp"; 3922 3923 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3924 3925 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 3926 3927 qcom,qmp = <&aoss_qmp>; 3928 3929 qcom,smem-states = <&smp2p_cdsp_out 0>; 3930 qcom,smem-state-names = "stop"; 3931 3932 status = "disabled"; 3933 3934 glink-edge { 3935 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3936 IPCC_MPROC_SIGNAL_GLINK_QMP 3937 IRQ_TYPE_EDGE_RISING>; 3938 mboxes = <&ipcc IPCC_CLIENT_CDSP 3939 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3940 3941 label = "cdsp"; 3942 qcom,remote-pid = <5>; 3943 3944 fastrpc { 3945 compatible = "qcom,fastrpc"; 3946 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3947 label = "cdsp"; 3948 #address-cells = <1>; 3949 #size-cells = <0>; 3950 3951 compute-cb@1 { 3952 compatible = "qcom,fastrpc-compute-cb"; 3953 reg = <1>; 3954 iommus = <&apps_smmu 0x1961 0x0>, 3955 <&apps_smmu 0x0c01 0x20>, 3956 <&apps_smmu 0x19c1 0x10>; 3957 }; 3958 3959 compute-cb@2 { 3960 compatible = "qcom,fastrpc-compute-cb"; 3961 reg = <2>; 3962 iommus = <&apps_smmu 0x1962 0x0>, 3963 <&apps_smmu 0x0c02 0x20>, 3964 <&apps_smmu 0x19c2 0x10>; 3965 }; 3966 3967 compute-cb@3 { 3968 compatible = "qcom,fastrpc-compute-cb"; 3969 reg = <3>; 3970 iommus = <&apps_smmu 0x1963 0x0>, 3971 <&apps_smmu 0x0c03 0x20>, 3972 <&apps_smmu 0x19c3 0x10>; 3973 }; 3974 3975 compute-cb@4 { 3976 compatible = "qcom,fastrpc-compute-cb"; 3977 reg = <4>; 3978 iommus = <&apps_smmu 0x1964 0x0>, 3979 <&apps_smmu 0x0c04 0x20>, 3980 <&apps_smmu 0x19c4 0x10>; 3981 }; 3982 3983 compute-cb@5 { 3984 compatible = "qcom,fastrpc-compute-cb"; 3985 reg = <5>; 3986 iommus = <&apps_smmu 0x1965 0x0>, 3987 <&apps_smmu 0x0c05 0x20>, 3988 <&apps_smmu 0x19c5 0x10>; 3989 }; 3990 3991 compute-cb@6 { 3992 compatible = "qcom,fastrpc-compute-cb"; 3993 reg = <6>; 3994 iommus = <&apps_smmu 0x1966 0x0>, 3995 <&apps_smmu 0x0c06 0x20>, 3996 <&apps_smmu 0x19c6 0x10>; 3997 }; 3998 3999 compute-cb@7 { 4000 compatible = "qcom,fastrpc-compute-cb"; 4001 reg = <7>; 4002 iommus = <&apps_smmu 0x1967 0x0>, 4003 <&apps_smmu 0x0c07 0x20>, 4004 <&apps_smmu 0x19c7 0x10>; 4005 }; 4006 4007 compute-cb@8 { 4008 compatible = "qcom,fastrpc-compute-cb"; 4009 reg = <8>; 4010 iommus = <&apps_smmu 0x1968 0x0>, 4011 <&apps_smmu 0x0c08 0x20>, 4012 <&apps_smmu 0x19c8 0x10>; 4013 }; 4014 4015 /* note: secure cb9 in downstream */ 4016 }; 4017 }; 4018 }; 4019 }; 4020 4021 thermal-zones { 4022 aoss0-thermal { 4023 polling-delay-passive = <0>; 4024 polling-delay = <0>; 4025 thermal-sensors = <&tsens0 0>; 4026 4027 trips { 4028 thermal-engine-config { 4029 temperature = <125000>; 4030 hysteresis = <1000>; 4031 type = "passive"; 4032 }; 4033 4034 reset-mon-config { 4035 temperature = <115000>; 4036 hysteresis = <5000>; 4037 type = "passive"; 4038 }; 4039 }; 4040 }; 4041 4042 cpuss0-thermal { 4043 polling-delay-passive = <0>; 4044 polling-delay = <0>; 4045 thermal-sensors = <&tsens0 1>; 4046 4047 trips { 4048 thermal-engine-config { 4049 temperature = <125000>; 4050 hysteresis = <1000>; 4051 type = "passive"; 4052 }; 4053 4054 reset-mon-config { 4055 temperature = <115000>; 4056 hysteresis = <5000>; 4057 type = "passive"; 4058 }; 4059 }; 4060 }; 4061 4062 cpuss1-thermal { 4063 polling-delay-passive = <0>; 4064 polling-delay = <0>; 4065 thermal-sensors = <&tsens0 2>; 4066 4067 trips { 4068 thermal-engine-config { 4069 temperature = <125000>; 4070 hysteresis = <1000>; 4071 type = "passive"; 4072 }; 4073 4074 reset-mon-config { 4075 temperature = <115000>; 4076 hysteresis = <5000>; 4077 type = "passive"; 4078 }; 4079 }; 4080 }; 4081 4082 cpuss2-thermal { 4083 polling-delay-passive = <0>; 4084 polling-delay = <0>; 4085 thermal-sensors = <&tsens0 3>; 4086 4087 trips { 4088 thermal-engine-config { 4089 temperature = <125000>; 4090 hysteresis = <1000>; 4091 type = "passive"; 4092 }; 4093 4094 reset-mon-config { 4095 temperature = <115000>; 4096 hysteresis = <5000>; 4097 type = "passive"; 4098 }; 4099 }; 4100 }; 4101 4102 cpuss3-thermal { 4103 polling-delay-passive = <0>; 4104 polling-delay = <0>; 4105 thermal-sensors = <&tsens0 4>; 4106 4107 trips { 4108 thermal-engine-config { 4109 temperature = <125000>; 4110 hysteresis = <1000>; 4111 type = "passive"; 4112 }; 4113 4114 reset-mon-config { 4115 temperature = <115000>; 4116 hysteresis = <5000>; 4117 type = "passive"; 4118 }; 4119 }; 4120 }; 4121 4122 cpu3-top-thermal { 4123 polling-delay-passive = <0>; 4124 polling-delay = <0>; 4125 thermal-sensors = <&tsens0 5>; 4126 4127 trips { 4128 cpu3_top_alert0: trip-point0 { 4129 temperature = <90000>; 4130 hysteresis = <2000>; 4131 type = "passive"; 4132 }; 4133 4134 cpu3_top_alert1: trip-point1 { 4135 temperature = <95000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu3_top_crit: cpu-critical { 4141 temperature = <110000>; 4142 hysteresis = <1000>; 4143 type = "critical"; 4144 }; 4145 }; 4146 }; 4147 4148 cpu3-bottom-thermal { 4149 polling-delay-passive = <0>; 4150 polling-delay = <0>; 4151 thermal-sensors = <&tsens0 6>; 4152 4153 trips { 4154 cpu3_bottom_alert0: trip-point0 { 4155 temperature = <90000>; 4156 hysteresis = <2000>; 4157 type = "passive"; 4158 }; 4159 4160 cpu3_bottom_alert1: trip-point1 { 4161 temperature = <95000>; 4162 hysteresis = <2000>; 4163 type = "passive"; 4164 }; 4165 4166 cpu3_bottom_crit: cpu-critical { 4167 temperature = <110000>; 4168 hysteresis = <1000>; 4169 type = "critical"; 4170 }; 4171 }; 4172 }; 4173 4174 cpu4-top-thermal { 4175 polling-delay-passive = <0>; 4176 polling-delay = <0>; 4177 thermal-sensors = <&tsens0 7>; 4178 4179 trips { 4180 cpu4_top_alert0: trip-point0 { 4181 temperature = <90000>; 4182 hysteresis = <2000>; 4183 type = "passive"; 4184 }; 4185 4186 cpu4_top_alert1: trip-point1 { 4187 temperature = <95000>; 4188 hysteresis = <2000>; 4189 type = "passive"; 4190 }; 4191 4192 cpu4_top_crit: cpu-critical { 4193 temperature = <110000>; 4194 hysteresis = <1000>; 4195 type = "critical"; 4196 }; 4197 }; 4198 }; 4199 4200 cpu4-bottom-thermal { 4201 polling-delay-passive = <0>; 4202 polling-delay = <0>; 4203 thermal-sensors = <&tsens0 8>; 4204 4205 trips { 4206 cpu4_bottom_alert0: trip-point0 { 4207 temperature = <90000>; 4208 hysteresis = <2000>; 4209 type = "passive"; 4210 }; 4211 4212 cpu4_bottom_alert1: trip-point1 { 4213 temperature = <95000>; 4214 hysteresis = <2000>; 4215 type = "passive"; 4216 }; 4217 4218 cpu4_bottom_crit: cpu-critical { 4219 temperature = <110000>; 4220 hysteresis = <1000>; 4221 type = "critical"; 4222 }; 4223 }; 4224 }; 4225 4226 cpu5-top-thermal { 4227 polling-delay-passive = <0>; 4228 polling-delay = <0>; 4229 thermal-sensors = <&tsens0 9>; 4230 4231 trips { 4232 cpu5_top_alert0: trip-point0 { 4233 temperature = <90000>; 4234 hysteresis = <2000>; 4235 type = "passive"; 4236 }; 4237 4238 cpu5_top_alert1: trip-point1 { 4239 temperature = <95000>; 4240 hysteresis = <2000>; 4241 type = "passive"; 4242 }; 4243 4244 cpu5_top_crit: cpu-critical { 4245 temperature = <110000>; 4246 hysteresis = <1000>; 4247 type = "critical"; 4248 }; 4249 }; 4250 }; 4251 4252 cpu5-bottom-thermal { 4253 polling-delay-passive = <0>; 4254 polling-delay = <0>; 4255 thermal-sensors = <&tsens0 10>; 4256 4257 trips { 4258 cpu5_bottom_alert0: trip-point0 { 4259 temperature = <90000>; 4260 hysteresis = <2000>; 4261 type = "passive"; 4262 }; 4263 4264 cpu5_bottom_alert1: trip-point1 { 4265 temperature = <95000>; 4266 hysteresis = <2000>; 4267 type = "passive"; 4268 }; 4269 4270 cpu5_bottom_crit: cpu-critical { 4271 temperature = <110000>; 4272 hysteresis = <1000>; 4273 type = "critical"; 4274 }; 4275 }; 4276 }; 4277 4278 cpu6-top-thermal { 4279 polling-delay-passive = <0>; 4280 polling-delay = <0>; 4281 thermal-sensors = <&tsens0 11>; 4282 4283 trips { 4284 cpu6_top_alert0: trip-point0 { 4285 temperature = <90000>; 4286 hysteresis = <2000>; 4287 type = "passive"; 4288 }; 4289 4290 cpu6_top_alert1: trip-point1 { 4291 temperature = <95000>; 4292 hysteresis = <2000>; 4293 type = "passive"; 4294 }; 4295 4296 cpu6_top_crit: cpu-critical { 4297 temperature = <110000>; 4298 hysteresis = <1000>; 4299 type = "critical"; 4300 }; 4301 }; 4302 }; 4303 4304 cpu6-bottom-thermal { 4305 polling-delay-passive = <0>; 4306 polling-delay = <0>; 4307 thermal-sensors = <&tsens0 12>; 4308 4309 trips { 4310 cpu6_bottom_alert0: trip-point0 { 4311 temperature = <90000>; 4312 hysteresis = <2000>; 4313 type = "passive"; 4314 }; 4315 4316 cpu6_bottom_alert1: trip-point1 { 4317 temperature = <95000>; 4318 hysteresis = <2000>; 4319 type = "passive"; 4320 }; 4321 4322 cpu6_bottom_crit: cpu-critical { 4323 temperature = <110000>; 4324 hysteresis = <1000>; 4325 type = "critical"; 4326 }; 4327 }; 4328 }; 4329 4330 cpu7-top-thermal { 4331 polling-delay-passive = <0>; 4332 polling-delay = <0>; 4333 thermal-sensors = <&tsens0 13>; 4334 4335 trips { 4336 cpu7_top_alert0: trip-point0 { 4337 temperature = <90000>; 4338 hysteresis = <2000>; 4339 type = "passive"; 4340 }; 4341 4342 cpu7_top_alert1: trip-point1 { 4343 temperature = <95000>; 4344 hysteresis = <2000>; 4345 type = "passive"; 4346 }; 4347 4348 cpu7_top_crit: cpu-critical { 4349 temperature = <110000>; 4350 hysteresis = <1000>; 4351 type = "critical"; 4352 }; 4353 }; 4354 }; 4355 4356 cpu7-middle-thermal { 4357 polling-delay-passive = <0>; 4358 polling-delay = <0>; 4359 thermal-sensors = <&tsens0 14>; 4360 4361 trips { 4362 cpu7_middle_alert0: trip-point0 { 4363 temperature = <90000>; 4364 hysteresis = <2000>; 4365 type = "passive"; 4366 }; 4367 4368 cpu7_middle_alert1: trip-point1 { 4369 temperature = <95000>; 4370 hysteresis = <2000>; 4371 type = "passive"; 4372 }; 4373 4374 cpu7_middle_crit: cpu-critical { 4375 temperature = <110000>; 4376 hysteresis = <1000>; 4377 type = "critical"; 4378 }; 4379 }; 4380 }; 4381 4382 cpu7-bottom-thermal { 4383 polling-delay-passive = <0>; 4384 polling-delay = <0>; 4385 thermal-sensors = <&tsens0 15>; 4386 4387 trips { 4388 cpu7_bottom_alert0: trip-point0 { 4389 temperature = <90000>; 4390 hysteresis = <2000>; 4391 type = "passive"; 4392 }; 4393 4394 cpu7_bottom_alert1: trip-point1 { 4395 temperature = <95000>; 4396 hysteresis = <2000>; 4397 type = "passive"; 4398 }; 4399 4400 cpu7_bottom_crit: cpu-critical { 4401 temperature = <110000>; 4402 hysteresis = <1000>; 4403 type = "critical"; 4404 }; 4405 }; 4406 }; 4407 4408 aoss1-thermal { 4409 polling-delay-passive = <0>; 4410 polling-delay = <0>; 4411 thermal-sensors = <&tsens1 0>; 4412 4413 trips { 4414 thermal-engine-config { 4415 temperature = <125000>; 4416 hysteresis = <1000>; 4417 type = "passive"; 4418 }; 4419 4420 reset-mon-config { 4421 temperature = <115000>; 4422 hysteresis = <5000>; 4423 type = "passive"; 4424 }; 4425 }; 4426 }; 4427 4428 cpu0-thermal { 4429 polling-delay-passive = <0>; 4430 polling-delay = <0>; 4431 thermal-sensors = <&tsens1 1>; 4432 4433 trips { 4434 cpu0_alert0: trip-point0 { 4435 temperature = <90000>; 4436 hysteresis = <2000>; 4437 type = "passive"; 4438 }; 4439 4440 cpu0_alert1: trip-point1 { 4441 temperature = <95000>; 4442 hysteresis = <2000>; 4443 type = "passive"; 4444 }; 4445 4446 cpu0_crit: cpu-critical { 4447 temperature = <110000>; 4448 hysteresis = <1000>; 4449 type = "critical"; 4450 }; 4451 }; 4452 }; 4453 4454 cpu1-thermal { 4455 polling-delay-passive = <0>; 4456 polling-delay = <0>; 4457 thermal-sensors = <&tsens1 2>; 4458 4459 trips { 4460 cpu1_alert0: trip-point0 { 4461 temperature = <90000>; 4462 hysteresis = <2000>; 4463 type = "passive"; 4464 }; 4465 4466 cpu1_alert1: trip-point1 { 4467 temperature = <95000>; 4468 hysteresis = <2000>; 4469 type = "passive"; 4470 }; 4471 4472 cpu1_crit: cpu-critical { 4473 temperature = <110000>; 4474 hysteresis = <1000>; 4475 type = "critical"; 4476 }; 4477 }; 4478 }; 4479 4480 cpu2-thermal { 4481 polling-delay-passive = <0>; 4482 polling-delay = <0>; 4483 thermal-sensors = <&tsens1 3>; 4484 4485 trips { 4486 cpu2_alert0: trip-point0 { 4487 temperature = <90000>; 4488 hysteresis = <2000>; 4489 type = "passive"; 4490 }; 4491 4492 cpu2_alert1: trip-point1 { 4493 temperature = <95000>; 4494 hysteresis = <2000>; 4495 type = "passive"; 4496 }; 4497 4498 cpu2_crit: cpu-critical { 4499 temperature = <110000>; 4500 hysteresis = <1000>; 4501 type = "critical"; 4502 }; 4503 }; 4504 }; 4505 4506 cdsp0-thermal { 4507 polling-delay-passive = <10>; 4508 polling-delay = <0>; 4509 thermal-sensors = <&tsens2 4>; 4510 4511 trips { 4512 thermal-engine-config { 4513 temperature = <125000>; 4514 hysteresis = <1000>; 4515 type = "passive"; 4516 }; 4517 4518 thermal-hal-config { 4519 temperature = <125000>; 4520 hysteresis = <1000>; 4521 type = "passive"; 4522 }; 4523 4524 reset-mon-config { 4525 temperature = <115000>; 4526 hysteresis = <5000>; 4527 type = "passive"; 4528 }; 4529 4530 cdsp0_junction_config: junction-config { 4531 temperature = <95000>; 4532 hysteresis = <5000>; 4533 type = "passive"; 4534 }; 4535 }; 4536 }; 4537 4538 cdsp1-thermal { 4539 polling-delay-passive = <10>; 4540 polling-delay = <0>; 4541 thermal-sensors = <&tsens2 5>; 4542 4543 trips { 4544 thermal-engine-config { 4545 temperature = <125000>; 4546 hysteresis = <1000>; 4547 type = "passive"; 4548 }; 4549 4550 thermal-hal-config { 4551 temperature = <125000>; 4552 hysteresis = <1000>; 4553 type = "passive"; 4554 }; 4555 4556 reset-mon-config { 4557 temperature = <115000>; 4558 hysteresis = <5000>; 4559 type = "passive"; 4560 }; 4561 4562 cdsp1_junction_config: junction-config { 4563 temperature = <95000>; 4564 hysteresis = <5000>; 4565 type = "passive"; 4566 }; 4567 }; 4568 }; 4569 4570 cdsp2-thermal { 4571 polling-delay-passive = <10>; 4572 polling-delay = <0>; 4573 thermal-sensors = <&tsens2 6>; 4574 4575 trips { 4576 thermal-engine-config { 4577 temperature = <125000>; 4578 hysteresis = <1000>; 4579 type = "passive"; 4580 }; 4581 4582 thermal-hal-config { 4583 temperature = <125000>; 4584 hysteresis = <1000>; 4585 type = "passive"; 4586 }; 4587 4588 reset-mon-config { 4589 temperature = <115000>; 4590 hysteresis = <5000>; 4591 type = "passive"; 4592 }; 4593 4594 cdsp2_junction_config: junction-config { 4595 temperature = <95000>; 4596 hysteresis = <5000>; 4597 type = "passive"; 4598 }; 4599 }; 4600 }; 4601 4602 cdsp3-thermal { 4603 polling-delay-passive = <10>; 4604 polling-delay = <0>; 4605 thermal-sensors = <&tsens2 7>; 4606 4607 trips { 4608 thermal-engine-config { 4609 temperature = <125000>; 4610 hysteresis = <1000>; 4611 type = "passive"; 4612 }; 4613 4614 thermal-hal-config { 4615 temperature = <125000>; 4616 hysteresis = <1000>; 4617 type = "passive"; 4618 }; 4619 4620 reset-mon-config { 4621 temperature = <115000>; 4622 hysteresis = <5000>; 4623 type = "passive"; 4624 }; 4625 4626 cdsp3_junction_config: junction-config { 4627 temperature = <95000>; 4628 hysteresis = <5000>; 4629 type = "passive"; 4630 }; 4631 }; 4632 }; 4633 4634 video-thermal { 4635 polling-delay-passive = <0>; 4636 polling-delay = <0>; 4637 thermal-sensors = <&tsens1 8>; 4638 4639 trips { 4640 thermal-engine-config { 4641 temperature = <125000>; 4642 hysteresis = <1000>; 4643 type = "passive"; 4644 }; 4645 4646 reset-mon-config { 4647 temperature = <115000>; 4648 hysteresis = <5000>; 4649 type = "passive"; 4650 }; 4651 }; 4652 }; 4653 4654 mem-thermal { 4655 polling-delay-passive = <10>; 4656 polling-delay = <0>; 4657 thermal-sensors = <&tsens1 9>; 4658 4659 trips { 4660 thermal-engine-config { 4661 temperature = <125000>; 4662 hysteresis = <1000>; 4663 type = "passive"; 4664 }; 4665 4666 ddr_config0: ddr0-config { 4667 temperature = <90000>; 4668 hysteresis = <5000>; 4669 type = "passive"; 4670 }; 4671 4672 reset-mon-config { 4673 temperature = <115000>; 4674 hysteresis = <5000>; 4675 type = "passive"; 4676 }; 4677 }; 4678 }; 4679 4680 modem0-thermal { 4681 polling-delay-passive = <0>; 4682 polling-delay = <0>; 4683 thermal-sensors = <&tsens1 10>; 4684 4685 trips { 4686 thermal-engine-config { 4687 temperature = <125000>; 4688 hysteresis = <1000>; 4689 type = "passive"; 4690 }; 4691 4692 mdmss0_config0: mdmss0-config0 { 4693 temperature = <102000>; 4694 hysteresis = <3000>; 4695 type = "passive"; 4696 }; 4697 4698 mdmss0_config1: mdmss0-config1 { 4699 temperature = <105000>; 4700 hysteresis = <3000>; 4701 type = "passive"; 4702 }; 4703 4704 reset-mon-config { 4705 temperature = <115000>; 4706 hysteresis = <5000>; 4707 type = "passive"; 4708 }; 4709 }; 4710 }; 4711 4712 modem1-thermal { 4713 polling-delay-passive = <0>; 4714 polling-delay = <0>; 4715 thermal-sensors = <&tsens1 11>; 4716 4717 trips { 4718 thermal-engine-config { 4719 temperature = <125000>; 4720 hysteresis = <1000>; 4721 type = "passive"; 4722 }; 4723 4724 mdmss1_config0: mdmss1-config0 { 4725 temperature = <102000>; 4726 hysteresis = <3000>; 4727 type = "passive"; 4728 }; 4729 4730 mdmss1_config1: mdmss1-config1 { 4731 temperature = <105000>; 4732 hysteresis = <3000>; 4733 type = "passive"; 4734 }; 4735 4736 reset-mon-config { 4737 temperature = <115000>; 4738 hysteresis = <5000>; 4739 type = "passive"; 4740 }; 4741 }; 4742 }; 4743 4744 modem2-thermal { 4745 polling-delay-passive = <0>; 4746 polling-delay = <0>; 4747 thermal-sensors = <&tsens1 12>; 4748 4749 trips { 4750 thermal-engine-config { 4751 temperature = <125000>; 4752 hysteresis = <1000>; 4753 type = "passive"; 4754 }; 4755 4756 mdmss2_config0: mdmss2-config0 { 4757 temperature = <102000>; 4758 hysteresis = <3000>; 4759 type = "passive"; 4760 }; 4761 4762 mdmss2_config1: mdmss2-config1 { 4763 temperature = <105000>; 4764 hysteresis = <3000>; 4765 type = "passive"; 4766 }; 4767 4768 reset-mon-config { 4769 temperature = <115000>; 4770 hysteresis = <5000>; 4771 type = "passive"; 4772 }; 4773 }; 4774 }; 4775 4776 modem3-thermal { 4777 polling-delay-passive = <0>; 4778 polling-delay = <0>; 4779 thermal-sensors = <&tsens1 13>; 4780 4781 trips { 4782 thermal-engine-config { 4783 temperature = <125000>; 4784 hysteresis = <1000>; 4785 type = "passive"; 4786 }; 4787 4788 mdmss3_config0: mdmss3-config0 { 4789 temperature = <102000>; 4790 hysteresis = <3000>; 4791 type = "passive"; 4792 }; 4793 4794 mdmss3_config1: mdmss3-config1 { 4795 temperature = <105000>; 4796 hysteresis = <3000>; 4797 type = "passive"; 4798 }; 4799 4800 reset-mon-config { 4801 temperature = <115000>; 4802 hysteresis = <5000>; 4803 type = "passive"; 4804 }; 4805 }; 4806 }; 4807 4808 camera0-thermal { 4809 polling-delay-passive = <0>; 4810 polling-delay = <0>; 4811 thermal-sensors = <&tsens1 14>; 4812 4813 trips { 4814 thermal-engine-config { 4815 temperature = <125000>; 4816 hysteresis = <1000>; 4817 type = "passive"; 4818 }; 4819 4820 reset-mon-config { 4821 temperature = <115000>; 4822 hysteresis = <5000>; 4823 type = "passive"; 4824 }; 4825 }; 4826 }; 4827 4828 camera1-thermal { 4829 polling-delay-passive = <0>; 4830 polling-delay = <0>; 4831 thermal-sensors = <&tsens1 15>; 4832 4833 trips { 4834 thermal-engine-config { 4835 temperature = <125000>; 4836 hysteresis = <1000>; 4837 type = "passive"; 4838 }; 4839 4840 reset-mon-config { 4841 temperature = <115000>; 4842 hysteresis = <5000>; 4843 type = "passive"; 4844 }; 4845 }; 4846 }; 4847 4848 aoss2-thermal { 4849 polling-delay-passive = <0>; 4850 polling-delay = <0>; 4851 thermal-sensors = <&tsens2 0>; 4852 4853 trips { 4854 thermal-engine-config { 4855 temperature = <125000>; 4856 hysteresis = <1000>; 4857 type = "passive"; 4858 }; 4859 4860 reset-mon-config { 4861 temperature = <115000>; 4862 hysteresis = <5000>; 4863 type = "passive"; 4864 }; 4865 }; 4866 }; 4867 4868 gpuss-0-thermal { 4869 polling-delay-passive = <10>; 4870 polling-delay = <0>; 4871 thermal-sensors = <&tsens2 1>; 4872 4873 trips { 4874 thermal-engine-config { 4875 temperature = <125000>; 4876 hysteresis = <1000>; 4877 type = "passive"; 4878 }; 4879 4880 thermal-hal-config { 4881 temperature = <125000>; 4882 hysteresis = <1000>; 4883 type = "passive"; 4884 }; 4885 4886 reset-mon-config { 4887 temperature = <115000>; 4888 hysteresis = <5000>; 4889 type = "passive"; 4890 }; 4891 4892 gpu0_junction_config: junction-config { 4893 temperature = <95000>; 4894 hysteresis = <5000>; 4895 type = "passive"; 4896 }; 4897 }; 4898 }; 4899 4900 gpuss-1-thermal { 4901 polling-delay-passive = <10>; 4902 polling-delay = <0>; 4903 thermal-sensors = <&tsens2 2>; 4904 4905 trips { 4906 thermal-engine-config { 4907 temperature = <125000>; 4908 hysteresis = <1000>; 4909 type = "passive"; 4910 }; 4911 4912 thermal-hal-config { 4913 temperature = <125000>; 4914 hysteresis = <1000>; 4915 type = "passive"; 4916 }; 4917 4918 reset-mon-config { 4919 temperature = <115000>; 4920 hysteresis = <5000>; 4921 type = "passive"; 4922 }; 4923 4924 gpu1_junction_config: junction-config { 4925 temperature = <95000>; 4926 hysteresis = <5000>; 4927 type = "passive"; 4928 }; 4929 }; 4930 }; 4931 4932 gpuss-2-thermal { 4933 polling-delay-passive = <10>; 4934 polling-delay = <0>; 4935 thermal-sensors = <&tsens2 3>; 4936 4937 trips { 4938 thermal-engine-config { 4939 temperature = <125000>; 4940 hysteresis = <1000>; 4941 type = "passive"; 4942 }; 4943 4944 thermal-hal-config { 4945 temperature = <125000>; 4946 hysteresis = <1000>; 4947 type = "passive"; 4948 }; 4949 4950 reset-mon-config { 4951 temperature = <115000>; 4952 hysteresis = <5000>; 4953 type = "passive"; 4954 }; 4955 4956 gpu2_junction_config: junction-config { 4957 temperature = <95000>; 4958 hysteresis = <5000>; 4959 type = "passive"; 4960 }; 4961 }; 4962 }; 4963 4964 gpuss-3-thermal { 4965 polling-delay-passive = <10>; 4966 polling-delay = <0>; 4967 thermal-sensors = <&tsens2 4>; 4968 4969 trips { 4970 thermal-engine-config { 4971 temperature = <125000>; 4972 hysteresis = <1000>; 4973 type = "passive"; 4974 }; 4975 4976 thermal-hal-config { 4977 temperature = <125000>; 4978 hysteresis = <1000>; 4979 type = "passive"; 4980 }; 4981 4982 reset-mon-config { 4983 temperature = <115000>; 4984 hysteresis = <5000>; 4985 type = "passive"; 4986 }; 4987 4988 gpu3_junction_config: junction-config { 4989 temperature = <95000>; 4990 hysteresis = <5000>; 4991 type = "passive"; 4992 }; 4993 }; 4994 }; 4995 4996 gpuss-4-thermal { 4997 polling-delay-passive = <10>; 4998 polling-delay = <0>; 4999 thermal-sensors = <&tsens2 5>; 5000 5001 trips { 5002 thermal-engine-config { 5003 temperature = <125000>; 5004 hysteresis = <1000>; 5005 type = "passive"; 5006 }; 5007 5008 thermal-hal-config { 5009 temperature = <125000>; 5010 hysteresis = <1000>; 5011 type = "passive"; 5012 }; 5013 5014 reset-mon-config { 5015 temperature = <115000>; 5016 hysteresis = <5000>; 5017 type = "passive"; 5018 }; 5019 5020 gpu4_junction_config: junction-config { 5021 temperature = <95000>; 5022 hysteresis = <5000>; 5023 type = "passive"; 5024 }; 5025 }; 5026 }; 5027 5028 gpuss-5-thermal { 5029 polling-delay-passive = <10>; 5030 polling-delay = <0>; 5031 thermal-sensors = <&tsens2 6>; 5032 5033 trips { 5034 thermal-engine-config { 5035 temperature = <125000>; 5036 hysteresis = <1000>; 5037 type = "passive"; 5038 }; 5039 5040 thermal-hal-config { 5041 temperature = <125000>; 5042 hysteresis = <1000>; 5043 type = "passive"; 5044 }; 5045 5046 reset-mon-config { 5047 temperature = <115000>; 5048 hysteresis = <5000>; 5049 type = "passive"; 5050 }; 5051 5052 gpu5_junction_config: junction-config { 5053 temperature = <95000>; 5054 hysteresis = <5000>; 5055 type = "passive"; 5056 }; 5057 }; 5058 }; 5059 5060 gpuss-6-thermal { 5061 polling-delay-passive = <10>; 5062 polling-delay = <0>; 5063 thermal-sensors = <&tsens2 7>; 5064 5065 trips { 5066 thermal-engine-config { 5067 temperature = <125000>; 5068 hysteresis = <1000>; 5069 type = "passive"; 5070 }; 5071 5072 thermal-hal-config { 5073 temperature = <125000>; 5074 hysteresis = <1000>; 5075 type = "passive"; 5076 }; 5077 5078 reset-mon-config { 5079 temperature = <115000>; 5080 hysteresis = <5000>; 5081 type = "passive"; 5082 }; 5083 5084 gpu6_junction_config: junction-config { 5085 temperature = <95000>; 5086 hysteresis = <5000>; 5087 type = "passive"; 5088 }; 5089 }; 5090 }; 5091 5092 gpuss-7-thermal { 5093 polling-delay-passive = <10>; 5094 polling-delay = <0>; 5095 thermal-sensors = <&tsens2 8>; 5096 5097 trips { 5098 thermal-engine-config { 5099 temperature = <125000>; 5100 hysteresis = <1000>; 5101 type = "passive"; 5102 }; 5103 5104 thermal-hal-config { 5105 temperature = <125000>; 5106 hysteresis = <1000>; 5107 type = "passive"; 5108 }; 5109 5110 reset-mon-config { 5111 temperature = <115000>; 5112 hysteresis = <5000>; 5113 type = "passive"; 5114 }; 5115 5116 gpu7_junction_config: junction-config { 5117 temperature = <95000>; 5118 hysteresis = <5000>; 5119 type = "passive"; 5120 }; 5121 }; 5122 }; 5123 }; 5124 5125 timer { 5126 compatible = "arm,armv8-timer"; 5127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5131 }; 5132}; 5133