1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/interconnect/qcom,sm8450.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <76800000>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32000>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo780"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 power-domains = <&CPU_PD0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 #cooling-cells = <2>; 57 clocks = <&cpufreq_hw 0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 next-level-cache = <&L3_0>; 61 L3_0: l3-cache { 62 compatible = "cache"; 63 }; 64 }; 65 }; 66 67 CPU1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo780"; 70 reg = <0x0 0x100>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_100>; 73 power-domains = <&CPU_PD1>; 74 power-domain-names = "psci"; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 #cooling-cells = <2>; 77 clocks = <&cpufreq_hw 0>; 78 L2_100: l2-cache { 79 compatible = "cache"; 80 next-level-cache = <&L3_0>; 81 }; 82 }; 83 84 CPU2: cpu@200 { 85 device_type = "cpu"; 86 compatible = "qcom,kryo780"; 87 reg = <0x0 0x200>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_200>; 90 power-domains = <&CPU_PD2>; 91 power-domain-names = "psci"; 92 qcom,freq-domain = <&cpufreq_hw 0>; 93 #cooling-cells = <2>; 94 clocks = <&cpufreq_hw 0>; 95 L2_200: l2-cache { 96 compatible = "cache"; 97 next-level-cache = <&L3_0>; 98 }; 99 }; 100 101 CPU3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo780"; 104 reg = <0x0 0x300>; 105 enable-method = "psci"; 106 next-level-cache = <&L2_300>; 107 power-domains = <&CPU_PD3>; 108 power-domain-names = "psci"; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 #cooling-cells = <2>; 111 clocks = <&cpufreq_hw 0>; 112 L2_300: l2-cache { 113 compatible = "cache"; 114 next-level-cache = <&L3_0>; 115 }; 116 }; 117 118 CPU4: cpu@400 { 119 device_type = "cpu"; 120 compatible = "qcom,kryo780"; 121 reg = <0x0 0x400>; 122 enable-method = "psci"; 123 next-level-cache = <&L2_400>; 124 power-domains = <&CPU_PD4>; 125 power-domain-names = "psci"; 126 qcom,freq-domain = <&cpufreq_hw 1>; 127 #cooling-cells = <2>; 128 clocks = <&cpufreq_hw 1>; 129 L2_400: l2-cache { 130 compatible = "cache"; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU5: cpu@500 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x500>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_500>; 141 power-domains = <&CPU_PD5>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 #cooling-cells = <2>; 145 clocks = <&cpufreq_hw 1>; 146 L2_500: l2-cache { 147 compatible = "cache"; 148 next-level-cache = <&L3_0>; 149 }; 150 151 }; 152 153 CPU6: cpu@600 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo780"; 156 reg = <0x0 0x600>; 157 enable-method = "psci"; 158 next-level-cache = <&L2_600>; 159 power-domains = <&CPU_PD6>; 160 power-domain-names = "psci"; 161 qcom,freq-domain = <&cpufreq_hw 1>; 162 #cooling-cells = <2>; 163 clocks = <&cpufreq_hw 1>; 164 L2_600: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU7: cpu@700 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo780"; 173 reg = <0x0 0x700>; 174 enable-method = "psci"; 175 next-level-cache = <&L2_700>; 176 power-domains = <&CPU_PD7>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 2>; 179 #cooling-cells = <2>; 180 clocks = <&cpufreq_hw 2>; 181 L2_700: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 }; 185 }; 186 187 cpu-map { 188 cluster0 { 189 core0 { 190 cpu = <&CPU0>; 191 }; 192 193 core1 { 194 cpu = <&CPU1>; 195 }; 196 197 core2 { 198 cpu = <&CPU2>; 199 }; 200 201 core3 { 202 cpu = <&CPU3>; 203 }; 204 205 core4 { 206 cpu = <&CPU4>; 207 }; 208 209 core5 { 210 cpu = <&CPU5>; 211 }; 212 213 core6 { 214 cpu = <&CPU6>; 215 }; 216 217 core7 { 218 cpu = <&CPU7>; 219 }; 220 }; 221 }; 222 223 idle-states { 224 entry-method = "psci"; 225 226 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 227 compatible = "arm,idle-state"; 228 idle-state-name = "silver-rail-power-collapse"; 229 arm,psci-suspend-param = <0x40000004>; 230 entry-latency-us = <800>; 231 exit-latency-us = <750>; 232 min-residency-us = <4090>; 233 local-timer-stop; 234 }; 235 236 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "gold-rail-power-collapse"; 239 arm,psci-suspend-param = <0x40000004>; 240 entry-latency-us = <600>; 241 exit-latency-us = <1550>; 242 min-residency-us = <4791>; 243 local-timer-stop; 244 }; 245 }; 246 247 domain-idle-states { 248 CLUSTER_SLEEP_0: cluster-sleep-0 { 249 compatible = "domain-idle-state"; 250 idle-state-name = "cluster-l3-off"; 251 arm,psci-suspend-param = <0x41000044>; 252 entry-latency-us = <1050>; 253 exit-latency-us = <2500>; 254 min-residency-us = <5309>; 255 local-timer-stop; 256 }; 257 258 CLUSTER_SLEEP_1: cluster-sleep-1 { 259 compatible = "domain-idle-state"; 260 idle-state-name = "cluster-power-collapse"; 261 arm,psci-suspend-param = <0x4100c344>; 262 entry-latency-us = <2700>; 263 exit-latency-us = <3500>; 264 min-residency-us = <13959>; 265 local-timer-stop; 266 }; 267 }; 268 }; 269 270 firmware { 271 scm: scm { 272 compatible = "qcom,scm-sm8450", "qcom,scm"; 273 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 274 #reset-cells = <1>; 275 }; 276 }; 277 278 clk_virt: interconnect-0 { 279 compatible = "qcom,sm8450-clk-virt"; 280 #interconnect-cells = <2>; 281 qcom,bcm-voters = <&apps_bcm_voter>; 282 }; 283 284 mc_virt: interconnect-1 { 285 compatible = "qcom,sm8450-mc-virt"; 286 #interconnect-cells = <2>; 287 qcom,bcm-voters = <&apps_bcm_voter>; 288 }; 289 290 memory@a0000000 { 291 device_type = "memory"; 292 /* We expect the bootloader to fill in the size */ 293 reg = <0x0 0xa0000000 0x0 0x0>; 294 }; 295 296 pmu { 297 compatible = "arm,armv8-pmuv3"; 298 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 299 }; 300 301 psci { 302 compatible = "arm,psci-1.0"; 303 method = "smc"; 304 305 CPU_PD0: cpu0 { 306 #power-domain-cells = <0>; 307 power-domains = <&CLUSTER_PD>; 308 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 309 }; 310 311 CPU_PD1: cpu1 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 315 }; 316 317 CPU_PD2: cpu2 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 321 }; 322 323 CPU_PD3: cpu3 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD4: cpu4 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&BIG_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD5: cpu5 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&BIG_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD6: cpu6 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&BIG_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD7: cpu7 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CLUSTER_PD: cpu-cluster0 { 354 #power-domain-cells = <0>; 355 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 356 }; 357 }; 358 359 qup_opp_table_100mhz: opp-table-qup { 360 compatible = "operating-points-v2"; 361 362 opp-50000000 { 363 opp-hz = /bits/ 64 <50000000>; 364 required-opps = <&rpmhpd_opp_min_svs>; 365 }; 366 367 opp-75000000 { 368 opp-hz = /bits/ 64 <75000000>; 369 required-opps = <&rpmhpd_opp_low_svs>; 370 }; 371 372 opp-100000000 { 373 opp-hz = /bits/ 64 <100000000>; 374 required-opps = <&rpmhpd_opp_svs>; 375 }; 376 }; 377 378 reserved_memory: reserved-memory { 379 #address-cells = <2>; 380 #size-cells = <2>; 381 ranges; 382 383 hyp_mem: memory@80000000 { 384 reg = <0x0 0x80000000 0x0 0x600000>; 385 no-map; 386 }; 387 388 xbl_dt_log_mem: memory@80600000 { 389 reg = <0x0 0x80600000 0x0 0x40000>; 390 no-map; 391 }; 392 393 xbl_ramdump_mem: memory@80640000 { 394 reg = <0x0 0x80640000 0x0 0x180000>; 395 no-map; 396 }; 397 398 xbl_sc_mem: memory@807c0000 { 399 reg = <0x0 0x807c0000 0x0 0x40000>; 400 no-map; 401 }; 402 403 aop_image_mem: memory@80800000 { 404 reg = <0x0 0x80800000 0x0 0x60000>; 405 no-map; 406 }; 407 408 aop_cmd_db_mem: memory@80860000 { 409 compatible = "qcom,cmd-db"; 410 reg = <0x0 0x80860000 0x0 0x20000>; 411 no-map; 412 }; 413 414 aop_config_mem: memory@80880000 { 415 reg = <0x0 0x80880000 0x0 0x20000>; 416 no-map; 417 }; 418 419 tme_crash_dump_mem: memory@808a0000 { 420 reg = <0x0 0x808a0000 0x0 0x40000>; 421 no-map; 422 }; 423 424 tme_log_mem: memory@808e0000 { 425 reg = <0x0 0x808e0000 0x0 0x4000>; 426 no-map; 427 }; 428 429 uefi_log_mem: memory@808e4000 { 430 reg = <0x0 0x808e4000 0x0 0x10000>; 431 no-map; 432 }; 433 434 /* secdata region can be reused by apps */ 435 smem: memory@80900000 { 436 compatible = "qcom,smem"; 437 reg = <0x0 0x80900000 0x0 0x200000>; 438 hwlocks = <&tcsr_mutex 3>; 439 no-map; 440 }; 441 442 cpucp_fw_mem: memory@80b00000 { 443 reg = <0x0 0x80b00000 0x0 0x100000>; 444 no-map; 445 }; 446 447 cdsp_secure_heap: memory@80c00000 { 448 reg = <0x0 0x80c00000 0x0 0x4600000>; 449 no-map; 450 }; 451 452 video_mem: memory@85700000 { 453 reg = <0x0 0x85700000 0x0 0x700000>; 454 no-map; 455 }; 456 457 adsp_mem: memory@85e00000 { 458 reg = <0x0 0x85e00000 0x0 0x2100000>; 459 no-map; 460 }; 461 462 slpi_mem: memory@88000000 { 463 reg = <0x0 0x88000000 0x0 0x1900000>; 464 no-map; 465 }; 466 467 cdsp_mem: memory@89900000 { 468 reg = <0x0 0x89900000 0x0 0x2000000>; 469 no-map; 470 }; 471 472 ipa_fw_mem: memory@8b900000 { 473 reg = <0x0 0x8b900000 0x0 0x10000>; 474 no-map; 475 }; 476 477 ipa_gsi_mem: memory@8b910000 { 478 reg = <0x0 0x8b910000 0x0 0xa000>; 479 no-map; 480 }; 481 482 gpu_micro_code_mem: memory@8b91a000 { 483 reg = <0x0 0x8b91a000 0x0 0x2000>; 484 no-map; 485 }; 486 487 spss_region_mem: memory@8ba00000 { 488 reg = <0x0 0x8ba00000 0x0 0x180000>; 489 no-map; 490 }; 491 492 /* First part of the "SPU secure shared memory" region */ 493 spu_tz_shared_mem: memory@8bb80000 { 494 reg = <0x0 0x8bb80000 0x0 0x60000>; 495 no-map; 496 }; 497 498 /* Second part of the "SPU secure shared memory" region */ 499 spu_modem_shared_mem: memory@8bbe0000 { 500 reg = <0x0 0x8bbe0000 0x0 0x20000>; 501 no-map; 502 }; 503 504 mpss_mem: memory@8bc00000 { 505 reg = <0x0 0x8bc00000 0x0 0x13200000>; 506 no-map; 507 }; 508 509 cvp_mem: memory@9ee00000 { 510 reg = <0x0 0x9ee00000 0x0 0x700000>; 511 no-map; 512 }; 513 514 camera_mem: memory@9f500000 { 515 reg = <0x0 0x9f500000 0x0 0x800000>; 516 no-map; 517 }; 518 519 rmtfs_mem: memory@9fd00000 { 520 compatible = "qcom,rmtfs-mem"; 521 reg = <0x0 0x9fd00000 0x0 0x280000>; 522 no-map; 523 524 qcom,client-id = <1>; 525 qcom,vmid = <15>; 526 }; 527 528 xbl_sc_mem2: memory@a6e00000 { 529 reg = <0x0 0xa6e00000 0x0 0x40000>; 530 no-map; 531 }; 532 533 global_sync_mem: memory@a6f00000 { 534 reg = <0x0 0xa6f00000 0x0 0x100000>; 535 no-map; 536 }; 537 538 /* uefi region can be reused by APPS */ 539 540 /* Linux kernel image is loaded at 0xa0000000 */ 541 542 oem_vm_mem: memory@bb000000 { 543 reg = <0x0 0xbb000000 0x0 0x5000000>; 544 no-map; 545 }; 546 547 mte_mem: memory@c0000000 { 548 reg = <0x0 0xc0000000 0x0 0x20000000>; 549 no-map; 550 }; 551 552 qheebsp_reserved_mem: memory@e0000000 { 553 reg = <0x0 0xe0000000 0x0 0x600000>; 554 no-map; 555 }; 556 557 cpusys_vm_mem: memory@e0600000 { 558 reg = <0x0 0xe0600000 0x0 0x400000>; 559 no-map; 560 }; 561 562 hyp_reserved_mem: memory@e0a00000 { 563 reg = <0x0 0xe0a00000 0x0 0x100000>; 564 no-map; 565 }; 566 567 trust_ui_vm_mem: memory@e0b00000 { 568 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 569 no-map; 570 }; 571 572 trust_ui_vm_qrtr: memory@e55f3000 { 573 reg = <0x0 0xe55f3000 0x0 0x9000>; 574 no-map; 575 }; 576 577 trust_ui_vm_vblk0_ring: memory@e55fc000 { 578 reg = <0x0 0xe55fc000 0x0 0x4000>; 579 no-map; 580 }; 581 582 trust_ui_vm_swiotlb: memory@e5600000 { 583 reg = <0x0 0xe5600000 0x0 0x100000>; 584 no-map; 585 }; 586 587 tz_stat_mem: memory@e8800000 { 588 reg = <0x0 0xe8800000 0x0 0x100000>; 589 no-map; 590 }; 591 592 tags_mem: memory@e8900000 { 593 reg = <0x0 0xe8900000 0x0 0x1200000>; 594 no-map; 595 }; 596 597 qtee_mem: memory@e9b00000 { 598 reg = <0x0 0xe9b00000 0x0 0x500000>; 599 no-map; 600 }; 601 602 trusted_apps_mem: memory@ea000000 { 603 reg = <0x0 0xea000000 0x0 0x3900000>; 604 no-map; 605 }; 606 607 trusted_apps_ext_mem: memory@ed900000 { 608 reg = <0x0 0xed900000 0x0 0x3b00000>; 609 no-map; 610 }; 611 }; 612 613 smp2p-adsp { 614 compatible = "qcom,smp2p"; 615 qcom,smem = <443>, <429>; 616 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 617 IPCC_MPROC_SIGNAL_SMP2P 618 IRQ_TYPE_EDGE_RISING>; 619 mboxes = <&ipcc IPCC_CLIENT_LPASS 620 IPCC_MPROC_SIGNAL_SMP2P>; 621 622 qcom,local-pid = <0>; 623 qcom,remote-pid = <2>; 624 625 smp2p_adsp_out: master-kernel { 626 qcom,entry-name = "master-kernel"; 627 #qcom,smem-state-cells = <1>; 628 }; 629 630 smp2p_adsp_in: slave-kernel { 631 qcom,entry-name = "slave-kernel"; 632 interrupt-controller; 633 #interrupt-cells = <2>; 634 }; 635 }; 636 637 smp2p-cdsp { 638 compatible = "qcom,smp2p"; 639 qcom,smem = <94>, <432>; 640 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 641 IPCC_MPROC_SIGNAL_SMP2P 642 IRQ_TYPE_EDGE_RISING>; 643 mboxes = <&ipcc IPCC_CLIENT_CDSP 644 IPCC_MPROC_SIGNAL_SMP2P>; 645 646 qcom,local-pid = <0>; 647 qcom,remote-pid = <5>; 648 649 smp2p_cdsp_out: master-kernel { 650 qcom,entry-name = "master-kernel"; 651 #qcom,smem-state-cells = <1>; 652 }; 653 654 smp2p_cdsp_in: slave-kernel { 655 qcom,entry-name = "slave-kernel"; 656 interrupt-controller; 657 #interrupt-cells = <2>; 658 }; 659 }; 660 661 smp2p-modem { 662 compatible = "qcom,smp2p"; 663 qcom,smem = <435>, <428>; 664 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 665 IPCC_MPROC_SIGNAL_SMP2P 666 IRQ_TYPE_EDGE_RISING>; 667 mboxes = <&ipcc IPCC_CLIENT_MPSS 668 IPCC_MPROC_SIGNAL_SMP2P>; 669 670 qcom,local-pid = <0>; 671 qcom,remote-pid = <1>; 672 673 smp2p_modem_out: master-kernel { 674 qcom,entry-name = "master-kernel"; 675 #qcom,smem-state-cells = <1>; 676 }; 677 678 smp2p_modem_in: slave-kernel { 679 qcom,entry-name = "slave-kernel"; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 684 ipa_smp2p_out: ipa-ap-to-modem { 685 qcom,entry-name = "ipa"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 ipa_smp2p_in: ipa-modem-to-ap { 690 qcom,entry-name = "ipa"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-slpi { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <481>, <430>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_SLPI 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <3>; 707 708 smp2p_slpi_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 smp2p_slpi_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 }; 719 720 soc: soc@0 { 721 #address-cells = <2>; 722 #size-cells = <2>; 723 ranges = <0 0 0 0 0x10 0>; 724 dma-ranges = <0 0 0 0 0x10 0>; 725 compatible = "simple-bus"; 726 727 gcc: clock-controller@100000 { 728 compatible = "qcom,gcc-sm8450"; 729 reg = <0x0 0x00100000 0x0 0x1f4200>; 730 #clock-cells = <1>; 731 #reset-cells = <1>; 732 #power-domain-cells = <1>; 733 clocks = <&rpmhcc RPMH_CXO_CLK>, 734 <&pcie0_lane>, 735 <&pcie1_lane>, 736 <&sleep_clk>; 737 clock-names = "bi_tcxo", 738 "pcie_0_pipe_clk", 739 "pcie_1_pipe_clk", 740 "sleep_clk"; 741 }; 742 743 gpi_dma2: dma-controller@800000 { 744 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 745 #dma-cells = <3>; 746 reg = <0 0x800000 0 0x60000>; 747 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 759 dma-channels = <12>; 760 dma-channel-mask = <0x7e>; 761 iommus = <&apps_smmu 0x496 0x0>; 762 status = "disabled"; 763 }; 764 765 qupv3_id_2: geniqup@8c0000 { 766 compatible = "qcom,geni-se-qup"; 767 reg = <0x0 0x008c0000 0x0 0x2000>; 768 clock-names = "m-ahb", "s-ahb"; 769 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 770 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 771 iommus = <&apps_smmu 0x483 0x0>; 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges; 775 status = "disabled"; 776 777 i2c15: i2c@880000 { 778 compatible = "qcom,geni-i2c"; 779 reg = <0x0 0x00880000 0x0 0x4000>; 780 clock-names = "se"; 781 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&qup_i2c15_data_clk>; 784 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 788 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 789 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 790 interconnect-names = "qup-core", "qup-config", "qup-memory"; 791 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 792 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 793 dma-names = "tx", "rx"; 794 status = "disabled"; 795 }; 796 797 spi15: spi@880000 { 798 compatible = "qcom,geni-spi"; 799 reg = <0x0 0x00880000 0x0 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 802 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 805 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 806 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 807 interconnect-names = "qup-core", "qup-config"; 808 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 809 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 810 dma-names = "tx", "rx"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 status = "disabled"; 814 }; 815 816 i2c16: i2c@884000 { 817 compatible = "qcom,geni-i2c"; 818 reg = <0x0 0x00884000 0x0 0x4000>; 819 clock-names = "se"; 820 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_i2c16_data_clk>; 823 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 827 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 828 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 830 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 831 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 832 dma-names = "tx", "rx"; 833 status = "disabled"; 834 }; 835 836 spi16: spi@884000 { 837 compatible = "qcom,geni-spi"; 838 reg = <0x0 0x00884000 0x0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 841 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 844 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 845 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 846 interconnect-names = "qup-core", "qup-config"; 847 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 848 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 849 dma-names = "tx", "rx"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 i2c17: i2c@888000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0x0 0x00888000 0x0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_i2c17_data_clk>; 862 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 866 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 867 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 868 interconnect-names = "qup-core", "qup-config", "qup-memory"; 869 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 870 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 871 dma-names = "tx", "rx"; 872 status = "disabled"; 873 }; 874 875 spi17: spi@888000 { 876 compatible = "qcom,geni-spi"; 877 reg = <0x0 0x00888000 0x0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 880 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 883 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 884 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 885 interconnect-names = "qup-core", "qup-config"; 886 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 887 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 888 dma-names = "tx", "rx"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 894 i2c18: i2c@88c000 { 895 compatible = "qcom,geni-i2c"; 896 reg = <0x0 0x0088c000 0x0 0x4000>; 897 clock-names = "se"; 898 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&qup_i2c18_data_clk>; 901 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 905 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 906 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 907 interconnect-names = "qup-core", "qup-config", "qup-memory"; 908 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 909 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 910 dma-names = "tx", "rx"; 911 status = "disabled"; 912 }; 913 914 spi18: spi@88c000 { 915 compatible = "qcom,geni-spi"; 916 reg = <0 0x0088c000 0 0x4000>; 917 clock-names = "se"; 918 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 919 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 922 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 923 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 924 interconnect-names = "qup-core", "qup-config"; 925 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 926 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 927 dma-names = "tx", "rx"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 933 i2c19: i2c@890000 { 934 compatible = "qcom,geni-i2c"; 935 reg = <0x0 0x00890000 0x0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_i2c19_data_clk>; 940 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 944 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 945 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 946 interconnect-names = "qup-core", "qup-config", "qup-memory"; 947 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 948 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 949 dma-names = "tx", "rx"; 950 status = "disabled"; 951 }; 952 953 spi19: spi@890000 { 954 compatible = "qcom,geni-spi"; 955 reg = <0 0x00890000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 958 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 961 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 962 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 963 interconnect-names = "qup-core", "qup-config"; 964 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 965 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 966 dma-names = "tx", "rx"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 i2c20: i2c@894000 { 973 compatible = "qcom,geni-i2c"; 974 reg = <0x0 0x00894000 0x0 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_i2c20_data_clk>; 979 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 983 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 984 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 985 interconnect-names = "qup-core", "qup-config", "qup-memory"; 986 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 987 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 988 dma-names = "tx", "rx"; 989 status = "disabled"; 990 }; 991 992 uart20: serial@894000 { 993 compatible = "qcom,geni-uart"; 994 reg = <0 0x00894000 0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_uart20_default>; 999 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 spi20: spi@894000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00894000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1015 interconnect-names = "qup-core", "qup-config"; 1016 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1017 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1018 dma-names = "tx", "rx"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 i2c21: i2c@898000 { 1025 compatible = "qcom,geni-i2c"; 1026 reg = <0x0 0x00898000 0x0 0x4000>; 1027 clock-names = "se"; 1028 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&qup_i2c21_data_clk>; 1031 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1035 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1036 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1037 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1038 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1039 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1040 dma-names = "tx", "rx"; 1041 status = "disabled"; 1042 }; 1043 1044 spi21: spi@898000 { 1045 compatible = "qcom,geni-spi"; 1046 reg = <0 0x00898000 0 0x4000>; 1047 clock-names = "se"; 1048 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1049 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1053 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1054 interconnect-names = "qup-core", "qup-config"; 1055 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1056 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1057 dma-names = "tx", "rx"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 }; 1063 1064 gpi_dma0: dma-controller@900000 { 1065 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1066 #dma-cells = <3>; 1067 reg = <0 0x900000 0 0x60000>; 1068 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1080 dma-channels = <12>; 1081 dma-channel-mask = <0x7e>; 1082 iommus = <&apps_smmu 0x5b6 0x0>; 1083 status = "disabled"; 1084 }; 1085 1086 qupv3_id_0: geniqup@9c0000 { 1087 compatible = "qcom,geni-se-qup"; 1088 reg = <0x0 0x009c0000 0x0 0x2000>; 1089 clock-names = "m-ahb", "s-ahb"; 1090 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1091 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1092 iommus = <&apps_smmu 0x5a3 0x0>; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1094 interconnect-names = "qup-core"; 1095 #address-cells = <2>; 1096 #size-cells = <2>; 1097 ranges; 1098 status = "disabled"; 1099 1100 i2c0: i2c@980000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0x0 0x00980000 0x0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c0_data_clk>; 1107 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1111 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1112 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1113 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1114 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1115 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1116 dma-names = "tx", "rx"; 1117 status = "disabled"; 1118 }; 1119 1120 spi0: spi@980000 { 1121 compatible = "qcom,geni-spi"; 1122 reg = <0x0 0x00980000 0x0 0x4000>; 1123 clock-names = "se"; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1125 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1128 power-domains = <&rpmhpd SM8450_CX>; 1129 operating-points-v2 = <&qup_opp_table_100mhz>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1131 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1132 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1133 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1134 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1135 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1136 dma-names = "tx", "rx"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 i2c1: i2c@984000 { 1143 compatible = "qcom,geni-i2c"; 1144 reg = <0x0 0x00984000 0x0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_i2c1_data_clk>; 1149 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1153 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1154 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1155 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1156 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1157 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1158 dma-names = "tx", "rx"; 1159 status = "disabled"; 1160 }; 1161 1162 spi1: spi@984000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0x0 0x00984000 0x0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1167 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1172 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1173 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1174 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1175 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1176 dma-names = "tx", "rx"; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 status = "disabled"; 1180 }; 1181 1182 i2c2: i2c@988000 { 1183 compatible = "qcom,geni-i2c"; 1184 reg = <0x0 0x00988000 0x0 0x4000>; 1185 clock-names = "se"; 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1187 pinctrl-names = "default"; 1188 pinctrl-0 = <&qup_i2c2_data_clk>; 1189 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1193 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1194 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1195 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1196 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1197 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1198 dma-names = "tx", "rx"; 1199 status = "disabled"; 1200 }; 1201 1202 spi2: spi@988000 { 1203 compatible = "qcom,geni-spi"; 1204 reg = <0x0 0x00988000 0x0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1207 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1211 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1212 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1214 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1215 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1216 dma-names = "tx", "rx"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 1223 i2c3: i2c@98c000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0x0 0x0098c000 0x0 0x4000>; 1226 clock-names = "se"; 1227 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c3_data_clk>; 1230 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1234 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1235 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1237 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1238 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1239 dma-names = "tx", "rx"; 1240 status = "disabled"; 1241 }; 1242 1243 spi3: spi@98c000 { 1244 compatible = "qcom,geni-spi"; 1245 reg = <0x0 0x0098c000 0x0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1248 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1252 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1253 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1254 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1255 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1256 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1257 dma-names = "tx", "rx"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 i2c4: i2c@990000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0x0 0x00990000 0x0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&qup_i2c4_data_clk>; 1270 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1274 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1275 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1276 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1277 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1278 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1279 dma-names = "tx", "rx"; 1280 status = "disabled"; 1281 }; 1282 1283 spi4: spi@990000 { 1284 compatible = "qcom,geni-spi"; 1285 reg = <0x0 0x00990000 0x0 0x4000>; 1286 clock-names = "se"; 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1288 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1289 pinctrl-names = "default"; 1290 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1291 power-domains = <&rpmhpd SM8450_CX>; 1292 operating-points-v2 = <&qup_opp_table_100mhz>; 1293 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1294 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1295 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1296 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1297 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1298 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 i2c5: i2c@994000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0x0 0x00994000 0x0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_i2c5_data_clk>; 1312 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1316 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1317 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1318 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1319 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1320 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1321 dma-names = "tx", "rx"; 1322 status = "disabled"; 1323 }; 1324 1325 spi5: spi@994000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0x0 0x00994000 0x0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1330 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1334 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1335 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1336 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1337 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1338 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 status = "disabled"; 1343 }; 1344 1345 1346 i2c6: i2c@998000 { 1347 compatible = "qcom,geni-i2c"; 1348 reg = <0x0 0x998000 0x0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_i2c6_data_clk>; 1353 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1357 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1358 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1359 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1360 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1361 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1362 dma-names = "tx", "rx"; 1363 status = "disabled"; 1364 }; 1365 1366 spi6: spi@998000 { 1367 compatible = "qcom,geni-spi"; 1368 reg = <0x0 0x998000 0x0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1371 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1375 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1377 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1378 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1379 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 uart7: serial@99c000 { 1387 compatible = "qcom,geni-debug-uart"; 1388 reg = <0 0x0099c000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1393 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 }; 1399 1400 gpi_dma1: dma-controller@a00000 { 1401 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1402 #dma-cells = <3>; 1403 reg = <0 0xa00000 0 0x60000>; 1404 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1416 dma-channels = <12>; 1417 dma-channel-mask = <0x7e>; 1418 iommus = <&apps_smmu 0x56 0x0>; 1419 status = "disabled"; 1420 }; 1421 1422 qupv3_id_1: geniqup@ac0000 { 1423 compatible = "qcom,geni-se-qup"; 1424 reg = <0x0 0x00ac0000 0x0 0x6000>; 1425 clock-names = "m-ahb", "s-ahb"; 1426 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1427 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1428 iommus = <&apps_smmu 0x43 0x0>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1430 interconnect-names = "qup-core"; 1431 #address-cells = <2>; 1432 #size-cells = <2>; 1433 ranges; 1434 status = "disabled"; 1435 1436 i2c8: i2c@a80000 { 1437 compatible = "qcom,geni-i2c"; 1438 reg = <0x0 0x00a80000 0x0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&qup_i2c8_data_clk>; 1443 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1447 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1448 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1449 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1450 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1451 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1452 dma-names = "tx", "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 spi8: spi@a80000 { 1457 compatible = "qcom,geni-spi"; 1458 reg = <0x0 0x00a80000 0x0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1461 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1465 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1466 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1467 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1468 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1469 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1470 dma-names = "tx", "rx"; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 i2c9: i2c@a84000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0x0 0x00a84000 0x0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&qup_i2c9_data_clk>; 1483 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1488 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1489 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1490 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1491 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 spi9: spi@a84000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0x0 0x00a84000 0x0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1501 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1506 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1509 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1510 dma-names = "tx", "rx"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 i2c10: i2c@a88000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0x0 0x00a88000 0x0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c10_data_clk>; 1523 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1527 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1528 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1529 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1530 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1531 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1532 dma-names = "tx", "rx"; 1533 status = "disabled"; 1534 }; 1535 1536 spi10: spi@a88000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0x0 0x00a88000 0x0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1541 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1546 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1547 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1548 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1549 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1550 dma-names = "tx", "rx"; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 status = "disabled"; 1554 }; 1555 1556 i2c11: i2c@a8c000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0x0 0x00a8c000 0x0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_i2c11_data_clk>; 1563 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1567 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1568 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1569 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1570 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1571 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1572 dma-names = "tx", "rx"; 1573 status = "disabled"; 1574 }; 1575 1576 spi11: spi@a8c000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0x0 0x00a8c000 0x0 0x4000>; 1579 clock-names = "se"; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1581 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1585 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1586 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1587 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1588 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1589 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 status = "disabled"; 1594 }; 1595 1596 i2c12: i2c@a90000 { 1597 compatible = "qcom,geni-i2c"; 1598 reg = <0x0 0x00a90000 0x0 0x4000>; 1599 clock-names = "se"; 1600 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1601 pinctrl-names = "default"; 1602 pinctrl-0 = <&qup_i2c12_data_clk>; 1603 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1607 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1608 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1609 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1610 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1611 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1612 dma-names = "tx", "rx"; 1613 status = "disabled"; 1614 }; 1615 1616 spi12: spi@a90000 { 1617 compatible = "qcom,geni-spi"; 1618 reg = <0x0 0x00a90000 0x0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1621 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1624 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1625 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1626 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1627 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1628 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1629 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1630 dma-names = "tx", "rx"; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 status = "disabled"; 1634 }; 1635 1636 i2c13: i2c@a94000 { 1637 compatible = "qcom,geni-i2c"; 1638 reg = <0 0x00a94000 0 0x4000>; 1639 clock-names = "se"; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&qup_i2c13_data_clk>; 1643 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1644 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1645 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1646 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1647 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1648 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1649 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1650 dma-names = "tx", "rx"; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 status = "disabled"; 1654 }; 1655 1656 spi13: spi@a94000 { 1657 compatible = "qcom,geni-spi"; 1658 reg = <0x0 0x00a94000 0x0 0x4000>; 1659 clock-names = "se"; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1661 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1666 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1667 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1668 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1669 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1670 dma-names = "tx", "rx"; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 status = "disabled"; 1674 }; 1675 1676 i2c14: i2c@a98000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x00a98000 0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c14_data_clk>; 1683 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1684 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1685 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1686 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1687 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1688 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1689 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1690 dma-names = "tx", "rx"; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 spi14: spi@a98000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0x0 0x00a98000 0x0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1701 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1704 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1705 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1706 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1707 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1708 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1709 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1710 dma-names = "tx", "rx"; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 }; 1716 1717 pcie0: pci@1c00000 { 1718 compatible = "qcom,pcie-sm8450-pcie0"; 1719 reg = <0 0x01c00000 0 0x3000>, 1720 <0 0x60000000 0 0xf1d>, 1721 <0 0x60000f20 0 0xa8>, 1722 <0 0x60001000 0 0x1000>, 1723 <0 0x60100000 0 0x100000>; 1724 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1725 device_type = "pci"; 1726 linux,pci-domain = <0>; 1727 bus-range = <0x00 0xff>; 1728 num-lanes = <1>; 1729 1730 #address-cells = <3>; 1731 #size-cells = <2>; 1732 1733 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1734 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1735 1736 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1737 interrupt-names = "msi"; 1738 #interrupt-cells = <1>; 1739 interrupt-map-mask = <0 0 0 0x7>; 1740 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1741 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1742 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1743 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1744 1745 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1746 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1747 <&pcie0_lane>, 1748 <&rpmhcc RPMH_CXO_CLK>, 1749 <&gcc GCC_PCIE_0_AUX_CLK>, 1750 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1751 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1752 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1753 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1754 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1755 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1756 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1757 clock-names = "pipe", 1758 "pipe_mux", 1759 "phy_pipe", 1760 "ref", 1761 "aux", 1762 "cfg", 1763 "bus_master", 1764 "bus_slave", 1765 "slave_q2a", 1766 "ddrss_sf_tbu", 1767 "aggre0", 1768 "aggre1"; 1769 1770 iommus = <&apps_smmu 0x1c00 0x7f>; 1771 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1772 <0x100 &apps_smmu 0x1c01 0x1>; 1773 1774 resets = <&gcc GCC_PCIE_0_BCR>; 1775 reset-names = "pci"; 1776 1777 power-domains = <&gcc PCIE_0_GDSC>; 1778 power-domain-names = "gdsc"; 1779 1780 phys = <&pcie0_lane>; 1781 phy-names = "pciephy"; 1782 1783 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1784 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1785 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&pcie0_default_state>; 1788 1789 status = "disabled"; 1790 }; 1791 1792 pcie0_phy: phy@1c06000 { 1793 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1794 reg = <0 0x01c06000 0 0x200>; 1795 #address-cells = <2>; 1796 #size-cells = <2>; 1797 ranges; 1798 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1799 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1800 <&gcc GCC_PCIE_0_CLKREF_EN>, 1801 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1802 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1803 1804 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1805 reset-names = "phy"; 1806 1807 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1808 assigned-clock-rates = <100000000>; 1809 1810 status = "disabled"; 1811 1812 pcie0_lane: phy@1c06200 { 1813 reg = <0 0x1c06e00 0 0x200>, /* tx */ 1814 <0 0x1c07000 0 0x200>, /* rx */ 1815 <0 0x1c06200 0 0x200>, /* pcs */ 1816 <0 0x1c06600 0 0x200>; /* pcs_pcie */ 1817 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1818 clock-names = "pipe0"; 1819 1820 #clock-cells = <0>; 1821 #phy-cells = <0>; 1822 clock-output-names = "pcie_0_pipe_clk"; 1823 }; 1824 }; 1825 1826 pcie1: pci@1c08000 { 1827 compatible = "qcom,pcie-sm8450-pcie1"; 1828 reg = <0 0x01c08000 0 0x3000>, 1829 <0 0x40000000 0 0xf1d>, 1830 <0 0x40000f20 0 0xa8>, 1831 <0 0x40001000 0 0x1000>, 1832 <0 0x40100000 0 0x100000>; 1833 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1834 device_type = "pci"; 1835 linux,pci-domain = <1>; 1836 bus-range = <0x00 0xff>; 1837 num-lanes = <2>; 1838 1839 #address-cells = <3>; 1840 #size-cells = <2>; 1841 1842 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1843 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1844 1845 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1846 interrupt-names = "msi"; 1847 #interrupt-cells = <1>; 1848 interrupt-map-mask = <0 0 0 0x7>; 1849 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1850 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1851 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1852 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1853 1854 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1855 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1856 <&pcie1_lane>, 1857 <&rpmhcc RPMH_CXO_CLK>, 1858 <&gcc GCC_PCIE_1_AUX_CLK>, 1859 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1860 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1861 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1862 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1863 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1864 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1865 clock-names = "pipe", 1866 "pipe_mux", 1867 "phy_pipe", 1868 "ref", 1869 "aux", 1870 "cfg", 1871 "bus_master", 1872 "bus_slave", 1873 "slave_q2a", 1874 "ddrss_sf_tbu", 1875 "aggre1"; 1876 1877 iommus = <&apps_smmu 0x1c80 0x7f>; 1878 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1879 <0x100 &apps_smmu 0x1c81 0x1>; 1880 1881 resets = <&gcc GCC_PCIE_1_BCR>; 1882 reset-names = "pci"; 1883 1884 power-domains = <&gcc PCIE_1_GDSC>; 1885 power-domain-names = "gdsc"; 1886 1887 phys = <&pcie1_lane>; 1888 phy-names = "pciephy"; 1889 1890 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; 1891 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1892 1893 pinctrl-names = "default"; 1894 pinctrl-0 = <&pcie1_default_state>; 1895 1896 status = "disabled"; 1897 }; 1898 1899 pcie1_phy: phy@1c0f000 { 1900 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1901 reg = <0 0x01c0f000 0 0x200>; 1902 #address-cells = <2>; 1903 #size-cells = <2>; 1904 ranges; 1905 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1906 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1907 <&gcc GCC_PCIE_1_CLKREF_EN>, 1908 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1909 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1910 1911 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1912 reset-names = "phy"; 1913 1914 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1915 assigned-clock-rates = <100000000>; 1916 1917 status = "disabled"; 1918 1919 pcie1_lane: phy@1c0e000 { 1920 reg = <0 0x1c0e000 0 0x200>, /* tx */ 1921 <0 0x1c0e200 0 0x300>, /* rx */ 1922 <0 0x1c0f200 0 0x200>, /* pcs */ 1923 <0 0x1c0e800 0 0x200>, /* tx */ 1924 <0 0x1c0ea00 0 0x300>, /* rx */ 1925 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ 1926 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1927 clock-names = "pipe0"; 1928 1929 #clock-cells = <0>; 1930 #phy-cells = <0>; 1931 clock-output-names = "pcie_1_pipe_clk"; 1932 }; 1933 }; 1934 1935 config_noc: interconnect@1500000 { 1936 compatible = "qcom,sm8450-config-noc"; 1937 reg = <0 0x01500000 0 0x1c000>; 1938 #interconnect-cells = <2>; 1939 qcom,bcm-voters = <&apps_bcm_voter>; 1940 }; 1941 1942 system_noc: interconnect@1680000 { 1943 compatible = "qcom,sm8450-system-noc"; 1944 reg = <0 0x01680000 0 0x1e200>; 1945 #interconnect-cells = <2>; 1946 qcom,bcm-voters = <&apps_bcm_voter>; 1947 }; 1948 1949 pcie_noc: interconnect@16c0000 { 1950 compatible = "qcom,sm8450-pcie-anoc"; 1951 reg = <0 0x016c0000 0 0xe280>; 1952 #interconnect-cells = <2>; 1953 qcom,bcm-voters = <&apps_bcm_voter>; 1954 }; 1955 1956 aggre1_noc: interconnect@16e0000 { 1957 compatible = "qcom,sm8450-aggre1-noc"; 1958 reg = <0 0x016e0000 0 0x1c080>; 1959 #interconnect-cells = <2>; 1960 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1961 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1962 qcom,bcm-voters = <&apps_bcm_voter>; 1963 }; 1964 1965 aggre2_noc: interconnect@1700000 { 1966 compatible = "qcom,sm8450-aggre2-noc"; 1967 reg = <0 0x01700000 0 0x31080>; 1968 #interconnect-cells = <2>; 1969 qcom,bcm-voters = <&apps_bcm_voter>; 1970 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1971 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1972 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1973 <&rpmhcc RPMH_IPA_CLK>; 1974 }; 1975 1976 mmss_noc: interconnect@1740000 { 1977 compatible = "qcom,sm8450-mmss-noc"; 1978 reg = <0 0x01740000 0 0x1f080>; 1979 #interconnect-cells = <2>; 1980 qcom,bcm-voters = <&apps_bcm_voter>; 1981 }; 1982 1983 tcsr_mutex: hwlock@1f40000 { 1984 compatible = "qcom,tcsr-mutex"; 1985 reg = <0x0 0x01f40000 0x0 0x40000>; 1986 #hwlock-cells = <1>; 1987 }; 1988 1989 usb_1_hsphy: phy@88e3000 { 1990 compatible = "qcom,sm8450-usb-hs-phy", 1991 "qcom,usb-snps-hs-7nm-phy"; 1992 reg = <0 0x088e3000 0 0x400>; 1993 status = "disabled"; 1994 #phy-cells = <0>; 1995 1996 clocks = <&rpmhcc RPMH_CXO_CLK>; 1997 clock-names = "ref"; 1998 1999 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2000 }; 2001 2002 usb_1_qmpphy: phy-wrapper@88e9000 { 2003 compatible = "qcom,sm8450-qmp-usb3-phy"; 2004 reg = <0 0x088e9000 0 0x200>, 2005 <0 0x088e8000 0 0x20>; 2006 status = "disabled"; 2007 #address-cells = <2>; 2008 #size-cells = <2>; 2009 ranges; 2010 2011 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2012 <&rpmhcc RPMH_CXO_CLK>, 2013 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2014 clock-names = "aux", "ref_clk_src", "com_aux"; 2015 2016 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2017 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2018 reset-names = "phy", "common"; 2019 2020 usb_1_ssphy: phy@88e9200 { 2021 reg = <0 0x088e9200 0 0x200>, 2022 <0 0x088e9400 0 0x200>, 2023 <0 0x088e9c00 0 0x400>, 2024 <0 0x088e9600 0 0x200>, 2025 <0 0x088e9800 0 0x200>, 2026 <0 0x088e9a00 0 0x100>; 2027 #phy-cells = <0>; 2028 #clock-cells = <0>; 2029 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2030 clock-names = "pipe0"; 2031 clock-output-names = "usb3_phy_pipe_clk_src"; 2032 }; 2033 }; 2034 2035 remoteproc_slpi: remoteproc@2400000 { 2036 compatible = "qcom,sm8450-slpi-pas"; 2037 reg = <0 0x02400000 0 0x4000>; 2038 2039 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2040 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2041 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2042 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2043 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2044 interrupt-names = "wdog", "fatal", "ready", 2045 "handover", "stop-ack"; 2046 2047 clocks = <&rpmhcc RPMH_CXO_CLK>; 2048 clock-names = "xo"; 2049 2050 power-domains = <&rpmhpd SM8450_LCX>, 2051 <&rpmhpd SM8450_LMX>; 2052 power-domain-names = "lcx", "lmx"; 2053 2054 memory-region = <&slpi_mem>; 2055 2056 qcom,qmp = <&aoss_qmp>; 2057 2058 qcom,smem-states = <&smp2p_slpi_out 0>; 2059 qcom,smem-state-names = "stop"; 2060 2061 status = "disabled"; 2062 2063 glink-edge { 2064 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2065 IPCC_MPROC_SIGNAL_GLINK_QMP 2066 IRQ_TYPE_EDGE_RISING>; 2067 mboxes = <&ipcc IPCC_CLIENT_SLPI 2068 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2069 2070 label = "slpi"; 2071 qcom,remote-pid = <3>; 2072 2073 fastrpc { 2074 compatible = "qcom,fastrpc"; 2075 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2076 label = "sdsp"; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 2080 compute-cb@1 { 2081 compatible = "qcom,fastrpc-compute-cb"; 2082 reg = <1>; 2083 iommus = <&apps_smmu 0x0541 0x0>; 2084 }; 2085 2086 compute-cb@2 { 2087 compatible = "qcom,fastrpc-compute-cb"; 2088 reg = <2>; 2089 iommus = <&apps_smmu 0x0542 0x0>; 2090 }; 2091 2092 compute-cb@3 { 2093 compatible = "qcom,fastrpc-compute-cb"; 2094 reg = <3>; 2095 iommus = <&apps_smmu 0x0543 0x0>; 2096 /* note: shared-cb = <4> in downstream */ 2097 }; 2098 }; 2099 }; 2100 }; 2101 2102 wsa2macro: codec@31e0000 { 2103 compatible = "qcom,sm8450-lpass-wsa-macro"; 2104 reg = <0 0x031e0000 0 0x1000>; 2105 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2106 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2107 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2108 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2109 <&vamacro>; 2110 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2111 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2112 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2113 assigned-clock-rates = <19200000>, <19200000>; 2114 2115 #clock-cells = <0>; 2116 clock-output-names = "wsa2-mclk"; 2117 pinctrl-names = "default"; 2118 pinctrl-0 = <&wsa2_swr_active>; 2119 #sound-dai-cells = <1>; 2120 }; 2121 2122 /* WSA2 */ 2123 swr4: soundwire-controller@31f0000 { 2124 compatible = "qcom,soundwire-v1.7.0"; 2125 reg = <0 0x031f0000 0 0x2000>; 2126 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2127 clocks = <&wsa2macro>; 2128 clock-names = "iface"; 2129 2130 qcom,din-ports = <2>; 2131 qcom,dout-ports = <6>; 2132 2133 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2134 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2135 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2136 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2137 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2138 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2139 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2140 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2141 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2142 2143 #address-cells = <2>; 2144 #size-cells = <0>; 2145 #sound-dai-cells = <1>; 2146 }; 2147 2148 rxmacro: codec@3200000 { 2149 compatible = "qcom,sm8450-lpass-rx-macro"; 2150 reg = <0 0x3200000 0 0x1000>; 2151 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2152 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2153 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2154 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2155 <&vamacro>; 2156 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2157 2158 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2159 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2160 assigned-clock-rates = <19200000>, <19200000>; 2161 2162 #clock-cells = <0>; 2163 clock-output-names = "mclk"; 2164 pinctrl-names = "default"; 2165 pinctrl-0 = <&rx_swr_active>; 2166 #sound-dai-cells = <1>; 2167 }; 2168 2169 swr1: soundwire-controller@3210000 { 2170 compatible = "qcom,soundwire-v1.7.0"; 2171 reg = <0 0x3210000 0 0x2000>; 2172 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2173 clocks = <&rxmacro>; 2174 clock-names = "iface"; 2175 label = "RX"; 2176 qcom,din-ports = <0>; 2177 qcom,dout-ports = <5>; 2178 2179 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2180 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2181 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2182 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2183 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2184 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2185 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2186 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2187 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2188 2189 #address-cells = <2>; 2190 #size-cells = <0>; 2191 #sound-dai-cells = <1>; 2192 }; 2193 2194 txmacro: codec@3220000 { 2195 compatible = "qcom,sm8450-lpass-tx-macro"; 2196 reg = <0 0x3220000 0 0x1000>; 2197 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2198 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2199 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2200 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2201 <&vamacro>; 2202 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2203 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2204 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2205 assigned-clock-rates = <19200000>, <19200000>; 2206 2207 #clock-cells = <0>; 2208 clock-output-names = "mclk"; 2209 pinctrl-names = "default"; 2210 pinctrl-0 = <&tx_swr_active>; 2211 #sound-dai-cells = <1>; 2212 }; 2213 2214 wsamacro: codec@3240000 { 2215 compatible = "qcom,sm8450-lpass-wsa-macro"; 2216 reg = <0 0x03240000 0 0x1000>; 2217 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2218 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2219 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2220 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2221 <&vamacro>; 2222 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2223 2224 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2225 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2226 assigned-clock-rates = <19200000>, <19200000>; 2227 2228 #clock-cells = <0>; 2229 clock-output-names = "mclk"; 2230 pinctrl-names = "default"; 2231 pinctrl-0 = <&wsa_swr_active>; 2232 #sound-dai-cells = <1>; 2233 }; 2234 2235 /* WSA */ 2236 swr0: soundwire-controller@3250000 { 2237 compatible = "qcom,soundwire-v1.7.0"; 2238 reg = <0 0x03250000 0 0x2000>; 2239 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2240 clocks = <&wsamacro>; 2241 clock-names = "iface"; 2242 2243 qcom,din-ports = <2>; 2244 qcom,dout-ports = <6>; 2245 2246 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2247 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2248 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2249 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2250 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2251 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2252 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2253 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2254 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2255 2256 #address-cells = <2>; 2257 #size-cells = <0>; 2258 #sound-dai-cells = <1>; 2259 }; 2260 2261 swr2: soundwire-controller@33b0000 { 2262 compatible = "qcom,soundwire-v1.7.0"; 2263 reg = <0 0x33b0000 0 0x2000>; 2264 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2265 <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2266 interrupt-names = "core", "wake"; 2267 2268 clocks = <&vamacro>; 2269 clock-names = "iface"; 2270 label = "TX"; 2271 2272 qcom,din-ports = <4>; 2273 qcom,dout-ports = <0>; 2274 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2275 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2276 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2277 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2278 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2279 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2280 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2281 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2282 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2283 2284 #address-cells = <2>; 2285 #size-cells = <0>; 2286 #sound-dai-cells = <1>; 2287 }; 2288 2289 vamacro: codec@33f0000 { 2290 compatible = "qcom,sm8450-lpass-va-macro"; 2291 reg = <0 0x033f0000 0 0x1000>; 2292 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2293 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2294 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2295 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2296 clock-names = "mclk", "macro", "dcodec", "npl"; 2297 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2298 assigned-clock-rates = <19200000>; 2299 2300 #clock-cells = <0>; 2301 clock-output-names = "fsgen"; 2302 #sound-dai-cells = <1>; 2303 }; 2304 2305 remoteproc_adsp: remoteproc@30000000 { 2306 compatible = "qcom,sm8450-adsp-pas"; 2307 reg = <0 0x30000000 0 0x100>; 2308 2309 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2310 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2311 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2312 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2313 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2314 interrupt-names = "wdog", "fatal", "ready", 2315 "handover", "stop-ack"; 2316 2317 clocks = <&rpmhcc RPMH_CXO_CLK>; 2318 clock-names = "xo"; 2319 2320 power-domains = <&rpmhpd SM8450_LCX>, 2321 <&rpmhpd SM8450_LMX>; 2322 power-domain-names = "lcx", "lmx"; 2323 2324 memory-region = <&adsp_mem>; 2325 2326 qcom,qmp = <&aoss_qmp>; 2327 2328 qcom,smem-states = <&smp2p_adsp_out 0>; 2329 qcom,smem-state-names = "stop"; 2330 2331 status = "disabled"; 2332 2333 remoteproc_adsp_glink: glink-edge { 2334 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2335 IPCC_MPROC_SIGNAL_GLINK_QMP 2336 IRQ_TYPE_EDGE_RISING>; 2337 mboxes = <&ipcc IPCC_CLIENT_LPASS 2338 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2339 2340 label = "lpass"; 2341 qcom,remote-pid = <2>; 2342 2343 gpr { 2344 compatible = "qcom,gpr"; 2345 qcom,glink-channels = "adsp_apps"; 2346 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2347 qcom,intents = <512 20>; 2348 #address-cells = <1>; 2349 #size-cells = <0>; 2350 2351 q6apm: service@1 { 2352 compatible = "qcom,q6apm"; 2353 reg = <GPR_APM_MODULE_IID>; 2354 #sound-dai-cells = <0>; 2355 qcom,protection-domain = "avs/audio", 2356 "msm/adsp/audio_pd"; 2357 2358 q6apmdai: dais { 2359 compatible = "qcom,q6apm-dais"; 2360 iommus = <&apps_smmu 0x1801 0x0>; 2361 }; 2362 2363 q6apmbedai: bedais { 2364 compatible = "qcom,q6apm-lpass-dais"; 2365 #sound-dai-cells = <1>; 2366 }; 2367 }; 2368 2369 q6prm: service@2 { 2370 compatible = "qcom,q6prm"; 2371 reg = <GPR_PRM_MODULE_IID>; 2372 qcom,protection-domain = "avs/audio", 2373 "msm/adsp/audio_pd"; 2374 2375 q6prmcc: clock-controller { 2376 compatible = "qcom,q6prm-lpass-clocks"; 2377 #clock-cells = <2>; 2378 }; 2379 }; 2380 }; 2381 2382 fastrpc { 2383 compatible = "qcom,fastrpc"; 2384 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2385 label = "adsp"; 2386 #address-cells = <1>; 2387 #size-cells = <0>; 2388 2389 compute-cb@3 { 2390 compatible = "qcom,fastrpc-compute-cb"; 2391 reg = <3>; 2392 iommus = <&apps_smmu 0x1803 0x0>; 2393 }; 2394 2395 compute-cb@4 { 2396 compatible = "qcom,fastrpc-compute-cb"; 2397 reg = <4>; 2398 iommus = <&apps_smmu 0x1804 0x0>; 2399 }; 2400 2401 compute-cb@5 { 2402 compatible = "qcom,fastrpc-compute-cb"; 2403 reg = <5>; 2404 iommus = <&apps_smmu 0x1805 0x0>; 2405 }; 2406 }; 2407 }; 2408 }; 2409 2410 remoteproc_cdsp: remoteproc@32300000 { 2411 compatible = "qcom,sm8450-cdsp-pas"; 2412 reg = <0 0x32300000 0 0x1400000>; 2413 2414 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2415 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2416 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2417 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2418 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2419 interrupt-names = "wdog", "fatal", "ready", 2420 "handover", "stop-ack"; 2421 2422 clocks = <&rpmhcc RPMH_CXO_CLK>; 2423 clock-names = "xo"; 2424 2425 power-domains = <&rpmhpd SM8450_CX>, 2426 <&rpmhpd SM8450_MXC>; 2427 power-domain-names = "cx", "mxc"; 2428 2429 memory-region = <&cdsp_mem>; 2430 2431 qcom,qmp = <&aoss_qmp>; 2432 2433 qcom,smem-states = <&smp2p_cdsp_out 0>; 2434 qcom,smem-state-names = "stop"; 2435 2436 status = "disabled"; 2437 2438 glink-edge { 2439 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2440 IPCC_MPROC_SIGNAL_GLINK_QMP 2441 IRQ_TYPE_EDGE_RISING>; 2442 mboxes = <&ipcc IPCC_CLIENT_CDSP 2443 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2444 2445 label = "cdsp"; 2446 qcom,remote-pid = <5>; 2447 2448 fastrpc { 2449 compatible = "qcom,fastrpc"; 2450 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2451 label = "cdsp"; 2452 #address-cells = <1>; 2453 #size-cells = <0>; 2454 2455 compute-cb@1 { 2456 compatible = "qcom,fastrpc-compute-cb"; 2457 reg = <1>; 2458 iommus = <&apps_smmu 0x2161 0x0400>, 2459 <&apps_smmu 0x1021 0x1420>; 2460 }; 2461 2462 compute-cb@2 { 2463 compatible = "qcom,fastrpc-compute-cb"; 2464 reg = <2>; 2465 iommus = <&apps_smmu 0x2162 0x0400>, 2466 <&apps_smmu 0x1022 0x1420>; 2467 }; 2468 2469 compute-cb@3 { 2470 compatible = "qcom,fastrpc-compute-cb"; 2471 reg = <3>; 2472 iommus = <&apps_smmu 0x2163 0x0400>, 2473 <&apps_smmu 0x1023 0x1420>; 2474 }; 2475 2476 compute-cb@4 { 2477 compatible = "qcom,fastrpc-compute-cb"; 2478 reg = <4>; 2479 iommus = <&apps_smmu 0x2164 0x0400>, 2480 <&apps_smmu 0x1024 0x1420>; 2481 }; 2482 2483 compute-cb@5 { 2484 compatible = "qcom,fastrpc-compute-cb"; 2485 reg = <5>; 2486 iommus = <&apps_smmu 0x2165 0x0400>, 2487 <&apps_smmu 0x1025 0x1420>; 2488 }; 2489 2490 compute-cb@6 { 2491 compatible = "qcom,fastrpc-compute-cb"; 2492 reg = <6>; 2493 iommus = <&apps_smmu 0x2166 0x0400>, 2494 <&apps_smmu 0x1026 0x1420>; 2495 }; 2496 2497 compute-cb@7 { 2498 compatible = "qcom,fastrpc-compute-cb"; 2499 reg = <7>; 2500 iommus = <&apps_smmu 0x2167 0x0400>, 2501 <&apps_smmu 0x1027 0x1420>; 2502 }; 2503 2504 compute-cb@8 { 2505 compatible = "qcom,fastrpc-compute-cb"; 2506 reg = <8>; 2507 iommus = <&apps_smmu 0x2168 0x0400>, 2508 <&apps_smmu 0x1028 0x1420>; 2509 }; 2510 2511 /* note: secure cb9 in downstream */ 2512 }; 2513 }; 2514 }; 2515 2516 remoteproc_mpss: remoteproc@4080000 { 2517 compatible = "qcom,sm8450-mpss-pas"; 2518 reg = <0x0 0x04080000 0x0 0x4040>; 2519 2520 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2521 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2522 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2523 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2524 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2525 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2526 interrupt-names = "wdog", "fatal", "ready", "handover", 2527 "stop-ack", "shutdown-ack"; 2528 2529 clocks = <&rpmhcc RPMH_CXO_CLK>; 2530 clock-names = "xo"; 2531 2532 power-domains = <&rpmhpd SM8450_CX>, 2533 <&rpmhpd SM8450_MSS>; 2534 power-domain-names = "cx", "mss"; 2535 2536 memory-region = <&mpss_mem>; 2537 2538 qcom,qmp = <&aoss_qmp>; 2539 2540 qcom,smem-states = <&smp2p_modem_out 0>; 2541 qcom,smem-state-names = "stop"; 2542 2543 status = "disabled"; 2544 2545 glink-edge { 2546 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2547 IPCC_MPROC_SIGNAL_GLINK_QMP 2548 IRQ_TYPE_EDGE_RISING>; 2549 mboxes = <&ipcc IPCC_CLIENT_MPSS 2550 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2551 label = "modem"; 2552 qcom,remote-pid = <1>; 2553 }; 2554 }; 2555 2556 cci0: cci@ac15000 { 2557 compatible = "qcom,sm8450-cci"; 2558 reg = <0 0xac15000 0 0x1000>; 2559 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2560 power-domains = <&camcc TITAN_TOP_GDSC>; 2561 2562 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2563 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2564 <&camcc CAM_CC_CPAS_AHB_CLK>, 2565 <&camcc CAM_CC_CCI_0_CLK>, 2566 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2567 clock-names = "camnoc_axi", 2568 "slow_ahb_src", 2569 "cpas_ahb", 2570 "cci", 2571 "cci_src"; 2572 pinctrl-0 = <&cci0_default &cci1_default>; 2573 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2574 pinctrl-names = "default", "sleep"; 2575 2576 status = "disabled"; 2577 #address-cells = <1>; 2578 #size-cells = <0>; 2579 2580 cci0_i2c0: i2c-bus@0 { 2581 reg = <0>; 2582 clock-frequency = <1000000>; 2583 #address-cells = <1>; 2584 #size-cells = <0>; 2585 }; 2586 2587 cci0_i2c1: i2c-bus@1 { 2588 reg = <1>; 2589 clock-frequency = <1000000>; 2590 #address-cells = <1>; 2591 #size-cells = <0>; 2592 }; 2593 }; 2594 2595 cci1: cci@ac16000 { 2596 compatible = "qcom,sm8450-cci"; 2597 reg = <0 0xac16000 0 0x1000>; 2598 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2599 power-domains = <&camcc TITAN_TOP_GDSC>; 2600 2601 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2602 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2603 <&camcc CAM_CC_CPAS_AHB_CLK>, 2604 <&camcc CAM_CC_CCI_1_CLK>, 2605 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2606 clock-names = "camnoc_axi", 2607 "slow_ahb_src", 2608 "cpas_ahb", 2609 "cci", 2610 "cci_src"; 2611 pinctrl-0 = <&cci2_default &cci3_default>; 2612 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2613 pinctrl-names = "default", "sleep"; 2614 2615 status = "disabled"; 2616 #address-cells = <1>; 2617 #size-cells = <0>; 2618 2619 cci1_i2c0: i2c-bus@0 { 2620 reg = <0>; 2621 clock-frequency = <1000000>; 2622 #address-cells = <1>; 2623 #size-cells = <0>; 2624 }; 2625 2626 cci1_i2c1: i2c-bus@1 { 2627 reg = <1>; 2628 clock-frequency = <1000000>; 2629 #address-cells = <1>; 2630 #size-cells = <0>; 2631 }; 2632 }; 2633 2634 camcc: clock-controller@ade0000 { 2635 compatible = "qcom,sm8450-camcc"; 2636 reg = <0 0x0ade0000 0 0x20000>; 2637 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2638 <&rpmhcc RPMH_CXO_CLK>, 2639 <&rpmhcc RPMH_CXO_CLK_A>, 2640 <&sleep_clk>; 2641 power-domains = <&rpmhpd SM8450_MMCX>; 2642 required-opps = <&rpmhpd_opp_low_svs>; 2643 #clock-cells = <1>; 2644 #reset-cells = <1>; 2645 #power-domain-cells = <1>; 2646 status = "disabled"; 2647 }; 2648 2649 dispcc: clock-controller@af00000 { 2650 compatible = "qcom,sm8450-dispcc"; 2651 reg = <0 0x0af00000 0 0x20000>; 2652 clocks = <&rpmhcc RPMH_CXO_CLK>, 2653 <&rpmhcc RPMH_CXO_CLK_A>, 2654 <&gcc GCC_DISP_AHB_CLK>, 2655 <&sleep_clk>, 2656 <0>, /* dsi0 */ 2657 <0>, 2658 <0>, /* dsi1 */ 2659 <0>, 2660 <0>, /* dp0 */ 2661 <0>, 2662 <0>, /* dp1 */ 2663 <0>, 2664 <0>, /* dp2 */ 2665 <0>, 2666 <0>, /* dp3 */ 2667 <0>; 2668 power-domains = <&rpmhpd SM8450_MMCX>; 2669 required-opps = <&rpmhpd_opp_low_svs>; 2670 #clock-cells = <1>; 2671 #reset-cells = <1>; 2672 #power-domain-cells = <1>; 2673 status = "disabled"; 2674 }; 2675 2676 pdc: interrupt-controller@b220000 { 2677 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 2678 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2679 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 2680 <94 609 31>, <125 63 1>, <126 716 12>; 2681 #interrupt-cells = <2>; 2682 interrupt-parent = <&intc>; 2683 interrupt-controller; 2684 }; 2685 2686 tsens0: thermal-sensor@c263000 { 2687 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 2688 reg = <0 0x0c263000 0 0x1000>, /* TM */ 2689 <0 0x0c222000 0 0x1000>; /* SROT */ 2690 #qcom,sensors = <16>; 2691 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2693 interrupt-names = "uplow", "critical"; 2694 #thermal-sensor-cells = <1>; 2695 }; 2696 2697 tsens1: thermal-sensor@c265000 { 2698 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 2699 reg = <0 0x0c265000 0 0x1000>, /* TM */ 2700 <0 0x0c223000 0 0x1000>; /* SROT */ 2701 #qcom,sensors = <16>; 2702 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2704 interrupt-names = "uplow", "critical"; 2705 #thermal-sensor-cells = <1>; 2706 }; 2707 2708 aoss_qmp: power-controller@c300000 { 2709 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 2710 reg = <0 0x0c300000 0 0x400>; 2711 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2712 IRQ_TYPE_EDGE_RISING>; 2713 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2714 2715 #clock-cells = <0>; 2716 }; 2717 2718 ipcc: mailbox@ed18000 { 2719 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 2720 reg = <0 0x0ed18000 0 0x1000>; 2721 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2722 interrupt-controller; 2723 #interrupt-cells = <3>; 2724 #mbox-cells = <2>; 2725 }; 2726 2727 tlmm: pinctrl@f100000 { 2728 compatible = "qcom,sm8450-tlmm"; 2729 reg = <0 0x0f100000 0 0x300000>; 2730 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2731 gpio-controller; 2732 #gpio-cells = <2>; 2733 interrupt-controller; 2734 #interrupt-cells = <2>; 2735 gpio-ranges = <&tlmm 0 0 211>; 2736 wakeup-parent = <&pdc>; 2737 2738 sdc2_default_state: sdc2-default-state { 2739 clk-pins { 2740 pins = "sdc2_clk"; 2741 drive-strength = <16>; 2742 bias-disable; 2743 }; 2744 2745 cmd-pins { 2746 pins = "sdc2_cmd"; 2747 drive-strength = <16>; 2748 bias-pull-up; 2749 }; 2750 2751 data-pins { 2752 pins = "sdc2_data"; 2753 drive-strength = <16>; 2754 bias-pull-up; 2755 }; 2756 }; 2757 2758 sdc2_sleep_state: sdc2-sleep-state { 2759 clk-pins { 2760 pins = "sdc2_clk"; 2761 drive-strength = <2>; 2762 bias-disable; 2763 }; 2764 2765 cmd-pins { 2766 pins = "sdc2_cmd"; 2767 drive-strength = <2>; 2768 bias-pull-up; 2769 }; 2770 2771 data-pins { 2772 pins = "sdc2_data"; 2773 drive-strength = <2>; 2774 bias-pull-up; 2775 }; 2776 }; 2777 2778 cci0_default: cci0-default-state { 2779 /* SDA, SCL */ 2780 pins = "gpio110", "gpio111"; 2781 function = "cci_i2c"; 2782 drive-strength = <2>; 2783 bias-pull-up; 2784 }; 2785 2786 cci0_sleep: cci0-sleep-state { 2787 /* SDA, SCL */ 2788 pins = "gpio110", "gpio111"; 2789 function = "cci_i2c"; 2790 drive-strength = <2>; 2791 bias-pull-down; 2792 }; 2793 2794 cci1_default: cci1-default-state { 2795 /* SDA, SCL */ 2796 pins = "gpio112", "gpio113"; 2797 function = "cci_i2c"; 2798 drive-strength = <2>; 2799 bias-pull-up; 2800 }; 2801 2802 cci1_sleep: cci1-sleep-state { 2803 /* SDA, SCL */ 2804 pins = "gpio112", "gpio113"; 2805 function = "cci_i2c"; 2806 drive-strength = <2>; 2807 bias-pull-down; 2808 }; 2809 2810 cci2_default: cci2-default-state { 2811 /* SDA, SCL */ 2812 pins = "gpio114", "gpio115"; 2813 function = "cci_i2c"; 2814 drive-strength = <2>; 2815 bias-pull-up; 2816 }; 2817 2818 cci2_sleep: cci2-sleep-state { 2819 /* SDA, SCL */ 2820 pins = "gpio114", "gpio115"; 2821 function = "cci_i2c"; 2822 drive-strength = <2>; 2823 bias-pull-down; 2824 }; 2825 2826 cci3_default: cci3-default-state { 2827 /* SDA, SCL */ 2828 pins = "gpio208", "gpio209"; 2829 function = "cci_i2c"; 2830 drive-strength = <2>; 2831 bias-pull-up; 2832 }; 2833 2834 cci3_sleep: cci3-sleep-state { 2835 /* SDA, SCL */ 2836 pins = "gpio208", "gpio209"; 2837 function = "cci_i2c"; 2838 drive-strength = <2>; 2839 bias-pull-down; 2840 }; 2841 2842 pcie0_default_state: pcie0-default-state { 2843 perst-pins { 2844 pins = "gpio94"; 2845 function = "gpio"; 2846 drive-strength = <2>; 2847 bias-pull-down; 2848 }; 2849 2850 clkreq-pins { 2851 pins = "gpio95"; 2852 function = "pcie0_clkreqn"; 2853 drive-strength = <2>; 2854 bias-pull-up; 2855 }; 2856 2857 wake-pins { 2858 pins = "gpio96"; 2859 function = "gpio"; 2860 drive-strength = <2>; 2861 bias-pull-up; 2862 }; 2863 }; 2864 2865 pcie1_default_state: pcie1-default-state { 2866 perst-pins { 2867 pins = "gpio97"; 2868 function = "gpio"; 2869 drive-strength = <2>; 2870 bias-pull-down; 2871 }; 2872 2873 clkreq-pins { 2874 pins = "gpio98"; 2875 function = "pcie1_clkreqn"; 2876 drive-strength = <2>; 2877 bias-pull-up; 2878 }; 2879 2880 wake-pins { 2881 pins = "gpio99"; 2882 function = "gpio"; 2883 drive-strength = <2>; 2884 bias-pull-up; 2885 }; 2886 }; 2887 2888 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2889 pins = "gpio0", "gpio1"; 2890 function = "qup0"; 2891 }; 2892 2893 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2894 pins = "gpio4", "gpio5"; 2895 function = "qup1"; 2896 }; 2897 2898 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2899 pins = "gpio8", "gpio9"; 2900 function = "qup2"; 2901 }; 2902 2903 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2904 pins = "gpio12", "gpio13"; 2905 function = "qup3"; 2906 }; 2907 2908 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2909 pins = "gpio16", "gpio17"; 2910 function = "qup4"; 2911 }; 2912 2913 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2914 pins = "gpio206", "gpio207"; 2915 function = "qup5"; 2916 }; 2917 2918 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2919 pins = "gpio20", "gpio21"; 2920 function = "qup6"; 2921 }; 2922 2923 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2924 pins = "gpio28", "gpio29"; 2925 function = "qup8"; 2926 }; 2927 2928 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2929 pins = "gpio32", "gpio33"; 2930 function = "qup9"; 2931 }; 2932 2933 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2934 pins = "gpio36", "gpio37"; 2935 function = "qup10"; 2936 }; 2937 2938 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2939 pins = "gpio40", "gpio41"; 2940 function = "qup11"; 2941 }; 2942 2943 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2944 pins = "gpio44", "gpio45"; 2945 function = "qup12"; 2946 }; 2947 2948 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2949 pins = "gpio48", "gpio49"; 2950 function = "qup13"; 2951 drive-strength = <2>; 2952 bias-pull-up; 2953 }; 2954 2955 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 2956 pins = "gpio52", "gpio53"; 2957 function = "qup14"; 2958 drive-strength = <2>; 2959 bias-pull-up; 2960 }; 2961 2962 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2963 pins = "gpio56", "gpio57"; 2964 function = "qup15"; 2965 }; 2966 2967 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 2968 pins = "gpio60", "gpio61"; 2969 function = "qup16"; 2970 }; 2971 2972 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 2973 pins = "gpio64", "gpio65"; 2974 function = "qup17"; 2975 }; 2976 2977 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 2978 pins = "gpio68", "gpio69"; 2979 function = "qup18"; 2980 }; 2981 2982 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 2983 pins = "gpio72", "gpio73"; 2984 function = "qup19"; 2985 }; 2986 2987 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 2988 pins = "gpio76", "gpio77"; 2989 function = "qup20"; 2990 }; 2991 2992 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 2993 pins = "gpio80", "gpio81"; 2994 function = "qup21"; 2995 }; 2996 2997 qup_spi0_cs: qup-spi0-cs-state { 2998 pins = "gpio3"; 2999 function = "qup0"; 3000 }; 3001 3002 qup_spi0_data_clk: qup-spi0-data-clk-state { 3003 pins = "gpio0", "gpio1", "gpio2"; 3004 function = "qup0"; 3005 }; 3006 3007 qup_spi1_cs: qup-spi1-cs-state { 3008 pins = "gpio7"; 3009 function = "qup1"; 3010 }; 3011 3012 qup_spi1_data_clk: qup-spi1-data-clk-state { 3013 pins = "gpio4", "gpio5", "gpio6"; 3014 function = "qup1"; 3015 }; 3016 3017 qup_spi2_cs: qup-spi2-cs-state { 3018 pins = "gpio11"; 3019 function = "qup2"; 3020 }; 3021 3022 qup_spi2_data_clk: qup-spi2-data-clk-state { 3023 pins = "gpio8", "gpio9", "gpio10"; 3024 function = "qup2"; 3025 }; 3026 3027 qup_spi3_cs: qup-spi3-cs-state { 3028 pins = "gpio15"; 3029 function = "qup3"; 3030 }; 3031 3032 qup_spi3_data_clk: qup-spi3-data-clk-state { 3033 pins = "gpio12", "gpio13", "gpio14"; 3034 function = "qup3"; 3035 }; 3036 3037 qup_spi4_cs: qup-spi4-cs-state { 3038 pins = "gpio19"; 3039 function = "qup4"; 3040 drive-strength = <6>; 3041 bias-disable; 3042 }; 3043 3044 qup_spi4_data_clk: qup-spi4-data-clk-state { 3045 pins = "gpio16", "gpio17", "gpio18"; 3046 function = "qup4"; 3047 }; 3048 3049 qup_spi5_cs: qup-spi5-cs-state { 3050 pins = "gpio85"; 3051 function = "qup5"; 3052 }; 3053 3054 qup_spi5_data_clk: qup-spi5-data-clk-state { 3055 pins = "gpio206", "gpio207", "gpio84"; 3056 function = "qup5"; 3057 }; 3058 3059 qup_spi6_cs: qup-spi6-cs-state { 3060 pins = "gpio23"; 3061 function = "qup6"; 3062 }; 3063 3064 qup_spi6_data_clk: qup-spi6-data-clk-state { 3065 pins = "gpio20", "gpio21", "gpio22"; 3066 function = "qup6"; 3067 }; 3068 3069 qup_spi8_cs: qup-spi8-cs-state { 3070 pins = "gpio31"; 3071 function = "qup8"; 3072 }; 3073 3074 qup_spi8_data_clk: qup-spi8-data-clk-state { 3075 pins = "gpio28", "gpio29", "gpio30"; 3076 function = "qup8"; 3077 }; 3078 3079 qup_spi9_cs: qup-spi9-cs-state { 3080 pins = "gpio35"; 3081 function = "qup9"; 3082 }; 3083 3084 qup_spi9_data_clk: qup-spi9-data-clk-state { 3085 pins = "gpio32", "gpio33", "gpio34"; 3086 function = "qup9"; 3087 }; 3088 3089 qup_spi10_cs: qup-spi10-cs-state { 3090 pins = "gpio39"; 3091 function = "qup10"; 3092 }; 3093 3094 qup_spi10_data_clk: qup-spi10-data-clk-state { 3095 pins = "gpio36", "gpio37", "gpio38"; 3096 function = "qup10"; 3097 }; 3098 3099 qup_spi11_cs: qup-spi11-cs-state { 3100 pins = "gpio43"; 3101 function = "qup11"; 3102 }; 3103 3104 qup_spi11_data_clk: qup-spi11-data-clk-state { 3105 pins = "gpio40", "gpio41", "gpio42"; 3106 function = "qup11"; 3107 }; 3108 3109 qup_spi12_cs: qup-spi12-cs-state { 3110 pins = "gpio47"; 3111 function = "qup12"; 3112 }; 3113 3114 qup_spi12_data_clk: qup-spi12-data-clk-state { 3115 pins = "gpio44", "gpio45", "gpio46"; 3116 function = "qup12"; 3117 }; 3118 3119 qup_spi13_cs: qup-spi13-cs-state { 3120 pins = "gpio51"; 3121 function = "qup13"; 3122 }; 3123 3124 qup_spi13_data_clk: qup-spi13-data-clk-state { 3125 pins = "gpio48", "gpio49", "gpio50"; 3126 function = "qup13"; 3127 }; 3128 3129 qup_spi14_cs: qup-spi14-cs-state { 3130 pins = "gpio55"; 3131 function = "qup14"; 3132 }; 3133 3134 qup_spi14_data_clk: qup-spi14-data-clk-state { 3135 pins = "gpio52", "gpio53", "gpio54"; 3136 function = "qup14"; 3137 }; 3138 3139 qup_spi15_cs: qup-spi15-cs-state { 3140 pins = "gpio59"; 3141 function = "qup15"; 3142 }; 3143 3144 qup_spi15_data_clk: qup-spi15-data-clk-state { 3145 pins = "gpio56", "gpio57", "gpio58"; 3146 function = "qup15"; 3147 }; 3148 3149 qup_spi16_cs: qup-spi16-cs-state { 3150 pins = "gpio63"; 3151 function = "qup16"; 3152 }; 3153 3154 qup_spi16_data_clk: qup-spi16-data-clk-state { 3155 pins = "gpio60", "gpio61", "gpio62"; 3156 function = "qup16"; 3157 }; 3158 3159 qup_spi17_cs: qup-spi17-cs-state { 3160 pins = "gpio67"; 3161 function = "qup17"; 3162 }; 3163 3164 qup_spi17_data_clk: qup-spi17-data-clk-state { 3165 pins = "gpio64", "gpio65", "gpio66"; 3166 function = "qup17"; 3167 }; 3168 3169 qup_spi18_cs: qup-spi18-cs-state { 3170 pins = "gpio71"; 3171 function = "qup18"; 3172 drive-strength = <6>; 3173 bias-disable; 3174 }; 3175 3176 qup_spi18_data_clk: qup-spi18-data-clk-state { 3177 pins = "gpio68", "gpio69", "gpio70"; 3178 function = "qup18"; 3179 drive-strength = <6>; 3180 bias-disable; 3181 }; 3182 3183 qup_spi19_cs: qup-spi19-cs-state { 3184 pins = "gpio75"; 3185 function = "qup19"; 3186 drive-strength = <6>; 3187 bias-disable; 3188 }; 3189 3190 qup_spi19_data_clk: qup-spi19-data-clk-state { 3191 pins = "gpio72", "gpio73", "gpio74"; 3192 function = "qup19"; 3193 drive-strength = <6>; 3194 bias-disable; 3195 }; 3196 3197 qup_spi20_cs: qup-spi20-cs-state { 3198 pins = "gpio79"; 3199 function = "qup20"; 3200 }; 3201 3202 qup_spi20_data_clk: qup-spi20-data-clk-state { 3203 pins = "gpio76", "gpio77", "gpio78"; 3204 function = "qup20"; 3205 }; 3206 3207 qup_spi21_cs: qup-spi21-cs-state { 3208 pins = "gpio83"; 3209 function = "qup21"; 3210 }; 3211 3212 qup_spi21_data_clk: qup-spi21-data-clk-state { 3213 pins = "gpio80", "gpio81", "gpio82"; 3214 function = "qup21"; 3215 }; 3216 3217 qup_uart7_rx: qup-uart7-rx-state { 3218 pins = "gpio26"; 3219 function = "qup7"; 3220 drive-strength = <2>; 3221 bias-disable; 3222 }; 3223 3224 qup_uart7_tx: qup-uart7-tx-state { 3225 pins = "gpio27"; 3226 function = "qup7"; 3227 drive-strength = <2>; 3228 bias-disable; 3229 }; 3230 3231 qup_uart20_default: qup-uart20-default-state { 3232 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3233 function = "qup20"; 3234 }; 3235 3236 }; 3237 3238 lpass_tlmm: pinctrl@3440000{ 3239 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3240 reg = <0 0x3440000 0x0 0x20000>, 3241 <0 0x34d0000 0x0 0x10000>; 3242 gpio-controller; 3243 #gpio-cells = <2>; 3244 gpio-ranges = <&lpass_tlmm 0 0 23>; 3245 3246 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3247 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3248 clock-names = "core", "audio"; 3249 3250 tx_swr_active: tx-swr-active-state { 3251 clk-pins { 3252 pins = "gpio0"; 3253 function = "swr_tx_clk"; 3254 drive-strength = <2>; 3255 slew-rate = <1>; 3256 bias-disable; 3257 }; 3258 3259 data-pins { 3260 pins = "gpio1", "gpio2", "gpio14"; 3261 function = "swr_tx_data"; 3262 drive-strength = <2>; 3263 slew-rate = <1>; 3264 bias-bus-hold; 3265 }; 3266 }; 3267 3268 rx_swr_active: rx-swr-active-state { 3269 clk-pins { 3270 pins = "gpio3"; 3271 function = "swr_rx_clk"; 3272 drive-strength = <2>; 3273 slew-rate = <1>; 3274 bias-disable; 3275 }; 3276 3277 data-pins { 3278 pins = "gpio4", "gpio5"; 3279 function = "swr_rx_data"; 3280 drive-strength = <2>; 3281 slew-rate = <1>; 3282 bias-bus-hold; 3283 }; 3284 }; 3285 3286 dmic01_default: dmic01-default-state { 3287 clk-pins { 3288 pins = "gpio6"; 3289 function = "dmic1_clk"; 3290 drive-strength = <8>; 3291 output-high; 3292 }; 3293 3294 data-pins { 3295 pins = "gpio7"; 3296 function = "dmic1_data"; 3297 drive-strength = <8>; 3298 input-enable; 3299 }; 3300 }; 3301 3302 dmic02_default: dmic02-default-state { 3303 clk-pins { 3304 pins = "gpio8"; 3305 function = "dmic2_clk"; 3306 drive-strength = <8>; 3307 output-high; 3308 }; 3309 3310 data-pins { 3311 pins = "gpio9"; 3312 function = "dmic2_data"; 3313 drive-strength = <8>; 3314 input-enable; 3315 }; 3316 }; 3317 3318 wsa_swr_active: wsa-swr-active-state { 3319 clk-pins { 3320 pins = "gpio10"; 3321 function = "wsa_swr_clk"; 3322 drive-strength = <2>; 3323 slew-rate = <1>; 3324 bias-disable; 3325 }; 3326 3327 data-pins { 3328 pins = "gpio11"; 3329 function = "wsa_swr_data"; 3330 drive-strength = <2>; 3331 slew-rate = <1>; 3332 bias-bus-hold; 3333 }; 3334 }; 3335 3336 wsa2_swr_active: wsa2-swr-active-state { 3337 clk-pins { 3338 pins = "gpio15"; 3339 function = "wsa2_swr_clk"; 3340 drive-strength = <2>; 3341 slew-rate = <1>; 3342 bias-disable; 3343 }; 3344 3345 data-pins { 3346 pins = "gpio16"; 3347 function = "wsa2_swr_data"; 3348 drive-strength = <2>; 3349 slew-rate = <1>; 3350 bias-bus-hold; 3351 }; 3352 }; 3353 }; 3354 3355 apps_smmu: iommu@15000000 { 3356 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3357 reg = <0 0x15000000 0 0x100000>; 3358 #iommu-cells = <2>; 3359 #global-interrupts = <1>; 3360 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3457 }; 3458 3459 intc: interrupt-controller@17100000 { 3460 compatible = "arm,gic-v3"; 3461 #interrupt-cells = <3>; 3462 interrupt-controller; 3463 #redistributor-regions = <1>; 3464 redistributor-stride = <0x0 0x40000>; 3465 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3466 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3467 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3468 #address-cells = <2>; 3469 #size-cells = <2>; 3470 ranges; 3471 3472 gic_its: msi-controller@17140000 { 3473 compatible = "arm,gic-v3-its"; 3474 reg = <0x0 0x17140000 0x0 0x20000>; 3475 msi-controller; 3476 #msi-cells = <1>; 3477 }; 3478 }; 3479 3480 timer@17420000 { 3481 compatible = "arm,armv7-timer-mem"; 3482 #address-cells = <1>; 3483 #size-cells = <1>; 3484 ranges = <0 0 0 0x20000000>; 3485 reg = <0x0 0x17420000 0x0 0x1000>; 3486 clock-frequency = <19200000>; 3487 3488 frame@17421000 { 3489 frame-number = <0>; 3490 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3492 reg = <0x17421000 0x1000>, 3493 <0x17422000 0x1000>; 3494 }; 3495 3496 frame@17423000 { 3497 frame-number = <1>; 3498 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3499 reg = <0x17423000 0x1000>; 3500 status = "disabled"; 3501 }; 3502 3503 frame@17425000 { 3504 frame-number = <2>; 3505 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3506 reg = <0x17425000 0x1000>; 3507 status = "disabled"; 3508 }; 3509 3510 frame@17427000 { 3511 frame-number = <3>; 3512 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3513 reg = <0x17427000 0x1000>; 3514 status = "disabled"; 3515 }; 3516 3517 frame@17429000 { 3518 frame-number = <4>; 3519 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3520 reg = <0x17429000 0x1000>; 3521 status = "disabled"; 3522 }; 3523 3524 frame@1742b000 { 3525 frame-number = <5>; 3526 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3527 reg = <0x1742b000 0x1000>; 3528 status = "disabled"; 3529 }; 3530 3531 frame@1742d000 { 3532 frame-number = <6>; 3533 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3534 reg = <0x1742d000 0x1000>; 3535 status = "disabled"; 3536 }; 3537 }; 3538 3539 apps_rsc: rsc@17a00000 { 3540 label = "apps_rsc"; 3541 compatible = "qcom,rpmh-rsc"; 3542 reg = <0x0 0x17a00000 0x0 0x10000>, 3543 <0x0 0x17a10000 0x0 0x10000>, 3544 <0x0 0x17a20000 0x0 0x10000>, 3545 <0x0 0x17a30000 0x0 0x10000>; 3546 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3547 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3550 qcom,tcs-offset = <0xd00>; 3551 qcom,drv-id = <2>; 3552 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3553 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3554 power-domains = <&CLUSTER_PD>; 3555 3556 apps_bcm_voter: bcm-voter { 3557 compatible = "qcom,bcm-voter"; 3558 }; 3559 3560 rpmhcc: clock-controller { 3561 compatible = "qcom,sm8450-rpmh-clk"; 3562 #clock-cells = <1>; 3563 clock-names = "xo"; 3564 clocks = <&xo_board>; 3565 }; 3566 3567 rpmhpd: power-controller { 3568 compatible = "qcom,sm8450-rpmhpd"; 3569 #power-domain-cells = <1>; 3570 operating-points-v2 = <&rpmhpd_opp_table>; 3571 3572 rpmhpd_opp_table: opp-table { 3573 compatible = "operating-points-v2"; 3574 3575 rpmhpd_opp_ret: opp1 { 3576 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3577 }; 3578 3579 rpmhpd_opp_min_svs: opp2 { 3580 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3581 }; 3582 3583 rpmhpd_opp_low_svs: opp3 { 3584 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3585 }; 3586 3587 rpmhpd_opp_svs: opp4 { 3588 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3589 }; 3590 3591 rpmhpd_opp_svs_l1: opp5 { 3592 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3593 }; 3594 3595 rpmhpd_opp_nom: opp6 { 3596 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3597 }; 3598 3599 rpmhpd_opp_nom_l1: opp7 { 3600 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3601 }; 3602 3603 rpmhpd_opp_nom_l2: opp8 { 3604 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3605 }; 3606 3607 rpmhpd_opp_turbo: opp9 { 3608 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3609 }; 3610 3611 rpmhpd_opp_turbo_l1: opp10 { 3612 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3613 }; 3614 }; 3615 }; 3616 }; 3617 3618 cpufreq_hw: cpufreq@17d91000 { 3619 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 3620 reg = <0 0x17d91000 0 0x1000>, 3621 <0 0x17d92000 0 0x1000>, 3622 <0 0x17d93000 0 0x1000>; 3623 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3624 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3625 clock-names = "xo", "alternate"; 3626 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3629 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3630 #freq-domain-cells = <1>; 3631 #clock-cells = <1>; 3632 }; 3633 3634 gem_noc: interconnect@19100000 { 3635 compatible = "qcom,sm8450-gem-noc"; 3636 reg = <0 0x19100000 0 0xbb800>; 3637 #interconnect-cells = <2>; 3638 qcom,bcm-voters = <&apps_bcm_voter>; 3639 }; 3640 3641 system-cache-controller@19200000 { 3642 compatible = "qcom,sm8450-llcc"; 3643 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; 3644 reg-names = "llcc_base", "llcc_broadcast_base"; 3645 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3646 }; 3647 3648 ufs_mem_hc: ufshc@1d84000 { 3649 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 3650 "jedec,ufs-2.0"; 3651 reg = <0 0x01d84000 0 0x3000>, 3652 <0 0x01d88000 0 0x8000>; 3653 reg-names = "std", "ice"; 3654 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3655 phys = <&ufs_mem_phy_lanes>; 3656 phy-names = "ufsphy"; 3657 lanes-per-direction = <2>; 3658 #reset-cells = <1>; 3659 resets = <&gcc GCC_UFS_PHY_BCR>; 3660 reset-names = "rst"; 3661 3662 power-domains = <&gcc UFS_PHY_GDSC>; 3663 3664 iommus = <&apps_smmu 0xe0 0x0>; 3665 3666 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 3667 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 3668 interconnect-names = "ufs-ddr", "cpu-ufs"; 3669 clock-names = 3670 "core_clk", 3671 "bus_aggr_clk", 3672 "iface_clk", 3673 "core_clk_unipro", 3674 "ref_clk", 3675 "tx_lane0_sync_clk", 3676 "rx_lane0_sync_clk", 3677 "rx_lane1_sync_clk", 3678 "ice_core_clk"; 3679 clocks = 3680 <&gcc GCC_UFS_PHY_AXI_CLK>, 3681 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3682 <&gcc GCC_UFS_PHY_AHB_CLK>, 3683 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3684 <&rpmhcc RPMH_CXO_CLK>, 3685 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3686 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3687 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 3688 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 3689 freq-table-hz = 3690 <75000000 300000000>, 3691 <0 0>, 3692 <0 0>, 3693 <75000000 300000000>, 3694 <75000000 300000000>, 3695 <0 0>, 3696 <0 0>, 3697 <0 0>, 3698 <75000000 300000000>; 3699 status = "disabled"; 3700 }; 3701 3702 ufs_mem_phy: phy@1d87000 { 3703 compatible = "qcom,sm8450-qmp-ufs-phy"; 3704 reg = <0 0x01d87000 0 0x1c4>; 3705 #address-cells = <2>; 3706 #size-cells = <2>; 3707 ranges; 3708 clock-names = "ref", "ref_aux", "qref"; 3709 clocks = <&rpmhcc RPMH_CXO_CLK>, 3710 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3711 <&gcc GCC_UFS_0_CLKREF_EN>; 3712 3713 resets = <&ufs_mem_hc 0>; 3714 reset-names = "ufsphy"; 3715 status = "disabled"; 3716 3717 ufs_mem_phy_lanes: phy@1d87400 { 3718 reg = <0 0x01d87400 0 0x188>, 3719 <0 0x01d87600 0 0x200>, 3720 <0 0x01d87c00 0 0x200>, 3721 <0 0x01d87800 0 0x188>, 3722 <0 0x01d87a00 0 0x200>; 3723 #phy-cells = <0>; 3724 }; 3725 }; 3726 3727 sdhc_2: mmc@8804000 { 3728 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 3729 reg = <0 0x08804000 0 0x1000>; 3730 3731 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3733 interrupt-names = "hc_irq", "pwr_irq"; 3734 3735 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3736 <&gcc GCC_SDCC2_APPS_CLK>, 3737 <&rpmhcc RPMH_CXO_CLK>; 3738 clock-names = "iface", "core", "xo"; 3739 resets = <&gcc GCC_SDCC2_BCR>; 3740 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3741 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3742 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3743 iommus = <&apps_smmu 0x4a0 0x0>; 3744 power-domains = <&rpmhpd SM8450_CX>; 3745 operating-points-v2 = <&sdhc2_opp_table>; 3746 bus-width = <4>; 3747 dma-coherent; 3748 3749 /* Forbid SDR104/SDR50 - broken hw! */ 3750 sdhci-caps-mask = <0x3 0x0>; 3751 3752 status = "disabled"; 3753 3754 sdhc2_opp_table: opp-table { 3755 compatible = "operating-points-v2"; 3756 3757 opp-100000000 { 3758 opp-hz = /bits/ 64 <100000000>; 3759 required-opps = <&rpmhpd_opp_low_svs>; 3760 }; 3761 3762 opp-202000000 { 3763 opp-hz = /bits/ 64 <202000000>; 3764 required-opps = <&rpmhpd_opp_svs_l1>; 3765 }; 3766 }; 3767 }; 3768 3769 usb_1: usb@a6f8800 { 3770 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 3771 reg = <0 0x0a6f8800 0 0x400>; 3772 status = "disabled"; 3773 #address-cells = <2>; 3774 #size-cells = <2>; 3775 ranges; 3776 3777 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3778 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3779 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3780 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3781 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3782 <&gcc GCC_USB3_0_CLKREF_EN>; 3783 clock-names = "cfg_noc", 3784 "core", 3785 "iface", 3786 "sleep", 3787 "mock_utmi", 3788 "xo"; 3789 3790 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3791 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3792 assigned-clock-rates = <19200000>, <200000000>; 3793 3794 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3795 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3796 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3797 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3798 interrupt-names = "hs_phy_irq", 3799 "ss_phy_irq", 3800 "dm_hs_phy_irq", 3801 "dp_hs_phy_irq"; 3802 3803 power-domains = <&gcc USB30_PRIM_GDSC>; 3804 3805 resets = <&gcc GCC_USB30_PRIM_BCR>; 3806 3807 usb_1_dwc3: usb@a600000 { 3808 compatible = "snps,dwc3"; 3809 reg = <0 0x0a600000 0 0xcd00>; 3810 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3811 iommus = <&apps_smmu 0x0 0x0>; 3812 snps,dis_u2_susphy_quirk; 3813 snps,dis_enblslpm_quirk; 3814 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3815 phy-names = "usb2-phy", "usb3-phy"; 3816 }; 3817 }; 3818 3819 nsp_noc: interconnect@320c0000 { 3820 compatible = "qcom,sm8450-nsp-noc"; 3821 reg = <0 0x320c0000 0 0x10000>; 3822 #interconnect-cells = <2>; 3823 qcom,bcm-voters = <&apps_bcm_voter>; 3824 }; 3825 3826 lpass_ag_noc: interconnect@3c40000 { 3827 compatible = "qcom,sm8450-lpass-ag-noc"; 3828 reg = <0 0x3c40000 0 0x17200>; 3829 #interconnect-cells = <2>; 3830 qcom,bcm-voters = <&apps_bcm_voter>; 3831 }; 3832 }; 3833 3834 sound: sound { 3835 }; 3836 3837 thermal-zones { 3838 aoss0-thermal { 3839 polling-delay-passive = <0>; 3840 polling-delay = <0>; 3841 thermal-sensors = <&tsens0 0>; 3842 3843 trips { 3844 thermal-engine-config { 3845 temperature = <125000>; 3846 hysteresis = <1000>; 3847 type = "passive"; 3848 }; 3849 3850 reset-mon-cfg { 3851 temperature = <115000>; 3852 hysteresis = <5000>; 3853 type = "passive"; 3854 }; 3855 }; 3856 }; 3857 3858 cpuss0-thermal { 3859 polling-delay-passive = <0>; 3860 polling-delay = <0>; 3861 thermal-sensors = <&tsens0 1>; 3862 3863 trips { 3864 thermal-engine-config { 3865 temperature = <125000>; 3866 hysteresis = <1000>; 3867 type = "passive"; 3868 }; 3869 3870 reset-mon-cfg { 3871 temperature = <115000>; 3872 hysteresis = <5000>; 3873 type = "passive"; 3874 }; 3875 }; 3876 }; 3877 3878 cpuss1-thermal { 3879 polling-delay-passive = <0>; 3880 polling-delay = <0>; 3881 thermal-sensors = <&tsens0 2>; 3882 3883 trips { 3884 thermal-engine-config { 3885 temperature = <125000>; 3886 hysteresis = <1000>; 3887 type = "passive"; 3888 }; 3889 3890 reset-mon-cfg { 3891 temperature = <115000>; 3892 hysteresis = <5000>; 3893 type = "passive"; 3894 }; 3895 }; 3896 }; 3897 3898 cpuss3-thermal { 3899 polling-delay-passive = <0>; 3900 polling-delay = <0>; 3901 thermal-sensors = <&tsens0 3>; 3902 3903 trips { 3904 thermal-engine-config { 3905 temperature = <125000>; 3906 hysteresis = <1000>; 3907 type = "passive"; 3908 }; 3909 3910 reset-mon-cfg { 3911 temperature = <115000>; 3912 hysteresis = <5000>; 3913 type = "passive"; 3914 }; 3915 }; 3916 }; 3917 3918 cpuss4-thermal { 3919 polling-delay-passive = <0>; 3920 polling-delay = <0>; 3921 thermal-sensors = <&tsens0 4>; 3922 3923 trips { 3924 thermal-engine-config { 3925 temperature = <125000>; 3926 hysteresis = <1000>; 3927 type = "passive"; 3928 }; 3929 3930 reset-mon-cfg { 3931 temperature = <115000>; 3932 hysteresis = <5000>; 3933 type = "passive"; 3934 }; 3935 }; 3936 }; 3937 3938 cpu4-top-thermal { 3939 polling-delay-passive = <0>; 3940 polling-delay = <0>; 3941 thermal-sensors = <&tsens0 5>; 3942 3943 trips { 3944 cpu4_top_alert0: trip-point0 { 3945 temperature = <90000>; 3946 hysteresis = <2000>; 3947 type = "passive"; 3948 }; 3949 3950 cpu4_top_alert1: trip-point1 { 3951 temperature = <95000>; 3952 hysteresis = <2000>; 3953 type = "passive"; 3954 }; 3955 3956 cpu4_top_crit: cpu_crit { 3957 temperature = <110000>; 3958 hysteresis = <1000>; 3959 type = "critical"; 3960 }; 3961 }; 3962 }; 3963 3964 cpu4-bottom-thermal { 3965 polling-delay-passive = <0>; 3966 polling-delay = <0>; 3967 thermal-sensors = <&tsens0 6>; 3968 3969 trips { 3970 cpu4_bottom_alert0: trip-point0 { 3971 temperature = <90000>; 3972 hysteresis = <2000>; 3973 type = "passive"; 3974 }; 3975 3976 cpu4_bottom_alert1: trip-point1 { 3977 temperature = <95000>; 3978 hysteresis = <2000>; 3979 type = "passive"; 3980 }; 3981 3982 cpu4_bottom_crit: cpu_crit { 3983 temperature = <110000>; 3984 hysteresis = <1000>; 3985 type = "critical"; 3986 }; 3987 }; 3988 }; 3989 3990 cpu5-top-thermal { 3991 polling-delay-passive = <0>; 3992 polling-delay = <0>; 3993 thermal-sensors = <&tsens0 7>; 3994 3995 trips { 3996 cpu5_top_alert0: trip-point0 { 3997 temperature = <90000>; 3998 hysteresis = <2000>; 3999 type = "passive"; 4000 }; 4001 4002 cpu5_top_alert1: trip-point1 { 4003 temperature = <95000>; 4004 hysteresis = <2000>; 4005 type = "passive"; 4006 }; 4007 4008 cpu5_top_crit: cpu_crit { 4009 temperature = <110000>; 4010 hysteresis = <1000>; 4011 type = "critical"; 4012 }; 4013 }; 4014 }; 4015 4016 cpu5-bottom-thermal { 4017 polling-delay-passive = <0>; 4018 polling-delay = <0>; 4019 thermal-sensors = <&tsens0 8>; 4020 4021 trips { 4022 cpu5_bottom_alert0: trip-point0 { 4023 temperature = <90000>; 4024 hysteresis = <2000>; 4025 type = "passive"; 4026 }; 4027 4028 cpu5_bottom_alert1: trip-point1 { 4029 temperature = <95000>; 4030 hysteresis = <2000>; 4031 type = "passive"; 4032 }; 4033 4034 cpu5_bottom_crit: cpu_crit { 4035 temperature = <110000>; 4036 hysteresis = <1000>; 4037 type = "critical"; 4038 }; 4039 }; 4040 }; 4041 4042 cpu6-top-thermal { 4043 polling-delay-passive = <0>; 4044 polling-delay = <0>; 4045 thermal-sensors = <&tsens0 9>; 4046 4047 trips { 4048 cpu6_top_alert0: trip-point0 { 4049 temperature = <90000>; 4050 hysteresis = <2000>; 4051 type = "passive"; 4052 }; 4053 4054 cpu6_top_alert1: trip-point1 { 4055 temperature = <95000>; 4056 hysteresis = <2000>; 4057 type = "passive"; 4058 }; 4059 4060 cpu6_top_crit: cpu_crit { 4061 temperature = <110000>; 4062 hysteresis = <1000>; 4063 type = "critical"; 4064 }; 4065 }; 4066 }; 4067 4068 cpu6-bottom-thermal { 4069 polling-delay-passive = <0>; 4070 polling-delay = <0>; 4071 thermal-sensors = <&tsens0 10>; 4072 4073 trips { 4074 cpu6_bottom_alert0: trip-point0 { 4075 temperature = <90000>; 4076 hysteresis = <2000>; 4077 type = "passive"; 4078 }; 4079 4080 cpu6_bottom_alert1: trip-point1 { 4081 temperature = <95000>; 4082 hysteresis = <2000>; 4083 type = "passive"; 4084 }; 4085 4086 cpu6_bottom_crit: cpu_crit { 4087 temperature = <110000>; 4088 hysteresis = <1000>; 4089 type = "critical"; 4090 }; 4091 }; 4092 }; 4093 4094 cpu7-top-thermal { 4095 polling-delay-passive = <0>; 4096 polling-delay = <0>; 4097 thermal-sensors = <&tsens0 11>; 4098 4099 trips { 4100 cpu7_top_alert0: trip-point0 { 4101 temperature = <90000>; 4102 hysteresis = <2000>; 4103 type = "passive"; 4104 }; 4105 4106 cpu7_top_alert1: trip-point1 { 4107 temperature = <95000>; 4108 hysteresis = <2000>; 4109 type = "passive"; 4110 }; 4111 4112 cpu7_top_crit: cpu_crit { 4113 temperature = <110000>; 4114 hysteresis = <1000>; 4115 type = "critical"; 4116 }; 4117 }; 4118 }; 4119 4120 cpu7-middle-thermal { 4121 polling-delay-passive = <0>; 4122 polling-delay = <0>; 4123 thermal-sensors = <&tsens0 12>; 4124 4125 trips { 4126 cpu7_middle_alert0: trip-point0 { 4127 temperature = <90000>; 4128 hysteresis = <2000>; 4129 type = "passive"; 4130 }; 4131 4132 cpu7_middle_alert1: trip-point1 { 4133 temperature = <95000>; 4134 hysteresis = <2000>; 4135 type = "passive"; 4136 }; 4137 4138 cpu7_middle_crit: cpu_crit { 4139 temperature = <110000>; 4140 hysteresis = <1000>; 4141 type = "critical"; 4142 }; 4143 }; 4144 }; 4145 4146 cpu7-bottom-thermal { 4147 polling-delay-passive = <0>; 4148 polling-delay = <0>; 4149 thermal-sensors = <&tsens0 13>; 4150 4151 trips { 4152 cpu7_bottom_alert0: trip-point0 { 4153 temperature = <90000>; 4154 hysteresis = <2000>; 4155 type = "passive"; 4156 }; 4157 4158 cpu7_bottom_alert1: trip-point1 { 4159 temperature = <95000>; 4160 hysteresis = <2000>; 4161 type = "passive"; 4162 }; 4163 4164 cpu7_bottom_crit: cpu_crit { 4165 temperature = <110000>; 4166 hysteresis = <1000>; 4167 type = "critical"; 4168 }; 4169 }; 4170 }; 4171 4172 gpu-top-thermal { 4173 polling-delay-passive = <10>; 4174 polling-delay = <0>; 4175 thermal-sensors = <&tsens0 14>; 4176 4177 trips { 4178 thermal-engine-config { 4179 temperature = <125000>; 4180 hysteresis = <1000>; 4181 type = "passive"; 4182 }; 4183 4184 thermal-hal-config { 4185 temperature = <125000>; 4186 hysteresis = <1000>; 4187 type = "passive"; 4188 }; 4189 4190 reset-mon-cfg { 4191 temperature = <115000>; 4192 hysteresis = <5000>; 4193 type = "passive"; 4194 }; 4195 4196 gpu0_tj_cfg: tj_cfg { 4197 temperature = <95000>; 4198 hysteresis = <5000>; 4199 type = "passive"; 4200 }; 4201 }; 4202 }; 4203 4204 gpu-bottom-thermal { 4205 polling-delay-passive = <10>; 4206 polling-delay = <0>; 4207 thermal-sensors = <&tsens0 15>; 4208 4209 trips { 4210 thermal-engine-config { 4211 temperature = <125000>; 4212 hysteresis = <1000>; 4213 type = "passive"; 4214 }; 4215 4216 thermal-hal-config { 4217 temperature = <125000>; 4218 hysteresis = <1000>; 4219 type = "passive"; 4220 }; 4221 4222 reset-mon-cfg { 4223 temperature = <115000>; 4224 hysteresis = <5000>; 4225 type = "passive"; 4226 }; 4227 4228 gpu1_tj_cfg: tj_cfg { 4229 temperature = <95000>; 4230 hysteresis = <5000>; 4231 type = "passive"; 4232 }; 4233 }; 4234 }; 4235 4236 aoss1-thermal { 4237 polling-delay-passive = <0>; 4238 polling-delay = <0>; 4239 thermal-sensors = <&tsens1 0>; 4240 4241 trips { 4242 thermal-engine-config { 4243 temperature = <125000>; 4244 hysteresis = <1000>; 4245 type = "passive"; 4246 }; 4247 4248 reset-mon-cfg { 4249 temperature = <115000>; 4250 hysteresis = <5000>; 4251 type = "passive"; 4252 }; 4253 }; 4254 }; 4255 4256 cpu0-thermal { 4257 polling-delay-passive = <0>; 4258 polling-delay = <0>; 4259 thermal-sensors = <&tsens1 1>; 4260 4261 trips { 4262 cpu0_alert0: trip-point0 { 4263 temperature = <90000>; 4264 hysteresis = <2000>; 4265 type = "passive"; 4266 }; 4267 4268 cpu0_alert1: trip-point1 { 4269 temperature = <95000>; 4270 hysteresis = <2000>; 4271 type = "passive"; 4272 }; 4273 4274 cpu0_crit: cpu_crit { 4275 temperature = <110000>; 4276 hysteresis = <1000>; 4277 type = "critical"; 4278 }; 4279 }; 4280 }; 4281 4282 cpu1-thermal { 4283 polling-delay-passive = <0>; 4284 polling-delay = <0>; 4285 thermal-sensors = <&tsens1 2>; 4286 4287 trips { 4288 cpu1_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "passive"; 4292 }; 4293 4294 cpu1_alert1: trip-point1 { 4295 temperature = <95000>; 4296 hysteresis = <2000>; 4297 type = "passive"; 4298 }; 4299 4300 cpu1_crit: cpu_crit { 4301 temperature = <110000>; 4302 hysteresis = <1000>; 4303 type = "critical"; 4304 }; 4305 }; 4306 }; 4307 4308 cpu2-thermal { 4309 polling-delay-passive = <0>; 4310 polling-delay = <0>; 4311 thermal-sensors = <&tsens1 3>; 4312 4313 trips { 4314 cpu2_alert0: trip-point0 { 4315 temperature = <90000>; 4316 hysteresis = <2000>; 4317 type = "passive"; 4318 }; 4319 4320 cpu2_alert1: trip-point1 { 4321 temperature = <95000>; 4322 hysteresis = <2000>; 4323 type = "passive"; 4324 }; 4325 4326 cpu2_crit: cpu_crit { 4327 temperature = <110000>; 4328 hysteresis = <1000>; 4329 type = "critical"; 4330 }; 4331 }; 4332 }; 4333 4334 cpu3-thermal { 4335 polling-delay-passive = <0>; 4336 polling-delay = <0>; 4337 thermal-sensors = <&tsens1 4>; 4338 4339 trips { 4340 cpu3_alert0: trip-point0 { 4341 temperature = <90000>; 4342 hysteresis = <2000>; 4343 type = "passive"; 4344 }; 4345 4346 cpu3_alert1: trip-point1 { 4347 temperature = <95000>; 4348 hysteresis = <2000>; 4349 type = "passive"; 4350 }; 4351 4352 cpu3_crit: cpu_crit { 4353 temperature = <110000>; 4354 hysteresis = <1000>; 4355 type = "critical"; 4356 }; 4357 }; 4358 }; 4359 4360 cdsp0-thermal { 4361 polling-delay-passive = <10>; 4362 polling-delay = <0>; 4363 thermal-sensors = <&tsens1 5>; 4364 4365 trips { 4366 thermal-engine-config { 4367 temperature = <125000>; 4368 hysteresis = <1000>; 4369 type = "passive"; 4370 }; 4371 4372 thermal-hal-config { 4373 temperature = <125000>; 4374 hysteresis = <1000>; 4375 type = "passive"; 4376 }; 4377 4378 reset-mon-cfg { 4379 temperature = <115000>; 4380 hysteresis = <5000>; 4381 type = "passive"; 4382 }; 4383 4384 cdsp_0_config: junction-config { 4385 temperature = <95000>; 4386 hysteresis = <5000>; 4387 type = "passive"; 4388 }; 4389 }; 4390 }; 4391 4392 cdsp1-thermal { 4393 polling-delay-passive = <10>; 4394 polling-delay = <0>; 4395 thermal-sensors = <&tsens1 6>; 4396 4397 trips { 4398 thermal-engine-config { 4399 temperature = <125000>; 4400 hysteresis = <1000>; 4401 type = "passive"; 4402 }; 4403 4404 thermal-hal-config { 4405 temperature = <125000>; 4406 hysteresis = <1000>; 4407 type = "passive"; 4408 }; 4409 4410 reset-mon-cfg { 4411 temperature = <115000>; 4412 hysteresis = <5000>; 4413 type = "passive"; 4414 }; 4415 4416 cdsp_1_config: junction-config { 4417 temperature = <95000>; 4418 hysteresis = <5000>; 4419 type = "passive"; 4420 }; 4421 }; 4422 }; 4423 4424 cdsp2-thermal { 4425 polling-delay-passive = <10>; 4426 polling-delay = <0>; 4427 thermal-sensors = <&tsens1 7>; 4428 4429 trips { 4430 thermal-engine-config { 4431 temperature = <125000>; 4432 hysteresis = <1000>; 4433 type = "passive"; 4434 }; 4435 4436 thermal-hal-config { 4437 temperature = <125000>; 4438 hysteresis = <1000>; 4439 type = "passive"; 4440 }; 4441 4442 reset-mon-cfg { 4443 temperature = <115000>; 4444 hysteresis = <5000>; 4445 type = "passive"; 4446 }; 4447 4448 cdsp_2_config: junction-config { 4449 temperature = <95000>; 4450 hysteresis = <5000>; 4451 type = "passive"; 4452 }; 4453 }; 4454 }; 4455 4456 video-thermal { 4457 polling-delay-passive = <0>; 4458 polling-delay = <0>; 4459 thermal-sensors = <&tsens1 8>; 4460 4461 trips { 4462 thermal-engine-config { 4463 temperature = <125000>; 4464 hysteresis = <1000>; 4465 type = "passive"; 4466 }; 4467 4468 reset-mon-cfg { 4469 temperature = <115000>; 4470 hysteresis = <5000>; 4471 type = "passive"; 4472 }; 4473 }; 4474 }; 4475 4476 mem-thermal { 4477 polling-delay-passive = <10>; 4478 polling-delay = <0>; 4479 thermal-sensors = <&tsens1 9>; 4480 4481 trips { 4482 thermal-engine-config { 4483 temperature = <125000>; 4484 hysteresis = <1000>; 4485 type = "passive"; 4486 }; 4487 4488 ddr_config0: ddr0-config { 4489 temperature = <90000>; 4490 hysteresis = <5000>; 4491 type = "passive"; 4492 }; 4493 4494 reset-mon-cfg { 4495 temperature = <115000>; 4496 hysteresis = <5000>; 4497 type = "passive"; 4498 }; 4499 }; 4500 }; 4501 4502 modem0-thermal { 4503 polling-delay-passive = <0>; 4504 polling-delay = <0>; 4505 thermal-sensors = <&tsens1 10>; 4506 4507 trips { 4508 thermal-engine-config { 4509 temperature = <125000>; 4510 hysteresis = <1000>; 4511 type = "passive"; 4512 }; 4513 4514 mdmss0_config0: mdmss0-config0 { 4515 temperature = <102000>; 4516 hysteresis = <3000>; 4517 type = "passive"; 4518 }; 4519 4520 mdmss0_config1: mdmss0-config1 { 4521 temperature = <105000>; 4522 hysteresis = <3000>; 4523 type = "passive"; 4524 }; 4525 4526 reset-mon-cfg { 4527 temperature = <115000>; 4528 hysteresis = <5000>; 4529 type = "passive"; 4530 }; 4531 }; 4532 }; 4533 4534 modem1-thermal { 4535 polling-delay-passive = <0>; 4536 polling-delay = <0>; 4537 thermal-sensors = <&tsens1 11>; 4538 4539 trips { 4540 thermal-engine-config { 4541 temperature = <125000>; 4542 hysteresis = <1000>; 4543 type = "passive"; 4544 }; 4545 4546 mdmss1_config0: mdmss1-config0 { 4547 temperature = <102000>; 4548 hysteresis = <3000>; 4549 type = "passive"; 4550 }; 4551 4552 mdmss1_config1: mdmss1-config1 { 4553 temperature = <105000>; 4554 hysteresis = <3000>; 4555 type = "passive"; 4556 }; 4557 4558 reset-mon-cfg { 4559 temperature = <115000>; 4560 hysteresis = <5000>; 4561 type = "passive"; 4562 }; 4563 }; 4564 }; 4565 4566 modem2-thermal { 4567 polling-delay-passive = <0>; 4568 polling-delay = <0>; 4569 thermal-sensors = <&tsens1 12>; 4570 4571 trips { 4572 thermal-engine-config { 4573 temperature = <125000>; 4574 hysteresis = <1000>; 4575 type = "passive"; 4576 }; 4577 4578 mdmss2_config0: mdmss2-config0 { 4579 temperature = <102000>; 4580 hysteresis = <3000>; 4581 type = "passive"; 4582 }; 4583 4584 mdmss2_config1: mdmss2-config1 { 4585 temperature = <105000>; 4586 hysteresis = <3000>; 4587 type = "passive"; 4588 }; 4589 4590 reset-mon-cfg { 4591 temperature = <115000>; 4592 hysteresis = <5000>; 4593 type = "passive"; 4594 }; 4595 }; 4596 }; 4597 4598 modem3-thermal { 4599 polling-delay-passive = <0>; 4600 polling-delay = <0>; 4601 thermal-sensors = <&tsens1 13>; 4602 4603 trips { 4604 thermal-engine-config { 4605 temperature = <125000>; 4606 hysteresis = <1000>; 4607 type = "passive"; 4608 }; 4609 4610 mdmss3_config0: mdmss3-config0 { 4611 temperature = <102000>; 4612 hysteresis = <3000>; 4613 type = "passive"; 4614 }; 4615 4616 mdmss3_config1: mdmss3-config1 { 4617 temperature = <105000>; 4618 hysteresis = <3000>; 4619 type = "passive"; 4620 }; 4621 4622 reset-mon-cfg { 4623 temperature = <115000>; 4624 hysteresis = <5000>; 4625 type = "passive"; 4626 }; 4627 }; 4628 }; 4629 4630 camera0-thermal { 4631 polling-delay-passive = <0>; 4632 polling-delay = <0>; 4633 thermal-sensors = <&tsens1 14>; 4634 4635 trips { 4636 thermal-engine-config { 4637 temperature = <125000>; 4638 hysteresis = <1000>; 4639 type = "passive"; 4640 }; 4641 4642 reset-mon-cfg { 4643 temperature = <115000>; 4644 hysteresis = <5000>; 4645 type = "passive"; 4646 }; 4647 }; 4648 }; 4649 4650 camera1-thermal { 4651 polling-delay-passive = <0>; 4652 polling-delay = <0>; 4653 thermal-sensors = <&tsens1 15>; 4654 4655 trips { 4656 thermal-engine-config { 4657 temperature = <125000>; 4658 hysteresis = <1000>; 4659 type = "passive"; 4660 }; 4661 4662 reset-mon-cfg { 4663 temperature = <115000>; 4664 hysteresis = <5000>; 4665 type = "passive"; 4666 }; 4667 }; 4668 }; 4669 }; 4670 4671 timer { 4672 compatible = "arm,armv8-timer"; 4673 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4674 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4675 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4676 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4677 clock-frequency = <19200000>; 4678 }; 4679}; 4680