1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/phy/phy-qcom-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/interconnect/qcom,sm8450.h> 17#include <dt-bindings/soc/qcom,gpr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <76800000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 CPU0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo780"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 #cooling-cells = <2>; 58 clocks = <&cpufreq_hw 0>; 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 next-level-cache = <&L3_0>; 63 L3_0: l3-cache { 64 compatible = "cache"; 65 cache-level = <3>; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo780"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 next-level-cache = <&L2_100>; 76 power-domains = <&CPU_PD1>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 #cooling-cells = <2>; 80 clocks = <&cpufreq_hw 0>; 81 L2_100: l2-cache { 82 compatible = "cache"; 83 cache-level = <2>; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo780"; 91 reg = <0x0 0x200>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_200>; 94 power-domains = <&CPU_PD2>; 95 power-domain-names = "psci"; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 #cooling-cells = <2>; 98 clocks = <&cpufreq_hw 0>; 99 L2_200: l2-cache { 100 compatible = "cache"; 101 cache-level = <2>; 102 next-level-cache = <&L3_0>; 103 }; 104 }; 105 106 CPU3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo780"; 109 reg = <0x0 0x300>; 110 enable-method = "psci"; 111 next-level-cache = <&L2_300>; 112 power-domains = <&CPU_PD3>; 113 power-domain-names = "psci"; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 #cooling-cells = <2>; 116 clocks = <&cpufreq_hw 0>; 117 L2_300: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU4: cpu@400 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo780"; 127 reg = <0x0 0x400>; 128 enable-method = "psci"; 129 next-level-cache = <&L2_400>; 130 power-domains = <&CPU_PD4>; 131 power-domain-names = "psci"; 132 qcom,freq-domain = <&cpufreq_hw 1>; 133 #cooling-cells = <2>; 134 clocks = <&cpufreq_hw 1>; 135 L2_400: l2-cache { 136 compatible = "cache"; 137 cache-level = <2>; 138 next-level-cache = <&L3_0>; 139 }; 140 }; 141 142 CPU5: cpu@500 { 143 device_type = "cpu"; 144 compatible = "qcom,kryo780"; 145 reg = <0x0 0x500>; 146 enable-method = "psci"; 147 next-level-cache = <&L2_500>; 148 power-domains = <&CPU_PD5>; 149 power-domain-names = "psci"; 150 qcom,freq-domain = <&cpufreq_hw 1>; 151 #cooling-cells = <2>; 152 clocks = <&cpufreq_hw 1>; 153 L2_500: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU6: cpu@600 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo780"; 163 reg = <0x0 0x600>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_600>; 166 power-domains = <&CPU_PD6>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 #cooling-cells = <2>; 170 clocks = <&cpufreq_hw 1>; 171 L2_600: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo780"; 181 reg = <0x0 0x700>; 182 enable-method = "psci"; 183 next-level-cache = <&L2_700>; 184 power-domains = <&CPU_PD7>; 185 power-domain-names = "psci"; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 #cooling-cells = <2>; 188 clocks = <&cpufreq_hw 2>; 189 L2_700: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 214 core4 { 215 cpu = <&CPU4>; 216 }; 217 218 core5 { 219 cpu = <&CPU5>; 220 }; 221 222 core6 { 223 cpu = <&CPU6>; 224 }; 225 226 core7 { 227 cpu = <&CPU7>; 228 }; 229 }; 230 }; 231 232 idle-states { 233 entry-method = "psci"; 234 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "silver-rail-power-collapse"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <800>; 240 exit-latency-us = <750>; 241 min-residency-us = <4090>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "gold-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <600>; 250 exit-latency-us = <1550>; 251 min-residency-us = <4791>; 252 local-timer-stop; 253 }; 254 }; 255 256 domain-idle-states { 257 CLUSTER_SLEEP_0: cluster-sleep-0 { 258 compatible = "domain-idle-state"; 259 arm,psci-suspend-param = <0x41000044>; 260 entry-latency-us = <1050>; 261 exit-latency-us = <2500>; 262 min-residency-us = <5309>; 263 }; 264 265 CLUSTER_SLEEP_1: cluster-sleep-1 { 266 compatible = "domain-idle-state"; 267 arm,psci-suspend-param = <0x4100c344>; 268 entry-latency-us = <2700>; 269 exit-latency-us = <3500>; 270 min-residency-us = <13959>; 271 }; 272 }; 273 }; 274 275 firmware { 276 scm: scm { 277 compatible = "qcom,scm-sm8450", "qcom,scm"; 278 qcom,dload-mode = <&tcsr 0x13000>; 279 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 280 #reset-cells = <1>; 281 }; 282 }; 283 284 clk_virt: interconnect-0 { 285 compatible = "qcom,sm8450-clk-virt"; 286 #interconnect-cells = <2>; 287 qcom,bcm-voters = <&apps_bcm_voter>; 288 }; 289 290 mc_virt: interconnect-1 { 291 compatible = "qcom,sm8450-mc-virt"; 292 #interconnect-cells = <2>; 293 qcom,bcm-voters = <&apps_bcm_voter>; 294 }; 295 296 memory@a0000000 { 297 device_type = "memory"; 298 /* We expect the bootloader to fill in the size */ 299 reg = <0x0 0xa0000000 0x0 0x0>; 300 }; 301 302 pmu { 303 compatible = "arm,armv8-pmuv3"; 304 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 305 }; 306 307 psci { 308 compatible = "arm,psci-1.0"; 309 method = "smc"; 310 311 CPU_PD0: power-domain-cpu0 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 315 }; 316 317 CPU_PD1: power-domain-cpu1 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 321 }; 322 323 CPU_PD2: power-domain-cpu2 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD3: power-domain-cpu3 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD4: power-domain-cpu4 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&BIG_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD5: power-domain-cpu5 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&BIG_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD6: power-domain-cpu6 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD7: power-domain-cpu7 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CLUSTER_PD: power-domain-cpu-cluster0 { 360 #power-domain-cells = <0>; 361 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 362 }; 363 }; 364 365 qup_opp_table_100mhz: opp-table-qup { 366 compatible = "operating-points-v2"; 367 368 opp-50000000 { 369 opp-hz = /bits/ 64 <50000000>; 370 required-opps = <&rpmhpd_opp_min_svs>; 371 }; 372 373 opp-75000000 { 374 opp-hz = /bits/ 64 <75000000>; 375 required-opps = <&rpmhpd_opp_low_svs>; 376 }; 377 378 opp-100000000 { 379 opp-hz = /bits/ 64 <100000000>; 380 required-opps = <&rpmhpd_opp_svs>; 381 }; 382 }; 383 384 reserved_memory: reserved-memory { 385 #address-cells = <2>; 386 #size-cells = <2>; 387 ranges; 388 389 hyp_mem: memory@80000000 { 390 reg = <0x0 0x80000000 0x0 0x600000>; 391 no-map; 392 }; 393 394 xbl_dt_log_mem: memory@80600000 { 395 reg = <0x0 0x80600000 0x0 0x40000>; 396 no-map; 397 }; 398 399 xbl_ramdump_mem: memory@80640000 { 400 reg = <0x0 0x80640000 0x0 0x180000>; 401 no-map; 402 }; 403 404 xbl_sc_mem: memory@807c0000 { 405 reg = <0x0 0x807c0000 0x0 0x40000>; 406 no-map; 407 }; 408 409 aop_image_mem: memory@80800000 { 410 reg = <0x0 0x80800000 0x0 0x60000>; 411 no-map; 412 }; 413 414 aop_cmd_db_mem: memory@80860000 { 415 compatible = "qcom,cmd-db"; 416 reg = <0x0 0x80860000 0x0 0x20000>; 417 no-map; 418 }; 419 420 aop_config_mem: memory@80880000 { 421 reg = <0x0 0x80880000 0x0 0x20000>; 422 no-map; 423 }; 424 425 tme_crash_dump_mem: memory@808a0000 { 426 reg = <0x0 0x808a0000 0x0 0x40000>; 427 no-map; 428 }; 429 430 tme_log_mem: memory@808e0000 { 431 reg = <0x0 0x808e0000 0x0 0x4000>; 432 no-map; 433 }; 434 435 uefi_log_mem: memory@808e4000 { 436 reg = <0x0 0x808e4000 0x0 0x10000>; 437 no-map; 438 }; 439 440 /* secdata region can be reused by apps */ 441 smem: memory@80900000 { 442 compatible = "qcom,smem"; 443 reg = <0x0 0x80900000 0x0 0x200000>; 444 hwlocks = <&tcsr_mutex 3>; 445 no-map; 446 }; 447 448 cpucp_fw_mem: memory@80b00000 { 449 reg = <0x0 0x80b00000 0x0 0x100000>; 450 no-map; 451 }; 452 453 cdsp_secure_heap: memory@80c00000 { 454 reg = <0x0 0x80c00000 0x0 0x4600000>; 455 no-map; 456 }; 457 458 video_mem: memory@85700000 { 459 reg = <0x0 0x85700000 0x0 0x700000>; 460 no-map; 461 }; 462 463 adsp_mem: memory@85e00000 { 464 reg = <0x0 0x85e00000 0x0 0x2100000>; 465 no-map; 466 }; 467 468 slpi_mem: memory@88000000 { 469 reg = <0x0 0x88000000 0x0 0x1900000>; 470 no-map; 471 }; 472 473 cdsp_mem: memory@89900000 { 474 reg = <0x0 0x89900000 0x0 0x2000000>; 475 no-map; 476 }; 477 478 ipa_fw_mem: memory@8b900000 { 479 reg = <0x0 0x8b900000 0x0 0x10000>; 480 no-map; 481 }; 482 483 ipa_gsi_mem: memory@8b910000 { 484 reg = <0x0 0x8b910000 0x0 0xa000>; 485 no-map; 486 }; 487 488 gpu_micro_code_mem: memory@8b91a000 { 489 reg = <0x0 0x8b91a000 0x0 0x2000>; 490 no-map; 491 }; 492 493 spss_region_mem: memory@8ba00000 { 494 reg = <0x0 0x8ba00000 0x0 0x180000>; 495 no-map; 496 }; 497 498 /* First part of the "SPU secure shared memory" region */ 499 spu_tz_shared_mem: memory@8bb80000 { 500 reg = <0x0 0x8bb80000 0x0 0x60000>; 501 no-map; 502 }; 503 504 /* Second part of the "SPU secure shared memory" region */ 505 spu_modem_shared_mem: memory@8bbe0000 { 506 reg = <0x0 0x8bbe0000 0x0 0x20000>; 507 no-map; 508 }; 509 510 mpss_mem: memory@8bc00000 { 511 reg = <0x0 0x8bc00000 0x0 0x13200000>; 512 no-map; 513 }; 514 515 cvp_mem: memory@9ee00000 { 516 reg = <0x0 0x9ee00000 0x0 0x700000>; 517 no-map; 518 }; 519 520 camera_mem: memory@9f500000 { 521 reg = <0x0 0x9f500000 0x0 0x800000>; 522 no-map; 523 }; 524 525 rmtfs_mem: memory@9fd00000 { 526 compatible = "qcom,rmtfs-mem"; 527 reg = <0x0 0x9fd00000 0x0 0x280000>; 528 no-map; 529 530 qcom,client-id = <1>; 531 qcom,vmid = <15>; 532 }; 533 534 xbl_sc_mem2: memory@a6e00000 { 535 reg = <0x0 0xa6e00000 0x0 0x40000>; 536 no-map; 537 }; 538 539 global_sync_mem: memory@a6f00000 { 540 reg = <0x0 0xa6f00000 0x0 0x100000>; 541 no-map; 542 }; 543 544 /* uefi region can be reused by APPS */ 545 546 /* Linux kernel image is loaded at 0xa0000000 */ 547 548 oem_vm_mem: memory@bb000000 { 549 reg = <0x0 0xbb000000 0x0 0x5000000>; 550 no-map; 551 }; 552 553 mte_mem: memory@c0000000 { 554 reg = <0x0 0xc0000000 0x0 0x20000000>; 555 no-map; 556 }; 557 558 qheebsp_reserved_mem: memory@e0000000 { 559 reg = <0x0 0xe0000000 0x0 0x600000>; 560 no-map; 561 }; 562 563 cpusys_vm_mem: memory@e0600000 { 564 reg = <0x0 0xe0600000 0x0 0x400000>; 565 no-map; 566 }; 567 568 hyp_reserved_mem: memory@e0a00000 { 569 reg = <0x0 0xe0a00000 0x0 0x100000>; 570 no-map; 571 }; 572 573 trust_ui_vm_mem: memory@e0b00000 { 574 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 575 no-map; 576 }; 577 578 trust_ui_vm_qrtr: memory@e55f3000 { 579 reg = <0x0 0xe55f3000 0x0 0x9000>; 580 no-map; 581 }; 582 583 trust_ui_vm_vblk0_ring: memory@e55fc000 { 584 reg = <0x0 0xe55fc000 0x0 0x4000>; 585 no-map; 586 }; 587 588 trust_ui_vm_swiotlb: memory@e5600000 { 589 reg = <0x0 0xe5600000 0x0 0x100000>; 590 no-map; 591 }; 592 593 tz_stat_mem: memory@e8800000 { 594 reg = <0x0 0xe8800000 0x0 0x100000>; 595 no-map; 596 }; 597 598 tags_mem: memory@e8900000 { 599 reg = <0x0 0xe8900000 0x0 0x1200000>; 600 no-map; 601 }; 602 603 qtee_mem: memory@e9b00000 { 604 reg = <0x0 0xe9b00000 0x0 0x500000>; 605 no-map; 606 }; 607 608 trusted_apps_mem: memory@ea000000 { 609 reg = <0x0 0xea000000 0x0 0x3900000>; 610 no-map; 611 }; 612 613 trusted_apps_ext_mem: memory@ed900000 { 614 reg = <0x0 0xed900000 0x0 0x3b00000>; 615 no-map; 616 }; 617 }; 618 619 smp2p-adsp { 620 compatible = "qcom,smp2p"; 621 qcom,smem = <443>, <429>; 622 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 623 IPCC_MPROC_SIGNAL_SMP2P 624 IRQ_TYPE_EDGE_RISING>; 625 mboxes = <&ipcc IPCC_CLIENT_LPASS 626 IPCC_MPROC_SIGNAL_SMP2P>; 627 628 qcom,local-pid = <0>; 629 qcom,remote-pid = <2>; 630 631 smp2p_adsp_out: master-kernel { 632 qcom,entry-name = "master-kernel"; 633 #qcom,smem-state-cells = <1>; 634 }; 635 636 smp2p_adsp_in: slave-kernel { 637 qcom,entry-name = "slave-kernel"; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 }; 641 }; 642 643 smp2p-cdsp { 644 compatible = "qcom,smp2p"; 645 qcom,smem = <94>, <432>; 646 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 647 IPCC_MPROC_SIGNAL_SMP2P 648 IRQ_TYPE_EDGE_RISING>; 649 mboxes = <&ipcc IPCC_CLIENT_CDSP 650 IPCC_MPROC_SIGNAL_SMP2P>; 651 652 qcom,local-pid = <0>; 653 qcom,remote-pid = <5>; 654 655 smp2p_cdsp_out: master-kernel { 656 qcom,entry-name = "master-kernel"; 657 #qcom,smem-state-cells = <1>; 658 }; 659 660 smp2p_cdsp_in: slave-kernel { 661 qcom,entry-name = "slave-kernel"; 662 interrupt-controller; 663 #interrupt-cells = <2>; 664 }; 665 }; 666 667 smp2p-modem { 668 compatible = "qcom,smp2p"; 669 qcom,smem = <435>, <428>; 670 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 671 IPCC_MPROC_SIGNAL_SMP2P 672 IRQ_TYPE_EDGE_RISING>; 673 mboxes = <&ipcc IPCC_CLIENT_MPSS 674 IPCC_MPROC_SIGNAL_SMP2P>; 675 676 qcom,local-pid = <0>; 677 qcom,remote-pid = <1>; 678 679 smp2p_modem_out: master-kernel { 680 qcom,entry-name = "master-kernel"; 681 #qcom,smem-state-cells = <1>; 682 }; 683 684 smp2p_modem_in: slave-kernel { 685 qcom,entry-name = "slave-kernel"; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 690 ipa_smp2p_out: ipa-ap-to-modem { 691 qcom,entry-name = "ipa"; 692 #qcom,smem-state-cells = <1>; 693 }; 694 695 ipa_smp2p_in: ipa-modem-to-ap { 696 qcom,entry-name = "ipa"; 697 interrupt-controller; 698 #interrupt-cells = <2>; 699 }; 700 }; 701 702 smp2p-slpi { 703 compatible = "qcom,smp2p"; 704 qcom,smem = <481>, <430>; 705 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 706 IPCC_MPROC_SIGNAL_SMP2P 707 IRQ_TYPE_EDGE_RISING>; 708 mboxes = <&ipcc IPCC_CLIENT_SLPI 709 IPCC_MPROC_SIGNAL_SMP2P>; 710 711 qcom,local-pid = <0>; 712 qcom,remote-pid = <3>; 713 714 smp2p_slpi_out: master-kernel { 715 qcom,entry-name = "master-kernel"; 716 #qcom,smem-state-cells = <1>; 717 }; 718 719 smp2p_slpi_in: slave-kernel { 720 qcom,entry-name = "slave-kernel"; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 soc: soc@0 { 727 #address-cells = <2>; 728 #size-cells = <2>; 729 ranges = <0 0 0 0 0x10 0>; 730 dma-ranges = <0 0 0 0 0x10 0>; 731 compatible = "simple-bus"; 732 733 gcc: clock-controller@100000 { 734 compatible = "qcom,gcc-sm8450"; 735 reg = <0x0 0x00100000 0x0 0x1f4200>; 736 #clock-cells = <1>; 737 #reset-cells = <1>; 738 #power-domain-cells = <1>; 739 clocks = <&rpmhcc RPMH_CXO_CLK>, 740 <&sleep_clk>, 741 <&pcie0_lane>, 742 <&pcie1_lane>, 743 <0>, 744 <&ufs_mem_phy_lanes 0>, 745 <&ufs_mem_phy_lanes 1>, 746 <&ufs_mem_phy_lanes 2>, 747 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 748 clock-names = "bi_tcxo", 749 "sleep_clk", 750 "pcie_0_pipe_clk", 751 "pcie_1_pipe_clk", 752 "pcie_1_phy_aux_clk", 753 "ufs_phy_rx_symbol_0_clk", 754 "ufs_phy_rx_symbol_1_clk", 755 "ufs_phy_tx_symbol_0_clk", 756 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 757 }; 758 759 gpi_dma2: dma-controller@800000 { 760 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 761 #dma-cells = <3>; 762 reg = <0 0x00800000 0 0x60000>; 763 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 775 dma-channels = <12>; 776 dma-channel-mask = <0x7e>; 777 iommus = <&apps_smmu 0x496 0x0>; 778 status = "disabled"; 779 }; 780 781 qupv3_id_2: geniqup@8c0000 { 782 compatible = "qcom,geni-se-qup"; 783 reg = <0x0 0x008c0000 0x0 0x2000>; 784 clock-names = "m-ahb", "s-ahb"; 785 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 786 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 787 iommus = <&apps_smmu 0x483 0x0>; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 ranges; 791 status = "disabled"; 792 793 i2c15: i2c@880000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0x0 0x00880000 0x0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c15_data_clk>; 800 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 804 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 805 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 806 interconnect-names = "qup-core", "qup-config", "qup-memory"; 807 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 808 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 809 dma-names = "tx", "rx"; 810 status = "disabled"; 811 }; 812 813 spi15: spi@880000 { 814 compatible = "qcom,geni-spi"; 815 reg = <0x0 0x00880000 0x0 0x4000>; 816 clock-names = "se"; 817 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 818 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 821 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 822 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 823 interconnect-names = "qup-core", "qup-config"; 824 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 825 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 826 dma-names = "tx", "rx"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 status = "disabled"; 830 }; 831 832 i2c16: i2c@884000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0x0 0x00884000 0x0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c16_data_clk>; 839 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 843 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 844 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", "qup-memory"; 846 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 status = "disabled"; 850 }; 851 852 spi16: spi@884000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0x0 0x00884000 0x0 0x4000>; 855 clock-names = "se"; 856 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 857 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 860 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 861 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 862 interconnect-names = "qup-core", "qup-config"; 863 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 864 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 865 dma-names = "tx", "rx"; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 status = "disabled"; 869 }; 870 871 i2c17: i2c@888000 { 872 compatible = "qcom,geni-i2c"; 873 reg = <0x0 0x00888000 0x0 0x4000>; 874 clock-names = "se"; 875 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&qup_i2c17_data_clk>; 878 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 882 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 883 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 884 interconnect-names = "qup-core", "qup-config", "qup-memory"; 885 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 886 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 887 dma-names = "tx", "rx"; 888 status = "disabled"; 889 }; 890 891 spi17: spi@888000 { 892 compatible = "qcom,geni-spi"; 893 reg = <0x0 0x00888000 0x0 0x4000>; 894 clock-names = "se"; 895 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 896 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 899 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 900 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 901 interconnect-names = "qup-core", "qup-config"; 902 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 903 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 904 dma-names = "tx", "rx"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 910 i2c18: i2c@88c000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0x0 0x0088c000 0x0 0x4000>; 913 clock-names = "se"; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 915 pinctrl-names = "default"; 916 pinctrl-0 = <&qup_i2c18_data_clk>; 917 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 921 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 922 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 923 interconnect-names = "qup-core", "qup-config", "qup-memory"; 924 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 925 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 926 dma-names = "tx", "rx"; 927 status = "disabled"; 928 }; 929 930 spi18: spi@88c000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0 0x0088c000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 935 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 938 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 939 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 940 interconnect-names = "qup-core", "qup-config"; 941 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 942 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 943 dma-names = "tx", "rx"; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 status = "disabled"; 947 }; 948 949 i2c19: i2c@890000 { 950 compatible = "qcom,geni-i2c"; 951 reg = <0x0 0x00890000 0x0 0x4000>; 952 clock-names = "se"; 953 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_i2c19_data_clk>; 956 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 960 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 961 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 962 interconnect-names = "qup-core", "qup-config", "qup-memory"; 963 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 964 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 965 dma-names = "tx", "rx"; 966 status = "disabled"; 967 }; 968 969 spi19: spi@890000 { 970 compatible = "qcom,geni-spi"; 971 reg = <0 0x00890000 0 0x4000>; 972 clock-names = "se"; 973 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 974 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 977 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 978 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 979 interconnect-names = "qup-core", "qup-config"; 980 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 981 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 982 dma-names = "tx", "rx"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 i2c20: i2c@894000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0x0 0x00894000 0x0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_i2c20_data_clk>; 995 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 999 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1000 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1001 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1002 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1003 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1004 dma-names = "tx", "rx"; 1005 status = "disabled"; 1006 }; 1007 1008 uart20: serial@894000 { 1009 compatible = "qcom,geni-uart"; 1010 reg = <0 0x00894000 0 0x4000>; 1011 clock-names = "se"; 1012 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_uart20_default>; 1015 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1016 status = "disabled"; 1017 }; 1018 1019 spi20: spi@894000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x00894000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1024 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1027 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1028 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1029 interconnect-names = "qup-core", "qup-config"; 1030 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1031 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1032 dma-names = "tx", "rx"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c21: i2c@898000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0x0 0x00898000 0x0 0x4000>; 1041 clock-names = "se"; 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_i2c21_data_clk>; 1045 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1050 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1051 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1052 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1053 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1054 dma-names = "tx", "rx"; 1055 status = "disabled"; 1056 }; 1057 1058 spi21: spi@898000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x00898000 0 0x4000>; 1061 clock-names = "se"; 1062 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1063 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1068 interconnect-names = "qup-core", "qup-config"; 1069 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1070 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1071 dma-names = "tx", "rx"; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 }; 1077 1078 gpi_dma0: dma-controller@900000 { 1079 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1080 #dma-cells = <3>; 1081 reg = <0 0x00900000 0 0x60000>; 1082 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1094 dma-channels = <12>; 1095 dma-channel-mask = <0x7e>; 1096 iommus = <&apps_smmu 0x5b6 0x0>; 1097 status = "disabled"; 1098 }; 1099 1100 qupv3_id_0: geniqup@9c0000 { 1101 compatible = "qcom,geni-se-qup"; 1102 reg = <0x0 0x009c0000 0x0 0x2000>; 1103 clock-names = "m-ahb", "s-ahb"; 1104 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1105 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1106 iommus = <&apps_smmu 0x5a3 0x0>; 1107 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1108 interconnect-names = "qup-core"; 1109 #address-cells = <2>; 1110 #size-cells = <2>; 1111 ranges; 1112 status = "disabled"; 1113 1114 i2c0: i2c@980000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0x0 0x00980000 0x0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c0_data_clk>; 1121 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1125 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1126 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1127 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1128 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1129 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1130 dma-names = "tx", "rx"; 1131 status = "disabled"; 1132 }; 1133 1134 spi0: spi@980000 { 1135 compatible = "qcom,geni-spi"; 1136 reg = <0x0 0x00980000 0x0 0x4000>; 1137 clock-names = "se"; 1138 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1139 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1142 power-domains = <&rpmhpd SM8450_CX>; 1143 operating-points-v2 = <&qup_opp_table_100mhz>; 1144 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1145 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1146 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1147 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1148 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1149 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1150 dma-names = "tx", "rx"; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c1: i2c@984000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0x0 0x00984000 0x0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c1_data_clk>; 1163 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1167 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1168 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1169 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1170 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1171 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1172 dma-names = "tx", "rx"; 1173 status = "disabled"; 1174 }; 1175 1176 spi1: spi@984000 { 1177 compatible = "qcom,geni-spi"; 1178 reg = <0x0 0x00984000 0x0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1181 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1186 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1187 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1188 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1189 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1190 dma-names = "tx", "rx"; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 status = "disabled"; 1194 }; 1195 1196 i2c2: i2c@988000 { 1197 compatible = "qcom,geni-i2c"; 1198 reg = <0x0 0x00988000 0x0 0x4000>; 1199 clock-names = "se"; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&qup_i2c2_data_clk>; 1203 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1207 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1208 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1209 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1210 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1211 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1212 dma-names = "tx", "rx"; 1213 status = "disabled"; 1214 }; 1215 1216 spi2: spi@988000 { 1217 compatible = "qcom,geni-spi"; 1218 reg = <0x0 0x00988000 0x0 0x4000>; 1219 clock-names = "se"; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1221 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1227 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1228 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1229 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1230 dma-names = "tx", "rx"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 1237 i2c3: i2c@98c000 { 1238 compatible = "qcom,geni-i2c"; 1239 reg = <0x0 0x0098c000 0x0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_i2c3_data_clk>; 1244 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1248 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1249 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1250 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1251 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1252 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1253 dma-names = "tx", "rx"; 1254 status = "disabled"; 1255 }; 1256 1257 spi3: spi@98c000 { 1258 compatible = "qcom,geni-spi"; 1259 reg = <0x0 0x0098c000 0x0 0x4000>; 1260 clock-names = "se"; 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1262 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1267 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1268 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1269 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1270 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1271 dma-names = "tx", "rx"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 i2c4: i2c@990000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0x0 0x00990000 0x0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c4_data_clk>; 1284 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1288 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1289 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1290 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1291 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1292 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1293 dma-names = "tx", "rx"; 1294 status = "disabled"; 1295 }; 1296 1297 spi4: spi@990000 { 1298 compatible = "qcom,geni-spi"; 1299 reg = <0x0 0x00990000 0x0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1302 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1305 power-domains = <&rpmhpd SM8450_CX>; 1306 operating-points-v2 = <&qup_opp_table_100mhz>; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1308 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1309 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1310 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1311 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1312 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1313 dma-names = "tx", "rx"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 i2c5: i2c@994000 { 1320 compatible = "qcom,geni-i2c"; 1321 reg = <0x0 0x00994000 0x0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_i2c5_data_clk>; 1326 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1331 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1333 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1334 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1335 dma-names = "tx", "rx"; 1336 status = "disabled"; 1337 }; 1338 1339 spi5: spi@994000 { 1340 compatible = "qcom,geni-spi"; 1341 reg = <0x0 0x00994000 0x0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1350 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1352 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1353 dma-names = "tx", "rx"; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 1359 1360 i2c6: i2c@998000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0x0 0x00998000 0x0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c6_data_clk>; 1367 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1371 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1372 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1374 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 status = "disabled"; 1378 }; 1379 1380 spi6: spi@998000 { 1381 compatible = "qcom,geni-spi"; 1382 reg = <0x0 0x00998000 0x0 0x4000>; 1383 clock-names = "se"; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1385 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1390 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1391 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1393 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1394 dma-names = "tx", "rx"; 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 status = "disabled"; 1398 }; 1399 1400 uart7: serial@99c000 { 1401 compatible = "qcom,geni-debug-uart"; 1402 reg = <0 0x0099c000 0 0x4000>; 1403 clock-names = "se"; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1405 pinctrl-names = "default"; 1406 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1407 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1408 status = "disabled"; 1409 }; 1410 }; 1411 1412 gpi_dma1: dma-controller@a00000 { 1413 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1414 #dma-cells = <3>; 1415 reg = <0 0x00a00000 0 0x60000>; 1416 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1428 dma-channels = <12>; 1429 dma-channel-mask = <0x7e>; 1430 iommus = <&apps_smmu 0x56 0x0>; 1431 status = "disabled"; 1432 }; 1433 1434 qupv3_id_1: geniqup@ac0000 { 1435 compatible = "qcom,geni-se-qup"; 1436 reg = <0x0 0x00ac0000 0x0 0x6000>; 1437 clock-names = "m-ahb", "s-ahb"; 1438 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1439 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1440 iommus = <&apps_smmu 0x43 0x0>; 1441 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1442 interconnect-names = "qup-core"; 1443 #address-cells = <2>; 1444 #size-cells = <2>; 1445 ranges; 1446 status = "disabled"; 1447 1448 i2c8: i2c@a80000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0x0 0x00a80000 0x0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_i2c8_data_clk>; 1455 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1459 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1460 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1463 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1464 dma-names = "tx", "rx"; 1465 status = "disabled"; 1466 }; 1467 1468 spi8: spi@a80000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0x0 0x00a80000 0x0 0x4000>; 1471 clock-names = "se"; 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1473 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1474 pinctrl-names = "default"; 1475 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1477 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1478 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1479 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1480 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1481 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1482 dma-names = "tx", "rx"; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 i2c9: i2c@a84000 { 1489 compatible = "qcom,geni-i2c"; 1490 reg = <0x0 0x00a84000 0x0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_i2c9_data_clk>; 1495 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1499 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1500 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1501 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1502 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1503 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1504 dma-names = "tx", "rx"; 1505 status = "disabled"; 1506 }; 1507 1508 spi9: spi@a84000 { 1509 compatible = "qcom,geni-spi"; 1510 reg = <0x0 0x00a84000 0x0 0x4000>; 1511 clock-names = "se"; 1512 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1513 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1518 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1519 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1520 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1521 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1522 dma-names = "tx", "rx"; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 status = "disabled"; 1526 }; 1527 1528 i2c10: i2c@a88000 { 1529 compatible = "qcom,geni-i2c"; 1530 reg = <0x0 0x00a88000 0x0 0x4000>; 1531 clock-names = "se"; 1532 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&qup_i2c10_data_clk>; 1535 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1539 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1540 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1541 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1542 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1543 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1544 dma-names = "tx", "rx"; 1545 status = "disabled"; 1546 }; 1547 1548 spi10: spi@a88000 { 1549 compatible = "qcom,geni-spi"; 1550 reg = <0x0 0x00a88000 0x0 0x4000>; 1551 clock-names = "se"; 1552 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1553 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1554 pinctrl-names = "default"; 1555 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1556 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1557 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1558 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1559 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1560 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1561 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1562 dma-names = "tx", "rx"; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 i2c11: i2c@a8c000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0x0 0x00a8c000 0x0 0x4000>; 1571 clock-names = "se"; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c11_data_clk>; 1575 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1579 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1580 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1582 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1583 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1584 dma-names = "tx", "rx"; 1585 status = "disabled"; 1586 }; 1587 1588 spi11: spi@a8c000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0x0 0x00a8c000 0x0 0x4000>; 1591 clock-names = "se"; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1593 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1597 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1598 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1599 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1600 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1601 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1602 dma-names = "tx", "rx"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 i2c12: i2c@a90000 { 1609 compatible = "qcom,geni-i2c"; 1610 reg = <0x0 0x00a90000 0x0 0x4000>; 1611 clock-names = "se"; 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1613 pinctrl-names = "default"; 1614 pinctrl-0 = <&qup_i2c12_data_clk>; 1615 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1619 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1620 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1621 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1622 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1623 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1624 dma-names = "tx", "rx"; 1625 status = "disabled"; 1626 }; 1627 1628 spi12: spi@a90000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0x0 0x00a90000 0x0 0x4000>; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1633 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1638 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1639 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1640 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1641 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1642 dma-names = "tx", "rx"; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c13: i2c@a94000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00a94000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c13_data_clk>; 1655 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1656 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1657 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1658 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1659 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1660 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1661 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1662 dma-names = "tx", "rx"; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 spi13: spi@a94000 { 1669 compatible = "qcom,geni-spi"; 1670 reg = <0x0 0x00a94000 0x0 0x4000>; 1671 clock-names = "se"; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1673 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1674 pinctrl-names = "default"; 1675 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1677 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1678 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1679 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1680 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1681 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1682 dma-names = "tx", "rx"; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 status = "disabled"; 1686 }; 1687 1688 i2c14: i2c@a98000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0 0x00a98000 0 0x4000>; 1691 clock-names = "se"; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_i2c14_data_clk>; 1695 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1698 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1699 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1700 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1702 dma-names = "tx", "rx"; 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 status = "disabled"; 1706 }; 1707 1708 spi14: spi@a98000 { 1709 compatible = "qcom,geni-spi"; 1710 reg = <0x0 0x00a98000 0x0 0x4000>; 1711 clock-names = "se"; 1712 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1713 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1716 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1717 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1718 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1719 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1720 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1721 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1722 dma-names = "tx", "rx"; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 }; 1728 1729 pcie0: pci@1c00000 { 1730 compatible = "qcom,pcie-sm8450-pcie0"; 1731 reg = <0 0x01c00000 0 0x3000>, 1732 <0 0x60000000 0 0xf1d>, 1733 <0 0x60000f20 0 0xa8>, 1734 <0 0x60001000 0 0x1000>, 1735 <0 0x60100000 0 0x100000>; 1736 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1737 device_type = "pci"; 1738 linux,pci-domain = <0>; 1739 bus-range = <0x00 0xff>; 1740 num-lanes = <1>; 1741 1742 #address-cells = <3>; 1743 #size-cells = <2>; 1744 1745 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1746 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1747 1748 /* 1749 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1750 * Hence, the IDs are swapped. 1751 */ 1752 msi-map = <0x0 &gic_its 0x5981 0x1>, 1753 <0x100 &gic_its 0x5980 0x1>; 1754 msi-map-mask = <0xff00>; 1755 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1756 interrupt-names = "msi"; 1757 #interrupt-cells = <1>; 1758 interrupt-map-mask = <0 0 0 0x7>; 1759 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1760 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1761 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1762 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1763 1764 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1765 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1766 <&pcie0_lane>, 1767 <&rpmhcc RPMH_CXO_CLK>, 1768 <&gcc GCC_PCIE_0_AUX_CLK>, 1769 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1770 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1771 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1772 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1773 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1774 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1775 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1776 clock-names = "pipe", 1777 "pipe_mux", 1778 "phy_pipe", 1779 "ref", 1780 "aux", 1781 "cfg", 1782 "bus_master", 1783 "bus_slave", 1784 "slave_q2a", 1785 "ddrss_sf_tbu", 1786 "aggre0", 1787 "aggre1"; 1788 1789 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1790 <0x100 &apps_smmu 0x1c01 0x1>; 1791 1792 resets = <&gcc GCC_PCIE_0_BCR>; 1793 reset-names = "pci"; 1794 1795 power-domains = <&gcc PCIE_0_GDSC>; 1796 1797 phys = <&pcie0_lane>; 1798 phy-names = "pciephy"; 1799 1800 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1801 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1802 1803 pinctrl-names = "default"; 1804 pinctrl-0 = <&pcie0_default_state>; 1805 1806 status = "disabled"; 1807 }; 1808 1809 pcie0_phy: phy@1c06000 { 1810 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1811 reg = <0 0x01c06000 0 0x200>; 1812 #address-cells = <2>; 1813 #size-cells = <2>; 1814 ranges; 1815 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1816 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1817 <&gcc GCC_PCIE_0_CLKREF_EN>, 1818 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1819 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1820 1821 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1822 reset-names = "phy"; 1823 1824 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1825 assigned-clock-rates = <100000000>; 1826 1827 status = "disabled"; 1828 1829 pcie0_lane: phy@1c06200 { 1830 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1831 <0 0x01c07000 0 0x200>, /* rx */ 1832 <0 0x01c06200 0 0x200>, /* pcs */ 1833 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1834 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1835 clock-names = "pipe0"; 1836 1837 #clock-cells = <0>; 1838 #phy-cells = <0>; 1839 clock-output-names = "pcie_0_pipe_clk"; 1840 }; 1841 }; 1842 1843 pcie1: pci@1c08000 { 1844 compatible = "qcom,pcie-sm8450-pcie1"; 1845 reg = <0 0x01c08000 0 0x3000>, 1846 <0 0x40000000 0 0xf1d>, 1847 <0 0x40000f20 0 0xa8>, 1848 <0 0x40001000 0 0x1000>, 1849 <0 0x40100000 0 0x100000>; 1850 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1851 device_type = "pci"; 1852 linux,pci-domain = <1>; 1853 bus-range = <0x00 0xff>; 1854 num-lanes = <2>; 1855 1856 #address-cells = <3>; 1857 #size-cells = <2>; 1858 1859 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1860 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1861 1862 /* 1863 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1864 * Hence, the IDs are swapped. 1865 */ 1866 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1867 <0x100 &gic_its 0x5a00 0x1>; 1868 msi-map-mask = <0xff00>; 1869 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1870 interrupt-names = "msi"; 1871 #interrupt-cells = <1>; 1872 interrupt-map-mask = <0 0 0 0x7>; 1873 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1874 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1875 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1876 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1877 1878 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1879 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1880 <&pcie1_lane>, 1881 <&rpmhcc RPMH_CXO_CLK>, 1882 <&gcc GCC_PCIE_1_AUX_CLK>, 1883 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1884 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1885 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1886 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1887 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1888 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1889 clock-names = "pipe", 1890 "pipe_mux", 1891 "phy_pipe", 1892 "ref", 1893 "aux", 1894 "cfg", 1895 "bus_master", 1896 "bus_slave", 1897 "slave_q2a", 1898 "ddrss_sf_tbu", 1899 "aggre1"; 1900 1901 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1902 <0x100 &apps_smmu 0x1c81 0x1>; 1903 1904 resets = <&gcc GCC_PCIE_1_BCR>; 1905 reset-names = "pci"; 1906 1907 power-domains = <&gcc PCIE_1_GDSC>; 1908 1909 phys = <&pcie1_lane>; 1910 phy-names = "pciephy"; 1911 1912 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1913 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1914 1915 pinctrl-names = "default"; 1916 pinctrl-0 = <&pcie1_default_state>; 1917 1918 status = "disabled"; 1919 }; 1920 1921 pcie1_phy: phy@1c0f000 { 1922 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1923 reg = <0 0x01c0f000 0 0x200>; 1924 #address-cells = <2>; 1925 #size-cells = <2>; 1926 ranges; 1927 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1928 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1929 <&gcc GCC_PCIE_1_CLKREF_EN>, 1930 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1931 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1932 1933 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1934 reset-names = "phy"; 1935 1936 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1937 assigned-clock-rates = <100000000>; 1938 1939 status = "disabled"; 1940 1941 pcie1_lane: phy@1c0e000 { 1942 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1943 <0 0x01c0e200 0 0x300>, /* rx */ 1944 <0 0x01c0f200 0 0x200>, /* pcs */ 1945 <0 0x01c0e800 0 0x200>, /* tx */ 1946 <0 0x01c0ea00 0 0x300>, /* rx */ 1947 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1948 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1949 clock-names = "pipe0"; 1950 1951 #clock-cells = <0>; 1952 #phy-cells = <0>; 1953 clock-output-names = "pcie_1_pipe_clk"; 1954 }; 1955 }; 1956 1957 config_noc: interconnect@1500000 { 1958 compatible = "qcom,sm8450-config-noc"; 1959 reg = <0 0x01500000 0 0x1c000>; 1960 #interconnect-cells = <2>; 1961 qcom,bcm-voters = <&apps_bcm_voter>; 1962 }; 1963 1964 system_noc: interconnect@1680000 { 1965 compatible = "qcom,sm8450-system-noc"; 1966 reg = <0 0x01680000 0 0x1e200>; 1967 #interconnect-cells = <2>; 1968 qcom,bcm-voters = <&apps_bcm_voter>; 1969 }; 1970 1971 pcie_noc: interconnect@16c0000 { 1972 compatible = "qcom,sm8450-pcie-anoc"; 1973 reg = <0 0x016c0000 0 0xe280>; 1974 #interconnect-cells = <2>; 1975 qcom,bcm-voters = <&apps_bcm_voter>; 1976 }; 1977 1978 aggre1_noc: interconnect@16e0000 { 1979 compatible = "qcom,sm8450-aggre1-noc"; 1980 reg = <0 0x016e0000 0 0x1c080>; 1981 #interconnect-cells = <2>; 1982 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1983 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1984 qcom,bcm-voters = <&apps_bcm_voter>; 1985 }; 1986 1987 aggre2_noc: interconnect@1700000 { 1988 compatible = "qcom,sm8450-aggre2-noc"; 1989 reg = <0 0x01700000 0 0x31080>; 1990 #interconnect-cells = <2>; 1991 qcom,bcm-voters = <&apps_bcm_voter>; 1992 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1993 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1994 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1995 <&rpmhcc RPMH_IPA_CLK>; 1996 }; 1997 1998 mmss_noc: interconnect@1740000 { 1999 compatible = "qcom,sm8450-mmss-noc"; 2000 reg = <0 0x01740000 0 0x1f080>; 2001 #interconnect-cells = <2>; 2002 qcom,bcm-voters = <&apps_bcm_voter>; 2003 }; 2004 2005 tcsr_mutex: hwlock@1f40000 { 2006 compatible = "qcom,tcsr-mutex"; 2007 reg = <0x0 0x01f40000 0x0 0x40000>; 2008 #hwlock-cells = <1>; 2009 }; 2010 2011 tcsr: syscon@1fc0000 { 2012 compatible = "qcom,sm8450-tcsr", "syscon"; 2013 reg = <0x0 0x1fc0000 0x0 0x30000>; 2014 }; 2015 2016 usb_1_hsphy: phy@88e3000 { 2017 compatible = "qcom,sm8450-usb-hs-phy", 2018 "qcom,usb-snps-hs-7nm-phy"; 2019 reg = <0 0x088e3000 0 0x400>; 2020 status = "disabled"; 2021 #phy-cells = <0>; 2022 2023 clocks = <&rpmhcc RPMH_CXO_CLK>; 2024 clock-names = "ref"; 2025 2026 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2027 }; 2028 2029 usb_1_qmpphy: phy@88e8000 { 2030 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2031 reg = <0 0x088e8000 0 0x3000>; 2032 2033 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2034 <&rpmhcc RPMH_CXO_CLK>, 2035 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2036 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2037 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2038 2039 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2040 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2041 reset-names = "phy", "common"; 2042 2043 #clock-cells = <1>; 2044 #phy-cells = <1>; 2045 2046 status = "disabled"; 2047 }; 2048 2049 remoteproc_slpi: remoteproc@2400000 { 2050 compatible = "qcom,sm8450-slpi-pas"; 2051 reg = <0 0x02400000 0 0x4000>; 2052 2053 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2054 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2055 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2056 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2057 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2058 interrupt-names = "wdog", "fatal", "ready", 2059 "handover", "stop-ack"; 2060 2061 clocks = <&rpmhcc RPMH_CXO_CLK>; 2062 clock-names = "xo"; 2063 2064 power-domains = <&rpmhpd SM8450_LCX>, 2065 <&rpmhpd SM8450_LMX>; 2066 power-domain-names = "lcx", "lmx"; 2067 2068 memory-region = <&slpi_mem>; 2069 2070 qcom,qmp = <&aoss_qmp>; 2071 2072 qcom,smem-states = <&smp2p_slpi_out 0>; 2073 qcom,smem-state-names = "stop"; 2074 2075 status = "disabled"; 2076 2077 glink-edge { 2078 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2079 IPCC_MPROC_SIGNAL_GLINK_QMP 2080 IRQ_TYPE_EDGE_RISING>; 2081 mboxes = <&ipcc IPCC_CLIENT_SLPI 2082 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2083 2084 label = "slpi"; 2085 qcom,remote-pid = <3>; 2086 2087 fastrpc { 2088 compatible = "qcom,fastrpc"; 2089 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2090 label = "sdsp"; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 2094 compute-cb@1 { 2095 compatible = "qcom,fastrpc-compute-cb"; 2096 reg = <1>; 2097 iommus = <&apps_smmu 0x0541 0x0>; 2098 }; 2099 2100 compute-cb@2 { 2101 compatible = "qcom,fastrpc-compute-cb"; 2102 reg = <2>; 2103 iommus = <&apps_smmu 0x0542 0x0>; 2104 }; 2105 2106 compute-cb@3 { 2107 compatible = "qcom,fastrpc-compute-cb"; 2108 reg = <3>; 2109 iommus = <&apps_smmu 0x0543 0x0>; 2110 /* note: shared-cb = <4> in downstream */ 2111 }; 2112 }; 2113 }; 2114 }; 2115 2116 wsa2macro: codec@31e0000 { 2117 compatible = "qcom,sm8450-lpass-wsa-macro"; 2118 reg = <0 0x031e0000 0 0x1000>; 2119 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2120 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2121 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2122 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2123 <&vamacro>; 2124 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2125 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2126 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2127 assigned-clock-rates = <19200000>, <19200000>; 2128 2129 #clock-cells = <0>; 2130 clock-output-names = "wsa2-mclk"; 2131 pinctrl-names = "default"; 2132 pinctrl-0 = <&wsa2_swr_active>; 2133 #sound-dai-cells = <1>; 2134 }; 2135 2136 swr4: soundwire-controller@31f0000 { 2137 compatible = "qcom,soundwire-v1.7.0"; 2138 reg = <0 0x031f0000 0 0x2000>; 2139 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2140 clocks = <&wsa2macro>; 2141 clock-names = "iface"; 2142 label = "WSA2"; 2143 2144 qcom,din-ports = <2>; 2145 qcom,dout-ports = <6>; 2146 2147 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2148 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2149 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2150 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2151 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2152 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2153 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2154 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2155 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2156 2157 #address-cells = <2>; 2158 #size-cells = <0>; 2159 #sound-dai-cells = <1>; 2160 status = "disabled"; 2161 }; 2162 2163 rxmacro: codec@3200000 { 2164 compatible = "qcom,sm8450-lpass-rx-macro"; 2165 reg = <0 0x03200000 0 0x1000>; 2166 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2167 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2168 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2169 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2170 <&vamacro>; 2171 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2172 2173 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2174 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2175 assigned-clock-rates = <19200000>, <19200000>; 2176 2177 #clock-cells = <0>; 2178 clock-output-names = "mclk"; 2179 pinctrl-names = "default"; 2180 pinctrl-0 = <&rx_swr_active>; 2181 #sound-dai-cells = <1>; 2182 }; 2183 2184 swr1: soundwire-controller@3210000 { 2185 compatible = "qcom,soundwire-v1.7.0"; 2186 reg = <0 0x03210000 0 0x2000>; 2187 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2188 clocks = <&rxmacro>; 2189 clock-names = "iface"; 2190 label = "RX"; 2191 qcom,din-ports = <0>; 2192 qcom,dout-ports = <5>; 2193 2194 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2195 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2196 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2197 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2198 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2199 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2200 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2201 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2202 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2203 2204 #address-cells = <2>; 2205 #size-cells = <0>; 2206 #sound-dai-cells = <1>; 2207 status = "disabled"; 2208 }; 2209 2210 txmacro: codec@3220000 { 2211 compatible = "qcom,sm8450-lpass-tx-macro"; 2212 reg = <0 0x03220000 0 0x1000>; 2213 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2214 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2215 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2216 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2217 <&vamacro>; 2218 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2219 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2220 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2221 assigned-clock-rates = <19200000>, <19200000>; 2222 2223 #clock-cells = <0>; 2224 clock-output-names = "mclk"; 2225 pinctrl-names = "default"; 2226 pinctrl-0 = <&tx_swr_active>; 2227 #sound-dai-cells = <1>; 2228 }; 2229 2230 wsamacro: codec@3240000 { 2231 compatible = "qcom,sm8450-lpass-wsa-macro"; 2232 reg = <0 0x03240000 0 0x1000>; 2233 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2234 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2235 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2236 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2237 <&vamacro>; 2238 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2239 2240 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2241 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2242 assigned-clock-rates = <19200000>, <19200000>; 2243 2244 #clock-cells = <0>; 2245 clock-output-names = "mclk"; 2246 pinctrl-names = "default"; 2247 pinctrl-0 = <&wsa_swr_active>; 2248 #sound-dai-cells = <1>; 2249 }; 2250 2251 swr0: soundwire-controller@3250000 { 2252 compatible = "qcom,soundwire-v1.7.0"; 2253 reg = <0 0x03250000 0 0x2000>; 2254 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&wsamacro>; 2256 clock-names = "iface"; 2257 label = "WSA"; 2258 2259 qcom,din-ports = <2>; 2260 qcom,dout-ports = <6>; 2261 2262 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2263 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2264 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2265 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2266 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2267 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2268 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2269 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2270 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2271 2272 #address-cells = <2>; 2273 #size-cells = <0>; 2274 #sound-dai-cells = <1>; 2275 status = "disabled"; 2276 }; 2277 2278 swr2: soundwire-controller@33b0000 { 2279 compatible = "qcom,soundwire-v1.7.0"; 2280 reg = <0 0x033b0000 0 0x2000>; 2281 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2283 interrupt-names = "core", "wakeup"; 2284 2285 clocks = <&vamacro>; 2286 clock-names = "iface"; 2287 label = "TX"; 2288 2289 qcom,din-ports = <4>; 2290 qcom,dout-ports = <0>; 2291 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2292 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2293 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2294 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2295 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2296 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2297 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2298 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2299 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2300 2301 #address-cells = <2>; 2302 #size-cells = <0>; 2303 #sound-dai-cells = <1>; 2304 status = "disabled"; 2305 }; 2306 2307 vamacro: codec@33f0000 { 2308 compatible = "qcom,sm8450-lpass-va-macro"; 2309 reg = <0 0x033f0000 0 0x1000>; 2310 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2311 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2312 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2313 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2314 clock-names = "mclk", "macro", "dcodec", "npl"; 2315 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2316 assigned-clock-rates = <19200000>; 2317 2318 #clock-cells = <0>; 2319 clock-output-names = "fsgen"; 2320 #sound-dai-cells = <1>; 2321 status = "disabled"; 2322 }; 2323 2324 remoteproc_adsp: remoteproc@30000000 { 2325 compatible = "qcom,sm8450-adsp-pas"; 2326 reg = <0 0x30000000 0 0x100>; 2327 2328 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2329 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2330 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2331 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2332 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2333 interrupt-names = "wdog", "fatal", "ready", 2334 "handover", "stop-ack"; 2335 2336 clocks = <&rpmhcc RPMH_CXO_CLK>; 2337 clock-names = "xo"; 2338 2339 power-domains = <&rpmhpd SM8450_LCX>, 2340 <&rpmhpd SM8450_LMX>; 2341 power-domain-names = "lcx", "lmx"; 2342 2343 memory-region = <&adsp_mem>; 2344 2345 qcom,qmp = <&aoss_qmp>; 2346 2347 qcom,smem-states = <&smp2p_adsp_out 0>; 2348 qcom,smem-state-names = "stop"; 2349 2350 status = "disabled"; 2351 2352 remoteproc_adsp_glink: glink-edge { 2353 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2354 IPCC_MPROC_SIGNAL_GLINK_QMP 2355 IRQ_TYPE_EDGE_RISING>; 2356 mboxes = <&ipcc IPCC_CLIENT_LPASS 2357 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2358 2359 label = "lpass"; 2360 qcom,remote-pid = <2>; 2361 2362 gpr { 2363 compatible = "qcom,gpr"; 2364 qcom,glink-channels = "adsp_apps"; 2365 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2366 qcom,intents = <512 20>; 2367 #address-cells = <1>; 2368 #size-cells = <0>; 2369 2370 q6apm: service@1 { 2371 compatible = "qcom,q6apm"; 2372 reg = <GPR_APM_MODULE_IID>; 2373 #sound-dai-cells = <0>; 2374 qcom,protection-domain = "avs/audio", 2375 "msm/adsp/audio_pd"; 2376 2377 q6apmdai: dais { 2378 compatible = "qcom,q6apm-dais"; 2379 iommus = <&apps_smmu 0x1801 0x0>; 2380 }; 2381 2382 q6apmbedai: bedais { 2383 compatible = "qcom,q6apm-lpass-dais"; 2384 #sound-dai-cells = <1>; 2385 }; 2386 }; 2387 2388 q6prm: service@2 { 2389 compatible = "qcom,q6prm"; 2390 reg = <GPR_PRM_MODULE_IID>; 2391 qcom,protection-domain = "avs/audio", 2392 "msm/adsp/audio_pd"; 2393 2394 q6prmcc: clock-controller { 2395 compatible = "qcom,q6prm-lpass-clocks"; 2396 #clock-cells = <2>; 2397 }; 2398 }; 2399 }; 2400 2401 fastrpc { 2402 compatible = "qcom,fastrpc"; 2403 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2404 label = "adsp"; 2405 #address-cells = <1>; 2406 #size-cells = <0>; 2407 2408 compute-cb@3 { 2409 compatible = "qcom,fastrpc-compute-cb"; 2410 reg = <3>; 2411 iommus = <&apps_smmu 0x1803 0x0>; 2412 }; 2413 2414 compute-cb@4 { 2415 compatible = "qcom,fastrpc-compute-cb"; 2416 reg = <4>; 2417 iommus = <&apps_smmu 0x1804 0x0>; 2418 }; 2419 2420 compute-cb@5 { 2421 compatible = "qcom,fastrpc-compute-cb"; 2422 reg = <5>; 2423 iommus = <&apps_smmu 0x1805 0x0>; 2424 }; 2425 }; 2426 }; 2427 }; 2428 2429 remoteproc_cdsp: remoteproc@32300000 { 2430 compatible = "qcom,sm8450-cdsp-pas"; 2431 reg = <0 0x32300000 0 0x1400000>; 2432 2433 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2434 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2435 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2436 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2437 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2438 interrupt-names = "wdog", "fatal", "ready", 2439 "handover", "stop-ack"; 2440 2441 clocks = <&rpmhcc RPMH_CXO_CLK>; 2442 clock-names = "xo"; 2443 2444 power-domains = <&rpmhpd SM8450_CX>, 2445 <&rpmhpd SM8450_MXC>; 2446 power-domain-names = "cx", "mxc"; 2447 2448 memory-region = <&cdsp_mem>; 2449 2450 qcom,qmp = <&aoss_qmp>; 2451 2452 qcom,smem-states = <&smp2p_cdsp_out 0>; 2453 qcom,smem-state-names = "stop"; 2454 2455 status = "disabled"; 2456 2457 glink-edge { 2458 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2459 IPCC_MPROC_SIGNAL_GLINK_QMP 2460 IRQ_TYPE_EDGE_RISING>; 2461 mboxes = <&ipcc IPCC_CLIENT_CDSP 2462 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2463 2464 label = "cdsp"; 2465 qcom,remote-pid = <5>; 2466 2467 fastrpc { 2468 compatible = "qcom,fastrpc"; 2469 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2470 label = "cdsp"; 2471 #address-cells = <1>; 2472 #size-cells = <0>; 2473 2474 compute-cb@1 { 2475 compatible = "qcom,fastrpc-compute-cb"; 2476 reg = <1>; 2477 iommus = <&apps_smmu 0x2161 0x0400>, 2478 <&apps_smmu 0x1021 0x1420>; 2479 }; 2480 2481 compute-cb@2 { 2482 compatible = "qcom,fastrpc-compute-cb"; 2483 reg = <2>; 2484 iommus = <&apps_smmu 0x2162 0x0400>, 2485 <&apps_smmu 0x1022 0x1420>; 2486 }; 2487 2488 compute-cb@3 { 2489 compatible = "qcom,fastrpc-compute-cb"; 2490 reg = <3>; 2491 iommus = <&apps_smmu 0x2163 0x0400>, 2492 <&apps_smmu 0x1023 0x1420>; 2493 }; 2494 2495 compute-cb@4 { 2496 compatible = "qcom,fastrpc-compute-cb"; 2497 reg = <4>; 2498 iommus = <&apps_smmu 0x2164 0x0400>, 2499 <&apps_smmu 0x1024 0x1420>; 2500 }; 2501 2502 compute-cb@5 { 2503 compatible = "qcom,fastrpc-compute-cb"; 2504 reg = <5>; 2505 iommus = <&apps_smmu 0x2165 0x0400>, 2506 <&apps_smmu 0x1025 0x1420>; 2507 }; 2508 2509 compute-cb@6 { 2510 compatible = "qcom,fastrpc-compute-cb"; 2511 reg = <6>; 2512 iommus = <&apps_smmu 0x2166 0x0400>, 2513 <&apps_smmu 0x1026 0x1420>; 2514 }; 2515 2516 compute-cb@7 { 2517 compatible = "qcom,fastrpc-compute-cb"; 2518 reg = <7>; 2519 iommus = <&apps_smmu 0x2167 0x0400>, 2520 <&apps_smmu 0x1027 0x1420>; 2521 }; 2522 2523 compute-cb@8 { 2524 compatible = "qcom,fastrpc-compute-cb"; 2525 reg = <8>; 2526 iommus = <&apps_smmu 0x2168 0x0400>, 2527 <&apps_smmu 0x1028 0x1420>; 2528 }; 2529 2530 /* note: secure cb9 in downstream */ 2531 }; 2532 }; 2533 }; 2534 2535 remoteproc_mpss: remoteproc@4080000 { 2536 compatible = "qcom,sm8450-mpss-pas"; 2537 reg = <0x0 0x04080000 0x0 0x4040>; 2538 2539 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2540 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2541 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2542 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2543 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2544 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2545 interrupt-names = "wdog", "fatal", "ready", "handover", 2546 "stop-ack", "shutdown-ack"; 2547 2548 clocks = <&rpmhcc RPMH_CXO_CLK>; 2549 clock-names = "xo"; 2550 2551 power-domains = <&rpmhpd SM8450_CX>, 2552 <&rpmhpd SM8450_MSS>; 2553 power-domain-names = "cx", "mss"; 2554 2555 memory-region = <&mpss_mem>; 2556 2557 qcom,qmp = <&aoss_qmp>; 2558 2559 qcom,smem-states = <&smp2p_modem_out 0>; 2560 qcom,smem-state-names = "stop"; 2561 2562 status = "disabled"; 2563 2564 glink-edge { 2565 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2566 IPCC_MPROC_SIGNAL_GLINK_QMP 2567 IRQ_TYPE_EDGE_RISING>; 2568 mboxes = <&ipcc IPCC_CLIENT_MPSS 2569 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2570 label = "modem"; 2571 qcom,remote-pid = <1>; 2572 }; 2573 }; 2574 2575 cci0: cci@ac15000 { 2576 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2577 reg = <0 0x0ac15000 0 0x1000>; 2578 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2579 power-domains = <&camcc TITAN_TOP_GDSC>; 2580 2581 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2582 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2583 <&camcc CAM_CC_CPAS_AHB_CLK>, 2584 <&camcc CAM_CC_CCI_0_CLK>, 2585 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2586 clock-names = "camnoc_axi", 2587 "slow_ahb_src", 2588 "cpas_ahb", 2589 "cci", 2590 "cci_src"; 2591 pinctrl-0 = <&cci0_default &cci1_default>; 2592 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2593 pinctrl-names = "default", "sleep"; 2594 2595 status = "disabled"; 2596 #address-cells = <1>; 2597 #size-cells = <0>; 2598 2599 cci0_i2c0: i2c-bus@0 { 2600 reg = <0>; 2601 clock-frequency = <1000000>; 2602 #address-cells = <1>; 2603 #size-cells = <0>; 2604 }; 2605 2606 cci0_i2c1: i2c-bus@1 { 2607 reg = <1>; 2608 clock-frequency = <1000000>; 2609 #address-cells = <1>; 2610 #size-cells = <0>; 2611 }; 2612 }; 2613 2614 cci1: cci@ac16000 { 2615 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2616 reg = <0 0x0ac16000 0 0x1000>; 2617 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2618 power-domains = <&camcc TITAN_TOP_GDSC>; 2619 2620 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2621 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2622 <&camcc CAM_CC_CPAS_AHB_CLK>, 2623 <&camcc CAM_CC_CCI_1_CLK>, 2624 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2625 clock-names = "camnoc_axi", 2626 "slow_ahb_src", 2627 "cpas_ahb", 2628 "cci", 2629 "cci_src"; 2630 pinctrl-0 = <&cci2_default &cci3_default>; 2631 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2632 pinctrl-names = "default", "sleep"; 2633 2634 status = "disabled"; 2635 #address-cells = <1>; 2636 #size-cells = <0>; 2637 2638 cci1_i2c0: i2c-bus@0 { 2639 reg = <0>; 2640 clock-frequency = <1000000>; 2641 #address-cells = <1>; 2642 #size-cells = <0>; 2643 }; 2644 2645 cci1_i2c1: i2c-bus@1 { 2646 reg = <1>; 2647 clock-frequency = <1000000>; 2648 #address-cells = <1>; 2649 #size-cells = <0>; 2650 }; 2651 }; 2652 2653 camcc: clock-controller@ade0000 { 2654 compatible = "qcom,sm8450-camcc"; 2655 reg = <0 0x0ade0000 0 0x20000>; 2656 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2657 <&rpmhcc RPMH_CXO_CLK>, 2658 <&rpmhcc RPMH_CXO_CLK_A>, 2659 <&sleep_clk>; 2660 power-domains = <&rpmhpd SM8450_MMCX>; 2661 required-opps = <&rpmhpd_opp_low_svs>; 2662 #clock-cells = <1>; 2663 #reset-cells = <1>; 2664 #power-domain-cells = <1>; 2665 status = "disabled"; 2666 }; 2667 2668 mdss: display-subsystem@ae00000 { 2669 compatible = "qcom,sm8450-mdss"; 2670 reg = <0 0x0ae00000 0 0x1000>; 2671 reg-names = "mdss"; 2672 2673 /* same path used twice */ 2674 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2675 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; 2676 interconnect-names = "mdp0-mem", "mdp1-mem"; 2677 2678 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2679 2680 power-domains = <&dispcc MDSS_GDSC>; 2681 2682 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2683 <&gcc GCC_DISP_HF_AXI_CLK>, 2684 <&gcc GCC_DISP_SF_AXI_CLK>, 2685 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2686 2687 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2688 interrupt-controller; 2689 #interrupt-cells = <1>; 2690 2691 iommus = <&apps_smmu 0x2800 0x402>; 2692 2693 #address-cells = <2>; 2694 #size-cells = <2>; 2695 ranges; 2696 2697 status = "disabled"; 2698 2699 mdss_mdp: display-controller@ae01000 { 2700 compatible = "qcom,sm8450-dpu"; 2701 reg = <0 0x0ae01000 0 0x8f000>, 2702 <0 0x0aeb0000 0 0x2008>; 2703 reg-names = "mdp", "vbif"; 2704 2705 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2706 <&gcc GCC_DISP_SF_AXI_CLK>, 2707 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2708 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2709 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2710 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2711 clock-names = "bus", 2712 "nrt_bus", 2713 "iface", 2714 "lut", 2715 "core", 2716 "vsync"; 2717 2718 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2719 assigned-clock-rates = <19200000>; 2720 2721 operating-points-v2 = <&mdp_opp_table>; 2722 power-domains = <&rpmhpd SM8450_MMCX>; 2723 2724 interrupt-parent = <&mdss>; 2725 interrupts = <0>; 2726 2727 ports { 2728 #address-cells = <1>; 2729 #size-cells = <0>; 2730 2731 port@0 { 2732 reg = <0>; 2733 dpu_intf1_out: endpoint { 2734 remote-endpoint = <&mdss_dsi0_in>; 2735 }; 2736 }; 2737 2738 port@1 { 2739 reg = <1>; 2740 dpu_intf2_out: endpoint { 2741 remote-endpoint = <&mdss_dsi1_in>; 2742 }; 2743 }; 2744 2745 port@2 { 2746 reg = <2>; 2747 dpu_intf0_out: endpoint { 2748 remote-endpoint = <&mdss_dp0_in>; 2749 }; 2750 }; 2751 }; 2752 2753 mdp_opp_table: opp-table { 2754 compatible = "operating-points-v2"; 2755 2756 opp-172000000 { 2757 opp-hz = /bits/ 64 <172000000>; 2758 required-opps = <&rpmhpd_opp_low_svs_d1>; 2759 }; 2760 2761 opp-200000000 { 2762 opp-hz = /bits/ 64 <200000000>; 2763 required-opps = <&rpmhpd_opp_low_svs>; 2764 }; 2765 2766 opp-325000000 { 2767 opp-hz = /bits/ 64 <325000000>; 2768 required-opps = <&rpmhpd_opp_svs>; 2769 }; 2770 2771 opp-375000000 { 2772 opp-hz = /bits/ 64 <375000000>; 2773 required-opps = <&rpmhpd_opp_svs_l1>; 2774 }; 2775 2776 opp-500000000 { 2777 opp-hz = /bits/ 64 <500000000>; 2778 required-opps = <&rpmhpd_opp_nom>; 2779 }; 2780 }; 2781 }; 2782 2783 mdss_dp0: displayport-controller@ae90000 { 2784 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2785 reg = <0 0xae90000 0 0x200>, 2786 <0 0xae90200 0 0x200>, 2787 <0 0xae90400 0 0xc00>, 2788 <0 0xae91000 0 0x400>, 2789 <0 0xae91400 0 0x400>; 2790 interrupt-parent = <&mdss>; 2791 interrupts = <12>; 2792 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2793 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2794 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2795 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2796 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2797 clock-names = "core_iface", 2798 "core_aux", 2799 "ctrl_link", 2800 "ctrl_link_iface", 2801 "stream_pixel"; 2802 2803 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2804 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2805 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2806 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2807 2808 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2809 phy-names = "dp"; 2810 2811 #sound-dai-cells = <0>; 2812 2813 operating-points-v2 = <&dp_opp_table>; 2814 power-domains = <&rpmhpd SM8450_MMCX>; 2815 2816 status = "disabled"; 2817 2818 ports { 2819 #address-cells = <1>; 2820 #size-cells = <0>; 2821 2822 port@0 { 2823 reg = <0>; 2824 mdss_dp0_in: endpoint { 2825 remote-endpoint = <&dpu_intf0_out>; 2826 }; 2827 }; 2828 }; 2829 2830 dp_opp_table: opp-table { 2831 compatible = "operating-points-v2"; 2832 2833 opp-160000000 { 2834 opp-hz = /bits/ 64 <160000000>; 2835 required-opps = <&rpmhpd_opp_low_svs>; 2836 }; 2837 2838 opp-270000000 { 2839 opp-hz = /bits/ 64 <270000000>; 2840 required-opps = <&rpmhpd_opp_svs>; 2841 }; 2842 2843 opp-540000000 { 2844 opp-hz = /bits/ 64 <540000000>; 2845 required-opps = <&rpmhpd_opp_svs_l1>; 2846 }; 2847 2848 opp-810000000 { 2849 opp-hz = /bits/ 64 <810000000>; 2850 required-opps = <&rpmhpd_opp_nom>; 2851 }; 2852 }; 2853 }; 2854 2855 mdss_dsi0: dsi@ae94000 { 2856 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2857 reg = <0 0x0ae94000 0 0x400>; 2858 reg-names = "dsi_ctrl"; 2859 2860 interrupt-parent = <&mdss>; 2861 interrupts = <4>; 2862 2863 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2864 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2865 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2866 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2867 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2868 <&gcc GCC_DISP_HF_AXI_CLK>; 2869 clock-names = "byte", 2870 "byte_intf", 2871 "pixel", 2872 "core", 2873 "iface", 2874 "bus"; 2875 2876 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2877 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2878 2879 operating-points-v2 = <&mdss_dsi_opp_table>; 2880 power-domains = <&rpmhpd SM8450_MMCX>; 2881 2882 phys = <&mdss_dsi0_phy>; 2883 phy-names = "dsi"; 2884 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 2888 status = "disabled"; 2889 2890 ports { 2891 #address-cells = <1>; 2892 #size-cells = <0>; 2893 2894 port@0 { 2895 reg = <0>; 2896 mdss_dsi0_in: endpoint { 2897 remote-endpoint = <&dpu_intf1_out>; 2898 }; 2899 }; 2900 2901 port@1 { 2902 reg = <1>; 2903 mdss_dsi0_out: endpoint { 2904 }; 2905 }; 2906 }; 2907 2908 mdss_dsi_opp_table: opp-table { 2909 compatible = "operating-points-v2"; 2910 2911 opp-187500000 { 2912 opp-hz = /bits/ 64 <187500000>; 2913 required-opps = <&rpmhpd_opp_low_svs>; 2914 }; 2915 2916 opp-300000000 { 2917 opp-hz = /bits/ 64 <300000000>; 2918 required-opps = <&rpmhpd_opp_svs>; 2919 }; 2920 2921 opp-358000000 { 2922 opp-hz = /bits/ 64 <358000000>; 2923 required-opps = <&rpmhpd_opp_svs_l1>; 2924 }; 2925 }; 2926 }; 2927 2928 mdss_dsi0_phy: phy@ae94400 { 2929 compatible = "qcom,sm8450-dsi-phy-5nm"; 2930 reg = <0 0x0ae94400 0 0x200>, 2931 <0 0x0ae94600 0 0x280>, 2932 <0 0x0ae94900 0 0x260>; 2933 reg-names = "dsi_phy", 2934 "dsi_phy_lane", 2935 "dsi_pll"; 2936 2937 #clock-cells = <1>; 2938 #phy-cells = <0>; 2939 2940 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2941 <&rpmhcc RPMH_CXO_CLK>; 2942 clock-names = "iface", "ref"; 2943 2944 status = "disabled"; 2945 }; 2946 2947 mdss_dsi1: dsi@ae96000 { 2948 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2949 reg = <0 0x0ae96000 0 0x400>; 2950 reg-names = "dsi_ctrl"; 2951 2952 interrupt-parent = <&mdss>; 2953 interrupts = <5>; 2954 2955 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2956 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2957 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2958 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2959 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2960 <&gcc GCC_DISP_HF_AXI_CLK>; 2961 clock-names = "byte", 2962 "byte_intf", 2963 "pixel", 2964 "core", 2965 "iface", 2966 "bus"; 2967 2968 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2969 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2970 2971 operating-points-v2 = <&mdss_dsi_opp_table>; 2972 power-domains = <&rpmhpd SM8450_MMCX>; 2973 2974 phys = <&mdss_dsi1_phy>; 2975 phy-names = "dsi"; 2976 2977 #address-cells = <1>; 2978 #size-cells = <0>; 2979 2980 status = "disabled"; 2981 2982 ports { 2983 #address-cells = <1>; 2984 #size-cells = <0>; 2985 2986 port@0 { 2987 reg = <0>; 2988 mdss_dsi1_in: endpoint { 2989 remote-endpoint = <&dpu_intf2_out>; 2990 }; 2991 }; 2992 2993 port@1 { 2994 reg = <1>; 2995 mdss_dsi1_out: endpoint { 2996 }; 2997 }; 2998 }; 2999 }; 3000 3001 mdss_dsi1_phy: phy@ae96400 { 3002 compatible = "qcom,sm8450-dsi-phy-5nm"; 3003 reg = <0 0x0ae96400 0 0x200>, 3004 <0 0x0ae96600 0 0x280>, 3005 <0 0x0ae96900 0 0x260>; 3006 reg-names = "dsi_phy", 3007 "dsi_phy_lane", 3008 "dsi_pll"; 3009 3010 #clock-cells = <1>; 3011 #phy-cells = <0>; 3012 3013 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3014 <&rpmhcc RPMH_CXO_CLK>; 3015 clock-names = "iface", "ref"; 3016 3017 status = "disabled"; 3018 }; 3019 }; 3020 3021 dispcc: clock-controller@af00000 { 3022 compatible = "qcom,sm8450-dispcc"; 3023 reg = <0 0x0af00000 0 0x20000>; 3024 clocks = <&rpmhcc RPMH_CXO_CLK>, 3025 <&rpmhcc RPMH_CXO_CLK_A>, 3026 <&gcc GCC_DISP_AHB_CLK>, 3027 <&sleep_clk>, 3028 <&mdss_dsi0_phy 0>, 3029 <&mdss_dsi0_phy 1>, 3030 <&mdss_dsi1_phy 0>, 3031 <&mdss_dsi1_phy 1>, 3032 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3033 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3034 <0>, /* dp1 */ 3035 <0>, 3036 <0>, /* dp2 */ 3037 <0>, 3038 <0>, /* dp3 */ 3039 <0>; 3040 power-domains = <&rpmhpd SM8450_MMCX>; 3041 required-opps = <&rpmhpd_opp_low_svs>; 3042 #clock-cells = <1>; 3043 #reset-cells = <1>; 3044 #power-domain-cells = <1>; 3045 status = "disabled"; 3046 }; 3047 3048 pdc: interrupt-controller@b220000 { 3049 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3050 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3051 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3052 <94 609 31>, <125 63 1>, <126 716 12>; 3053 #interrupt-cells = <2>; 3054 interrupt-parent = <&intc>; 3055 interrupt-controller; 3056 }; 3057 3058 tsens0: thermal-sensor@c263000 { 3059 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3060 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3061 <0 0x0c222000 0 0x1000>; /* SROT */ 3062 #qcom,sensors = <16>; 3063 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3065 interrupt-names = "uplow", "critical"; 3066 #thermal-sensor-cells = <1>; 3067 }; 3068 3069 tsens1: thermal-sensor@c265000 { 3070 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3071 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3072 <0 0x0c223000 0 0x1000>; /* SROT */ 3073 #qcom,sensors = <16>; 3074 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3076 interrupt-names = "uplow", "critical"; 3077 #thermal-sensor-cells = <1>; 3078 }; 3079 3080 aoss_qmp: power-management@c300000 { 3081 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3082 reg = <0 0x0c300000 0 0x400>; 3083 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3084 IRQ_TYPE_EDGE_RISING>; 3085 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3086 3087 #clock-cells = <0>; 3088 }; 3089 3090 spmi_bus: spmi@c400000 { 3091 compatible = "qcom,spmi-pmic-arb"; 3092 reg = <0 0x0c400000 0 0x00003000>, 3093 <0 0x0c500000 0 0x00400000>, 3094 <0 0x0c440000 0 0x00080000>, 3095 <0 0x0c4c0000 0 0x00010000>, 3096 <0 0x0c42d000 0 0x00010000>; 3097 reg-names = "core", 3098 "chnls", 3099 "obsrvr", 3100 "intr", 3101 "cnfg"; 3102 interrupt-names = "periph_irq"; 3103 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3104 qcom,ee = <0>; 3105 qcom,channel = <0>; 3106 interrupt-controller; 3107 #interrupt-cells = <4>; 3108 #address-cells = <2>; 3109 #size-cells = <0>; 3110 }; 3111 3112 ipcc: mailbox@ed18000 { 3113 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3114 reg = <0 0x0ed18000 0 0x1000>; 3115 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3116 interrupt-controller; 3117 #interrupt-cells = <3>; 3118 #mbox-cells = <2>; 3119 }; 3120 3121 tlmm: pinctrl@f100000 { 3122 compatible = "qcom,sm8450-tlmm"; 3123 reg = <0 0x0f100000 0 0x300000>; 3124 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3125 gpio-controller; 3126 #gpio-cells = <2>; 3127 interrupt-controller; 3128 #interrupt-cells = <2>; 3129 gpio-ranges = <&tlmm 0 0 211>; 3130 wakeup-parent = <&pdc>; 3131 3132 sdc2_default_state: sdc2-default-state { 3133 clk-pins { 3134 pins = "sdc2_clk"; 3135 drive-strength = <16>; 3136 bias-disable; 3137 }; 3138 3139 cmd-pins { 3140 pins = "sdc2_cmd"; 3141 drive-strength = <16>; 3142 bias-pull-up; 3143 }; 3144 3145 data-pins { 3146 pins = "sdc2_data"; 3147 drive-strength = <16>; 3148 bias-pull-up; 3149 }; 3150 }; 3151 3152 sdc2_sleep_state: sdc2-sleep-state { 3153 clk-pins { 3154 pins = "sdc2_clk"; 3155 drive-strength = <2>; 3156 bias-disable; 3157 }; 3158 3159 cmd-pins { 3160 pins = "sdc2_cmd"; 3161 drive-strength = <2>; 3162 bias-pull-up; 3163 }; 3164 3165 data-pins { 3166 pins = "sdc2_data"; 3167 drive-strength = <2>; 3168 bias-pull-up; 3169 }; 3170 }; 3171 3172 cci0_default: cci0-default-state { 3173 /* SDA, SCL */ 3174 pins = "gpio110", "gpio111"; 3175 function = "cci_i2c"; 3176 drive-strength = <2>; 3177 bias-pull-up; 3178 }; 3179 3180 cci0_sleep: cci0-sleep-state { 3181 /* SDA, SCL */ 3182 pins = "gpio110", "gpio111"; 3183 function = "cci_i2c"; 3184 drive-strength = <2>; 3185 bias-pull-down; 3186 }; 3187 3188 cci1_default: cci1-default-state { 3189 /* SDA, SCL */ 3190 pins = "gpio112", "gpio113"; 3191 function = "cci_i2c"; 3192 drive-strength = <2>; 3193 bias-pull-up; 3194 }; 3195 3196 cci1_sleep: cci1-sleep-state { 3197 /* SDA, SCL */ 3198 pins = "gpio112", "gpio113"; 3199 function = "cci_i2c"; 3200 drive-strength = <2>; 3201 bias-pull-down; 3202 }; 3203 3204 cci2_default: cci2-default-state { 3205 /* SDA, SCL */ 3206 pins = "gpio114", "gpio115"; 3207 function = "cci_i2c"; 3208 drive-strength = <2>; 3209 bias-pull-up; 3210 }; 3211 3212 cci2_sleep: cci2-sleep-state { 3213 /* SDA, SCL */ 3214 pins = "gpio114", "gpio115"; 3215 function = "cci_i2c"; 3216 drive-strength = <2>; 3217 bias-pull-down; 3218 }; 3219 3220 cci3_default: cci3-default-state { 3221 /* SDA, SCL */ 3222 pins = "gpio208", "gpio209"; 3223 function = "cci_i2c"; 3224 drive-strength = <2>; 3225 bias-pull-up; 3226 }; 3227 3228 cci3_sleep: cci3-sleep-state { 3229 /* SDA, SCL */ 3230 pins = "gpio208", "gpio209"; 3231 function = "cci_i2c"; 3232 drive-strength = <2>; 3233 bias-pull-down; 3234 }; 3235 3236 pcie0_default_state: pcie0-default-state { 3237 perst-pins { 3238 pins = "gpio94"; 3239 function = "gpio"; 3240 drive-strength = <2>; 3241 bias-pull-down; 3242 }; 3243 3244 clkreq-pins { 3245 pins = "gpio95"; 3246 function = "pcie0_clkreqn"; 3247 drive-strength = <2>; 3248 bias-pull-up; 3249 }; 3250 3251 wake-pins { 3252 pins = "gpio96"; 3253 function = "gpio"; 3254 drive-strength = <2>; 3255 bias-pull-up; 3256 }; 3257 }; 3258 3259 pcie1_default_state: pcie1-default-state { 3260 perst-pins { 3261 pins = "gpio97"; 3262 function = "gpio"; 3263 drive-strength = <2>; 3264 bias-pull-down; 3265 }; 3266 3267 clkreq-pins { 3268 pins = "gpio98"; 3269 function = "pcie1_clkreqn"; 3270 drive-strength = <2>; 3271 bias-pull-up; 3272 }; 3273 3274 wake-pins { 3275 pins = "gpio99"; 3276 function = "gpio"; 3277 drive-strength = <2>; 3278 bias-pull-up; 3279 }; 3280 }; 3281 3282 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3283 pins = "gpio0", "gpio1"; 3284 function = "qup0"; 3285 }; 3286 3287 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3288 pins = "gpio4", "gpio5"; 3289 function = "qup1"; 3290 }; 3291 3292 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3293 pins = "gpio8", "gpio9"; 3294 function = "qup2"; 3295 }; 3296 3297 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3298 pins = "gpio12", "gpio13"; 3299 function = "qup3"; 3300 }; 3301 3302 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3303 pins = "gpio16", "gpio17"; 3304 function = "qup4"; 3305 }; 3306 3307 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3308 pins = "gpio206", "gpio207"; 3309 function = "qup5"; 3310 }; 3311 3312 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3313 pins = "gpio20", "gpio21"; 3314 function = "qup6"; 3315 }; 3316 3317 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3318 pins = "gpio28", "gpio29"; 3319 function = "qup8"; 3320 }; 3321 3322 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3323 pins = "gpio32", "gpio33"; 3324 function = "qup9"; 3325 }; 3326 3327 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3328 pins = "gpio36", "gpio37"; 3329 function = "qup10"; 3330 }; 3331 3332 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3333 pins = "gpio40", "gpio41"; 3334 function = "qup11"; 3335 }; 3336 3337 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3338 pins = "gpio44", "gpio45"; 3339 function = "qup12"; 3340 }; 3341 3342 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3343 pins = "gpio48", "gpio49"; 3344 function = "qup13"; 3345 drive-strength = <2>; 3346 bias-pull-up; 3347 }; 3348 3349 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3350 pins = "gpio52", "gpio53"; 3351 function = "qup14"; 3352 drive-strength = <2>; 3353 bias-pull-up; 3354 }; 3355 3356 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3357 pins = "gpio56", "gpio57"; 3358 function = "qup15"; 3359 }; 3360 3361 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3362 pins = "gpio60", "gpio61"; 3363 function = "qup16"; 3364 }; 3365 3366 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3367 pins = "gpio64", "gpio65"; 3368 function = "qup17"; 3369 }; 3370 3371 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3372 pins = "gpio68", "gpio69"; 3373 function = "qup18"; 3374 }; 3375 3376 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3377 pins = "gpio72", "gpio73"; 3378 function = "qup19"; 3379 }; 3380 3381 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3382 pins = "gpio76", "gpio77"; 3383 function = "qup20"; 3384 }; 3385 3386 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3387 pins = "gpio80", "gpio81"; 3388 function = "qup21"; 3389 }; 3390 3391 qup_spi0_cs: qup-spi0-cs-state { 3392 pins = "gpio3"; 3393 function = "qup0"; 3394 }; 3395 3396 qup_spi0_data_clk: qup-spi0-data-clk-state { 3397 pins = "gpio0", "gpio1", "gpio2"; 3398 function = "qup0"; 3399 }; 3400 3401 qup_spi1_cs: qup-spi1-cs-state { 3402 pins = "gpio7"; 3403 function = "qup1"; 3404 }; 3405 3406 qup_spi1_data_clk: qup-spi1-data-clk-state { 3407 pins = "gpio4", "gpio5", "gpio6"; 3408 function = "qup1"; 3409 }; 3410 3411 qup_spi2_cs: qup-spi2-cs-state { 3412 pins = "gpio11"; 3413 function = "qup2"; 3414 }; 3415 3416 qup_spi2_data_clk: qup-spi2-data-clk-state { 3417 pins = "gpio8", "gpio9", "gpio10"; 3418 function = "qup2"; 3419 }; 3420 3421 qup_spi3_cs: qup-spi3-cs-state { 3422 pins = "gpio15"; 3423 function = "qup3"; 3424 }; 3425 3426 qup_spi3_data_clk: qup-spi3-data-clk-state { 3427 pins = "gpio12", "gpio13", "gpio14"; 3428 function = "qup3"; 3429 }; 3430 3431 qup_spi4_cs: qup-spi4-cs-state { 3432 pins = "gpio19"; 3433 function = "qup4"; 3434 drive-strength = <6>; 3435 bias-disable; 3436 }; 3437 3438 qup_spi4_data_clk: qup-spi4-data-clk-state { 3439 pins = "gpio16", "gpio17", "gpio18"; 3440 function = "qup4"; 3441 }; 3442 3443 qup_spi5_cs: qup-spi5-cs-state { 3444 pins = "gpio85"; 3445 function = "qup5"; 3446 }; 3447 3448 qup_spi5_data_clk: qup-spi5-data-clk-state { 3449 pins = "gpio206", "gpio207", "gpio84"; 3450 function = "qup5"; 3451 }; 3452 3453 qup_spi6_cs: qup-spi6-cs-state { 3454 pins = "gpio23"; 3455 function = "qup6"; 3456 }; 3457 3458 qup_spi6_data_clk: qup-spi6-data-clk-state { 3459 pins = "gpio20", "gpio21", "gpio22"; 3460 function = "qup6"; 3461 }; 3462 3463 qup_spi8_cs: qup-spi8-cs-state { 3464 pins = "gpio31"; 3465 function = "qup8"; 3466 }; 3467 3468 qup_spi8_data_clk: qup-spi8-data-clk-state { 3469 pins = "gpio28", "gpio29", "gpio30"; 3470 function = "qup8"; 3471 }; 3472 3473 qup_spi9_cs: qup-spi9-cs-state { 3474 pins = "gpio35"; 3475 function = "qup9"; 3476 }; 3477 3478 qup_spi9_data_clk: qup-spi9-data-clk-state { 3479 pins = "gpio32", "gpio33", "gpio34"; 3480 function = "qup9"; 3481 }; 3482 3483 qup_spi10_cs: qup-spi10-cs-state { 3484 pins = "gpio39"; 3485 function = "qup10"; 3486 }; 3487 3488 qup_spi10_data_clk: qup-spi10-data-clk-state { 3489 pins = "gpio36", "gpio37", "gpio38"; 3490 function = "qup10"; 3491 }; 3492 3493 qup_spi11_cs: qup-spi11-cs-state { 3494 pins = "gpio43"; 3495 function = "qup11"; 3496 }; 3497 3498 qup_spi11_data_clk: qup-spi11-data-clk-state { 3499 pins = "gpio40", "gpio41", "gpio42"; 3500 function = "qup11"; 3501 }; 3502 3503 qup_spi12_cs: qup-spi12-cs-state { 3504 pins = "gpio47"; 3505 function = "qup12"; 3506 }; 3507 3508 qup_spi12_data_clk: qup-spi12-data-clk-state { 3509 pins = "gpio44", "gpio45", "gpio46"; 3510 function = "qup12"; 3511 }; 3512 3513 qup_spi13_cs: qup-spi13-cs-state { 3514 pins = "gpio51"; 3515 function = "qup13"; 3516 }; 3517 3518 qup_spi13_data_clk: qup-spi13-data-clk-state { 3519 pins = "gpio48", "gpio49", "gpio50"; 3520 function = "qup13"; 3521 }; 3522 3523 qup_spi14_cs: qup-spi14-cs-state { 3524 pins = "gpio55"; 3525 function = "qup14"; 3526 }; 3527 3528 qup_spi14_data_clk: qup-spi14-data-clk-state { 3529 pins = "gpio52", "gpio53", "gpio54"; 3530 function = "qup14"; 3531 }; 3532 3533 qup_spi15_cs: qup-spi15-cs-state { 3534 pins = "gpio59"; 3535 function = "qup15"; 3536 }; 3537 3538 qup_spi15_data_clk: qup-spi15-data-clk-state { 3539 pins = "gpio56", "gpio57", "gpio58"; 3540 function = "qup15"; 3541 }; 3542 3543 qup_spi16_cs: qup-spi16-cs-state { 3544 pins = "gpio63"; 3545 function = "qup16"; 3546 }; 3547 3548 qup_spi16_data_clk: qup-spi16-data-clk-state { 3549 pins = "gpio60", "gpio61", "gpio62"; 3550 function = "qup16"; 3551 }; 3552 3553 qup_spi17_cs: qup-spi17-cs-state { 3554 pins = "gpio67"; 3555 function = "qup17"; 3556 }; 3557 3558 qup_spi17_data_clk: qup-spi17-data-clk-state { 3559 pins = "gpio64", "gpio65", "gpio66"; 3560 function = "qup17"; 3561 }; 3562 3563 qup_spi18_cs: qup-spi18-cs-state { 3564 pins = "gpio71"; 3565 function = "qup18"; 3566 drive-strength = <6>; 3567 bias-disable; 3568 }; 3569 3570 qup_spi18_data_clk: qup-spi18-data-clk-state { 3571 pins = "gpio68", "gpio69", "gpio70"; 3572 function = "qup18"; 3573 drive-strength = <6>; 3574 bias-disable; 3575 }; 3576 3577 qup_spi19_cs: qup-spi19-cs-state { 3578 pins = "gpio75"; 3579 function = "qup19"; 3580 drive-strength = <6>; 3581 bias-disable; 3582 }; 3583 3584 qup_spi19_data_clk: qup-spi19-data-clk-state { 3585 pins = "gpio72", "gpio73", "gpio74"; 3586 function = "qup19"; 3587 drive-strength = <6>; 3588 bias-disable; 3589 }; 3590 3591 qup_spi20_cs: qup-spi20-cs-state { 3592 pins = "gpio79"; 3593 function = "qup20"; 3594 }; 3595 3596 qup_spi20_data_clk: qup-spi20-data-clk-state { 3597 pins = "gpio76", "gpio77", "gpio78"; 3598 function = "qup20"; 3599 }; 3600 3601 qup_spi21_cs: qup-spi21-cs-state { 3602 pins = "gpio83"; 3603 function = "qup21"; 3604 }; 3605 3606 qup_spi21_data_clk: qup-spi21-data-clk-state { 3607 pins = "gpio80", "gpio81", "gpio82"; 3608 function = "qup21"; 3609 }; 3610 3611 qup_uart7_rx: qup-uart7-rx-state { 3612 pins = "gpio26"; 3613 function = "qup7"; 3614 drive-strength = <2>; 3615 bias-disable; 3616 }; 3617 3618 qup_uart7_tx: qup-uart7-tx-state { 3619 pins = "gpio27"; 3620 function = "qup7"; 3621 drive-strength = <2>; 3622 bias-disable; 3623 }; 3624 3625 qup_uart20_default: qup-uart20-default-state { 3626 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3627 function = "qup20"; 3628 }; 3629 }; 3630 3631 lpass_tlmm: pinctrl@3440000 { 3632 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3633 reg = <0 0x03440000 0x0 0x20000>, 3634 <0 0x034d0000 0x0 0x10000>; 3635 gpio-controller; 3636 #gpio-cells = <2>; 3637 gpio-ranges = <&lpass_tlmm 0 0 23>; 3638 3639 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3640 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3641 clock-names = "core", "audio"; 3642 3643 tx_swr_active: tx-swr-active-state { 3644 clk-pins { 3645 pins = "gpio0"; 3646 function = "swr_tx_clk"; 3647 drive-strength = <2>; 3648 slew-rate = <1>; 3649 bias-disable; 3650 }; 3651 3652 data-pins { 3653 pins = "gpio1", "gpio2", "gpio14"; 3654 function = "swr_tx_data"; 3655 drive-strength = <2>; 3656 slew-rate = <1>; 3657 bias-bus-hold; 3658 }; 3659 }; 3660 3661 rx_swr_active: rx-swr-active-state { 3662 clk-pins { 3663 pins = "gpio3"; 3664 function = "swr_rx_clk"; 3665 drive-strength = <2>; 3666 slew-rate = <1>; 3667 bias-disable; 3668 }; 3669 3670 data-pins { 3671 pins = "gpio4", "gpio5"; 3672 function = "swr_rx_data"; 3673 drive-strength = <2>; 3674 slew-rate = <1>; 3675 bias-bus-hold; 3676 }; 3677 }; 3678 3679 dmic01_default: dmic01-default-state { 3680 clk-pins { 3681 pins = "gpio6"; 3682 function = "dmic1_clk"; 3683 drive-strength = <8>; 3684 output-high; 3685 }; 3686 3687 data-pins { 3688 pins = "gpio7"; 3689 function = "dmic1_data"; 3690 drive-strength = <8>; 3691 }; 3692 }; 3693 3694 dmic02_default: dmic02-default-state { 3695 clk-pins { 3696 pins = "gpio8"; 3697 function = "dmic2_clk"; 3698 drive-strength = <8>; 3699 output-high; 3700 }; 3701 3702 data-pins { 3703 pins = "gpio9"; 3704 function = "dmic2_data"; 3705 drive-strength = <8>; 3706 }; 3707 }; 3708 3709 wsa_swr_active: wsa-swr-active-state { 3710 clk-pins { 3711 pins = "gpio10"; 3712 function = "wsa_swr_clk"; 3713 drive-strength = <2>; 3714 slew-rate = <1>; 3715 bias-disable; 3716 }; 3717 3718 data-pins { 3719 pins = "gpio11"; 3720 function = "wsa_swr_data"; 3721 drive-strength = <2>; 3722 slew-rate = <1>; 3723 bias-bus-hold; 3724 }; 3725 }; 3726 3727 wsa2_swr_active: wsa2-swr-active-state { 3728 clk-pins { 3729 pins = "gpio15"; 3730 function = "wsa2_swr_clk"; 3731 drive-strength = <2>; 3732 slew-rate = <1>; 3733 bias-disable; 3734 }; 3735 3736 data-pins { 3737 pins = "gpio16"; 3738 function = "wsa2_swr_data"; 3739 drive-strength = <2>; 3740 slew-rate = <1>; 3741 bias-bus-hold; 3742 }; 3743 }; 3744 }; 3745 3746 sram@146aa000 { 3747 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3748 reg = <0 0x146aa000 0 0x1000>; 3749 ranges = <0 0 0x146aa000 0x1000>; 3750 3751 #address-cells = <1>; 3752 #size-cells = <1>; 3753 3754 pil-reloc@94c { 3755 compatible = "qcom,pil-reloc-info"; 3756 reg = <0x94c 0xc8>; 3757 }; 3758 }; 3759 3760 apps_smmu: iommu@15000000 { 3761 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3762 reg = <0 0x15000000 0 0x100000>; 3763 #iommu-cells = <2>; 3764 #global-interrupts = <1>; 3765 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3862 }; 3863 3864 intc: interrupt-controller@17100000 { 3865 compatible = "arm,gic-v3"; 3866 #interrupt-cells = <3>; 3867 interrupt-controller; 3868 #redistributor-regions = <1>; 3869 redistributor-stride = <0x0 0x40000>; 3870 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3871 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3872 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3873 #address-cells = <2>; 3874 #size-cells = <2>; 3875 ranges; 3876 3877 gic_its: msi-controller@17140000 { 3878 compatible = "arm,gic-v3-its"; 3879 reg = <0x0 0x17140000 0x0 0x20000>; 3880 msi-controller; 3881 #msi-cells = <1>; 3882 }; 3883 }; 3884 3885 timer@17420000 { 3886 compatible = "arm,armv7-timer-mem"; 3887 #address-cells = <1>; 3888 #size-cells = <1>; 3889 ranges = <0 0 0 0x20000000>; 3890 reg = <0x0 0x17420000 0x0 0x1000>; 3891 clock-frequency = <19200000>; 3892 3893 frame@17421000 { 3894 frame-number = <0>; 3895 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3897 reg = <0x17421000 0x1000>, 3898 <0x17422000 0x1000>; 3899 }; 3900 3901 frame@17423000 { 3902 frame-number = <1>; 3903 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3904 reg = <0x17423000 0x1000>; 3905 status = "disabled"; 3906 }; 3907 3908 frame@17425000 { 3909 frame-number = <2>; 3910 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3911 reg = <0x17425000 0x1000>; 3912 status = "disabled"; 3913 }; 3914 3915 frame@17427000 { 3916 frame-number = <3>; 3917 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3918 reg = <0x17427000 0x1000>; 3919 status = "disabled"; 3920 }; 3921 3922 frame@17429000 { 3923 frame-number = <4>; 3924 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3925 reg = <0x17429000 0x1000>; 3926 status = "disabled"; 3927 }; 3928 3929 frame@1742b000 { 3930 frame-number = <5>; 3931 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3932 reg = <0x1742b000 0x1000>; 3933 status = "disabled"; 3934 }; 3935 3936 frame@1742d000 { 3937 frame-number = <6>; 3938 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3939 reg = <0x1742d000 0x1000>; 3940 status = "disabled"; 3941 }; 3942 }; 3943 3944 apps_rsc: rsc@17a00000 { 3945 label = "apps_rsc"; 3946 compatible = "qcom,rpmh-rsc"; 3947 reg = <0x0 0x17a00000 0x0 0x10000>, 3948 <0x0 0x17a10000 0x0 0x10000>, 3949 <0x0 0x17a20000 0x0 0x10000>, 3950 <0x0 0x17a30000 0x0 0x10000>; 3951 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3952 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3955 qcom,tcs-offset = <0xd00>; 3956 qcom,drv-id = <2>; 3957 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3958 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3959 power-domains = <&CLUSTER_PD>; 3960 3961 apps_bcm_voter: bcm-voter { 3962 compatible = "qcom,bcm-voter"; 3963 }; 3964 3965 rpmhcc: clock-controller { 3966 compatible = "qcom,sm8450-rpmh-clk"; 3967 #clock-cells = <1>; 3968 clock-names = "xo"; 3969 clocks = <&xo_board>; 3970 }; 3971 3972 rpmhpd: power-controller { 3973 compatible = "qcom,sm8450-rpmhpd"; 3974 #power-domain-cells = <1>; 3975 operating-points-v2 = <&rpmhpd_opp_table>; 3976 3977 rpmhpd_opp_table: opp-table { 3978 compatible = "operating-points-v2"; 3979 3980 rpmhpd_opp_ret: opp1 { 3981 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3982 }; 3983 3984 rpmhpd_opp_min_svs: opp2 { 3985 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3986 }; 3987 3988 rpmhpd_opp_low_svs_d1: opp3 { 3989 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3990 }; 3991 3992 rpmhpd_opp_low_svs: opp4 { 3993 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3994 }; 3995 3996 rpmhpd_opp_svs: opp5 { 3997 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3998 }; 3999 4000 rpmhpd_opp_svs_l1: opp6 { 4001 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4002 }; 4003 4004 rpmhpd_opp_nom: opp7 { 4005 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4006 }; 4007 4008 rpmhpd_opp_nom_l1: opp8 { 4009 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4010 }; 4011 4012 rpmhpd_opp_nom_l2: opp9 { 4013 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4014 }; 4015 4016 rpmhpd_opp_turbo: opp10 { 4017 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4018 }; 4019 4020 rpmhpd_opp_turbo_l1: opp11 { 4021 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4022 }; 4023 }; 4024 }; 4025 }; 4026 4027 cpufreq_hw: cpufreq@17d91000 { 4028 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4029 reg = <0 0x17d91000 0 0x1000>, 4030 <0 0x17d92000 0 0x1000>, 4031 <0 0x17d93000 0 0x1000>; 4032 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4033 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4034 clock-names = "xo", "alternate"; 4035 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4038 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4039 #freq-domain-cells = <1>; 4040 #clock-cells = <1>; 4041 }; 4042 4043 gem_noc: interconnect@19100000 { 4044 compatible = "qcom,sm8450-gem-noc"; 4045 reg = <0 0x19100000 0 0xbb800>; 4046 #interconnect-cells = <2>; 4047 qcom,bcm-voters = <&apps_bcm_voter>; 4048 }; 4049 4050 system-cache-controller@19200000 { 4051 compatible = "qcom,sm8450-llcc"; 4052 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4053 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4054 <0 0x19a00000 0 0x80000>; 4055 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4056 "llcc3_base", "llcc_broadcast_base"; 4057 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4058 }; 4059 4060 ufs_mem_hc: ufshc@1d84000 { 4061 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4062 "jedec,ufs-2.0"; 4063 reg = <0 0x01d84000 0 0x3000>, 4064 <0 0x01d88000 0 0x8000>; 4065 reg-names = "std", "ice"; 4066 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4067 phys = <&ufs_mem_phy_lanes>; 4068 phy-names = "ufsphy"; 4069 lanes-per-direction = <2>; 4070 #reset-cells = <1>; 4071 resets = <&gcc GCC_UFS_PHY_BCR>; 4072 reset-names = "rst"; 4073 4074 power-domains = <&gcc UFS_PHY_GDSC>; 4075 4076 iommus = <&apps_smmu 0xe0 0x0>; 4077 dma-coherent; 4078 4079 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4081 interconnect-names = "ufs-ddr", "cpu-ufs"; 4082 clock-names = 4083 "core_clk", 4084 "bus_aggr_clk", 4085 "iface_clk", 4086 "core_clk_unipro", 4087 "ref_clk", 4088 "tx_lane0_sync_clk", 4089 "rx_lane0_sync_clk", 4090 "rx_lane1_sync_clk", 4091 "ice_core_clk"; 4092 clocks = 4093 <&gcc GCC_UFS_PHY_AXI_CLK>, 4094 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4095 <&gcc GCC_UFS_PHY_AHB_CLK>, 4096 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4097 <&rpmhcc RPMH_CXO_CLK>, 4098 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4099 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4100 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 4101 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4102 freq-table-hz = 4103 <75000000 300000000>, 4104 <0 0>, 4105 <0 0>, 4106 <75000000 300000000>, 4107 <75000000 300000000>, 4108 <0 0>, 4109 <0 0>, 4110 <0 0>, 4111 <75000000 300000000>; 4112 status = "disabled"; 4113 }; 4114 4115 ufs_mem_phy: phy@1d87000 { 4116 compatible = "qcom,sm8450-qmp-ufs-phy"; 4117 reg = <0 0x01d87000 0 0x1c4>; 4118 #address-cells = <2>; 4119 #size-cells = <2>; 4120 ranges; 4121 clock-names = "ref", "ref_aux", "qref"; 4122 clocks = <&rpmhcc RPMH_CXO_CLK>, 4123 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4124 <&gcc GCC_UFS_0_CLKREF_EN>; 4125 4126 resets = <&ufs_mem_hc 0>; 4127 reset-names = "ufsphy"; 4128 status = "disabled"; 4129 4130 ufs_mem_phy_lanes: phy@1d87400 { 4131 reg = <0 0x01d87400 0 0x188>, 4132 <0 0x01d87600 0 0x200>, 4133 <0 0x01d87c00 0 0x200>, 4134 <0 0x01d87800 0 0x188>, 4135 <0 0x01d87a00 0 0x200>; 4136 #clock-cells = <1>; 4137 #phy-cells = <0>; 4138 }; 4139 }; 4140 4141 sdhc_2: mmc@8804000 { 4142 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4143 reg = <0 0x08804000 0 0x1000>; 4144 4145 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4147 interrupt-names = "hc_irq", "pwr_irq"; 4148 4149 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4150 <&gcc GCC_SDCC2_APPS_CLK>, 4151 <&rpmhcc RPMH_CXO_CLK>; 4152 clock-names = "iface", "core", "xo"; 4153 resets = <&gcc GCC_SDCC2_BCR>; 4154 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4155 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4156 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4157 iommus = <&apps_smmu 0x4a0 0x0>; 4158 power-domains = <&rpmhpd SM8450_CX>; 4159 operating-points-v2 = <&sdhc2_opp_table>; 4160 bus-width = <4>; 4161 dma-coherent; 4162 4163 /* Forbid SDR104/SDR50 - broken hw! */ 4164 sdhci-caps-mask = <0x3 0x0>; 4165 4166 status = "disabled"; 4167 4168 sdhc2_opp_table: opp-table { 4169 compatible = "operating-points-v2"; 4170 4171 opp-100000000 { 4172 opp-hz = /bits/ 64 <100000000>; 4173 required-opps = <&rpmhpd_opp_low_svs>; 4174 }; 4175 4176 opp-202000000 { 4177 opp-hz = /bits/ 64 <202000000>; 4178 required-opps = <&rpmhpd_opp_svs_l1>; 4179 }; 4180 }; 4181 }; 4182 4183 usb_1: usb@a6f8800 { 4184 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4185 reg = <0 0x0a6f8800 0 0x400>; 4186 status = "disabled"; 4187 #address-cells = <2>; 4188 #size-cells = <2>; 4189 ranges; 4190 4191 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4192 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4193 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4194 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4195 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4196 <&gcc GCC_USB3_0_CLKREF_EN>; 4197 clock-names = "cfg_noc", 4198 "core", 4199 "iface", 4200 "sleep", 4201 "mock_utmi", 4202 "xo"; 4203 4204 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4205 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4206 assigned-clock-rates = <19200000>, <200000000>; 4207 4208 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4209 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4210 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4211 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4212 interrupt-names = "hs_phy_irq", 4213 "ss_phy_irq", 4214 "dm_hs_phy_irq", 4215 "dp_hs_phy_irq"; 4216 4217 power-domains = <&gcc USB30_PRIM_GDSC>; 4218 4219 resets = <&gcc GCC_USB30_PRIM_BCR>; 4220 4221 usb_1_dwc3: usb@a600000 { 4222 compatible = "snps,dwc3"; 4223 reg = <0 0x0a600000 0 0xcd00>; 4224 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4225 iommus = <&apps_smmu 0x0 0x0>; 4226 snps,dis_u2_susphy_quirk; 4227 snps,dis_enblslpm_quirk; 4228 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4229 phy-names = "usb2-phy", "usb3-phy"; 4230 4231 ports { 4232 #address-cells = <1>; 4233 #size-cells = <0>; 4234 4235 port@0 { 4236 reg = <0>; 4237 4238 usb_1_dwc3_hs: endpoint { 4239 }; 4240 }; 4241 4242 port@1 { 4243 reg = <1>; 4244 4245 usb_1_dwc3_ss: endpoint { 4246 }; 4247 }; 4248 }; 4249 }; 4250 }; 4251 4252 nsp_noc: interconnect@320c0000 { 4253 compatible = "qcom,sm8450-nsp-noc"; 4254 reg = <0 0x320c0000 0 0x10000>; 4255 #interconnect-cells = <2>; 4256 qcom,bcm-voters = <&apps_bcm_voter>; 4257 }; 4258 4259 lpass_ag_noc: interconnect@3c40000 { 4260 compatible = "qcom,sm8450-lpass-ag-noc"; 4261 reg = <0 0x03c40000 0 0x17200>; 4262 #interconnect-cells = <2>; 4263 qcom,bcm-voters = <&apps_bcm_voter>; 4264 }; 4265 }; 4266 4267 sound: sound { 4268 }; 4269 4270 thermal-zones { 4271 aoss0-thermal { 4272 polling-delay-passive = <0>; 4273 polling-delay = <0>; 4274 thermal-sensors = <&tsens0 0>; 4275 4276 trips { 4277 thermal-engine-config { 4278 temperature = <125000>; 4279 hysteresis = <1000>; 4280 type = "passive"; 4281 }; 4282 4283 reset-mon-cfg { 4284 temperature = <115000>; 4285 hysteresis = <5000>; 4286 type = "passive"; 4287 }; 4288 }; 4289 }; 4290 4291 cpuss0-thermal { 4292 polling-delay-passive = <0>; 4293 polling-delay = <0>; 4294 thermal-sensors = <&tsens0 1>; 4295 4296 trips { 4297 thermal-engine-config { 4298 temperature = <125000>; 4299 hysteresis = <1000>; 4300 type = "passive"; 4301 }; 4302 4303 reset-mon-cfg { 4304 temperature = <115000>; 4305 hysteresis = <5000>; 4306 type = "passive"; 4307 }; 4308 }; 4309 }; 4310 4311 cpuss1-thermal { 4312 polling-delay-passive = <0>; 4313 polling-delay = <0>; 4314 thermal-sensors = <&tsens0 2>; 4315 4316 trips { 4317 thermal-engine-config { 4318 temperature = <125000>; 4319 hysteresis = <1000>; 4320 type = "passive"; 4321 }; 4322 4323 reset-mon-cfg { 4324 temperature = <115000>; 4325 hysteresis = <5000>; 4326 type = "passive"; 4327 }; 4328 }; 4329 }; 4330 4331 cpuss3-thermal { 4332 polling-delay-passive = <0>; 4333 polling-delay = <0>; 4334 thermal-sensors = <&tsens0 3>; 4335 4336 trips { 4337 thermal-engine-config { 4338 temperature = <125000>; 4339 hysteresis = <1000>; 4340 type = "passive"; 4341 }; 4342 4343 reset-mon-cfg { 4344 temperature = <115000>; 4345 hysteresis = <5000>; 4346 type = "passive"; 4347 }; 4348 }; 4349 }; 4350 4351 cpuss4-thermal { 4352 polling-delay-passive = <0>; 4353 polling-delay = <0>; 4354 thermal-sensors = <&tsens0 4>; 4355 4356 trips { 4357 thermal-engine-config { 4358 temperature = <125000>; 4359 hysteresis = <1000>; 4360 type = "passive"; 4361 }; 4362 4363 reset-mon-cfg { 4364 temperature = <115000>; 4365 hysteresis = <5000>; 4366 type = "passive"; 4367 }; 4368 }; 4369 }; 4370 4371 cpu4-top-thermal { 4372 polling-delay-passive = <0>; 4373 polling-delay = <0>; 4374 thermal-sensors = <&tsens0 5>; 4375 4376 trips { 4377 cpu4_top_alert0: trip-point0 { 4378 temperature = <90000>; 4379 hysteresis = <2000>; 4380 type = "passive"; 4381 }; 4382 4383 cpu4_top_alert1: trip-point1 { 4384 temperature = <95000>; 4385 hysteresis = <2000>; 4386 type = "passive"; 4387 }; 4388 4389 cpu4_top_crit: cpu-crit { 4390 temperature = <110000>; 4391 hysteresis = <1000>; 4392 type = "critical"; 4393 }; 4394 }; 4395 }; 4396 4397 cpu4-bottom-thermal { 4398 polling-delay-passive = <0>; 4399 polling-delay = <0>; 4400 thermal-sensors = <&tsens0 6>; 4401 4402 trips { 4403 cpu4_bottom_alert0: trip-point0 { 4404 temperature = <90000>; 4405 hysteresis = <2000>; 4406 type = "passive"; 4407 }; 4408 4409 cpu4_bottom_alert1: trip-point1 { 4410 temperature = <95000>; 4411 hysteresis = <2000>; 4412 type = "passive"; 4413 }; 4414 4415 cpu4_bottom_crit: cpu-crit { 4416 temperature = <110000>; 4417 hysteresis = <1000>; 4418 type = "critical"; 4419 }; 4420 }; 4421 }; 4422 4423 cpu5-top-thermal { 4424 polling-delay-passive = <0>; 4425 polling-delay = <0>; 4426 thermal-sensors = <&tsens0 7>; 4427 4428 trips { 4429 cpu5_top_alert0: trip-point0 { 4430 temperature = <90000>; 4431 hysteresis = <2000>; 4432 type = "passive"; 4433 }; 4434 4435 cpu5_top_alert1: trip-point1 { 4436 temperature = <95000>; 4437 hysteresis = <2000>; 4438 type = "passive"; 4439 }; 4440 4441 cpu5_top_crit: cpu-crit { 4442 temperature = <110000>; 4443 hysteresis = <1000>; 4444 type = "critical"; 4445 }; 4446 }; 4447 }; 4448 4449 cpu5-bottom-thermal { 4450 polling-delay-passive = <0>; 4451 polling-delay = <0>; 4452 thermal-sensors = <&tsens0 8>; 4453 4454 trips { 4455 cpu5_bottom_alert0: trip-point0 { 4456 temperature = <90000>; 4457 hysteresis = <2000>; 4458 type = "passive"; 4459 }; 4460 4461 cpu5_bottom_alert1: trip-point1 { 4462 temperature = <95000>; 4463 hysteresis = <2000>; 4464 type = "passive"; 4465 }; 4466 4467 cpu5_bottom_crit: cpu-crit { 4468 temperature = <110000>; 4469 hysteresis = <1000>; 4470 type = "critical"; 4471 }; 4472 }; 4473 }; 4474 4475 cpu6-top-thermal { 4476 polling-delay-passive = <0>; 4477 polling-delay = <0>; 4478 thermal-sensors = <&tsens0 9>; 4479 4480 trips { 4481 cpu6_top_alert0: trip-point0 { 4482 temperature = <90000>; 4483 hysteresis = <2000>; 4484 type = "passive"; 4485 }; 4486 4487 cpu6_top_alert1: trip-point1 { 4488 temperature = <95000>; 4489 hysteresis = <2000>; 4490 type = "passive"; 4491 }; 4492 4493 cpu6_top_crit: cpu-crit { 4494 temperature = <110000>; 4495 hysteresis = <1000>; 4496 type = "critical"; 4497 }; 4498 }; 4499 }; 4500 4501 cpu6-bottom-thermal { 4502 polling-delay-passive = <0>; 4503 polling-delay = <0>; 4504 thermal-sensors = <&tsens0 10>; 4505 4506 trips { 4507 cpu6_bottom_alert0: trip-point0 { 4508 temperature = <90000>; 4509 hysteresis = <2000>; 4510 type = "passive"; 4511 }; 4512 4513 cpu6_bottom_alert1: trip-point1 { 4514 temperature = <95000>; 4515 hysteresis = <2000>; 4516 type = "passive"; 4517 }; 4518 4519 cpu6_bottom_crit: cpu-crit { 4520 temperature = <110000>; 4521 hysteresis = <1000>; 4522 type = "critical"; 4523 }; 4524 }; 4525 }; 4526 4527 cpu7-top-thermal { 4528 polling-delay-passive = <0>; 4529 polling-delay = <0>; 4530 thermal-sensors = <&tsens0 11>; 4531 4532 trips { 4533 cpu7_top_alert0: trip-point0 { 4534 temperature = <90000>; 4535 hysteresis = <2000>; 4536 type = "passive"; 4537 }; 4538 4539 cpu7_top_alert1: trip-point1 { 4540 temperature = <95000>; 4541 hysteresis = <2000>; 4542 type = "passive"; 4543 }; 4544 4545 cpu7_top_crit: cpu-crit { 4546 temperature = <110000>; 4547 hysteresis = <1000>; 4548 type = "critical"; 4549 }; 4550 }; 4551 }; 4552 4553 cpu7-middle-thermal { 4554 polling-delay-passive = <0>; 4555 polling-delay = <0>; 4556 thermal-sensors = <&tsens0 12>; 4557 4558 trips { 4559 cpu7_middle_alert0: trip-point0 { 4560 temperature = <90000>; 4561 hysteresis = <2000>; 4562 type = "passive"; 4563 }; 4564 4565 cpu7_middle_alert1: trip-point1 { 4566 temperature = <95000>; 4567 hysteresis = <2000>; 4568 type = "passive"; 4569 }; 4570 4571 cpu7_middle_crit: cpu-crit { 4572 temperature = <110000>; 4573 hysteresis = <1000>; 4574 type = "critical"; 4575 }; 4576 }; 4577 }; 4578 4579 cpu7-bottom-thermal { 4580 polling-delay-passive = <0>; 4581 polling-delay = <0>; 4582 thermal-sensors = <&tsens0 13>; 4583 4584 trips { 4585 cpu7_bottom_alert0: trip-point0 { 4586 temperature = <90000>; 4587 hysteresis = <2000>; 4588 type = "passive"; 4589 }; 4590 4591 cpu7_bottom_alert1: trip-point1 { 4592 temperature = <95000>; 4593 hysteresis = <2000>; 4594 type = "passive"; 4595 }; 4596 4597 cpu7_bottom_crit: cpu-crit { 4598 temperature = <110000>; 4599 hysteresis = <1000>; 4600 type = "critical"; 4601 }; 4602 }; 4603 }; 4604 4605 gpu-top-thermal { 4606 polling-delay-passive = <10>; 4607 polling-delay = <0>; 4608 thermal-sensors = <&tsens0 14>; 4609 4610 trips { 4611 thermal-engine-config { 4612 temperature = <125000>; 4613 hysteresis = <1000>; 4614 type = "passive"; 4615 }; 4616 4617 thermal-hal-config { 4618 temperature = <125000>; 4619 hysteresis = <1000>; 4620 type = "passive"; 4621 }; 4622 4623 reset-mon-cfg { 4624 temperature = <115000>; 4625 hysteresis = <5000>; 4626 type = "passive"; 4627 }; 4628 4629 gpu0_tj_cfg: tj-cfg { 4630 temperature = <95000>; 4631 hysteresis = <5000>; 4632 type = "passive"; 4633 }; 4634 }; 4635 }; 4636 4637 gpu-bottom-thermal { 4638 polling-delay-passive = <10>; 4639 polling-delay = <0>; 4640 thermal-sensors = <&tsens0 15>; 4641 4642 trips { 4643 thermal-engine-config { 4644 temperature = <125000>; 4645 hysteresis = <1000>; 4646 type = "passive"; 4647 }; 4648 4649 thermal-hal-config { 4650 temperature = <125000>; 4651 hysteresis = <1000>; 4652 type = "passive"; 4653 }; 4654 4655 reset-mon-cfg { 4656 temperature = <115000>; 4657 hysteresis = <5000>; 4658 type = "passive"; 4659 }; 4660 4661 gpu1_tj_cfg: tj-cfg { 4662 temperature = <95000>; 4663 hysteresis = <5000>; 4664 type = "passive"; 4665 }; 4666 }; 4667 }; 4668 4669 aoss1-thermal { 4670 polling-delay-passive = <0>; 4671 polling-delay = <0>; 4672 thermal-sensors = <&tsens1 0>; 4673 4674 trips { 4675 thermal-engine-config { 4676 temperature = <125000>; 4677 hysteresis = <1000>; 4678 type = "passive"; 4679 }; 4680 4681 reset-mon-cfg { 4682 temperature = <115000>; 4683 hysteresis = <5000>; 4684 type = "passive"; 4685 }; 4686 }; 4687 }; 4688 4689 cpu0-thermal { 4690 polling-delay-passive = <0>; 4691 polling-delay = <0>; 4692 thermal-sensors = <&tsens1 1>; 4693 4694 trips { 4695 cpu0_alert0: trip-point0 { 4696 temperature = <90000>; 4697 hysteresis = <2000>; 4698 type = "passive"; 4699 }; 4700 4701 cpu0_alert1: trip-point1 { 4702 temperature = <95000>; 4703 hysteresis = <2000>; 4704 type = "passive"; 4705 }; 4706 4707 cpu0_crit: cpu-crit { 4708 temperature = <110000>; 4709 hysteresis = <1000>; 4710 type = "critical"; 4711 }; 4712 }; 4713 }; 4714 4715 cpu1-thermal { 4716 polling-delay-passive = <0>; 4717 polling-delay = <0>; 4718 thermal-sensors = <&tsens1 2>; 4719 4720 trips { 4721 cpu1_alert0: trip-point0 { 4722 temperature = <90000>; 4723 hysteresis = <2000>; 4724 type = "passive"; 4725 }; 4726 4727 cpu1_alert1: trip-point1 { 4728 temperature = <95000>; 4729 hysteresis = <2000>; 4730 type = "passive"; 4731 }; 4732 4733 cpu1_crit: cpu-crit { 4734 temperature = <110000>; 4735 hysteresis = <1000>; 4736 type = "critical"; 4737 }; 4738 }; 4739 }; 4740 4741 cpu2-thermal { 4742 polling-delay-passive = <0>; 4743 polling-delay = <0>; 4744 thermal-sensors = <&tsens1 3>; 4745 4746 trips { 4747 cpu2_alert0: trip-point0 { 4748 temperature = <90000>; 4749 hysteresis = <2000>; 4750 type = "passive"; 4751 }; 4752 4753 cpu2_alert1: trip-point1 { 4754 temperature = <95000>; 4755 hysteresis = <2000>; 4756 type = "passive"; 4757 }; 4758 4759 cpu2_crit: cpu-crit { 4760 temperature = <110000>; 4761 hysteresis = <1000>; 4762 type = "critical"; 4763 }; 4764 }; 4765 }; 4766 4767 cpu3-thermal { 4768 polling-delay-passive = <0>; 4769 polling-delay = <0>; 4770 thermal-sensors = <&tsens1 4>; 4771 4772 trips { 4773 cpu3_alert0: trip-point0 { 4774 temperature = <90000>; 4775 hysteresis = <2000>; 4776 type = "passive"; 4777 }; 4778 4779 cpu3_alert1: trip-point1 { 4780 temperature = <95000>; 4781 hysteresis = <2000>; 4782 type = "passive"; 4783 }; 4784 4785 cpu3_crit: cpu-crit { 4786 temperature = <110000>; 4787 hysteresis = <1000>; 4788 type = "critical"; 4789 }; 4790 }; 4791 }; 4792 4793 cdsp0-thermal { 4794 polling-delay-passive = <10>; 4795 polling-delay = <0>; 4796 thermal-sensors = <&tsens1 5>; 4797 4798 trips { 4799 thermal-engine-config { 4800 temperature = <125000>; 4801 hysteresis = <1000>; 4802 type = "passive"; 4803 }; 4804 4805 thermal-hal-config { 4806 temperature = <125000>; 4807 hysteresis = <1000>; 4808 type = "passive"; 4809 }; 4810 4811 reset-mon-cfg { 4812 temperature = <115000>; 4813 hysteresis = <5000>; 4814 type = "passive"; 4815 }; 4816 4817 cdsp_0_config: junction-config { 4818 temperature = <95000>; 4819 hysteresis = <5000>; 4820 type = "passive"; 4821 }; 4822 }; 4823 }; 4824 4825 cdsp1-thermal { 4826 polling-delay-passive = <10>; 4827 polling-delay = <0>; 4828 thermal-sensors = <&tsens1 6>; 4829 4830 trips { 4831 thermal-engine-config { 4832 temperature = <125000>; 4833 hysteresis = <1000>; 4834 type = "passive"; 4835 }; 4836 4837 thermal-hal-config { 4838 temperature = <125000>; 4839 hysteresis = <1000>; 4840 type = "passive"; 4841 }; 4842 4843 reset-mon-cfg { 4844 temperature = <115000>; 4845 hysteresis = <5000>; 4846 type = "passive"; 4847 }; 4848 4849 cdsp_1_config: junction-config { 4850 temperature = <95000>; 4851 hysteresis = <5000>; 4852 type = "passive"; 4853 }; 4854 }; 4855 }; 4856 4857 cdsp2-thermal { 4858 polling-delay-passive = <10>; 4859 polling-delay = <0>; 4860 thermal-sensors = <&tsens1 7>; 4861 4862 trips { 4863 thermal-engine-config { 4864 temperature = <125000>; 4865 hysteresis = <1000>; 4866 type = "passive"; 4867 }; 4868 4869 thermal-hal-config { 4870 temperature = <125000>; 4871 hysteresis = <1000>; 4872 type = "passive"; 4873 }; 4874 4875 reset-mon-cfg { 4876 temperature = <115000>; 4877 hysteresis = <5000>; 4878 type = "passive"; 4879 }; 4880 4881 cdsp_2_config: junction-config { 4882 temperature = <95000>; 4883 hysteresis = <5000>; 4884 type = "passive"; 4885 }; 4886 }; 4887 }; 4888 4889 video-thermal { 4890 polling-delay-passive = <0>; 4891 polling-delay = <0>; 4892 thermal-sensors = <&tsens1 8>; 4893 4894 trips { 4895 thermal-engine-config { 4896 temperature = <125000>; 4897 hysteresis = <1000>; 4898 type = "passive"; 4899 }; 4900 4901 reset-mon-cfg { 4902 temperature = <115000>; 4903 hysteresis = <5000>; 4904 type = "passive"; 4905 }; 4906 }; 4907 }; 4908 4909 mem-thermal { 4910 polling-delay-passive = <10>; 4911 polling-delay = <0>; 4912 thermal-sensors = <&tsens1 9>; 4913 4914 trips { 4915 thermal-engine-config { 4916 temperature = <125000>; 4917 hysteresis = <1000>; 4918 type = "passive"; 4919 }; 4920 4921 ddr_config0: ddr0-config { 4922 temperature = <90000>; 4923 hysteresis = <5000>; 4924 type = "passive"; 4925 }; 4926 4927 reset-mon-cfg { 4928 temperature = <115000>; 4929 hysteresis = <5000>; 4930 type = "passive"; 4931 }; 4932 }; 4933 }; 4934 4935 modem0-thermal { 4936 polling-delay-passive = <0>; 4937 polling-delay = <0>; 4938 thermal-sensors = <&tsens1 10>; 4939 4940 trips { 4941 thermal-engine-config { 4942 temperature = <125000>; 4943 hysteresis = <1000>; 4944 type = "passive"; 4945 }; 4946 4947 mdmss0_config0: mdmss0-config0 { 4948 temperature = <102000>; 4949 hysteresis = <3000>; 4950 type = "passive"; 4951 }; 4952 4953 mdmss0_config1: mdmss0-config1 { 4954 temperature = <105000>; 4955 hysteresis = <3000>; 4956 type = "passive"; 4957 }; 4958 4959 reset-mon-cfg { 4960 temperature = <115000>; 4961 hysteresis = <5000>; 4962 type = "passive"; 4963 }; 4964 }; 4965 }; 4966 4967 modem1-thermal { 4968 polling-delay-passive = <0>; 4969 polling-delay = <0>; 4970 thermal-sensors = <&tsens1 11>; 4971 4972 trips { 4973 thermal-engine-config { 4974 temperature = <125000>; 4975 hysteresis = <1000>; 4976 type = "passive"; 4977 }; 4978 4979 mdmss1_config0: mdmss1-config0 { 4980 temperature = <102000>; 4981 hysteresis = <3000>; 4982 type = "passive"; 4983 }; 4984 4985 mdmss1_config1: mdmss1-config1 { 4986 temperature = <105000>; 4987 hysteresis = <3000>; 4988 type = "passive"; 4989 }; 4990 4991 reset-mon-cfg { 4992 temperature = <115000>; 4993 hysteresis = <5000>; 4994 type = "passive"; 4995 }; 4996 }; 4997 }; 4998 4999 modem2-thermal { 5000 polling-delay-passive = <0>; 5001 polling-delay = <0>; 5002 thermal-sensors = <&tsens1 12>; 5003 5004 trips { 5005 thermal-engine-config { 5006 temperature = <125000>; 5007 hysteresis = <1000>; 5008 type = "passive"; 5009 }; 5010 5011 mdmss2_config0: mdmss2-config0 { 5012 temperature = <102000>; 5013 hysteresis = <3000>; 5014 type = "passive"; 5015 }; 5016 5017 mdmss2_config1: mdmss2-config1 { 5018 temperature = <105000>; 5019 hysteresis = <3000>; 5020 type = "passive"; 5021 }; 5022 5023 reset-mon-cfg { 5024 temperature = <115000>; 5025 hysteresis = <5000>; 5026 type = "passive"; 5027 }; 5028 }; 5029 }; 5030 5031 modem3-thermal { 5032 polling-delay-passive = <0>; 5033 polling-delay = <0>; 5034 thermal-sensors = <&tsens1 13>; 5035 5036 trips { 5037 thermal-engine-config { 5038 temperature = <125000>; 5039 hysteresis = <1000>; 5040 type = "passive"; 5041 }; 5042 5043 mdmss3_config0: mdmss3-config0 { 5044 temperature = <102000>; 5045 hysteresis = <3000>; 5046 type = "passive"; 5047 }; 5048 5049 mdmss3_config1: mdmss3-config1 { 5050 temperature = <105000>; 5051 hysteresis = <3000>; 5052 type = "passive"; 5053 }; 5054 5055 reset-mon-cfg { 5056 temperature = <115000>; 5057 hysteresis = <5000>; 5058 type = "passive"; 5059 }; 5060 }; 5061 }; 5062 5063 camera0-thermal { 5064 polling-delay-passive = <0>; 5065 polling-delay = <0>; 5066 thermal-sensors = <&tsens1 14>; 5067 5068 trips { 5069 thermal-engine-config { 5070 temperature = <125000>; 5071 hysteresis = <1000>; 5072 type = "passive"; 5073 }; 5074 5075 reset-mon-cfg { 5076 temperature = <115000>; 5077 hysteresis = <5000>; 5078 type = "passive"; 5079 }; 5080 }; 5081 }; 5082 5083 camera1-thermal { 5084 polling-delay-passive = <0>; 5085 polling-delay = <0>; 5086 thermal-sensors = <&tsens1 15>; 5087 5088 trips { 5089 thermal-engine-config { 5090 temperature = <125000>; 5091 hysteresis = <1000>; 5092 type = "passive"; 5093 }; 5094 5095 reset-mon-cfg { 5096 temperature = <115000>; 5097 hysteresis = <5000>; 5098 type = "passive"; 5099 }; 5100 }; 5101 }; 5102 }; 5103 5104 timer { 5105 compatible = "arm,armv8-timer"; 5106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5110 clock-frequency = <19200000>; 5111 }; 5112}; 5113