1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8450.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <76800000>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32000>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 CPU0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo780"; 54 reg = <0x0 0x0>; 55 enable-method = "psci"; 56 next-level-cache = <&L2_0>; 57 power-domains = <&CPU_PD0>; 58 power-domain-names = "psci"; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 #cooling-cells = <2>; 61 clocks = <&cpufreq_hw 0>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 CPU1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo780"; 78 reg = <0x0 0x100>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 #cooling-cells = <2>; 85 clocks = <&cpufreq_hw 0>; 86 L2_100: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-unified; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo780"; 97 reg = <0x0 0x200>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_200>; 100 power-domains = <&CPU_PD2>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 #cooling-cells = <2>; 104 clocks = <&cpufreq_hw 0>; 105 L2_200: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo780"; 116 reg = <0x0 0x300>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_300>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 #cooling-cells = <2>; 123 clocks = <&cpufreq_hw 0>; 124 L2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo780"; 135 reg = <0x0 0x400>; 136 enable-method = "psci"; 137 next-level-cache = <&L2_400>; 138 power-domains = <&CPU_PD4>; 139 power-domain-names = "psci"; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 #cooling-cells = <2>; 142 clocks = <&cpufreq_hw 1>; 143 L2_400: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU5: cpu@500 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo780"; 154 reg = <0x0 0x500>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_500>; 157 power-domains = <&CPU_PD5>; 158 power-domain-names = "psci"; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 #cooling-cells = <2>; 161 clocks = <&cpufreq_hw 1>; 162 L2_500: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU6: cpu@600 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo780"; 173 reg = <0x0 0x600>; 174 enable-method = "psci"; 175 next-level-cache = <&L2_600>; 176 power-domains = <&CPU_PD6>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 #cooling-cells = <2>; 180 clocks = <&cpufreq_hw 1>; 181 L2_600: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 CPU7: cpu@700 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo780"; 192 reg = <0x0 0x700>; 193 enable-method = "psci"; 194 next-level-cache = <&L2_700>; 195 power-domains = <&CPU_PD7>; 196 power-domain-names = "psci"; 197 qcom,freq-domain = <&cpufreq_hw 2>; 198 #cooling-cells = <2>; 199 clocks = <&cpufreq_hw 2>; 200 L2_700: l2-cache { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 cpu-map { 209 cluster0 { 210 core0 { 211 cpu = <&CPU0>; 212 }; 213 214 core1 { 215 cpu = <&CPU1>; 216 }; 217 218 core2 { 219 cpu = <&CPU2>; 220 }; 221 222 core3 { 223 cpu = <&CPU3>; 224 }; 225 226 core4 { 227 cpu = <&CPU4>; 228 }; 229 230 core5 { 231 cpu = <&CPU5>; 232 }; 233 234 core6 { 235 cpu = <&CPU6>; 236 }; 237 238 core7 { 239 cpu = <&CPU7>; 240 }; 241 }; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "silver-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <800>; 252 exit-latency-us = <750>; 253 min-residency-us = <4090>; 254 local-timer-stop; 255 }; 256 257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "gold-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <600>; 262 exit-latency-us = <1550>; 263 min-residency-us = <4791>; 264 local-timer-stop; 265 }; 266 }; 267 268 domain-idle-states { 269 CLUSTER_SLEEP_0: cluster-sleep-0 { 270 compatible = "domain-idle-state"; 271 arm,psci-suspend-param = <0x41000044>; 272 entry-latency-us = <1050>; 273 exit-latency-us = <2500>; 274 min-residency-us = <5309>; 275 }; 276 277 CLUSTER_SLEEP_1: cluster-sleep-1 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x4100c344>; 280 entry-latency-us = <2700>; 281 exit-latency-us = <3500>; 282 min-residency-us = <13959>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm: scm { 289 compatible = "qcom,scm-sm8450", "qcom,scm"; 290 qcom,dload-mode = <&tcsr 0x13000>; 291 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 292 #reset-cells = <1>; 293 }; 294 }; 295 296 clk_virt: interconnect-0 { 297 compatible = "qcom,sm8450-clk-virt"; 298 #interconnect-cells = <2>; 299 qcom,bcm-voters = <&apps_bcm_voter>; 300 }; 301 302 mc_virt: interconnect-1 { 303 compatible = "qcom,sm8450-mc-virt"; 304 #interconnect-cells = <2>; 305 qcom,bcm-voters = <&apps_bcm_voter>; 306 }; 307 308 memory@a0000000 { 309 device_type = "memory"; 310 /* We expect the bootloader to fill in the size */ 311 reg = <0x0 0xa0000000 0x0 0x0>; 312 }; 313 314 pmu { 315 compatible = "arm,armv8-pmuv3"; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 323 CPU_PD0: power-domain-cpu0 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD1: power-domain-cpu1 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD2: power-domain-cpu2 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD3: power-domain-cpu3 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD4: power-domain-cpu4 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD5: power-domain-cpu5 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CPU_PD6: power-domain-cpu6 { 360 #power-domain-cells = <0>; 361 power-domains = <&CLUSTER_PD>; 362 domain-idle-states = <&BIG_CPU_SLEEP_0>; 363 }; 364 365 CPU_PD7: power-domain-cpu7 { 366 #power-domain-cells = <0>; 367 power-domains = <&CLUSTER_PD>; 368 domain-idle-states = <&BIG_CPU_SLEEP_0>; 369 }; 370 371 CLUSTER_PD: power-domain-cpu-cluster0 { 372 #power-domain-cells = <0>; 373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 374 }; 375 }; 376 377 qup_opp_table_100mhz: opp-table-qup { 378 compatible = "operating-points-v2"; 379 380 opp-50000000 { 381 opp-hz = /bits/ 64 <50000000>; 382 required-opps = <&rpmhpd_opp_min_svs>; 383 }; 384 385 opp-75000000 { 386 opp-hz = /bits/ 64 <75000000>; 387 required-opps = <&rpmhpd_opp_low_svs>; 388 }; 389 390 opp-100000000 { 391 opp-hz = /bits/ 64 <100000000>; 392 required-opps = <&rpmhpd_opp_svs>; 393 }; 394 }; 395 396 reserved_memory: reserved-memory { 397 #address-cells = <2>; 398 #size-cells = <2>; 399 ranges; 400 401 hyp_mem: memory@80000000 { 402 reg = <0x0 0x80000000 0x0 0x600000>; 403 no-map; 404 }; 405 406 xbl_dt_log_mem: memory@80600000 { 407 reg = <0x0 0x80600000 0x0 0x40000>; 408 no-map; 409 }; 410 411 xbl_ramdump_mem: memory@80640000 { 412 reg = <0x0 0x80640000 0x0 0x180000>; 413 no-map; 414 }; 415 416 xbl_sc_mem: memory@807c0000 { 417 reg = <0x0 0x807c0000 0x0 0x40000>; 418 no-map; 419 }; 420 421 aop_image_mem: memory@80800000 { 422 reg = <0x0 0x80800000 0x0 0x60000>; 423 no-map; 424 }; 425 426 aop_cmd_db_mem: memory@80860000 { 427 compatible = "qcom,cmd-db"; 428 reg = <0x0 0x80860000 0x0 0x20000>; 429 no-map; 430 }; 431 432 aop_config_mem: memory@80880000 { 433 reg = <0x0 0x80880000 0x0 0x20000>; 434 no-map; 435 }; 436 437 tme_crash_dump_mem: memory@808a0000 { 438 reg = <0x0 0x808a0000 0x0 0x40000>; 439 no-map; 440 }; 441 442 tme_log_mem: memory@808e0000 { 443 reg = <0x0 0x808e0000 0x0 0x4000>; 444 no-map; 445 }; 446 447 uefi_log_mem: memory@808e4000 { 448 reg = <0x0 0x808e4000 0x0 0x10000>; 449 no-map; 450 }; 451 452 /* secdata region can be reused by apps */ 453 smem: memory@80900000 { 454 compatible = "qcom,smem"; 455 reg = <0x0 0x80900000 0x0 0x200000>; 456 hwlocks = <&tcsr_mutex 3>; 457 no-map; 458 }; 459 460 cpucp_fw_mem: memory@80b00000 { 461 reg = <0x0 0x80b00000 0x0 0x100000>; 462 no-map; 463 }; 464 465 cdsp_secure_heap: memory@80c00000 { 466 reg = <0x0 0x80c00000 0x0 0x4600000>; 467 no-map; 468 }; 469 470 video_mem: memory@85700000 { 471 reg = <0x0 0x85700000 0x0 0x700000>; 472 no-map; 473 }; 474 475 adsp_mem: memory@85e00000 { 476 reg = <0x0 0x85e00000 0x0 0x2100000>; 477 no-map; 478 }; 479 480 slpi_mem: memory@88000000 { 481 reg = <0x0 0x88000000 0x0 0x1900000>; 482 no-map; 483 }; 484 485 cdsp_mem: memory@89900000 { 486 reg = <0x0 0x89900000 0x0 0x2000000>; 487 no-map; 488 }; 489 490 ipa_fw_mem: memory@8b900000 { 491 reg = <0x0 0x8b900000 0x0 0x10000>; 492 no-map; 493 }; 494 495 ipa_gsi_mem: memory@8b910000 { 496 reg = <0x0 0x8b910000 0x0 0xa000>; 497 no-map; 498 }; 499 500 gpu_micro_code_mem: memory@8b91a000 { 501 reg = <0x0 0x8b91a000 0x0 0x2000>; 502 no-map; 503 }; 504 505 spss_region_mem: memory@8ba00000 { 506 reg = <0x0 0x8ba00000 0x0 0x180000>; 507 no-map; 508 }; 509 510 /* First part of the "SPU secure shared memory" region */ 511 spu_tz_shared_mem: memory@8bb80000 { 512 reg = <0x0 0x8bb80000 0x0 0x60000>; 513 no-map; 514 }; 515 516 /* Second part of the "SPU secure shared memory" region */ 517 spu_modem_shared_mem: memory@8bbe0000 { 518 reg = <0x0 0x8bbe0000 0x0 0x20000>; 519 no-map; 520 }; 521 522 mpss_mem: memory@8bc00000 { 523 reg = <0x0 0x8bc00000 0x0 0x13200000>; 524 no-map; 525 }; 526 527 cvp_mem: memory@9ee00000 { 528 reg = <0x0 0x9ee00000 0x0 0x700000>; 529 no-map; 530 }; 531 532 camera_mem: memory@9f500000 { 533 reg = <0x0 0x9f500000 0x0 0x800000>; 534 no-map; 535 }; 536 537 rmtfs_mem: memory@9fd00000 { 538 compatible = "qcom,rmtfs-mem"; 539 reg = <0x0 0x9fd00000 0x0 0x280000>; 540 no-map; 541 542 qcom,client-id = <1>; 543 qcom,vmid = <15>; 544 }; 545 546 xbl_sc_mem2: memory@a6e00000 { 547 reg = <0x0 0xa6e00000 0x0 0x40000>; 548 no-map; 549 }; 550 551 global_sync_mem: memory@a6f00000 { 552 reg = <0x0 0xa6f00000 0x0 0x100000>; 553 no-map; 554 }; 555 556 /* uefi region can be reused by APPS */ 557 558 /* Linux kernel image is loaded at 0xa0000000 */ 559 560 oem_vm_mem: memory@bb000000 { 561 reg = <0x0 0xbb000000 0x0 0x5000000>; 562 no-map; 563 }; 564 565 mte_mem: memory@c0000000 { 566 reg = <0x0 0xc0000000 0x0 0x20000000>; 567 no-map; 568 }; 569 570 qheebsp_reserved_mem: memory@e0000000 { 571 reg = <0x0 0xe0000000 0x0 0x600000>; 572 no-map; 573 }; 574 575 cpusys_vm_mem: memory@e0600000 { 576 reg = <0x0 0xe0600000 0x0 0x400000>; 577 no-map; 578 }; 579 580 hyp_reserved_mem: memory@e0a00000 { 581 reg = <0x0 0xe0a00000 0x0 0x100000>; 582 no-map; 583 }; 584 585 trust_ui_vm_mem: memory@e0b00000 { 586 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 587 no-map; 588 }; 589 590 trust_ui_vm_qrtr: memory@e55f3000 { 591 reg = <0x0 0xe55f3000 0x0 0x9000>; 592 no-map; 593 }; 594 595 trust_ui_vm_vblk0_ring: memory@e55fc000 { 596 reg = <0x0 0xe55fc000 0x0 0x4000>; 597 no-map; 598 }; 599 600 trust_ui_vm_swiotlb: memory@e5600000 { 601 reg = <0x0 0xe5600000 0x0 0x100000>; 602 no-map; 603 }; 604 605 tz_stat_mem: memory@e8800000 { 606 reg = <0x0 0xe8800000 0x0 0x100000>; 607 no-map; 608 }; 609 610 tags_mem: memory@e8900000 { 611 reg = <0x0 0xe8900000 0x0 0x1200000>; 612 no-map; 613 }; 614 615 qtee_mem: memory@e9b00000 { 616 reg = <0x0 0xe9b00000 0x0 0x500000>; 617 no-map; 618 }; 619 620 trusted_apps_mem: memory@ea000000 { 621 reg = <0x0 0xea000000 0x0 0x3900000>; 622 no-map; 623 }; 624 625 trusted_apps_ext_mem: memory@ed900000 { 626 reg = <0x0 0xed900000 0x0 0x3b00000>; 627 no-map; 628 }; 629 }; 630 631 smp2p-adsp { 632 compatible = "qcom,smp2p"; 633 qcom,smem = <443>, <429>; 634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 635 IPCC_MPROC_SIGNAL_SMP2P 636 IRQ_TYPE_EDGE_RISING>; 637 mboxes = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P>; 639 640 qcom,local-pid = <0>; 641 qcom,remote-pid = <2>; 642 643 smp2p_adsp_out: master-kernel { 644 qcom,entry-name = "master-kernel"; 645 #qcom,smem-state-cells = <1>; 646 }; 647 648 smp2p_adsp_in: slave-kernel { 649 qcom,entry-name = "slave-kernel"; 650 interrupt-controller; 651 #interrupt-cells = <2>; 652 }; 653 }; 654 655 smp2p-cdsp { 656 compatible = "qcom,smp2p"; 657 qcom,smem = <94>, <432>; 658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 659 IPCC_MPROC_SIGNAL_SMP2P 660 IRQ_TYPE_EDGE_RISING>; 661 mboxes = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P>; 663 664 qcom,local-pid = <0>; 665 qcom,remote-pid = <5>; 666 667 smp2p_cdsp_out: master-kernel { 668 qcom,entry-name = "master-kernel"; 669 #qcom,smem-state-cells = <1>; 670 }; 671 672 smp2p_cdsp_in: slave-kernel { 673 qcom,entry-name = "slave-kernel"; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 }; 677 }; 678 679 smp2p-modem { 680 compatible = "qcom,smp2p"; 681 qcom,smem = <435>, <428>; 682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P>; 687 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <1>; 690 691 smp2p_modem_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 smp2p_modem_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 702 ipa_smp2p_out: ipa-ap-to-modem { 703 qcom,entry-name = "ipa"; 704 #qcom,smem-state-cells = <1>; 705 }; 706 707 ipa_smp2p_in: ipa-modem-to-ap { 708 qcom,entry-name = "ipa"; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 }; 713 714 smp2p-slpi { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <481>, <430>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <3>; 725 726 smp2p_slpi_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_slpi_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 soc: soc@0 { 739 #address-cells = <2>; 740 #size-cells = <2>; 741 ranges = <0 0 0 0 0x10 0>; 742 dma-ranges = <0 0 0 0 0x10 0>; 743 compatible = "simple-bus"; 744 745 gcc: clock-controller@100000 { 746 compatible = "qcom,gcc-sm8450"; 747 reg = <0x0 0x00100000 0x0 0x1f4200>; 748 #clock-cells = <1>; 749 #reset-cells = <1>; 750 #power-domain-cells = <1>; 751 clocks = <&rpmhcc RPMH_CXO_CLK>, 752 <&sleep_clk>, 753 <&pcie0_lane>, 754 <&pcie1_lane>, 755 <0>, 756 <&ufs_mem_phy_lanes 0>, 757 <&ufs_mem_phy_lanes 1>, 758 <&ufs_mem_phy_lanes 2>, 759 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 760 clock-names = "bi_tcxo", 761 "sleep_clk", 762 "pcie_0_pipe_clk", 763 "pcie_1_pipe_clk", 764 "pcie_1_phy_aux_clk", 765 "ufs_phy_rx_symbol_0_clk", 766 "ufs_phy_rx_symbol_1_clk", 767 "ufs_phy_tx_symbol_0_clk", 768 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 769 }; 770 771 gpi_dma2: dma-controller@800000 { 772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 773 #dma-cells = <3>; 774 reg = <0 0x00800000 0 0x60000>; 775 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 787 dma-channels = <12>; 788 dma-channel-mask = <0x7e>; 789 iommus = <&apps_smmu 0x496 0x0>; 790 status = "disabled"; 791 }; 792 793 qupv3_id_2: geniqup@8c0000 { 794 compatible = "qcom,geni-se-qup"; 795 reg = <0x0 0x008c0000 0x0 0x2000>; 796 clock-names = "m-ahb", "s-ahb"; 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 799 iommus = <&apps_smmu 0x483 0x0>; 800 #address-cells = <2>; 801 #size-cells = <2>; 802 ranges; 803 status = "disabled"; 804 805 i2c15: i2c@880000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0x0 0x00880000 0x0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_i2c15_data_clk>; 812 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 816 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 818 interconnect-names = "qup-core", "qup-config", "qup-memory"; 819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 820 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 821 dma-names = "tx", "rx"; 822 status = "disabled"; 823 }; 824 825 spi15: spi@880000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0x0 0x00880000 0x0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 834 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 837 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 838 dma-names = "tx", "rx"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 844 i2c16: i2c@884000 { 845 compatible = "qcom,geni-i2c"; 846 reg = <0x0 0x00884000 0x0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&qup_i2c16_data_clk>; 851 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 855 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 856 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 857 interconnect-names = "qup-core", "qup-config", "qup-memory"; 858 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 859 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 860 dma-names = "tx", "rx"; 861 status = "disabled"; 862 }; 863 864 spi16: spi@884000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0x0 0x00884000 0x0 0x4000>; 867 clock-names = "se"; 868 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 869 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 870 pinctrl-names = "default"; 871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 873 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 874 interconnect-names = "qup-core", "qup-config"; 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 876 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 877 dma-names = "tx", "rx"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 status = "disabled"; 881 }; 882 883 i2c17: i2c@888000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0x0 0x00888000 0x0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_i2c17_data_clk>; 890 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 894 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 898 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 899 dma-names = "tx", "rx"; 900 status = "disabled"; 901 }; 902 903 spi17: spi@888000 { 904 compatible = "qcom,geni-spi"; 905 reg = <0x0 0x00888000 0x0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 908 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 912 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 i2c18: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0x0 0x0088c000 0x0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c18_data_clk>; 929 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 933 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", "qup-memory"; 936 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 937 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 938 dma-names = "tx", "rx"; 939 status = "disabled"; 940 }; 941 942 spi18: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 947 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 952 interconnect-names = "qup-core", "qup-config"; 953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 954 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 955 dma-names = "tx", "rx"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c19: i2c@890000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0x0 0x00890000 0x0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_i2c19_data_clk>; 968 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 976 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 status = "disabled"; 979 }; 980 981 spi19: spi@890000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0 0x00890000 0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 986 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 990 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 993 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 994 dma-names = "tx", "rx"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c20: i2c@894000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00894000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c20_data_clk>; 1007 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1011 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1012 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1014 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1015 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1016 dma-names = "tx", "rx"; 1017 status = "disabled"; 1018 }; 1019 1020 uart20: serial@894000 { 1021 compatible = "qcom,geni-uart"; 1022 reg = <0 0x00894000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_uart20_default>; 1027 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 status = "disabled"; 1035 }; 1036 1037 spi20: spi@894000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00894000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1042 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1049 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c21: i2c@898000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0x0 0x00898000 0x0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c21_data_clk>; 1063 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1071 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi21: spi@898000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00898000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1081 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1084 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1085 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1088 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 }; 1095 1096 gpi_dma0: dma-controller@900000 { 1097 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1098 #dma-cells = <3>; 1099 reg = <0 0x00900000 0 0x60000>; 1100 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1112 dma-channels = <12>; 1113 dma-channel-mask = <0x7e>; 1114 iommus = <&apps_smmu 0x5b6 0x0>; 1115 status = "disabled"; 1116 }; 1117 1118 qupv3_id_0: geniqup@9c0000 { 1119 compatible = "qcom,geni-se-qup"; 1120 reg = <0x0 0x009c0000 0x0 0x2000>; 1121 clock-names = "m-ahb", "s-ahb"; 1122 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1123 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1124 iommus = <&apps_smmu 0x5a3 0x0>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1126 interconnect-names = "qup-core"; 1127 #address-cells = <2>; 1128 #size-cells = <2>; 1129 ranges; 1130 status = "disabled"; 1131 1132 i2c0: i2c@980000 { 1133 compatible = "qcom,geni-i2c"; 1134 reg = <0x0 0x00980000 0x0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_i2c0_data_clk>; 1139 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1143 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1144 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1145 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1147 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 status = "disabled"; 1150 }; 1151 1152 spi0: spi@980000 { 1153 compatible = "qcom,geni-spi"; 1154 reg = <0x0 0x00980000 0x0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1157 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1160 power-domains = <&rpmhpd RPMHPD_CX>; 1161 operating-points-v2 = <&qup_opp_table_100mhz>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1164 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1166 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1167 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1168 dma-names = "tx", "rx"; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c1: i2c@984000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0x0 0x00984000 0x0 0x4000>; 1177 clock-names = "se"; 1178 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c1_data_clk>; 1181 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1185 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1186 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1187 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1188 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 status = "disabled"; 1192 }; 1193 1194 spi1: spi@984000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0x0 0x00984000 0x0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1204 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1205 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1207 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1208 dma-names = "tx", "rx"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 i2c2: i2c@988000 { 1215 compatible = "qcom,geni-i2c"; 1216 reg = <0x0 0x00988000 0x0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1219 pinctrl-names = "default"; 1220 pinctrl-0 = <&qup_i2c2_data_clk>; 1221 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1227 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1228 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1229 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1230 dma-names = "tx", "rx"; 1231 status = "disabled"; 1232 }; 1233 1234 spi2: spi@988000 { 1235 compatible = "qcom,geni-spi"; 1236 reg = <0x0 0x00988000 0x0 0x4000>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1239 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1246 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1247 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1248 dma-names = "tx", "rx"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 1255 i2c3: i2c@98c000 { 1256 compatible = "qcom,geni-i2c"; 1257 reg = <0x0 0x0098c000 0x0 0x4000>; 1258 clock-names = "se"; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_i2c3_data_clk>; 1262 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1267 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1268 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1269 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1270 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1271 dma-names = "tx", "rx"; 1272 status = "disabled"; 1273 }; 1274 1275 spi3: spi@98c000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0x0 0x0098c000 0x0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1285 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1288 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1289 dma-names = "tx", "rx"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 i2c4: i2c@990000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0x0 0x00990000 0x0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&qup_i2c4_data_clk>; 1302 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1306 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1307 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi4: spi@990000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0x0 0x00990000 0x0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1320 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1323 power-domains = <&rpmhpd RPMHPD_CX>; 1324 operating-points-v2 = <&qup_opp_table_100mhz>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1326 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1327 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1328 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1329 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1330 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c5: i2c@994000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0x0 0x00994000 0x0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c5_data_clk>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1350 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1352 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1353 dma-names = "tx", "rx"; 1354 status = "disabled"; 1355 }; 1356 1357 spi5: spi@994000 { 1358 compatible = "qcom,geni-spi"; 1359 reg = <0x0 0x00994000 0x0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1362 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1363 pinctrl-names = "default"; 1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1368 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1369 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1370 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1371 dma-names = "tx", "rx"; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 1378 i2c6: i2c@998000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0x0 0x00998000 0x0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c6_data_clk>; 1385 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1390 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1391 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1393 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1394 dma-names = "tx", "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 spi6: spi@998000 { 1399 compatible = "qcom,geni-spi"; 1400 reg = <0x0 0x00998000 0x0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1407 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1408 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1409 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1410 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1411 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1412 dma-names = "tx", "rx"; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 uart7: serial@99c000 { 1419 compatible = "qcom,geni-debug-uart"; 1420 reg = <0 0x0099c000 0 0x4000>; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1427 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1429 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1430 interconnect-names = "qup-core", 1431 "qup-config"; 1432 status = "disabled"; 1433 }; 1434 }; 1435 1436 gpi_dma1: dma-controller@a00000 { 1437 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1438 #dma-cells = <3>; 1439 reg = <0 0x00a00000 0 0x60000>; 1440 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1452 dma-channels = <12>; 1453 dma-channel-mask = <0x7e>; 1454 iommus = <&apps_smmu 0x56 0x0>; 1455 status = "disabled"; 1456 }; 1457 1458 qupv3_id_1: geniqup@ac0000 { 1459 compatible = "qcom,geni-se-qup"; 1460 reg = <0x0 0x00ac0000 0x0 0x6000>; 1461 clock-names = "m-ahb", "s-ahb"; 1462 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1463 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1464 iommus = <&apps_smmu 0x43 0x0>; 1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1466 interconnect-names = "qup-core"; 1467 #address-cells = <2>; 1468 #size-cells = <2>; 1469 ranges; 1470 status = "disabled"; 1471 1472 i2c8: i2c@a80000 { 1473 compatible = "qcom,geni-i2c"; 1474 reg = <0x0 0x00a80000 0x0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_i2c8_data_clk>; 1479 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1485 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1486 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1487 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1488 dma-names = "tx", "rx"; 1489 status = "disabled"; 1490 }; 1491 1492 spi8: spi@a80000 { 1493 compatible = "qcom,geni-spi"; 1494 reg = <0x0 0x00a80000 0x0 0x4000>; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1497 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1503 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1504 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1505 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1506 dma-names = "tx", "rx"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c9: i2c@a84000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x00a84000 0x0 0x4000>; 1515 clock-names = "se"; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c9_data_clk>; 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi9: spi@a84000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0x0 0x00a84000 0x0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1537 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1543 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1544 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1545 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1546 dma-names = "tx", "rx"; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 i2c10: i2c@a88000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0x0 0x00a88000 0x0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_i2c10_data_clk>; 1559 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1565 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1566 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1567 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 spi10: spi@a88000 { 1573 compatible = "qcom,geni-spi"; 1574 reg = <0x0 0x00a88000 0x0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1577 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1583 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1585 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1586 dma-names = "tx", "rx"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c11: i2c@a8c000 { 1593 compatible = "qcom,geni-i2c"; 1594 reg = <0x0 0x00a8c000 0x0 0x4000>; 1595 clock-names = "se"; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_i2c11_data_clk>; 1599 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1607 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 spi11: spi@a8c000 { 1613 compatible = "qcom,geni-spi"; 1614 reg = <0x0 0x00a8c000 0x0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1623 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1624 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1625 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1626 dma-names = "tx", "rx"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c12: i2c@a90000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0x0 0x00a90000 0x0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c12_data_clk>; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1643 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1644 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1645 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1646 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1648 dma-names = "tx", "rx"; 1649 status = "disabled"; 1650 }; 1651 1652 spi12: spi@a90000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0x0 0x00a90000 0x0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1657 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1658 pinctrl-names = "default"; 1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1663 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1664 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 i2c13: i2c@a94000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a94000 0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_i2c13_data_clk>; 1679 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1685 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1686 dma-names = "tx", "rx"; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 spi13: spi@a94000 { 1693 compatible = "qcom,geni-spi"; 1694 reg = <0x0 0x00a94000 0x0 0x4000>; 1695 clock-names = "se"; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1697 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1703 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1704 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1705 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 i2c14: i2c@a98000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a98000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c14_data_clk>; 1719 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1723 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1725 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1726 dma-names = "tx", "rx"; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 spi14: spi@a98000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0x00a98000 0x0 0x4000>; 1735 clock-names = "se"; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1737 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1741 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1742 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1743 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1744 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1745 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1746 dma-names = "tx", "rx"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 }; 1752 1753 rng: rng@10c3000 { 1754 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee"; 1755 reg = <0 0x010c3000 0 0x1000>; 1756 }; 1757 1758 pcie0: pci@1c00000 { 1759 compatible = "qcom,pcie-sm8450-pcie0"; 1760 reg = <0 0x01c00000 0 0x3000>, 1761 <0 0x60000000 0 0xf1d>, 1762 <0 0x60000f20 0 0xa8>, 1763 <0 0x60001000 0 0x1000>, 1764 <0 0x60100000 0 0x100000>; 1765 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1766 device_type = "pci"; 1767 linux,pci-domain = <0>; 1768 bus-range = <0x00 0xff>; 1769 num-lanes = <1>; 1770 1771 #address-cells = <3>; 1772 #size-cells = <2>; 1773 1774 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1775 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1776 1777 /* 1778 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1779 * Hence, the IDs are swapped. 1780 */ 1781 msi-map = <0x0 &gic_its 0x5981 0x1>, 1782 <0x100 &gic_its 0x5980 0x1>; 1783 msi-map-mask = <0xff00>; 1784 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1785 interrupt-names = "msi"; 1786 #interrupt-cells = <1>; 1787 interrupt-map-mask = <0 0 0 0x7>; 1788 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1789 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1790 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1791 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1792 1793 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1794 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1795 <&pcie0_lane>, 1796 <&rpmhcc RPMH_CXO_CLK>, 1797 <&gcc GCC_PCIE_0_AUX_CLK>, 1798 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1799 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1800 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1801 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1802 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1803 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1804 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1805 clock-names = "pipe", 1806 "pipe_mux", 1807 "phy_pipe", 1808 "ref", 1809 "aux", 1810 "cfg", 1811 "bus_master", 1812 "bus_slave", 1813 "slave_q2a", 1814 "ddrss_sf_tbu", 1815 "aggre0", 1816 "aggre1"; 1817 1818 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1819 <0x100 &apps_smmu 0x1c01 0x1>; 1820 1821 resets = <&gcc GCC_PCIE_0_BCR>; 1822 reset-names = "pci"; 1823 1824 power-domains = <&gcc PCIE_0_GDSC>; 1825 1826 phys = <&pcie0_lane>; 1827 phy-names = "pciephy"; 1828 1829 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1830 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1831 1832 pinctrl-names = "default"; 1833 pinctrl-0 = <&pcie0_default_state>; 1834 1835 status = "disabled"; 1836 }; 1837 1838 pcie0_phy: phy@1c06000 { 1839 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1840 reg = <0 0x01c06000 0 0x200>; 1841 #address-cells = <2>; 1842 #size-cells = <2>; 1843 ranges; 1844 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1845 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1846 <&gcc GCC_PCIE_0_CLKREF_EN>, 1847 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1848 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1849 1850 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1851 reset-names = "phy"; 1852 1853 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1854 assigned-clock-rates = <100000000>; 1855 1856 status = "disabled"; 1857 1858 pcie0_lane: phy@1c06200 { 1859 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1860 <0 0x01c07000 0 0x200>, /* rx */ 1861 <0 0x01c06200 0 0x200>, /* pcs */ 1862 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1863 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1864 clock-names = "pipe0"; 1865 1866 #clock-cells = <0>; 1867 #phy-cells = <0>; 1868 clock-output-names = "pcie_0_pipe_clk"; 1869 }; 1870 }; 1871 1872 pcie1: pci@1c08000 { 1873 compatible = "qcom,pcie-sm8450-pcie1"; 1874 reg = <0 0x01c08000 0 0x3000>, 1875 <0 0x40000000 0 0xf1d>, 1876 <0 0x40000f20 0 0xa8>, 1877 <0 0x40001000 0 0x1000>, 1878 <0 0x40100000 0 0x100000>; 1879 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1880 device_type = "pci"; 1881 linux,pci-domain = <1>; 1882 bus-range = <0x00 0xff>; 1883 num-lanes = <2>; 1884 1885 #address-cells = <3>; 1886 #size-cells = <2>; 1887 1888 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1889 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1890 1891 /* 1892 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1893 * Hence, the IDs are swapped. 1894 */ 1895 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1896 <0x100 &gic_its 0x5a00 0x1>; 1897 msi-map-mask = <0xff00>; 1898 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1899 interrupt-names = "msi"; 1900 #interrupt-cells = <1>; 1901 interrupt-map-mask = <0 0 0 0x7>; 1902 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1903 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1904 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1905 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1906 1907 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1908 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1909 <&pcie1_lane>, 1910 <&rpmhcc RPMH_CXO_CLK>, 1911 <&gcc GCC_PCIE_1_AUX_CLK>, 1912 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1913 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1914 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1915 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1916 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1917 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1918 clock-names = "pipe", 1919 "pipe_mux", 1920 "phy_pipe", 1921 "ref", 1922 "aux", 1923 "cfg", 1924 "bus_master", 1925 "bus_slave", 1926 "slave_q2a", 1927 "ddrss_sf_tbu", 1928 "aggre1"; 1929 1930 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1931 <0x100 &apps_smmu 0x1c81 0x1>; 1932 1933 resets = <&gcc GCC_PCIE_1_BCR>; 1934 reset-names = "pci"; 1935 1936 power-domains = <&gcc PCIE_1_GDSC>; 1937 1938 phys = <&pcie1_lane>; 1939 phy-names = "pciephy"; 1940 1941 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1942 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1943 1944 pinctrl-names = "default"; 1945 pinctrl-0 = <&pcie1_default_state>; 1946 1947 status = "disabled"; 1948 }; 1949 1950 pcie1_phy: phy@1c0f000 { 1951 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1952 reg = <0 0x01c0f000 0 0x200>; 1953 #address-cells = <2>; 1954 #size-cells = <2>; 1955 ranges; 1956 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1957 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1958 <&gcc GCC_PCIE_1_CLKREF_EN>, 1959 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1960 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1961 1962 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1963 reset-names = "phy"; 1964 1965 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1966 assigned-clock-rates = <100000000>; 1967 1968 status = "disabled"; 1969 1970 pcie1_lane: phy@1c0e000 { 1971 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1972 <0 0x01c0e200 0 0x300>, /* rx */ 1973 <0 0x01c0f200 0 0x200>, /* pcs */ 1974 <0 0x01c0e800 0 0x200>, /* tx */ 1975 <0 0x01c0ea00 0 0x300>, /* rx */ 1976 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1977 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1978 clock-names = "pipe0"; 1979 1980 #clock-cells = <0>; 1981 #phy-cells = <0>; 1982 clock-output-names = "pcie_1_pipe_clk"; 1983 }; 1984 }; 1985 1986 config_noc: interconnect@1500000 { 1987 compatible = "qcom,sm8450-config-noc"; 1988 reg = <0 0x01500000 0 0x1c000>; 1989 #interconnect-cells = <2>; 1990 qcom,bcm-voters = <&apps_bcm_voter>; 1991 }; 1992 1993 system_noc: interconnect@1680000 { 1994 compatible = "qcom,sm8450-system-noc"; 1995 reg = <0 0x01680000 0 0x1e200>; 1996 #interconnect-cells = <2>; 1997 qcom,bcm-voters = <&apps_bcm_voter>; 1998 }; 1999 2000 pcie_noc: interconnect@16c0000 { 2001 compatible = "qcom,sm8450-pcie-anoc"; 2002 reg = <0 0x016c0000 0 0xe280>; 2003 #interconnect-cells = <2>; 2004 qcom,bcm-voters = <&apps_bcm_voter>; 2005 }; 2006 2007 aggre1_noc: interconnect@16e0000 { 2008 compatible = "qcom,sm8450-aggre1-noc"; 2009 reg = <0 0x016e0000 0 0x1c080>; 2010 #interconnect-cells = <2>; 2011 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2012 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2013 qcom,bcm-voters = <&apps_bcm_voter>; 2014 }; 2015 2016 aggre2_noc: interconnect@1700000 { 2017 compatible = "qcom,sm8450-aggre2-noc"; 2018 reg = <0 0x01700000 0 0x31080>; 2019 #interconnect-cells = <2>; 2020 qcom,bcm-voters = <&apps_bcm_voter>; 2021 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2022 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2023 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2024 <&rpmhcc RPMH_IPA_CLK>; 2025 }; 2026 2027 mmss_noc: interconnect@1740000 { 2028 compatible = "qcom,sm8450-mmss-noc"; 2029 reg = <0 0x01740000 0 0x1f080>; 2030 #interconnect-cells = <2>; 2031 qcom,bcm-voters = <&apps_bcm_voter>; 2032 }; 2033 2034 tcsr_mutex: hwlock@1f40000 { 2035 compatible = "qcom,tcsr-mutex"; 2036 reg = <0x0 0x01f40000 0x0 0x40000>; 2037 #hwlock-cells = <1>; 2038 }; 2039 2040 tcsr: syscon@1fc0000 { 2041 compatible = "qcom,sm8450-tcsr", "syscon"; 2042 reg = <0x0 0x1fc0000 0x0 0x30000>; 2043 }; 2044 2045 usb_1_hsphy: phy@88e3000 { 2046 compatible = "qcom,sm8450-usb-hs-phy", 2047 "qcom,usb-snps-hs-7nm-phy"; 2048 reg = <0 0x088e3000 0 0x400>; 2049 status = "disabled"; 2050 #phy-cells = <0>; 2051 2052 clocks = <&rpmhcc RPMH_CXO_CLK>; 2053 clock-names = "ref"; 2054 2055 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2056 }; 2057 2058 usb_1_qmpphy: phy@88e8000 { 2059 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2060 reg = <0 0x088e8000 0 0x3000>; 2061 2062 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2063 <&rpmhcc RPMH_CXO_CLK>, 2064 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2065 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2066 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2067 2068 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2069 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2070 reset-names = "phy", "common"; 2071 2072 #clock-cells = <1>; 2073 #phy-cells = <1>; 2074 2075 status = "disabled"; 2076 2077 ports { 2078 #address-cells = <1>; 2079 #size-cells = <0>; 2080 2081 port@0 { 2082 reg = <0>; 2083 2084 usb_1_qmpphy_out: endpoint { 2085 }; 2086 }; 2087 2088 port@1 { 2089 reg = <1>; 2090 2091 usb_1_qmpphy_usb_ss_in: endpoint { 2092 }; 2093 }; 2094 2095 port@2 { 2096 reg = <2>; 2097 2098 usb_1_qmpphy_dp_in: endpoint { 2099 }; 2100 }; 2101 }; 2102 }; 2103 2104 remoteproc_slpi: remoteproc@2400000 { 2105 compatible = "qcom,sm8450-slpi-pas"; 2106 reg = <0 0x02400000 0 0x4000>; 2107 2108 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2109 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2110 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2111 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2112 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2113 interrupt-names = "wdog", "fatal", "ready", 2114 "handover", "stop-ack"; 2115 2116 clocks = <&rpmhcc RPMH_CXO_CLK>; 2117 clock-names = "xo"; 2118 2119 power-domains = <&rpmhpd RPMHPD_LCX>, 2120 <&rpmhpd RPMHPD_LMX>; 2121 power-domain-names = "lcx", "lmx"; 2122 2123 memory-region = <&slpi_mem>; 2124 2125 qcom,qmp = <&aoss_qmp>; 2126 2127 qcom,smem-states = <&smp2p_slpi_out 0>; 2128 qcom,smem-state-names = "stop"; 2129 2130 status = "disabled"; 2131 2132 glink-edge { 2133 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2134 IPCC_MPROC_SIGNAL_GLINK_QMP 2135 IRQ_TYPE_EDGE_RISING>; 2136 mboxes = <&ipcc IPCC_CLIENT_SLPI 2137 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2138 2139 label = "slpi"; 2140 qcom,remote-pid = <3>; 2141 2142 fastrpc { 2143 compatible = "qcom,fastrpc"; 2144 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2145 label = "sdsp"; 2146 #address-cells = <1>; 2147 #size-cells = <0>; 2148 2149 compute-cb@1 { 2150 compatible = "qcom,fastrpc-compute-cb"; 2151 reg = <1>; 2152 iommus = <&apps_smmu 0x0541 0x0>; 2153 }; 2154 2155 compute-cb@2 { 2156 compatible = "qcom,fastrpc-compute-cb"; 2157 reg = <2>; 2158 iommus = <&apps_smmu 0x0542 0x0>; 2159 }; 2160 2161 compute-cb@3 { 2162 compatible = "qcom,fastrpc-compute-cb"; 2163 reg = <3>; 2164 iommus = <&apps_smmu 0x0543 0x0>; 2165 /* note: shared-cb = <4> in downstream */ 2166 }; 2167 }; 2168 }; 2169 }; 2170 2171 wsa2macro: codec@31e0000 { 2172 compatible = "qcom,sm8450-lpass-wsa-macro"; 2173 reg = <0 0x031e0000 0 0x1000>; 2174 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2175 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2176 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2177 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2178 <&vamacro>; 2179 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2180 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2181 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2182 assigned-clock-rates = <19200000>, <19200000>; 2183 2184 #clock-cells = <0>; 2185 clock-output-names = "wsa2-mclk"; 2186 pinctrl-names = "default"; 2187 pinctrl-0 = <&wsa2_swr_active>; 2188 #sound-dai-cells = <1>; 2189 }; 2190 2191 swr4: soundwire@31f0000 { 2192 compatible = "qcom,soundwire-v1.7.0"; 2193 reg = <0 0x031f0000 0 0x2000>; 2194 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2195 clocks = <&wsa2macro>; 2196 clock-names = "iface"; 2197 label = "WSA2"; 2198 2199 qcom,din-ports = <2>; 2200 qcom,dout-ports = <6>; 2201 2202 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2203 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2204 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2205 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2206 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2207 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2208 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2209 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2210 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2211 2212 #address-cells = <2>; 2213 #size-cells = <0>; 2214 #sound-dai-cells = <1>; 2215 status = "disabled"; 2216 }; 2217 2218 rxmacro: codec@3200000 { 2219 compatible = "qcom,sm8450-lpass-rx-macro"; 2220 reg = <0 0x03200000 0 0x1000>; 2221 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2222 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2223 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2224 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2225 <&vamacro>; 2226 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2227 2228 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2229 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2230 assigned-clock-rates = <19200000>, <19200000>; 2231 2232 #clock-cells = <0>; 2233 clock-output-names = "mclk"; 2234 pinctrl-names = "default"; 2235 pinctrl-0 = <&rx_swr_active>; 2236 #sound-dai-cells = <1>; 2237 }; 2238 2239 swr1: soundwire@3210000 { 2240 compatible = "qcom,soundwire-v1.7.0"; 2241 reg = <0 0x03210000 0 0x2000>; 2242 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2243 clocks = <&rxmacro>; 2244 clock-names = "iface"; 2245 label = "RX"; 2246 qcom,din-ports = <0>; 2247 qcom,dout-ports = <5>; 2248 2249 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2250 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2251 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2252 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2253 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2254 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2255 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2256 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2257 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2258 2259 #address-cells = <2>; 2260 #size-cells = <0>; 2261 #sound-dai-cells = <1>; 2262 status = "disabled"; 2263 }; 2264 2265 txmacro: codec@3220000 { 2266 compatible = "qcom,sm8450-lpass-tx-macro"; 2267 reg = <0 0x03220000 0 0x1000>; 2268 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2269 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2270 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2271 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2272 <&vamacro>; 2273 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2274 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2275 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2276 assigned-clock-rates = <19200000>, <19200000>; 2277 2278 #clock-cells = <0>; 2279 clock-output-names = "mclk"; 2280 pinctrl-names = "default"; 2281 pinctrl-0 = <&tx_swr_active>; 2282 #sound-dai-cells = <1>; 2283 }; 2284 2285 wsamacro: codec@3240000 { 2286 compatible = "qcom,sm8450-lpass-wsa-macro"; 2287 reg = <0 0x03240000 0 0x1000>; 2288 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2289 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2290 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2291 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2292 <&vamacro>; 2293 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2294 2295 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2296 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2297 assigned-clock-rates = <19200000>, <19200000>; 2298 2299 #clock-cells = <0>; 2300 clock-output-names = "mclk"; 2301 pinctrl-names = "default"; 2302 pinctrl-0 = <&wsa_swr_active>; 2303 #sound-dai-cells = <1>; 2304 }; 2305 2306 swr0: soundwire@3250000 { 2307 compatible = "qcom,soundwire-v1.7.0"; 2308 reg = <0 0x03250000 0 0x2000>; 2309 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2310 clocks = <&wsamacro>; 2311 clock-names = "iface"; 2312 label = "WSA"; 2313 2314 qcom,din-ports = <2>; 2315 qcom,dout-ports = <6>; 2316 2317 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2318 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2319 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2320 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2321 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2322 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2323 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2324 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2325 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2326 2327 #address-cells = <2>; 2328 #size-cells = <0>; 2329 #sound-dai-cells = <1>; 2330 status = "disabled"; 2331 }; 2332 2333 swr2: soundwire@33b0000 { 2334 compatible = "qcom,soundwire-v1.7.0"; 2335 reg = <0 0x033b0000 0 0x2000>; 2336 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2338 interrupt-names = "core", "wakeup"; 2339 2340 clocks = <&txmacro>; 2341 clock-names = "iface"; 2342 label = "TX"; 2343 2344 qcom,din-ports = <4>; 2345 qcom,dout-ports = <0>; 2346 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2347 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2348 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2349 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2350 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2351 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2352 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2353 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2354 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2355 2356 #address-cells = <2>; 2357 #size-cells = <0>; 2358 #sound-dai-cells = <1>; 2359 status = "disabled"; 2360 }; 2361 2362 vamacro: codec@33f0000 { 2363 compatible = "qcom,sm8450-lpass-va-macro"; 2364 reg = <0 0x033f0000 0 0x1000>; 2365 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2366 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2367 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2368 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2369 clock-names = "mclk", "macro", "dcodec", "npl"; 2370 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2371 assigned-clock-rates = <19200000>; 2372 2373 #clock-cells = <0>; 2374 clock-output-names = "fsgen"; 2375 #sound-dai-cells = <1>; 2376 status = "disabled"; 2377 }; 2378 2379 remoteproc_adsp: remoteproc@30000000 { 2380 compatible = "qcom,sm8450-adsp-pas"; 2381 reg = <0 0x30000000 0 0x100>; 2382 2383 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2384 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2385 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2386 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2387 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2388 interrupt-names = "wdog", "fatal", "ready", 2389 "handover", "stop-ack"; 2390 2391 clocks = <&rpmhcc RPMH_CXO_CLK>; 2392 clock-names = "xo"; 2393 2394 power-domains = <&rpmhpd RPMHPD_LCX>, 2395 <&rpmhpd RPMHPD_LMX>; 2396 power-domain-names = "lcx", "lmx"; 2397 2398 memory-region = <&adsp_mem>; 2399 2400 qcom,qmp = <&aoss_qmp>; 2401 2402 qcom,smem-states = <&smp2p_adsp_out 0>; 2403 qcom,smem-state-names = "stop"; 2404 2405 status = "disabled"; 2406 2407 remoteproc_adsp_glink: glink-edge { 2408 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2409 IPCC_MPROC_SIGNAL_GLINK_QMP 2410 IRQ_TYPE_EDGE_RISING>; 2411 mboxes = <&ipcc IPCC_CLIENT_LPASS 2412 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2413 2414 label = "lpass"; 2415 qcom,remote-pid = <2>; 2416 2417 gpr { 2418 compatible = "qcom,gpr"; 2419 qcom,glink-channels = "adsp_apps"; 2420 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2421 qcom,intents = <512 20>; 2422 #address-cells = <1>; 2423 #size-cells = <0>; 2424 2425 q6apm: service@1 { 2426 compatible = "qcom,q6apm"; 2427 reg = <GPR_APM_MODULE_IID>; 2428 #sound-dai-cells = <0>; 2429 qcom,protection-domain = "avs/audio", 2430 "msm/adsp/audio_pd"; 2431 2432 q6apmdai: dais { 2433 compatible = "qcom,q6apm-dais"; 2434 iommus = <&apps_smmu 0x1801 0x0>; 2435 }; 2436 2437 q6apmbedai: bedais { 2438 compatible = "qcom,q6apm-lpass-dais"; 2439 #sound-dai-cells = <1>; 2440 }; 2441 }; 2442 2443 q6prm: service@2 { 2444 compatible = "qcom,q6prm"; 2445 reg = <GPR_PRM_MODULE_IID>; 2446 qcom,protection-domain = "avs/audio", 2447 "msm/adsp/audio_pd"; 2448 2449 q6prmcc: clock-controller { 2450 compatible = "qcom,q6prm-lpass-clocks"; 2451 #clock-cells = <2>; 2452 }; 2453 }; 2454 }; 2455 2456 fastrpc { 2457 compatible = "qcom,fastrpc"; 2458 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2459 label = "adsp"; 2460 #address-cells = <1>; 2461 #size-cells = <0>; 2462 2463 compute-cb@3 { 2464 compatible = "qcom,fastrpc-compute-cb"; 2465 reg = <3>; 2466 iommus = <&apps_smmu 0x1803 0x0>; 2467 }; 2468 2469 compute-cb@4 { 2470 compatible = "qcom,fastrpc-compute-cb"; 2471 reg = <4>; 2472 iommus = <&apps_smmu 0x1804 0x0>; 2473 }; 2474 2475 compute-cb@5 { 2476 compatible = "qcom,fastrpc-compute-cb"; 2477 reg = <5>; 2478 iommus = <&apps_smmu 0x1805 0x0>; 2479 }; 2480 }; 2481 }; 2482 }; 2483 2484 remoteproc_cdsp: remoteproc@32300000 { 2485 compatible = "qcom,sm8450-cdsp-pas"; 2486 reg = <0 0x32300000 0 0x1400000>; 2487 2488 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2489 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2490 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2491 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2492 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2493 interrupt-names = "wdog", "fatal", "ready", 2494 "handover", "stop-ack"; 2495 2496 clocks = <&rpmhcc RPMH_CXO_CLK>; 2497 clock-names = "xo"; 2498 2499 power-domains = <&rpmhpd RPMHPD_CX>, 2500 <&rpmhpd RPMHPD_MXC>; 2501 power-domain-names = "cx", "mxc"; 2502 2503 memory-region = <&cdsp_mem>; 2504 2505 qcom,qmp = <&aoss_qmp>; 2506 2507 qcom,smem-states = <&smp2p_cdsp_out 0>; 2508 qcom,smem-state-names = "stop"; 2509 2510 status = "disabled"; 2511 2512 glink-edge { 2513 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2514 IPCC_MPROC_SIGNAL_GLINK_QMP 2515 IRQ_TYPE_EDGE_RISING>; 2516 mboxes = <&ipcc IPCC_CLIENT_CDSP 2517 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2518 2519 label = "cdsp"; 2520 qcom,remote-pid = <5>; 2521 2522 fastrpc { 2523 compatible = "qcom,fastrpc"; 2524 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2525 label = "cdsp"; 2526 #address-cells = <1>; 2527 #size-cells = <0>; 2528 2529 compute-cb@1 { 2530 compatible = "qcom,fastrpc-compute-cb"; 2531 reg = <1>; 2532 iommus = <&apps_smmu 0x2161 0x0400>, 2533 <&apps_smmu 0x1021 0x1420>; 2534 }; 2535 2536 compute-cb@2 { 2537 compatible = "qcom,fastrpc-compute-cb"; 2538 reg = <2>; 2539 iommus = <&apps_smmu 0x2162 0x0400>, 2540 <&apps_smmu 0x1022 0x1420>; 2541 }; 2542 2543 compute-cb@3 { 2544 compatible = "qcom,fastrpc-compute-cb"; 2545 reg = <3>; 2546 iommus = <&apps_smmu 0x2163 0x0400>, 2547 <&apps_smmu 0x1023 0x1420>; 2548 }; 2549 2550 compute-cb@4 { 2551 compatible = "qcom,fastrpc-compute-cb"; 2552 reg = <4>; 2553 iommus = <&apps_smmu 0x2164 0x0400>, 2554 <&apps_smmu 0x1024 0x1420>; 2555 }; 2556 2557 compute-cb@5 { 2558 compatible = "qcom,fastrpc-compute-cb"; 2559 reg = <5>; 2560 iommus = <&apps_smmu 0x2165 0x0400>, 2561 <&apps_smmu 0x1025 0x1420>; 2562 }; 2563 2564 compute-cb@6 { 2565 compatible = "qcom,fastrpc-compute-cb"; 2566 reg = <6>; 2567 iommus = <&apps_smmu 0x2166 0x0400>, 2568 <&apps_smmu 0x1026 0x1420>; 2569 }; 2570 2571 compute-cb@7 { 2572 compatible = "qcom,fastrpc-compute-cb"; 2573 reg = <7>; 2574 iommus = <&apps_smmu 0x2167 0x0400>, 2575 <&apps_smmu 0x1027 0x1420>; 2576 }; 2577 2578 compute-cb@8 { 2579 compatible = "qcom,fastrpc-compute-cb"; 2580 reg = <8>; 2581 iommus = <&apps_smmu 0x2168 0x0400>, 2582 <&apps_smmu 0x1028 0x1420>; 2583 }; 2584 2585 /* note: secure cb9 in downstream */ 2586 }; 2587 }; 2588 }; 2589 2590 remoteproc_mpss: remoteproc@4080000 { 2591 compatible = "qcom,sm8450-mpss-pas"; 2592 reg = <0x0 0x04080000 0x0 0x4040>; 2593 2594 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2595 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2596 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2597 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2598 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2599 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2600 interrupt-names = "wdog", "fatal", "ready", "handover", 2601 "stop-ack", "shutdown-ack"; 2602 2603 clocks = <&rpmhcc RPMH_CXO_CLK>; 2604 clock-names = "xo"; 2605 2606 power-domains = <&rpmhpd RPMHPD_CX>, 2607 <&rpmhpd RPMHPD_MSS>; 2608 power-domain-names = "cx", "mss"; 2609 2610 memory-region = <&mpss_mem>; 2611 2612 qcom,qmp = <&aoss_qmp>; 2613 2614 qcom,smem-states = <&smp2p_modem_out 0>; 2615 qcom,smem-state-names = "stop"; 2616 2617 status = "disabled"; 2618 2619 glink-edge { 2620 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2621 IPCC_MPROC_SIGNAL_GLINK_QMP 2622 IRQ_TYPE_EDGE_RISING>; 2623 mboxes = <&ipcc IPCC_CLIENT_MPSS 2624 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2625 label = "modem"; 2626 qcom,remote-pid = <1>; 2627 }; 2628 }; 2629 2630 videocc: clock-controller@aaf0000 { 2631 compatible = "qcom,sm8450-videocc"; 2632 reg = <0 0x0aaf0000 0 0x10000>; 2633 clocks = <&rpmhcc RPMH_CXO_CLK>, 2634 <&gcc GCC_VIDEO_AHB_CLK>; 2635 power-domains = <&rpmhpd RPMHPD_MMCX>; 2636 required-opps = <&rpmhpd_opp_low_svs>; 2637 #clock-cells = <1>; 2638 #reset-cells = <1>; 2639 #power-domain-cells = <1>; 2640 }; 2641 2642 cci0: cci@ac15000 { 2643 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2644 reg = <0 0x0ac15000 0 0x1000>; 2645 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2646 power-domains = <&camcc TITAN_TOP_GDSC>; 2647 2648 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2649 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2650 <&camcc CAM_CC_CPAS_AHB_CLK>, 2651 <&camcc CAM_CC_CCI_0_CLK>, 2652 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2653 clock-names = "camnoc_axi", 2654 "slow_ahb_src", 2655 "cpas_ahb", 2656 "cci", 2657 "cci_src"; 2658 pinctrl-0 = <&cci0_default &cci1_default>; 2659 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2660 pinctrl-names = "default", "sleep"; 2661 2662 status = "disabled"; 2663 #address-cells = <1>; 2664 #size-cells = <0>; 2665 2666 cci0_i2c0: i2c-bus@0 { 2667 reg = <0>; 2668 clock-frequency = <1000000>; 2669 #address-cells = <1>; 2670 #size-cells = <0>; 2671 }; 2672 2673 cci0_i2c1: i2c-bus@1 { 2674 reg = <1>; 2675 clock-frequency = <1000000>; 2676 #address-cells = <1>; 2677 #size-cells = <0>; 2678 }; 2679 }; 2680 2681 cci1: cci@ac16000 { 2682 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2683 reg = <0 0x0ac16000 0 0x1000>; 2684 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2685 power-domains = <&camcc TITAN_TOP_GDSC>; 2686 2687 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2688 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2689 <&camcc CAM_CC_CPAS_AHB_CLK>, 2690 <&camcc CAM_CC_CCI_1_CLK>, 2691 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2692 clock-names = "camnoc_axi", 2693 "slow_ahb_src", 2694 "cpas_ahb", 2695 "cci", 2696 "cci_src"; 2697 pinctrl-0 = <&cci2_default &cci3_default>; 2698 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2699 pinctrl-names = "default", "sleep"; 2700 2701 status = "disabled"; 2702 #address-cells = <1>; 2703 #size-cells = <0>; 2704 2705 cci1_i2c0: i2c-bus@0 { 2706 reg = <0>; 2707 clock-frequency = <1000000>; 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 }; 2711 2712 cci1_i2c1: i2c-bus@1 { 2713 reg = <1>; 2714 clock-frequency = <1000000>; 2715 #address-cells = <1>; 2716 #size-cells = <0>; 2717 }; 2718 }; 2719 2720 camcc: clock-controller@ade0000 { 2721 compatible = "qcom,sm8450-camcc"; 2722 reg = <0 0x0ade0000 0 0x20000>; 2723 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2724 <&rpmhcc RPMH_CXO_CLK>, 2725 <&rpmhcc RPMH_CXO_CLK_A>, 2726 <&sleep_clk>; 2727 power-domains = <&rpmhpd RPMHPD_MMCX>; 2728 required-opps = <&rpmhpd_opp_low_svs>; 2729 #clock-cells = <1>; 2730 #reset-cells = <1>; 2731 #power-domain-cells = <1>; 2732 status = "disabled"; 2733 }; 2734 2735 mdss: display-subsystem@ae00000 { 2736 compatible = "qcom,sm8450-mdss"; 2737 reg = <0 0x0ae00000 0 0x1000>; 2738 reg-names = "mdss"; 2739 2740 /* same path used twice */ 2741 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2742 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2743 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2744 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2745 interconnect-names = "mdp0-mem", 2746 "mdp1-mem", 2747 "cpu-cfg"; 2748 2749 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2750 2751 power-domains = <&dispcc MDSS_GDSC>; 2752 2753 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2754 <&gcc GCC_DISP_HF_AXI_CLK>, 2755 <&gcc GCC_DISP_SF_AXI_CLK>, 2756 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2757 2758 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2759 interrupt-controller; 2760 #interrupt-cells = <1>; 2761 2762 iommus = <&apps_smmu 0x2800 0x402>; 2763 2764 #address-cells = <2>; 2765 #size-cells = <2>; 2766 ranges; 2767 2768 status = "disabled"; 2769 2770 mdss_mdp: display-controller@ae01000 { 2771 compatible = "qcom,sm8450-dpu"; 2772 reg = <0 0x0ae01000 0 0x8f000>, 2773 <0 0x0aeb0000 0 0x2008>; 2774 reg-names = "mdp", "vbif"; 2775 2776 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2777 <&gcc GCC_DISP_SF_AXI_CLK>, 2778 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2779 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2780 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2781 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2782 clock-names = "bus", 2783 "nrt_bus", 2784 "iface", 2785 "lut", 2786 "core", 2787 "vsync"; 2788 2789 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2790 assigned-clock-rates = <19200000>; 2791 2792 operating-points-v2 = <&mdp_opp_table>; 2793 power-domains = <&rpmhpd RPMHPD_MMCX>; 2794 2795 interrupt-parent = <&mdss>; 2796 interrupts = <0>; 2797 2798 ports { 2799 #address-cells = <1>; 2800 #size-cells = <0>; 2801 2802 port@0 { 2803 reg = <0>; 2804 dpu_intf1_out: endpoint { 2805 remote-endpoint = <&mdss_dsi0_in>; 2806 }; 2807 }; 2808 2809 port@1 { 2810 reg = <1>; 2811 dpu_intf2_out: endpoint { 2812 remote-endpoint = <&mdss_dsi1_in>; 2813 }; 2814 }; 2815 2816 port@2 { 2817 reg = <2>; 2818 dpu_intf0_out: endpoint { 2819 remote-endpoint = <&mdss_dp0_in>; 2820 }; 2821 }; 2822 }; 2823 2824 mdp_opp_table: opp-table { 2825 compatible = "operating-points-v2"; 2826 2827 opp-172000000 { 2828 opp-hz = /bits/ 64 <172000000>; 2829 required-opps = <&rpmhpd_opp_low_svs_d1>; 2830 }; 2831 2832 opp-200000000 { 2833 opp-hz = /bits/ 64 <200000000>; 2834 required-opps = <&rpmhpd_opp_low_svs>; 2835 }; 2836 2837 opp-325000000 { 2838 opp-hz = /bits/ 64 <325000000>; 2839 required-opps = <&rpmhpd_opp_svs>; 2840 }; 2841 2842 opp-375000000 { 2843 opp-hz = /bits/ 64 <375000000>; 2844 required-opps = <&rpmhpd_opp_svs_l1>; 2845 }; 2846 2847 opp-500000000 { 2848 opp-hz = /bits/ 64 <500000000>; 2849 required-opps = <&rpmhpd_opp_nom>; 2850 }; 2851 }; 2852 }; 2853 2854 mdss_dp0: displayport-controller@ae90000 { 2855 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2856 reg = <0 0xae90000 0 0x200>, 2857 <0 0xae90200 0 0x200>, 2858 <0 0xae90400 0 0xc00>, 2859 <0 0xae91000 0 0x400>, 2860 <0 0xae91400 0 0x400>; 2861 interrupt-parent = <&mdss>; 2862 interrupts = <12>; 2863 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2864 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2865 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2866 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2867 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2868 clock-names = "core_iface", 2869 "core_aux", 2870 "ctrl_link", 2871 "ctrl_link_iface", 2872 "stream_pixel"; 2873 2874 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2875 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2876 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2877 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2878 2879 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2880 phy-names = "dp"; 2881 2882 #sound-dai-cells = <0>; 2883 2884 operating-points-v2 = <&dp_opp_table>; 2885 power-domains = <&rpmhpd RPMHPD_MMCX>; 2886 2887 status = "disabled"; 2888 2889 ports { 2890 #address-cells = <1>; 2891 #size-cells = <0>; 2892 2893 port@0 { 2894 reg = <0>; 2895 mdss_dp0_in: endpoint { 2896 remote-endpoint = <&dpu_intf0_out>; 2897 }; 2898 }; 2899 }; 2900 2901 dp_opp_table: opp-table { 2902 compatible = "operating-points-v2"; 2903 2904 opp-160000000 { 2905 opp-hz = /bits/ 64 <160000000>; 2906 required-opps = <&rpmhpd_opp_low_svs>; 2907 }; 2908 2909 opp-270000000 { 2910 opp-hz = /bits/ 64 <270000000>; 2911 required-opps = <&rpmhpd_opp_svs>; 2912 }; 2913 2914 opp-540000000 { 2915 opp-hz = /bits/ 64 <540000000>; 2916 required-opps = <&rpmhpd_opp_svs_l1>; 2917 }; 2918 2919 opp-810000000 { 2920 opp-hz = /bits/ 64 <810000000>; 2921 required-opps = <&rpmhpd_opp_nom>; 2922 }; 2923 }; 2924 }; 2925 2926 mdss_dsi0: dsi@ae94000 { 2927 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2928 reg = <0 0x0ae94000 0 0x400>; 2929 reg-names = "dsi_ctrl"; 2930 2931 interrupt-parent = <&mdss>; 2932 interrupts = <4>; 2933 2934 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2935 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2936 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2937 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2938 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2939 <&gcc GCC_DISP_HF_AXI_CLK>; 2940 clock-names = "byte", 2941 "byte_intf", 2942 "pixel", 2943 "core", 2944 "iface", 2945 "bus"; 2946 2947 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2948 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2949 2950 operating-points-v2 = <&mdss_dsi_opp_table>; 2951 power-domains = <&rpmhpd RPMHPD_MMCX>; 2952 2953 phys = <&mdss_dsi0_phy>; 2954 phy-names = "dsi"; 2955 2956 #address-cells = <1>; 2957 #size-cells = <0>; 2958 2959 status = "disabled"; 2960 2961 ports { 2962 #address-cells = <1>; 2963 #size-cells = <0>; 2964 2965 port@0 { 2966 reg = <0>; 2967 mdss_dsi0_in: endpoint { 2968 remote-endpoint = <&dpu_intf1_out>; 2969 }; 2970 }; 2971 2972 port@1 { 2973 reg = <1>; 2974 mdss_dsi0_out: endpoint { 2975 }; 2976 }; 2977 }; 2978 2979 mdss_dsi_opp_table: opp-table { 2980 compatible = "operating-points-v2"; 2981 2982 opp-187500000 { 2983 opp-hz = /bits/ 64 <187500000>; 2984 required-opps = <&rpmhpd_opp_low_svs>; 2985 }; 2986 2987 opp-300000000 { 2988 opp-hz = /bits/ 64 <300000000>; 2989 required-opps = <&rpmhpd_opp_svs>; 2990 }; 2991 2992 opp-358000000 { 2993 opp-hz = /bits/ 64 <358000000>; 2994 required-opps = <&rpmhpd_opp_svs_l1>; 2995 }; 2996 }; 2997 }; 2998 2999 mdss_dsi0_phy: phy@ae94400 { 3000 compatible = "qcom,sm8450-dsi-phy-5nm"; 3001 reg = <0 0x0ae94400 0 0x200>, 3002 <0 0x0ae94600 0 0x280>, 3003 <0 0x0ae94900 0 0x260>; 3004 reg-names = "dsi_phy", 3005 "dsi_phy_lane", 3006 "dsi_pll"; 3007 3008 #clock-cells = <1>; 3009 #phy-cells = <0>; 3010 3011 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3012 <&rpmhcc RPMH_CXO_CLK>; 3013 clock-names = "iface", "ref"; 3014 3015 status = "disabled"; 3016 }; 3017 3018 mdss_dsi1: dsi@ae96000 { 3019 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3020 reg = <0 0x0ae96000 0 0x400>; 3021 reg-names = "dsi_ctrl"; 3022 3023 interrupt-parent = <&mdss>; 3024 interrupts = <5>; 3025 3026 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3027 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3028 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3029 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3030 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3031 <&gcc GCC_DISP_HF_AXI_CLK>; 3032 clock-names = "byte", 3033 "byte_intf", 3034 "pixel", 3035 "core", 3036 "iface", 3037 "bus"; 3038 3039 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3040 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3041 3042 operating-points-v2 = <&mdss_dsi_opp_table>; 3043 power-domains = <&rpmhpd RPMHPD_MMCX>; 3044 3045 phys = <&mdss_dsi1_phy>; 3046 phy-names = "dsi"; 3047 3048 #address-cells = <1>; 3049 #size-cells = <0>; 3050 3051 status = "disabled"; 3052 3053 ports { 3054 #address-cells = <1>; 3055 #size-cells = <0>; 3056 3057 port@0 { 3058 reg = <0>; 3059 mdss_dsi1_in: endpoint { 3060 remote-endpoint = <&dpu_intf2_out>; 3061 }; 3062 }; 3063 3064 port@1 { 3065 reg = <1>; 3066 mdss_dsi1_out: endpoint { 3067 }; 3068 }; 3069 }; 3070 }; 3071 3072 mdss_dsi1_phy: phy@ae96400 { 3073 compatible = "qcom,sm8450-dsi-phy-5nm"; 3074 reg = <0 0x0ae96400 0 0x200>, 3075 <0 0x0ae96600 0 0x280>, 3076 <0 0x0ae96900 0 0x260>; 3077 reg-names = "dsi_phy", 3078 "dsi_phy_lane", 3079 "dsi_pll"; 3080 3081 #clock-cells = <1>; 3082 #phy-cells = <0>; 3083 3084 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3085 <&rpmhcc RPMH_CXO_CLK>; 3086 clock-names = "iface", "ref"; 3087 3088 status = "disabled"; 3089 }; 3090 }; 3091 3092 dispcc: clock-controller@af00000 { 3093 compatible = "qcom,sm8450-dispcc"; 3094 reg = <0 0x0af00000 0 0x20000>; 3095 clocks = <&rpmhcc RPMH_CXO_CLK>, 3096 <&rpmhcc RPMH_CXO_CLK_A>, 3097 <&gcc GCC_DISP_AHB_CLK>, 3098 <&sleep_clk>, 3099 <&mdss_dsi0_phy 0>, 3100 <&mdss_dsi0_phy 1>, 3101 <&mdss_dsi1_phy 0>, 3102 <&mdss_dsi1_phy 1>, 3103 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3104 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3105 <0>, /* dp1 */ 3106 <0>, 3107 <0>, /* dp2 */ 3108 <0>, 3109 <0>, /* dp3 */ 3110 <0>; 3111 power-domains = <&rpmhpd RPMHPD_MMCX>; 3112 required-opps = <&rpmhpd_opp_low_svs>; 3113 #clock-cells = <1>; 3114 #reset-cells = <1>; 3115 #power-domain-cells = <1>; 3116 status = "disabled"; 3117 }; 3118 3119 pdc: interrupt-controller@b220000 { 3120 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3121 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3122 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3123 <94 609 31>, <125 63 1>, <126 716 12>; 3124 #interrupt-cells = <2>; 3125 interrupt-parent = <&intc>; 3126 interrupt-controller; 3127 }; 3128 3129 tsens0: thermal-sensor@c263000 { 3130 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3131 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3132 <0 0x0c222000 0 0x1000>; /* SROT */ 3133 #qcom,sensors = <16>; 3134 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3136 interrupt-names = "uplow", "critical"; 3137 #thermal-sensor-cells = <1>; 3138 }; 3139 3140 tsens1: thermal-sensor@c265000 { 3141 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3142 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3143 <0 0x0c223000 0 0x1000>; /* SROT */ 3144 #qcom,sensors = <16>; 3145 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3147 interrupt-names = "uplow", "critical"; 3148 #thermal-sensor-cells = <1>; 3149 }; 3150 3151 aoss_qmp: power-management@c300000 { 3152 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3153 reg = <0 0x0c300000 0 0x400>; 3154 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3155 IRQ_TYPE_EDGE_RISING>; 3156 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3157 3158 #clock-cells = <0>; 3159 }; 3160 3161 sram@c3f0000 { 3162 compatible = "qcom,rpmh-stats"; 3163 reg = <0 0x0c3f0000 0 0x400>; 3164 }; 3165 3166 spmi_bus: spmi@c400000 { 3167 compatible = "qcom,spmi-pmic-arb"; 3168 reg = <0 0x0c400000 0 0x00003000>, 3169 <0 0x0c500000 0 0x00400000>, 3170 <0 0x0c440000 0 0x00080000>, 3171 <0 0x0c4c0000 0 0x00010000>, 3172 <0 0x0c42d000 0 0x00010000>; 3173 reg-names = "core", 3174 "chnls", 3175 "obsrvr", 3176 "intr", 3177 "cnfg"; 3178 interrupt-names = "periph_irq"; 3179 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3180 qcom,ee = <0>; 3181 qcom,channel = <0>; 3182 interrupt-controller; 3183 #interrupt-cells = <4>; 3184 #address-cells = <2>; 3185 #size-cells = <0>; 3186 }; 3187 3188 ipcc: mailbox@ed18000 { 3189 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3190 reg = <0 0x0ed18000 0 0x1000>; 3191 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3192 interrupt-controller; 3193 #interrupt-cells = <3>; 3194 #mbox-cells = <2>; 3195 }; 3196 3197 tlmm: pinctrl@f100000 { 3198 compatible = "qcom,sm8450-tlmm"; 3199 reg = <0 0x0f100000 0 0x300000>; 3200 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3201 gpio-controller; 3202 #gpio-cells = <2>; 3203 interrupt-controller; 3204 #interrupt-cells = <2>; 3205 gpio-ranges = <&tlmm 0 0 211>; 3206 wakeup-parent = <&pdc>; 3207 3208 sdc2_default_state: sdc2-default-state { 3209 clk-pins { 3210 pins = "sdc2_clk"; 3211 drive-strength = <16>; 3212 bias-disable; 3213 }; 3214 3215 cmd-pins { 3216 pins = "sdc2_cmd"; 3217 drive-strength = <16>; 3218 bias-pull-up; 3219 }; 3220 3221 data-pins { 3222 pins = "sdc2_data"; 3223 drive-strength = <16>; 3224 bias-pull-up; 3225 }; 3226 }; 3227 3228 sdc2_sleep_state: sdc2-sleep-state { 3229 clk-pins { 3230 pins = "sdc2_clk"; 3231 drive-strength = <2>; 3232 bias-disable; 3233 }; 3234 3235 cmd-pins { 3236 pins = "sdc2_cmd"; 3237 drive-strength = <2>; 3238 bias-pull-up; 3239 }; 3240 3241 data-pins { 3242 pins = "sdc2_data"; 3243 drive-strength = <2>; 3244 bias-pull-up; 3245 }; 3246 }; 3247 3248 cci0_default: cci0-default-state { 3249 /* SDA, SCL */ 3250 pins = "gpio110", "gpio111"; 3251 function = "cci_i2c"; 3252 drive-strength = <2>; 3253 bias-pull-up; 3254 }; 3255 3256 cci0_sleep: cci0-sleep-state { 3257 /* SDA, SCL */ 3258 pins = "gpio110", "gpio111"; 3259 function = "cci_i2c"; 3260 drive-strength = <2>; 3261 bias-pull-down; 3262 }; 3263 3264 cci1_default: cci1-default-state { 3265 /* SDA, SCL */ 3266 pins = "gpio112", "gpio113"; 3267 function = "cci_i2c"; 3268 drive-strength = <2>; 3269 bias-pull-up; 3270 }; 3271 3272 cci1_sleep: cci1-sleep-state { 3273 /* SDA, SCL */ 3274 pins = "gpio112", "gpio113"; 3275 function = "cci_i2c"; 3276 drive-strength = <2>; 3277 bias-pull-down; 3278 }; 3279 3280 cci2_default: cci2-default-state { 3281 /* SDA, SCL */ 3282 pins = "gpio114", "gpio115"; 3283 function = "cci_i2c"; 3284 drive-strength = <2>; 3285 bias-pull-up; 3286 }; 3287 3288 cci2_sleep: cci2-sleep-state { 3289 /* SDA, SCL */ 3290 pins = "gpio114", "gpio115"; 3291 function = "cci_i2c"; 3292 drive-strength = <2>; 3293 bias-pull-down; 3294 }; 3295 3296 cci3_default: cci3-default-state { 3297 /* SDA, SCL */ 3298 pins = "gpio208", "gpio209"; 3299 function = "cci_i2c"; 3300 drive-strength = <2>; 3301 bias-pull-up; 3302 }; 3303 3304 cci3_sleep: cci3-sleep-state { 3305 /* SDA, SCL */ 3306 pins = "gpio208", "gpio209"; 3307 function = "cci_i2c"; 3308 drive-strength = <2>; 3309 bias-pull-down; 3310 }; 3311 3312 pcie0_default_state: pcie0-default-state { 3313 perst-pins { 3314 pins = "gpio94"; 3315 function = "gpio"; 3316 drive-strength = <2>; 3317 bias-pull-down; 3318 }; 3319 3320 clkreq-pins { 3321 pins = "gpio95"; 3322 function = "pcie0_clkreqn"; 3323 drive-strength = <2>; 3324 bias-pull-up; 3325 }; 3326 3327 wake-pins { 3328 pins = "gpio96"; 3329 function = "gpio"; 3330 drive-strength = <2>; 3331 bias-pull-up; 3332 }; 3333 }; 3334 3335 pcie1_default_state: pcie1-default-state { 3336 perst-pins { 3337 pins = "gpio97"; 3338 function = "gpio"; 3339 drive-strength = <2>; 3340 bias-pull-down; 3341 }; 3342 3343 clkreq-pins { 3344 pins = "gpio98"; 3345 function = "pcie1_clkreqn"; 3346 drive-strength = <2>; 3347 bias-pull-up; 3348 }; 3349 3350 wake-pins { 3351 pins = "gpio99"; 3352 function = "gpio"; 3353 drive-strength = <2>; 3354 bias-pull-up; 3355 }; 3356 }; 3357 3358 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3359 pins = "gpio0", "gpio1"; 3360 function = "qup0"; 3361 }; 3362 3363 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3364 pins = "gpio4", "gpio5"; 3365 function = "qup1"; 3366 }; 3367 3368 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3369 pins = "gpio8", "gpio9"; 3370 function = "qup2"; 3371 }; 3372 3373 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3374 pins = "gpio12", "gpio13"; 3375 function = "qup3"; 3376 }; 3377 3378 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3379 pins = "gpio16", "gpio17"; 3380 function = "qup4"; 3381 }; 3382 3383 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3384 pins = "gpio206", "gpio207"; 3385 function = "qup5"; 3386 }; 3387 3388 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3389 pins = "gpio20", "gpio21"; 3390 function = "qup6"; 3391 }; 3392 3393 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3394 pins = "gpio28", "gpio29"; 3395 function = "qup8"; 3396 }; 3397 3398 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3399 pins = "gpio32", "gpio33"; 3400 function = "qup9"; 3401 }; 3402 3403 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3404 pins = "gpio36", "gpio37"; 3405 function = "qup10"; 3406 }; 3407 3408 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3409 pins = "gpio40", "gpio41"; 3410 function = "qup11"; 3411 }; 3412 3413 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3414 pins = "gpio44", "gpio45"; 3415 function = "qup12"; 3416 }; 3417 3418 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3419 pins = "gpio48", "gpio49"; 3420 function = "qup13"; 3421 drive-strength = <2>; 3422 bias-pull-up; 3423 }; 3424 3425 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3426 pins = "gpio52", "gpio53"; 3427 function = "qup14"; 3428 drive-strength = <2>; 3429 bias-pull-up; 3430 }; 3431 3432 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3433 pins = "gpio56", "gpio57"; 3434 function = "qup15"; 3435 }; 3436 3437 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3438 pins = "gpio60", "gpio61"; 3439 function = "qup16"; 3440 }; 3441 3442 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3443 pins = "gpio64", "gpio65"; 3444 function = "qup17"; 3445 }; 3446 3447 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3448 pins = "gpio68", "gpio69"; 3449 function = "qup18"; 3450 }; 3451 3452 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3453 pins = "gpio72", "gpio73"; 3454 function = "qup19"; 3455 }; 3456 3457 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3458 pins = "gpio76", "gpio77"; 3459 function = "qup20"; 3460 }; 3461 3462 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3463 pins = "gpio80", "gpio81"; 3464 function = "qup21"; 3465 }; 3466 3467 qup_spi0_cs: qup-spi0-cs-state { 3468 pins = "gpio3"; 3469 function = "qup0"; 3470 }; 3471 3472 qup_spi0_data_clk: qup-spi0-data-clk-state { 3473 pins = "gpio0", "gpio1", "gpio2"; 3474 function = "qup0"; 3475 }; 3476 3477 qup_spi1_cs: qup-spi1-cs-state { 3478 pins = "gpio7"; 3479 function = "qup1"; 3480 }; 3481 3482 qup_spi1_data_clk: qup-spi1-data-clk-state { 3483 pins = "gpio4", "gpio5", "gpio6"; 3484 function = "qup1"; 3485 }; 3486 3487 qup_spi2_cs: qup-spi2-cs-state { 3488 pins = "gpio11"; 3489 function = "qup2"; 3490 }; 3491 3492 qup_spi2_data_clk: qup-spi2-data-clk-state { 3493 pins = "gpio8", "gpio9", "gpio10"; 3494 function = "qup2"; 3495 }; 3496 3497 qup_spi3_cs: qup-spi3-cs-state { 3498 pins = "gpio15"; 3499 function = "qup3"; 3500 }; 3501 3502 qup_spi3_data_clk: qup-spi3-data-clk-state { 3503 pins = "gpio12", "gpio13", "gpio14"; 3504 function = "qup3"; 3505 }; 3506 3507 qup_spi4_cs: qup-spi4-cs-state { 3508 pins = "gpio19"; 3509 function = "qup4"; 3510 drive-strength = <6>; 3511 bias-disable; 3512 }; 3513 3514 qup_spi4_data_clk: qup-spi4-data-clk-state { 3515 pins = "gpio16", "gpio17", "gpio18"; 3516 function = "qup4"; 3517 }; 3518 3519 qup_spi5_cs: qup-spi5-cs-state { 3520 pins = "gpio85"; 3521 function = "qup5"; 3522 }; 3523 3524 qup_spi5_data_clk: qup-spi5-data-clk-state { 3525 pins = "gpio206", "gpio207", "gpio84"; 3526 function = "qup5"; 3527 }; 3528 3529 qup_spi6_cs: qup-spi6-cs-state { 3530 pins = "gpio23"; 3531 function = "qup6"; 3532 }; 3533 3534 qup_spi6_data_clk: qup-spi6-data-clk-state { 3535 pins = "gpio20", "gpio21", "gpio22"; 3536 function = "qup6"; 3537 }; 3538 3539 qup_spi8_cs: qup-spi8-cs-state { 3540 pins = "gpio31"; 3541 function = "qup8"; 3542 }; 3543 3544 qup_spi8_data_clk: qup-spi8-data-clk-state { 3545 pins = "gpio28", "gpio29", "gpio30"; 3546 function = "qup8"; 3547 }; 3548 3549 qup_spi9_cs: qup-spi9-cs-state { 3550 pins = "gpio35"; 3551 function = "qup9"; 3552 }; 3553 3554 qup_spi9_data_clk: qup-spi9-data-clk-state { 3555 pins = "gpio32", "gpio33", "gpio34"; 3556 function = "qup9"; 3557 }; 3558 3559 qup_spi10_cs: qup-spi10-cs-state { 3560 pins = "gpio39"; 3561 function = "qup10"; 3562 }; 3563 3564 qup_spi10_data_clk: qup-spi10-data-clk-state { 3565 pins = "gpio36", "gpio37", "gpio38"; 3566 function = "qup10"; 3567 }; 3568 3569 qup_spi11_cs: qup-spi11-cs-state { 3570 pins = "gpio43"; 3571 function = "qup11"; 3572 }; 3573 3574 qup_spi11_data_clk: qup-spi11-data-clk-state { 3575 pins = "gpio40", "gpio41", "gpio42"; 3576 function = "qup11"; 3577 }; 3578 3579 qup_spi12_cs: qup-spi12-cs-state { 3580 pins = "gpio47"; 3581 function = "qup12"; 3582 }; 3583 3584 qup_spi12_data_clk: qup-spi12-data-clk-state { 3585 pins = "gpio44", "gpio45", "gpio46"; 3586 function = "qup12"; 3587 }; 3588 3589 qup_spi13_cs: qup-spi13-cs-state { 3590 pins = "gpio51"; 3591 function = "qup13"; 3592 }; 3593 3594 qup_spi13_data_clk: qup-spi13-data-clk-state { 3595 pins = "gpio48", "gpio49", "gpio50"; 3596 function = "qup13"; 3597 }; 3598 3599 qup_spi14_cs: qup-spi14-cs-state { 3600 pins = "gpio55"; 3601 function = "qup14"; 3602 }; 3603 3604 qup_spi14_data_clk: qup-spi14-data-clk-state { 3605 pins = "gpio52", "gpio53", "gpio54"; 3606 function = "qup14"; 3607 }; 3608 3609 qup_spi15_cs: qup-spi15-cs-state { 3610 pins = "gpio59"; 3611 function = "qup15"; 3612 }; 3613 3614 qup_spi15_data_clk: qup-spi15-data-clk-state { 3615 pins = "gpio56", "gpio57", "gpio58"; 3616 function = "qup15"; 3617 }; 3618 3619 qup_spi16_cs: qup-spi16-cs-state { 3620 pins = "gpio63"; 3621 function = "qup16"; 3622 }; 3623 3624 qup_spi16_data_clk: qup-spi16-data-clk-state { 3625 pins = "gpio60", "gpio61", "gpio62"; 3626 function = "qup16"; 3627 }; 3628 3629 qup_spi17_cs: qup-spi17-cs-state { 3630 pins = "gpio67"; 3631 function = "qup17"; 3632 }; 3633 3634 qup_spi17_data_clk: qup-spi17-data-clk-state { 3635 pins = "gpio64", "gpio65", "gpio66"; 3636 function = "qup17"; 3637 }; 3638 3639 qup_spi18_cs: qup-spi18-cs-state { 3640 pins = "gpio71"; 3641 function = "qup18"; 3642 drive-strength = <6>; 3643 bias-disable; 3644 }; 3645 3646 qup_spi18_data_clk: qup-spi18-data-clk-state { 3647 pins = "gpio68", "gpio69", "gpio70"; 3648 function = "qup18"; 3649 drive-strength = <6>; 3650 bias-disable; 3651 }; 3652 3653 qup_spi19_cs: qup-spi19-cs-state { 3654 pins = "gpio75"; 3655 function = "qup19"; 3656 drive-strength = <6>; 3657 bias-disable; 3658 }; 3659 3660 qup_spi19_data_clk: qup-spi19-data-clk-state { 3661 pins = "gpio72", "gpio73", "gpio74"; 3662 function = "qup19"; 3663 drive-strength = <6>; 3664 bias-disable; 3665 }; 3666 3667 qup_spi20_cs: qup-spi20-cs-state { 3668 pins = "gpio79"; 3669 function = "qup20"; 3670 }; 3671 3672 qup_spi20_data_clk: qup-spi20-data-clk-state { 3673 pins = "gpio76", "gpio77", "gpio78"; 3674 function = "qup20"; 3675 }; 3676 3677 qup_spi21_cs: qup-spi21-cs-state { 3678 pins = "gpio83"; 3679 function = "qup21"; 3680 }; 3681 3682 qup_spi21_data_clk: qup-spi21-data-clk-state { 3683 pins = "gpio80", "gpio81", "gpio82"; 3684 function = "qup21"; 3685 }; 3686 3687 qup_uart7_rx: qup-uart7-rx-state { 3688 pins = "gpio26"; 3689 function = "qup7"; 3690 drive-strength = <2>; 3691 bias-disable; 3692 }; 3693 3694 qup_uart7_tx: qup-uart7-tx-state { 3695 pins = "gpio27"; 3696 function = "qup7"; 3697 drive-strength = <2>; 3698 bias-disable; 3699 }; 3700 3701 qup_uart20_default: qup-uart20-default-state { 3702 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3703 function = "qup20"; 3704 }; 3705 }; 3706 3707 lpass_tlmm: pinctrl@3440000 { 3708 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3709 reg = <0 0x03440000 0x0 0x20000>, 3710 <0 0x034d0000 0x0 0x10000>; 3711 gpio-controller; 3712 #gpio-cells = <2>; 3713 gpio-ranges = <&lpass_tlmm 0 0 23>; 3714 3715 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3716 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3717 clock-names = "core", "audio"; 3718 3719 tx_swr_active: tx-swr-active-state { 3720 clk-pins { 3721 pins = "gpio0"; 3722 function = "swr_tx_clk"; 3723 drive-strength = <2>; 3724 slew-rate = <1>; 3725 bias-disable; 3726 }; 3727 3728 data-pins { 3729 pins = "gpio1", "gpio2", "gpio14"; 3730 function = "swr_tx_data"; 3731 drive-strength = <2>; 3732 slew-rate = <1>; 3733 bias-bus-hold; 3734 }; 3735 }; 3736 3737 rx_swr_active: rx-swr-active-state { 3738 clk-pins { 3739 pins = "gpio3"; 3740 function = "swr_rx_clk"; 3741 drive-strength = <2>; 3742 slew-rate = <1>; 3743 bias-disable; 3744 }; 3745 3746 data-pins { 3747 pins = "gpio4", "gpio5"; 3748 function = "swr_rx_data"; 3749 drive-strength = <2>; 3750 slew-rate = <1>; 3751 bias-bus-hold; 3752 }; 3753 }; 3754 3755 dmic01_default: dmic01-default-state { 3756 clk-pins { 3757 pins = "gpio6"; 3758 function = "dmic1_clk"; 3759 drive-strength = <8>; 3760 output-high; 3761 }; 3762 3763 data-pins { 3764 pins = "gpio7"; 3765 function = "dmic1_data"; 3766 drive-strength = <8>; 3767 }; 3768 }; 3769 3770 dmic02_default: dmic02-default-state { 3771 clk-pins { 3772 pins = "gpio8"; 3773 function = "dmic2_clk"; 3774 drive-strength = <8>; 3775 output-high; 3776 }; 3777 3778 data-pins { 3779 pins = "gpio9"; 3780 function = "dmic2_data"; 3781 drive-strength = <8>; 3782 }; 3783 }; 3784 3785 wsa_swr_active: wsa-swr-active-state { 3786 clk-pins { 3787 pins = "gpio10"; 3788 function = "wsa_swr_clk"; 3789 drive-strength = <2>; 3790 slew-rate = <1>; 3791 bias-disable; 3792 }; 3793 3794 data-pins { 3795 pins = "gpio11"; 3796 function = "wsa_swr_data"; 3797 drive-strength = <2>; 3798 slew-rate = <1>; 3799 bias-bus-hold; 3800 }; 3801 }; 3802 3803 wsa2_swr_active: wsa2-swr-active-state { 3804 clk-pins { 3805 pins = "gpio15"; 3806 function = "wsa2_swr_clk"; 3807 drive-strength = <2>; 3808 slew-rate = <1>; 3809 bias-disable; 3810 }; 3811 3812 data-pins { 3813 pins = "gpio16"; 3814 function = "wsa2_swr_data"; 3815 drive-strength = <2>; 3816 slew-rate = <1>; 3817 bias-bus-hold; 3818 }; 3819 }; 3820 }; 3821 3822 sram@146aa000 { 3823 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3824 reg = <0 0x146aa000 0 0x1000>; 3825 ranges = <0 0 0x146aa000 0x1000>; 3826 3827 #address-cells = <1>; 3828 #size-cells = <1>; 3829 3830 pil-reloc@94c { 3831 compatible = "qcom,pil-reloc-info"; 3832 reg = <0x94c 0xc8>; 3833 }; 3834 }; 3835 3836 apps_smmu: iommu@15000000 { 3837 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3838 reg = <0 0x15000000 0 0x100000>; 3839 #iommu-cells = <2>; 3840 #global-interrupts = <1>; 3841 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3938 }; 3939 3940 intc: interrupt-controller@17100000 { 3941 compatible = "arm,gic-v3"; 3942 #interrupt-cells = <3>; 3943 interrupt-controller; 3944 #redistributor-regions = <1>; 3945 redistributor-stride = <0x0 0x40000>; 3946 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3947 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3948 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3949 #address-cells = <2>; 3950 #size-cells = <2>; 3951 ranges; 3952 3953 gic_its: msi-controller@17140000 { 3954 compatible = "arm,gic-v3-its"; 3955 reg = <0x0 0x17140000 0x0 0x20000>; 3956 msi-controller; 3957 #msi-cells = <1>; 3958 }; 3959 }; 3960 3961 timer@17420000 { 3962 compatible = "arm,armv7-timer-mem"; 3963 #address-cells = <1>; 3964 #size-cells = <1>; 3965 ranges = <0 0 0 0x20000000>; 3966 reg = <0x0 0x17420000 0x0 0x1000>; 3967 clock-frequency = <19200000>; 3968 3969 frame@17421000 { 3970 frame-number = <0>; 3971 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3973 reg = <0x17421000 0x1000>, 3974 <0x17422000 0x1000>; 3975 }; 3976 3977 frame@17423000 { 3978 frame-number = <1>; 3979 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3980 reg = <0x17423000 0x1000>; 3981 status = "disabled"; 3982 }; 3983 3984 frame@17425000 { 3985 frame-number = <2>; 3986 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3987 reg = <0x17425000 0x1000>; 3988 status = "disabled"; 3989 }; 3990 3991 frame@17427000 { 3992 frame-number = <3>; 3993 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3994 reg = <0x17427000 0x1000>; 3995 status = "disabled"; 3996 }; 3997 3998 frame@17429000 { 3999 frame-number = <4>; 4000 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4001 reg = <0x17429000 0x1000>; 4002 status = "disabled"; 4003 }; 4004 4005 frame@1742b000 { 4006 frame-number = <5>; 4007 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4008 reg = <0x1742b000 0x1000>; 4009 status = "disabled"; 4010 }; 4011 4012 frame@1742d000 { 4013 frame-number = <6>; 4014 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4015 reg = <0x1742d000 0x1000>; 4016 status = "disabled"; 4017 }; 4018 }; 4019 4020 apps_rsc: rsc@17a00000 { 4021 label = "apps_rsc"; 4022 compatible = "qcom,rpmh-rsc"; 4023 reg = <0x0 0x17a00000 0x0 0x10000>, 4024 <0x0 0x17a10000 0x0 0x10000>, 4025 <0x0 0x17a20000 0x0 0x10000>, 4026 <0x0 0x17a30000 0x0 0x10000>; 4027 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4028 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4031 qcom,tcs-offset = <0xd00>; 4032 qcom,drv-id = <2>; 4033 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4034 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4035 power-domains = <&CLUSTER_PD>; 4036 4037 apps_bcm_voter: bcm-voter { 4038 compatible = "qcom,bcm-voter"; 4039 }; 4040 4041 rpmhcc: clock-controller { 4042 compatible = "qcom,sm8450-rpmh-clk"; 4043 #clock-cells = <1>; 4044 clock-names = "xo"; 4045 clocks = <&xo_board>; 4046 }; 4047 4048 rpmhpd: power-controller { 4049 compatible = "qcom,sm8450-rpmhpd"; 4050 #power-domain-cells = <1>; 4051 operating-points-v2 = <&rpmhpd_opp_table>; 4052 4053 rpmhpd_opp_table: opp-table { 4054 compatible = "operating-points-v2"; 4055 4056 rpmhpd_opp_ret: opp1 { 4057 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4058 }; 4059 4060 rpmhpd_opp_min_svs: opp2 { 4061 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4062 }; 4063 4064 rpmhpd_opp_low_svs_d1: opp3 { 4065 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4066 }; 4067 4068 rpmhpd_opp_low_svs: opp4 { 4069 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4070 }; 4071 4072 rpmhpd_opp_low_svs_l1: opp5 { 4073 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4074 }; 4075 4076 rpmhpd_opp_svs: opp6 { 4077 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4078 }; 4079 4080 rpmhpd_opp_svs_l0: opp7 { 4081 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4082 }; 4083 4084 rpmhpd_opp_svs_l1: opp8 { 4085 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4086 }; 4087 4088 rpmhpd_opp_svs_l2: opp9 { 4089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4090 }; 4091 4092 rpmhpd_opp_nom: opp10 { 4093 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4094 }; 4095 4096 rpmhpd_opp_nom_l1: opp11 { 4097 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4098 }; 4099 4100 rpmhpd_opp_nom_l2: opp12 { 4101 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4102 }; 4103 4104 rpmhpd_opp_turbo: opp13 { 4105 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4106 }; 4107 4108 rpmhpd_opp_turbo_l1: opp14 { 4109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4110 }; 4111 }; 4112 }; 4113 }; 4114 4115 cpufreq_hw: cpufreq@17d91000 { 4116 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4117 reg = <0 0x17d91000 0 0x1000>, 4118 <0 0x17d92000 0 0x1000>, 4119 <0 0x17d93000 0 0x1000>; 4120 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4121 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4122 clock-names = "xo", "alternate"; 4123 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4126 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4127 #freq-domain-cells = <1>; 4128 #clock-cells = <1>; 4129 }; 4130 4131 gem_noc: interconnect@19100000 { 4132 compatible = "qcom,sm8450-gem-noc"; 4133 reg = <0 0x19100000 0 0xbb800>; 4134 #interconnect-cells = <2>; 4135 qcom,bcm-voters = <&apps_bcm_voter>; 4136 }; 4137 4138 system-cache-controller@19200000 { 4139 compatible = "qcom,sm8450-llcc"; 4140 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4141 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4142 <0 0x19a00000 0 0x80000>; 4143 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4144 "llcc3_base", "llcc_broadcast_base"; 4145 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4146 }; 4147 4148 ufs_mem_hc: ufshc@1d84000 { 4149 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4150 "jedec,ufs-2.0"; 4151 reg = <0 0x01d84000 0 0x3000>; 4152 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4153 phys = <&ufs_mem_phy_lanes>; 4154 phy-names = "ufsphy"; 4155 lanes-per-direction = <2>; 4156 #reset-cells = <1>; 4157 resets = <&gcc GCC_UFS_PHY_BCR>; 4158 reset-names = "rst"; 4159 4160 power-domains = <&gcc UFS_PHY_GDSC>; 4161 4162 iommus = <&apps_smmu 0xe0 0x0>; 4163 dma-coherent; 4164 4165 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4166 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4167 interconnect-names = "ufs-ddr", "cpu-ufs"; 4168 clock-names = 4169 "core_clk", 4170 "bus_aggr_clk", 4171 "iface_clk", 4172 "core_clk_unipro", 4173 "ref_clk", 4174 "tx_lane0_sync_clk", 4175 "rx_lane0_sync_clk", 4176 "rx_lane1_sync_clk"; 4177 clocks = 4178 <&gcc GCC_UFS_PHY_AXI_CLK>, 4179 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4180 <&gcc GCC_UFS_PHY_AHB_CLK>, 4181 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4182 <&rpmhcc RPMH_CXO_CLK>, 4183 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4184 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4185 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4186 freq-table-hz = 4187 <75000000 300000000>, 4188 <0 0>, 4189 <0 0>, 4190 <75000000 300000000>, 4191 <75000000 300000000>, 4192 <0 0>, 4193 <0 0>, 4194 <0 0>; 4195 qcom,ice = <&ice>; 4196 4197 status = "disabled"; 4198 }; 4199 4200 ufs_mem_phy: phy@1d87000 { 4201 compatible = "qcom,sm8450-qmp-ufs-phy"; 4202 reg = <0 0x01d87000 0 0x1c4>; 4203 #address-cells = <2>; 4204 #size-cells = <2>; 4205 ranges; 4206 clock-names = "ref", "ref_aux", "qref"; 4207 clocks = <&rpmhcc RPMH_CXO_CLK>, 4208 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4209 <&gcc GCC_UFS_0_CLKREF_EN>; 4210 4211 resets = <&ufs_mem_hc 0>; 4212 reset-names = "ufsphy"; 4213 status = "disabled"; 4214 4215 ufs_mem_phy_lanes: phy@1d87400 { 4216 reg = <0 0x01d87400 0 0x188>, 4217 <0 0x01d87600 0 0x200>, 4218 <0 0x01d87c00 0 0x200>, 4219 <0 0x01d87800 0 0x188>, 4220 <0 0x01d87a00 0 0x200>; 4221 #clock-cells = <1>; 4222 #phy-cells = <0>; 4223 }; 4224 }; 4225 4226 ice: crypto@1d88000 { 4227 compatible = "qcom,sm8450-inline-crypto-engine", 4228 "qcom,inline-crypto-engine"; 4229 reg = <0 0x01d88000 0 0x8000>; 4230 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4231 }; 4232 4233 cryptobam: dma-controller@1dc4000 { 4234 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4235 reg = <0 0x01dc4000 0 0x28000>; 4236 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4237 #dma-cells = <1>; 4238 qcom,ee = <0>; 4239 qcom,controlled-remotely; 4240 iommus = <&apps_smmu 0x584 0x11>, 4241 <&apps_smmu 0x588 0x0>, 4242 <&apps_smmu 0x598 0x5>, 4243 <&apps_smmu 0x59a 0x0>, 4244 <&apps_smmu 0x59f 0x0>; 4245 }; 4246 4247 crypto: crypto@1dfa000 { 4248 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4249 reg = <0 0x01dfa000 0 0x6000>; 4250 dmas = <&cryptobam 4>, <&cryptobam 5>; 4251 dma-names = "rx", "tx"; 4252 iommus = <&apps_smmu 0x584 0x11>, 4253 <&apps_smmu 0x588 0x0>, 4254 <&apps_smmu 0x598 0x5>, 4255 <&apps_smmu 0x59a 0x0>, 4256 <&apps_smmu 0x59f 0x0>; 4257 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4258 interconnect-names = "memory"; 4259 }; 4260 4261 sdhc_2: mmc@8804000 { 4262 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4263 reg = <0 0x08804000 0 0x1000>; 4264 4265 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4267 interrupt-names = "hc_irq", "pwr_irq"; 4268 4269 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4270 <&gcc GCC_SDCC2_APPS_CLK>, 4271 <&rpmhcc RPMH_CXO_CLK>; 4272 clock-names = "iface", "core", "xo"; 4273 resets = <&gcc GCC_SDCC2_BCR>; 4274 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4275 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4276 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4277 iommus = <&apps_smmu 0x4a0 0x0>; 4278 power-domains = <&rpmhpd RPMHPD_CX>; 4279 operating-points-v2 = <&sdhc2_opp_table>; 4280 bus-width = <4>; 4281 dma-coherent; 4282 4283 /* Forbid SDR104/SDR50 - broken hw! */ 4284 sdhci-caps-mask = <0x3 0x0>; 4285 4286 status = "disabled"; 4287 4288 sdhc2_opp_table: opp-table { 4289 compatible = "operating-points-v2"; 4290 4291 opp-100000000 { 4292 opp-hz = /bits/ 64 <100000000>; 4293 required-opps = <&rpmhpd_opp_low_svs>; 4294 }; 4295 4296 opp-202000000 { 4297 opp-hz = /bits/ 64 <202000000>; 4298 required-opps = <&rpmhpd_opp_svs_l1>; 4299 }; 4300 }; 4301 }; 4302 4303 usb_1: usb@a6f8800 { 4304 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4305 reg = <0 0x0a6f8800 0 0x400>; 4306 status = "disabled"; 4307 #address-cells = <2>; 4308 #size-cells = <2>; 4309 ranges; 4310 4311 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4312 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4313 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4314 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4315 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4316 <&gcc GCC_USB3_0_CLKREF_EN>; 4317 clock-names = "cfg_noc", 4318 "core", 4319 "iface", 4320 "sleep", 4321 "mock_utmi", 4322 "xo"; 4323 4324 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4325 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4326 assigned-clock-rates = <19200000>, <200000000>; 4327 4328 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4329 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4330 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4331 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4332 interrupt-names = "hs_phy_irq", 4333 "ss_phy_irq", 4334 "dm_hs_phy_irq", 4335 "dp_hs_phy_irq"; 4336 4337 power-domains = <&gcc USB30_PRIM_GDSC>; 4338 4339 resets = <&gcc GCC_USB30_PRIM_BCR>; 4340 4341 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4343 interconnect-names = "usb-ddr", "apps-usb"; 4344 4345 usb_1_dwc3: usb@a600000 { 4346 compatible = "snps,dwc3"; 4347 reg = <0 0x0a600000 0 0xcd00>; 4348 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4349 iommus = <&apps_smmu 0x0 0x0>; 4350 snps,dis_u2_susphy_quirk; 4351 snps,dis_enblslpm_quirk; 4352 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4353 phy-names = "usb2-phy", "usb3-phy"; 4354 4355 ports { 4356 #address-cells = <1>; 4357 #size-cells = <0>; 4358 4359 port@0 { 4360 reg = <0>; 4361 4362 usb_1_dwc3_hs: endpoint { 4363 }; 4364 }; 4365 4366 port@1 { 4367 reg = <1>; 4368 4369 usb_1_dwc3_ss: endpoint { 4370 }; 4371 }; 4372 }; 4373 }; 4374 }; 4375 4376 nsp_noc: interconnect@320c0000 { 4377 compatible = "qcom,sm8450-nsp-noc"; 4378 reg = <0 0x320c0000 0 0x10000>; 4379 #interconnect-cells = <2>; 4380 qcom,bcm-voters = <&apps_bcm_voter>; 4381 }; 4382 4383 lpass_ag_noc: interconnect@3c40000 { 4384 compatible = "qcom,sm8450-lpass-ag-noc"; 4385 reg = <0 0x03c40000 0 0x17200>; 4386 #interconnect-cells = <2>; 4387 qcom,bcm-voters = <&apps_bcm_voter>; 4388 }; 4389 }; 4390 4391 sound: sound { 4392 }; 4393 4394 thermal-zones { 4395 aoss0-thermal { 4396 polling-delay-passive = <0>; 4397 polling-delay = <0>; 4398 thermal-sensors = <&tsens0 0>; 4399 4400 trips { 4401 thermal-engine-config { 4402 temperature = <125000>; 4403 hysteresis = <1000>; 4404 type = "passive"; 4405 }; 4406 4407 reset-mon-cfg { 4408 temperature = <115000>; 4409 hysteresis = <5000>; 4410 type = "passive"; 4411 }; 4412 }; 4413 }; 4414 4415 cpuss0-thermal { 4416 polling-delay-passive = <0>; 4417 polling-delay = <0>; 4418 thermal-sensors = <&tsens0 1>; 4419 4420 trips { 4421 thermal-engine-config { 4422 temperature = <125000>; 4423 hysteresis = <1000>; 4424 type = "passive"; 4425 }; 4426 4427 reset-mon-cfg { 4428 temperature = <115000>; 4429 hysteresis = <5000>; 4430 type = "passive"; 4431 }; 4432 }; 4433 }; 4434 4435 cpuss1-thermal { 4436 polling-delay-passive = <0>; 4437 polling-delay = <0>; 4438 thermal-sensors = <&tsens0 2>; 4439 4440 trips { 4441 thermal-engine-config { 4442 temperature = <125000>; 4443 hysteresis = <1000>; 4444 type = "passive"; 4445 }; 4446 4447 reset-mon-cfg { 4448 temperature = <115000>; 4449 hysteresis = <5000>; 4450 type = "passive"; 4451 }; 4452 }; 4453 }; 4454 4455 cpuss3-thermal { 4456 polling-delay-passive = <0>; 4457 polling-delay = <0>; 4458 thermal-sensors = <&tsens0 3>; 4459 4460 trips { 4461 thermal-engine-config { 4462 temperature = <125000>; 4463 hysteresis = <1000>; 4464 type = "passive"; 4465 }; 4466 4467 reset-mon-cfg { 4468 temperature = <115000>; 4469 hysteresis = <5000>; 4470 type = "passive"; 4471 }; 4472 }; 4473 }; 4474 4475 cpuss4-thermal { 4476 polling-delay-passive = <0>; 4477 polling-delay = <0>; 4478 thermal-sensors = <&tsens0 4>; 4479 4480 trips { 4481 thermal-engine-config { 4482 temperature = <125000>; 4483 hysteresis = <1000>; 4484 type = "passive"; 4485 }; 4486 4487 reset-mon-cfg { 4488 temperature = <115000>; 4489 hysteresis = <5000>; 4490 type = "passive"; 4491 }; 4492 }; 4493 }; 4494 4495 cpu4-top-thermal { 4496 polling-delay-passive = <0>; 4497 polling-delay = <0>; 4498 thermal-sensors = <&tsens0 5>; 4499 4500 trips { 4501 cpu4_top_alert0: trip-point0 { 4502 temperature = <90000>; 4503 hysteresis = <2000>; 4504 type = "passive"; 4505 }; 4506 4507 cpu4_top_alert1: trip-point1 { 4508 temperature = <95000>; 4509 hysteresis = <2000>; 4510 type = "passive"; 4511 }; 4512 4513 cpu4_top_crit: cpu-crit { 4514 temperature = <110000>; 4515 hysteresis = <1000>; 4516 type = "critical"; 4517 }; 4518 }; 4519 }; 4520 4521 cpu4-bottom-thermal { 4522 polling-delay-passive = <0>; 4523 polling-delay = <0>; 4524 thermal-sensors = <&tsens0 6>; 4525 4526 trips { 4527 cpu4_bottom_alert0: trip-point0 { 4528 temperature = <90000>; 4529 hysteresis = <2000>; 4530 type = "passive"; 4531 }; 4532 4533 cpu4_bottom_alert1: trip-point1 { 4534 temperature = <95000>; 4535 hysteresis = <2000>; 4536 type = "passive"; 4537 }; 4538 4539 cpu4_bottom_crit: cpu-crit { 4540 temperature = <110000>; 4541 hysteresis = <1000>; 4542 type = "critical"; 4543 }; 4544 }; 4545 }; 4546 4547 cpu5-top-thermal { 4548 polling-delay-passive = <0>; 4549 polling-delay = <0>; 4550 thermal-sensors = <&tsens0 7>; 4551 4552 trips { 4553 cpu5_top_alert0: trip-point0 { 4554 temperature = <90000>; 4555 hysteresis = <2000>; 4556 type = "passive"; 4557 }; 4558 4559 cpu5_top_alert1: trip-point1 { 4560 temperature = <95000>; 4561 hysteresis = <2000>; 4562 type = "passive"; 4563 }; 4564 4565 cpu5_top_crit: cpu-crit { 4566 temperature = <110000>; 4567 hysteresis = <1000>; 4568 type = "critical"; 4569 }; 4570 }; 4571 }; 4572 4573 cpu5-bottom-thermal { 4574 polling-delay-passive = <0>; 4575 polling-delay = <0>; 4576 thermal-sensors = <&tsens0 8>; 4577 4578 trips { 4579 cpu5_bottom_alert0: trip-point0 { 4580 temperature = <90000>; 4581 hysteresis = <2000>; 4582 type = "passive"; 4583 }; 4584 4585 cpu5_bottom_alert1: trip-point1 { 4586 temperature = <95000>; 4587 hysteresis = <2000>; 4588 type = "passive"; 4589 }; 4590 4591 cpu5_bottom_crit: cpu-crit { 4592 temperature = <110000>; 4593 hysteresis = <1000>; 4594 type = "critical"; 4595 }; 4596 }; 4597 }; 4598 4599 cpu6-top-thermal { 4600 polling-delay-passive = <0>; 4601 polling-delay = <0>; 4602 thermal-sensors = <&tsens0 9>; 4603 4604 trips { 4605 cpu6_top_alert0: trip-point0 { 4606 temperature = <90000>; 4607 hysteresis = <2000>; 4608 type = "passive"; 4609 }; 4610 4611 cpu6_top_alert1: trip-point1 { 4612 temperature = <95000>; 4613 hysteresis = <2000>; 4614 type = "passive"; 4615 }; 4616 4617 cpu6_top_crit: cpu-crit { 4618 temperature = <110000>; 4619 hysteresis = <1000>; 4620 type = "critical"; 4621 }; 4622 }; 4623 }; 4624 4625 cpu6-bottom-thermal { 4626 polling-delay-passive = <0>; 4627 polling-delay = <0>; 4628 thermal-sensors = <&tsens0 10>; 4629 4630 trips { 4631 cpu6_bottom_alert0: trip-point0 { 4632 temperature = <90000>; 4633 hysteresis = <2000>; 4634 type = "passive"; 4635 }; 4636 4637 cpu6_bottom_alert1: trip-point1 { 4638 temperature = <95000>; 4639 hysteresis = <2000>; 4640 type = "passive"; 4641 }; 4642 4643 cpu6_bottom_crit: cpu-crit { 4644 temperature = <110000>; 4645 hysteresis = <1000>; 4646 type = "critical"; 4647 }; 4648 }; 4649 }; 4650 4651 cpu7-top-thermal { 4652 polling-delay-passive = <0>; 4653 polling-delay = <0>; 4654 thermal-sensors = <&tsens0 11>; 4655 4656 trips { 4657 cpu7_top_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu7_top_alert1: trip-point1 { 4664 temperature = <95000>; 4665 hysteresis = <2000>; 4666 type = "passive"; 4667 }; 4668 4669 cpu7_top_crit: cpu-crit { 4670 temperature = <110000>; 4671 hysteresis = <1000>; 4672 type = "critical"; 4673 }; 4674 }; 4675 }; 4676 4677 cpu7-middle-thermal { 4678 polling-delay-passive = <0>; 4679 polling-delay = <0>; 4680 thermal-sensors = <&tsens0 12>; 4681 4682 trips { 4683 cpu7_middle_alert0: trip-point0 { 4684 temperature = <90000>; 4685 hysteresis = <2000>; 4686 type = "passive"; 4687 }; 4688 4689 cpu7_middle_alert1: trip-point1 { 4690 temperature = <95000>; 4691 hysteresis = <2000>; 4692 type = "passive"; 4693 }; 4694 4695 cpu7_middle_crit: cpu-crit { 4696 temperature = <110000>; 4697 hysteresis = <1000>; 4698 type = "critical"; 4699 }; 4700 }; 4701 }; 4702 4703 cpu7-bottom-thermal { 4704 polling-delay-passive = <0>; 4705 polling-delay = <0>; 4706 thermal-sensors = <&tsens0 13>; 4707 4708 trips { 4709 cpu7_bottom_alert0: trip-point0 { 4710 temperature = <90000>; 4711 hysteresis = <2000>; 4712 type = "passive"; 4713 }; 4714 4715 cpu7_bottom_alert1: trip-point1 { 4716 temperature = <95000>; 4717 hysteresis = <2000>; 4718 type = "passive"; 4719 }; 4720 4721 cpu7_bottom_crit: cpu-crit { 4722 temperature = <110000>; 4723 hysteresis = <1000>; 4724 type = "critical"; 4725 }; 4726 }; 4727 }; 4728 4729 gpu-top-thermal { 4730 polling-delay-passive = <10>; 4731 polling-delay = <0>; 4732 thermal-sensors = <&tsens0 14>; 4733 4734 trips { 4735 thermal-engine-config { 4736 temperature = <125000>; 4737 hysteresis = <1000>; 4738 type = "passive"; 4739 }; 4740 4741 thermal-hal-config { 4742 temperature = <125000>; 4743 hysteresis = <1000>; 4744 type = "passive"; 4745 }; 4746 4747 reset-mon-cfg { 4748 temperature = <115000>; 4749 hysteresis = <5000>; 4750 type = "passive"; 4751 }; 4752 4753 gpu0_tj_cfg: tj-cfg { 4754 temperature = <95000>; 4755 hysteresis = <5000>; 4756 type = "passive"; 4757 }; 4758 }; 4759 }; 4760 4761 gpu-bottom-thermal { 4762 polling-delay-passive = <10>; 4763 polling-delay = <0>; 4764 thermal-sensors = <&tsens0 15>; 4765 4766 trips { 4767 thermal-engine-config { 4768 temperature = <125000>; 4769 hysteresis = <1000>; 4770 type = "passive"; 4771 }; 4772 4773 thermal-hal-config { 4774 temperature = <125000>; 4775 hysteresis = <1000>; 4776 type = "passive"; 4777 }; 4778 4779 reset-mon-cfg { 4780 temperature = <115000>; 4781 hysteresis = <5000>; 4782 type = "passive"; 4783 }; 4784 4785 gpu1_tj_cfg: tj-cfg { 4786 temperature = <95000>; 4787 hysteresis = <5000>; 4788 type = "passive"; 4789 }; 4790 }; 4791 }; 4792 4793 aoss1-thermal { 4794 polling-delay-passive = <0>; 4795 polling-delay = <0>; 4796 thermal-sensors = <&tsens1 0>; 4797 4798 trips { 4799 thermal-engine-config { 4800 temperature = <125000>; 4801 hysteresis = <1000>; 4802 type = "passive"; 4803 }; 4804 4805 reset-mon-cfg { 4806 temperature = <115000>; 4807 hysteresis = <5000>; 4808 type = "passive"; 4809 }; 4810 }; 4811 }; 4812 4813 cpu0-thermal { 4814 polling-delay-passive = <0>; 4815 polling-delay = <0>; 4816 thermal-sensors = <&tsens1 1>; 4817 4818 trips { 4819 cpu0_alert0: trip-point0 { 4820 temperature = <90000>; 4821 hysteresis = <2000>; 4822 type = "passive"; 4823 }; 4824 4825 cpu0_alert1: trip-point1 { 4826 temperature = <95000>; 4827 hysteresis = <2000>; 4828 type = "passive"; 4829 }; 4830 4831 cpu0_crit: cpu-crit { 4832 temperature = <110000>; 4833 hysteresis = <1000>; 4834 type = "critical"; 4835 }; 4836 }; 4837 }; 4838 4839 cpu1-thermal { 4840 polling-delay-passive = <0>; 4841 polling-delay = <0>; 4842 thermal-sensors = <&tsens1 2>; 4843 4844 trips { 4845 cpu1_alert0: trip-point0 { 4846 temperature = <90000>; 4847 hysteresis = <2000>; 4848 type = "passive"; 4849 }; 4850 4851 cpu1_alert1: trip-point1 { 4852 temperature = <95000>; 4853 hysteresis = <2000>; 4854 type = "passive"; 4855 }; 4856 4857 cpu1_crit: cpu-crit { 4858 temperature = <110000>; 4859 hysteresis = <1000>; 4860 type = "critical"; 4861 }; 4862 }; 4863 }; 4864 4865 cpu2-thermal { 4866 polling-delay-passive = <0>; 4867 polling-delay = <0>; 4868 thermal-sensors = <&tsens1 3>; 4869 4870 trips { 4871 cpu2_alert0: trip-point0 { 4872 temperature = <90000>; 4873 hysteresis = <2000>; 4874 type = "passive"; 4875 }; 4876 4877 cpu2_alert1: trip-point1 { 4878 temperature = <95000>; 4879 hysteresis = <2000>; 4880 type = "passive"; 4881 }; 4882 4883 cpu2_crit: cpu-crit { 4884 temperature = <110000>; 4885 hysteresis = <1000>; 4886 type = "critical"; 4887 }; 4888 }; 4889 }; 4890 4891 cpu3-thermal { 4892 polling-delay-passive = <0>; 4893 polling-delay = <0>; 4894 thermal-sensors = <&tsens1 4>; 4895 4896 trips { 4897 cpu3_alert0: trip-point0 { 4898 temperature = <90000>; 4899 hysteresis = <2000>; 4900 type = "passive"; 4901 }; 4902 4903 cpu3_alert1: trip-point1 { 4904 temperature = <95000>; 4905 hysteresis = <2000>; 4906 type = "passive"; 4907 }; 4908 4909 cpu3_crit: cpu-crit { 4910 temperature = <110000>; 4911 hysteresis = <1000>; 4912 type = "critical"; 4913 }; 4914 }; 4915 }; 4916 4917 cdsp0-thermal { 4918 polling-delay-passive = <10>; 4919 polling-delay = <0>; 4920 thermal-sensors = <&tsens1 5>; 4921 4922 trips { 4923 thermal-engine-config { 4924 temperature = <125000>; 4925 hysteresis = <1000>; 4926 type = "passive"; 4927 }; 4928 4929 thermal-hal-config { 4930 temperature = <125000>; 4931 hysteresis = <1000>; 4932 type = "passive"; 4933 }; 4934 4935 reset-mon-cfg { 4936 temperature = <115000>; 4937 hysteresis = <5000>; 4938 type = "passive"; 4939 }; 4940 4941 cdsp_0_config: junction-config { 4942 temperature = <95000>; 4943 hysteresis = <5000>; 4944 type = "passive"; 4945 }; 4946 }; 4947 }; 4948 4949 cdsp1-thermal { 4950 polling-delay-passive = <10>; 4951 polling-delay = <0>; 4952 thermal-sensors = <&tsens1 6>; 4953 4954 trips { 4955 thermal-engine-config { 4956 temperature = <125000>; 4957 hysteresis = <1000>; 4958 type = "passive"; 4959 }; 4960 4961 thermal-hal-config { 4962 temperature = <125000>; 4963 hysteresis = <1000>; 4964 type = "passive"; 4965 }; 4966 4967 reset-mon-cfg { 4968 temperature = <115000>; 4969 hysteresis = <5000>; 4970 type = "passive"; 4971 }; 4972 4973 cdsp_1_config: junction-config { 4974 temperature = <95000>; 4975 hysteresis = <5000>; 4976 type = "passive"; 4977 }; 4978 }; 4979 }; 4980 4981 cdsp2-thermal { 4982 polling-delay-passive = <10>; 4983 polling-delay = <0>; 4984 thermal-sensors = <&tsens1 7>; 4985 4986 trips { 4987 thermal-engine-config { 4988 temperature = <125000>; 4989 hysteresis = <1000>; 4990 type = "passive"; 4991 }; 4992 4993 thermal-hal-config { 4994 temperature = <125000>; 4995 hysteresis = <1000>; 4996 type = "passive"; 4997 }; 4998 4999 reset-mon-cfg { 5000 temperature = <115000>; 5001 hysteresis = <5000>; 5002 type = "passive"; 5003 }; 5004 5005 cdsp_2_config: junction-config { 5006 temperature = <95000>; 5007 hysteresis = <5000>; 5008 type = "passive"; 5009 }; 5010 }; 5011 }; 5012 5013 video-thermal { 5014 polling-delay-passive = <0>; 5015 polling-delay = <0>; 5016 thermal-sensors = <&tsens1 8>; 5017 5018 trips { 5019 thermal-engine-config { 5020 temperature = <125000>; 5021 hysteresis = <1000>; 5022 type = "passive"; 5023 }; 5024 5025 reset-mon-cfg { 5026 temperature = <115000>; 5027 hysteresis = <5000>; 5028 type = "passive"; 5029 }; 5030 }; 5031 }; 5032 5033 mem-thermal { 5034 polling-delay-passive = <10>; 5035 polling-delay = <0>; 5036 thermal-sensors = <&tsens1 9>; 5037 5038 trips { 5039 thermal-engine-config { 5040 temperature = <125000>; 5041 hysteresis = <1000>; 5042 type = "passive"; 5043 }; 5044 5045 ddr_config0: ddr0-config { 5046 temperature = <90000>; 5047 hysteresis = <5000>; 5048 type = "passive"; 5049 }; 5050 5051 reset-mon-cfg { 5052 temperature = <115000>; 5053 hysteresis = <5000>; 5054 type = "passive"; 5055 }; 5056 }; 5057 }; 5058 5059 modem0-thermal { 5060 polling-delay-passive = <0>; 5061 polling-delay = <0>; 5062 thermal-sensors = <&tsens1 10>; 5063 5064 trips { 5065 thermal-engine-config { 5066 temperature = <125000>; 5067 hysteresis = <1000>; 5068 type = "passive"; 5069 }; 5070 5071 mdmss0_config0: mdmss0-config0 { 5072 temperature = <102000>; 5073 hysteresis = <3000>; 5074 type = "passive"; 5075 }; 5076 5077 mdmss0_config1: mdmss0-config1 { 5078 temperature = <105000>; 5079 hysteresis = <3000>; 5080 type = "passive"; 5081 }; 5082 5083 reset-mon-cfg { 5084 temperature = <115000>; 5085 hysteresis = <5000>; 5086 type = "passive"; 5087 }; 5088 }; 5089 }; 5090 5091 modem1-thermal { 5092 polling-delay-passive = <0>; 5093 polling-delay = <0>; 5094 thermal-sensors = <&tsens1 11>; 5095 5096 trips { 5097 thermal-engine-config { 5098 temperature = <125000>; 5099 hysteresis = <1000>; 5100 type = "passive"; 5101 }; 5102 5103 mdmss1_config0: mdmss1-config0 { 5104 temperature = <102000>; 5105 hysteresis = <3000>; 5106 type = "passive"; 5107 }; 5108 5109 mdmss1_config1: mdmss1-config1 { 5110 temperature = <105000>; 5111 hysteresis = <3000>; 5112 type = "passive"; 5113 }; 5114 5115 reset-mon-cfg { 5116 temperature = <115000>; 5117 hysteresis = <5000>; 5118 type = "passive"; 5119 }; 5120 }; 5121 }; 5122 5123 modem2-thermal { 5124 polling-delay-passive = <0>; 5125 polling-delay = <0>; 5126 thermal-sensors = <&tsens1 12>; 5127 5128 trips { 5129 thermal-engine-config { 5130 temperature = <125000>; 5131 hysteresis = <1000>; 5132 type = "passive"; 5133 }; 5134 5135 mdmss2_config0: mdmss2-config0 { 5136 temperature = <102000>; 5137 hysteresis = <3000>; 5138 type = "passive"; 5139 }; 5140 5141 mdmss2_config1: mdmss2-config1 { 5142 temperature = <105000>; 5143 hysteresis = <3000>; 5144 type = "passive"; 5145 }; 5146 5147 reset-mon-cfg { 5148 temperature = <115000>; 5149 hysteresis = <5000>; 5150 type = "passive"; 5151 }; 5152 }; 5153 }; 5154 5155 modem3-thermal { 5156 polling-delay-passive = <0>; 5157 polling-delay = <0>; 5158 thermal-sensors = <&tsens1 13>; 5159 5160 trips { 5161 thermal-engine-config { 5162 temperature = <125000>; 5163 hysteresis = <1000>; 5164 type = "passive"; 5165 }; 5166 5167 mdmss3_config0: mdmss3-config0 { 5168 temperature = <102000>; 5169 hysteresis = <3000>; 5170 type = "passive"; 5171 }; 5172 5173 mdmss3_config1: mdmss3-config1 { 5174 temperature = <105000>; 5175 hysteresis = <3000>; 5176 type = "passive"; 5177 }; 5178 5179 reset-mon-cfg { 5180 temperature = <115000>; 5181 hysteresis = <5000>; 5182 type = "passive"; 5183 }; 5184 }; 5185 }; 5186 5187 camera0-thermal { 5188 polling-delay-passive = <0>; 5189 polling-delay = <0>; 5190 thermal-sensors = <&tsens1 14>; 5191 5192 trips { 5193 thermal-engine-config { 5194 temperature = <125000>; 5195 hysteresis = <1000>; 5196 type = "passive"; 5197 }; 5198 5199 reset-mon-cfg { 5200 temperature = <115000>; 5201 hysteresis = <5000>; 5202 type = "passive"; 5203 }; 5204 }; 5205 }; 5206 5207 camera1-thermal { 5208 polling-delay-passive = <0>; 5209 polling-delay = <0>; 5210 thermal-sensors = <&tsens1 15>; 5211 5212 trips { 5213 thermal-engine-config { 5214 temperature = <125000>; 5215 hysteresis = <1000>; 5216 type = "passive"; 5217 }; 5218 5219 reset-mon-cfg { 5220 temperature = <115000>; 5221 hysteresis = <5000>; 5222 type = "passive"; 5223 }; 5224 }; 5225 }; 5226 }; 5227 5228 timer { 5229 compatible = "arm,armv8-timer"; 5230 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5231 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5232 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5233 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5234 clock-frequency = <19200000>; 5235 }; 5236}; 5237