1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/interconnect/qcom,sm8450.h> 13#include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <76800000>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <32000>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo780"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 next-level-cache = <&L2_0>; 47 power-domains = <&CPU_PD0>; 48 power-domain-names = "psci"; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 L2_0: l2-cache { 51 compatible = "cache"; 52 next-level-cache = <&L3_0>; 53 L3_0: l3-cache { 54 compatible = "cache"; 55 }; 56 }; 57 }; 58 59 CPU1: cpu@100 { 60 device_type = "cpu"; 61 compatible = "qcom,kryo780"; 62 reg = <0x0 0x100>; 63 enable-method = "psci"; 64 next-level-cache = <&L2_100>; 65 power-domains = <&CPU_PD1>; 66 power-domain-names = "psci"; 67 qcom,freq-domain = <&cpufreq_hw 0>; 68 L2_100: l2-cache { 69 compatible = "cache"; 70 next-level-cache = <&L3_0>; 71 }; 72 }; 73 74 CPU2: cpu@200 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo780"; 77 reg = <0x0 0x200>; 78 enable-method = "psci"; 79 next-level-cache = <&L2_200>; 80 power-domains = <&CPU_PD2>; 81 power-domain-names = "psci"; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo780"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_300>; 95 power-domains = <&CPU_PD3>; 96 power-domain-names = "psci"; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 L2_300: l2-cache { 99 compatible = "cache"; 100 next-level-cache = <&L3_0>; 101 }; 102 }; 103 104 CPU4: cpu@400 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo780"; 107 reg = <0x0 0x400>; 108 enable-method = "psci"; 109 next-level-cache = <&L2_400>; 110 power-domains = <&CPU_PD4>; 111 power-domain-names = "psci"; 112 qcom,freq-domain = <&cpufreq_hw 1>; 113 L2_400: l2-cache { 114 compatible = "cache"; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU5: cpu@500 { 120 device_type = "cpu"; 121 compatible = "qcom,kryo780"; 122 reg = <0x0 0x500>; 123 enable-method = "psci"; 124 next-level-cache = <&L2_500>; 125 power-domains = <&CPU_PD5>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 1>; 128 L2_500: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 133 }; 134 135 CPU6: cpu@600 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x600>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_600>; 141 power-domains = <&CPU_PD6>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 L2_600: l2-cache { 145 compatible = "cache"; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU7: cpu@700 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo780"; 153 reg = <0x0 0x700>; 154 enable-method = "psci"; 155 next-level-cache = <&L2_700>; 156 power-domains = <&CPU_PD7>; 157 power-domain-names = "psci"; 158 qcom,freq-domain = <&cpufreq_hw 2>; 159 L2_700: l2-cache { 160 compatible = "cache"; 161 next-level-cache = <&L3_0>; 162 }; 163 }; 164 165 cpu-map { 166 cluster0 { 167 core0 { 168 cpu = <&CPU0>; 169 }; 170 171 core1 { 172 cpu = <&CPU1>; 173 }; 174 175 core2 { 176 cpu = <&CPU2>; 177 }; 178 179 core3 { 180 cpu = <&CPU3>; 181 }; 182 183 core4 { 184 cpu = <&CPU4>; 185 }; 186 187 core5 { 188 cpu = <&CPU5>; 189 }; 190 191 core6 { 192 cpu = <&CPU6>; 193 }; 194 195 core7 { 196 cpu = <&CPU7>; 197 }; 198 }; 199 }; 200 201 idle-states { 202 entry-method = "psci"; 203 204 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 205 compatible = "arm,idle-state"; 206 idle-state-name = "silver-rail-power-collapse"; 207 arm,psci-suspend-param = <0x40000004>; 208 entry-latency-us = <800>; 209 exit-latency-us = <750>; 210 min-residency-us = <4090>; 211 local-timer-stop; 212 }; 213 214 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 215 compatible = "arm,idle-state"; 216 idle-state-name = "gold-rail-power-collapse"; 217 arm,psci-suspend-param = <0x40000004>; 218 entry-latency-us = <600>; 219 exit-latency-us = <1550>; 220 min-residency-us = <4791>; 221 local-timer-stop; 222 }; 223 }; 224 225 domain-idle-states { 226 CLUSTER_SLEEP_0: cluster-sleep-0 { 227 compatible = "domain-idle-state"; 228 idle-state-name = "cluster-l3-off"; 229 arm,psci-suspend-param = <0x41000044>; 230 entry-latency-us = <1050>; 231 exit-latency-us = <2500>; 232 min-residency-us = <5309>; 233 local-timer-stop; 234 }; 235 236 CLUSTER_SLEEP_1: cluster-sleep-1 { 237 compatible = "domain-idle-state"; 238 idle-state-name = "cluster-power-collapse"; 239 arm,psci-suspend-param = <0x4100c344>; 240 entry-latency-us = <2700>; 241 exit-latency-us = <3500>; 242 min-residency-us = <13959>; 243 local-timer-stop; 244 }; 245 }; 246 }; 247 248 firmware { 249 scm: scm { 250 compatible = "qcom,scm-sm8450", "qcom,scm"; 251 #reset-cells = <1>; 252 }; 253 }; 254 255 clk_virt: interconnect@0 { 256 compatible = "qcom,sm8450-clk-virt"; 257 #interconnect-cells = <2>; 258 qcom,bcm-voters = <&apps_bcm_voter>; 259 }; 260 261 mc_virt: interconnect@1 { 262 compatible = "qcom,sm8450-mc-virt"; 263 #interconnect-cells = <2>; 264 qcom,bcm-voters = <&apps_bcm_voter>; 265 }; 266 267 memory@a0000000 { 268 device_type = "memory"; 269 /* We expect the bootloader to fill in the size */ 270 reg = <0x0 0xa0000000 0x0 0x0>; 271 }; 272 273 pmu { 274 compatible = "arm,armv8-pmuv3"; 275 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 psci { 279 compatible = "arm,psci-1.0"; 280 method = "smc"; 281 282 CPU_PD0: cpu0 { 283 #power-domain-cells = <0>; 284 power-domains = <&CLUSTER_PD>; 285 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 286 }; 287 288 CPU_PD1: cpu1 { 289 #power-domain-cells = <0>; 290 power-domains = <&CLUSTER_PD>; 291 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 292 }; 293 294 CPU_PD2: cpu2 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 298 }; 299 300 CPU_PD3: cpu3 { 301 #power-domain-cells = <0>; 302 power-domains = <&CLUSTER_PD>; 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 304 }; 305 306 CPU_PD4: cpu4 { 307 #power-domain-cells = <0>; 308 power-domains = <&CLUSTER_PD>; 309 domain-idle-states = <&BIG_CPU_SLEEP_0>; 310 }; 311 312 CPU_PD5: cpu5 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&BIG_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD6: cpu6 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&BIG_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD7: cpu7 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&BIG_CPU_SLEEP_0>; 328 }; 329 330 CLUSTER_PD: cpu-cluster0 { 331 #power-domain-cells = <0>; 332 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 333 }; 334 }; 335 336 reserved_memory: reserved-memory { 337 #address-cells = <2>; 338 #size-cells = <2>; 339 ranges; 340 341 hyp_mem: memory@80000000 { 342 reg = <0x0 0x80000000 0x0 0x600000>; 343 no-map; 344 }; 345 346 xbl_dt_log_mem: memory@80600000 { 347 reg = <0x0 0x80600000 0x0 0x40000>; 348 no-map; 349 }; 350 351 xbl_ramdump_mem: memory@80640000 { 352 reg = <0x0 0x80640000 0x0 0x180000>; 353 no-map; 354 }; 355 356 xbl_sc_mem: memory@807c0000 { 357 reg = <0x0 0x807c0000 0x0 0x40000>; 358 no-map; 359 }; 360 361 aop_image_mem: memory@80800000 { 362 reg = <0x0 0x80800000 0x0 0x60000>; 363 no-map; 364 }; 365 366 aop_cmd_db_mem: memory@80860000 { 367 compatible = "qcom,cmd-db"; 368 reg = <0x0 0x80860000 0x0 0x20000>; 369 no-map; 370 }; 371 372 aop_config_mem: memory@80880000 { 373 reg = <0x0 0x80880000 0x0 0x20000>; 374 no-map; 375 }; 376 377 tme_crash_dump_mem: memory@808a0000 { 378 reg = <0x0 0x808a0000 0x0 0x40000>; 379 no-map; 380 }; 381 382 tme_log_mem: memory@808e0000 { 383 reg = <0x0 0x808e0000 0x0 0x4000>; 384 no-map; 385 }; 386 387 uefi_log_mem: memory@808e4000 { 388 reg = <0x0 0x808e4000 0x0 0x10000>; 389 no-map; 390 }; 391 392 /* secdata region can be reused by apps */ 393 smem: memory@80900000 { 394 compatible = "qcom,smem"; 395 reg = <0x0 0x80900000 0x0 0x200000>; 396 hwlocks = <&tcsr_mutex 3>; 397 no-map; 398 }; 399 400 cpucp_fw_mem: memory@80b00000 { 401 reg = <0x0 0x80b00000 0x0 0x100000>; 402 no-map; 403 }; 404 405 cdsp_secure_heap: memory@80c00000 { 406 reg = <0x0 0x80c00000 0x0 0x4600000>; 407 no-map; 408 }; 409 410 camera_mem: memory@85200000 { 411 reg = <0x0 0x85200000 0x0 0x500000>; 412 no-map; 413 }; 414 415 video_mem: memory@85700000 { 416 reg = <0x0 0x85700000 0x0 0x700000>; 417 no-map; 418 }; 419 420 adsp_mem: memory@85e00000 { 421 reg = <0x0 0x85e00000 0x0 0x2100000>; 422 no-map; 423 }; 424 425 slpi_mem: memory@88000000 { 426 reg = <0x0 0x88000000 0x0 0x1900000>; 427 no-map; 428 }; 429 430 cdsp_mem: memory@89900000 { 431 reg = <0x0 0x89900000 0x0 0x2000000>; 432 no-map; 433 }; 434 435 ipa_fw_mem: memory@8b900000 { 436 reg = <0x0 0x8b900000 0x0 0x10000>; 437 no-map; 438 }; 439 440 ipa_gsi_mem: memory@8b910000 { 441 reg = <0x0 0x8b910000 0x0 0xa000>; 442 no-map; 443 }; 444 445 gpu_micro_code_mem: memory@8b91a000 { 446 reg = <0x0 0x8b91a000 0x0 0x2000>; 447 no-map; 448 }; 449 450 spss_region_mem: memory@8ba00000 { 451 reg = <0x0 0x8ba00000 0x0 0x180000>; 452 no-map; 453 }; 454 455 /* First part of the "SPU secure shared memory" region */ 456 spu_tz_shared_mem: memory@8bb80000 { 457 reg = <0x0 0x8bb80000 0x0 0x60000>; 458 no-map; 459 }; 460 461 /* Second part of the "SPU secure shared memory" region */ 462 spu_modem_shared_mem: memory@8bbe0000 { 463 reg = <0x0 0x8bbe0000 0x0 0x20000>; 464 no-map; 465 }; 466 467 mpss_mem: memory@8bc00000 { 468 reg = <0x0 0x8bc00000 0x0 0x13200000>; 469 no-map; 470 }; 471 472 cvp_mem: memory@9ee00000 { 473 reg = <0x0 0x9ee00000 0x0 0x700000>; 474 no-map; 475 }; 476 477 rmtfs_mem: memory@9fd00000 { 478 compatible = "qcom,rmtfs-mem"; 479 reg = <0x0 0x9fd00000 0x0 0x280000>; 480 no-map; 481 482 qcom,client-id = <1>; 483 qcom,vmid = <15>; 484 }; 485 486 global_sync_mem: memory@a6f00000 { 487 reg = <0x0 0xa6f00000 0x0 0x100000>; 488 no-map; 489 }; 490 491 /* uefi region can be reused by APPS */ 492 493 /* Linux kernel image is loaded at 0xa0000000 */ 494 495 oem_vm_mem: memory@bb000000 { 496 reg = <0x0 0xbb000000 0x0 0x5000000>; 497 no-map; 498 }; 499 500 mte_mem: memory@c0000000 { 501 reg = <0x0 0xc0000000 0x0 0x20000000>; 502 no-map; 503 }; 504 505 qheebsp_reserved_mem: memory@e0000000 { 506 reg = <0x0 0xe0000000 0x0 0x600000>; 507 no-map; 508 }; 509 510 cpusys_vm_mem: memory@e0600000 { 511 reg = <0x0 0xe0600000 0x0 0x400000>; 512 no-map; 513 }; 514 515 hyp_reserved_mem: memory@e0a00000 { 516 reg = <0x0 0xe0a00000 0x0 0x100000>; 517 no-map; 518 }; 519 520 trust_ui_vm_mem: memory@e0b00000 { 521 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 522 no-map; 523 }; 524 525 trust_ui_vm_qrtr: memory@e55f3000 { 526 reg = <0x0 0xe55f3000 0x0 0x9000>; 527 no-map; 528 }; 529 530 trust_ui_vm_vblk0_ring: memory@e55fc000 { 531 reg = <0x0 0xe55fc000 0x0 0x4000>; 532 no-map; 533 }; 534 535 trust_ui_vm_swiotlb: memory@e5600000 { 536 reg = <0x0 0xe5600000 0x0 0x100000>; 537 no-map; 538 }; 539 540 tz_stat_mem: memory@e8800000 { 541 reg = <0x0 0xe8800000 0x0 0x100000>; 542 no-map; 543 }; 544 545 tags_mem: memory@e8900000 { 546 reg = <0x0 0xe8900000 0x0 0x1200000>; 547 no-map; 548 }; 549 550 qtee_mem: memory@e9b00000 { 551 reg = <0x0 0xe9b00000 0x0 0x500000>; 552 no-map; 553 }; 554 555 trusted_apps_mem: memory@ea000000 { 556 reg = <0x0 0xea000000 0x0 0x3900000>; 557 no-map; 558 }; 559 560 trusted_apps_ext_mem: memory@ed900000 { 561 reg = <0x0 0xed900000 0x0 0x3b00000>; 562 no-map; 563 }; 564 }; 565 566 smp2p-adsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <443>, <429>; 569 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 570 IPCC_MPROC_SIGNAL_SMP2P 571 IRQ_TYPE_EDGE_RISING>; 572 mboxes = <&ipcc IPCC_CLIENT_LPASS 573 IPCC_MPROC_SIGNAL_SMP2P>; 574 575 qcom,local-pid = <0>; 576 qcom,remote-pid = <2>; 577 578 smp2p_adsp_out: master-kernel { 579 qcom,entry-name = "master-kernel"; 580 #qcom,smem-state-cells = <1>; 581 }; 582 583 smp2p_adsp_in: slave-kernel { 584 qcom,entry-name = "slave-kernel"; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-cdsp { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <94>, <432>; 593 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 594 IPCC_MPROC_SIGNAL_SMP2P 595 IRQ_TYPE_EDGE_RISING>; 596 mboxes = <&ipcc IPCC_CLIENT_CDSP 597 IPCC_MPROC_SIGNAL_SMP2P>; 598 599 qcom,local-pid = <0>; 600 qcom,remote-pid = <5>; 601 602 smp2p_cdsp_out: master-kernel { 603 qcom,entry-name = "master-kernel"; 604 #qcom,smem-state-cells = <1>; 605 }; 606 607 smp2p_cdsp_in: slave-kernel { 608 qcom,entry-name = "slave-kernel"; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 }; 613 614 smp2p-modem { 615 compatible = "qcom,smp2p"; 616 qcom,smem = <435>, <428>; 617 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 618 IPCC_MPROC_SIGNAL_SMP2P 619 IRQ_TYPE_EDGE_RISING>; 620 mboxes = <&ipcc IPCC_CLIENT_MPSS 621 IPCC_MPROC_SIGNAL_SMP2P>; 622 623 qcom,local-pid = <0>; 624 qcom,remote-pid = <1>; 625 626 smp2p_modem_out: master-kernel { 627 qcom,entry-name = "master-kernel"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 smp2p_modem_in: slave-kernel { 632 qcom,entry-name = "slave-kernel"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 637 ipa_smp2p_out: ipa-ap-to-modem { 638 qcom,entry-name = "ipa"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 ipa_smp2p_in: ipa-modem-to-ap { 643 qcom,entry-name = "ipa"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 smp2p-slpi { 650 compatible = "qcom,smp2p"; 651 qcom,smem = <481>, <430>; 652 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 653 IPCC_MPROC_SIGNAL_SMP2P 654 IRQ_TYPE_EDGE_RISING>; 655 mboxes = <&ipcc IPCC_CLIENT_SLPI 656 IPCC_MPROC_SIGNAL_SMP2P>; 657 658 qcom,local-pid = <0>; 659 qcom,remote-pid = <3>; 660 661 smp2p_slpi_out: master-kernel { 662 qcom,entry-name = "master-kernel"; 663 #qcom,smem-state-cells = <1>; 664 }; 665 666 smp2p_slpi_in: slave-kernel { 667 qcom,entry-name = "slave-kernel"; 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 }; 671 }; 672 673 soc: soc@0 { 674 #address-cells = <2>; 675 #size-cells = <2>; 676 ranges = <0 0 0 0 0x10 0>; 677 dma-ranges = <0 0 0 0 0x10 0>; 678 compatible = "simple-bus"; 679 680 gcc: clock-controller@100000 { 681 compatible = "qcom,gcc-sm8450"; 682 reg = <0x0 0x00100000 0x0 0x1f4200>; 683 #clock-cells = <1>; 684 #reset-cells = <1>; 685 #power-domain-cells = <1>; 686 clock-names = "bi_tcxo", "sleep_clk"; 687 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 688 }; 689 690 qupv3_id_0: geniqup@9c0000 { 691 compatible = "qcom,geni-se-qup"; 692 reg = <0x0 0x009c0000 0x0 0x2000>; 693 clock-names = "m-ahb", "s-ahb"; 694 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 695 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 696 #address-cells = <2>; 697 #size-cells = <2>; 698 ranges; 699 status = "disabled"; 700 701 uart7: serial@99c000 { 702 compatible = "qcom,geni-debug-uart"; 703 reg = <0 0x0099c000 0 0x4000>; 704 clock-names = "se"; 705 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 708 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 status = "disabled"; 712 }; 713 }; 714 715 qupv3_id_1: geniqup@ac0000 { 716 compatible = "qcom,geni-se-qup"; 717 reg = <0x0 0x00ac0000 0x0 0x6000>; 718 clock-names = "m-ahb", "s-ahb"; 719 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 720 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 721 #address-cells = <2>; 722 #size-cells = <2>; 723 ranges; 724 status = "disabled"; 725 726 i2c13: i2c@a94000 { 727 compatible = "qcom,geni-i2c"; 728 reg = <0 0x00a94000 0 0x4000>; 729 clock-names = "se"; 730 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&qup_i2c13_data_clk>; 733 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 status = "disabled"; 737 }; 738 739 i2c14: i2c@a98000 { 740 compatible = "qcom,geni-i2c"; 741 reg = <0 0x00a98000 0 0x4000>; 742 clock-names = "se"; 743 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&qup_i2c14_data_clk>; 746 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 status = "disabled"; 750 }; 751 }; 752 753 config_noc: interconnect@1500000 { 754 compatible = "qcom,sm8450-config-noc"; 755 reg = <0 0x01500000 0 0x1c000>; 756 #interconnect-cells = <2>; 757 qcom,bcm-voters = <&apps_bcm_voter>; 758 }; 759 760 system_noc: interconnect@1680000 { 761 compatible = "qcom,sm8450-system-noc"; 762 reg = <0 0x01680000 0 0x1e200>; 763 #interconnect-cells = <2>; 764 qcom,bcm-voters = <&apps_bcm_voter>; 765 }; 766 767 pcie_noc: interconnect@16c0000 { 768 compatible = "qcom,sm8450-pcie-anoc"; 769 reg = <0 0x016c0000 0 0xe280>; 770 #interconnect-cells = <2>; 771 qcom,bcm-voters = <&apps_bcm_voter>; 772 }; 773 774 aggre1_noc: interconnect@16e0000 { 775 compatible = "qcom,sm8450-aggre1-noc"; 776 reg = <0 0x016e0000 0 0x1c080>; 777 #interconnect-cells = <2>; 778 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 779 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 780 qcom,bcm-voters = <&apps_bcm_voter>; 781 }; 782 783 aggre2_noc: interconnect@1700000 { 784 compatible = "qcom,sm8450-aggre2-noc"; 785 reg = <0 0x01700000 0 0x31080>; 786 #interconnect-cells = <2>; 787 qcom,bcm-voters = <&apps_bcm_voter>; 788 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 789 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 790 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 791 <&rpmhcc RPMH_IPA_CLK>; 792 }; 793 794 mmss_noc: interconnect@1740000 { 795 compatible = "qcom,sm8450-mmss-noc"; 796 reg = <0 0x01740000 0 0x1f080>; 797 #interconnect-cells = <2>; 798 qcom,bcm-voters = <&apps_bcm_voter>; 799 }; 800 801 tcsr_mutex: hwlock@1f40000 { 802 compatible = "qcom,tcsr-mutex"; 803 reg = <0x0 0x01f40000 0x0 0x40000>; 804 #hwlock-cells = <1>; 805 }; 806 807 usb_1_hsphy: phy@88e3000 { 808 compatible = "qcom,sm8450-usb-hs-phy", 809 "qcom,usb-snps-hs-7nm-phy"; 810 reg = <0 0x088e3000 0 0x400>; 811 status = "disabled"; 812 #phy-cells = <0>; 813 814 clocks = <&rpmhcc RPMH_CXO_CLK>; 815 clock-names = "ref"; 816 817 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 818 }; 819 820 usb_1_qmpphy: phy-wrapper@88e9000 { 821 compatible = "qcom,sm8450-qmp-usb3-phy"; 822 reg = <0 0x088e9000 0 0x200>, 823 <0 0x088e8000 0 0x20>; 824 status = "disabled"; 825 #address-cells = <2>; 826 #size-cells = <2>; 827 ranges; 828 829 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 830 <&rpmhcc RPMH_CXO_CLK>, 831 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 832 clock-names = "aux", "ref_clk_src", "com_aux"; 833 834 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 835 <&gcc GCC_USB3_PHY_PRIM_BCR>; 836 reset-names = "phy", "common"; 837 838 usb_1_ssphy: phy@88e9200 { 839 reg = <0 0x088e9200 0 0x200>, 840 <0 0x088e9400 0 0x200>, 841 <0 0x088e9c00 0 0x400>, 842 <0 0x088e9600 0 0x200>, 843 <0 0x088e9800 0 0x200>, 844 <0 0x088e9a00 0 0x100>; 845 #phy-cells = <0>; 846 #clock-cells = <1>; 847 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 848 clock-names = "pipe0"; 849 clock-output-names = "usb3_phy_pipe_clk_src"; 850 }; 851 }; 852 853 remoteproc_slpi: remoteproc@2400000 { 854 compatible = "qcom,sm8450-slpi-pas"; 855 reg = <0 0x02400000 0 0x4000>; 856 857 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 858 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 862 interrupt-names = "wdog", "fatal", "ready", 863 "handover", "stop-ack"; 864 865 clocks = <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "xo"; 867 868 power-domains = <&rpmhpd SM8450_LCX>, 869 <&rpmhpd SM8450_LMX>; 870 power-domain-names = "lcx", "lmx"; 871 872 memory-region = <&slpi_mem>; 873 874 qcom,qmp = <&aoss_qmp>; 875 876 qcom,smem-states = <&smp2p_slpi_out 0>; 877 qcom,smem-state-names = "stop"; 878 879 status = "disabled"; 880 881 glink-edge { 882 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 883 IPCC_MPROC_SIGNAL_GLINK_QMP 884 IRQ_TYPE_EDGE_RISING>; 885 mboxes = <&ipcc IPCC_CLIENT_SLPI 886 IPCC_MPROC_SIGNAL_GLINK_QMP>; 887 888 label = "slpi"; 889 qcom,remote-pid = <3>; 890 }; 891 }; 892 893 remoteproc_adsp: remoteproc@30000000 { 894 compatible = "qcom,sm8450-adsp-pas"; 895 reg = <0 0x030000000 0 0x100>; 896 897 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 898 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 899 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 900 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 901 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 902 interrupt-names = "wdog", "fatal", "ready", 903 "handover", "stop-ack"; 904 905 clocks = <&rpmhcc RPMH_CXO_CLK>; 906 clock-names = "xo"; 907 908 power-domains = <&rpmhpd SM8450_LCX>, 909 <&rpmhpd SM8450_LMX>; 910 power-domain-names = "lcx", "lmx"; 911 912 memory-region = <&adsp_mem>; 913 914 qcom,qmp = <&aoss_qmp>; 915 916 qcom,smem-states = <&smp2p_adsp_out 0>; 917 qcom,smem-state-names = "stop"; 918 919 status = "disabled"; 920 921 remoteproc_adsp_glink: glink-edge { 922 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 923 IPCC_MPROC_SIGNAL_GLINK_QMP 924 IRQ_TYPE_EDGE_RISING>; 925 mboxes = <&ipcc IPCC_CLIENT_LPASS 926 IPCC_MPROC_SIGNAL_GLINK_QMP>; 927 928 label = "lpass"; 929 qcom,remote-pid = <2>; 930 }; 931 }; 932 933 remoteproc_cdsp: remoteproc@32300000 { 934 compatible = "qcom,sm8450-cdsp-pas"; 935 reg = <0 0x032300000 0 0x1400000>; 936 937 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 938 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 939 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 940 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 941 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 942 interrupt-names = "wdog", "fatal", "ready", 943 "handover", "stop-ack"; 944 945 clocks = <&rpmhcc RPMH_CXO_CLK>; 946 clock-names = "xo"; 947 948 power-domains = <&rpmhpd SM8450_CX>, 949 <&rpmhpd SM8450_MXC>; 950 power-domain-names = "cx", "mxc"; 951 952 memory-region = <&cdsp_mem>; 953 954 qcom,qmp = <&aoss_qmp>; 955 956 qcom,smem-states = <&smp2p_cdsp_out 0>; 957 qcom,smem-state-names = "stop"; 958 959 status = "disabled"; 960 961 glink-edge { 962 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 963 IPCC_MPROC_SIGNAL_GLINK_QMP 964 IRQ_TYPE_EDGE_RISING>; 965 mboxes = <&ipcc IPCC_CLIENT_CDSP 966 IPCC_MPROC_SIGNAL_GLINK_QMP>; 967 968 label = "cdsp"; 969 qcom,remote-pid = <5>; 970 }; 971 }; 972 973 remoteproc_mpss: remoteproc@4080000 { 974 compatible = "qcom,sm8450-mpss-pas"; 975 reg = <0x0 0x04080000 0x0 0x4040>; 976 977 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 978 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 979 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 980 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 981 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 982 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 983 interrupt-names = "wdog", "fatal", "ready", "handover", 984 "stop-ack", "shutdown-ack"; 985 986 clocks = <&rpmhcc RPMH_CXO_CLK>; 987 clock-names = "xo"; 988 989 power-domains = <&rpmhpd 0>, 990 <&rpmhpd 12>; 991 power-domain-names = "cx", "mss"; 992 993 memory-region = <&mpss_mem>; 994 995 qcom,qmp = <&aoss_qmp>; 996 997 qcom,smem-states = <&smp2p_modem_out 0>; 998 qcom,smem-state-names = "stop"; 999 1000 status = "disabled"; 1001 1002 glink-edge { 1003 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1004 IPCC_MPROC_SIGNAL_GLINK_QMP 1005 IRQ_TYPE_EDGE_RISING>; 1006 mboxes = <&ipcc IPCC_CLIENT_MPSS 1007 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1008 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1009 label = "modem"; 1010 qcom,remote-pid = <1>; 1011 }; 1012 }; 1013 1014 pdc: interrupt-controller@b220000 { 1015 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 1016 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 1017 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 1018 <94 609 31>, <125 63 1>, <126 716 12>; 1019 #interrupt-cells = <2>; 1020 interrupt-parent = <&intc>; 1021 interrupt-controller; 1022 }; 1023 1024 aoss_qmp: power-controller@c300000 { 1025 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 1026 reg = <0 0x0c300000 0 0x400>; 1027 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1028 IRQ_TYPE_EDGE_RISING>; 1029 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1030 1031 #clock-cells = <0>; 1032 }; 1033 1034 ipcc: mailbox@ed18000 { 1035 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 1036 reg = <0 0x0ed18000 0 0x1000>; 1037 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1038 interrupt-controller; 1039 #interrupt-cells = <3>; 1040 #mbox-cells = <2>; 1041 }; 1042 1043 tlmm: pinctrl@f100000 { 1044 compatible = "qcom,sm8450-tlmm"; 1045 reg = <0 0x0f100000 0 0x300000>; 1046 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1047 gpio-controller; 1048 #gpio-cells = <2>; 1049 interrupt-controller; 1050 #interrupt-cells = <2>; 1051 gpio-ranges = <&tlmm 0 0 211>; 1052 wakeup-parent = <&pdc>; 1053 1054 qup_i2c13_data_clk: qup-i2c13-data-clk { 1055 pins = "gpio48", "gpio49"; 1056 function = "qup13"; 1057 drive-strength = <2>; 1058 bias-pull-up; 1059 }; 1060 1061 qup_i2c14_data_clk: qup-i2c14-data-clk { 1062 pins = "gpio52", "gpio53"; 1063 function = "qup14"; 1064 drive-strength = <2>; 1065 bias-pull-up; 1066 }; 1067 1068 qup_uart7_rx: qup-uart7-rx { 1069 pins = "gpio26"; 1070 function = "qup7"; 1071 drive-strength = <2>; 1072 bias-disable; 1073 }; 1074 1075 qup_uart7_tx: qup-uart7-tx { 1076 pins = "gpio27"; 1077 function = "qup7"; 1078 drive-strength = <2>; 1079 bias-disable; 1080 }; 1081 }; 1082 1083 apps_smmu: iommu@15000000 { 1084 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 1085 reg = <0 0x15000000 0 0x100000>; 1086 #iommu-cells = <2>; 1087 #global-interrupts = <1>; 1088 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 1185 }; 1186 1187 intc: interrupt-controller@17100000 { 1188 compatible = "arm,gic-v3"; 1189 #interrupt-cells = <3>; 1190 interrupt-controller; 1191 #redistributor-regions = <1>; 1192 redistributor-stride = <0x0 0x40000>; 1193 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 1194 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 1195 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1196 }; 1197 1198 timer@17420000 { 1199 compatible = "arm,armv7-timer-mem"; 1200 #address-cells = <2>; 1201 #size-cells = <2>; 1202 ranges; 1203 reg = <0x0 0x17420000 0x0 0x1000>; 1204 clock-frequency = <19200000>; 1205 1206 frame@17421000 { 1207 frame-number = <0>; 1208 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1210 reg = <0x0 0x17421000 0x0 0x1000>, 1211 <0x0 0x17422000 0x0 0x1000>; 1212 }; 1213 1214 frame@17423000 { 1215 frame-number = <1>; 1216 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1217 reg = <0x0 0x17423000 0x0 0x1000>; 1218 status = "disabled"; 1219 }; 1220 1221 frame@17425000 { 1222 frame-number = <2>; 1223 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1224 reg = <0x0 0x17425000 0x0 0x1000>; 1225 status = "disabled"; 1226 }; 1227 1228 frame@17427000 { 1229 frame-number = <3>; 1230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1231 reg = <0x0 0x17427000 0x0 0x1000>; 1232 status = "disabled"; 1233 }; 1234 1235 frame@17429000 { 1236 frame-number = <4>; 1237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1238 reg = <0x0 0x17429000 0x0 0x1000>; 1239 status = "disabled"; 1240 }; 1241 1242 frame@1742b000 { 1243 frame-number = <5>; 1244 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1245 reg = <0x0 0x1742b000 0x0 0x1000>; 1246 status = "disabled"; 1247 }; 1248 1249 frame@1742d000 { 1250 frame-number = <6>; 1251 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1252 reg = <0x0 0x1742d000 0x0 0x1000>; 1253 status = "disabled"; 1254 }; 1255 }; 1256 1257 apps_rsc: rsc@17a00000 { 1258 label = "apps_rsc"; 1259 compatible = "qcom,rpmh-rsc"; 1260 reg = <0x0 0x17a00000 0x0 0x10000>, 1261 <0x0 0x17a10000 0x0 0x10000>, 1262 <0x0 0x17a20000 0x0 0x10000>, 1263 <0x0 0x17a30000 0x0 0x10000>; 1264 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 1265 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1268 qcom,tcs-offset = <0xd00>; 1269 qcom,drv-id = <2>; 1270 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 1271 <WAKE_TCS 2>, <CONTROL_TCS 0>; 1272 1273 apps_bcm_voter: bcm-voter { 1274 compatible = "qcom,bcm-voter"; 1275 }; 1276 1277 rpmhcc: clock-controller { 1278 compatible = "qcom,sm8450-rpmh-clk"; 1279 #clock-cells = <1>; 1280 clock-names = "xo"; 1281 clocks = <&xo_board>; 1282 }; 1283 1284 rpmhpd: power-controller { 1285 compatible = "qcom,sm8450-rpmhpd"; 1286 #power-domain-cells = <1>; 1287 operating-points-v2 = <&rpmhpd_opp_table>; 1288 1289 rpmhpd_opp_table: opp-table { 1290 compatible = "operating-points-v2"; 1291 1292 rpmhpd_opp_ret: opp1 { 1293 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1294 }; 1295 1296 rpmhpd_opp_min_svs: opp2 { 1297 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1298 }; 1299 1300 rpmhpd_opp_low_svs: opp3 { 1301 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1302 }; 1303 1304 rpmhpd_opp_svs: opp4 { 1305 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1306 }; 1307 1308 rpmhpd_opp_svs_l1: opp5 { 1309 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1310 }; 1311 1312 rpmhpd_opp_nom: opp6 { 1313 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1314 }; 1315 1316 rpmhpd_opp_nom_l1: opp7 { 1317 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1318 }; 1319 1320 rpmhpd_opp_nom_l2: opp8 { 1321 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1322 }; 1323 1324 rpmhpd_opp_turbo: opp9 { 1325 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1326 }; 1327 1328 rpmhpd_opp_turbo_l1: opp10 { 1329 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1330 }; 1331 }; 1332 }; 1333 }; 1334 1335 cpufreq_hw: cpufreq@17d91000 { 1336 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 1337 reg = <0 0x17d91000 0 0x1000>, 1338 <0 0x17d92000 0 0x1000>, 1339 <0 0x17d93000 0 0x1000>; 1340 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 1341 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1342 clock-names = "xo", "alternate"; 1343 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1346 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 1347 #freq-domain-cells = <1>; 1348 }; 1349 1350 gem_noc: interconnect@19100000 { 1351 compatible = "qcom,sm8450-gem-noc"; 1352 reg = <0 0x19100000 0 0xbb800>; 1353 #interconnect-cells = <2>; 1354 qcom,bcm-voters = <&apps_bcm_voter>; 1355 }; 1356 1357 system-cache-controller@19200000 { 1358 compatible = "qcom,sm8450-llcc"; 1359 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; 1360 reg-names = "llcc_base", "llcc_broadcast_base"; 1361 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1362 }; 1363 1364 ufs_mem_hc: ufshc@1d84000 { 1365 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 1366 "jedec,ufs-2.0"; 1367 reg = <0 0x01d84000 0 0x3000>; 1368 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1369 phys = <&ufs_mem_phy_lanes>; 1370 phy-names = "ufsphy"; 1371 lanes-per-direction = <2>; 1372 #reset-cells = <1>; 1373 resets = <&gcc GCC_UFS_PHY_BCR>; 1374 reset-names = "rst"; 1375 1376 power-domains = <&gcc UFS_PHY_GDSC>; 1377 1378 iommus = <&apps_smmu 0xe0 0x0>; 1379 1380 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 1381 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 1382 interconnect-names = "ufs-ddr", "cpu-ufs"; 1383 clock-names = 1384 "core_clk", 1385 "bus_aggr_clk", 1386 "iface_clk", 1387 "core_clk_unipro", 1388 "ref_clk", 1389 "tx_lane0_sync_clk", 1390 "rx_lane0_sync_clk", 1391 "rx_lane1_sync_clk"; 1392 clocks = 1393 <&gcc GCC_UFS_PHY_AXI_CLK>, 1394 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1395 <&gcc GCC_UFS_PHY_AHB_CLK>, 1396 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1397 <&rpmhcc RPMH_CXO_CLK>, 1398 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1399 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1400 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1401 freq-table-hz = 1402 <75000000 300000000>, 1403 <0 0>, 1404 <0 0>, 1405 <75000000 300000000>, 1406 <75000000 300000000>, 1407 <0 0>, 1408 <0 0>, 1409 <0 0>; 1410 status = "disabled"; 1411 }; 1412 1413 ufs_mem_phy: phy@1d87000 { 1414 compatible = "qcom,sm8450-qmp-ufs-phy"; 1415 reg = <0 0x01d87000 0 0xe10>; 1416 #address-cells = <2>; 1417 #size-cells = <2>; 1418 ranges; 1419 clock-names = "ref", "ref_aux", "qref"; 1420 clocks = <&rpmhcc RPMH_CXO_CLK>, 1421 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1422 <&gcc GCC_UFS_0_CLKREF_EN>; 1423 1424 resets = <&ufs_mem_hc 0>; 1425 reset-names = "ufsphy"; 1426 status = "disabled"; 1427 1428 ufs_mem_phy_lanes: lanes@1d87400 { 1429 reg = <0 0x01d87400 0 0x108>, 1430 <0 0x01d87600 0 0x1e0>, 1431 <0 0x01d87c00 0 0x1dc>, 1432 <0 0x01d87800 0 0x108>, 1433 <0 0x01d87a00 0 0x1e0>; 1434 #phy-cells = <0>; 1435 #clock-cells = <0>; 1436 }; 1437 }; 1438 1439 usb_1: usb@a6f8800 { 1440 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 1441 reg = <0 0x0a6f8800 0 0x400>; 1442 status = "disabled"; 1443 #address-cells = <2>; 1444 #size-cells = <2>; 1445 ranges; 1446 1447 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1448 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1449 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1450 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1451 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1452 <&gcc GCC_USB3_0_CLKREF_EN>; 1453 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1454 "sleep", "xo"; 1455 1456 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1457 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1458 assigned-clock-rates = <19200000>, <200000000>; 1459 1460 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1461 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1462 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1463 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1464 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1465 "dm_hs_phy_irq", "ss_phy_irq"; 1466 1467 power-domains = <&gcc USB30_PRIM_GDSC>; 1468 1469 resets = <&gcc GCC_USB30_PRIM_BCR>; 1470 1471 usb_1_dwc3: usb@a600000 { 1472 compatible = "snps,dwc3"; 1473 reg = <0 0x0a600000 0 0xcd00>; 1474 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1475 iommus = <&apps_smmu 0x0 0x0>; 1476 snps,dis_u2_susphy_quirk; 1477 snps,dis_enblslpm_quirk; 1478 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1479 phy-names = "usb2-phy", "usb3-phy"; 1480 }; 1481 }; 1482 1483 nsp_noc: interconnect@320c0000 { 1484 compatible = "qcom,sm8450-nsp-noc"; 1485 reg = <0 0x320c0000 0 0x10000>; 1486 #interconnect-cells = <2>; 1487 qcom,bcm-voters = <&apps_bcm_voter>; 1488 }; 1489 1490 lpass_ag_noc: interconnect@3c40000 { 1491 compatible = "qcom,sm8450-lpass-ag-noc"; 1492 reg = <0 0x3c40000 0 0x17200>; 1493 #interconnect-cells = <2>; 1494 qcom,bcm-voters = <&apps_bcm_voter>; 1495 }; 1496 }; 1497 1498 timer { 1499 compatible = "arm,armv8-timer"; 1500 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1501 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1502 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1503 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1504 clock-frequency = <19200000>; 1505 }; 1506}; 1507