1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/interconnect/qcom,sm8450.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <76800000>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32000>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo780"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 power-domains = <&CPU_PD0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 #cooling-cells = <2>; 57 clocks = <&cpufreq_hw 0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 next-level-cache = <&L3_0>; 62 L3_0: l3-cache { 63 compatible = "cache"; 64 cache-level = <3>; 65 }; 66 }; 67 }; 68 69 CPU1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "qcom,kryo780"; 72 reg = <0x0 0x100>; 73 enable-method = "psci"; 74 next-level-cache = <&L2_100>; 75 power-domains = <&CPU_PD1>; 76 power-domain-names = "psci"; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 #cooling-cells = <2>; 79 clocks = <&cpufreq_hw 0>; 80 L2_100: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 next-level-cache = <&L3_0>; 84 }; 85 }; 86 87 CPU2: cpu@200 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo780"; 90 reg = <0x0 0x200>; 91 enable-method = "psci"; 92 next-level-cache = <&L2_200>; 93 power-domains = <&CPU_PD2>; 94 power-domain-names = "psci"; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 clocks = <&cpufreq_hw 0>; 98 L2_200: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU3: cpu@300 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo780"; 108 reg = <0x0 0x300>; 109 enable-method = "psci"; 110 next-level-cache = <&L2_300>; 111 power-domains = <&CPU_PD3>; 112 power-domain-names = "psci"; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 clocks = <&cpufreq_hw 0>; 116 L2_300: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU4: cpu@400 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo780"; 126 reg = <0x0 0x400>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_400>; 129 power-domains = <&CPU_PD4>; 130 power-domain-names = "psci"; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 #cooling-cells = <2>; 133 clocks = <&cpufreq_hw 1>; 134 L2_400: l2-cache { 135 compatible = "cache"; 136 cache-level = <2>; 137 next-level-cache = <&L3_0>; 138 }; 139 }; 140 141 CPU5: cpu@500 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo780"; 144 reg = <0x0 0x500>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_500>; 147 power-domains = <&CPU_PD5>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 #cooling-cells = <2>; 151 clocks = <&cpufreq_hw 1>; 152 L2_500: l2-cache { 153 compatible = "cache"; 154 cache-level = <2>; 155 next-level-cache = <&L3_0>; 156 }; 157 158 }; 159 160 CPU6: cpu@600 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo780"; 163 reg = <0x0 0x600>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_600>; 166 power-domains = <&CPU_PD6>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 #cooling-cells = <2>; 170 clocks = <&cpufreq_hw 1>; 171 L2_600: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo780"; 181 reg = <0x0 0x700>; 182 enable-method = "psci"; 183 next-level-cache = <&L2_700>; 184 power-domains = <&CPU_PD7>; 185 power-domain-names = "psci"; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 #cooling-cells = <2>; 188 clocks = <&cpufreq_hw 2>; 189 L2_700: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 214 core4 { 215 cpu = <&CPU4>; 216 }; 217 218 core5 { 219 cpu = <&CPU5>; 220 }; 221 222 core6 { 223 cpu = <&CPU6>; 224 }; 225 226 core7 { 227 cpu = <&CPU7>; 228 }; 229 }; 230 }; 231 232 idle-states { 233 entry-method = "psci"; 234 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "silver-rail-power-collapse"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <800>; 240 exit-latency-us = <750>; 241 min-residency-us = <4090>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "gold-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <600>; 250 exit-latency-us = <1550>; 251 min-residency-us = <4791>; 252 local-timer-stop; 253 }; 254 }; 255 256 domain-idle-states { 257 CLUSTER_SLEEP_0: cluster-sleep-0 { 258 compatible = "domain-idle-state"; 259 idle-state-name = "cluster-l3-off"; 260 arm,psci-suspend-param = <0x41000044>; 261 entry-latency-us = <1050>; 262 exit-latency-us = <2500>; 263 min-residency-us = <5309>; 264 local-timer-stop; 265 }; 266 267 CLUSTER_SLEEP_1: cluster-sleep-1 { 268 compatible = "domain-idle-state"; 269 idle-state-name = "cluster-power-collapse"; 270 arm,psci-suspend-param = <0x4100c344>; 271 entry-latency-us = <2700>; 272 exit-latency-us = <3500>; 273 min-residency-us = <13959>; 274 local-timer-stop; 275 }; 276 }; 277 }; 278 279 firmware { 280 scm: scm { 281 compatible = "qcom,scm-sm8450", "qcom,scm"; 282 qcom,dload-mode = <&tcsr 0x13000>; 283 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 284 #reset-cells = <1>; 285 }; 286 }; 287 288 clk_virt: interconnect-0 { 289 compatible = "qcom,sm8450-clk-virt"; 290 #interconnect-cells = <2>; 291 qcom,bcm-voters = <&apps_bcm_voter>; 292 }; 293 294 mc_virt: interconnect-1 { 295 compatible = "qcom,sm8450-mc-virt"; 296 #interconnect-cells = <2>; 297 qcom,bcm-voters = <&apps_bcm_voter>; 298 }; 299 300 memory@a0000000 { 301 device_type = "memory"; 302 /* We expect the bootloader to fill in the size */ 303 reg = <0x0 0xa0000000 0x0 0x0>; 304 }; 305 306 pmu { 307 compatible = "arm,armv8-pmuv3"; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 309 }; 310 311 psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 315 CPU_PD0: power-domain-cpu0 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_PD>; 318 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD1: power-domain-cpu1 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_PD>; 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD2: power-domain-cpu2 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_PD>; 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD3: power-domain-cpu3 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_PD>; 336 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 337 }; 338 339 CPU_PD4: power-domain-cpu4 { 340 #power-domain-cells = <0>; 341 power-domains = <&CLUSTER_PD>; 342 domain-idle-states = <&BIG_CPU_SLEEP_0>; 343 }; 344 345 CPU_PD5: power-domain-cpu5 { 346 #power-domain-cells = <0>; 347 power-domains = <&CLUSTER_PD>; 348 domain-idle-states = <&BIG_CPU_SLEEP_0>; 349 }; 350 351 CPU_PD6: power-domain-cpu6 { 352 #power-domain-cells = <0>; 353 power-domains = <&CLUSTER_PD>; 354 domain-idle-states = <&BIG_CPU_SLEEP_0>; 355 }; 356 357 CPU_PD7: power-domain-cpu7 { 358 #power-domain-cells = <0>; 359 power-domains = <&CLUSTER_PD>; 360 domain-idle-states = <&BIG_CPU_SLEEP_0>; 361 }; 362 363 CLUSTER_PD: power-domain-cpu-cluster0 { 364 #power-domain-cells = <0>; 365 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 366 }; 367 }; 368 369 qup_opp_table_100mhz: opp-table-qup { 370 compatible = "operating-points-v2"; 371 372 opp-50000000 { 373 opp-hz = /bits/ 64 <50000000>; 374 required-opps = <&rpmhpd_opp_min_svs>; 375 }; 376 377 opp-75000000 { 378 opp-hz = /bits/ 64 <75000000>; 379 required-opps = <&rpmhpd_opp_low_svs>; 380 }; 381 382 opp-100000000 { 383 opp-hz = /bits/ 64 <100000000>; 384 required-opps = <&rpmhpd_opp_svs>; 385 }; 386 }; 387 388 reserved_memory: reserved-memory { 389 #address-cells = <2>; 390 #size-cells = <2>; 391 ranges; 392 393 hyp_mem: memory@80000000 { 394 reg = <0x0 0x80000000 0x0 0x600000>; 395 no-map; 396 }; 397 398 xbl_dt_log_mem: memory@80600000 { 399 reg = <0x0 0x80600000 0x0 0x40000>; 400 no-map; 401 }; 402 403 xbl_ramdump_mem: memory@80640000 { 404 reg = <0x0 0x80640000 0x0 0x180000>; 405 no-map; 406 }; 407 408 xbl_sc_mem: memory@807c0000 { 409 reg = <0x0 0x807c0000 0x0 0x40000>; 410 no-map; 411 }; 412 413 aop_image_mem: memory@80800000 { 414 reg = <0x0 0x80800000 0x0 0x60000>; 415 no-map; 416 }; 417 418 aop_cmd_db_mem: memory@80860000 { 419 compatible = "qcom,cmd-db"; 420 reg = <0x0 0x80860000 0x0 0x20000>; 421 no-map; 422 }; 423 424 aop_config_mem: memory@80880000 { 425 reg = <0x0 0x80880000 0x0 0x20000>; 426 no-map; 427 }; 428 429 tme_crash_dump_mem: memory@808a0000 { 430 reg = <0x0 0x808a0000 0x0 0x40000>; 431 no-map; 432 }; 433 434 tme_log_mem: memory@808e0000 { 435 reg = <0x0 0x808e0000 0x0 0x4000>; 436 no-map; 437 }; 438 439 uefi_log_mem: memory@808e4000 { 440 reg = <0x0 0x808e4000 0x0 0x10000>; 441 no-map; 442 }; 443 444 /* secdata region can be reused by apps */ 445 smem: memory@80900000 { 446 compatible = "qcom,smem"; 447 reg = <0x0 0x80900000 0x0 0x200000>; 448 hwlocks = <&tcsr_mutex 3>; 449 no-map; 450 }; 451 452 cpucp_fw_mem: memory@80b00000 { 453 reg = <0x0 0x80b00000 0x0 0x100000>; 454 no-map; 455 }; 456 457 cdsp_secure_heap: memory@80c00000 { 458 reg = <0x0 0x80c00000 0x0 0x4600000>; 459 no-map; 460 }; 461 462 video_mem: memory@85700000 { 463 reg = <0x0 0x85700000 0x0 0x700000>; 464 no-map; 465 }; 466 467 adsp_mem: memory@85e00000 { 468 reg = <0x0 0x85e00000 0x0 0x2100000>; 469 no-map; 470 }; 471 472 slpi_mem: memory@88000000 { 473 reg = <0x0 0x88000000 0x0 0x1900000>; 474 no-map; 475 }; 476 477 cdsp_mem: memory@89900000 { 478 reg = <0x0 0x89900000 0x0 0x2000000>; 479 no-map; 480 }; 481 482 ipa_fw_mem: memory@8b900000 { 483 reg = <0x0 0x8b900000 0x0 0x10000>; 484 no-map; 485 }; 486 487 ipa_gsi_mem: memory@8b910000 { 488 reg = <0x0 0x8b910000 0x0 0xa000>; 489 no-map; 490 }; 491 492 gpu_micro_code_mem: memory@8b91a000 { 493 reg = <0x0 0x8b91a000 0x0 0x2000>; 494 no-map; 495 }; 496 497 spss_region_mem: memory@8ba00000 { 498 reg = <0x0 0x8ba00000 0x0 0x180000>; 499 no-map; 500 }; 501 502 /* First part of the "SPU secure shared memory" region */ 503 spu_tz_shared_mem: memory@8bb80000 { 504 reg = <0x0 0x8bb80000 0x0 0x60000>; 505 no-map; 506 }; 507 508 /* Second part of the "SPU secure shared memory" region */ 509 spu_modem_shared_mem: memory@8bbe0000 { 510 reg = <0x0 0x8bbe0000 0x0 0x20000>; 511 no-map; 512 }; 513 514 mpss_mem: memory@8bc00000 { 515 reg = <0x0 0x8bc00000 0x0 0x13200000>; 516 no-map; 517 }; 518 519 cvp_mem: memory@9ee00000 { 520 reg = <0x0 0x9ee00000 0x0 0x700000>; 521 no-map; 522 }; 523 524 camera_mem: memory@9f500000 { 525 reg = <0x0 0x9f500000 0x0 0x800000>; 526 no-map; 527 }; 528 529 rmtfs_mem: memory@9fd00000 { 530 compatible = "qcom,rmtfs-mem"; 531 reg = <0x0 0x9fd00000 0x0 0x280000>; 532 no-map; 533 534 qcom,client-id = <1>; 535 qcom,vmid = <15>; 536 }; 537 538 xbl_sc_mem2: memory@a6e00000 { 539 reg = <0x0 0xa6e00000 0x0 0x40000>; 540 no-map; 541 }; 542 543 global_sync_mem: memory@a6f00000 { 544 reg = <0x0 0xa6f00000 0x0 0x100000>; 545 no-map; 546 }; 547 548 /* uefi region can be reused by APPS */ 549 550 /* Linux kernel image is loaded at 0xa0000000 */ 551 552 oem_vm_mem: memory@bb000000 { 553 reg = <0x0 0xbb000000 0x0 0x5000000>; 554 no-map; 555 }; 556 557 mte_mem: memory@c0000000 { 558 reg = <0x0 0xc0000000 0x0 0x20000000>; 559 no-map; 560 }; 561 562 qheebsp_reserved_mem: memory@e0000000 { 563 reg = <0x0 0xe0000000 0x0 0x600000>; 564 no-map; 565 }; 566 567 cpusys_vm_mem: memory@e0600000 { 568 reg = <0x0 0xe0600000 0x0 0x400000>; 569 no-map; 570 }; 571 572 hyp_reserved_mem: memory@e0a00000 { 573 reg = <0x0 0xe0a00000 0x0 0x100000>; 574 no-map; 575 }; 576 577 trust_ui_vm_mem: memory@e0b00000 { 578 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 579 no-map; 580 }; 581 582 trust_ui_vm_qrtr: memory@e55f3000 { 583 reg = <0x0 0xe55f3000 0x0 0x9000>; 584 no-map; 585 }; 586 587 trust_ui_vm_vblk0_ring: memory@e55fc000 { 588 reg = <0x0 0xe55fc000 0x0 0x4000>; 589 no-map; 590 }; 591 592 trust_ui_vm_swiotlb: memory@e5600000 { 593 reg = <0x0 0xe5600000 0x0 0x100000>; 594 no-map; 595 }; 596 597 tz_stat_mem: memory@e8800000 { 598 reg = <0x0 0xe8800000 0x0 0x100000>; 599 no-map; 600 }; 601 602 tags_mem: memory@e8900000 { 603 reg = <0x0 0xe8900000 0x0 0x1200000>; 604 no-map; 605 }; 606 607 qtee_mem: memory@e9b00000 { 608 reg = <0x0 0xe9b00000 0x0 0x500000>; 609 no-map; 610 }; 611 612 trusted_apps_mem: memory@ea000000 { 613 reg = <0x0 0xea000000 0x0 0x3900000>; 614 no-map; 615 }; 616 617 trusted_apps_ext_mem: memory@ed900000 { 618 reg = <0x0 0xed900000 0x0 0x3b00000>; 619 no-map; 620 }; 621 }; 622 623 smp2p-adsp { 624 compatible = "qcom,smp2p"; 625 qcom,smem = <443>, <429>; 626 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 627 IPCC_MPROC_SIGNAL_SMP2P 628 IRQ_TYPE_EDGE_RISING>; 629 mboxes = <&ipcc IPCC_CLIENT_LPASS 630 IPCC_MPROC_SIGNAL_SMP2P>; 631 632 qcom,local-pid = <0>; 633 qcom,remote-pid = <2>; 634 635 smp2p_adsp_out: master-kernel { 636 qcom,entry-name = "master-kernel"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 smp2p_adsp_in: slave-kernel { 641 qcom,entry-name = "slave-kernel"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 }; 646 647 smp2p-cdsp { 648 compatible = "qcom,smp2p"; 649 qcom,smem = <94>, <432>; 650 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 651 IPCC_MPROC_SIGNAL_SMP2P 652 IRQ_TYPE_EDGE_RISING>; 653 mboxes = <&ipcc IPCC_CLIENT_CDSP 654 IPCC_MPROC_SIGNAL_SMP2P>; 655 656 qcom,local-pid = <0>; 657 qcom,remote-pid = <5>; 658 659 smp2p_cdsp_out: master-kernel { 660 qcom,entry-name = "master-kernel"; 661 #qcom,smem-state-cells = <1>; 662 }; 663 664 smp2p_cdsp_in: slave-kernel { 665 qcom,entry-name = "slave-kernel"; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 }; 669 }; 670 671 smp2p-modem { 672 compatible = "qcom,smp2p"; 673 qcom,smem = <435>, <428>; 674 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 675 IPCC_MPROC_SIGNAL_SMP2P 676 IRQ_TYPE_EDGE_RISING>; 677 mboxes = <&ipcc IPCC_CLIENT_MPSS 678 IPCC_MPROC_SIGNAL_SMP2P>; 679 680 qcom,local-pid = <0>; 681 qcom,remote-pid = <1>; 682 683 smp2p_modem_out: master-kernel { 684 qcom,entry-name = "master-kernel"; 685 #qcom,smem-state-cells = <1>; 686 }; 687 688 smp2p_modem_in: slave-kernel { 689 qcom,entry-name = "slave-kernel"; 690 interrupt-controller; 691 #interrupt-cells = <2>; 692 }; 693 694 ipa_smp2p_out: ipa-ap-to-modem { 695 qcom,entry-name = "ipa"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 ipa_smp2p_in: ipa-modem-to-ap { 700 qcom,entry-name = "ipa"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 }; 705 706 smp2p-slpi { 707 compatible = "qcom,smp2p"; 708 qcom,smem = <481>, <430>; 709 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 710 IPCC_MPROC_SIGNAL_SMP2P 711 IRQ_TYPE_EDGE_RISING>; 712 mboxes = <&ipcc IPCC_CLIENT_SLPI 713 IPCC_MPROC_SIGNAL_SMP2P>; 714 715 qcom,local-pid = <0>; 716 qcom,remote-pid = <3>; 717 718 smp2p_slpi_out: master-kernel { 719 qcom,entry-name = "master-kernel"; 720 #qcom,smem-state-cells = <1>; 721 }; 722 723 smp2p_slpi_in: slave-kernel { 724 qcom,entry-name = "slave-kernel"; 725 interrupt-controller; 726 #interrupt-cells = <2>; 727 }; 728 }; 729 730 soc: soc@0 { 731 #address-cells = <2>; 732 #size-cells = <2>; 733 ranges = <0 0 0 0 0x10 0>; 734 dma-ranges = <0 0 0 0 0x10 0>; 735 compatible = "simple-bus"; 736 737 gcc: clock-controller@100000 { 738 compatible = "qcom,gcc-sm8450"; 739 reg = <0x0 0x00100000 0x0 0x1f4200>; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 #power-domain-cells = <1>; 743 clocks = <&rpmhcc RPMH_CXO_CLK>, 744 <&sleep_clk>, 745 <&pcie0_lane>, 746 <&pcie1_lane>, 747 <0>, 748 <&ufs_mem_phy_lanes 0>, 749 <&ufs_mem_phy_lanes 1>, 750 <&ufs_mem_phy_lanes 2>, 751 <0>; 752 clock-names = "bi_tcxo", 753 "sleep_clk", 754 "pcie_0_pipe_clk", 755 "pcie_1_pipe_clk", 756 "pcie_1_phy_aux_clk", 757 "ufs_phy_rx_symbol_0_clk", 758 "ufs_phy_rx_symbol_1_clk", 759 "ufs_phy_tx_symbol_0_clk", 760 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 761 }; 762 763 gpi_dma2: dma-controller@800000 { 764 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 765 #dma-cells = <3>; 766 reg = <0 0x00800000 0 0x60000>; 767 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 779 dma-channels = <12>; 780 dma-channel-mask = <0x7e>; 781 iommus = <&apps_smmu 0x496 0x0>; 782 status = "disabled"; 783 }; 784 785 qupv3_id_2: geniqup@8c0000 { 786 compatible = "qcom,geni-se-qup"; 787 reg = <0x0 0x008c0000 0x0 0x2000>; 788 clock-names = "m-ahb", "s-ahb"; 789 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 790 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 791 iommus = <&apps_smmu 0x483 0x0>; 792 #address-cells = <2>; 793 #size-cells = <2>; 794 ranges; 795 status = "disabled"; 796 797 i2c15: i2c@880000 { 798 compatible = "qcom,geni-i2c"; 799 reg = <0x0 0x00880000 0x0 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&qup_i2c15_data_clk>; 804 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 808 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 809 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 810 interconnect-names = "qup-core", "qup-config", "qup-memory"; 811 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 812 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 813 dma-names = "tx", "rx"; 814 status = "disabled"; 815 }; 816 817 spi15: spi@880000 { 818 compatible = "qcom,geni-spi"; 819 reg = <0x0 0x00880000 0x0 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 822 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 825 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 826 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 827 interconnect-names = "qup-core", "qup-config"; 828 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 829 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 830 dma-names = "tx", "rx"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 i2c16: i2c@884000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0x0 0x00884000 0x0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&qup_i2c16_data_clk>; 843 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 847 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 848 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 849 interconnect-names = "qup-core", "qup-config", "qup-memory"; 850 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 851 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 852 dma-names = "tx", "rx"; 853 status = "disabled"; 854 }; 855 856 spi16: spi@884000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0x0 0x00884000 0x0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 861 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 864 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 865 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 866 interconnect-names = "qup-core", "qup-config"; 867 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 869 dma-names = "tx", "rx"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 status = "disabled"; 873 }; 874 875 i2c17: i2c@888000 { 876 compatible = "qcom,geni-i2c"; 877 reg = <0x0 0x00888000 0x0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_i2c17_data_clk>; 882 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 886 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 887 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 888 interconnect-names = "qup-core", "qup-config", "qup-memory"; 889 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 890 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 891 dma-names = "tx", "rx"; 892 status = "disabled"; 893 }; 894 895 spi17: spi@888000 { 896 compatible = "qcom,geni-spi"; 897 reg = <0x0 0x00888000 0x0 0x4000>; 898 clock-names = "se"; 899 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 900 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 904 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 905 interconnect-names = "qup-core", "qup-config"; 906 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 907 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 908 dma-names = "tx", "rx"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 i2c18: i2c@88c000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x0 0x0088c000 0x0 0x4000>; 917 clock-names = "se"; 918 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&qup_i2c18_data_clk>; 921 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 925 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 926 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 929 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 930 dma-names = "tx", "rx"; 931 status = "disabled"; 932 }; 933 934 spi18: spi@88c000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0 0x0088c000 0 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 939 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 942 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 943 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 944 interconnect-names = "qup-core", "qup-config"; 945 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 946 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 947 dma-names = "tx", "rx"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 i2c19: i2c@890000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0x0 0x00890000 0x0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c19_data_clk>; 960 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 964 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 965 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", "qup-memory"; 967 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 968 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 969 dma-names = "tx", "rx"; 970 status = "disabled"; 971 }; 972 973 spi19: spi@890000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x00890000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 978 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 982 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 983 interconnect-names = "qup-core", "qup-config"; 984 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 985 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 i2c20: i2c@894000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0x0 0x00894000 0x0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c20_data_clk>; 999 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1003 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1004 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1006 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1007 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1008 dma-names = "tx", "rx"; 1009 status = "disabled"; 1010 }; 1011 1012 uart20: serial@894000 { 1013 compatible = "qcom,geni-uart"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_uart20_default>; 1019 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 spi20: spi@894000 { 1026 compatible = "qcom,geni-spi"; 1027 reg = <0 0x00894000 0 0x4000>; 1028 clock-names = "se"; 1029 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1034 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1035 interconnect-names = "qup-core", "qup-config"; 1036 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1037 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1038 dma-names = "tx", "rx"; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 status = "disabled"; 1042 }; 1043 1044 i2c21: i2c@898000 { 1045 compatible = "qcom,geni-i2c"; 1046 reg = <0x0 0x00898000 0x0 0x4000>; 1047 clock-names = "se"; 1048 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1049 pinctrl-names = "default"; 1050 pinctrl-0 = <&qup_i2c21_data_clk>; 1051 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1055 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1056 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1057 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1058 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1059 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1060 dma-names = "tx", "rx"; 1061 status = "disabled"; 1062 }; 1063 1064 spi21: spi@898000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x00898000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1069 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1072 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1073 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1074 interconnect-names = "qup-core", "qup-config"; 1075 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1076 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1077 dma-names = "tx", "rx"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 }; 1083 1084 gpi_dma0: dma-controller@900000 { 1085 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1086 #dma-cells = <3>; 1087 reg = <0 0x00900000 0 0x60000>; 1088 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1100 dma-channels = <12>; 1101 dma-channel-mask = <0x7e>; 1102 iommus = <&apps_smmu 0x5b6 0x0>; 1103 status = "disabled"; 1104 }; 1105 1106 qupv3_id_0: geniqup@9c0000 { 1107 compatible = "qcom,geni-se-qup"; 1108 reg = <0x0 0x009c0000 0x0 0x2000>; 1109 clock-names = "m-ahb", "s-ahb"; 1110 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1111 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1112 iommus = <&apps_smmu 0x5a3 0x0>; 1113 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1114 interconnect-names = "qup-core"; 1115 #address-cells = <2>; 1116 #size-cells = <2>; 1117 ranges; 1118 status = "disabled"; 1119 1120 i2c0: i2c@980000 { 1121 compatible = "qcom,geni-i2c"; 1122 reg = <0x0 0x00980000 0x0 0x4000>; 1123 clock-names = "se"; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&qup_i2c0_data_clk>; 1127 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1131 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1132 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1133 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1134 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1135 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1136 dma-names = "tx", "rx"; 1137 status = "disabled"; 1138 }; 1139 1140 spi0: spi@980000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0x0 0x00980000 0x0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1145 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1148 power-domains = <&rpmhpd SM8450_CX>; 1149 operating-points-v2 = <&qup_opp_table_100mhz>; 1150 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1151 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1152 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1153 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1154 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1155 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1156 dma-names = "tx", "rx"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 i2c1: i2c@984000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0x0 0x00984000 0x0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&qup_i2c1_data_clk>; 1169 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1173 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1174 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1176 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1177 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1178 dma-names = "tx", "rx"; 1179 status = "disabled"; 1180 }; 1181 1182 spi1: spi@984000 { 1183 compatible = "qcom,geni-spi"; 1184 reg = <0x0 0x00984000 0x0 0x4000>; 1185 clock-names = "se"; 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1187 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1190 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1191 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1192 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1193 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1194 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1195 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1196 dma-names = "tx", "rx"; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 i2c2: i2c@988000 { 1203 compatible = "qcom,geni-i2c"; 1204 reg = <0x0 0x00988000 0x0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_i2c2_data_clk>; 1209 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1213 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1214 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1215 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1216 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1217 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1218 dma-names = "tx", "rx"; 1219 status = "disabled"; 1220 }; 1221 1222 spi2: spi@988000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0x0 0x00988000 0x0 0x4000>; 1225 clock-names = "se"; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1227 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1230 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1231 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1232 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1233 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1234 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1235 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1236 dma-names = "tx", "rx"; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 1243 i2c3: i2c@98c000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0x0 0x0098c000 0x0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c3_data_clk>; 1250 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1255 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1257 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1258 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1259 dma-names = "tx", "rx"; 1260 status = "disabled"; 1261 }; 1262 1263 spi3: spi@98c000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0x0 0x0098c000 0x0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1268 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1272 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1273 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1274 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1275 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1276 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 i2c4: i2c@990000 { 1284 compatible = "qcom,geni-i2c"; 1285 reg = <0x0 0x00990000 0x0 0x4000>; 1286 clock-names = "se"; 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&qup_i2c4_data_clk>; 1290 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1294 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1295 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1296 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1297 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1298 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1299 dma-names = "tx", "rx"; 1300 status = "disabled"; 1301 }; 1302 1303 spi4: spi@990000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0x0 0x00990000 0x0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1308 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1311 power-domains = <&rpmhpd SM8450_CX>; 1312 operating-points-v2 = <&qup_opp_table_100mhz>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1315 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1317 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1318 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1319 dma-names = "tx", "rx"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 i2c5: i2c@994000 { 1326 compatible = "qcom,geni-i2c"; 1327 reg = <0x0 0x00994000 0x0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_i2c5_data_clk>; 1332 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1336 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1337 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1338 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1339 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1340 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1341 dma-names = "tx", "rx"; 1342 status = "disabled"; 1343 }; 1344 1345 spi5: spi@994000 { 1346 compatible = "qcom,geni-spi"; 1347 reg = <0x0 0x00994000 0x0 0x4000>; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1350 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1354 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1355 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1356 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1357 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1358 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1359 dma-names = "tx", "rx"; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 1366 i2c6: i2c@998000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0x0 0x00998000 0x0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c6_data_clk>; 1373 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1377 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1378 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1379 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1380 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1381 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1382 dma-names = "tx", "rx"; 1383 status = "disabled"; 1384 }; 1385 1386 spi6: spi@998000 { 1387 compatible = "qcom,geni-spi"; 1388 reg = <0x0 0x00998000 0x0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1391 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1396 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1397 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1398 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1399 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1400 dma-names = "tx", "rx"; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 status = "disabled"; 1404 }; 1405 1406 uart7: serial@99c000 { 1407 compatible = "qcom,geni-debug-uart"; 1408 reg = <0 0x0099c000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1413 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 }; 1419 1420 gpi_dma1: dma-controller@a00000 { 1421 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1422 #dma-cells = <3>; 1423 reg = <0 0x00a00000 0 0x60000>; 1424 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1436 dma-channels = <12>; 1437 dma-channel-mask = <0x7e>; 1438 iommus = <&apps_smmu 0x56 0x0>; 1439 status = "disabled"; 1440 }; 1441 1442 qupv3_id_1: geniqup@ac0000 { 1443 compatible = "qcom,geni-se-qup"; 1444 reg = <0x0 0x00ac0000 0x0 0x6000>; 1445 clock-names = "m-ahb", "s-ahb"; 1446 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1447 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1448 iommus = <&apps_smmu 0x43 0x0>; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1450 interconnect-names = "qup-core"; 1451 #address-cells = <2>; 1452 #size-cells = <2>; 1453 ranges; 1454 status = "disabled"; 1455 1456 i2c8: i2c@a80000 { 1457 compatible = "qcom,geni-i2c"; 1458 reg = <0x0 0x00a80000 0x0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c8_data_clk>; 1463 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1467 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1468 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1469 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1470 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1471 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1472 dma-names = "tx", "rx"; 1473 status = "disabled"; 1474 }; 1475 1476 spi8: spi@a80000 { 1477 compatible = "qcom,geni-spi"; 1478 reg = <0x0 0x00a80000 0x0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1481 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1482 pinctrl-names = "default"; 1483 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1485 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1486 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1487 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1488 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1489 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1490 dma-names = "tx", "rx"; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 i2c9: i2c@a84000 { 1497 compatible = "qcom,geni-i2c"; 1498 reg = <0x0 0x00a84000 0x0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_i2c9_data_clk>; 1503 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1508 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1509 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1510 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1511 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1512 dma-names = "tx", "rx"; 1513 status = "disabled"; 1514 }; 1515 1516 spi9: spi@a84000 { 1517 compatible = "qcom,geni-spi"; 1518 reg = <0x0 0x00a84000 0x0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1521 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1524 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1525 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1526 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1527 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1528 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1529 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1530 dma-names = "tx", "rx"; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 i2c10: i2c@a88000 { 1537 compatible = "qcom,geni-i2c"; 1538 reg = <0x0 0x00a88000 0x0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_i2c10_data_clk>; 1543 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1547 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1548 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1549 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1550 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1551 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1552 dma-names = "tx", "rx"; 1553 status = "disabled"; 1554 }; 1555 1556 spi10: spi@a88000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0x0 0x00a88000 0x0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1561 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1565 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1566 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1567 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1568 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1569 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1570 dma-names = "tx", "rx"; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 i2c11: i2c@a8c000 { 1577 compatible = "qcom,geni-i2c"; 1578 reg = <0x0 0x00a8c000 0x0 0x4000>; 1579 clock-names = "se"; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_i2c11_data_clk>; 1583 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1587 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1588 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1589 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1590 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1591 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1592 dma-names = "tx", "rx"; 1593 status = "disabled"; 1594 }; 1595 1596 spi11: spi@a8c000 { 1597 compatible = "qcom,geni-spi"; 1598 reg = <0x0 0x00a8c000 0x0 0x4000>; 1599 clock-names = "se"; 1600 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1601 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1606 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1607 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1608 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1609 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1610 dma-names = "tx", "rx"; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c12: i2c@a90000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0x0 0x00a90000 0x0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c12_data_clk>; 1623 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1627 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1628 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1629 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1630 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1631 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1632 dma-names = "tx", "rx"; 1633 status = "disabled"; 1634 }; 1635 1636 spi12: spi@a90000 { 1637 compatible = "qcom,geni-spi"; 1638 reg = <0x0 0x00a90000 0x0 0x4000>; 1639 clock-names = "se"; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1641 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1644 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1645 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1646 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1647 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1648 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1649 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1650 dma-names = "tx", "rx"; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 status = "disabled"; 1654 }; 1655 1656 i2c13: i2c@a94000 { 1657 compatible = "qcom,geni-i2c"; 1658 reg = <0 0x00a94000 0 0x4000>; 1659 clock-names = "se"; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1661 pinctrl-names = "default"; 1662 pinctrl-0 = <&qup_i2c13_data_clk>; 1663 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1666 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1667 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1668 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1669 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1670 dma-names = "tx", "rx"; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 status = "disabled"; 1674 }; 1675 1676 spi13: spi@a94000 { 1677 compatible = "qcom,geni-spi"; 1678 reg = <0x0 0x00a94000 0x0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1681 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1684 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1685 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1686 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1687 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1688 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1689 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1690 dma-names = "tx", "rx"; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 i2c14: i2c@a98000 { 1697 compatible = "qcom,geni-i2c"; 1698 reg = <0 0x00a98000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_i2c14_data_clk>; 1703 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1704 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1705 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1706 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1707 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1708 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1709 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1710 dma-names = "tx", "rx"; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 spi14: spi@a98000 { 1717 compatible = "qcom,geni-spi"; 1718 reg = <0x0 0x00a98000 0x0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1721 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1722 pinctrl-names = "default"; 1723 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1725 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1726 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1727 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1728 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1729 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1730 dma-names = "tx", "rx"; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 status = "disabled"; 1734 }; 1735 }; 1736 1737 pcie0: pci@1c00000 { 1738 compatible = "qcom,pcie-sm8450-pcie0"; 1739 reg = <0 0x01c00000 0 0x3000>, 1740 <0 0x60000000 0 0xf1d>, 1741 <0 0x60000f20 0 0xa8>, 1742 <0 0x60001000 0 0x1000>, 1743 <0 0x60100000 0 0x100000>; 1744 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1745 device_type = "pci"; 1746 linux,pci-domain = <0>; 1747 bus-range = <0x00 0xff>; 1748 num-lanes = <1>; 1749 1750 #address-cells = <3>; 1751 #size-cells = <2>; 1752 1753 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1754 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1755 1756 /* 1757 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1758 * Hence, the IDs are swapped. 1759 */ 1760 msi-map = <0x0 &gic_its 0x5981 0x1>, 1761 <0x100 &gic_its 0x5980 0x1>; 1762 msi-map-mask = <0xff00>; 1763 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1764 interrupt-names = "msi"; 1765 #interrupt-cells = <1>; 1766 interrupt-map-mask = <0 0 0 0x7>; 1767 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1768 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1769 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1770 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1771 1772 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1773 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1774 <&pcie0_lane>, 1775 <&rpmhcc RPMH_CXO_CLK>, 1776 <&gcc GCC_PCIE_0_AUX_CLK>, 1777 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1778 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1779 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1780 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1781 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1782 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1783 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1784 clock-names = "pipe", 1785 "pipe_mux", 1786 "phy_pipe", 1787 "ref", 1788 "aux", 1789 "cfg", 1790 "bus_master", 1791 "bus_slave", 1792 "slave_q2a", 1793 "ddrss_sf_tbu", 1794 "aggre0", 1795 "aggre1"; 1796 1797 iommus = <&apps_smmu 0x1c00 0x7f>; 1798 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1799 <0x100 &apps_smmu 0x1c01 0x1>; 1800 1801 resets = <&gcc GCC_PCIE_0_BCR>; 1802 reset-names = "pci"; 1803 1804 power-domains = <&gcc PCIE_0_GDSC>; 1805 power-domain-names = "gdsc"; 1806 1807 phys = <&pcie0_lane>; 1808 phy-names = "pciephy"; 1809 1810 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1811 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1812 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&pcie0_default_state>; 1815 1816 status = "disabled"; 1817 }; 1818 1819 pcie0_phy: phy@1c06000 { 1820 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1821 reg = <0 0x01c06000 0 0x200>; 1822 #address-cells = <2>; 1823 #size-cells = <2>; 1824 ranges; 1825 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1826 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1827 <&gcc GCC_PCIE_0_CLKREF_EN>, 1828 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1829 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1830 1831 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1832 reset-names = "phy"; 1833 1834 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1835 assigned-clock-rates = <100000000>; 1836 1837 status = "disabled"; 1838 1839 pcie0_lane: phy@1c06200 { 1840 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1841 <0 0x01c07000 0 0x200>, /* rx */ 1842 <0 0x01c06200 0 0x200>, /* pcs */ 1843 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1844 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1845 clock-names = "pipe0"; 1846 1847 #clock-cells = <0>; 1848 #phy-cells = <0>; 1849 clock-output-names = "pcie_0_pipe_clk"; 1850 }; 1851 }; 1852 1853 pcie1: pci@1c08000 { 1854 compatible = "qcom,pcie-sm8450-pcie1"; 1855 reg = <0 0x01c08000 0 0x3000>, 1856 <0 0x40000000 0 0xf1d>, 1857 <0 0x40000f20 0 0xa8>, 1858 <0 0x40001000 0 0x1000>, 1859 <0 0x40100000 0 0x100000>; 1860 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1861 device_type = "pci"; 1862 linux,pci-domain = <1>; 1863 bus-range = <0x00 0xff>; 1864 num-lanes = <2>; 1865 1866 #address-cells = <3>; 1867 #size-cells = <2>; 1868 1869 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1870 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1871 1872 /* 1873 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1874 * Hence, the IDs are swapped. 1875 */ 1876 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1877 <0x100 &gic_its 0x5a00 0x1>; 1878 msi-map-mask = <0xff00>; 1879 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1880 interrupt-names = "msi"; 1881 #interrupt-cells = <1>; 1882 interrupt-map-mask = <0 0 0 0x7>; 1883 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1884 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1885 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1886 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1887 1888 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1889 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1890 <&pcie1_lane>, 1891 <&rpmhcc RPMH_CXO_CLK>, 1892 <&gcc GCC_PCIE_1_AUX_CLK>, 1893 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1894 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1895 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1896 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1897 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1898 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1899 clock-names = "pipe", 1900 "pipe_mux", 1901 "phy_pipe", 1902 "ref", 1903 "aux", 1904 "cfg", 1905 "bus_master", 1906 "bus_slave", 1907 "slave_q2a", 1908 "ddrss_sf_tbu", 1909 "aggre1"; 1910 1911 iommus = <&apps_smmu 0x1c80 0x7f>; 1912 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1913 <0x100 &apps_smmu 0x1c81 0x1>; 1914 1915 resets = <&gcc GCC_PCIE_1_BCR>; 1916 reset-names = "pci"; 1917 1918 power-domains = <&gcc PCIE_1_GDSC>; 1919 power-domain-names = "gdsc"; 1920 1921 phys = <&pcie1_lane>; 1922 phy-names = "pciephy"; 1923 1924 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; 1925 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1926 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&pcie1_default_state>; 1929 1930 status = "disabled"; 1931 }; 1932 1933 pcie1_phy: phy@1c0f000 { 1934 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1935 reg = <0 0x01c0f000 0 0x200>; 1936 #address-cells = <2>; 1937 #size-cells = <2>; 1938 ranges; 1939 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1940 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1941 <&gcc GCC_PCIE_1_CLKREF_EN>, 1942 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1943 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1944 1945 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1946 reset-names = "phy"; 1947 1948 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1949 assigned-clock-rates = <100000000>; 1950 1951 status = "disabled"; 1952 1953 pcie1_lane: phy@1c0e000 { 1954 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1955 <0 0x01c0e200 0 0x300>, /* rx */ 1956 <0 0x01c0f200 0 0x200>, /* pcs */ 1957 <0 0x01c0e800 0 0x200>, /* tx */ 1958 <0 0x01c0ea00 0 0x300>, /* rx */ 1959 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1960 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1961 clock-names = "pipe0"; 1962 1963 #clock-cells = <0>; 1964 #phy-cells = <0>; 1965 clock-output-names = "pcie_1_pipe_clk"; 1966 }; 1967 }; 1968 1969 config_noc: interconnect@1500000 { 1970 compatible = "qcom,sm8450-config-noc"; 1971 reg = <0 0x01500000 0 0x1c000>; 1972 #interconnect-cells = <2>; 1973 qcom,bcm-voters = <&apps_bcm_voter>; 1974 }; 1975 1976 system_noc: interconnect@1680000 { 1977 compatible = "qcom,sm8450-system-noc"; 1978 reg = <0 0x01680000 0 0x1e200>; 1979 #interconnect-cells = <2>; 1980 qcom,bcm-voters = <&apps_bcm_voter>; 1981 }; 1982 1983 pcie_noc: interconnect@16c0000 { 1984 compatible = "qcom,sm8450-pcie-anoc"; 1985 reg = <0 0x016c0000 0 0xe280>; 1986 #interconnect-cells = <2>; 1987 qcom,bcm-voters = <&apps_bcm_voter>; 1988 }; 1989 1990 aggre1_noc: interconnect@16e0000 { 1991 compatible = "qcom,sm8450-aggre1-noc"; 1992 reg = <0 0x016e0000 0 0x1c080>; 1993 #interconnect-cells = <2>; 1994 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1995 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1996 qcom,bcm-voters = <&apps_bcm_voter>; 1997 }; 1998 1999 aggre2_noc: interconnect@1700000 { 2000 compatible = "qcom,sm8450-aggre2-noc"; 2001 reg = <0 0x01700000 0 0x31080>; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2005 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2006 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2007 <&rpmhcc RPMH_IPA_CLK>; 2008 }; 2009 2010 mmss_noc: interconnect@1740000 { 2011 compatible = "qcom,sm8450-mmss-noc"; 2012 reg = <0 0x01740000 0 0x1f080>; 2013 #interconnect-cells = <2>; 2014 qcom,bcm-voters = <&apps_bcm_voter>; 2015 }; 2016 2017 tcsr_mutex: hwlock@1f40000 { 2018 compatible = "qcom,tcsr-mutex"; 2019 reg = <0x0 0x01f40000 0x0 0x40000>; 2020 #hwlock-cells = <1>; 2021 }; 2022 2023 tcsr: syscon@1fc0000 { 2024 compatible = "qcom,sm8450-tcsr", "syscon"; 2025 reg = <0x0 0x1fc0000 0x0 0x30000>; 2026 }; 2027 2028 usb_1_hsphy: phy@88e3000 { 2029 compatible = "qcom,sm8450-usb-hs-phy", 2030 "qcom,usb-snps-hs-7nm-phy"; 2031 reg = <0 0x088e3000 0 0x400>; 2032 status = "disabled"; 2033 #phy-cells = <0>; 2034 2035 clocks = <&rpmhcc RPMH_CXO_CLK>; 2036 clock-names = "ref"; 2037 2038 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2039 }; 2040 2041 usb_1_qmpphy: phy-wrapper@88e9000 { 2042 compatible = "qcom,sm8450-qmp-usb3-phy"; 2043 reg = <0 0x088e9000 0 0x200>, 2044 <0 0x088e8000 0 0x20>; 2045 status = "disabled"; 2046 #address-cells = <2>; 2047 #size-cells = <2>; 2048 ranges; 2049 2050 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2051 <&rpmhcc RPMH_CXO_CLK>, 2052 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2053 clock-names = "aux", "ref_clk_src", "com_aux"; 2054 2055 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2056 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2057 reset-names = "phy", "common"; 2058 2059 usb_1_ssphy: phy@88e9200 { 2060 reg = <0 0x088e9200 0 0x200>, 2061 <0 0x088e9400 0 0x200>, 2062 <0 0x088e9c00 0 0x400>, 2063 <0 0x088e9600 0 0x200>, 2064 <0 0x088e9800 0 0x200>, 2065 <0 0x088e9a00 0 0x100>; 2066 #phy-cells = <0>; 2067 #clock-cells = <0>; 2068 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2069 clock-names = "pipe0"; 2070 clock-output-names = "usb3_phy_pipe_clk_src"; 2071 }; 2072 }; 2073 2074 remoteproc_slpi: remoteproc@2400000 { 2075 compatible = "qcom,sm8450-slpi-pas"; 2076 reg = <0 0x02400000 0 0x4000>; 2077 2078 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2079 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2080 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2081 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2082 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2083 interrupt-names = "wdog", "fatal", "ready", 2084 "handover", "stop-ack"; 2085 2086 clocks = <&rpmhcc RPMH_CXO_CLK>; 2087 clock-names = "xo"; 2088 2089 power-domains = <&rpmhpd SM8450_LCX>, 2090 <&rpmhpd SM8450_LMX>; 2091 power-domain-names = "lcx", "lmx"; 2092 2093 memory-region = <&slpi_mem>; 2094 2095 qcom,qmp = <&aoss_qmp>; 2096 2097 qcom,smem-states = <&smp2p_slpi_out 0>; 2098 qcom,smem-state-names = "stop"; 2099 2100 status = "disabled"; 2101 2102 glink-edge { 2103 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2104 IPCC_MPROC_SIGNAL_GLINK_QMP 2105 IRQ_TYPE_EDGE_RISING>; 2106 mboxes = <&ipcc IPCC_CLIENT_SLPI 2107 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2108 2109 label = "slpi"; 2110 qcom,remote-pid = <3>; 2111 2112 fastrpc { 2113 compatible = "qcom,fastrpc"; 2114 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2115 label = "sdsp"; 2116 #address-cells = <1>; 2117 #size-cells = <0>; 2118 2119 compute-cb@1 { 2120 compatible = "qcom,fastrpc-compute-cb"; 2121 reg = <1>; 2122 iommus = <&apps_smmu 0x0541 0x0>; 2123 }; 2124 2125 compute-cb@2 { 2126 compatible = "qcom,fastrpc-compute-cb"; 2127 reg = <2>; 2128 iommus = <&apps_smmu 0x0542 0x0>; 2129 }; 2130 2131 compute-cb@3 { 2132 compatible = "qcom,fastrpc-compute-cb"; 2133 reg = <3>; 2134 iommus = <&apps_smmu 0x0543 0x0>; 2135 /* note: shared-cb = <4> in downstream */ 2136 }; 2137 }; 2138 }; 2139 }; 2140 2141 wsa2macro: codec@31e0000 { 2142 compatible = "qcom,sm8450-lpass-wsa-macro"; 2143 reg = <0 0x031e0000 0 0x1000>; 2144 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2145 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2146 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2147 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2148 <&vamacro>; 2149 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2150 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2151 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2152 assigned-clock-rates = <19200000>, <19200000>; 2153 2154 #clock-cells = <0>; 2155 clock-output-names = "wsa2-mclk"; 2156 pinctrl-names = "default"; 2157 pinctrl-0 = <&wsa2_swr_active>; 2158 #sound-dai-cells = <1>; 2159 }; 2160 2161 /* WSA2 */ 2162 swr4: soundwire-controller@31f0000 { 2163 compatible = "qcom,soundwire-v1.7.0"; 2164 reg = <0 0x031f0000 0 0x2000>; 2165 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2166 clocks = <&wsa2macro>; 2167 clock-names = "iface"; 2168 2169 qcom,din-ports = <2>; 2170 qcom,dout-ports = <6>; 2171 2172 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2173 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2174 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2175 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2176 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2177 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2178 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2179 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2180 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2181 2182 #address-cells = <2>; 2183 #size-cells = <0>; 2184 #sound-dai-cells = <1>; 2185 status = "disabled"; 2186 }; 2187 2188 rxmacro: codec@3200000 { 2189 compatible = "qcom,sm8450-lpass-rx-macro"; 2190 reg = <0 0x03200000 0 0x1000>; 2191 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2192 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2193 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2194 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2195 <&vamacro>; 2196 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2197 2198 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2199 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2200 assigned-clock-rates = <19200000>, <19200000>; 2201 2202 #clock-cells = <0>; 2203 clock-output-names = "mclk"; 2204 pinctrl-names = "default"; 2205 pinctrl-0 = <&rx_swr_active>; 2206 #sound-dai-cells = <1>; 2207 }; 2208 2209 swr1: soundwire-controller@3210000 { 2210 compatible = "qcom,soundwire-v1.7.0"; 2211 reg = <0 0x03210000 0 0x2000>; 2212 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2213 clocks = <&rxmacro>; 2214 clock-names = "iface"; 2215 label = "RX"; 2216 qcom,din-ports = <0>; 2217 qcom,dout-ports = <5>; 2218 2219 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2220 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2221 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2222 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2223 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2224 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2225 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2226 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2227 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2228 2229 #address-cells = <2>; 2230 #size-cells = <0>; 2231 #sound-dai-cells = <1>; 2232 status = "disabled"; 2233 }; 2234 2235 txmacro: codec@3220000 { 2236 compatible = "qcom,sm8450-lpass-tx-macro"; 2237 reg = <0 0x03220000 0 0x1000>; 2238 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2239 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2240 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2241 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2242 <&vamacro>; 2243 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2244 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2245 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2246 assigned-clock-rates = <19200000>, <19200000>; 2247 2248 #clock-cells = <0>; 2249 clock-output-names = "mclk"; 2250 pinctrl-names = "default"; 2251 pinctrl-0 = <&tx_swr_active>; 2252 #sound-dai-cells = <1>; 2253 }; 2254 2255 wsamacro: codec@3240000 { 2256 compatible = "qcom,sm8450-lpass-wsa-macro"; 2257 reg = <0 0x03240000 0 0x1000>; 2258 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2259 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2260 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&vamacro>; 2263 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2264 2265 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2266 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2267 assigned-clock-rates = <19200000>, <19200000>; 2268 2269 #clock-cells = <0>; 2270 clock-output-names = "mclk"; 2271 pinctrl-names = "default"; 2272 pinctrl-0 = <&wsa_swr_active>; 2273 #sound-dai-cells = <1>; 2274 }; 2275 2276 /* WSA */ 2277 swr0: soundwire-controller@3250000 { 2278 compatible = "qcom,soundwire-v1.7.0"; 2279 reg = <0 0x03250000 0 0x2000>; 2280 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2281 clocks = <&wsamacro>; 2282 clock-names = "iface"; 2283 2284 qcom,din-ports = <2>; 2285 qcom,dout-ports = <6>; 2286 2287 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2288 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2289 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2290 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2291 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2292 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2293 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2294 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2295 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2296 2297 #address-cells = <2>; 2298 #size-cells = <0>; 2299 #sound-dai-cells = <1>; 2300 status = "disabled"; 2301 }; 2302 2303 swr2: soundwire-controller@33b0000 { 2304 compatible = "qcom,soundwire-v1.7.0"; 2305 reg = <0 0x033b0000 0 0x2000>; 2306 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2307 <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2308 interrupt-names = "core", "wakeup"; 2309 2310 clocks = <&vamacro>; 2311 clock-names = "iface"; 2312 label = "TX"; 2313 2314 qcom,din-ports = <4>; 2315 qcom,dout-ports = <0>; 2316 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2317 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2318 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2319 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2320 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2321 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2322 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2323 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2324 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2325 2326 #address-cells = <2>; 2327 #size-cells = <0>; 2328 #sound-dai-cells = <1>; 2329 status = "disabled"; 2330 }; 2331 2332 vamacro: codec@33f0000 { 2333 compatible = "qcom,sm8450-lpass-va-macro"; 2334 reg = <0 0x033f0000 0 0x1000>; 2335 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2336 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2337 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2338 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2339 clock-names = "mclk", "macro", "dcodec", "npl"; 2340 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2341 assigned-clock-rates = <19200000>; 2342 2343 #clock-cells = <0>; 2344 clock-output-names = "fsgen"; 2345 #sound-dai-cells = <1>; 2346 status = "disabled"; 2347 }; 2348 2349 remoteproc_adsp: remoteproc@30000000 { 2350 compatible = "qcom,sm8450-adsp-pas"; 2351 reg = <0 0x30000000 0 0x100>; 2352 2353 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2354 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2355 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2356 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2357 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2358 interrupt-names = "wdog", "fatal", "ready", 2359 "handover", "stop-ack"; 2360 2361 clocks = <&rpmhcc RPMH_CXO_CLK>; 2362 clock-names = "xo"; 2363 2364 power-domains = <&rpmhpd SM8450_LCX>, 2365 <&rpmhpd SM8450_LMX>; 2366 power-domain-names = "lcx", "lmx"; 2367 2368 memory-region = <&adsp_mem>; 2369 2370 qcom,qmp = <&aoss_qmp>; 2371 2372 qcom,smem-states = <&smp2p_adsp_out 0>; 2373 qcom,smem-state-names = "stop"; 2374 2375 status = "disabled"; 2376 2377 remoteproc_adsp_glink: glink-edge { 2378 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2379 IPCC_MPROC_SIGNAL_GLINK_QMP 2380 IRQ_TYPE_EDGE_RISING>; 2381 mboxes = <&ipcc IPCC_CLIENT_LPASS 2382 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2383 2384 label = "lpass"; 2385 qcom,remote-pid = <2>; 2386 2387 gpr { 2388 compatible = "qcom,gpr"; 2389 qcom,glink-channels = "adsp_apps"; 2390 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2391 qcom,intents = <512 20>; 2392 #address-cells = <1>; 2393 #size-cells = <0>; 2394 2395 q6apm: service@1 { 2396 compatible = "qcom,q6apm"; 2397 reg = <GPR_APM_MODULE_IID>; 2398 #sound-dai-cells = <0>; 2399 qcom,protection-domain = "avs/audio", 2400 "msm/adsp/audio_pd"; 2401 2402 q6apmdai: dais { 2403 compatible = "qcom,q6apm-dais"; 2404 iommus = <&apps_smmu 0x1801 0x0>; 2405 }; 2406 2407 q6apmbedai: bedais { 2408 compatible = "qcom,q6apm-lpass-dais"; 2409 #sound-dai-cells = <1>; 2410 }; 2411 }; 2412 2413 q6prm: service@2 { 2414 compatible = "qcom,q6prm"; 2415 reg = <GPR_PRM_MODULE_IID>; 2416 qcom,protection-domain = "avs/audio", 2417 "msm/adsp/audio_pd"; 2418 2419 q6prmcc: clock-controller { 2420 compatible = "qcom,q6prm-lpass-clocks"; 2421 #clock-cells = <2>; 2422 }; 2423 }; 2424 }; 2425 2426 fastrpc { 2427 compatible = "qcom,fastrpc"; 2428 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2429 label = "adsp"; 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 compute-cb@3 { 2434 compatible = "qcom,fastrpc-compute-cb"; 2435 reg = <3>; 2436 iommus = <&apps_smmu 0x1803 0x0>; 2437 }; 2438 2439 compute-cb@4 { 2440 compatible = "qcom,fastrpc-compute-cb"; 2441 reg = <4>; 2442 iommus = <&apps_smmu 0x1804 0x0>; 2443 }; 2444 2445 compute-cb@5 { 2446 compatible = "qcom,fastrpc-compute-cb"; 2447 reg = <5>; 2448 iommus = <&apps_smmu 0x1805 0x0>; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 remoteproc_cdsp: remoteproc@32300000 { 2455 compatible = "qcom,sm8450-cdsp-pas"; 2456 reg = <0 0x32300000 0 0x1400000>; 2457 2458 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2459 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2460 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2461 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2462 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2463 interrupt-names = "wdog", "fatal", "ready", 2464 "handover", "stop-ack"; 2465 2466 clocks = <&rpmhcc RPMH_CXO_CLK>; 2467 clock-names = "xo"; 2468 2469 power-domains = <&rpmhpd SM8450_CX>, 2470 <&rpmhpd SM8450_MXC>; 2471 power-domain-names = "cx", "mxc"; 2472 2473 memory-region = <&cdsp_mem>; 2474 2475 qcom,qmp = <&aoss_qmp>; 2476 2477 qcom,smem-states = <&smp2p_cdsp_out 0>; 2478 qcom,smem-state-names = "stop"; 2479 2480 status = "disabled"; 2481 2482 glink-edge { 2483 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2484 IPCC_MPROC_SIGNAL_GLINK_QMP 2485 IRQ_TYPE_EDGE_RISING>; 2486 mboxes = <&ipcc IPCC_CLIENT_CDSP 2487 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2488 2489 label = "cdsp"; 2490 qcom,remote-pid = <5>; 2491 2492 fastrpc { 2493 compatible = "qcom,fastrpc"; 2494 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2495 label = "cdsp"; 2496 #address-cells = <1>; 2497 #size-cells = <0>; 2498 2499 compute-cb@1 { 2500 compatible = "qcom,fastrpc-compute-cb"; 2501 reg = <1>; 2502 iommus = <&apps_smmu 0x2161 0x0400>, 2503 <&apps_smmu 0x1021 0x1420>; 2504 }; 2505 2506 compute-cb@2 { 2507 compatible = "qcom,fastrpc-compute-cb"; 2508 reg = <2>; 2509 iommus = <&apps_smmu 0x2162 0x0400>, 2510 <&apps_smmu 0x1022 0x1420>; 2511 }; 2512 2513 compute-cb@3 { 2514 compatible = "qcom,fastrpc-compute-cb"; 2515 reg = <3>; 2516 iommus = <&apps_smmu 0x2163 0x0400>, 2517 <&apps_smmu 0x1023 0x1420>; 2518 }; 2519 2520 compute-cb@4 { 2521 compatible = "qcom,fastrpc-compute-cb"; 2522 reg = <4>; 2523 iommus = <&apps_smmu 0x2164 0x0400>, 2524 <&apps_smmu 0x1024 0x1420>; 2525 }; 2526 2527 compute-cb@5 { 2528 compatible = "qcom,fastrpc-compute-cb"; 2529 reg = <5>; 2530 iommus = <&apps_smmu 0x2165 0x0400>, 2531 <&apps_smmu 0x1025 0x1420>; 2532 }; 2533 2534 compute-cb@6 { 2535 compatible = "qcom,fastrpc-compute-cb"; 2536 reg = <6>; 2537 iommus = <&apps_smmu 0x2166 0x0400>, 2538 <&apps_smmu 0x1026 0x1420>; 2539 }; 2540 2541 compute-cb@7 { 2542 compatible = "qcom,fastrpc-compute-cb"; 2543 reg = <7>; 2544 iommus = <&apps_smmu 0x2167 0x0400>, 2545 <&apps_smmu 0x1027 0x1420>; 2546 }; 2547 2548 compute-cb@8 { 2549 compatible = "qcom,fastrpc-compute-cb"; 2550 reg = <8>; 2551 iommus = <&apps_smmu 0x2168 0x0400>, 2552 <&apps_smmu 0x1028 0x1420>; 2553 }; 2554 2555 /* note: secure cb9 in downstream */ 2556 }; 2557 }; 2558 }; 2559 2560 remoteproc_mpss: remoteproc@4080000 { 2561 compatible = "qcom,sm8450-mpss-pas"; 2562 reg = <0x0 0x04080000 0x0 0x4040>; 2563 2564 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2565 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2566 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2567 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2568 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2569 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2570 interrupt-names = "wdog", "fatal", "ready", "handover", 2571 "stop-ack", "shutdown-ack"; 2572 2573 clocks = <&rpmhcc RPMH_CXO_CLK>; 2574 clock-names = "xo"; 2575 2576 power-domains = <&rpmhpd SM8450_CX>, 2577 <&rpmhpd SM8450_MSS>; 2578 power-domain-names = "cx", "mss"; 2579 2580 memory-region = <&mpss_mem>; 2581 2582 qcom,qmp = <&aoss_qmp>; 2583 2584 qcom,smem-states = <&smp2p_modem_out 0>; 2585 qcom,smem-state-names = "stop"; 2586 2587 status = "disabled"; 2588 2589 glink-edge { 2590 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2591 IPCC_MPROC_SIGNAL_GLINK_QMP 2592 IRQ_TYPE_EDGE_RISING>; 2593 mboxes = <&ipcc IPCC_CLIENT_MPSS 2594 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2595 label = "modem"; 2596 qcom,remote-pid = <1>; 2597 }; 2598 }; 2599 2600 cci0: cci@ac15000 { 2601 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2602 reg = <0 0x0ac15000 0 0x1000>; 2603 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2604 power-domains = <&camcc TITAN_TOP_GDSC>; 2605 2606 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2607 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2608 <&camcc CAM_CC_CPAS_AHB_CLK>, 2609 <&camcc CAM_CC_CCI_0_CLK>, 2610 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2611 clock-names = "camnoc_axi", 2612 "slow_ahb_src", 2613 "cpas_ahb", 2614 "cci", 2615 "cci_src"; 2616 pinctrl-0 = <&cci0_default &cci1_default>; 2617 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2618 pinctrl-names = "default", "sleep"; 2619 2620 status = "disabled"; 2621 #address-cells = <1>; 2622 #size-cells = <0>; 2623 2624 cci0_i2c0: i2c-bus@0 { 2625 reg = <0>; 2626 clock-frequency = <1000000>; 2627 #address-cells = <1>; 2628 #size-cells = <0>; 2629 }; 2630 2631 cci0_i2c1: i2c-bus@1 { 2632 reg = <1>; 2633 clock-frequency = <1000000>; 2634 #address-cells = <1>; 2635 #size-cells = <0>; 2636 }; 2637 }; 2638 2639 cci1: cci@ac16000 { 2640 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2641 reg = <0 0x0ac16000 0 0x1000>; 2642 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2643 power-domains = <&camcc TITAN_TOP_GDSC>; 2644 2645 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2646 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2647 <&camcc CAM_CC_CPAS_AHB_CLK>, 2648 <&camcc CAM_CC_CCI_1_CLK>, 2649 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2650 clock-names = "camnoc_axi", 2651 "slow_ahb_src", 2652 "cpas_ahb", 2653 "cci", 2654 "cci_src"; 2655 pinctrl-0 = <&cci2_default &cci3_default>; 2656 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2657 pinctrl-names = "default", "sleep"; 2658 2659 status = "disabled"; 2660 #address-cells = <1>; 2661 #size-cells = <0>; 2662 2663 cci1_i2c0: i2c-bus@0 { 2664 reg = <0>; 2665 clock-frequency = <1000000>; 2666 #address-cells = <1>; 2667 #size-cells = <0>; 2668 }; 2669 2670 cci1_i2c1: i2c-bus@1 { 2671 reg = <1>; 2672 clock-frequency = <1000000>; 2673 #address-cells = <1>; 2674 #size-cells = <0>; 2675 }; 2676 }; 2677 2678 camcc: clock-controller@ade0000 { 2679 compatible = "qcom,sm8450-camcc"; 2680 reg = <0 0x0ade0000 0 0x20000>; 2681 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2682 <&rpmhcc RPMH_CXO_CLK>, 2683 <&rpmhcc RPMH_CXO_CLK_A>, 2684 <&sleep_clk>; 2685 power-domains = <&rpmhpd SM8450_MMCX>; 2686 required-opps = <&rpmhpd_opp_low_svs>; 2687 #clock-cells = <1>; 2688 #reset-cells = <1>; 2689 #power-domain-cells = <1>; 2690 status = "disabled"; 2691 }; 2692 2693 mdss: display-subsystem@ae00000 { 2694 compatible = "qcom,sm8450-mdss"; 2695 reg = <0 0x0ae00000 0 0x1000>; 2696 reg-names = "mdss"; 2697 2698 /* same path used twice */ 2699 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2700 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; 2701 interconnect-names = "mdp0-mem", "mdp1-mem"; 2702 2703 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2704 2705 power-domains = <&dispcc MDSS_GDSC>; 2706 2707 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2708 <&gcc GCC_DISP_HF_AXI_CLK>, 2709 <&gcc GCC_DISP_SF_AXI_CLK>, 2710 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2711 2712 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2713 interrupt-controller; 2714 #interrupt-cells = <1>; 2715 2716 iommus = <&apps_smmu 0x2800 0x402>; 2717 2718 #address-cells = <2>; 2719 #size-cells = <2>; 2720 ranges; 2721 2722 status = "disabled"; 2723 2724 mdss_mdp: display-controller@ae01000 { 2725 compatible = "qcom,sm8450-dpu"; 2726 reg = <0 0x0ae01000 0 0x8f000>, 2727 <0 0x0aeb0000 0 0x2008>; 2728 reg-names = "mdp", "vbif"; 2729 2730 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2731 <&gcc GCC_DISP_SF_AXI_CLK>, 2732 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2733 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2734 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2735 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2736 clock-names = "bus", 2737 "nrt_bus", 2738 "iface", 2739 "lut", 2740 "core", 2741 "vsync"; 2742 2743 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2744 assigned-clock-rates = <19200000>; 2745 2746 operating-points-v2 = <&mdp_opp_table>; 2747 power-domains = <&rpmhpd SM8450_MMCX>; 2748 2749 interrupt-parent = <&mdss>; 2750 interrupts = <0>; 2751 2752 ports { 2753 #address-cells = <1>; 2754 #size-cells = <0>; 2755 2756 port@0 { 2757 reg = <0>; 2758 dpu_intf1_out: endpoint { 2759 remote-endpoint = <&mdss_dsi0_in>; 2760 }; 2761 }; 2762 2763 port@1 { 2764 reg = <1>; 2765 dpu_intf2_out: endpoint { 2766 remote-endpoint = <&mdss_dsi1_in>; 2767 }; 2768 }; 2769 2770 }; 2771 2772 mdp_opp_table: opp-table { 2773 compatible = "operating-points-v2"; 2774 2775 opp-172000000 { 2776 opp-hz = /bits/ 64 <172000000>; 2777 required-opps = <&rpmhpd_opp_low_svs_d1>; 2778 }; 2779 2780 opp-200000000 { 2781 opp-hz = /bits/ 64 <200000000>; 2782 required-opps = <&rpmhpd_opp_low_svs>; 2783 }; 2784 2785 opp-325000000 { 2786 opp-hz = /bits/ 64 <325000000>; 2787 required-opps = <&rpmhpd_opp_svs>; 2788 }; 2789 2790 opp-375000000 { 2791 opp-hz = /bits/ 64 <375000000>; 2792 required-opps = <&rpmhpd_opp_svs_l1>; 2793 }; 2794 2795 opp-500000000 { 2796 opp-hz = /bits/ 64 <500000000>; 2797 required-opps = <&rpmhpd_opp_nom>; 2798 }; 2799 }; 2800 }; 2801 2802 mdss_dsi0: dsi@ae94000 { 2803 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2804 reg = <0 0x0ae94000 0 0x400>; 2805 reg-names = "dsi_ctrl"; 2806 2807 interrupt-parent = <&mdss>; 2808 interrupts = <4>; 2809 2810 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2811 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2812 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2813 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2814 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2815 <&gcc GCC_DISP_HF_AXI_CLK>; 2816 clock-names = "byte", 2817 "byte_intf", 2818 "pixel", 2819 "core", 2820 "iface", 2821 "bus"; 2822 2823 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2824 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2825 2826 operating-points-v2 = <&mdss_dsi_opp_table>; 2827 power-domains = <&rpmhpd SM8450_MMCX>; 2828 2829 phys = <&mdss_dsi0_phy>; 2830 phy-names = "dsi"; 2831 2832 #address-cells = <1>; 2833 #size-cells = <0>; 2834 2835 status = "disabled"; 2836 2837 ports { 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 port@0 { 2842 reg = <0>; 2843 mdss_dsi0_in: endpoint { 2844 remote-endpoint = <&dpu_intf1_out>; 2845 }; 2846 }; 2847 2848 port@1 { 2849 reg = <1>; 2850 mdss_dsi0_out: endpoint { 2851 }; 2852 }; 2853 }; 2854 2855 mdss_dsi_opp_table: opp-table { 2856 compatible = "operating-points-v2"; 2857 2858 opp-187500000 { 2859 opp-hz = /bits/ 64 <187500000>; 2860 required-opps = <&rpmhpd_opp_low_svs>; 2861 }; 2862 2863 opp-300000000 { 2864 opp-hz = /bits/ 64 <300000000>; 2865 required-opps = <&rpmhpd_opp_svs>; 2866 }; 2867 2868 opp-358000000 { 2869 opp-hz = /bits/ 64 <358000000>; 2870 required-opps = <&rpmhpd_opp_svs_l1>; 2871 }; 2872 }; 2873 }; 2874 2875 mdss_dsi0_phy: phy@ae94400 { 2876 compatible = "qcom,dsi-phy-5nm-8450"; 2877 reg = <0 0x0ae94400 0 0x200>, 2878 <0 0x0ae94600 0 0x280>, 2879 <0 0x0ae94900 0 0x260>; 2880 reg-names = "dsi_phy", 2881 "dsi_phy_lane", 2882 "dsi_pll"; 2883 2884 #clock-cells = <1>; 2885 #phy-cells = <0>; 2886 2887 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2888 <&rpmhcc RPMH_CXO_CLK>; 2889 clock-names = "iface", "ref"; 2890 2891 status = "disabled"; 2892 }; 2893 2894 mdss_dsi1: dsi@ae96000 { 2895 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2896 reg = <0 0x0ae96000 0 0x400>; 2897 reg-names = "dsi_ctrl"; 2898 2899 interrupt-parent = <&mdss>; 2900 interrupts = <5>; 2901 2902 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2903 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2904 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2905 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2906 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2907 <&gcc GCC_DISP_HF_AXI_CLK>; 2908 clock-names = "byte", 2909 "byte_intf", 2910 "pixel", 2911 "core", 2912 "iface", 2913 "bus"; 2914 2915 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2916 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2917 2918 operating-points-v2 = <&mdss_dsi_opp_table>; 2919 power-domains = <&rpmhpd SM8450_MMCX>; 2920 2921 phys = <&mdss_dsi1_phy>; 2922 phy-names = "dsi"; 2923 2924 #address-cells = <1>; 2925 #size-cells = <0>; 2926 2927 status = "disabled"; 2928 2929 ports { 2930 #address-cells = <1>; 2931 #size-cells = <0>; 2932 2933 port@0 { 2934 reg = <0>; 2935 mdss_dsi1_in: endpoint { 2936 remote-endpoint = <&dpu_intf2_out>; 2937 }; 2938 }; 2939 2940 port@1 { 2941 reg = <1>; 2942 mdss_dsi1_out: endpoint { 2943 }; 2944 }; 2945 }; 2946 }; 2947 2948 mdss_dsi1_phy: phy@ae96400 { 2949 compatible = "qcom,dsi-phy-5nm-8450"; 2950 reg = <0 0x0ae96400 0 0x200>, 2951 <0 0x0ae96600 0 0x280>, 2952 <0 0x0ae96900 0 0x260>; 2953 reg-names = "dsi_phy", 2954 "dsi_phy_lane", 2955 "dsi_pll"; 2956 2957 #clock-cells = <1>; 2958 #phy-cells = <0>; 2959 2960 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2961 <&rpmhcc RPMH_CXO_CLK>; 2962 clock-names = "iface", "ref"; 2963 2964 status = "disabled"; 2965 }; 2966 }; 2967 2968 dispcc: clock-controller@af00000 { 2969 compatible = "qcom,sm8450-dispcc"; 2970 reg = <0 0x0af00000 0 0x20000>; 2971 clocks = <&rpmhcc RPMH_CXO_CLK>, 2972 <&rpmhcc RPMH_CXO_CLK_A>, 2973 <&gcc GCC_DISP_AHB_CLK>, 2974 <&sleep_clk>, 2975 <&mdss_dsi0_phy 0>, 2976 <&mdss_dsi0_phy 1>, 2977 <&mdss_dsi1_phy 0>, 2978 <&mdss_dsi1_phy 1>, 2979 <0>, /* dp0 */ 2980 <0>, 2981 <0>, /* dp1 */ 2982 <0>, 2983 <0>, /* dp2 */ 2984 <0>, 2985 <0>, /* dp3 */ 2986 <0>; 2987 power-domains = <&rpmhpd SM8450_MMCX>; 2988 required-opps = <&rpmhpd_opp_low_svs>; 2989 #clock-cells = <1>; 2990 #reset-cells = <1>; 2991 #power-domain-cells = <1>; 2992 status = "disabled"; 2993 }; 2994 2995 pdc: interrupt-controller@b220000 { 2996 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 2997 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2998 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 2999 <94 609 31>, <125 63 1>, <126 716 12>; 3000 #interrupt-cells = <2>; 3001 interrupt-parent = <&intc>; 3002 interrupt-controller; 3003 }; 3004 3005 tsens0: thermal-sensor@c263000 { 3006 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3007 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3008 <0 0x0c222000 0 0x1000>; /* SROT */ 3009 #qcom,sensors = <16>; 3010 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3011 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3012 interrupt-names = "uplow", "critical"; 3013 #thermal-sensor-cells = <1>; 3014 }; 3015 3016 tsens1: thermal-sensor@c265000 { 3017 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3018 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3019 <0 0x0c223000 0 0x1000>; /* SROT */ 3020 #qcom,sensors = <16>; 3021 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3023 interrupt-names = "uplow", "critical"; 3024 #thermal-sensor-cells = <1>; 3025 }; 3026 3027 aoss_qmp: power-management@c300000 { 3028 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3029 reg = <0 0x0c300000 0 0x400>; 3030 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3031 IRQ_TYPE_EDGE_RISING>; 3032 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3033 3034 #clock-cells = <0>; 3035 }; 3036 3037 spmi_bus: spmi@c400000 { 3038 compatible = "qcom,spmi-pmic-arb"; 3039 reg = <0 0x0c400000 0 0x00003000>, 3040 <0 0x0c500000 0 0x00400000>, 3041 <0 0x0c440000 0 0x00080000>, 3042 <0 0x0c4c0000 0 0x00010000>, 3043 <0 0x0c42d000 0 0x00010000>; 3044 reg-names = "core", 3045 "chnls", 3046 "obsrvr", 3047 "intr", 3048 "cnfg"; 3049 interrupt-names = "periph_irq"; 3050 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3051 qcom,ee = <0>; 3052 qcom,channel = <0>; 3053 interrupt-controller; 3054 #interrupt-cells = <4>; 3055 #address-cells = <2>; 3056 #size-cells = <0>; 3057 }; 3058 3059 ipcc: mailbox@ed18000 { 3060 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3061 reg = <0 0x0ed18000 0 0x1000>; 3062 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3063 interrupt-controller; 3064 #interrupt-cells = <3>; 3065 #mbox-cells = <2>; 3066 }; 3067 3068 tlmm: pinctrl@f100000 { 3069 compatible = "qcom,sm8450-tlmm"; 3070 reg = <0 0x0f100000 0 0x300000>; 3071 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3072 gpio-controller; 3073 #gpio-cells = <2>; 3074 interrupt-controller; 3075 #interrupt-cells = <2>; 3076 gpio-ranges = <&tlmm 0 0 211>; 3077 wakeup-parent = <&pdc>; 3078 3079 sdc2_default_state: sdc2-default-state { 3080 clk-pins { 3081 pins = "sdc2_clk"; 3082 drive-strength = <16>; 3083 bias-disable; 3084 }; 3085 3086 cmd-pins { 3087 pins = "sdc2_cmd"; 3088 drive-strength = <16>; 3089 bias-pull-up; 3090 }; 3091 3092 data-pins { 3093 pins = "sdc2_data"; 3094 drive-strength = <16>; 3095 bias-pull-up; 3096 }; 3097 }; 3098 3099 sdc2_sleep_state: sdc2-sleep-state { 3100 clk-pins { 3101 pins = "sdc2_clk"; 3102 drive-strength = <2>; 3103 bias-disable; 3104 }; 3105 3106 cmd-pins { 3107 pins = "sdc2_cmd"; 3108 drive-strength = <2>; 3109 bias-pull-up; 3110 }; 3111 3112 data-pins { 3113 pins = "sdc2_data"; 3114 drive-strength = <2>; 3115 bias-pull-up; 3116 }; 3117 }; 3118 3119 cci0_default: cci0-default-state { 3120 /* SDA, SCL */ 3121 pins = "gpio110", "gpio111"; 3122 function = "cci_i2c"; 3123 drive-strength = <2>; 3124 bias-pull-up; 3125 }; 3126 3127 cci0_sleep: cci0-sleep-state { 3128 /* SDA, SCL */ 3129 pins = "gpio110", "gpio111"; 3130 function = "cci_i2c"; 3131 drive-strength = <2>; 3132 bias-pull-down; 3133 }; 3134 3135 cci1_default: cci1-default-state { 3136 /* SDA, SCL */ 3137 pins = "gpio112", "gpio113"; 3138 function = "cci_i2c"; 3139 drive-strength = <2>; 3140 bias-pull-up; 3141 }; 3142 3143 cci1_sleep: cci1-sleep-state { 3144 /* SDA, SCL */ 3145 pins = "gpio112", "gpio113"; 3146 function = "cci_i2c"; 3147 drive-strength = <2>; 3148 bias-pull-down; 3149 }; 3150 3151 cci2_default: cci2-default-state { 3152 /* SDA, SCL */ 3153 pins = "gpio114", "gpio115"; 3154 function = "cci_i2c"; 3155 drive-strength = <2>; 3156 bias-pull-up; 3157 }; 3158 3159 cci2_sleep: cci2-sleep-state { 3160 /* SDA, SCL */ 3161 pins = "gpio114", "gpio115"; 3162 function = "cci_i2c"; 3163 drive-strength = <2>; 3164 bias-pull-down; 3165 }; 3166 3167 cci3_default: cci3-default-state { 3168 /* SDA, SCL */ 3169 pins = "gpio208", "gpio209"; 3170 function = "cci_i2c"; 3171 drive-strength = <2>; 3172 bias-pull-up; 3173 }; 3174 3175 cci3_sleep: cci3-sleep-state { 3176 /* SDA, SCL */ 3177 pins = "gpio208", "gpio209"; 3178 function = "cci_i2c"; 3179 drive-strength = <2>; 3180 bias-pull-down; 3181 }; 3182 3183 pcie0_default_state: pcie0-default-state { 3184 perst-pins { 3185 pins = "gpio94"; 3186 function = "gpio"; 3187 drive-strength = <2>; 3188 bias-pull-down; 3189 }; 3190 3191 clkreq-pins { 3192 pins = "gpio95"; 3193 function = "pcie0_clkreqn"; 3194 drive-strength = <2>; 3195 bias-pull-up; 3196 }; 3197 3198 wake-pins { 3199 pins = "gpio96"; 3200 function = "gpio"; 3201 drive-strength = <2>; 3202 bias-pull-up; 3203 }; 3204 }; 3205 3206 pcie1_default_state: pcie1-default-state { 3207 perst-pins { 3208 pins = "gpio97"; 3209 function = "gpio"; 3210 drive-strength = <2>; 3211 bias-pull-down; 3212 }; 3213 3214 clkreq-pins { 3215 pins = "gpio98"; 3216 function = "pcie1_clkreqn"; 3217 drive-strength = <2>; 3218 bias-pull-up; 3219 }; 3220 3221 wake-pins { 3222 pins = "gpio99"; 3223 function = "gpio"; 3224 drive-strength = <2>; 3225 bias-pull-up; 3226 }; 3227 }; 3228 3229 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3230 pins = "gpio0", "gpio1"; 3231 function = "qup0"; 3232 }; 3233 3234 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3235 pins = "gpio4", "gpio5"; 3236 function = "qup1"; 3237 }; 3238 3239 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3240 pins = "gpio8", "gpio9"; 3241 function = "qup2"; 3242 }; 3243 3244 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3245 pins = "gpio12", "gpio13"; 3246 function = "qup3"; 3247 }; 3248 3249 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3250 pins = "gpio16", "gpio17"; 3251 function = "qup4"; 3252 }; 3253 3254 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3255 pins = "gpio206", "gpio207"; 3256 function = "qup5"; 3257 }; 3258 3259 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3260 pins = "gpio20", "gpio21"; 3261 function = "qup6"; 3262 }; 3263 3264 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3265 pins = "gpio28", "gpio29"; 3266 function = "qup8"; 3267 }; 3268 3269 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3270 pins = "gpio32", "gpio33"; 3271 function = "qup9"; 3272 }; 3273 3274 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3275 pins = "gpio36", "gpio37"; 3276 function = "qup10"; 3277 }; 3278 3279 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3280 pins = "gpio40", "gpio41"; 3281 function = "qup11"; 3282 }; 3283 3284 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3285 pins = "gpio44", "gpio45"; 3286 function = "qup12"; 3287 }; 3288 3289 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3290 pins = "gpio48", "gpio49"; 3291 function = "qup13"; 3292 drive-strength = <2>; 3293 bias-pull-up; 3294 }; 3295 3296 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3297 pins = "gpio52", "gpio53"; 3298 function = "qup14"; 3299 drive-strength = <2>; 3300 bias-pull-up; 3301 }; 3302 3303 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3304 pins = "gpio56", "gpio57"; 3305 function = "qup15"; 3306 }; 3307 3308 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3309 pins = "gpio60", "gpio61"; 3310 function = "qup16"; 3311 }; 3312 3313 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3314 pins = "gpio64", "gpio65"; 3315 function = "qup17"; 3316 }; 3317 3318 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3319 pins = "gpio68", "gpio69"; 3320 function = "qup18"; 3321 }; 3322 3323 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3324 pins = "gpio72", "gpio73"; 3325 function = "qup19"; 3326 }; 3327 3328 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3329 pins = "gpio76", "gpio77"; 3330 function = "qup20"; 3331 }; 3332 3333 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3334 pins = "gpio80", "gpio81"; 3335 function = "qup21"; 3336 }; 3337 3338 qup_spi0_cs: qup-spi0-cs-state { 3339 pins = "gpio3"; 3340 function = "qup0"; 3341 }; 3342 3343 qup_spi0_data_clk: qup-spi0-data-clk-state { 3344 pins = "gpio0", "gpio1", "gpio2"; 3345 function = "qup0"; 3346 }; 3347 3348 qup_spi1_cs: qup-spi1-cs-state { 3349 pins = "gpio7"; 3350 function = "qup1"; 3351 }; 3352 3353 qup_spi1_data_clk: qup-spi1-data-clk-state { 3354 pins = "gpio4", "gpio5", "gpio6"; 3355 function = "qup1"; 3356 }; 3357 3358 qup_spi2_cs: qup-spi2-cs-state { 3359 pins = "gpio11"; 3360 function = "qup2"; 3361 }; 3362 3363 qup_spi2_data_clk: qup-spi2-data-clk-state { 3364 pins = "gpio8", "gpio9", "gpio10"; 3365 function = "qup2"; 3366 }; 3367 3368 qup_spi3_cs: qup-spi3-cs-state { 3369 pins = "gpio15"; 3370 function = "qup3"; 3371 }; 3372 3373 qup_spi3_data_clk: qup-spi3-data-clk-state { 3374 pins = "gpio12", "gpio13", "gpio14"; 3375 function = "qup3"; 3376 }; 3377 3378 qup_spi4_cs: qup-spi4-cs-state { 3379 pins = "gpio19"; 3380 function = "qup4"; 3381 drive-strength = <6>; 3382 bias-disable; 3383 }; 3384 3385 qup_spi4_data_clk: qup-spi4-data-clk-state { 3386 pins = "gpio16", "gpio17", "gpio18"; 3387 function = "qup4"; 3388 }; 3389 3390 qup_spi5_cs: qup-spi5-cs-state { 3391 pins = "gpio85"; 3392 function = "qup5"; 3393 }; 3394 3395 qup_spi5_data_clk: qup-spi5-data-clk-state { 3396 pins = "gpio206", "gpio207", "gpio84"; 3397 function = "qup5"; 3398 }; 3399 3400 qup_spi6_cs: qup-spi6-cs-state { 3401 pins = "gpio23"; 3402 function = "qup6"; 3403 }; 3404 3405 qup_spi6_data_clk: qup-spi6-data-clk-state { 3406 pins = "gpio20", "gpio21", "gpio22"; 3407 function = "qup6"; 3408 }; 3409 3410 qup_spi8_cs: qup-spi8-cs-state { 3411 pins = "gpio31"; 3412 function = "qup8"; 3413 }; 3414 3415 qup_spi8_data_clk: qup-spi8-data-clk-state { 3416 pins = "gpio28", "gpio29", "gpio30"; 3417 function = "qup8"; 3418 }; 3419 3420 qup_spi9_cs: qup-spi9-cs-state { 3421 pins = "gpio35"; 3422 function = "qup9"; 3423 }; 3424 3425 qup_spi9_data_clk: qup-spi9-data-clk-state { 3426 pins = "gpio32", "gpio33", "gpio34"; 3427 function = "qup9"; 3428 }; 3429 3430 qup_spi10_cs: qup-spi10-cs-state { 3431 pins = "gpio39"; 3432 function = "qup10"; 3433 }; 3434 3435 qup_spi10_data_clk: qup-spi10-data-clk-state { 3436 pins = "gpio36", "gpio37", "gpio38"; 3437 function = "qup10"; 3438 }; 3439 3440 qup_spi11_cs: qup-spi11-cs-state { 3441 pins = "gpio43"; 3442 function = "qup11"; 3443 }; 3444 3445 qup_spi11_data_clk: qup-spi11-data-clk-state { 3446 pins = "gpio40", "gpio41", "gpio42"; 3447 function = "qup11"; 3448 }; 3449 3450 qup_spi12_cs: qup-spi12-cs-state { 3451 pins = "gpio47"; 3452 function = "qup12"; 3453 }; 3454 3455 qup_spi12_data_clk: qup-spi12-data-clk-state { 3456 pins = "gpio44", "gpio45", "gpio46"; 3457 function = "qup12"; 3458 }; 3459 3460 qup_spi13_cs: qup-spi13-cs-state { 3461 pins = "gpio51"; 3462 function = "qup13"; 3463 }; 3464 3465 qup_spi13_data_clk: qup-spi13-data-clk-state { 3466 pins = "gpio48", "gpio49", "gpio50"; 3467 function = "qup13"; 3468 }; 3469 3470 qup_spi14_cs: qup-spi14-cs-state { 3471 pins = "gpio55"; 3472 function = "qup14"; 3473 }; 3474 3475 qup_spi14_data_clk: qup-spi14-data-clk-state { 3476 pins = "gpio52", "gpio53", "gpio54"; 3477 function = "qup14"; 3478 }; 3479 3480 qup_spi15_cs: qup-spi15-cs-state { 3481 pins = "gpio59"; 3482 function = "qup15"; 3483 }; 3484 3485 qup_spi15_data_clk: qup-spi15-data-clk-state { 3486 pins = "gpio56", "gpio57", "gpio58"; 3487 function = "qup15"; 3488 }; 3489 3490 qup_spi16_cs: qup-spi16-cs-state { 3491 pins = "gpio63"; 3492 function = "qup16"; 3493 }; 3494 3495 qup_spi16_data_clk: qup-spi16-data-clk-state { 3496 pins = "gpio60", "gpio61", "gpio62"; 3497 function = "qup16"; 3498 }; 3499 3500 qup_spi17_cs: qup-spi17-cs-state { 3501 pins = "gpio67"; 3502 function = "qup17"; 3503 }; 3504 3505 qup_spi17_data_clk: qup-spi17-data-clk-state { 3506 pins = "gpio64", "gpio65", "gpio66"; 3507 function = "qup17"; 3508 }; 3509 3510 qup_spi18_cs: qup-spi18-cs-state { 3511 pins = "gpio71"; 3512 function = "qup18"; 3513 drive-strength = <6>; 3514 bias-disable; 3515 }; 3516 3517 qup_spi18_data_clk: qup-spi18-data-clk-state { 3518 pins = "gpio68", "gpio69", "gpio70"; 3519 function = "qup18"; 3520 drive-strength = <6>; 3521 bias-disable; 3522 }; 3523 3524 qup_spi19_cs: qup-spi19-cs-state { 3525 pins = "gpio75"; 3526 function = "qup19"; 3527 drive-strength = <6>; 3528 bias-disable; 3529 }; 3530 3531 qup_spi19_data_clk: qup-spi19-data-clk-state { 3532 pins = "gpio72", "gpio73", "gpio74"; 3533 function = "qup19"; 3534 drive-strength = <6>; 3535 bias-disable; 3536 }; 3537 3538 qup_spi20_cs: qup-spi20-cs-state { 3539 pins = "gpio79"; 3540 function = "qup20"; 3541 }; 3542 3543 qup_spi20_data_clk: qup-spi20-data-clk-state { 3544 pins = "gpio76", "gpio77", "gpio78"; 3545 function = "qup20"; 3546 }; 3547 3548 qup_spi21_cs: qup-spi21-cs-state { 3549 pins = "gpio83"; 3550 function = "qup21"; 3551 }; 3552 3553 qup_spi21_data_clk: qup-spi21-data-clk-state { 3554 pins = "gpio80", "gpio81", "gpio82"; 3555 function = "qup21"; 3556 }; 3557 3558 qup_uart7_rx: qup-uart7-rx-state { 3559 pins = "gpio26"; 3560 function = "qup7"; 3561 drive-strength = <2>; 3562 bias-disable; 3563 }; 3564 3565 qup_uart7_tx: qup-uart7-tx-state { 3566 pins = "gpio27"; 3567 function = "qup7"; 3568 drive-strength = <2>; 3569 bias-disable; 3570 }; 3571 3572 qup_uart20_default: qup-uart20-default-state { 3573 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3574 function = "qup20"; 3575 }; 3576 3577 }; 3578 3579 lpass_tlmm: pinctrl@3440000 { 3580 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3581 reg = <0 0x03440000 0x0 0x20000>, 3582 <0 0x034d0000 0x0 0x10000>; 3583 gpio-controller; 3584 #gpio-cells = <2>; 3585 gpio-ranges = <&lpass_tlmm 0 0 23>; 3586 3587 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3588 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3589 clock-names = "core", "audio"; 3590 3591 tx_swr_active: tx-swr-active-state { 3592 clk-pins { 3593 pins = "gpio0"; 3594 function = "swr_tx_clk"; 3595 drive-strength = <2>; 3596 slew-rate = <1>; 3597 bias-disable; 3598 }; 3599 3600 data-pins { 3601 pins = "gpio1", "gpio2", "gpio14"; 3602 function = "swr_tx_data"; 3603 drive-strength = <2>; 3604 slew-rate = <1>; 3605 bias-bus-hold; 3606 }; 3607 }; 3608 3609 rx_swr_active: rx-swr-active-state { 3610 clk-pins { 3611 pins = "gpio3"; 3612 function = "swr_rx_clk"; 3613 drive-strength = <2>; 3614 slew-rate = <1>; 3615 bias-disable; 3616 }; 3617 3618 data-pins { 3619 pins = "gpio4", "gpio5"; 3620 function = "swr_rx_data"; 3621 drive-strength = <2>; 3622 slew-rate = <1>; 3623 bias-bus-hold; 3624 }; 3625 }; 3626 3627 dmic01_default: dmic01-default-state { 3628 clk-pins { 3629 pins = "gpio6"; 3630 function = "dmic1_clk"; 3631 drive-strength = <8>; 3632 output-high; 3633 }; 3634 3635 data-pins { 3636 pins = "gpio7"; 3637 function = "dmic1_data"; 3638 drive-strength = <8>; 3639 input-enable; 3640 }; 3641 }; 3642 3643 dmic02_default: dmic02-default-state { 3644 clk-pins { 3645 pins = "gpio8"; 3646 function = "dmic2_clk"; 3647 drive-strength = <8>; 3648 output-high; 3649 }; 3650 3651 data-pins { 3652 pins = "gpio9"; 3653 function = "dmic2_data"; 3654 drive-strength = <8>; 3655 input-enable; 3656 }; 3657 }; 3658 3659 wsa_swr_active: wsa-swr-active-state { 3660 clk-pins { 3661 pins = "gpio10"; 3662 function = "wsa_swr_clk"; 3663 drive-strength = <2>; 3664 slew-rate = <1>; 3665 bias-disable; 3666 }; 3667 3668 data-pins { 3669 pins = "gpio11"; 3670 function = "wsa_swr_data"; 3671 drive-strength = <2>; 3672 slew-rate = <1>; 3673 bias-bus-hold; 3674 }; 3675 }; 3676 3677 wsa2_swr_active: wsa2-swr-active-state { 3678 clk-pins { 3679 pins = "gpio15"; 3680 function = "wsa2_swr_clk"; 3681 drive-strength = <2>; 3682 slew-rate = <1>; 3683 bias-disable; 3684 }; 3685 3686 data-pins { 3687 pins = "gpio16"; 3688 function = "wsa2_swr_data"; 3689 drive-strength = <2>; 3690 slew-rate = <1>; 3691 bias-bus-hold; 3692 }; 3693 }; 3694 }; 3695 3696 apps_smmu: iommu@15000000 { 3697 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3698 reg = <0 0x15000000 0 0x100000>; 3699 #iommu-cells = <2>; 3700 #global-interrupts = <1>; 3701 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3798 }; 3799 3800 intc: interrupt-controller@17100000 { 3801 compatible = "arm,gic-v3"; 3802 #interrupt-cells = <3>; 3803 interrupt-controller; 3804 #redistributor-regions = <1>; 3805 redistributor-stride = <0x0 0x40000>; 3806 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3807 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3808 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3809 #address-cells = <2>; 3810 #size-cells = <2>; 3811 ranges; 3812 3813 gic_its: msi-controller@17140000 { 3814 compatible = "arm,gic-v3-its"; 3815 reg = <0x0 0x17140000 0x0 0x20000>; 3816 msi-controller; 3817 #msi-cells = <1>; 3818 }; 3819 }; 3820 3821 timer@17420000 { 3822 compatible = "arm,armv7-timer-mem"; 3823 #address-cells = <1>; 3824 #size-cells = <1>; 3825 ranges = <0 0 0 0x20000000>; 3826 reg = <0x0 0x17420000 0x0 0x1000>; 3827 clock-frequency = <19200000>; 3828 3829 frame@17421000 { 3830 frame-number = <0>; 3831 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3833 reg = <0x17421000 0x1000>, 3834 <0x17422000 0x1000>; 3835 }; 3836 3837 frame@17423000 { 3838 frame-number = <1>; 3839 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3840 reg = <0x17423000 0x1000>; 3841 status = "disabled"; 3842 }; 3843 3844 frame@17425000 { 3845 frame-number = <2>; 3846 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3847 reg = <0x17425000 0x1000>; 3848 status = "disabled"; 3849 }; 3850 3851 frame@17427000 { 3852 frame-number = <3>; 3853 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3854 reg = <0x17427000 0x1000>; 3855 status = "disabled"; 3856 }; 3857 3858 frame@17429000 { 3859 frame-number = <4>; 3860 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3861 reg = <0x17429000 0x1000>; 3862 status = "disabled"; 3863 }; 3864 3865 frame@1742b000 { 3866 frame-number = <5>; 3867 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3868 reg = <0x1742b000 0x1000>; 3869 status = "disabled"; 3870 }; 3871 3872 frame@1742d000 { 3873 frame-number = <6>; 3874 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3875 reg = <0x1742d000 0x1000>; 3876 status = "disabled"; 3877 }; 3878 }; 3879 3880 apps_rsc: rsc@17a00000 { 3881 label = "apps_rsc"; 3882 compatible = "qcom,rpmh-rsc"; 3883 reg = <0x0 0x17a00000 0x0 0x10000>, 3884 <0x0 0x17a10000 0x0 0x10000>, 3885 <0x0 0x17a20000 0x0 0x10000>, 3886 <0x0 0x17a30000 0x0 0x10000>; 3887 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3888 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3891 qcom,tcs-offset = <0xd00>; 3892 qcom,drv-id = <2>; 3893 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3894 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3895 power-domains = <&CLUSTER_PD>; 3896 3897 apps_bcm_voter: bcm-voter { 3898 compatible = "qcom,bcm-voter"; 3899 }; 3900 3901 rpmhcc: clock-controller { 3902 compatible = "qcom,sm8450-rpmh-clk"; 3903 #clock-cells = <1>; 3904 clock-names = "xo"; 3905 clocks = <&xo_board>; 3906 }; 3907 3908 rpmhpd: power-controller { 3909 compatible = "qcom,sm8450-rpmhpd"; 3910 #power-domain-cells = <1>; 3911 operating-points-v2 = <&rpmhpd_opp_table>; 3912 3913 rpmhpd_opp_table: opp-table { 3914 compatible = "operating-points-v2"; 3915 3916 rpmhpd_opp_ret: opp1 { 3917 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3918 }; 3919 3920 rpmhpd_opp_min_svs: opp2 { 3921 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3922 }; 3923 3924 rpmhpd_opp_low_svs_d1: opp3 { 3925 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3926 }; 3927 3928 rpmhpd_opp_low_svs: opp4 { 3929 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3930 }; 3931 3932 rpmhpd_opp_svs: opp5 { 3933 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3934 }; 3935 3936 rpmhpd_opp_svs_l1: opp6 { 3937 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3938 }; 3939 3940 rpmhpd_opp_nom: opp7 { 3941 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3942 }; 3943 3944 rpmhpd_opp_nom_l1: opp8 { 3945 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3946 }; 3947 3948 rpmhpd_opp_nom_l2: opp9 { 3949 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3950 }; 3951 3952 rpmhpd_opp_turbo: opp10 { 3953 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3954 }; 3955 3956 rpmhpd_opp_turbo_l1: opp11 { 3957 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3958 }; 3959 }; 3960 }; 3961 }; 3962 3963 cpufreq_hw: cpufreq@17d91000 { 3964 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 3965 reg = <0 0x17d91000 0 0x1000>, 3966 <0 0x17d92000 0 0x1000>, 3967 <0 0x17d93000 0 0x1000>; 3968 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3969 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3970 clock-names = "xo", "alternate"; 3971 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3974 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3975 #freq-domain-cells = <1>; 3976 #clock-cells = <1>; 3977 }; 3978 3979 gem_noc: interconnect@19100000 { 3980 compatible = "qcom,sm8450-gem-noc"; 3981 reg = <0 0x19100000 0 0xbb800>; 3982 #interconnect-cells = <2>; 3983 qcom,bcm-voters = <&apps_bcm_voter>; 3984 }; 3985 3986 system-cache-controller@19200000 { 3987 compatible = "qcom,sm8450-llcc"; 3988 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; 3989 reg-names = "llcc_base", "llcc_broadcast_base"; 3990 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3991 }; 3992 3993 ufs_mem_hc: ufshc@1d84000 { 3994 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 3995 "jedec,ufs-2.0"; 3996 reg = <0 0x01d84000 0 0x3000>, 3997 <0 0x01d88000 0 0x8000>; 3998 reg-names = "std", "ice"; 3999 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4000 phys = <&ufs_mem_phy_lanes>; 4001 phy-names = "ufsphy"; 4002 lanes-per-direction = <2>; 4003 #reset-cells = <1>; 4004 resets = <&gcc GCC_UFS_PHY_BCR>; 4005 reset-names = "rst"; 4006 4007 power-domains = <&gcc UFS_PHY_GDSC>; 4008 4009 iommus = <&apps_smmu 0xe0 0x0>; 4010 4011 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4012 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4013 interconnect-names = "ufs-ddr", "cpu-ufs"; 4014 clock-names = 4015 "core_clk", 4016 "bus_aggr_clk", 4017 "iface_clk", 4018 "core_clk_unipro", 4019 "ref_clk", 4020 "tx_lane0_sync_clk", 4021 "rx_lane0_sync_clk", 4022 "rx_lane1_sync_clk", 4023 "ice_core_clk"; 4024 clocks = 4025 <&gcc GCC_UFS_PHY_AXI_CLK>, 4026 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4027 <&gcc GCC_UFS_PHY_AHB_CLK>, 4028 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4029 <&rpmhcc RPMH_CXO_CLK>, 4030 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4031 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4032 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 4033 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4034 freq-table-hz = 4035 <75000000 300000000>, 4036 <0 0>, 4037 <0 0>, 4038 <75000000 300000000>, 4039 <75000000 300000000>, 4040 <0 0>, 4041 <0 0>, 4042 <0 0>, 4043 <75000000 300000000>; 4044 status = "disabled"; 4045 }; 4046 4047 ufs_mem_phy: phy@1d87000 { 4048 compatible = "qcom,sm8450-qmp-ufs-phy"; 4049 reg = <0 0x01d87000 0 0x1c4>; 4050 #address-cells = <2>; 4051 #size-cells = <2>; 4052 ranges; 4053 clock-names = "ref", "ref_aux", "qref"; 4054 clocks = <&rpmhcc RPMH_CXO_CLK>, 4055 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4056 <&gcc GCC_UFS_0_CLKREF_EN>; 4057 4058 resets = <&ufs_mem_hc 0>; 4059 reset-names = "ufsphy"; 4060 status = "disabled"; 4061 4062 ufs_mem_phy_lanes: phy@1d87400 { 4063 reg = <0 0x01d87400 0 0x188>, 4064 <0 0x01d87600 0 0x200>, 4065 <0 0x01d87c00 0 0x200>, 4066 <0 0x01d87800 0 0x188>, 4067 <0 0x01d87a00 0 0x200>; 4068 #clock-cells = <1>; 4069 #phy-cells = <0>; 4070 }; 4071 }; 4072 4073 sdhc_2: mmc@8804000 { 4074 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4075 reg = <0 0x08804000 0 0x1000>; 4076 4077 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4079 interrupt-names = "hc_irq", "pwr_irq"; 4080 4081 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4082 <&gcc GCC_SDCC2_APPS_CLK>, 4083 <&rpmhcc RPMH_CXO_CLK>; 4084 clock-names = "iface", "core", "xo"; 4085 resets = <&gcc GCC_SDCC2_BCR>; 4086 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4087 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4088 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4089 iommus = <&apps_smmu 0x4a0 0x0>; 4090 power-domains = <&rpmhpd SM8450_CX>; 4091 operating-points-v2 = <&sdhc2_opp_table>; 4092 bus-width = <4>; 4093 dma-coherent; 4094 4095 /* Forbid SDR104/SDR50 - broken hw! */ 4096 sdhci-caps-mask = <0x3 0x0>; 4097 4098 status = "disabled"; 4099 4100 sdhc2_opp_table: opp-table { 4101 compatible = "operating-points-v2"; 4102 4103 opp-100000000 { 4104 opp-hz = /bits/ 64 <100000000>; 4105 required-opps = <&rpmhpd_opp_low_svs>; 4106 }; 4107 4108 opp-202000000 { 4109 opp-hz = /bits/ 64 <202000000>; 4110 required-opps = <&rpmhpd_opp_svs_l1>; 4111 }; 4112 }; 4113 }; 4114 4115 usb_1: usb@a6f8800 { 4116 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4117 reg = <0 0x0a6f8800 0 0x400>; 4118 status = "disabled"; 4119 #address-cells = <2>; 4120 #size-cells = <2>; 4121 ranges; 4122 4123 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4124 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4125 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4126 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4127 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4128 <&gcc GCC_USB3_0_CLKREF_EN>; 4129 clock-names = "cfg_noc", 4130 "core", 4131 "iface", 4132 "sleep", 4133 "mock_utmi", 4134 "xo"; 4135 4136 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4137 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4138 assigned-clock-rates = <19200000>, <200000000>; 4139 4140 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4141 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4142 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4143 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4144 interrupt-names = "hs_phy_irq", 4145 "ss_phy_irq", 4146 "dm_hs_phy_irq", 4147 "dp_hs_phy_irq"; 4148 4149 power-domains = <&gcc USB30_PRIM_GDSC>; 4150 4151 resets = <&gcc GCC_USB30_PRIM_BCR>; 4152 4153 usb_1_dwc3: usb@a600000 { 4154 compatible = "snps,dwc3"; 4155 reg = <0 0x0a600000 0 0xcd00>; 4156 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4157 iommus = <&apps_smmu 0x0 0x0>; 4158 snps,dis_u2_susphy_quirk; 4159 snps,dis_enblslpm_quirk; 4160 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4161 phy-names = "usb2-phy", "usb3-phy"; 4162 }; 4163 }; 4164 4165 nsp_noc: interconnect@320c0000 { 4166 compatible = "qcom,sm8450-nsp-noc"; 4167 reg = <0 0x320c0000 0 0x10000>; 4168 #interconnect-cells = <2>; 4169 qcom,bcm-voters = <&apps_bcm_voter>; 4170 }; 4171 4172 lpass_ag_noc: interconnect@3c40000 { 4173 compatible = "qcom,sm8450-lpass-ag-noc"; 4174 reg = <0 0x03c40000 0 0x17200>; 4175 #interconnect-cells = <2>; 4176 qcom,bcm-voters = <&apps_bcm_voter>; 4177 }; 4178 }; 4179 4180 sound: sound { 4181 }; 4182 4183 thermal-zones { 4184 aoss0-thermal { 4185 polling-delay-passive = <0>; 4186 polling-delay = <0>; 4187 thermal-sensors = <&tsens0 0>; 4188 4189 trips { 4190 thermal-engine-config { 4191 temperature = <125000>; 4192 hysteresis = <1000>; 4193 type = "passive"; 4194 }; 4195 4196 reset-mon-cfg { 4197 temperature = <115000>; 4198 hysteresis = <5000>; 4199 type = "passive"; 4200 }; 4201 }; 4202 }; 4203 4204 cpuss0-thermal { 4205 polling-delay-passive = <0>; 4206 polling-delay = <0>; 4207 thermal-sensors = <&tsens0 1>; 4208 4209 trips { 4210 thermal-engine-config { 4211 temperature = <125000>; 4212 hysteresis = <1000>; 4213 type = "passive"; 4214 }; 4215 4216 reset-mon-cfg { 4217 temperature = <115000>; 4218 hysteresis = <5000>; 4219 type = "passive"; 4220 }; 4221 }; 4222 }; 4223 4224 cpuss1-thermal { 4225 polling-delay-passive = <0>; 4226 polling-delay = <0>; 4227 thermal-sensors = <&tsens0 2>; 4228 4229 trips { 4230 thermal-engine-config { 4231 temperature = <125000>; 4232 hysteresis = <1000>; 4233 type = "passive"; 4234 }; 4235 4236 reset-mon-cfg { 4237 temperature = <115000>; 4238 hysteresis = <5000>; 4239 type = "passive"; 4240 }; 4241 }; 4242 }; 4243 4244 cpuss3-thermal { 4245 polling-delay-passive = <0>; 4246 polling-delay = <0>; 4247 thermal-sensors = <&tsens0 3>; 4248 4249 trips { 4250 thermal-engine-config { 4251 temperature = <125000>; 4252 hysteresis = <1000>; 4253 type = "passive"; 4254 }; 4255 4256 reset-mon-cfg { 4257 temperature = <115000>; 4258 hysteresis = <5000>; 4259 type = "passive"; 4260 }; 4261 }; 4262 }; 4263 4264 cpuss4-thermal { 4265 polling-delay-passive = <0>; 4266 polling-delay = <0>; 4267 thermal-sensors = <&tsens0 4>; 4268 4269 trips { 4270 thermal-engine-config { 4271 temperature = <125000>; 4272 hysteresis = <1000>; 4273 type = "passive"; 4274 }; 4275 4276 reset-mon-cfg { 4277 temperature = <115000>; 4278 hysteresis = <5000>; 4279 type = "passive"; 4280 }; 4281 }; 4282 }; 4283 4284 cpu4-top-thermal { 4285 polling-delay-passive = <0>; 4286 polling-delay = <0>; 4287 thermal-sensors = <&tsens0 5>; 4288 4289 trips { 4290 cpu4_top_alert0: trip-point0 { 4291 temperature = <90000>; 4292 hysteresis = <2000>; 4293 type = "passive"; 4294 }; 4295 4296 cpu4_top_alert1: trip-point1 { 4297 temperature = <95000>; 4298 hysteresis = <2000>; 4299 type = "passive"; 4300 }; 4301 4302 cpu4_top_crit: cpu-crit { 4303 temperature = <110000>; 4304 hysteresis = <1000>; 4305 type = "critical"; 4306 }; 4307 }; 4308 }; 4309 4310 cpu4-bottom-thermal { 4311 polling-delay-passive = <0>; 4312 polling-delay = <0>; 4313 thermal-sensors = <&tsens0 6>; 4314 4315 trips { 4316 cpu4_bottom_alert0: trip-point0 { 4317 temperature = <90000>; 4318 hysteresis = <2000>; 4319 type = "passive"; 4320 }; 4321 4322 cpu4_bottom_alert1: trip-point1 { 4323 temperature = <95000>; 4324 hysteresis = <2000>; 4325 type = "passive"; 4326 }; 4327 4328 cpu4_bottom_crit: cpu-crit { 4329 temperature = <110000>; 4330 hysteresis = <1000>; 4331 type = "critical"; 4332 }; 4333 }; 4334 }; 4335 4336 cpu5-top-thermal { 4337 polling-delay-passive = <0>; 4338 polling-delay = <0>; 4339 thermal-sensors = <&tsens0 7>; 4340 4341 trips { 4342 cpu5_top_alert0: trip-point0 { 4343 temperature = <90000>; 4344 hysteresis = <2000>; 4345 type = "passive"; 4346 }; 4347 4348 cpu5_top_alert1: trip-point1 { 4349 temperature = <95000>; 4350 hysteresis = <2000>; 4351 type = "passive"; 4352 }; 4353 4354 cpu5_top_crit: cpu-crit { 4355 temperature = <110000>; 4356 hysteresis = <1000>; 4357 type = "critical"; 4358 }; 4359 }; 4360 }; 4361 4362 cpu5-bottom-thermal { 4363 polling-delay-passive = <0>; 4364 polling-delay = <0>; 4365 thermal-sensors = <&tsens0 8>; 4366 4367 trips { 4368 cpu5_bottom_alert0: trip-point0 { 4369 temperature = <90000>; 4370 hysteresis = <2000>; 4371 type = "passive"; 4372 }; 4373 4374 cpu5_bottom_alert1: trip-point1 { 4375 temperature = <95000>; 4376 hysteresis = <2000>; 4377 type = "passive"; 4378 }; 4379 4380 cpu5_bottom_crit: cpu-crit { 4381 temperature = <110000>; 4382 hysteresis = <1000>; 4383 type = "critical"; 4384 }; 4385 }; 4386 }; 4387 4388 cpu6-top-thermal { 4389 polling-delay-passive = <0>; 4390 polling-delay = <0>; 4391 thermal-sensors = <&tsens0 9>; 4392 4393 trips { 4394 cpu6_top_alert0: trip-point0 { 4395 temperature = <90000>; 4396 hysteresis = <2000>; 4397 type = "passive"; 4398 }; 4399 4400 cpu6_top_alert1: trip-point1 { 4401 temperature = <95000>; 4402 hysteresis = <2000>; 4403 type = "passive"; 4404 }; 4405 4406 cpu6_top_crit: cpu-crit { 4407 temperature = <110000>; 4408 hysteresis = <1000>; 4409 type = "critical"; 4410 }; 4411 }; 4412 }; 4413 4414 cpu6-bottom-thermal { 4415 polling-delay-passive = <0>; 4416 polling-delay = <0>; 4417 thermal-sensors = <&tsens0 10>; 4418 4419 trips { 4420 cpu6_bottom_alert0: trip-point0 { 4421 temperature = <90000>; 4422 hysteresis = <2000>; 4423 type = "passive"; 4424 }; 4425 4426 cpu6_bottom_alert1: trip-point1 { 4427 temperature = <95000>; 4428 hysteresis = <2000>; 4429 type = "passive"; 4430 }; 4431 4432 cpu6_bottom_crit: cpu-crit { 4433 temperature = <110000>; 4434 hysteresis = <1000>; 4435 type = "critical"; 4436 }; 4437 }; 4438 }; 4439 4440 cpu7-top-thermal { 4441 polling-delay-passive = <0>; 4442 polling-delay = <0>; 4443 thermal-sensors = <&tsens0 11>; 4444 4445 trips { 4446 cpu7_top_alert0: trip-point0 { 4447 temperature = <90000>; 4448 hysteresis = <2000>; 4449 type = "passive"; 4450 }; 4451 4452 cpu7_top_alert1: trip-point1 { 4453 temperature = <95000>; 4454 hysteresis = <2000>; 4455 type = "passive"; 4456 }; 4457 4458 cpu7_top_crit: cpu-crit { 4459 temperature = <110000>; 4460 hysteresis = <1000>; 4461 type = "critical"; 4462 }; 4463 }; 4464 }; 4465 4466 cpu7-middle-thermal { 4467 polling-delay-passive = <0>; 4468 polling-delay = <0>; 4469 thermal-sensors = <&tsens0 12>; 4470 4471 trips { 4472 cpu7_middle_alert0: trip-point0 { 4473 temperature = <90000>; 4474 hysteresis = <2000>; 4475 type = "passive"; 4476 }; 4477 4478 cpu7_middle_alert1: trip-point1 { 4479 temperature = <95000>; 4480 hysteresis = <2000>; 4481 type = "passive"; 4482 }; 4483 4484 cpu7_middle_crit: cpu-crit { 4485 temperature = <110000>; 4486 hysteresis = <1000>; 4487 type = "critical"; 4488 }; 4489 }; 4490 }; 4491 4492 cpu7-bottom-thermal { 4493 polling-delay-passive = <0>; 4494 polling-delay = <0>; 4495 thermal-sensors = <&tsens0 13>; 4496 4497 trips { 4498 cpu7_bottom_alert0: trip-point0 { 4499 temperature = <90000>; 4500 hysteresis = <2000>; 4501 type = "passive"; 4502 }; 4503 4504 cpu7_bottom_alert1: trip-point1 { 4505 temperature = <95000>; 4506 hysteresis = <2000>; 4507 type = "passive"; 4508 }; 4509 4510 cpu7_bottom_crit: cpu-crit { 4511 temperature = <110000>; 4512 hysteresis = <1000>; 4513 type = "critical"; 4514 }; 4515 }; 4516 }; 4517 4518 gpu-top-thermal { 4519 polling-delay-passive = <10>; 4520 polling-delay = <0>; 4521 thermal-sensors = <&tsens0 14>; 4522 4523 trips { 4524 thermal-engine-config { 4525 temperature = <125000>; 4526 hysteresis = <1000>; 4527 type = "passive"; 4528 }; 4529 4530 thermal-hal-config { 4531 temperature = <125000>; 4532 hysteresis = <1000>; 4533 type = "passive"; 4534 }; 4535 4536 reset-mon-cfg { 4537 temperature = <115000>; 4538 hysteresis = <5000>; 4539 type = "passive"; 4540 }; 4541 4542 gpu0_tj_cfg: tj-cfg { 4543 temperature = <95000>; 4544 hysteresis = <5000>; 4545 type = "passive"; 4546 }; 4547 }; 4548 }; 4549 4550 gpu-bottom-thermal { 4551 polling-delay-passive = <10>; 4552 polling-delay = <0>; 4553 thermal-sensors = <&tsens0 15>; 4554 4555 trips { 4556 thermal-engine-config { 4557 temperature = <125000>; 4558 hysteresis = <1000>; 4559 type = "passive"; 4560 }; 4561 4562 thermal-hal-config { 4563 temperature = <125000>; 4564 hysteresis = <1000>; 4565 type = "passive"; 4566 }; 4567 4568 reset-mon-cfg { 4569 temperature = <115000>; 4570 hysteresis = <5000>; 4571 type = "passive"; 4572 }; 4573 4574 gpu1_tj_cfg: tj-cfg { 4575 temperature = <95000>; 4576 hysteresis = <5000>; 4577 type = "passive"; 4578 }; 4579 }; 4580 }; 4581 4582 aoss1-thermal { 4583 polling-delay-passive = <0>; 4584 polling-delay = <0>; 4585 thermal-sensors = <&tsens1 0>; 4586 4587 trips { 4588 thermal-engine-config { 4589 temperature = <125000>; 4590 hysteresis = <1000>; 4591 type = "passive"; 4592 }; 4593 4594 reset-mon-cfg { 4595 temperature = <115000>; 4596 hysteresis = <5000>; 4597 type = "passive"; 4598 }; 4599 }; 4600 }; 4601 4602 cpu0-thermal { 4603 polling-delay-passive = <0>; 4604 polling-delay = <0>; 4605 thermal-sensors = <&tsens1 1>; 4606 4607 trips { 4608 cpu0_alert0: trip-point0 { 4609 temperature = <90000>; 4610 hysteresis = <2000>; 4611 type = "passive"; 4612 }; 4613 4614 cpu0_alert1: trip-point1 { 4615 temperature = <95000>; 4616 hysteresis = <2000>; 4617 type = "passive"; 4618 }; 4619 4620 cpu0_crit: cpu-crit { 4621 temperature = <110000>; 4622 hysteresis = <1000>; 4623 type = "critical"; 4624 }; 4625 }; 4626 }; 4627 4628 cpu1-thermal { 4629 polling-delay-passive = <0>; 4630 polling-delay = <0>; 4631 thermal-sensors = <&tsens1 2>; 4632 4633 trips { 4634 cpu1_alert0: trip-point0 { 4635 temperature = <90000>; 4636 hysteresis = <2000>; 4637 type = "passive"; 4638 }; 4639 4640 cpu1_alert1: trip-point1 { 4641 temperature = <95000>; 4642 hysteresis = <2000>; 4643 type = "passive"; 4644 }; 4645 4646 cpu1_crit: cpu-crit { 4647 temperature = <110000>; 4648 hysteresis = <1000>; 4649 type = "critical"; 4650 }; 4651 }; 4652 }; 4653 4654 cpu2-thermal { 4655 polling-delay-passive = <0>; 4656 polling-delay = <0>; 4657 thermal-sensors = <&tsens1 3>; 4658 4659 trips { 4660 cpu2_alert0: trip-point0 { 4661 temperature = <90000>; 4662 hysteresis = <2000>; 4663 type = "passive"; 4664 }; 4665 4666 cpu2_alert1: trip-point1 { 4667 temperature = <95000>; 4668 hysteresis = <2000>; 4669 type = "passive"; 4670 }; 4671 4672 cpu2_crit: cpu-crit { 4673 temperature = <110000>; 4674 hysteresis = <1000>; 4675 type = "critical"; 4676 }; 4677 }; 4678 }; 4679 4680 cpu3-thermal { 4681 polling-delay-passive = <0>; 4682 polling-delay = <0>; 4683 thermal-sensors = <&tsens1 4>; 4684 4685 trips { 4686 cpu3_alert0: trip-point0 { 4687 temperature = <90000>; 4688 hysteresis = <2000>; 4689 type = "passive"; 4690 }; 4691 4692 cpu3_alert1: trip-point1 { 4693 temperature = <95000>; 4694 hysteresis = <2000>; 4695 type = "passive"; 4696 }; 4697 4698 cpu3_crit: cpu-crit { 4699 temperature = <110000>; 4700 hysteresis = <1000>; 4701 type = "critical"; 4702 }; 4703 }; 4704 }; 4705 4706 cdsp0-thermal { 4707 polling-delay-passive = <10>; 4708 polling-delay = <0>; 4709 thermal-sensors = <&tsens1 5>; 4710 4711 trips { 4712 thermal-engine-config { 4713 temperature = <125000>; 4714 hysteresis = <1000>; 4715 type = "passive"; 4716 }; 4717 4718 thermal-hal-config { 4719 temperature = <125000>; 4720 hysteresis = <1000>; 4721 type = "passive"; 4722 }; 4723 4724 reset-mon-cfg { 4725 temperature = <115000>; 4726 hysteresis = <5000>; 4727 type = "passive"; 4728 }; 4729 4730 cdsp_0_config: junction-config { 4731 temperature = <95000>; 4732 hysteresis = <5000>; 4733 type = "passive"; 4734 }; 4735 }; 4736 }; 4737 4738 cdsp1-thermal { 4739 polling-delay-passive = <10>; 4740 polling-delay = <0>; 4741 thermal-sensors = <&tsens1 6>; 4742 4743 trips { 4744 thermal-engine-config { 4745 temperature = <125000>; 4746 hysteresis = <1000>; 4747 type = "passive"; 4748 }; 4749 4750 thermal-hal-config { 4751 temperature = <125000>; 4752 hysteresis = <1000>; 4753 type = "passive"; 4754 }; 4755 4756 reset-mon-cfg { 4757 temperature = <115000>; 4758 hysteresis = <5000>; 4759 type = "passive"; 4760 }; 4761 4762 cdsp_1_config: junction-config { 4763 temperature = <95000>; 4764 hysteresis = <5000>; 4765 type = "passive"; 4766 }; 4767 }; 4768 }; 4769 4770 cdsp2-thermal { 4771 polling-delay-passive = <10>; 4772 polling-delay = <0>; 4773 thermal-sensors = <&tsens1 7>; 4774 4775 trips { 4776 thermal-engine-config { 4777 temperature = <125000>; 4778 hysteresis = <1000>; 4779 type = "passive"; 4780 }; 4781 4782 thermal-hal-config { 4783 temperature = <125000>; 4784 hysteresis = <1000>; 4785 type = "passive"; 4786 }; 4787 4788 reset-mon-cfg { 4789 temperature = <115000>; 4790 hysteresis = <5000>; 4791 type = "passive"; 4792 }; 4793 4794 cdsp_2_config: junction-config { 4795 temperature = <95000>; 4796 hysteresis = <5000>; 4797 type = "passive"; 4798 }; 4799 }; 4800 }; 4801 4802 video-thermal { 4803 polling-delay-passive = <0>; 4804 polling-delay = <0>; 4805 thermal-sensors = <&tsens1 8>; 4806 4807 trips { 4808 thermal-engine-config { 4809 temperature = <125000>; 4810 hysteresis = <1000>; 4811 type = "passive"; 4812 }; 4813 4814 reset-mon-cfg { 4815 temperature = <115000>; 4816 hysteresis = <5000>; 4817 type = "passive"; 4818 }; 4819 }; 4820 }; 4821 4822 mem-thermal { 4823 polling-delay-passive = <10>; 4824 polling-delay = <0>; 4825 thermal-sensors = <&tsens1 9>; 4826 4827 trips { 4828 thermal-engine-config { 4829 temperature = <125000>; 4830 hysteresis = <1000>; 4831 type = "passive"; 4832 }; 4833 4834 ddr_config0: ddr0-config { 4835 temperature = <90000>; 4836 hysteresis = <5000>; 4837 type = "passive"; 4838 }; 4839 4840 reset-mon-cfg { 4841 temperature = <115000>; 4842 hysteresis = <5000>; 4843 type = "passive"; 4844 }; 4845 }; 4846 }; 4847 4848 modem0-thermal { 4849 polling-delay-passive = <0>; 4850 polling-delay = <0>; 4851 thermal-sensors = <&tsens1 10>; 4852 4853 trips { 4854 thermal-engine-config { 4855 temperature = <125000>; 4856 hysteresis = <1000>; 4857 type = "passive"; 4858 }; 4859 4860 mdmss0_config0: mdmss0-config0 { 4861 temperature = <102000>; 4862 hysteresis = <3000>; 4863 type = "passive"; 4864 }; 4865 4866 mdmss0_config1: mdmss0-config1 { 4867 temperature = <105000>; 4868 hysteresis = <3000>; 4869 type = "passive"; 4870 }; 4871 4872 reset-mon-cfg { 4873 temperature = <115000>; 4874 hysteresis = <5000>; 4875 type = "passive"; 4876 }; 4877 }; 4878 }; 4879 4880 modem1-thermal { 4881 polling-delay-passive = <0>; 4882 polling-delay = <0>; 4883 thermal-sensors = <&tsens1 11>; 4884 4885 trips { 4886 thermal-engine-config { 4887 temperature = <125000>; 4888 hysteresis = <1000>; 4889 type = "passive"; 4890 }; 4891 4892 mdmss1_config0: mdmss1-config0 { 4893 temperature = <102000>; 4894 hysteresis = <3000>; 4895 type = "passive"; 4896 }; 4897 4898 mdmss1_config1: mdmss1-config1 { 4899 temperature = <105000>; 4900 hysteresis = <3000>; 4901 type = "passive"; 4902 }; 4903 4904 reset-mon-cfg { 4905 temperature = <115000>; 4906 hysteresis = <5000>; 4907 type = "passive"; 4908 }; 4909 }; 4910 }; 4911 4912 modem2-thermal { 4913 polling-delay-passive = <0>; 4914 polling-delay = <0>; 4915 thermal-sensors = <&tsens1 12>; 4916 4917 trips { 4918 thermal-engine-config { 4919 temperature = <125000>; 4920 hysteresis = <1000>; 4921 type = "passive"; 4922 }; 4923 4924 mdmss2_config0: mdmss2-config0 { 4925 temperature = <102000>; 4926 hysteresis = <3000>; 4927 type = "passive"; 4928 }; 4929 4930 mdmss2_config1: mdmss2-config1 { 4931 temperature = <105000>; 4932 hysteresis = <3000>; 4933 type = "passive"; 4934 }; 4935 4936 reset-mon-cfg { 4937 temperature = <115000>; 4938 hysteresis = <5000>; 4939 type = "passive"; 4940 }; 4941 }; 4942 }; 4943 4944 modem3-thermal { 4945 polling-delay-passive = <0>; 4946 polling-delay = <0>; 4947 thermal-sensors = <&tsens1 13>; 4948 4949 trips { 4950 thermal-engine-config { 4951 temperature = <125000>; 4952 hysteresis = <1000>; 4953 type = "passive"; 4954 }; 4955 4956 mdmss3_config0: mdmss3-config0 { 4957 temperature = <102000>; 4958 hysteresis = <3000>; 4959 type = "passive"; 4960 }; 4961 4962 mdmss3_config1: mdmss3-config1 { 4963 temperature = <105000>; 4964 hysteresis = <3000>; 4965 type = "passive"; 4966 }; 4967 4968 reset-mon-cfg { 4969 temperature = <115000>; 4970 hysteresis = <5000>; 4971 type = "passive"; 4972 }; 4973 }; 4974 }; 4975 4976 camera0-thermal { 4977 polling-delay-passive = <0>; 4978 polling-delay = <0>; 4979 thermal-sensors = <&tsens1 14>; 4980 4981 trips { 4982 thermal-engine-config { 4983 temperature = <125000>; 4984 hysteresis = <1000>; 4985 type = "passive"; 4986 }; 4987 4988 reset-mon-cfg { 4989 temperature = <115000>; 4990 hysteresis = <5000>; 4991 type = "passive"; 4992 }; 4993 }; 4994 }; 4995 4996 camera1-thermal { 4997 polling-delay-passive = <0>; 4998 polling-delay = <0>; 4999 thermal-sensors = <&tsens1 15>; 5000 5001 trips { 5002 thermal-engine-config { 5003 temperature = <125000>; 5004 hysteresis = <1000>; 5005 type = "passive"; 5006 }; 5007 5008 reset-mon-cfg { 5009 temperature = <115000>; 5010 hysteresis = <5000>; 5011 type = "passive"; 5012 }; 5013 }; 5014 }; 5015 }; 5016 5017 timer { 5018 compatible = "arm,armv8-timer"; 5019 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5020 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5021 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5022 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5023 clock-frequency = <19200000>; 5024 }; 5025}; 5026