1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/interconnect/qcom,sm8450.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <76800000>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32000>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo780"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 qcom,freq-domain = <&cpufreq_hw 0>; 53 #cooling-cells = <2>; 54 L2_0: l2-cache { 55 compatible = "cache"; 56 next-level-cache = <&L3_0>; 57 L3_0: l3-cache { 58 compatible = "cache"; 59 }; 60 }; 61 }; 62 63 CPU1: cpu@100 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo780"; 66 reg = <0x0 0x100>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_100>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 qcom,freq-domain = <&cpufreq_hw 0>; 72 #cooling-cells = <2>; 73 L2_100: l2-cache { 74 compatible = "cache"; 75 next-level-cache = <&L3_0>; 76 }; 77 }; 78 79 CPU2: cpu@200 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo780"; 82 reg = <0x0 0x200>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_200>; 85 power-domains = <&CPU_PD2>; 86 power-domain-names = "psci"; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 #cooling-cells = <2>; 89 L2_200: l2-cache { 90 compatible = "cache"; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU3: cpu@300 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo780"; 98 reg = <0x0 0x300>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_300>; 101 power-domains = <&CPU_PD3>; 102 power-domain-names = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 #cooling-cells = <2>; 105 L2_300: l2-cache { 106 compatible = "cache"; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo780"; 114 reg = <0x0 0x400>; 115 enable-method = "psci"; 116 next-level-cache = <&L2_400>; 117 power-domains = <&CPU_PD4>; 118 power-domain-names = "psci"; 119 qcom,freq-domain = <&cpufreq_hw 1>; 120 #cooling-cells = <2>; 121 L2_400: l2-cache { 122 compatible = "cache"; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU5: cpu@500 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo780"; 130 reg = <0x0 0x500>; 131 enable-method = "psci"; 132 next-level-cache = <&L2_500>; 133 power-domains = <&CPU_PD5>; 134 power-domain-names = "psci"; 135 qcom,freq-domain = <&cpufreq_hw 1>; 136 #cooling-cells = <2>; 137 L2_500: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 142 }; 143 144 CPU6: cpu@600 { 145 device_type = "cpu"; 146 compatible = "qcom,kryo780"; 147 reg = <0x0 0x600>; 148 enable-method = "psci"; 149 next-level-cache = <&L2_600>; 150 power-domains = <&CPU_PD6>; 151 power-domain-names = "psci"; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 #cooling-cells = <2>; 154 L2_600: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU7: cpu@700 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo780"; 163 reg = <0x0 0x700>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_700>; 166 power-domains = <&CPU_PD7>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 2>; 169 #cooling-cells = <2>; 170 L2_700: l2-cache { 171 compatible = "cache"; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 cpu-map { 177 cluster0 { 178 core0 { 179 cpu = <&CPU0>; 180 }; 181 182 core1 { 183 cpu = <&CPU1>; 184 }; 185 186 core2 { 187 cpu = <&CPU2>; 188 }; 189 190 core3 { 191 cpu = <&CPU3>; 192 }; 193 194 core4 { 195 cpu = <&CPU4>; 196 }; 197 198 core5 { 199 cpu = <&CPU5>; 200 }; 201 202 core6 { 203 cpu = <&CPU6>; 204 }; 205 206 core7 { 207 cpu = <&CPU7>; 208 }; 209 }; 210 }; 211 212 idle-states { 213 entry-method = "psci"; 214 215 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 216 compatible = "arm,idle-state"; 217 idle-state-name = "silver-rail-power-collapse"; 218 arm,psci-suspend-param = <0x40000004>; 219 entry-latency-us = <800>; 220 exit-latency-us = <750>; 221 min-residency-us = <4090>; 222 local-timer-stop; 223 }; 224 225 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 226 compatible = "arm,idle-state"; 227 idle-state-name = "gold-rail-power-collapse"; 228 arm,psci-suspend-param = <0x40000004>; 229 entry-latency-us = <600>; 230 exit-latency-us = <1550>; 231 min-residency-us = <4791>; 232 local-timer-stop; 233 }; 234 }; 235 236 domain-idle-states { 237 CLUSTER_SLEEP_0: cluster-sleep-0 { 238 compatible = "domain-idle-state"; 239 idle-state-name = "cluster-l3-off"; 240 arm,psci-suspend-param = <0x41000044>; 241 entry-latency-us = <1050>; 242 exit-latency-us = <2500>; 243 min-residency-us = <5309>; 244 local-timer-stop; 245 }; 246 247 CLUSTER_SLEEP_1: cluster-sleep-1 { 248 compatible = "domain-idle-state"; 249 idle-state-name = "cluster-power-collapse"; 250 arm,psci-suspend-param = <0x4100c344>; 251 entry-latency-us = <2700>; 252 exit-latency-us = <3500>; 253 min-residency-us = <13959>; 254 local-timer-stop; 255 }; 256 }; 257 }; 258 259 firmware { 260 scm: scm { 261 compatible = "qcom,scm-sm8450", "qcom,scm"; 262 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 263 #reset-cells = <1>; 264 }; 265 }; 266 267 clk_virt: interconnect-0 { 268 compatible = "qcom,sm8450-clk-virt"; 269 #interconnect-cells = <2>; 270 qcom,bcm-voters = <&apps_bcm_voter>; 271 }; 272 273 mc_virt: interconnect-1 { 274 compatible = "qcom,sm8450-mc-virt"; 275 #interconnect-cells = <2>; 276 qcom,bcm-voters = <&apps_bcm_voter>; 277 }; 278 279 memory@a0000000 { 280 device_type = "memory"; 281 /* We expect the bootloader to fill in the size */ 282 reg = <0x0 0xa0000000 0x0 0x0>; 283 }; 284 285 pmu { 286 compatible = "arm,armv8-pmuv3"; 287 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 psci { 291 compatible = "arm,psci-1.0"; 292 method = "smc"; 293 294 CPU_PD0: cpu0 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 298 }; 299 300 CPU_PD1: cpu1 { 301 #power-domain-cells = <0>; 302 power-domains = <&CLUSTER_PD>; 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 304 }; 305 306 CPU_PD2: cpu2 { 307 #power-domain-cells = <0>; 308 power-domains = <&CLUSTER_PD>; 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 310 }; 311 312 CPU_PD3: cpu3 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD4: cpu4 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&BIG_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD5: cpu5 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&BIG_CPU_SLEEP_0>; 328 }; 329 330 CPU_PD6: cpu6 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&BIG_CPU_SLEEP_0>; 334 }; 335 336 CPU_PD7: cpu7 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0>; 340 }; 341 342 CLUSTER_PD: cpu-cluster0 { 343 #power-domain-cells = <0>; 344 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 345 }; 346 }; 347 348 qup_opp_table_100mhz: opp-table-qup { 349 compatible = "operating-points-v2"; 350 351 opp-50000000 { 352 opp-hz = /bits/ 64 <50000000>; 353 required-opps = <&rpmhpd_opp_min_svs>; 354 }; 355 356 opp-75000000 { 357 opp-hz = /bits/ 64 <75000000>; 358 required-opps = <&rpmhpd_opp_low_svs>; 359 }; 360 361 opp-100000000 { 362 opp-hz = /bits/ 64 <100000000>; 363 required-opps = <&rpmhpd_opp_svs>; 364 }; 365 }; 366 367 reserved_memory: reserved-memory { 368 #address-cells = <2>; 369 #size-cells = <2>; 370 ranges; 371 372 hyp_mem: memory@80000000 { 373 reg = <0x0 0x80000000 0x0 0x600000>; 374 no-map; 375 }; 376 377 xbl_dt_log_mem: memory@80600000 { 378 reg = <0x0 0x80600000 0x0 0x40000>; 379 no-map; 380 }; 381 382 xbl_ramdump_mem: memory@80640000 { 383 reg = <0x0 0x80640000 0x0 0x180000>; 384 no-map; 385 }; 386 387 xbl_sc_mem: memory@807c0000 { 388 reg = <0x0 0x807c0000 0x0 0x40000>; 389 no-map; 390 }; 391 392 aop_image_mem: memory@80800000 { 393 reg = <0x0 0x80800000 0x0 0x60000>; 394 no-map; 395 }; 396 397 aop_cmd_db_mem: memory@80860000 { 398 compatible = "qcom,cmd-db"; 399 reg = <0x0 0x80860000 0x0 0x20000>; 400 no-map; 401 }; 402 403 aop_config_mem: memory@80880000 { 404 reg = <0x0 0x80880000 0x0 0x20000>; 405 no-map; 406 }; 407 408 tme_crash_dump_mem: memory@808a0000 { 409 reg = <0x0 0x808a0000 0x0 0x40000>; 410 no-map; 411 }; 412 413 tme_log_mem: memory@808e0000 { 414 reg = <0x0 0x808e0000 0x0 0x4000>; 415 no-map; 416 }; 417 418 uefi_log_mem: memory@808e4000 { 419 reg = <0x0 0x808e4000 0x0 0x10000>; 420 no-map; 421 }; 422 423 /* secdata region can be reused by apps */ 424 smem: memory@80900000 { 425 compatible = "qcom,smem"; 426 reg = <0x0 0x80900000 0x0 0x200000>; 427 hwlocks = <&tcsr_mutex 3>; 428 no-map; 429 }; 430 431 cpucp_fw_mem: memory@80b00000 { 432 reg = <0x0 0x80b00000 0x0 0x100000>; 433 no-map; 434 }; 435 436 cdsp_secure_heap: memory@80c00000 { 437 reg = <0x0 0x80c00000 0x0 0x4600000>; 438 no-map; 439 }; 440 441 video_mem: memory@85700000 { 442 reg = <0x0 0x85700000 0x0 0x700000>; 443 no-map; 444 }; 445 446 adsp_mem: memory@85e00000 { 447 reg = <0x0 0x85e00000 0x0 0x2100000>; 448 no-map; 449 }; 450 451 slpi_mem: memory@88000000 { 452 reg = <0x0 0x88000000 0x0 0x1900000>; 453 no-map; 454 }; 455 456 cdsp_mem: memory@89900000 { 457 reg = <0x0 0x89900000 0x0 0x2000000>; 458 no-map; 459 }; 460 461 ipa_fw_mem: memory@8b900000 { 462 reg = <0x0 0x8b900000 0x0 0x10000>; 463 no-map; 464 }; 465 466 ipa_gsi_mem: memory@8b910000 { 467 reg = <0x0 0x8b910000 0x0 0xa000>; 468 no-map; 469 }; 470 471 gpu_micro_code_mem: memory@8b91a000 { 472 reg = <0x0 0x8b91a000 0x0 0x2000>; 473 no-map; 474 }; 475 476 spss_region_mem: memory@8ba00000 { 477 reg = <0x0 0x8ba00000 0x0 0x180000>; 478 no-map; 479 }; 480 481 /* First part of the "SPU secure shared memory" region */ 482 spu_tz_shared_mem: memory@8bb80000 { 483 reg = <0x0 0x8bb80000 0x0 0x60000>; 484 no-map; 485 }; 486 487 /* Second part of the "SPU secure shared memory" region */ 488 spu_modem_shared_mem: memory@8bbe0000 { 489 reg = <0x0 0x8bbe0000 0x0 0x20000>; 490 no-map; 491 }; 492 493 mpss_mem: memory@8bc00000 { 494 reg = <0x0 0x8bc00000 0x0 0x13200000>; 495 no-map; 496 }; 497 498 cvp_mem: memory@9ee00000 { 499 reg = <0x0 0x9ee00000 0x0 0x700000>; 500 no-map; 501 }; 502 503 camera_mem: memory@9f500000 { 504 reg = <0x0 0x9f500000 0x0 0x800000>; 505 no-map; 506 }; 507 508 rmtfs_mem: memory@9fd00000 { 509 compatible = "qcom,rmtfs-mem"; 510 reg = <0x0 0x9fd00000 0x0 0x280000>; 511 no-map; 512 513 qcom,client-id = <1>; 514 qcom,vmid = <15>; 515 }; 516 517 xbl_sc_mem2: memory@a6e00000 { 518 reg = <0x0 0xa6e00000 0x0 0x40000>; 519 no-map; 520 }; 521 522 global_sync_mem: memory@a6f00000 { 523 reg = <0x0 0xa6f00000 0x0 0x100000>; 524 no-map; 525 }; 526 527 /* uefi region can be reused by APPS */ 528 529 /* Linux kernel image is loaded at 0xa0000000 */ 530 531 oem_vm_mem: memory@bb000000 { 532 reg = <0x0 0xbb000000 0x0 0x5000000>; 533 no-map; 534 }; 535 536 mte_mem: memory@c0000000 { 537 reg = <0x0 0xc0000000 0x0 0x20000000>; 538 no-map; 539 }; 540 541 qheebsp_reserved_mem: memory@e0000000 { 542 reg = <0x0 0xe0000000 0x0 0x600000>; 543 no-map; 544 }; 545 546 cpusys_vm_mem: memory@e0600000 { 547 reg = <0x0 0xe0600000 0x0 0x400000>; 548 no-map; 549 }; 550 551 hyp_reserved_mem: memory@e0a00000 { 552 reg = <0x0 0xe0a00000 0x0 0x100000>; 553 no-map; 554 }; 555 556 trust_ui_vm_mem: memory@e0b00000 { 557 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 558 no-map; 559 }; 560 561 trust_ui_vm_qrtr: memory@e55f3000 { 562 reg = <0x0 0xe55f3000 0x0 0x9000>; 563 no-map; 564 }; 565 566 trust_ui_vm_vblk0_ring: memory@e55fc000 { 567 reg = <0x0 0xe55fc000 0x0 0x4000>; 568 no-map; 569 }; 570 571 trust_ui_vm_swiotlb: memory@e5600000 { 572 reg = <0x0 0xe5600000 0x0 0x100000>; 573 no-map; 574 }; 575 576 tz_stat_mem: memory@e8800000 { 577 reg = <0x0 0xe8800000 0x0 0x100000>; 578 no-map; 579 }; 580 581 tags_mem: memory@e8900000 { 582 reg = <0x0 0xe8900000 0x0 0x1200000>; 583 no-map; 584 }; 585 586 qtee_mem: memory@e9b00000 { 587 reg = <0x0 0xe9b00000 0x0 0x500000>; 588 no-map; 589 }; 590 591 trusted_apps_mem: memory@ea000000 { 592 reg = <0x0 0xea000000 0x0 0x3900000>; 593 no-map; 594 }; 595 596 trusted_apps_ext_mem: memory@ed900000 { 597 reg = <0x0 0xed900000 0x0 0x3b00000>; 598 no-map; 599 }; 600 }; 601 602 smp2p-adsp { 603 compatible = "qcom,smp2p"; 604 qcom,smem = <443>, <429>; 605 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 606 IPCC_MPROC_SIGNAL_SMP2P 607 IRQ_TYPE_EDGE_RISING>; 608 mboxes = <&ipcc IPCC_CLIENT_LPASS 609 IPCC_MPROC_SIGNAL_SMP2P>; 610 611 qcom,local-pid = <0>; 612 qcom,remote-pid = <2>; 613 614 smp2p_adsp_out: master-kernel { 615 qcom,entry-name = "master-kernel"; 616 #qcom,smem-state-cells = <1>; 617 }; 618 619 smp2p_adsp_in: slave-kernel { 620 qcom,entry-name = "slave-kernel"; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 }; 624 }; 625 626 smp2p-cdsp { 627 compatible = "qcom,smp2p"; 628 qcom,smem = <94>, <432>; 629 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 630 IPCC_MPROC_SIGNAL_SMP2P 631 IRQ_TYPE_EDGE_RISING>; 632 mboxes = <&ipcc IPCC_CLIENT_CDSP 633 IPCC_MPROC_SIGNAL_SMP2P>; 634 635 qcom,local-pid = <0>; 636 qcom,remote-pid = <5>; 637 638 smp2p_cdsp_out: master-kernel { 639 qcom,entry-name = "master-kernel"; 640 #qcom,smem-state-cells = <1>; 641 }; 642 643 smp2p_cdsp_in: slave-kernel { 644 qcom,entry-name = "slave-kernel"; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 }; 649 650 smp2p-modem { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <435>, <428>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_MPSS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <1>; 661 662 smp2p_modem_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 smp2p_modem_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 673 ipa_smp2p_out: ipa-ap-to-modem { 674 qcom,entry-name = "ipa"; 675 #qcom,smem-state-cells = <1>; 676 }; 677 678 ipa_smp2p_in: ipa-modem-to-ap { 679 qcom,entry-name = "ipa"; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 }; 684 685 smp2p-slpi { 686 compatible = "qcom,smp2p"; 687 qcom,smem = <481>, <430>; 688 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 689 IPCC_MPROC_SIGNAL_SMP2P 690 IRQ_TYPE_EDGE_RISING>; 691 mboxes = <&ipcc IPCC_CLIENT_SLPI 692 IPCC_MPROC_SIGNAL_SMP2P>; 693 694 qcom,local-pid = <0>; 695 qcom,remote-pid = <3>; 696 697 smp2p_slpi_out: master-kernel { 698 qcom,entry-name = "master-kernel"; 699 #qcom,smem-state-cells = <1>; 700 }; 701 702 smp2p_slpi_in: slave-kernel { 703 qcom,entry-name = "slave-kernel"; 704 interrupt-controller; 705 #interrupt-cells = <2>; 706 }; 707 }; 708 709 soc: soc@0 { 710 #address-cells = <2>; 711 #size-cells = <2>; 712 ranges = <0 0 0 0 0x10 0>; 713 dma-ranges = <0 0 0 0 0x10 0>; 714 compatible = "simple-bus"; 715 716 gcc: clock-controller@100000 { 717 compatible = "qcom,gcc-sm8450"; 718 reg = <0x0 0x00100000 0x0 0x1f4200>; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 #power-domain-cells = <1>; 722 clocks = <&rpmhcc RPMH_CXO_CLK>, 723 <&pcie0_lane>, 724 <&pcie1_lane>, 725 <&sleep_clk>; 726 clock-names = "bi_tcxo", 727 "pcie_0_pipe_clk", 728 "pcie_1_pipe_clk", 729 "sleep_clk"; 730 }; 731 732 gpi_dma2: dma-controller@800000 { 733 compatible = "qcom,sm8450-gpi-dma"; 734 #dma-cells = <3>; 735 reg = <0 0x800000 0 0x60000>; 736 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 748 dma-channels = <12>; 749 dma-channel-mask = <0x7e>; 750 iommus = <&apps_smmu 0x496 0x0>; 751 status = "disabled"; 752 }; 753 754 qupv3_id_2: geniqup@8c0000 { 755 compatible = "qcom,geni-se-qup"; 756 reg = <0x0 0x008c0000 0x0 0x2000>; 757 clock-names = "m-ahb", "s-ahb"; 758 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 759 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 760 iommus = <&apps_smmu 0x483 0x0>; 761 #address-cells = <2>; 762 #size-cells = <2>; 763 ranges; 764 status = "disabled"; 765 766 i2c15: i2c@880000 { 767 compatible = "qcom,geni-i2c"; 768 reg = <0x0 0x00880000 0x0 0x4000>; 769 clock-names = "se"; 770 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&qup_i2c15_data_clk>; 773 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 777 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 778 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 779 interconnect-names = "qup-core", "qup-config", "qup-memory"; 780 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 781 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 782 dma-names = "tx", "rx"; 783 status = "disabled"; 784 }; 785 786 spi15: spi@880000 { 787 compatible = "qcom,geni-spi"; 788 reg = <0x0 0x00880000 0x0 0x4000>; 789 clock-names = "se"; 790 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 791 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 794 spi-max-frequency = <50000000>; 795 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 796 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 797 interconnect-names = "qup-core", "qup-config"; 798 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 799 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 800 dma-names = "tx", "rx"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 i2c16: i2c@884000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0x0 0x00884000 0x0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_i2c16_data_clk>; 813 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 817 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 818 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 819 interconnect-names = "qup-core", "qup-config", "qup-memory"; 820 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 821 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 822 dma-names = "tx", "rx"; 823 status = "disabled"; 824 }; 825 826 spi16: spi@884000 { 827 compatible = "qcom,geni-spi"; 828 reg = <0x0 0x00884000 0x0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 831 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 834 spi-max-frequency = <50000000>; 835 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 836 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 837 interconnect-names = "qup-core", "qup-config"; 838 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 839 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 840 dma-names = "tx", "rx"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 status = "disabled"; 844 }; 845 846 i2c17: i2c@888000 { 847 compatible = "qcom,geni-i2c"; 848 reg = <0x0 0x00888000 0x0 0x4000>; 849 clock-names = "se"; 850 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&qup_i2c17_data_clk>; 853 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 857 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 858 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 859 interconnect-names = "qup-core", "qup-config", "qup-memory"; 860 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 861 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 862 dma-names = "tx", "rx"; 863 status = "disabled"; 864 }; 865 866 spi17: spi@888000 { 867 compatible = "qcom,geni-spi"; 868 reg = <0x0 0x00888000 0x0 0x4000>; 869 clock-names = "se"; 870 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 871 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 874 spi-max-frequency = <50000000>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 879 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 i2c18: i2c@88c000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0x0 0x0088c000 0x0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c18_data_clk>; 893 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 status = "disabled"; 904 }; 905 906 spi18: spi@88c000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x0088c000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 911 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 914 spi-max-frequency = <50000000>; 915 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 916 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 917 interconnect-names = "qup-core", "qup-config"; 918 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 919 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 920 dma-names = "tx", "rx"; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 status = "disabled"; 924 }; 925 926 i2c19: i2c@890000 { 927 compatible = "qcom,geni-i2c"; 928 reg = <0x0 0x00890000 0x0 0x4000>; 929 clock-names = "se"; 930 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_i2c19_data_clk>; 933 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 937 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 938 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 939 interconnect-names = "qup-core", "qup-config", "qup-memory"; 940 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 941 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 942 dma-names = "tx", "rx"; 943 status = "disabled"; 944 }; 945 946 spi19: spi@890000 { 947 compatible = "qcom,geni-spi"; 948 reg = <0 0x00890000 0 0x4000>; 949 clock-names = "se"; 950 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 951 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 954 spi-max-frequency = <50000000>; 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 956 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 957 interconnect-names = "qup-core", "qup-config"; 958 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 959 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 960 dma-names = "tx", "rx"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 i2c20: i2c@894000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0x0 0x00894000 0x0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c20_data_clk>; 973 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 977 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 978 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 979 interconnect-names = "qup-core", "qup-config", "qup-memory"; 980 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 981 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 982 dma-names = "tx", "rx"; 983 status = "disabled"; 984 }; 985 986 uart20: serial@894000 { 987 compatible = "qcom,geni-uart"; 988 reg = <0 0x00894000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&qup_uart20_default>; 993 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi20: spi@894000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x00894000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1004 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1007 spi-max-frequency = <50000000>; 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1009 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1010 interconnect-names = "qup-core", "qup-config"; 1011 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1012 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c21: i2c@898000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0x0 0x00898000 0x0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_i2c21_data_clk>; 1026 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1030 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1031 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1034 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1035 dma-names = "tx", "rx"; 1036 status = "disabled"; 1037 }; 1038 1039 spi21: spi@898000 { 1040 compatible = "qcom,geni-spi"; 1041 reg = <0 0x00898000 0 0x4000>; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1044 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1047 spi-max-frequency = <50000000>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 }; 1059 1060 gpi_dma0: dma-controller@900000 { 1061 compatible = "qcom,sm8450-gpi-dma"; 1062 #dma-cells = <3>; 1063 reg = <0 0x900000 0 0x60000>; 1064 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1076 dma-channels = <12>; 1077 dma-channel-mask = <0x7e>; 1078 iommus = <&apps_smmu 0x5b6 0x0>; 1079 status = "disabled"; 1080 }; 1081 1082 qupv3_id_0: geniqup@9c0000 { 1083 compatible = "qcom,geni-se-qup"; 1084 reg = <0x0 0x009c0000 0x0 0x2000>; 1085 clock-names = "m-ahb", "s-ahb"; 1086 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1087 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1088 iommus = <&apps_smmu 0x5a3 0x0>; 1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1090 interconnect-names = "qup-core"; 1091 #address-cells = <2>; 1092 #size-cells = <2>; 1093 ranges; 1094 status = "disabled"; 1095 1096 i2c0: i2c@980000 { 1097 compatible = "qcom,geni-i2c"; 1098 reg = <0x0 0x00980000 0x0 0x4000>; 1099 clock-names = "se"; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_i2c0_data_clk>; 1103 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1107 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1108 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1109 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1110 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1111 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1112 dma-names = "tx", "rx"; 1113 status = "disabled"; 1114 }; 1115 1116 spi0: spi@980000 { 1117 compatible = "qcom,geni-spi"; 1118 reg = <0x0 0x00980000 0x0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1121 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1124 power-domains = <&rpmhpd SM8450_CX>; 1125 operating-points-v2 = <&qup_opp_table_100mhz>; 1126 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1127 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1128 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1129 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1130 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1131 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1132 dma-names = "tx", "rx"; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c1: i2c@984000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0x0 0x00984000 0x0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_i2c1_data_clk>; 1145 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1150 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1151 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1152 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1153 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1154 dma-names = "tx", "rx"; 1155 status = "disabled"; 1156 }; 1157 1158 spi1: spi@984000 { 1159 compatible = "qcom,geni-spi"; 1160 reg = <0x0 0x00984000 0x0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1163 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1167 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1168 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1169 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1170 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1171 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1172 dma-names = "tx", "rx"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c2: i2c@988000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0x0 0x00988000 0x0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_i2c2_data_clk>; 1185 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1189 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1190 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1191 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1192 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1193 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1194 dma-names = "tx", "rx"; 1195 status = "disabled"; 1196 }; 1197 1198 spi2: spi@988000 { 1199 compatible = "qcom,geni-spi"; 1200 reg = <0x0 0x00988000 0x0 0x4000>; 1201 clock-names = "se"; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1203 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1206 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1207 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1208 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1209 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1210 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1211 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1212 dma-names = "tx", "rx"; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 1219 i2c3: i2c@98c000 { 1220 compatible = "qcom,geni-i2c"; 1221 reg = <0x0 0x0098c000 0x0 0x4000>; 1222 clock-names = "se"; 1223 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_i2c3_data_clk>; 1226 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1230 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1231 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1232 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1233 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1234 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1235 dma-names = "tx", "rx"; 1236 status = "disabled"; 1237 }; 1238 1239 spi3: spi@98c000 { 1240 compatible = "qcom,geni-spi"; 1241 reg = <0x0 0x0098c000 0x0 0x4000>; 1242 clock-names = "se"; 1243 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1244 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1247 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1248 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1249 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1250 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1251 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1252 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1253 dma-names = "tx", "rx"; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 i2c4: i2c@990000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0x0 0x00990000 0x0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_i2c4_data_clk>; 1266 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1270 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1271 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1272 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1273 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1274 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1275 dma-names = "tx", "rx"; 1276 status = "disabled"; 1277 }; 1278 1279 spi4: spi@990000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0x0 0x00990000 0x0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1284 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1287 power-domains = <&rpmhpd SM8450_CX>; 1288 operating-points-v2 = <&qup_opp_table_100mhz>; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1290 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1291 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1294 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1295 dma-names = "tx", "rx"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 i2c5: i2c@994000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0x0 0x00994000 0x0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_i2c5_data_clk>; 1308 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1312 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1313 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1314 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1315 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1316 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1317 dma-names = "tx", "rx"; 1318 status = "disabled"; 1319 }; 1320 1321 spi5: spi@994000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0x0 0x00994000 0x0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1326 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1331 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1333 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1334 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1335 dma-names = "tx", "rx"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 1342 i2c6: i2c@998000 { 1343 compatible = "qcom,geni-i2c"; 1344 reg = <0x0 0x998000 0x0 0x4000>; 1345 clock-names = "se"; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1347 pinctrl-names = "default"; 1348 pinctrl-0 = <&qup_i2c6_data_clk>; 1349 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1354 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1357 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1358 dma-names = "tx", "rx"; 1359 status = "disabled"; 1360 }; 1361 1362 spi6: spi@998000 { 1363 compatible = "qcom,geni-spi"; 1364 reg = <0x0 0x998000 0x0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1367 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1371 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1372 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1374 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1375 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 uart7: serial@99c000 { 1383 compatible = "qcom,geni-debug-uart"; 1384 reg = <0 0x0099c000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1389 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 }; 1395 1396 gpi_dma1: dma-controller@a00000 { 1397 compatible = "qcom,sm8450-gpi-dma"; 1398 #dma-cells = <3>; 1399 reg = <0 0xa00000 0 0x60000>; 1400 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1412 dma-channels = <12>; 1413 dma-channel-mask = <0x7e>; 1414 iommus = <&apps_smmu 0x56 0x0>; 1415 status = "disabled"; 1416 }; 1417 1418 qupv3_id_1: geniqup@ac0000 { 1419 compatible = "qcom,geni-se-qup"; 1420 reg = <0x0 0x00ac0000 0x0 0x6000>; 1421 clock-names = "m-ahb", "s-ahb"; 1422 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1423 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1424 iommus = <&apps_smmu 0x43 0x0>; 1425 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1426 interconnect-names = "qup-core"; 1427 #address-cells = <2>; 1428 #size-cells = <2>; 1429 ranges; 1430 status = "disabled"; 1431 1432 i2c8: i2c@a80000 { 1433 compatible = "qcom,geni-i2c"; 1434 reg = <0x0 0x00a80000 0x0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_i2c8_data_clk>; 1439 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1443 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1444 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1445 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1446 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1447 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1448 dma-names = "tx", "rx"; 1449 status = "disabled"; 1450 }; 1451 1452 spi8: spi@a80000 { 1453 compatible = "qcom,geni-spi"; 1454 reg = <0x0 0x00a80000 0x0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1457 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1460 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1461 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1462 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1463 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1464 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1465 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1466 dma-names = "tx", "rx"; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 status = "disabled"; 1470 }; 1471 1472 i2c9: i2c@a84000 { 1473 compatible = "qcom,geni-i2c"; 1474 reg = <0x0 0x00a84000 0x0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_i2c9_data_clk>; 1479 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1485 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1486 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1487 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1488 dma-names = "tx", "rx"; 1489 status = "disabled"; 1490 }; 1491 1492 spi9: spi@a84000 { 1493 compatible = "qcom,geni-spi"; 1494 reg = <0x0 0x00a84000 0x0 0x4000>; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1497 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1503 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1504 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1505 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1506 dma-names = "tx", "rx"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c10: i2c@a88000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x00a88000 0x0 0x4000>; 1515 clock-names = "se"; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c10_data_clk>; 1519 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi10: spi@a88000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0x0 0x00a88000 0x0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1537 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1543 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1544 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1545 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1546 dma-names = "tx", "rx"; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 i2c11: i2c@a8c000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0x0 0x00a8c000 0x0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_i2c11_data_clk>; 1559 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1565 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1566 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1567 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 spi11: spi@a8c000 { 1573 compatible = "qcom,geni-spi"; 1574 reg = <0x0 0x00a8c000 0x0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1577 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1583 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1584 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1585 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1586 dma-names = "tx", "rx"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c12: i2c@a90000 { 1593 compatible = "qcom,geni-i2c"; 1594 reg = <0x0 0x00a90000 0x0 0x4000>; 1595 clock-names = "se"; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_i2c12_data_clk>; 1599 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1607 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 spi12: spi@a90000 { 1613 compatible = "qcom,geni-spi"; 1614 reg = <0x0 0x00a90000 0x0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1617 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1623 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1624 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1625 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1626 dma-names = "tx", "rx"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c13: i2c@a94000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0 0x00a94000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c13_data_clk>; 1639 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1641 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1642 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1643 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1644 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1645 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1646 dma-names = "tx", "rx"; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 status = "disabled"; 1650 }; 1651 1652 spi13: spi@a94000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0x0 0x00a94000 0x0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1657 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1658 pinctrl-names = "default"; 1659 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1663 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1664 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 i2c14: i2c@a98000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a98000 0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_i2c14_data_clk>; 1679 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1684 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1685 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1686 dma-names = "tx", "rx"; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 spi14: spi@a98000 { 1693 compatible = "qcom,geni-spi"; 1694 reg = <0x0 0x00a98000 0x0 0x4000>; 1695 clock-names = "se"; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1697 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1703 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1704 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1705 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1706 dma-names = "tx", "rx"; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 }; 1712 1713 pcie0: pci@1c00000 { 1714 compatible = "qcom,pcie-sm8450-pcie0"; 1715 reg = <0 0x01c00000 0 0x3000>, 1716 <0 0x60000000 0 0xf1d>, 1717 <0 0x60000f20 0 0xa8>, 1718 <0 0x60001000 0 0x1000>, 1719 <0 0x60100000 0 0x100000>; 1720 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1721 device_type = "pci"; 1722 linux,pci-domain = <0>; 1723 bus-range = <0x00 0xff>; 1724 num-lanes = <1>; 1725 1726 #address-cells = <3>; 1727 #size-cells = <2>; 1728 1729 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1730 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1731 1732 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1733 interrupt-names = "msi"; 1734 #interrupt-cells = <1>; 1735 interrupt-map-mask = <0 0 0 0x7>; 1736 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1737 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1738 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1739 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1740 1741 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1742 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1743 <&pcie0_lane>, 1744 <&rpmhcc RPMH_CXO_CLK>, 1745 <&gcc GCC_PCIE_0_AUX_CLK>, 1746 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1747 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1748 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1749 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1750 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1751 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1752 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1753 clock-names = "pipe", 1754 "pipe_mux", 1755 "phy_pipe", 1756 "ref", 1757 "aux", 1758 "cfg", 1759 "bus_master", 1760 "bus_slave", 1761 "slave_q2a", 1762 "ddrss_sf_tbu", 1763 "aggre0", 1764 "aggre1"; 1765 1766 iommus = <&apps_smmu 0x1c00 0x7f>; 1767 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1768 <0x100 &apps_smmu 0x1c01 0x1>; 1769 1770 resets = <&gcc GCC_PCIE_0_BCR>; 1771 reset-names = "pci"; 1772 1773 power-domains = <&gcc PCIE_0_GDSC>; 1774 power-domain-names = "gdsc"; 1775 1776 phys = <&pcie0_lane>; 1777 phy-names = "pciephy"; 1778 1779 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1780 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1781 1782 pinctrl-names = "default"; 1783 pinctrl-0 = <&pcie0_default_state>; 1784 1785 status = "disabled"; 1786 }; 1787 1788 pcie0_phy: phy@1c06000 { 1789 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1790 reg = <0 0x01c06000 0 0x200>; 1791 #address-cells = <2>; 1792 #size-cells = <2>; 1793 ranges; 1794 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1795 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1796 <&gcc GCC_PCIE_0_CLKREF_EN>, 1797 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1798 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1799 1800 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1801 reset-names = "phy"; 1802 1803 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1804 assigned-clock-rates = <100000000>; 1805 1806 status = "disabled"; 1807 1808 pcie0_lane: phy@1c06200 { 1809 reg = <0 0x1c06e00 0 0x200>, /* tx */ 1810 <0 0x1c07000 0 0x200>, /* rx */ 1811 <0 0x1c06200 0 0x200>, /* pcs */ 1812 <0 0x1c06600 0 0x200>; /* pcs_pcie */ 1813 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1814 clock-names = "pipe0"; 1815 1816 #clock-cells = <0>; 1817 #phy-cells = <0>; 1818 clock-output-names = "pcie_0_pipe_clk"; 1819 }; 1820 }; 1821 1822 pcie1: pci@1c08000 { 1823 compatible = "qcom,pcie-sm8450-pcie1"; 1824 reg = <0 0x01c08000 0 0x3000>, 1825 <0 0x40000000 0 0xf1d>, 1826 <0 0x40000f20 0 0xa8>, 1827 <0 0x40001000 0 0x1000>, 1828 <0 0x40100000 0 0x100000>; 1829 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1830 device_type = "pci"; 1831 linux,pci-domain = <1>; 1832 bus-range = <0x00 0xff>; 1833 num-lanes = <2>; 1834 1835 #address-cells = <3>; 1836 #size-cells = <2>; 1837 1838 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1839 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1840 1841 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1842 interrupt-names = "msi"; 1843 #interrupt-cells = <1>; 1844 interrupt-map-mask = <0 0 0 0x7>; 1845 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1846 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1847 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1848 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1849 1850 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1851 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1852 <&pcie1_lane>, 1853 <&rpmhcc RPMH_CXO_CLK>, 1854 <&gcc GCC_PCIE_1_AUX_CLK>, 1855 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1856 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1857 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1858 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1859 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1860 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1861 clock-names = "pipe", 1862 "pipe_mux", 1863 "phy_pipe", 1864 "ref", 1865 "aux", 1866 "cfg", 1867 "bus_master", 1868 "bus_slave", 1869 "slave_q2a", 1870 "ddrss_sf_tbu", 1871 "aggre1"; 1872 1873 iommus = <&apps_smmu 0x1c80 0x7f>; 1874 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1875 <0x100 &apps_smmu 0x1c81 0x1>; 1876 1877 resets = <&gcc GCC_PCIE_1_BCR>; 1878 reset-names = "pci"; 1879 1880 power-domains = <&gcc PCIE_1_GDSC>; 1881 power-domain-names = "gdsc"; 1882 1883 phys = <&pcie1_lane>; 1884 phy-names = "pciephy"; 1885 1886 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; 1887 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1888 1889 pinctrl-names = "default"; 1890 pinctrl-0 = <&pcie1_default_state>; 1891 1892 status = "disabled"; 1893 }; 1894 1895 pcie1_phy: phy@1c0f000 { 1896 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1897 reg = <0 0x01c0f000 0 0x200>; 1898 #address-cells = <2>; 1899 #size-cells = <2>; 1900 ranges; 1901 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1902 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1903 <&gcc GCC_PCIE_1_CLKREF_EN>, 1904 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1905 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1906 1907 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1908 reset-names = "phy"; 1909 1910 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1911 assigned-clock-rates = <100000000>; 1912 1913 status = "disabled"; 1914 1915 pcie1_lane: phy@1c0e000 { 1916 reg = <0 0x1c0e000 0 0x200>, /* tx */ 1917 <0 0x1c0e200 0 0x300>, /* rx */ 1918 <0 0x1c0f200 0 0x200>, /* pcs */ 1919 <0 0x1c0e800 0 0x200>, /* tx */ 1920 <0 0x1c0ea00 0 0x300>, /* rx */ 1921 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ 1922 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1923 clock-names = "pipe0"; 1924 1925 #clock-cells = <0>; 1926 #phy-cells = <0>; 1927 clock-output-names = "pcie_1_pipe_clk"; 1928 }; 1929 }; 1930 1931 config_noc: interconnect@1500000 { 1932 compatible = "qcom,sm8450-config-noc"; 1933 reg = <0 0x01500000 0 0x1c000>; 1934 #interconnect-cells = <2>; 1935 qcom,bcm-voters = <&apps_bcm_voter>; 1936 }; 1937 1938 system_noc: interconnect@1680000 { 1939 compatible = "qcom,sm8450-system-noc"; 1940 reg = <0 0x01680000 0 0x1e200>; 1941 #interconnect-cells = <2>; 1942 qcom,bcm-voters = <&apps_bcm_voter>; 1943 }; 1944 1945 pcie_noc: interconnect@16c0000 { 1946 compatible = "qcom,sm8450-pcie-anoc"; 1947 reg = <0 0x016c0000 0 0xe280>; 1948 #interconnect-cells = <2>; 1949 qcom,bcm-voters = <&apps_bcm_voter>; 1950 }; 1951 1952 aggre1_noc: interconnect@16e0000 { 1953 compatible = "qcom,sm8450-aggre1-noc"; 1954 reg = <0 0x016e0000 0 0x1c080>; 1955 #interconnect-cells = <2>; 1956 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1957 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1958 qcom,bcm-voters = <&apps_bcm_voter>; 1959 }; 1960 1961 aggre2_noc: interconnect@1700000 { 1962 compatible = "qcom,sm8450-aggre2-noc"; 1963 reg = <0 0x01700000 0 0x31080>; 1964 #interconnect-cells = <2>; 1965 qcom,bcm-voters = <&apps_bcm_voter>; 1966 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1967 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1968 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1969 <&rpmhcc RPMH_IPA_CLK>; 1970 }; 1971 1972 mmss_noc: interconnect@1740000 { 1973 compatible = "qcom,sm8450-mmss-noc"; 1974 reg = <0 0x01740000 0 0x1f080>; 1975 #interconnect-cells = <2>; 1976 qcom,bcm-voters = <&apps_bcm_voter>; 1977 }; 1978 1979 tcsr_mutex: hwlock@1f40000 { 1980 compatible = "qcom,tcsr-mutex"; 1981 reg = <0x0 0x01f40000 0x0 0x40000>; 1982 #hwlock-cells = <1>; 1983 }; 1984 1985 usb_1_hsphy: phy@88e3000 { 1986 compatible = "qcom,sm8450-usb-hs-phy", 1987 "qcom,usb-snps-hs-7nm-phy"; 1988 reg = <0 0x088e3000 0 0x400>; 1989 status = "disabled"; 1990 #phy-cells = <0>; 1991 1992 clocks = <&rpmhcc RPMH_CXO_CLK>; 1993 clock-names = "ref"; 1994 1995 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1996 }; 1997 1998 usb_1_qmpphy: phy-wrapper@88e9000 { 1999 compatible = "qcom,sm8450-qmp-usb3-phy"; 2000 reg = <0 0x088e9000 0 0x200>, 2001 <0 0x088e8000 0 0x20>; 2002 status = "disabled"; 2003 #address-cells = <2>; 2004 #size-cells = <2>; 2005 ranges; 2006 2007 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2008 <&rpmhcc RPMH_CXO_CLK>, 2009 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2010 clock-names = "aux", "ref_clk_src", "com_aux"; 2011 2012 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2013 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2014 reset-names = "phy", "common"; 2015 2016 usb_1_ssphy: phy@88e9200 { 2017 reg = <0 0x088e9200 0 0x200>, 2018 <0 0x088e9400 0 0x200>, 2019 <0 0x088e9c00 0 0x400>, 2020 <0 0x088e9600 0 0x200>, 2021 <0 0x088e9800 0 0x200>, 2022 <0 0x088e9a00 0 0x100>; 2023 #phy-cells = <0>; 2024 #clock-cells = <0>; 2025 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2026 clock-names = "pipe0"; 2027 clock-output-names = "usb3_phy_pipe_clk_src"; 2028 }; 2029 }; 2030 2031 remoteproc_slpi: remoteproc@2400000 { 2032 compatible = "qcom,sm8450-slpi-pas"; 2033 reg = <0 0x02400000 0 0x4000>; 2034 2035 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2036 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2037 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2038 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2039 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2040 interrupt-names = "wdog", "fatal", "ready", 2041 "handover", "stop-ack"; 2042 2043 clocks = <&rpmhcc RPMH_CXO_CLK>; 2044 clock-names = "xo"; 2045 2046 power-domains = <&rpmhpd SM8450_LCX>, 2047 <&rpmhpd SM8450_LMX>; 2048 power-domain-names = "lcx", "lmx"; 2049 2050 memory-region = <&slpi_mem>; 2051 2052 qcom,qmp = <&aoss_qmp>; 2053 2054 qcom,smem-states = <&smp2p_slpi_out 0>; 2055 qcom,smem-state-names = "stop"; 2056 2057 status = "disabled"; 2058 2059 glink-edge { 2060 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2061 IPCC_MPROC_SIGNAL_GLINK_QMP 2062 IRQ_TYPE_EDGE_RISING>; 2063 mboxes = <&ipcc IPCC_CLIENT_SLPI 2064 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2065 2066 label = "slpi"; 2067 qcom,remote-pid = <3>; 2068 2069 fastrpc { 2070 compatible = "qcom,fastrpc"; 2071 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2072 label = "sdsp"; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 2076 compute-cb@1 { 2077 compatible = "qcom,fastrpc-compute-cb"; 2078 reg = <1>; 2079 iommus = <&apps_smmu 0x0541 0x0>; 2080 }; 2081 2082 compute-cb@2 { 2083 compatible = "qcom,fastrpc-compute-cb"; 2084 reg = <2>; 2085 iommus = <&apps_smmu 0x0542 0x0>; 2086 }; 2087 2088 compute-cb@3 { 2089 compatible = "qcom,fastrpc-compute-cb"; 2090 reg = <3>; 2091 iommus = <&apps_smmu 0x0543 0x0>; 2092 /* note: shared-cb = <4> in downstream */ 2093 }; 2094 }; 2095 }; 2096 }; 2097 2098 remoteproc_adsp: remoteproc@30000000 { 2099 compatible = "qcom,sm8450-adsp-pas"; 2100 reg = <0 0x030000000 0 0x100>; 2101 2102 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2103 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2104 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2105 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2106 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2107 interrupt-names = "wdog", "fatal", "ready", 2108 "handover", "stop-ack"; 2109 2110 clocks = <&rpmhcc RPMH_CXO_CLK>; 2111 clock-names = "xo"; 2112 2113 power-domains = <&rpmhpd SM8450_LCX>, 2114 <&rpmhpd SM8450_LMX>; 2115 power-domain-names = "lcx", "lmx"; 2116 2117 memory-region = <&adsp_mem>; 2118 2119 qcom,qmp = <&aoss_qmp>; 2120 2121 qcom,smem-states = <&smp2p_adsp_out 0>; 2122 qcom,smem-state-names = "stop"; 2123 2124 status = "disabled"; 2125 2126 remoteproc_adsp_glink: glink-edge { 2127 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2128 IPCC_MPROC_SIGNAL_GLINK_QMP 2129 IRQ_TYPE_EDGE_RISING>; 2130 mboxes = <&ipcc IPCC_CLIENT_LPASS 2131 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2132 2133 label = "lpass"; 2134 qcom,remote-pid = <2>; 2135 2136 fastrpc { 2137 compatible = "qcom,fastrpc"; 2138 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2139 label = "adsp"; 2140 #address-cells = <1>; 2141 #size-cells = <0>; 2142 2143 compute-cb@3 { 2144 compatible = "qcom,fastrpc-compute-cb"; 2145 reg = <3>; 2146 iommus = <&apps_smmu 0x1803 0x0>; 2147 }; 2148 2149 compute-cb@4 { 2150 compatible = "qcom,fastrpc-compute-cb"; 2151 reg = <4>; 2152 iommus = <&apps_smmu 0x1804 0x0>; 2153 }; 2154 2155 compute-cb@5 { 2156 compatible = "qcom,fastrpc-compute-cb"; 2157 reg = <5>; 2158 iommus = <&apps_smmu 0x1805 0x0>; 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 remoteproc_cdsp: remoteproc@32300000 { 2165 compatible = "qcom,sm8450-cdsp-pas"; 2166 reg = <0 0x032300000 0 0x1400000>; 2167 2168 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2169 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2170 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2171 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2172 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2173 interrupt-names = "wdog", "fatal", "ready", 2174 "handover", "stop-ack"; 2175 2176 clocks = <&rpmhcc RPMH_CXO_CLK>; 2177 clock-names = "xo"; 2178 2179 power-domains = <&rpmhpd SM8450_CX>, 2180 <&rpmhpd SM8450_MXC>; 2181 power-domain-names = "cx", "mxc"; 2182 2183 memory-region = <&cdsp_mem>; 2184 2185 qcom,qmp = <&aoss_qmp>; 2186 2187 qcom,smem-states = <&smp2p_cdsp_out 0>; 2188 qcom,smem-state-names = "stop"; 2189 2190 status = "disabled"; 2191 2192 glink-edge { 2193 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2194 IPCC_MPROC_SIGNAL_GLINK_QMP 2195 IRQ_TYPE_EDGE_RISING>; 2196 mboxes = <&ipcc IPCC_CLIENT_CDSP 2197 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2198 2199 label = "cdsp"; 2200 qcom,remote-pid = <5>; 2201 2202 fastrpc { 2203 compatible = "qcom,fastrpc"; 2204 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2205 label = "cdsp"; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 compute-cb@1 { 2210 compatible = "qcom,fastrpc-compute-cb"; 2211 reg = <1>; 2212 iommus = <&apps_smmu 0x2161 0x0400>, 2213 <&apps_smmu 0x1021 0x1420>; 2214 }; 2215 2216 compute-cb@2 { 2217 compatible = "qcom,fastrpc-compute-cb"; 2218 reg = <2>; 2219 iommus = <&apps_smmu 0x2162 0x0400>, 2220 <&apps_smmu 0x1022 0x1420>; 2221 }; 2222 2223 compute-cb@3 { 2224 compatible = "qcom,fastrpc-compute-cb"; 2225 reg = <3>; 2226 iommus = <&apps_smmu 0x2163 0x0400>, 2227 <&apps_smmu 0x1023 0x1420>; 2228 }; 2229 2230 compute-cb@4 { 2231 compatible = "qcom,fastrpc-compute-cb"; 2232 reg = <4>; 2233 iommus = <&apps_smmu 0x2164 0x0400>, 2234 <&apps_smmu 0x1024 0x1420>; 2235 }; 2236 2237 compute-cb@5 { 2238 compatible = "qcom,fastrpc-compute-cb"; 2239 reg = <5>; 2240 iommus = <&apps_smmu 0x2165 0x0400>, 2241 <&apps_smmu 0x1025 0x1420>; 2242 }; 2243 2244 compute-cb@6 { 2245 compatible = "qcom,fastrpc-compute-cb"; 2246 reg = <6>; 2247 iommus = <&apps_smmu 0x2166 0x0400>, 2248 <&apps_smmu 0x1026 0x1420>; 2249 }; 2250 2251 compute-cb@7 { 2252 compatible = "qcom,fastrpc-compute-cb"; 2253 reg = <7>; 2254 iommus = <&apps_smmu 0x2167 0x0400>, 2255 <&apps_smmu 0x1027 0x1420>; 2256 }; 2257 2258 compute-cb@8 { 2259 compatible = "qcom,fastrpc-compute-cb"; 2260 reg = <8>; 2261 iommus = <&apps_smmu 0x2168 0x0400>, 2262 <&apps_smmu 0x1028 0x1420>; 2263 }; 2264 2265 /* note: secure cb9 in downstream */ 2266 }; 2267 }; 2268 }; 2269 2270 remoteproc_mpss: remoteproc@4080000 { 2271 compatible = "qcom,sm8450-mpss-pas"; 2272 reg = <0x0 0x04080000 0x0 0x4040>; 2273 2274 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2275 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2276 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2277 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2278 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2279 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2280 interrupt-names = "wdog", "fatal", "ready", "handover", 2281 "stop-ack", "shutdown-ack"; 2282 2283 clocks = <&rpmhcc RPMH_CXO_CLK>; 2284 clock-names = "xo"; 2285 2286 power-domains = <&rpmhpd 0>, 2287 <&rpmhpd 12>; 2288 power-domain-names = "cx", "mss"; 2289 2290 memory-region = <&mpss_mem>; 2291 2292 qcom,qmp = <&aoss_qmp>; 2293 2294 qcom,smem-states = <&smp2p_modem_out 0>; 2295 qcom,smem-state-names = "stop"; 2296 2297 status = "disabled"; 2298 2299 glink-edge { 2300 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2301 IPCC_MPROC_SIGNAL_GLINK_QMP 2302 IRQ_TYPE_EDGE_RISING>; 2303 mboxes = <&ipcc IPCC_CLIENT_MPSS 2304 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2305 label = "modem"; 2306 qcom,remote-pid = <1>; 2307 }; 2308 }; 2309 2310 camcc: clock-controller@ade0000 { 2311 compatible = "qcom,sm8450-camcc"; 2312 reg = <0 0x0ade0000 0 0x20000>; 2313 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2314 <&rpmhcc RPMH_CXO_CLK>, 2315 <&rpmhcc RPMH_CXO_CLK_A>, 2316 <&sleep_clk>; 2317 power-domains = <&rpmhpd SM8450_MMCX>; 2318 required-opps = <&rpmhpd_opp_low_svs>; 2319 #clock-cells = <1>; 2320 #reset-cells = <1>; 2321 #power-domain-cells = <1>; 2322 status = "disabled"; 2323 }; 2324 2325 pdc: interrupt-controller@b220000 { 2326 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 2327 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2328 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 2329 <94 609 31>, <125 63 1>, <126 716 12>; 2330 #interrupt-cells = <2>; 2331 interrupt-parent = <&intc>; 2332 interrupt-controller; 2333 }; 2334 2335 tsens0: thermal-sensor@c263000 { 2336 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 2337 reg = <0 0x0c263000 0 0x1000>, /* TM */ 2338 <0 0x0c222000 0 0x1000>; /* SROT */ 2339 #qcom,sensors = <16>; 2340 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2341 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2342 interrupt-names = "uplow", "critical"; 2343 #thermal-sensor-cells = <1>; 2344 }; 2345 2346 tsens1: thermal-sensor@c265000 { 2347 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 2348 reg = <0 0x0c265000 0 0x1000>, /* TM */ 2349 <0 0x0c223000 0 0x1000>; /* SROT */ 2350 #qcom,sensors = <16>; 2351 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2353 interrupt-names = "uplow", "critical"; 2354 #thermal-sensor-cells = <1>; 2355 }; 2356 2357 aoss_qmp: power-controller@c300000 { 2358 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 2359 reg = <0 0x0c300000 0 0x400>; 2360 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2361 IRQ_TYPE_EDGE_RISING>; 2362 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2363 2364 #clock-cells = <0>; 2365 }; 2366 2367 ipcc: mailbox@ed18000 { 2368 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 2369 reg = <0 0x0ed18000 0 0x1000>; 2370 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2371 interrupt-controller; 2372 #interrupt-cells = <3>; 2373 #mbox-cells = <2>; 2374 }; 2375 2376 tlmm: pinctrl@f100000 { 2377 compatible = "qcom,sm8450-tlmm"; 2378 reg = <0 0x0f100000 0 0x300000>; 2379 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2380 gpio-controller; 2381 #gpio-cells = <2>; 2382 interrupt-controller; 2383 #interrupt-cells = <2>; 2384 gpio-ranges = <&tlmm 0 0 211>; 2385 wakeup-parent = <&pdc>; 2386 2387 sdc2_sleep_state: sdc2-sleep-state { 2388 clk-pins { 2389 pins = "sdc2_clk"; 2390 drive-strength = <2>; 2391 bias-disable; 2392 }; 2393 2394 cmd-pins { 2395 pins = "sdc2_cmd"; 2396 drive-strength = <2>; 2397 bias-pull-up; 2398 }; 2399 2400 data-pins { 2401 pins = "sdc2_data"; 2402 drive-strength = <2>; 2403 bias-pull-up; 2404 }; 2405 }; 2406 2407 pcie0_default_state: pcie0-default-state { 2408 perst-pins { 2409 pins = "gpio94"; 2410 function = "gpio"; 2411 drive-strength = <2>; 2412 bias-pull-down; 2413 }; 2414 2415 clkreq-pins { 2416 pins = "gpio95"; 2417 function = "pcie0_clkreqn"; 2418 drive-strength = <2>; 2419 bias-pull-up; 2420 }; 2421 2422 wake-pins { 2423 pins = "gpio96"; 2424 function = "gpio"; 2425 drive-strength = <2>; 2426 bias-pull-up; 2427 }; 2428 }; 2429 2430 pcie1_default_state: pcie1-default-state { 2431 perst-pins { 2432 pins = "gpio97"; 2433 function = "gpio"; 2434 drive-strength = <2>; 2435 bias-pull-down; 2436 }; 2437 2438 clkreq-pins { 2439 pins = "gpio98"; 2440 function = "pcie1_clkreqn"; 2441 drive-strength = <2>; 2442 bias-pull-up; 2443 }; 2444 2445 wake-pins { 2446 pins = "gpio99"; 2447 function = "gpio"; 2448 drive-strength = <2>; 2449 bias-pull-up; 2450 }; 2451 }; 2452 2453 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2454 pins = "gpio0", "gpio1"; 2455 function = "qup0"; 2456 }; 2457 2458 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2459 pins = "gpio4", "gpio5"; 2460 function = "qup1"; 2461 }; 2462 2463 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2464 pins = "gpio8", "gpio9"; 2465 function = "qup2"; 2466 }; 2467 2468 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2469 pins = "gpio12", "gpio13"; 2470 function = "qup3"; 2471 }; 2472 2473 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2474 pins = "gpio16", "gpio17"; 2475 function = "qup4"; 2476 }; 2477 2478 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2479 pins = "gpio206", "gpio207"; 2480 function = "qup5"; 2481 }; 2482 2483 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2484 pins = "gpio20", "gpio21"; 2485 function = "qup6"; 2486 }; 2487 2488 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2489 pins = "gpio28", "gpio29"; 2490 function = "qup8"; 2491 }; 2492 2493 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2494 pins = "gpio32", "gpio33"; 2495 function = "qup9"; 2496 }; 2497 2498 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2499 pins = "gpio36", "gpio37"; 2500 function = "qup10"; 2501 }; 2502 2503 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2504 pins = "gpio40", "gpio41"; 2505 function = "qup11"; 2506 }; 2507 2508 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2509 pins = "gpio44", "gpio45"; 2510 function = "qup12"; 2511 }; 2512 2513 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2514 pins = "gpio48", "gpio49"; 2515 function = "qup13"; 2516 drive-strength = <2>; 2517 bias-pull-up; 2518 }; 2519 2520 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 2521 pins = "gpio52", "gpio53"; 2522 function = "qup14"; 2523 drive-strength = <2>; 2524 bias-pull-up; 2525 }; 2526 2527 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2528 pins = "gpio56", "gpio57"; 2529 function = "qup15"; 2530 }; 2531 2532 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 2533 pins = "gpio60", "gpio61"; 2534 function = "qup16"; 2535 }; 2536 2537 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 2538 pins = "gpio64", "gpio65"; 2539 function = "qup17"; 2540 }; 2541 2542 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 2543 pins = "gpio68", "gpio69"; 2544 function = "qup18"; 2545 }; 2546 2547 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 2548 pins = "gpio72", "gpio73"; 2549 function = "qup19"; 2550 }; 2551 2552 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 2553 pins = "gpio76", "gpio77"; 2554 function = "qup20"; 2555 }; 2556 2557 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 2558 pins = "gpio80", "gpio81"; 2559 function = "qup21"; 2560 }; 2561 2562 qup_spi0_cs: qup-spi0-cs-state { 2563 pins = "gpio3"; 2564 function = "qup0"; 2565 }; 2566 2567 qup_spi0_data_clk: qup-spi0-data-clk-state { 2568 pins = "gpio0", "gpio1", "gpio2"; 2569 function = "qup0"; 2570 }; 2571 2572 qup_spi1_cs: qup-spi1-cs-state { 2573 pins = "gpio7"; 2574 function = "qup1"; 2575 }; 2576 2577 qup_spi1_data_clk: qup-spi1-data-clk-state { 2578 pins = "gpio4", "gpio5", "gpio6"; 2579 function = "qup1"; 2580 }; 2581 2582 qup_spi2_cs: qup-spi2-cs-state { 2583 pins = "gpio11"; 2584 function = "qup2"; 2585 }; 2586 2587 qup_spi2_data_clk: qup-spi2-data-clk-state { 2588 pins = "gpio8", "gpio9", "gpio10"; 2589 function = "qup2"; 2590 }; 2591 2592 qup_spi3_cs: qup-spi3-cs-state { 2593 pins = "gpio15"; 2594 function = "qup3"; 2595 }; 2596 2597 qup_spi3_data_clk: qup-spi3-data-clk-state { 2598 pins = "gpio12", "gpio13", "gpio14"; 2599 function = "qup3"; 2600 }; 2601 2602 qup_spi4_cs: qup-spi4-cs-state { 2603 pins = "gpio19"; 2604 function = "qup4"; 2605 drive-strength = <6>; 2606 bias-disable; 2607 }; 2608 2609 qup_spi4_data_clk: qup-spi4-data-clk-state { 2610 pins = "gpio16", "gpio17", "gpio18"; 2611 function = "qup4"; 2612 }; 2613 2614 qup_spi5_cs: qup-spi5-cs-state { 2615 pins = "gpio85"; 2616 function = "qup5"; 2617 }; 2618 2619 qup_spi5_data_clk: qup-spi5-data-clk-state { 2620 pins = "gpio206", "gpio207", "gpio84"; 2621 function = "qup5"; 2622 }; 2623 2624 qup_spi6_cs: qup-spi6-cs-state { 2625 pins = "gpio23"; 2626 function = "qup6"; 2627 }; 2628 2629 qup_spi6_data_clk: qup-spi6-data-clk-state { 2630 pins = "gpio20", "gpio21", "gpio22"; 2631 function = "qup6"; 2632 }; 2633 2634 qup_spi8_cs: qup-spi8-cs-state { 2635 pins = "gpio31"; 2636 function = "qup8"; 2637 }; 2638 2639 qup_spi8_data_clk: qup-spi8-data-clk-state { 2640 pins = "gpio28", "gpio29", "gpio30"; 2641 function = "qup8"; 2642 }; 2643 2644 qup_spi9_cs: qup-spi9-cs-state { 2645 pins = "gpio35"; 2646 function = "qup9"; 2647 }; 2648 2649 qup_spi9_data_clk: qup-spi9-data-clk-state { 2650 pins = "gpio32", "gpio33", "gpio34"; 2651 function = "qup9"; 2652 }; 2653 2654 qup_spi10_cs: qup-spi10-cs-state { 2655 pins = "gpio39"; 2656 function = "qup10"; 2657 }; 2658 2659 qup_spi10_data_clk: qup-spi10-data-clk-state { 2660 pins = "gpio36", "gpio37", "gpio38"; 2661 function = "qup10"; 2662 }; 2663 2664 qup_spi11_cs: qup-spi11-cs-state { 2665 pins = "gpio43"; 2666 function = "qup11"; 2667 }; 2668 2669 qup_spi11_data_clk: qup-spi11-data-clk-state { 2670 pins = "gpio40", "gpio41", "gpio42"; 2671 function = "qup11"; 2672 }; 2673 2674 qup_spi12_cs: qup-spi12-cs-state { 2675 pins = "gpio47"; 2676 function = "qup12"; 2677 }; 2678 2679 qup_spi12_data_clk: qup-spi12-data-clk-state { 2680 pins = "gpio44", "gpio45", "gpio46"; 2681 function = "qup12"; 2682 }; 2683 2684 qup_spi13_cs: qup-spi13-cs-state { 2685 pins = "gpio51"; 2686 function = "qup13"; 2687 }; 2688 2689 qup_spi13_data_clk: qup-spi13-data-clk-state { 2690 pins = "gpio48", "gpio49", "gpio50"; 2691 function = "qup13"; 2692 }; 2693 2694 qup_spi14_cs: qup-spi14-cs-state { 2695 pins = "gpio55"; 2696 function = "qup14"; 2697 }; 2698 2699 qup_spi14_data_clk: qup-spi14-data-clk-state { 2700 pins = "gpio52", "gpio53", "gpio54"; 2701 function = "qup14"; 2702 }; 2703 2704 qup_spi15_cs: qup-spi15-cs-state { 2705 pins = "gpio59"; 2706 function = "qup15"; 2707 }; 2708 2709 qup_spi15_data_clk: qup-spi15-data-clk-state { 2710 pins = "gpio56", "gpio57", "gpio58"; 2711 function = "qup15"; 2712 }; 2713 2714 qup_spi16_cs: qup-spi16-cs-state { 2715 pins = "gpio63"; 2716 function = "qup16"; 2717 }; 2718 2719 qup_spi16_data_clk: qup-spi16-data-clk-state { 2720 pins = "gpio60", "gpio61", "gpio62"; 2721 function = "qup16"; 2722 }; 2723 2724 qup_spi17_cs: qup-spi17-cs-state { 2725 pins = "gpio67"; 2726 function = "qup17"; 2727 }; 2728 2729 qup_spi17_data_clk: qup-spi17-data-clk-state { 2730 pins = "gpio64", "gpio65", "gpio66"; 2731 function = "qup17"; 2732 }; 2733 2734 qup_spi18_cs: qup-spi18-cs-state { 2735 pins = "gpio71"; 2736 function = "qup18"; 2737 drive-strength = <6>; 2738 bias-disable; 2739 }; 2740 2741 qup_spi18_data_clk: qup-spi18-data-clk-state { 2742 pins = "gpio68", "gpio69", "gpio70"; 2743 function = "qup18"; 2744 drive-strength = <6>; 2745 bias-disable; 2746 }; 2747 2748 qup_spi19_cs: qup-spi19-cs-state { 2749 pins = "gpio75"; 2750 function = "qup19"; 2751 drive-strength = <6>; 2752 bias-disable; 2753 }; 2754 2755 qup_spi19_data_clk: qup-spi19-data-clk-state { 2756 pins = "gpio72", "gpio73", "gpio74"; 2757 function = "qup19"; 2758 drive-strength = <6>; 2759 bias-disable; 2760 }; 2761 2762 qup_spi20_cs: qup-spi20-cs-state { 2763 pins = "gpio79"; 2764 function = "qup20"; 2765 }; 2766 2767 qup_spi20_data_clk: qup-spi20-data-clk-state { 2768 pins = "gpio76", "gpio77", "gpio78"; 2769 function = "qup20"; 2770 }; 2771 2772 qup_spi21_cs: qup-spi21-cs-state { 2773 pins = "gpio83"; 2774 function = "qup21"; 2775 }; 2776 2777 qup_spi21_data_clk: qup-spi21-data-clk-state { 2778 pins = "gpio80", "gpio81", "gpio82"; 2779 function = "qup21"; 2780 }; 2781 2782 qup_uart7_rx: qup-uart7-rx-state { 2783 pins = "gpio26"; 2784 function = "qup7"; 2785 drive-strength = <2>; 2786 bias-disable; 2787 }; 2788 2789 qup_uart7_tx: qup-uart7-tx-state { 2790 pins = "gpio27"; 2791 function = "qup7"; 2792 drive-strength = <2>; 2793 bias-disable; 2794 }; 2795 2796 qup_uart20_default: qup-uart20-default-state { 2797 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 2798 function = "qup20"; 2799 }; 2800 2801 }; 2802 2803 apps_smmu: iommu@15000000 { 2804 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 2805 reg = <0 0x15000000 0 0x100000>; 2806 #iommu-cells = <2>; 2807 #global-interrupts = <1>; 2808 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2814 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2817 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2819 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2820 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2821 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2823 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2824 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2825 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2826 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2827 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2828 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2829 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2830 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2832 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2836 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2839 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2840 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2842 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2843 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2848 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2849 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2854 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2855 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2856 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2857 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2858 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2859 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2860 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2861 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2862 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2863 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2866 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2867 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2868 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2869 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2870 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2871 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2872 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2873 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2874 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2875 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2879 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2881 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2885 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2886 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2890 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 2905 }; 2906 2907 intc: interrupt-controller@17100000 { 2908 compatible = "arm,gic-v3"; 2909 #interrupt-cells = <3>; 2910 interrupt-controller; 2911 #redistributor-regions = <1>; 2912 redistributor-stride = <0x0 0x40000>; 2913 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 2914 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 2915 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2916 #address-cells = <2>; 2917 #size-cells = <2>; 2918 ranges; 2919 2920 gic_its: msi-controller@17140000 { 2921 compatible = "arm,gic-v3-its"; 2922 reg = <0x0 0x17140000 0x0 0x20000>; 2923 msi-controller; 2924 #msi-cells = <1>; 2925 }; 2926 }; 2927 2928 timer@17420000 { 2929 compatible = "arm,armv7-timer-mem"; 2930 #address-cells = <1>; 2931 #size-cells = <1>; 2932 ranges = <0 0 0 0x20000000>; 2933 reg = <0x0 0x17420000 0x0 0x1000>; 2934 clock-frequency = <19200000>; 2935 2936 frame@17421000 { 2937 frame-number = <0>; 2938 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2940 reg = <0x17421000 0x1000>, 2941 <0x17422000 0x1000>; 2942 }; 2943 2944 frame@17423000 { 2945 frame-number = <1>; 2946 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2947 reg = <0x17423000 0x1000>; 2948 status = "disabled"; 2949 }; 2950 2951 frame@17425000 { 2952 frame-number = <2>; 2953 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2954 reg = <0x17425000 0x1000>; 2955 status = "disabled"; 2956 }; 2957 2958 frame@17427000 { 2959 frame-number = <3>; 2960 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2961 reg = <0x17427000 0x1000>; 2962 status = "disabled"; 2963 }; 2964 2965 frame@17429000 { 2966 frame-number = <4>; 2967 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2968 reg = <0x17429000 0x1000>; 2969 status = "disabled"; 2970 }; 2971 2972 frame@1742b000 { 2973 frame-number = <5>; 2974 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2975 reg = <0x1742b000 0x1000>; 2976 status = "disabled"; 2977 }; 2978 2979 frame@1742d000 { 2980 frame-number = <6>; 2981 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2982 reg = <0x1742d000 0x1000>; 2983 status = "disabled"; 2984 }; 2985 }; 2986 2987 apps_rsc: rsc@17a00000 { 2988 label = "apps_rsc"; 2989 compatible = "qcom,rpmh-rsc"; 2990 reg = <0x0 0x17a00000 0x0 0x10000>, 2991 <0x0 0x17a10000 0x0 0x10000>, 2992 <0x0 0x17a20000 0x0 0x10000>, 2993 <0x0 0x17a30000 0x0 0x10000>; 2994 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 2995 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2996 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2997 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2998 qcom,tcs-offset = <0xd00>; 2999 qcom,drv-id = <2>; 3000 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3001 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3002 3003 apps_bcm_voter: bcm-voter { 3004 compatible = "qcom,bcm-voter"; 3005 }; 3006 3007 rpmhcc: clock-controller { 3008 compatible = "qcom,sm8450-rpmh-clk"; 3009 #clock-cells = <1>; 3010 clock-names = "xo"; 3011 clocks = <&xo_board>; 3012 }; 3013 3014 rpmhpd: power-controller { 3015 compatible = "qcom,sm8450-rpmhpd"; 3016 #power-domain-cells = <1>; 3017 operating-points-v2 = <&rpmhpd_opp_table>; 3018 3019 rpmhpd_opp_table: opp-table { 3020 compatible = "operating-points-v2"; 3021 3022 rpmhpd_opp_ret: opp1 { 3023 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3024 }; 3025 3026 rpmhpd_opp_min_svs: opp2 { 3027 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3028 }; 3029 3030 rpmhpd_opp_low_svs: opp3 { 3031 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3032 }; 3033 3034 rpmhpd_opp_svs: opp4 { 3035 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3036 }; 3037 3038 rpmhpd_opp_svs_l1: opp5 { 3039 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3040 }; 3041 3042 rpmhpd_opp_nom: opp6 { 3043 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3044 }; 3045 3046 rpmhpd_opp_nom_l1: opp7 { 3047 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3048 }; 3049 3050 rpmhpd_opp_nom_l2: opp8 { 3051 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3052 }; 3053 3054 rpmhpd_opp_turbo: opp9 { 3055 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3056 }; 3057 3058 rpmhpd_opp_turbo_l1: opp10 { 3059 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3060 }; 3061 }; 3062 }; 3063 }; 3064 3065 cpufreq_hw: cpufreq@17d91000 { 3066 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 3067 reg = <0 0x17d91000 0 0x1000>, 3068 <0 0x17d92000 0 0x1000>, 3069 <0 0x17d93000 0 0x1000>; 3070 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3071 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3072 clock-names = "xo", "alternate"; 3073 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3076 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3077 #freq-domain-cells = <1>; 3078 }; 3079 3080 gem_noc: interconnect@19100000 { 3081 compatible = "qcom,sm8450-gem-noc"; 3082 reg = <0 0x19100000 0 0xbb800>; 3083 #interconnect-cells = <2>; 3084 qcom,bcm-voters = <&apps_bcm_voter>; 3085 }; 3086 3087 system-cache-controller@19200000 { 3088 compatible = "qcom,sm8450-llcc"; 3089 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; 3090 reg-names = "llcc_base", "llcc_broadcast_base"; 3091 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3092 }; 3093 3094 ufs_mem_hc: ufshc@1d84000 { 3095 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 3096 "jedec,ufs-2.0"; 3097 reg = <0 0x01d84000 0 0x3000>, 3098 <0 0x01d88000 0 0x8000>; 3099 reg-names = "std", "ice"; 3100 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3101 phys = <&ufs_mem_phy_lanes>; 3102 phy-names = "ufsphy"; 3103 lanes-per-direction = <2>; 3104 #reset-cells = <1>; 3105 resets = <&gcc GCC_UFS_PHY_BCR>; 3106 reset-names = "rst"; 3107 3108 power-domains = <&gcc UFS_PHY_GDSC>; 3109 3110 iommus = <&apps_smmu 0xe0 0x0>; 3111 3112 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 3113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 3114 interconnect-names = "ufs-ddr", "cpu-ufs"; 3115 clock-names = 3116 "core_clk", 3117 "bus_aggr_clk", 3118 "iface_clk", 3119 "core_clk_unipro", 3120 "ref_clk", 3121 "tx_lane0_sync_clk", 3122 "rx_lane0_sync_clk", 3123 "rx_lane1_sync_clk", 3124 "ice_core_clk"; 3125 clocks = 3126 <&gcc GCC_UFS_PHY_AXI_CLK>, 3127 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3128 <&gcc GCC_UFS_PHY_AHB_CLK>, 3129 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3130 <&rpmhcc RPMH_CXO_CLK>, 3131 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3132 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3133 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 3134 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 3135 freq-table-hz = 3136 <75000000 300000000>, 3137 <0 0>, 3138 <0 0>, 3139 <75000000 300000000>, 3140 <75000000 300000000>, 3141 <0 0>, 3142 <0 0>, 3143 <0 0>, 3144 <75000000 300000000>; 3145 status = "disabled"; 3146 }; 3147 3148 ufs_mem_phy: phy@1d87000 { 3149 compatible = "qcom,sm8450-qmp-ufs-phy"; 3150 reg = <0 0x01d87000 0 0x1c4>; 3151 #address-cells = <2>; 3152 #size-cells = <2>; 3153 ranges; 3154 clock-names = "ref", "ref_aux", "qref"; 3155 clocks = <&rpmhcc RPMH_CXO_CLK>, 3156 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3157 <&gcc GCC_UFS_0_CLKREF_EN>; 3158 3159 resets = <&ufs_mem_hc 0>; 3160 reset-names = "ufsphy"; 3161 status = "disabled"; 3162 3163 ufs_mem_phy_lanes: phy@1d87400 { 3164 reg = <0 0x01d87400 0 0x108>, 3165 <0 0x01d87600 0 0x1e0>, 3166 <0 0x01d87c00 0 0x1dc>, 3167 <0 0x01d87800 0 0x108>, 3168 <0 0x01d87a00 0 0x1e0>; 3169 #phy-cells = <0>; 3170 }; 3171 }; 3172 3173 sdhc_2: sdhci@8804000 { 3174 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 3175 reg = <0 0x08804000 0 0x1000>; 3176 3177 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3179 interrupt-names = "hc_irq", "pwr_irq"; 3180 3181 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3182 <&gcc GCC_SDCC2_APPS_CLK>, 3183 <&rpmhcc RPMH_CXO_CLK>; 3184 clock-names = "iface", "core", "xo"; 3185 resets = <&gcc GCC_SDCC2_BCR>; 3186 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3188 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3189 iommus = <&apps_smmu 0x4a0 0x0>; 3190 power-domains = <&rpmhpd SM8450_CX>; 3191 operating-points-v2 = <&sdhc2_opp_table>; 3192 bus-width = <4>; 3193 dma-coherent; 3194 3195 status = "disabled"; 3196 3197 sdhc2_opp_table: opp-table { 3198 compatible = "operating-points-v2"; 3199 3200 opp-100000000 { 3201 opp-hz = /bits/ 64 <100000000>; 3202 required-opps = <&rpmhpd_opp_low_svs>; 3203 }; 3204 3205 opp-202000000 { 3206 opp-hz = /bits/ 64 <202000000>; 3207 required-opps = <&rpmhpd_opp_svs_l1>; 3208 }; 3209 }; 3210 }; 3211 3212 usb_1: usb@a6f8800 { 3213 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 3214 reg = <0 0x0a6f8800 0 0x400>; 3215 status = "disabled"; 3216 #address-cells = <2>; 3217 #size-cells = <2>; 3218 ranges; 3219 3220 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3221 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3222 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3223 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3224 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3225 <&gcc GCC_USB3_0_CLKREF_EN>; 3226 clock-names = "cfg_noc", 3227 "core", 3228 "iface", 3229 "sleep", 3230 "mock_utmi", 3231 "xo"; 3232 3233 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3234 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3235 assigned-clock-rates = <19200000>, <200000000>; 3236 3237 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3238 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3239 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3240 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3241 interrupt-names = "hs_phy_irq", 3242 "ss_phy_irq", 3243 "dm_hs_phy_irq", 3244 "dp_hs_phy_irq"; 3245 3246 power-domains = <&gcc USB30_PRIM_GDSC>; 3247 3248 resets = <&gcc GCC_USB30_PRIM_BCR>; 3249 3250 usb_1_dwc3: usb@a600000 { 3251 compatible = "snps,dwc3"; 3252 reg = <0 0x0a600000 0 0xcd00>; 3253 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3254 iommus = <&apps_smmu 0x0 0x0>; 3255 snps,dis_u2_susphy_quirk; 3256 snps,dis_enblslpm_quirk; 3257 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3258 phy-names = "usb2-phy", "usb3-phy"; 3259 }; 3260 }; 3261 3262 nsp_noc: interconnect@320c0000 { 3263 compatible = "qcom,sm8450-nsp-noc"; 3264 reg = <0 0x320c0000 0 0x10000>; 3265 #interconnect-cells = <2>; 3266 qcom,bcm-voters = <&apps_bcm_voter>; 3267 }; 3268 3269 lpass_ag_noc: interconnect@3c40000 { 3270 compatible = "qcom,sm8450-lpass-ag-noc"; 3271 reg = <0 0x3c40000 0 0x17200>; 3272 #interconnect-cells = <2>; 3273 qcom,bcm-voters = <&apps_bcm_voter>; 3274 }; 3275 }; 3276 3277 thermal-zones { 3278 aoss0-thermal { 3279 polling-delay-passive = <0>; 3280 polling-delay = <0>; 3281 thermal-sensors = <&tsens0 0>; 3282 3283 trips { 3284 thermal-engine-config { 3285 temperature = <125000>; 3286 hysteresis = <1000>; 3287 type = "passive"; 3288 }; 3289 3290 reset-mon-cfg { 3291 temperature = <115000>; 3292 hysteresis = <5000>; 3293 type = "passive"; 3294 }; 3295 }; 3296 }; 3297 3298 cpuss0-thermal { 3299 polling-delay-passive = <0>; 3300 polling-delay = <0>; 3301 thermal-sensors = <&tsens0 1>; 3302 3303 trips { 3304 thermal-engine-config { 3305 temperature = <125000>; 3306 hysteresis = <1000>; 3307 type = "passive"; 3308 }; 3309 3310 reset-mon-cfg { 3311 temperature = <115000>; 3312 hysteresis = <5000>; 3313 type = "passive"; 3314 }; 3315 }; 3316 }; 3317 3318 cpuss1-thermal { 3319 polling-delay-passive = <0>; 3320 polling-delay = <0>; 3321 thermal-sensors = <&tsens0 2>; 3322 3323 trips { 3324 thermal-engine-config { 3325 temperature = <125000>; 3326 hysteresis = <1000>; 3327 type = "passive"; 3328 }; 3329 3330 reset-mon-cfg { 3331 temperature = <115000>; 3332 hysteresis = <5000>; 3333 type = "passive"; 3334 }; 3335 }; 3336 }; 3337 3338 cpuss3-thermal { 3339 polling-delay-passive = <0>; 3340 polling-delay = <0>; 3341 thermal-sensors = <&tsens0 3>; 3342 3343 trips { 3344 thermal-engine-config { 3345 temperature = <125000>; 3346 hysteresis = <1000>; 3347 type = "passive"; 3348 }; 3349 3350 reset-mon-cfg { 3351 temperature = <115000>; 3352 hysteresis = <5000>; 3353 type = "passive"; 3354 }; 3355 }; 3356 }; 3357 3358 cpuss4-thermal { 3359 polling-delay-passive = <0>; 3360 polling-delay = <0>; 3361 thermal-sensors = <&tsens0 4>; 3362 3363 trips { 3364 thermal-engine-config { 3365 temperature = <125000>; 3366 hysteresis = <1000>; 3367 type = "passive"; 3368 }; 3369 3370 reset-mon-cfg { 3371 temperature = <115000>; 3372 hysteresis = <5000>; 3373 type = "passive"; 3374 }; 3375 }; 3376 }; 3377 3378 cpu4-top-thermal { 3379 polling-delay-passive = <0>; 3380 polling-delay = <0>; 3381 thermal-sensors = <&tsens0 5>; 3382 3383 trips { 3384 cpu4_top_alert0: trip-point0 { 3385 temperature = <90000>; 3386 hysteresis = <2000>; 3387 type = "passive"; 3388 }; 3389 3390 cpu4_top_alert1: trip-point1 { 3391 temperature = <95000>; 3392 hysteresis = <2000>; 3393 type = "passive"; 3394 }; 3395 3396 cpu4_top_crit: cpu_crit { 3397 temperature = <110000>; 3398 hysteresis = <1000>; 3399 type = "critical"; 3400 }; 3401 }; 3402 }; 3403 3404 cpu4-bottom-thermal { 3405 polling-delay-passive = <0>; 3406 polling-delay = <0>; 3407 thermal-sensors = <&tsens0 6>; 3408 3409 trips { 3410 cpu4_bottom_alert0: trip-point0 { 3411 temperature = <90000>; 3412 hysteresis = <2000>; 3413 type = "passive"; 3414 }; 3415 3416 cpu4_bottom_alert1: trip-point1 { 3417 temperature = <95000>; 3418 hysteresis = <2000>; 3419 type = "passive"; 3420 }; 3421 3422 cpu4_bottom_crit: cpu_crit { 3423 temperature = <110000>; 3424 hysteresis = <1000>; 3425 type = "critical"; 3426 }; 3427 }; 3428 }; 3429 3430 cpu5-top-thermal { 3431 polling-delay-passive = <0>; 3432 polling-delay = <0>; 3433 thermal-sensors = <&tsens0 7>; 3434 3435 trips { 3436 cpu5_top_alert0: trip-point0 { 3437 temperature = <90000>; 3438 hysteresis = <2000>; 3439 type = "passive"; 3440 }; 3441 3442 cpu5_top_alert1: trip-point1 { 3443 temperature = <95000>; 3444 hysteresis = <2000>; 3445 type = "passive"; 3446 }; 3447 3448 cpu5_top_crit: cpu_crit { 3449 temperature = <110000>; 3450 hysteresis = <1000>; 3451 type = "critical"; 3452 }; 3453 }; 3454 }; 3455 3456 cpu5-bottom-thermal { 3457 polling-delay-passive = <0>; 3458 polling-delay = <0>; 3459 thermal-sensors = <&tsens0 8>; 3460 3461 trips { 3462 cpu5_bottom_alert0: trip-point0 { 3463 temperature = <90000>; 3464 hysteresis = <2000>; 3465 type = "passive"; 3466 }; 3467 3468 cpu5_bottom_alert1: trip-point1 { 3469 temperature = <95000>; 3470 hysteresis = <2000>; 3471 type = "passive"; 3472 }; 3473 3474 cpu5_bottom_crit: cpu_crit { 3475 temperature = <110000>; 3476 hysteresis = <1000>; 3477 type = "critical"; 3478 }; 3479 }; 3480 }; 3481 3482 cpu6-top-thermal { 3483 polling-delay-passive = <0>; 3484 polling-delay = <0>; 3485 thermal-sensors = <&tsens0 9>; 3486 3487 trips { 3488 cpu6_top_alert0: trip-point0 { 3489 temperature = <90000>; 3490 hysteresis = <2000>; 3491 type = "passive"; 3492 }; 3493 3494 cpu6_top_alert1: trip-point1 { 3495 temperature = <95000>; 3496 hysteresis = <2000>; 3497 type = "passive"; 3498 }; 3499 3500 cpu6_top_crit: cpu_crit { 3501 temperature = <110000>; 3502 hysteresis = <1000>; 3503 type = "critical"; 3504 }; 3505 }; 3506 }; 3507 3508 cpu6-bottom-thermal { 3509 polling-delay-passive = <0>; 3510 polling-delay = <0>; 3511 thermal-sensors = <&tsens0 10>; 3512 3513 trips { 3514 cpu6_bottom_alert0: trip-point0 { 3515 temperature = <90000>; 3516 hysteresis = <2000>; 3517 type = "passive"; 3518 }; 3519 3520 cpu6_bottom_alert1: trip-point1 { 3521 temperature = <95000>; 3522 hysteresis = <2000>; 3523 type = "passive"; 3524 }; 3525 3526 cpu6_bottom_crit: cpu_crit { 3527 temperature = <110000>; 3528 hysteresis = <1000>; 3529 type = "critical"; 3530 }; 3531 }; 3532 }; 3533 3534 cpu7-top-thermal { 3535 polling-delay-passive = <0>; 3536 polling-delay = <0>; 3537 thermal-sensors = <&tsens0 11>; 3538 3539 trips { 3540 cpu7_top_alert0: trip-point0 { 3541 temperature = <90000>; 3542 hysteresis = <2000>; 3543 type = "passive"; 3544 }; 3545 3546 cpu7_top_alert1: trip-point1 { 3547 temperature = <95000>; 3548 hysteresis = <2000>; 3549 type = "passive"; 3550 }; 3551 3552 cpu7_top_crit: cpu_crit { 3553 temperature = <110000>; 3554 hysteresis = <1000>; 3555 type = "critical"; 3556 }; 3557 }; 3558 }; 3559 3560 cpu7-middle-thermal { 3561 polling-delay-passive = <0>; 3562 polling-delay = <0>; 3563 thermal-sensors = <&tsens0 12>; 3564 3565 trips { 3566 cpu7_middle_alert0: trip-point0 { 3567 temperature = <90000>; 3568 hysteresis = <2000>; 3569 type = "passive"; 3570 }; 3571 3572 cpu7_middle_alert1: trip-point1 { 3573 temperature = <95000>; 3574 hysteresis = <2000>; 3575 type = "passive"; 3576 }; 3577 3578 cpu7_middle_crit: cpu_crit { 3579 temperature = <110000>; 3580 hysteresis = <1000>; 3581 type = "critical"; 3582 }; 3583 }; 3584 }; 3585 3586 cpu7-bottom-thermal { 3587 polling-delay-passive = <0>; 3588 polling-delay = <0>; 3589 thermal-sensors = <&tsens0 13>; 3590 3591 trips { 3592 cpu7_bottom_alert0: trip-point0 { 3593 temperature = <90000>; 3594 hysteresis = <2000>; 3595 type = "passive"; 3596 }; 3597 3598 cpu7_bottom_alert1: trip-point1 { 3599 temperature = <95000>; 3600 hysteresis = <2000>; 3601 type = "passive"; 3602 }; 3603 3604 cpu7_bottom_crit: cpu_crit { 3605 temperature = <110000>; 3606 hysteresis = <1000>; 3607 type = "critical"; 3608 }; 3609 }; 3610 }; 3611 3612 gpu-top-thermal { 3613 polling-delay-passive = <10>; 3614 polling-delay = <0>; 3615 thermal-sensors = <&tsens0 14>; 3616 3617 trips { 3618 thermal-engine-config { 3619 temperature = <125000>; 3620 hysteresis = <1000>; 3621 type = "passive"; 3622 }; 3623 3624 thermal-hal-config { 3625 temperature = <125000>; 3626 hysteresis = <1000>; 3627 type = "passive"; 3628 }; 3629 3630 reset-mon-cfg { 3631 temperature = <115000>; 3632 hysteresis = <5000>; 3633 type = "passive"; 3634 }; 3635 3636 gpu0_tj_cfg: tj_cfg { 3637 temperature = <95000>; 3638 hysteresis = <5000>; 3639 type = "passive"; 3640 }; 3641 }; 3642 }; 3643 3644 gpu-bottom-thermal { 3645 polling-delay-passive = <10>; 3646 polling-delay = <0>; 3647 thermal-sensors = <&tsens0 15>; 3648 3649 trips { 3650 thermal-engine-config { 3651 temperature = <125000>; 3652 hysteresis = <1000>; 3653 type = "passive"; 3654 }; 3655 3656 thermal-hal-config { 3657 temperature = <125000>; 3658 hysteresis = <1000>; 3659 type = "passive"; 3660 }; 3661 3662 reset-mon-cfg { 3663 temperature = <115000>; 3664 hysteresis = <5000>; 3665 type = "passive"; 3666 }; 3667 3668 gpu1_tj_cfg: tj_cfg { 3669 temperature = <95000>; 3670 hysteresis = <5000>; 3671 type = "passive"; 3672 }; 3673 }; 3674 }; 3675 3676 aoss1-thermal { 3677 polling-delay-passive = <0>; 3678 polling-delay = <0>; 3679 thermal-sensors = <&tsens1 0>; 3680 3681 trips { 3682 thermal-engine-config { 3683 temperature = <125000>; 3684 hysteresis = <1000>; 3685 type = "passive"; 3686 }; 3687 3688 reset-mon-cfg { 3689 temperature = <115000>; 3690 hysteresis = <5000>; 3691 type = "passive"; 3692 }; 3693 }; 3694 }; 3695 3696 cpu0-thermal { 3697 polling-delay-passive = <0>; 3698 polling-delay = <0>; 3699 thermal-sensors = <&tsens1 1>; 3700 3701 trips { 3702 cpu0_alert0: trip-point0 { 3703 temperature = <90000>; 3704 hysteresis = <2000>; 3705 type = "passive"; 3706 }; 3707 3708 cpu0_alert1: trip-point1 { 3709 temperature = <95000>; 3710 hysteresis = <2000>; 3711 type = "passive"; 3712 }; 3713 3714 cpu0_crit: cpu_crit { 3715 temperature = <110000>; 3716 hysteresis = <1000>; 3717 type = "critical"; 3718 }; 3719 }; 3720 }; 3721 3722 cpu1-thermal { 3723 polling-delay-passive = <0>; 3724 polling-delay = <0>; 3725 thermal-sensors = <&tsens1 2>; 3726 3727 trips { 3728 cpu1_alert0: trip-point0 { 3729 temperature = <90000>; 3730 hysteresis = <2000>; 3731 type = "passive"; 3732 }; 3733 3734 cpu1_alert1: trip-point1 { 3735 temperature = <95000>; 3736 hysteresis = <2000>; 3737 type = "passive"; 3738 }; 3739 3740 cpu1_crit: cpu_crit { 3741 temperature = <110000>; 3742 hysteresis = <1000>; 3743 type = "critical"; 3744 }; 3745 }; 3746 }; 3747 3748 cpu2-thermal { 3749 polling-delay-passive = <0>; 3750 polling-delay = <0>; 3751 thermal-sensors = <&tsens1 3>; 3752 3753 trips { 3754 cpu2_alert0: trip-point0 { 3755 temperature = <90000>; 3756 hysteresis = <2000>; 3757 type = "passive"; 3758 }; 3759 3760 cpu2_alert1: trip-point1 { 3761 temperature = <95000>; 3762 hysteresis = <2000>; 3763 type = "passive"; 3764 }; 3765 3766 cpu2_crit: cpu_crit { 3767 temperature = <110000>; 3768 hysteresis = <1000>; 3769 type = "critical"; 3770 }; 3771 }; 3772 }; 3773 3774 cpu3-thermal { 3775 polling-delay-passive = <0>; 3776 polling-delay = <0>; 3777 thermal-sensors = <&tsens1 4>; 3778 3779 trips { 3780 cpu3_alert0: trip-point0 { 3781 temperature = <90000>; 3782 hysteresis = <2000>; 3783 type = "passive"; 3784 }; 3785 3786 cpu3_alert1: trip-point1 { 3787 temperature = <95000>; 3788 hysteresis = <2000>; 3789 type = "passive"; 3790 }; 3791 3792 cpu3_crit: cpu_crit { 3793 temperature = <110000>; 3794 hysteresis = <1000>; 3795 type = "critical"; 3796 }; 3797 }; 3798 }; 3799 3800 cdsp0-thermal { 3801 polling-delay-passive = <10>; 3802 polling-delay = <0>; 3803 thermal-sensors = <&tsens1 5>; 3804 3805 trips { 3806 thermal-engine-config { 3807 temperature = <125000>; 3808 hysteresis = <1000>; 3809 type = "passive"; 3810 }; 3811 3812 thermal-hal-config { 3813 temperature = <125000>; 3814 hysteresis = <1000>; 3815 type = "passive"; 3816 }; 3817 3818 reset-mon-cfg { 3819 temperature = <115000>; 3820 hysteresis = <5000>; 3821 type = "passive"; 3822 }; 3823 3824 cdsp_0_config: junction-config { 3825 temperature = <95000>; 3826 hysteresis = <5000>; 3827 type = "passive"; 3828 }; 3829 }; 3830 }; 3831 3832 cdsp1-thermal { 3833 polling-delay-passive = <10>; 3834 polling-delay = <0>; 3835 thermal-sensors = <&tsens1 6>; 3836 3837 trips { 3838 thermal-engine-config { 3839 temperature = <125000>; 3840 hysteresis = <1000>; 3841 type = "passive"; 3842 }; 3843 3844 thermal-hal-config { 3845 temperature = <125000>; 3846 hysteresis = <1000>; 3847 type = "passive"; 3848 }; 3849 3850 reset-mon-cfg { 3851 temperature = <115000>; 3852 hysteresis = <5000>; 3853 type = "passive"; 3854 }; 3855 3856 cdsp_1_config: junction-config { 3857 temperature = <95000>; 3858 hysteresis = <5000>; 3859 type = "passive"; 3860 }; 3861 }; 3862 }; 3863 3864 cdsp2-thermal { 3865 polling-delay-passive = <10>; 3866 polling-delay = <0>; 3867 thermal-sensors = <&tsens1 7>; 3868 3869 trips { 3870 thermal-engine-config { 3871 temperature = <125000>; 3872 hysteresis = <1000>; 3873 type = "passive"; 3874 }; 3875 3876 thermal-hal-config { 3877 temperature = <125000>; 3878 hysteresis = <1000>; 3879 type = "passive"; 3880 }; 3881 3882 reset-mon-cfg { 3883 temperature = <115000>; 3884 hysteresis = <5000>; 3885 type = "passive"; 3886 }; 3887 3888 cdsp_2_config: junction-config { 3889 temperature = <95000>; 3890 hysteresis = <5000>; 3891 type = "passive"; 3892 }; 3893 }; 3894 }; 3895 3896 video-thermal { 3897 polling-delay-passive = <0>; 3898 polling-delay = <0>; 3899 thermal-sensors = <&tsens1 8>; 3900 3901 trips { 3902 thermal-engine-config { 3903 temperature = <125000>; 3904 hysteresis = <1000>; 3905 type = "passive"; 3906 }; 3907 3908 reset-mon-cfg { 3909 temperature = <115000>; 3910 hysteresis = <5000>; 3911 type = "passive"; 3912 }; 3913 }; 3914 }; 3915 3916 mem-thermal { 3917 polling-delay-passive = <10>; 3918 polling-delay = <0>; 3919 thermal-sensors = <&tsens1 9>; 3920 3921 trips { 3922 thermal-engine-config { 3923 temperature = <125000>; 3924 hysteresis = <1000>; 3925 type = "passive"; 3926 }; 3927 3928 ddr_config0: ddr0-config { 3929 temperature = <90000>; 3930 hysteresis = <5000>; 3931 type = "passive"; 3932 }; 3933 3934 reset-mon-cfg { 3935 temperature = <115000>; 3936 hysteresis = <5000>; 3937 type = "passive"; 3938 }; 3939 }; 3940 }; 3941 3942 modem0-thermal { 3943 polling-delay-passive = <0>; 3944 polling-delay = <0>; 3945 thermal-sensors = <&tsens1 10>; 3946 3947 trips { 3948 thermal-engine-config { 3949 temperature = <125000>; 3950 hysteresis = <1000>; 3951 type = "passive"; 3952 }; 3953 3954 mdmss0_config0: mdmss0-config0 { 3955 temperature = <102000>; 3956 hysteresis = <3000>; 3957 type = "passive"; 3958 }; 3959 3960 mdmss0_config1: mdmss0-config1 { 3961 temperature = <105000>; 3962 hysteresis = <3000>; 3963 type = "passive"; 3964 }; 3965 3966 reset-mon-cfg { 3967 temperature = <115000>; 3968 hysteresis = <5000>; 3969 type = "passive"; 3970 }; 3971 }; 3972 }; 3973 3974 modem1-thermal { 3975 polling-delay-passive = <0>; 3976 polling-delay = <0>; 3977 thermal-sensors = <&tsens1 11>; 3978 3979 trips { 3980 thermal-engine-config { 3981 temperature = <125000>; 3982 hysteresis = <1000>; 3983 type = "passive"; 3984 }; 3985 3986 mdmss1_config0: mdmss1-config0 { 3987 temperature = <102000>; 3988 hysteresis = <3000>; 3989 type = "passive"; 3990 }; 3991 3992 mdmss1_config1: mdmss1-config1 { 3993 temperature = <105000>; 3994 hysteresis = <3000>; 3995 type = "passive"; 3996 }; 3997 3998 reset-mon-cfg { 3999 temperature = <115000>; 4000 hysteresis = <5000>; 4001 type = "passive"; 4002 }; 4003 }; 4004 }; 4005 4006 modem2-thermal { 4007 polling-delay-passive = <0>; 4008 polling-delay = <0>; 4009 thermal-sensors = <&tsens1 12>; 4010 4011 trips { 4012 thermal-engine-config { 4013 temperature = <125000>; 4014 hysteresis = <1000>; 4015 type = "passive"; 4016 }; 4017 4018 mdmss2_config0: mdmss2-config0 { 4019 temperature = <102000>; 4020 hysteresis = <3000>; 4021 type = "passive"; 4022 }; 4023 4024 mdmss2_config1: mdmss2-config1 { 4025 temperature = <105000>; 4026 hysteresis = <3000>; 4027 type = "passive"; 4028 }; 4029 4030 reset-mon-cfg { 4031 temperature = <115000>; 4032 hysteresis = <5000>; 4033 type = "passive"; 4034 }; 4035 }; 4036 }; 4037 4038 modem3-thermal { 4039 polling-delay-passive = <0>; 4040 polling-delay = <0>; 4041 thermal-sensors = <&tsens1 13>; 4042 4043 trips { 4044 thermal-engine-config { 4045 temperature = <125000>; 4046 hysteresis = <1000>; 4047 type = "passive"; 4048 }; 4049 4050 mdmss3_config0: mdmss3-config0 { 4051 temperature = <102000>; 4052 hysteresis = <3000>; 4053 type = "passive"; 4054 }; 4055 4056 mdmss3_config1: mdmss3-config1 { 4057 temperature = <105000>; 4058 hysteresis = <3000>; 4059 type = "passive"; 4060 }; 4061 4062 reset-mon-cfg { 4063 temperature = <115000>; 4064 hysteresis = <5000>; 4065 type = "passive"; 4066 }; 4067 }; 4068 }; 4069 4070 camera0-thermal { 4071 polling-delay-passive = <0>; 4072 polling-delay = <0>; 4073 thermal-sensors = <&tsens1 14>; 4074 4075 trips { 4076 thermal-engine-config { 4077 temperature = <125000>; 4078 hysteresis = <1000>; 4079 type = "passive"; 4080 }; 4081 4082 reset-mon-cfg { 4083 temperature = <115000>; 4084 hysteresis = <5000>; 4085 type = "passive"; 4086 }; 4087 }; 4088 }; 4089 4090 camera1-thermal { 4091 polling-delay-passive = <0>; 4092 polling-delay = <0>; 4093 thermal-sensors = <&tsens1 15>; 4094 4095 trips { 4096 thermal-engine-config { 4097 temperature = <125000>; 4098 hysteresis = <1000>; 4099 type = "passive"; 4100 }; 4101 4102 reset-mon-cfg { 4103 temperature = <115000>; 4104 hysteresis = <5000>; 4105 type = "passive"; 4106 }; 4107 }; 4108 }; 4109 }; 4110 4111 timer { 4112 compatible = "arm,armv8-timer"; 4113 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4114 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4115 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4117 clock-frequency = <19200000>; 4118 }; 4119}; 4120