1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/interconnect/qcom,sm8450.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <76800000>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32000>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo780"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 power-domains = <&CPU_PD0>; 50 power-domain-names = "psci"; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 #cooling-cells = <2>; 53 L2_0: l2-cache { 54 compatible = "cache"; 55 next-level-cache = <&L3_0>; 56 L3_0: l3-cache { 57 compatible = "cache"; 58 }; 59 }; 60 }; 61 62 CPU1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo780"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_100>; 68 power-domains = <&CPU_PD1>; 69 power-domain-names = "psci"; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 #cooling-cells = <2>; 72 L2_100: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 }; 76 }; 77 78 CPU2: cpu@200 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo780"; 81 reg = <0x0 0x200>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_200>; 84 power-domains = <&CPU_PD2>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 L2_200: l2-cache { 89 compatible = "cache"; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo780"; 97 reg = <0x0 0x300>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_300>; 100 power-domains = <&CPU_PD3>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 #cooling-cells = <2>; 104 L2_300: l2-cache { 105 compatible = "cache"; 106 next-level-cache = <&L3_0>; 107 }; 108 }; 109 110 CPU4: cpu@400 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo780"; 113 reg = <0x0 0x400>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_400>; 116 power-domains = <&CPU_PD4>; 117 power-domain-names = "psci"; 118 qcom,freq-domain = <&cpufreq_hw 1>; 119 #cooling-cells = <2>; 120 L2_400: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU5: cpu@500 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo780"; 129 reg = <0x0 0x500>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_500>; 132 power-domains = <&CPU_PD5>; 133 power-domain-names = "psci"; 134 qcom,freq-domain = <&cpufreq_hw 1>; 135 #cooling-cells = <2>; 136 L2_500: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 }; 140 141 }; 142 143 CPU6: cpu@600 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo780"; 146 reg = <0x0 0x600>; 147 enable-method = "psci"; 148 next-level-cache = <&L2_600>; 149 power-domains = <&CPU_PD6>; 150 power-domain-names = "psci"; 151 qcom,freq-domain = <&cpufreq_hw 1>; 152 #cooling-cells = <2>; 153 L2_600: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU7: cpu@700 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo780"; 162 reg = <0x0 0x700>; 163 enable-method = "psci"; 164 next-level-cache = <&L2_700>; 165 power-domains = <&CPU_PD7>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 2>; 168 #cooling-cells = <2>; 169 L2_700: l2-cache { 170 compatible = "cache"; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 cpu-map { 176 cluster0 { 177 core0 { 178 cpu = <&CPU0>; 179 }; 180 181 core1 { 182 cpu = <&CPU1>; 183 }; 184 185 core2 { 186 cpu = <&CPU2>; 187 }; 188 189 core3 { 190 cpu = <&CPU3>; 191 }; 192 193 core4 { 194 cpu = <&CPU4>; 195 }; 196 197 core5 { 198 cpu = <&CPU5>; 199 }; 200 201 core6 { 202 cpu = <&CPU6>; 203 }; 204 205 core7 { 206 cpu = <&CPU7>; 207 }; 208 }; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 215 compatible = "arm,idle-state"; 216 idle-state-name = "silver-rail-power-collapse"; 217 arm,psci-suspend-param = <0x40000004>; 218 entry-latency-us = <800>; 219 exit-latency-us = <750>; 220 min-residency-us = <4090>; 221 local-timer-stop; 222 }; 223 224 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 225 compatible = "arm,idle-state"; 226 idle-state-name = "gold-rail-power-collapse"; 227 arm,psci-suspend-param = <0x40000004>; 228 entry-latency-us = <600>; 229 exit-latency-us = <1550>; 230 min-residency-us = <4791>; 231 local-timer-stop; 232 }; 233 }; 234 235 domain-idle-states { 236 CLUSTER_SLEEP_0: cluster-sleep-0 { 237 compatible = "domain-idle-state"; 238 idle-state-name = "cluster-l3-off"; 239 arm,psci-suspend-param = <0x41000044>; 240 entry-latency-us = <1050>; 241 exit-latency-us = <2500>; 242 min-residency-us = <5309>; 243 local-timer-stop; 244 }; 245 246 CLUSTER_SLEEP_1: cluster-sleep-1 { 247 compatible = "domain-idle-state"; 248 idle-state-name = "cluster-power-collapse"; 249 arm,psci-suspend-param = <0x4100c344>; 250 entry-latency-us = <2700>; 251 exit-latency-us = <3500>; 252 min-residency-us = <13959>; 253 local-timer-stop; 254 }; 255 }; 256 }; 257 258 firmware { 259 scm: scm { 260 compatible = "qcom,scm-sm8450", "qcom,scm"; 261 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 262 #reset-cells = <1>; 263 }; 264 }; 265 266 clk_virt: interconnect@0 { 267 compatible = "qcom,sm8450-clk-virt"; 268 #interconnect-cells = <2>; 269 qcom,bcm-voters = <&apps_bcm_voter>; 270 }; 271 272 mc_virt: interconnect@1 { 273 compatible = "qcom,sm8450-mc-virt"; 274 #interconnect-cells = <2>; 275 qcom,bcm-voters = <&apps_bcm_voter>; 276 }; 277 278 memory@a0000000 { 279 device_type = "memory"; 280 /* We expect the bootloader to fill in the size */ 281 reg = <0x0 0xa0000000 0x0 0x0>; 282 }; 283 284 pmu { 285 compatible = "arm,armv8-pmuv3"; 286 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 287 }; 288 289 psci { 290 compatible = "arm,psci-1.0"; 291 method = "smc"; 292 293 CPU_PD0: cpu0 { 294 #power-domain-cells = <0>; 295 power-domains = <&CLUSTER_PD>; 296 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 297 }; 298 299 CPU_PD1: cpu1 { 300 #power-domain-cells = <0>; 301 power-domains = <&CLUSTER_PD>; 302 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 303 }; 304 305 CPU_PD2: cpu2 { 306 #power-domain-cells = <0>; 307 power-domains = <&CLUSTER_PD>; 308 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 309 }; 310 311 CPU_PD3: cpu3 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 315 }; 316 317 CPU_PD4: cpu4 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&BIG_CPU_SLEEP_0>; 321 }; 322 323 CPU_PD5: cpu5 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&BIG_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD6: cpu6 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&BIG_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD7: cpu7 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&BIG_CPU_SLEEP_0>; 339 }; 340 341 CLUSTER_PD: cpu-cluster0 { 342 #power-domain-cells = <0>; 343 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 344 }; 345 }; 346 347 qup_opp_table_100mhz: opp-table-qup { 348 compatible = "operating-points-v2"; 349 350 opp-50000000 { 351 opp-hz = /bits/ 64 <50000000>; 352 required-opps = <&rpmhpd_opp_min_svs>; 353 }; 354 355 opp-75000000 { 356 opp-hz = /bits/ 64 <75000000>; 357 required-opps = <&rpmhpd_opp_low_svs>; 358 }; 359 360 opp-100000000 { 361 opp-hz = /bits/ 64 <100000000>; 362 required-opps = <&rpmhpd_opp_svs>; 363 }; 364 }; 365 366 reserved_memory: reserved-memory { 367 #address-cells = <2>; 368 #size-cells = <2>; 369 ranges; 370 371 hyp_mem: memory@80000000 { 372 reg = <0x0 0x80000000 0x0 0x600000>; 373 no-map; 374 }; 375 376 xbl_dt_log_mem: memory@80600000 { 377 reg = <0x0 0x80600000 0x0 0x40000>; 378 no-map; 379 }; 380 381 xbl_ramdump_mem: memory@80640000 { 382 reg = <0x0 0x80640000 0x0 0x180000>; 383 no-map; 384 }; 385 386 xbl_sc_mem: memory@807c0000 { 387 reg = <0x0 0x807c0000 0x0 0x40000>; 388 no-map; 389 }; 390 391 aop_image_mem: memory@80800000 { 392 reg = <0x0 0x80800000 0x0 0x60000>; 393 no-map; 394 }; 395 396 aop_cmd_db_mem: memory@80860000 { 397 compatible = "qcom,cmd-db"; 398 reg = <0x0 0x80860000 0x0 0x20000>; 399 no-map; 400 }; 401 402 aop_config_mem: memory@80880000 { 403 reg = <0x0 0x80880000 0x0 0x20000>; 404 no-map; 405 }; 406 407 tme_crash_dump_mem: memory@808a0000 { 408 reg = <0x0 0x808a0000 0x0 0x40000>; 409 no-map; 410 }; 411 412 tme_log_mem: memory@808e0000 { 413 reg = <0x0 0x808e0000 0x0 0x4000>; 414 no-map; 415 }; 416 417 uefi_log_mem: memory@808e4000 { 418 reg = <0x0 0x808e4000 0x0 0x10000>; 419 no-map; 420 }; 421 422 /* secdata region can be reused by apps */ 423 smem: memory@80900000 { 424 compatible = "qcom,smem"; 425 reg = <0x0 0x80900000 0x0 0x200000>; 426 hwlocks = <&tcsr_mutex 3>; 427 no-map; 428 }; 429 430 cpucp_fw_mem: memory@80b00000 { 431 reg = <0x0 0x80b00000 0x0 0x100000>; 432 no-map; 433 }; 434 435 cdsp_secure_heap: memory@80c00000 { 436 reg = <0x0 0x80c00000 0x0 0x4600000>; 437 no-map; 438 }; 439 440 camera_mem: memory@85200000 { 441 reg = <0x0 0x85200000 0x0 0x500000>; 442 no-map; 443 }; 444 445 video_mem: memory@85700000 { 446 reg = <0x0 0x85700000 0x0 0x700000>; 447 no-map; 448 }; 449 450 adsp_mem: memory@85e00000 { 451 reg = <0x0 0x85e00000 0x0 0x2100000>; 452 no-map; 453 }; 454 455 slpi_mem: memory@88000000 { 456 reg = <0x0 0x88000000 0x0 0x1900000>; 457 no-map; 458 }; 459 460 cdsp_mem: memory@89900000 { 461 reg = <0x0 0x89900000 0x0 0x2000000>; 462 no-map; 463 }; 464 465 ipa_fw_mem: memory@8b900000 { 466 reg = <0x0 0x8b900000 0x0 0x10000>; 467 no-map; 468 }; 469 470 ipa_gsi_mem: memory@8b910000 { 471 reg = <0x0 0x8b910000 0x0 0xa000>; 472 no-map; 473 }; 474 475 gpu_micro_code_mem: memory@8b91a000 { 476 reg = <0x0 0x8b91a000 0x0 0x2000>; 477 no-map; 478 }; 479 480 spss_region_mem: memory@8ba00000 { 481 reg = <0x0 0x8ba00000 0x0 0x180000>; 482 no-map; 483 }; 484 485 /* First part of the "SPU secure shared memory" region */ 486 spu_tz_shared_mem: memory@8bb80000 { 487 reg = <0x0 0x8bb80000 0x0 0x60000>; 488 no-map; 489 }; 490 491 /* Second part of the "SPU secure shared memory" region */ 492 spu_modem_shared_mem: memory@8bbe0000 { 493 reg = <0x0 0x8bbe0000 0x0 0x20000>; 494 no-map; 495 }; 496 497 mpss_mem: memory@8bc00000 { 498 reg = <0x0 0x8bc00000 0x0 0x13200000>; 499 no-map; 500 }; 501 502 cvp_mem: memory@9ee00000 { 503 reg = <0x0 0x9ee00000 0x0 0x700000>; 504 no-map; 505 }; 506 507 rmtfs_mem: memory@9fd00000 { 508 compatible = "qcom,rmtfs-mem"; 509 reg = <0x0 0x9fd00000 0x0 0x280000>; 510 no-map; 511 512 qcom,client-id = <1>; 513 qcom,vmid = <15>; 514 }; 515 516 global_sync_mem: memory@a6f00000 { 517 reg = <0x0 0xa6f00000 0x0 0x100000>; 518 no-map; 519 }; 520 521 /* uefi region can be reused by APPS */ 522 523 /* Linux kernel image is loaded at 0xa0000000 */ 524 525 oem_vm_mem: memory@bb000000 { 526 reg = <0x0 0xbb000000 0x0 0x5000000>; 527 no-map; 528 }; 529 530 mte_mem: memory@c0000000 { 531 reg = <0x0 0xc0000000 0x0 0x20000000>; 532 no-map; 533 }; 534 535 qheebsp_reserved_mem: memory@e0000000 { 536 reg = <0x0 0xe0000000 0x0 0x600000>; 537 no-map; 538 }; 539 540 cpusys_vm_mem: memory@e0600000 { 541 reg = <0x0 0xe0600000 0x0 0x400000>; 542 no-map; 543 }; 544 545 hyp_reserved_mem: memory@e0a00000 { 546 reg = <0x0 0xe0a00000 0x0 0x100000>; 547 no-map; 548 }; 549 550 trust_ui_vm_mem: memory@e0b00000 { 551 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 552 no-map; 553 }; 554 555 trust_ui_vm_qrtr: memory@e55f3000 { 556 reg = <0x0 0xe55f3000 0x0 0x9000>; 557 no-map; 558 }; 559 560 trust_ui_vm_vblk0_ring: memory@e55fc000 { 561 reg = <0x0 0xe55fc000 0x0 0x4000>; 562 no-map; 563 }; 564 565 trust_ui_vm_swiotlb: memory@e5600000 { 566 reg = <0x0 0xe5600000 0x0 0x100000>; 567 no-map; 568 }; 569 570 tz_stat_mem: memory@e8800000 { 571 reg = <0x0 0xe8800000 0x0 0x100000>; 572 no-map; 573 }; 574 575 tags_mem: memory@e8900000 { 576 reg = <0x0 0xe8900000 0x0 0x1200000>; 577 no-map; 578 }; 579 580 qtee_mem: memory@e9b00000 { 581 reg = <0x0 0xe9b00000 0x0 0x500000>; 582 no-map; 583 }; 584 585 trusted_apps_mem: memory@ea000000 { 586 reg = <0x0 0xea000000 0x0 0x3900000>; 587 no-map; 588 }; 589 590 trusted_apps_ext_mem: memory@ed900000 { 591 reg = <0x0 0xed900000 0x0 0x3b00000>; 592 no-map; 593 }; 594 }; 595 596 smp2p-adsp { 597 compatible = "qcom,smp2p"; 598 qcom,smem = <443>, <429>; 599 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 600 IPCC_MPROC_SIGNAL_SMP2P 601 IRQ_TYPE_EDGE_RISING>; 602 mboxes = <&ipcc IPCC_CLIENT_LPASS 603 IPCC_MPROC_SIGNAL_SMP2P>; 604 605 qcom,local-pid = <0>; 606 qcom,remote-pid = <2>; 607 608 smp2p_adsp_out: master-kernel { 609 qcom,entry-name = "master-kernel"; 610 #qcom,smem-state-cells = <1>; 611 }; 612 613 smp2p_adsp_in: slave-kernel { 614 qcom,entry-name = "slave-kernel"; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 }; 618 }; 619 620 smp2p-cdsp { 621 compatible = "qcom,smp2p"; 622 qcom,smem = <94>, <432>; 623 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 624 IPCC_MPROC_SIGNAL_SMP2P 625 IRQ_TYPE_EDGE_RISING>; 626 mboxes = <&ipcc IPCC_CLIENT_CDSP 627 IPCC_MPROC_SIGNAL_SMP2P>; 628 629 qcom,local-pid = <0>; 630 qcom,remote-pid = <5>; 631 632 smp2p_cdsp_out: master-kernel { 633 qcom,entry-name = "master-kernel"; 634 #qcom,smem-state-cells = <1>; 635 }; 636 637 smp2p_cdsp_in: slave-kernel { 638 qcom,entry-name = "slave-kernel"; 639 interrupt-controller; 640 #interrupt-cells = <2>; 641 }; 642 }; 643 644 smp2p-modem { 645 compatible = "qcom,smp2p"; 646 qcom,smem = <435>, <428>; 647 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 648 IPCC_MPROC_SIGNAL_SMP2P 649 IRQ_TYPE_EDGE_RISING>; 650 mboxes = <&ipcc IPCC_CLIENT_MPSS 651 IPCC_MPROC_SIGNAL_SMP2P>; 652 653 qcom,local-pid = <0>; 654 qcom,remote-pid = <1>; 655 656 smp2p_modem_out: master-kernel { 657 qcom,entry-name = "master-kernel"; 658 #qcom,smem-state-cells = <1>; 659 }; 660 661 smp2p_modem_in: slave-kernel { 662 qcom,entry-name = "slave-kernel"; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 }; 666 667 ipa_smp2p_out: ipa-ap-to-modem { 668 qcom,entry-name = "ipa"; 669 #qcom,smem-state-cells = <1>; 670 }; 671 672 ipa_smp2p_in: ipa-modem-to-ap { 673 qcom,entry-name = "ipa"; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 }; 677 }; 678 679 smp2p-slpi { 680 compatible = "qcom,smp2p"; 681 qcom,smem = <481>, <430>; 682 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&ipcc IPCC_CLIENT_SLPI 686 IPCC_MPROC_SIGNAL_SMP2P>; 687 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <3>; 690 691 smp2p_slpi_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 smp2p_slpi_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 }; 702 703 soc: soc@0 { 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges = <0 0 0 0 0x10 0>; 707 dma-ranges = <0 0 0 0 0x10 0>; 708 compatible = "simple-bus"; 709 710 gcc: clock-controller@100000 { 711 compatible = "qcom,gcc-sm8450"; 712 reg = <0x0 0x00100000 0x0 0x1f4200>; 713 #clock-cells = <1>; 714 #reset-cells = <1>; 715 #power-domain-cells = <1>; 716 clocks = <&rpmhcc RPMH_CXO_CLK>, 717 <&pcie0_lane>, 718 <&pcie1_lane>, 719 <&sleep_clk>; 720 clock-names = "bi_tcxo", 721 "pcie_0_pipe_clk", 722 "pcie_1_pipe_clk", 723 "sleep_clk"; 724 }; 725 726 gpi_dma2: dma-controller@800000 { 727 compatible = "qcom,sm8450-gpi-dma"; 728 #dma-cells = <3>; 729 reg = <0 0x800000 0 0x60000>; 730 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 742 dma-channels = <12>; 743 dma-channel-mask = <0x7e>; 744 iommus = <&apps_smmu 0x496 0x0>; 745 status = "disabled"; 746 }; 747 748 qupv3_id_2: geniqup@8c0000 { 749 compatible = "qcom,geni-se-qup"; 750 reg = <0x0 0x008c0000 0x0 0x2000>; 751 clock-names = "m-ahb", "s-ahb"; 752 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 753 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 754 iommus = <&apps_smmu 0x483 0x0>; 755 #address-cells = <2>; 756 #size-cells = <2>; 757 ranges; 758 status = "disabled"; 759 760 i2c15: i2c@880000 { 761 compatible = "qcom,geni-i2c"; 762 reg = <0x0 0x00880000 0x0 0x4000>; 763 clock-names = "se"; 764 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&qup_i2c15_data_clk>; 767 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 771 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 772 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 773 interconnect-names = "qup-core", "qup-config", "qup-memory"; 774 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 775 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 776 dma-names = "tx", "rx"; 777 status = "disabled"; 778 }; 779 780 spi15: spi@880000 { 781 compatible = "qcom,geni-spi"; 782 reg = <0x0 0x00880000 0x0 0x4000>; 783 clock-names = "se"; 784 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 785 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 788 spi-max-frequency = <50000000>; 789 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 790 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 791 interconnect-names = "qup-core", "qup-config"; 792 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 793 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 794 dma-names = "tx", "rx"; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 status = "disabled"; 798 }; 799 800 i2c16: i2c@884000 { 801 compatible = "qcom,geni-i2c"; 802 reg = <0x0 0x00884000 0x0 0x4000>; 803 clock-names = "se"; 804 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&qup_i2c16_data_clk>; 807 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 811 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 812 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 813 interconnect-names = "qup-core", "qup-config", "qup-memory"; 814 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 815 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 816 dma-names = "tx", "rx"; 817 status = "disabled"; 818 }; 819 820 spi16: spi@884000 { 821 compatible = "qcom,geni-spi"; 822 reg = <0x0 0x00884000 0x0 0x4000>; 823 clock-names = "se"; 824 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 825 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 828 spi-max-frequency = <50000000>; 829 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 830 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 831 interconnect-names = "qup-core", "qup-config"; 832 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 833 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 834 dma-names = "tx", "rx"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 i2c17: i2c@888000 { 841 compatible = "qcom,geni-i2c"; 842 reg = <0x0 0x00888000 0x0 0x4000>; 843 clock-names = "se"; 844 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&qup_i2c17_data_clk>; 847 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 851 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 852 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 853 interconnect-names = "qup-core", "qup-config", "qup-memory"; 854 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 855 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 856 dma-names = "tx", "rx"; 857 status = "disabled"; 858 }; 859 860 spi17: spi@888000 { 861 compatible = "qcom,geni-spi"; 862 reg = <0x0 0x00888000 0x0 0x4000>; 863 clock-names = "se"; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 865 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 868 spi-max-frequency = <50000000>; 869 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 870 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 871 interconnect-names = "qup-core", "qup-config"; 872 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 873 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 874 dma-names = "tx", "rx"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 i2c18: i2c@88c000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0x0 0x0088c000 0x0 0x4000>; 883 clock-names = "se"; 884 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&qup_i2c18_data_clk>; 887 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 891 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 892 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 894 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 895 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 896 dma-names = "tx", "rx"; 897 status = "disabled"; 898 }; 899 900 spi18: spi@88c000 { 901 compatible = "qcom,geni-spi"; 902 reg = <0 0x0088c000 0 0x4000>; 903 clock-names = "se"; 904 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 905 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 908 spi-max-frequency = <50000000>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 910 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 911 interconnect-names = "qup-core", "qup-config"; 912 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 913 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 914 dma-names = "tx", "rx"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 920 i2c19: i2c@890000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0x0 0x00890000 0x0 0x4000>; 923 clock-names = "se"; 924 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_i2c19_data_clk>; 927 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 931 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 932 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 933 interconnect-names = "qup-core", "qup-config", "qup-memory"; 934 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 935 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 936 dma-names = "tx", "rx"; 937 status = "disabled"; 938 }; 939 940 spi19: spi@890000 { 941 compatible = "qcom,geni-spi"; 942 reg = <0 0x00890000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 945 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 948 spi-max-frequency = <50000000>; 949 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 950 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 951 interconnect-names = "qup-core", "qup-config"; 952 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 953 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 954 dma-names = "tx", "rx"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 status = "disabled"; 958 }; 959 960 i2c20: i2c@894000 { 961 compatible = "qcom,geni-i2c"; 962 reg = <0x0 0x00894000 0x0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_i2c20_data_clk>; 967 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 971 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 972 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 973 interconnect-names = "qup-core", "qup-config", "qup-memory"; 974 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 975 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 976 dma-names = "tx", "rx"; 977 status = "disabled"; 978 }; 979 980 uart20: serial@894000 { 981 compatible = "qcom,geni-uart"; 982 reg = <0 0x00894000 0 0x4000>; 983 clock-names = "se"; 984 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&qup_uart20_default>; 987 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 spi20: spi@894000 { 994 compatible = "qcom,geni-spi"; 995 reg = <0 0x00894000 0 0x4000>; 996 clock-names = "se"; 997 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 998 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1001 spi-max-frequency = <50000000>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1003 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1004 interconnect-names = "qup-core", "qup-config"; 1005 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1006 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1007 dma-names = "tx", "rx"; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 status = "disabled"; 1011 }; 1012 1013 i2c21: i2c@898000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0x0 0x00898000 0x0 0x4000>; 1016 clock-names = "se"; 1017 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_i2c21_data_clk>; 1020 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1024 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1025 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1028 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 status = "disabled"; 1031 }; 1032 1033 spi21: spi@898000 { 1034 compatible = "qcom,geni-spi"; 1035 reg = <0 0x00898000 0 0x4000>; 1036 clock-names = "se"; 1037 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1038 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1041 spi-max-frequency = <50000000>; 1042 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1043 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1044 interconnect-names = "qup-core", "qup-config"; 1045 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1046 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1047 dma-names = "tx", "rx"; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 }; 1053 1054 gpi_dma0: dma-controller@900000 { 1055 compatible = "qcom,sm8450-gpi-dma"; 1056 #dma-cells = <3>; 1057 reg = <0 0x900000 0 0x60000>; 1058 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1070 dma-channels = <12>; 1071 dma-channel-mask = <0x7e>; 1072 iommus = <&apps_smmu 0x5b6 0x0>; 1073 status = "disabled"; 1074 }; 1075 1076 qupv3_id_0: geniqup@9c0000 { 1077 compatible = "qcom,geni-se-qup"; 1078 reg = <0x0 0x009c0000 0x0 0x2000>; 1079 clock-names = "m-ahb", "s-ahb"; 1080 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1081 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1082 iommus = <&apps_smmu 0x5a3 0x0>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1084 interconnect-names = "qup-core"; 1085 #address-cells = <2>; 1086 #size-cells = <2>; 1087 ranges; 1088 status = "disabled"; 1089 1090 i2c0: i2c@980000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0x0 0x00980000 0x0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_i2c0_data_clk>; 1097 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1101 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1102 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1105 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1106 dma-names = "tx", "rx"; 1107 status = "disabled"; 1108 }; 1109 1110 spi0: spi@980000 { 1111 compatible = "qcom,geni-spi"; 1112 reg = <0x0 0x00980000 0x0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1115 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1118 power-domains = <&rpmhpd SM8450_CX>; 1119 operating-points-v2 = <&qup_opp_table_100mhz>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1121 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1122 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1123 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1124 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1125 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c1: i2c@984000 { 1133 compatible = "qcom,geni-i2c"; 1134 reg = <0x0 0x00984000 0x0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_i2c1_data_clk>; 1139 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1143 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1144 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1145 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1146 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1147 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 status = "disabled"; 1150 }; 1151 1152 spi1: spi@984000 { 1153 compatible = "qcom,geni-spi"; 1154 reg = <0x0 0x00984000 0x0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1157 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1162 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1163 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1164 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1165 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1166 dma-names = "tx", "rx"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 i2c2: i2c@988000 { 1173 compatible = "qcom,geni-i2c"; 1174 reg = <0x0 0x00988000 0x0 0x4000>; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_i2c2_data_clk>; 1179 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1183 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1184 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1185 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1186 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1187 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 status = "disabled"; 1190 }; 1191 1192 spi2: spi@988000 { 1193 compatible = "qcom,geni-spi"; 1194 reg = <0x0 0x00988000 0x0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1197 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1202 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1203 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1204 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1205 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1206 dma-names = "tx", "rx"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 1212 1213 i2c3: i2c@98c000 { 1214 compatible = "qcom,geni-i2c"; 1215 reg = <0x0 0x0098c000 0x0 0x4000>; 1216 clock-names = "se"; 1217 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1218 pinctrl-names = "default"; 1219 pinctrl-0 = <&qup_i2c3_data_clk>; 1220 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1224 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1225 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1226 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1227 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1228 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1229 dma-names = "tx", "rx"; 1230 status = "disabled"; 1231 }; 1232 1233 spi3: spi@98c000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0x0 0x0098c000 0x0 0x4000>; 1236 clock-names = "se"; 1237 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1238 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1243 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1246 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1247 dma-names = "tx", "rx"; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 i2c4: i2c@990000 { 1254 compatible = "qcom,geni-i2c"; 1255 reg = <0x0 0x00990000 0x0 0x4000>; 1256 clock-names = "se"; 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&qup_i2c4_data_clk>; 1260 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1264 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1265 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1266 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1267 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1268 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1269 dma-names = "tx", "rx"; 1270 status = "disabled"; 1271 }; 1272 1273 spi4: spi@990000 { 1274 compatible = "qcom,geni-spi"; 1275 reg = <0x0 0x00990000 0x0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1278 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1281 power-domains = <&rpmhpd SM8450_CX>; 1282 operating-points-v2 = <&qup_opp_table_100mhz>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1285 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1288 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1289 dma-names = "tx", "rx"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 i2c5: i2c@994000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0x0 0x00994000 0x0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&qup_i2c5_data_clk>; 1302 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1306 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1307 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi5: spi@994000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0x0 0x00994000 0x0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1320 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1323 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1324 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1325 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1326 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1327 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1328 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1329 dma-names = "tx", "rx"; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 1336 i2c6: i2c@998000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0x0 0x998000 0x0 0x4000>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c6_data_clk>; 1343 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1348 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1351 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi6: spi@998000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0x0 0x998000 0x0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1361 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1365 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1366 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1368 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1369 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 uart7: serial@99c000 { 1377 compatible = "qcom,geni-debug-uart"; 1378 reg = <0 0x0099c000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1383 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 }; 1389 1390 gpi_dma1: dma-controller@a00000 { 1391 compatible = "qcom,sm8450-gpi-dma"; 1392 #dma-cells = <3>; 1393 reg = <0 0xa00000 0 0x60000>; 1394 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1406 dma-channels = <12>; 1407 dma-channel-mask = <0x7e>; 1408 iommus = <&apps_smmu 0x56 0x0>; 1409 status = "disabled"; 1410 }; 1411 1412 qupv3_id_1: geniqup@ac0000 { 1413 compatible = "qcom,geni-se-qup"; 1414 reg = <0x0 0x00ac0000 0x0 0x6000>; 1415 clock-names = "m-ahb", "s-ahb"; 1416 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1417 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1418 iommus = <&apps_smmu 0x43 0x0>; 1419 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1420 interconnect-names = "qup-core"; 1421 #address-cells = <2>; 1422 #size-cells = <2>; 1423 ranges; 1424 status = "disabled"; 1425 1426 i2c8: i2c@a80000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0x0 0x00a80000 0x0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_i2c8_data_clk>; 1433 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1437 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1438 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1439 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1440 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1441 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1442 dma-names = "tx", "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 spi8: spi@a80000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0x0 0x00a80000 0x0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1451 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1455 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1456 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1457 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1458 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1459 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1460 dma-names = "tx", "rx"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 i2c9: i2c@a84000 { 1467 compatible = "qcom,geni-i2c"; 1468 reg = <0x0 0x00a84000 0x0 0x4000>; 1469 clock-names = "se"; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_i2c9_data_clk>; 1473 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1477 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1478 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1479 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1480 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1481 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1482 dma-names = "tx", "rx"; 1483 status = "disabled"; 1484 }; 1485 1486 spi9: spi@a84000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0x0 0x00a84000 0x0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1491 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1495 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1496 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1497 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1498 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1499 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1500 dma-names = "tx", "rx"; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 i2c10: i2c@a88000 { 1507 compatible = "qcom,geni-i2c"; 1508 reg = <0x0 0x00a88000 0x0 0x4000>; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_i2c10_data_clk>; 1513 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1518 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1519 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1520 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1521 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1522 dma-names = "tx", "rx"; 1523 status = "disabled"; 1524 }; 1525 1526 spi10: spi@a88000 { 1527 compatible = "qcom,geni-spi"; 1528 reg = <0x0 0x00a88000 0x0 0x4000>; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1531 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1534 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1535 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1536 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1537 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1538 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1539 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1540 dma-names = "tx", "rx"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 i2c11: i2c@a8c000 { 1547 compatible = "qcom,geni-i2c"; 1548 reg = <0x0 0x00a8c000 0x0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_i2c11_data_clk>; 1553 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1557 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1558 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1559 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1560 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1561 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1562 dma-names = "tx", "rx"; 1563 status = "disabled"; 1564 }; 1565 1566 spi11: spi@a8c000 { 1567 compatible = "qcom,geni-spi"; 1568 reg = <0x0 0x00a8c000 0x0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1571 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1574 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1575 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1576 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1579 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1580 dma-names = "tx", "rx"; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 i2c12: i2c@a90000 { 1587 compatible = "qcom,geni-i2c"; 1588 reg = <0x0 0x00a90000 0x0 0x4000>; 1589 clock-names = "se"; 1590 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1591 pinctrl-names = "default"; 1592 pinctrl-0 = <&qup_i2c12_data_clk>; 1593 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1597 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1598 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1599 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1600 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1601 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1602 dma-names = "tx", "rx"; 1603 status = "disabled"; 1604 }; 1605 1606 spi12: spi@a90000 { 1607 compatible = "qcom,geni-spi"; 1608 reg = <0x0 0x00a90000 0x0 0x4000>; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1611 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1612 pinctrl-names = "default"; 1613 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1614 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1615 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1616 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1617 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1618 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1619 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1620 dma-names = "tx", "rx"; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 i2c13: i2c@a94000 { 1627 compatible = "qcom,geni-i2c"; 1628 reg = <0 0x00a94000 0 0x4000>; 1629 clock-names = "se"; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_i2c13_data_clk>; 1633 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1635 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1636 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1637 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1638 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1639 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1640 dma-names = "tx", "rx"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 }; 1645 1646 spi13: spi@a94000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0x0 0x00a94000 0x0 0x4000>; 1649 clock-names = "se"; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1651 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1655 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1656 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1657 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1658 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1660 dma-names = "tx", "rx"; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 i2c14: i2c@a98000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00a98000 0 0x4000>; 1669 clock-names = "se"; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_i2c14_data_clk>; 1673 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1674 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1675 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1676 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1677 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1678 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1679 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1680 dma-names = "tx", "rx"; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 status = "disabled"; 1684 }; 1685 1686 spi14: spi@a98000 { 1687 compatible = "qcom,geni-spi"; 1688 reg = <0x0 0x00a98000 0x0 0x4000>; 1689 clock-names = "se"; 1690 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1691 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1692 pinctrl-names = "default"; 1693 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1694 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1695 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1696 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1697 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1698 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1699 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1700 dma-names = "tx", "rx"; 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 status = "disabled"; 1704 }; 1705 }; 1706 1707 pcie0: pci@1c00000 { 1708 compatible = "qcom,pcie-sm8450-pcie0"; 1709 reg = <0 0x01c00000 0 0x3000>, 1710 <0 0x60000000 0 0xf1d>, 1711 <0 0x60000f20 0 0xa8>, 1712 <0 0x60001000 0 0x1000>, 1713 <0 0x60100000 0 0x100000>; 1714 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1715 device_type = "pci"; 1716 linux,pci-domain = <0>; 1717 bus-range = <0x00 0xff>; 1718 num-lanes = <1>; 1719 1720 #address-cells = <3>; 1721 #size-cells = <2>; 1722 1723 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1724 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1725 1726 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupt-names = "msi"; 1728 #interrupt-cells = <1>; 1729 interrupt-map-mask = <0 0 0 0x7>; 1730 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1731 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1732 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1733 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1734 1735 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1736 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1737 <&pcie0_lane>, 1738 <&rpmhcc RPMH_CXO_CLK>, 1739 <&gcc GCC_PCIE_0_AUX_CLK>, 1740 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1741 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1742 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1743 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1744 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1745 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1746 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1747 clock-names = "pipe", 1748 "pipe_mux", 1749 "phy_pipe", 1750 "ref", 1751 "aux", 1752 "cfg", 1753 "bus_master", 1754 "bus_slave", 1755 "slave_q2a", 1756 "ddrss_sf_tbu", 1757 "aggre0", 1758 "aggre1"; 1759 1760 iommus = <&apps_smmu 0x1c00 0x7f>; 1761 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1762 <0x100 &apps_smmu 0x1c01 0x1>; 1763 1764 resets = <&gcc GCC_PCIE_0_BCR>; 1765 reset-names = "pci"; 1766 1767 power-domains = <&gcc PCIE_0_GDSC>; 1768 power-domain-names = "gdsc"; 1769 1770 phys = <&pcie0_lane>; 1771 phy-names = "pciephy"; 1772 1773 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1774 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1775 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&pcie0_default_state>; 1778 1779 status = "disabled"; 1780 }; 1781 1782 pcie0_phy: phy@1c06000 { 1783 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1784 reg = <0 0x01c06000 0 0x200>; 1785 #address-cells = <2>; 1786 #size-cells = <2>; 1787 ranges; 1788 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1789 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1790 <&gcc GCC_PCIE_0_CLKREF_EN>, 1791 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1792 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1793 1794 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1795 reset-names = "phy"; 1796 1797 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1798 assigned-clock-rates = <100000000>; 1799 1800 status = "disabled"; 1801 1802 pcie0_lane: phy@1c06200 { 1803 reg = <0 0x1c06e00 0 0x200>, /* tx */ 1804 <0 0x1c07000 0 0x200>, /* rx */ 1805 <0 0x1c06200 0 0x200>, /* pcs */ 1806 <0 0x1c06600 0 0x200>; /* pcs_pcie */ 1807 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1808 clock-names = "pipe0"; 1809 1810 #clock-cells = <0>; 1811 #phy-cells = <0>; 1812 clock-output-names = "pcie_0_pipe_clk"; 1813 }; 1814 }; 1815 1816 pcie1: pci@1c08000 { 1817 compatible = "qcom,pcie-sm8450-pcie1"; 1818 reg = <0 0x01c08000 0 0x3000>, 1819 <0 0x40000000 0 0xf1d>, 1820 <0 0x40000f20 0 0xa8>, 1821 <0 0x40001000 0 0x1000>, 1822 <0 0x40100000 0 0x100000>; 1823 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1824 device_type = "pci"; 1825 linux,pci-domain = <1>; 1826 bus-range = <0x00 0xff>; 1827 num-lanes = <2>; 1828 1829 #address-cells = <3>; 1830 #size-cells = <2>; 1831 1832 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1833 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1834 1835 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "msi"; 1837 #interrupt-cells = <1>; 1838 interrupt-map-mask = <0 0 0 0x7>; 1839 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1840 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1841 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1842 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1843 1844 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1845 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1846 <&pcie1_lane>, 1847 <&rpmhcc RPMH_CXO_CLK>, 1848 <&gcc GCC_PCIE_1_AUX_CLK>, 1849 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1850 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1851 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1852 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1853 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1854 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1855 clock-names = "pipe", 1856 "pipe_mux", 1857 "phy_pipe", 1858 "ref", 1859 "aux", 1860 "cfg", 1861 "bus_master", 1862 "bus_slave", 1863 "slave_q2a", 1864 "ddrss_sf_tbu", 1865 "aggre1"; 1866 1867 iommus = <&apps_smmu 0x1c80 0x7f>; 1868 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1869 <0x100 &apps_smmu 0x1c81 0x1>; 1870 1871 resets = <&gcc GCC_PCIE_1_BCR>; 1872 reset-names = "pci"; 1873 1874 power-domains = <&gcc PCIE_1_GDSC>; 1875 power-domain-names = "gdsc"; 1876 1877 phys = <&pcie1_lane>; 1878 phy-names = "pciephy"; 1879 1880 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; 1881 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1882 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&pcie1_default_state>; 1885 1886 status = "disabled"; 1887 }; 1888 1889 pcie1_phy: phy@1c0f000 { 1890 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1891 reg = <0 0x01c0f000 0 0x200>; 1892 #address-cells = <2>; 1893 #size-cells = <2>; 1894 ranges; 1895 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1896 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1897 <&gcc GCC_PCIE_1_CLKREF_EN>, 1898 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1899 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1900 1901 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1902 reset-names = "phy"; 1903 1904 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1905 assigned-clock-rates = <100000000>; 1906 1907 status = "disabled"; 1908 1909 pcie1_lane: phy@1c0e000 { 1910 reg = <0 0x1c0e000 0 0x200>, /* tx */ 1911 <0 0x1c0e200 0 0x300>, /* rx */ 1912 <0 0x1c0f200 0 0x200>, /* pcs */ 1913 <0 0x1c0e800 0 0x200>, /* tx */ 1914 <0 0x1c0ea00 0 0x300>, /* rx */ 1915 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ 1916 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1917 clock-names = "pipe0"; 1918 1919 #clock-cells = <0>; 1920 #phy-cells = <0>; 1921 clock-output-names = "pcie_1_pipe_clk"; 1922 }; 1923 }; 1924 1925 config_noc: interconnect@1500000 { 1926 compatible = "qcom,sm8450-config-noc"; 1927 reg = <0 0x01500000 0 0x1c000>; 1928 #interconnect-cells = <2>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 system_noc: interconnect@1680000 { 1933 compatible = "qcom,sm8450-system-noc"; 1934 reg = <0 0x01680000 0 0x1e200>; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 pcie_noc: interconnect@16c0000 { 1940 compatible = "qcom,sm8450-pcie-anoc"; 1941 reg = <0 0x016c0000 0 0xe280>; 1942 #interconnect-cells = <2>; 1943 qcom,bcm-voters = <&apps_bcm_voter>; 1944 }; 1945 1946 aggre1_noc: interconnect@16e0000 { 1947 compatible = "qcom,sm8450-aggre1-noc"; 1948 reg = <0 0x016e0000 0 0x1c080>; 1949 #interconnect-cells = <2>; 1950 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1951 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1952 qcom,bcm-voters = <&apps_bcm_voter>; 1953 }; 1954 1955 aggre2_noc: interconnect@1700000 { 1956 compatible = "qcom,sm8450-aggre2-noc"; 1957 reg = <0 0x01700000 0 0x31080>; 1958 #interconnect-cells = <2>; 1959 qcom,bcm-voters = <&apps_bcm_voter>; 1960 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1961 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1962 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1963 <&rpmhcc RPMH_IPA_CLK>; 1964 }; 1965 1966 mmss_noc: interconnect@1740000 { 1967 compatible = "qcom,sm8450-mmss-noc"; 1968 reg = <0 0x01740000 0 0x1f080>; 1969 #interconnect-cells = <2>; 1970 qcom,bcm-voters = <&apps_bcm_voter>; 1971 }; 1972 1973 tcsr_mutex: hwlock@1f40000 { 1974 compatible = "qcom,tcsr-mutex"; 1975 reg = <0x0 0x01f40000 0x0 0x40000>; 1976 #hwlock-cells = <1>; 1977 }; 1978 1979 usb_1_hsphy: phy@88e3000 { 1980 compatible = "qcom,sm8450-usb-hs-phy", 1981 "qcom,usb-snps-hs-7nm-phy"; 1982 reg = <0 0x088e3000 0 0x400>; 1983 status = "disabled"; 1984 #phy-cells = <0>; 1985 1986 clocks = <&rpmhcc RPMH_CXO_CLK>; 1987 clock-names = "ref"; 1988 1989 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1990 }; 1991 1992 usb_1_qmpphy: phy-wrapper@88e9000 { 1993 compatible = "qcom,sm8450-qmp-usb3-phy"; 1994 reg = <0 0x088e9000 0 0x200>, 1995 <0 0x088e8000 0 0x20>; 1996 status = "disabled"; 1997 #address-cells = <2>; 1998 #size-cells = <2>; 1999 ranges; 2000 2001 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2002 <&rpmhcc RPMH_CXO_CLK>, 2003 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2004 clock-names = "aux", "ref_clk_src", "com_aux"; 2005 2006 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2007 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2008 reset-names = "phy", "common"; 2009 2010 usb_1_ssphy: phy@88e9200 { 2011 reg = <0 0x088e9200 0 0x200>, 2012 <0 0x088e9400 0 0x200>, 2013 <0 0x088e9c00 0 0x400>, 2014 <0 0x088e9600 0 0x200>, 2015 <0 0x088e9800 0 0x200>, 2016 <0 0x088e9a00 0 0x100>; 2017 #phy-cells = <0>; 2018 #clock-cells = <1>; 2019 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2020 clock-names = "pipe0"; 2021 clock-output-names = "usb3_phy_pipe_clk_src"; 2022 }; 2023 }; 2024 2025 remoteproc_slpi: remoteproc@2400000 { 2026 compatible = "qcom,sm8450-slpi-pas"; 2027 reg = <0 0x02400000 0 0x4000>; 2028 2029 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2030 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2031 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2032 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2033 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2034 interrupt-names = "wdog", "fatal", "ready", 2035 "handover", "stop-ack"; 2036 2037 clocks = <&rpmhcc RPMH_CXO_CLK>; 2038 clock-names = "xo"; 2039 2040 power-domains = <&rpmhpd SM8450_LCX>, 2041 <&rpmhpd SM8450_LMX>; 2042 power-domain-names = "lcx", "lmx"; 2043 2044 memory-region = <&slpi_mem>; 2045 2046 qcom,qmp = <&aoss_qmp>; 2047 2048 qcom,smem-states = <&smp2p_slpi_out 0>; 2049 qcom,smem-state-names = "stop"; 2050 2051 status = "disabled"; 2052 2053 glink-edge { 2054 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2055 IPCC_MPROC_SIGNAL_GLINK_QMP 2056 IRQ_TYPE_EDGE_RISING>; 2057 mboxes = <&ipcc IPCC_CLIENT_SLPI 2058 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2059 2060 label = "slpi"; 2061 qcom,remote-pid = <3>; 2062 2063 fastrpc { 2064 compatible = "qcom,fastrpc"; 2065 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2066 label = "sdsp"; 2067 #address-cells = <1>; 2068 #size-cells = <0>; 2069 2070 compute-cb@1 { 2071 compatible = "qcom,fastrpc-compute-cb"; 2072 reg = <1>; 2073 iommus = <&apps_smmu 0x0541 0x0>; 2074 }; 2075 2076 compute-cb@2 { 2077 compatible = "qcom,fastrpc-compute-cb"; 2078 reg = <2>; 2079 iommus = <&apps_smmu 0x0542 0x0>; 2080 }; 2081 2082 compute-cb@3 { 2083 compatible = "qcom,fastrpc-compute-cb"; 2084 reg = <3>; 2085 iommus = <&apps_smmu 0x0543 0x0>; 2086 /* note: shared-cb = <4> in downstream */ 2087 }; 2088 }; 2089 }; 2090 }; 2091 2092 remoteproc_adsp: remoteproc@30000000 { 2093 compatible = "qcom,sm8450-adsp-pas"; 2094 reg = <0 0x030000000 0 0x100>; 2095 2096 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2097 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2098 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2099 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2100 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2101 interrupt-names = "wdog", "fatal", "ready", 2102 "handover", "stop-ack"; 2103 2104 clocks = <&rpmhcc RPMH_CXO_CLK>; 2105 clock-names = "xo"; 2106 2107 power-domains = <&rpmhpd SM8450_LCX>, 2108 <&rpmhpd SM8450_LMX>; 2109 power-domain-names = "lcx", "lmx"; 2110 2111 memory-region = <&adsp_mem>; 2112 2113 qcom,qmp = <&aoss_qmp>; 2114 2115 qcom,smem-states = <&smp2p_adsp_out 0>; 2116 qcom,smem-state-names = "stop"; 2117 2118 status = "disabled"; 2119 2120 remoteproc_adsp_glink: glink-edge { 2121 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2122 IPCC_MPROC_SIGNAL_GLINK_QMP 2123 IRQ_TYPE_EDGE_RISING>; 2124 mboxes = <&ipcc IPCC_CLIENT_LPASS 2125 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2126 2127 label = "lpass"; 2128 qcom,remote-pid = <2>; 2129 2130 fastrpc { 2131 compatible = "qcom,fastrpc"; 2132 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2133 label = "adsp"; 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 2137 compute-cb@3 { 2138 compatible = "qcom,fastrpc-compute-cb"; 2139 reg = <3>; 2140 iommus = <&apps_smmu 0x1803 0x0>; 2141 }; 2142 2143 compute-cb@4 { 2144 compatible = "qcom,fastrpc-compute-cb"; 2145 reg = <4>; 2146 iommus = <&apps_smmu 0x1804 0x0>; 2147 }; 2148 2149 compute-cb@5 { 2150 compatible = "qcom,fastrpc-compute-cb"; 2151 reg = <5>; 2152 iommus = <&apps_smmu 0x1805 0x0>; 2153 }; 2154 }; 2155 }; 2156 }; 2157 2158 remoteproc_cdsp: remoteproc@32300000 { 2159 compatible = "qcom,sm8450-cdsp-pas"; 2160 reg = <0 0x032300000 0 0x1400000>; 2161 2162 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2163 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2164 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2165 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2166 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2167 interrupt-names = "wdog", "fatal", "ready", 2168 "handover", "stop-ack"; 2169 2170 clocks = <&rpmhcc RPMH_CXO_CLK>; 2171 clock-names = "xo"; 2172 2173 power-domains = <&rpmhpd SM8450_CX>, 2174 <&rpmhpd SM8450_MXC>; 2175 power-domain-names = "cx", "mxc"; 2176 2177 memory-region = <&cdsp_mem>; 2178 2179 qcom,qmp = <&aoss_qmp>; 2180 2181 qcom,smem-states = <&smp2p_cdsp_out 0>; 2182 qcom,smem-state-names = "stop"; 2183 2184 status = "disabled"; 2185 2186 glink-edge { 2187 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2188 IPCC_MPROC_SIGNAL_GLINK_QMP 2189 IRQ_TYPE_EDGE_RISING>; 2190 mboxes = <&ipcc IPCC_CLIENT_CDSP 2191 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2192 2193 label = "cdsp"; 2194 qcom,remote-pid = <5>; 2195 2196 fastrpc { 2197 compatible = "qcom,fastrpc"; 2198 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2199 label = "cdsp"; 2200 #address-cells = <1>; 2201 #size-cells = <0>; 2202 2203 compute-cb@1 { 2204 compatible = "qcom,fastrpc-compute-cb"; 2205 reg = <1>; 2206 iommus = <&apps_smmu 0x2161 0x0400>, 2207 <&apps_smmu 0x1021 0x1420>; 2208 }; 2209 2210 compute-cb@2 { 2211 compatible = "qcom,fastrpc-compute-cb"; 2212 reg = <2>; 2213 iommus = <&apps_smmu 0x2162 0x0400>, 2214 <&apps_smmu 0x1022 0x1420>; 2215 }; 2216 2217 compute-cb@3 { 2218 compatible = "qcom,fastrpc-compute-cb"; 2219 reg = <3>; 2220 iommus = <&apps_smmu 0x2163 0x0400>, 2221 <&apps_smmu 0x1023 0x1420>; 2222 }; 2223 2224 compute-cb@4 { 2225 compatible = "qcom,fastrpc-compute-cb"; 2226 reg = <4>; 2227 iommus = <&apps_smmu 0x2164 0x0400>, 2228 <&apps_smmu 0x1024 0x1420>; 2229 }; 2230 2231 compute-cb@5 { 2232 compatible = "qcom,fastrpc-compute-cb"; 2233 reg = <5>; 2234 iommus = <&apps_smmu 0x2165 0x0400>, 2235 <&apps_smmu 0x1025 0x1420>; 2236 }; 2237 2238 compute-cb@6 { 2239 compatible = "qcom,fastrpc-compute-cb"; 2240 reg = <6>; 2241 iommus = <&apps_smmu 0x2166 0x0400>, 2242 <&apps_smmu 0x1026 0x1420>; 2243 }; 2244 2245 compute-cb@7 { 2246 compatible = "qcom,fastrpc-compute-cb"; 2247 reg = <7>; 2248 iommus = <&apps_smmu 0x2167 0x0400>, 2249 <&apps_smmu 0x1027 0x1420>; 2250 }; 2251 2252 compute-cb@8 { 2253 compatible = "qcom,fastrpc-compute-cb"; 2254 reg = <8>; 2255 iommus = <&apps_smmu 0x2168 0x0400>, 2256 <&apps_smmu 0x1028 0x1420>; 2257 }; 2258 2259 /* note: secure cb9 in downstream */ 2260 }; 2261 }; 2262 }; 2263 2264 remoteproc_mpss: remoteproc@4080000 { 2265 compatible = "qcom,sm8450-mpss-pas"; 2266 reg = <0x0 0x04080000 0x0 0x4040>; 2267 2268 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2269 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2270 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2271 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2272 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2273 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2274 interrupt-names = "wdog", "fatal", "ready", "handover", 2275 "stop-ack", "shutdown-ack"; 2276 2277 clocks = <&rpmhcc RPMH_CXO_CLK>; 2278 clock-names = "xo"; 2279 2280 power-domains = <&rpmhpd 0>, 2281 <&rpmhpd 12>; 2282 power-domain-names = "cx", "mss"; 2283 2284 memory-region = <&mpss_mem>; 2285 2286 qcom,qmp = <&aoss_qmp>; 2287 2288 qcom,smem-states = <&smp2p_modem_out 0>; 2289 qcom,smem-state-names = "stop"; 2290 2291 status = "disabled"; 2292 2293 glink-edge { 2294 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2295 IPCC_MPROC_SIGNAL_GLINK_QMP 2296 IRQ_TYPE_EDGE_RISING>; 2297 mboxes = <&ipcc IPCC_CLIENT_MPSS 2298 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2299 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2300 label = "modem"; 2301 qcom,remote-pid = <1>; 2302 }; 2303 }; 2304 2305 pdc: interrupt-controller@b220000 { 2306 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 2307 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2308 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 2309 <94 609 31>, <125 63 1>, <126 716 12>; 2310 #interrupt-cells = <2>; 2311 interrupt-parent = <&intc>; 2312 interrupt-controller; 2313 }; 2314 2315 tsens0: thermal-sensor@c263000 { 2316 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 2317 reg = <0 0x0c263000 0 0x1000>, /* TM */ 2318 <0 0x0c222000 0 0x1000>; /* SROT */ 2319 #qcom,sensors = <16>; 2320 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2321 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2322 interrupt-names = "uplow", "critical"; 2323 #thermal-sensor-cells = <1>; 2324 }; 2325 2326 tsens1: thermal-sensor@c265000 { 2327 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 2328 reg = <0 0x0c265000 0 0x1000>, /* TM */ 2329 <0 0x0c223000 0 0x1000>; /* SROT */ 2330 #qcom,sensors = <16>; 2331 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2333 interrupt-names = "uplow", "critical"; 2334 #thermal-sensor-cells = <1>; 2335 }; 2336 2337 aoss_qmp: power-controller@c300000 { 2338 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 2339 reg = <0 0x0c300000 0 0x400>; 2340 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2341 IRQ_TYPE_EDGE_RISING>; 2342 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2343 2344 #clock-cells = <0>; 2345 }; 2346 2347 ipcc: mailbox@ed18000 { 2348 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 2349 reg = <0 0x0ed18000 0 0x1000>; 2350 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupt-controller; 2352 #interrupt-cells = <3>; 2353 #mbox-cells = <2>; 2354 }; 2355 2356 tlmm: pinctrl@f100000 { 2357 compatible = "qcom,sm8450-tlmm"; 2358 reg = <0 0x0f100000 0 0x300000>; 2359 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2360 gpio-controller; 2361 #gpio-cells = <2>; 2362 interrupt-controller; 2363 #interrupt-cells = <2>; 2364 gpio-ranges = <&tlmm 0 0 211>; 2365 wakeup-parent = <&pdc>; 2366 2367 pcie0_default_state: pcie0-default-state { 2368 perst { 2369 pins = "gpio94"; 2370 function = "gpio"; 2371 drive-strength = <2>; 2372 bias-pull-down; 2373 }; 2374 2375 clkreq { 2376 pins = "gpio95"; 2377 function = "pcie0_clkreqn"; 2378 drive-strength = <2>; 2379 bias-pull-up; 2380 }; 2381 2382 wake { 2383 pins = "gpio96"; 2384 function = "gpio"; 2385 drive-strength = <2>; 2386 bias-pull-up; 2387 }; 2388 }; 2389 2390 pcie1_default_state: pcie1-default-state { 2391 perst { 2392 pins = "gpio97"; 2393 function = "gpio"; 2394 drive-strength = <2>; 2395 bias-pull-down; 2396 }; 2397 2398 clkreq { 2399 pins = "gpio98"; 2400 function = "pcie1_clkreqn"; 2401 drive-strength = <2>; 2402 bias-pull-up; 2403 }; 2404 2405 wake { 2406 pins = "gpio99"; 2407 function = "gpio"; 2408 drive-strength = <2>; 2409 bias-pull-up; 2410 }; 2411 }; 2412 2413 qup_i2c0_data_clk: qup-i2c0-data-clk { 2414 pins = "gpio0", "gpio1"; 2415 function = "qup0"; 2416 }; 2417 2418 qup_i2c1_data_clk: qup-i2c1-data-clk { 2419 pins = "gpio4", "gpio5"; 2420 function = "qup1"; 2421 }; 2422 2423 qup_i2c2_data_clk: qup-i2c2-data-clk { 2424 pins = "gpio8", "gpio9"; 2425 function = "qup2"; 2426 }; 2427 2428 qup_i2c3_data_clk: qup-i2c3-data-clk { 2429 pins = "gpio12", "gpio13"; 2430 function = "qup3"; 2431 }; 2432 2433 qup_i2c4_data_clk: qup-i2c4-data-clk { 2434 pins = "gpio16", "gpio17"; 2435 function = "qup4"; 2436 }; 2437 2438 qup_i2c5_data_clk: qup-i2c5-data-clk { 2439 pins = "gpio206", "gpio207"; 2440 function = "qup5"; 2441 }; 2442 2443 qup_i2c6_data_clk: qup-i2c6-data-clk { 2444 pins = "gpio20", "gpio21"; 2445 function = "qup6"; 2446 }; 2447 2448 qup_i2c8_data_clk: qup-i2c8-data-clk { 2449 pins = "gpio28", "gpio29"; 2450 function = "qup8"; 2451 }; 2452 2453 qup_i2c9_data_clk: qup-i2c9-data-clk { 2454 pins = "gpio32", "gpio33"; 2455 function = "qup9"; 2456 }; 2457 2458 qup_i2c10_data_clk: qup-i2c10-data-clk { 2459 pins = "gpio36", "gpio37"; 2460 function = "qup10"; 2461 }; 2462 2463 qup_i2c11_data_clk: qup-i2c11-data-clk { 2464 pins = "gpio40", "gpio41"; 2465 function = "qup11"; 2466 }; 2467 2468 qup_i2c12_data_clk: qup-i2c12-data-clk { 2469 pins = "gpio44", "gpio45"; 2470 function = "qup12"; 2471 }; 2472 2473 qup_i2c13_data_clk: qup-i2c13-data-clk { 2474 pins = "gpio48", "gpio49"; 2475 function = "qup13"; 2476 drive-strength = <2>; 2477 bias-pull-up; 2478 }; 2479 2480 qup_i2c14_data_clk: qup-i2c14-data-clk { 2481 pins = "gpio52", "gpio53"; 2482 function = "qup14"; 2483 drive-strength = <2>; 2484 bias-pull-up; 2485 }; 2486 2487 qup_i2c15_data_clk: qup-i2c15-data-clk { 2488 pins = "gpio56", "gpio57"; 2489 function = "qup15"; 2490 }; 2491 2492 qup_i2c16_data_clk: qup-i2c16-data-clk { 2493 pins = "gpio60", "gpio61"; 2494 function = "qup16"; 2495 }; 2496 2497 qup_i2c17_data_clk: qup-i2c17-data-clk { 2498 pins = "gpio64", "gpio65"; 2499 function = "qup17"; 2500 }; 2501 2502 qup_i2c18_data_clk: qup-i2c18-data-clk { 2503 pins = "gpio68", "gpio69"; 2504 function = "qup18"; 2505 }; 2506 2507 qup_i2c19_data_clk: qup-i2c19-data-clk { 2508 pins = "gpio72", "gpio73"; 2509 function = "qup19"; 2510 }; 2511 2512 qup_i2c20_data_clk: qup-i2c20-data-clk { 2513 pins = "gpio76", "gpio77"; 2514 function = "qup20"; 2515 }; 2516 2517 qup_i2c21_data_clk: qup-i2c21-data-clk { 2518 pins = "gpio80", "gpio81"; 2519 function = "qup21"; 2520 }; 2521 2522 qup_spi0_cs: qup-spi0-cs { 2523 pins = "gpio3"; 2524 function = "qup0"; 2525 }; 2526 2527 qup_spi0_data_clk: qup-spi0-data-clk { 2528 pins = "gpio0", "gpio1", "gpio2"; 2529 function = "qup0"; 2530 }; 2531 2532 qup_spi1_cs: qup-spi1-cs { 2533 pins = "gpio7"; 2534 function = "qup1"; 2535 }; 2536 2537 qup_spi1_data_clk: qup-spi1-data-clk { 2538 pins = "gpio4", "gpio5", "gpio6"; 2539 function = "qup1"; 2540 }; 2541 2542 qup_spi2_cs: qup-spi2-cs { 2543 pins = "gpio11"; 2544 function = "qup2"; 2545 }; 2546 2547 qup_spi2_data_clk: qup-spi2-data-clk { 2548 pins = "gpio8", "gpio9", "gpio10"; 2549 function = "qup2"; 2550 }; 2551 2552 qup_spi3_cs: qup-spi3-cs { 2553 pins = "gpio15"; 2554 function = "qup3"; 2555 }; 2556 2557 qup_spi3_data_clk: qup-spi3-data-clk { 2558 pins = "gpio12", "gpio13", "gpio14"; 2559 function = "qup3"; 2560 }; 2561 2562 qup_spi4_cs: qup-spi4-cs { 2563 pins = "gpio19"; 2564 function = "qup4"; 2565 drive-strength = <6>; 2566 bias-disable; 2567 }; 2568 2569 qup_spi4_data_clk: qup-spi4-data-clk { 2570 pins = "gpio16", "gpio17", "gpio18"; 2571 function = "qup4"; 2572 }; 2573 2574 qup_spi5_cs: qup-spi5-cs { 2575 pins = "gpio85"; 2576 function = "qup5"; 2577 }; 2578 2579 qup_spi5_data_clk: qup-spi5-data-clk { 2580 pins = "gpio206", "gpio207", "gpio84"; 2581 function = "qup5"; 2582 }; 2583 2584 qup_spi6_cs: qup-spi6-cs { 2585 pins = "gpio23"; 2586 function = "qup6"; 2587 }; 2588 2589 qup_spi6_data_clk: qup-spi6-data-clk { 2590 pins = "gpio20", "gpio21", "gpio22"; 2591 function = "qup6"; 2592 }; 2593 2594 qup_spi8_cs: qup-spi8-cs { 2595 pins = "gpio31"; 2596 function = "qup8"; 2597 }; 2598 2599 qup_spi8_data_clk: qup-spi8-data-clk { 2600 pins = "gpio28", "gpio29", "gpio30"; 2601 function = "qup8"; 2602 }; 2603 2604 qup_spi9_cs: qup-spi9-cs { 2605 pins = "gpio35"; 2606 function = "qup9"; 2607 }; 2608 2609 qup_spi9_data_clk: qup-spi9-data-clk { 2610 pins = "gpio32", "gpio33", "gpio34"; 2611 function = "qup9"; 2612 }; 2613 2614 qup_spi10_cs: qup-spi10-cs { 2615 pins = "gpio39"; 2616 function = "qup10"; 2617 }; 2618 2619 qup_spi10_data_clk: qup-spi10-data-clk { 2620 pins = "gpio36", "gpio37", "gpio38"; 2621 function = "qup10"; 2622 }; 2623 2624 qup_spi11_cs: qup-spi11-cs { 2625 pins = "gpio43"; 2626 function = "qup11"; 2627 }; 2628 2629 qup_spi11_data_clk: qup-spi11-data-clk { 2630 pins = "gpio40", "gpio41", "gpio42"; 2631 function = "qup11"; 2632 }; 2633 2634 qup_spi12_cs: qup-spi12-cs { 2635 pins = "gpio47"; 2636 function = "qup12"; 2637 }; 2638 2639 qup_spi12_data_clk: qup-spi12-data-clk { 2640 pins = "gpio44", "gpio45", "gpio46"; 2641 function = "qup12"; 2642 }; 2643 2644 qup_spi13_cs: qup-spi13-cs { 2645 pins = "gpio51"; 2646 function = "qup13"; 2647 }; 2648 2649 qup_spi13_data_clk: qup-spi13-data-clk { 2650 pins = "gpio48", "gpio49", "gpio50"; 2651 function = "qup13"; 2652 }; 2653 2654 qup_spi14_cs: qup-spi14-cs { 2655 pins = "gpio55"; 2656 function = "qup14"; 2657 }; 2658 2659 qup_spi14_data_clk: qup-spi14-data-clk { 2660 pins = "gpio52", "gpio53", "gpio54"; 2661 function = "qup14"; 2662 }; 2663 2664 qup_spi15_cs: qup-spi15-cs { 2665 pins = "gpio59"; 2666 function = "qup15"; 2667 }; 2668 2669 qup_spi15_data_clk: qup-spi15-data-clk { 2670 pins = "gpio56", "gpio57", "gpio58"; 2671 function = "qup15"; 2672 }; 2673 2674 qup_spi16_cs: qup-spi16-cs { 2675 pins = "gpio63"; 2676 function = "qup16"; 2677 }; 2678 2679 qup_spi16_data_clk: qup-spi16-data-clk { 2680 pins = "gpio60", "gpio61", "gpio62"; 2681 function = "qup16"; 2682 }; 2683 2684 qup_spi17_cs: qup-spi17-cs { 2685 pins = "gpio67"; 2686 function = "qup17"; 2687 }; 2688 2689 qup_spi17_data_clk: qup-spi17-data-clk { 2690 pins = "gpio64", "gpio65", "gpio66"; 2691 function = "qup17"; 2692 }; 2693 2694 qup_spi18_cs: qup-spi18-cs { 2695 pins = "gpio71"; 2696 function = "qup18"; 2697 drive-strength = <6>; 2698 bias-disable; 2699 }; 2700 2701 qup_spi18_data_clk: qup-spi18-data-clk { 2702 pins = "gpio68", "gpio69", "gpio70"; 2703 function = "qup18"; 2704 drive-strength = <6>; 2705 bias-disable; 2706 }; 2707 2708 qup_spi19_cs: qup-spi19-cs { 2709 pins = "gpio75"; 2710 function = "qup19"; 2711 drive-strength = <6>; 2712 bias-disable; 2713 }; 2714 2715 qup_spi19_data_clk: qup-spi19-data-clk { 2716 pins = "gpio72", "gpio73", "gpio74"; 2717 function = "qup19"; 2718 drive-strength = <6>; 2719 bias-disable; 2720 }; 2721 2722 qup_spi20_cs: qup-spi20-cs { 2723 pins = "gpio79"; 2724 function = "qup20"; 2725 }; 2726 2727 qup_spi20_data_clk: qup-spi20-data-clk { 2728 pins = "gpio76", "gpio77", "gpio78"; 2729 function = "qup20"; 2730 }; 2731 2732 qup_spi21_cs: qup-spi21-cs { 2733 pins = "gpio83"; 2734 function = "qup21"; 2735 }; 2736 2737 qup_spi21_data_clk: qup-spi21-data-clk { 2738 pins = "gpio80", "gpio81", "gpio82"; 2739 function = "qup21"; 2740 }; 2741 2742 qup_uart7_rx: qup-uart7-rx { 2743 pins = "gpio26"; 2744 function = "qup7"; 2745 drive-strength = <2>; 2746 bias-disable; 2747 }; 2748 2749 qup_uart7_tx: qup-uart7-tx { 2750 pins = "gpio27"; 2751 function = "qup7"; 2752 drive-strength = <2>; 2753 bias-disable; 2754 }; 2755 2756 qup_uart20_default: qup-uart20-default { 2757 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 2758 function = "qup20"; 2759 }; 2760 2761 }; 2762 2763 apps_smmu: iommu@15000000 { 2764 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 2765 reg = <0 0x15000000 0 0x100000>; 2766 #iommu-cells = <2>; 2767 #global-interrupts = <1>; 2768 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2777 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2803 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2804 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2805 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2806 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2807 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2814 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2817 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2819 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2820 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2821 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2823 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2824 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2825 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2826 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2827 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2828 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2829 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2830 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2832 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2836 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2839 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2840 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2842 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2843 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2848 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2849 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2854 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2855 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2856 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2857 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2858 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2859 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2860 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2861 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2862 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2863 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 2865 }; 2866 2867 intc: interrupt-controller@17100000 { 2868 compatible = "arm,gic-v3"; 2869 #interrupt-cells = <3>; 2870 interrupt-controller; 2871 #redistributor-regions = <1>; 2872 redistributor-stride = <0x0 0x40000>; 2873 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 2874 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 2875 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2876 }; 2877 2878 timer@17420000 { 2879 compatible = "arm,armv7-timer-mem"; 2880 #address-cells = <1>; 2881 #size-cells = <1>; 2882 ranges = <0 0 0 0x20000000>; 2883 reg = <0x0 0x17420000 0x0 0x1000>; 2884 clock-frequency = <19200000>; 2885 2886 frame@17421000 { 2887 frame-number = <0>; 2888 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2890 reg = <0x17421000 0x1000>, 2891 <0x17422000 0x1000>; 2892 }; 2893 2894 frame@17423000 { 2895 frame-number = <1>; 2896 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2897 reg = <0x17423000 0x1000>; 2898 status = "disabled"; 2899 }; 2900 2901 frame@17425000 { 2902 frame-number = <2>; 2903 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2904 reg = <0x17425000 0x1000>; 2905 status = "disabled"; 2906 }; 2907 2908 frame@17427000 { 2909 frame-number = <3>; 2910 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2911 reg = <0x17427000 0x1000>; 2912 status = "disabled"; 2913 }; 2914 2915 frame@17429000 { 2916 frame-number = <4>; 2917 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2918 reg = <0x17429000 0x1000>; 2919 status = "disabled"; 2920 }; 2921 2922 frame@1742b000 { 2923 frame-number = <5>; 2924 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2925 reg = <0x1742b000 0x1000>; 2926 status = "disabled"; 2927 }; 2928 2929 frame@1742d000 { 2930 frame-number = <6>; 2931 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2932 reg = <0x1742d000 0x1000>; 2933 status = "disabled"; 2934 }; 2935 }; 2936 2937 apps_rsc: rsc@17a00000 { 2938 label = "apps_rsc"; 2939 compatible = "qcom,rpmh-rsc"; 2940 reg = <0x0 0x17a00000 0x0 0x10000>, 2941 <0x0 0x17a10000 0x0 0x10000>, 2942 <0x0 0x17a20000 0x0 0x10000>, 2943 <0x0 0x17a30000 0x0 0x10000>; 2944 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 2945 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2948 qcom,tcs-offset = <0xd00>; 2949 qcom,drv-id = <2>; 2950 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 2951 <WAKE_TCS 2>, <CONTROL_TCS 0>; 2952 2953 apps_bcm_voter: bcm-voter { 2954 compatible = "qcom,bcm-voter"; 2955 }; 2956 2957 rpmhcc: clock-controller { 2958 compatible = "qcom,sm8450-rpmh-clk"; 2959 #clock-cells = <1>; 2960 clock-names = "xo"; 2961 clocks = <&xo_board>; 2962 }; 2963 2964 rpmhpd: power-controller { 2965 compatible = "qcom,sm8450-rpmhpd"; 2966 #power-domain-cells = <1>; 2967 operating-points-v2 = <&rpmhpd_opp_table>; 2968 2969 rpmhpd_opp_table: opp-table { 2970 compatible = "operating-points-v2"; 2971 2972 rpmhpd_opp_ret: opp1 { 2973 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2974 }; 2975 2976 rpmhpd_opp_min_svs: opp2 { 2977 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2978 }; 2979 2980 rpmhpd_opp_low_svs: opp3 { 2981 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2982 }; 2983 2984 rpmhpd_opp_svs: opp4 { 2985 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2986 }; 2987 2988 rpmhpd_opp_svs_l1: opp5 { 2989 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2990 }; 2991 2992 rpmhpd_opp_nom: opp6 { 2993 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2994 }; 2995 2996 rpmhpd_opp_nom_l1: opp7 { 2997 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2998 }; 2999 3000 rpmhpd_opp_nom_l2: opp8 { 3001 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3002 }; 3003 3004 rpmhpd_opp_turbo: opp9 { 3005 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3006 }; 3007 3008 rpmhpd_opp_turbo_l1: opp10 { 3009 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3010 }; 3011 }; 3012 }; 3013 }; 3014 3015 cpufreq_hw: cpufreq@17d91000 { 3016 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 3017 reg = <0 0x17d91000 0 0x1000>, 3018 <0 0x17d92000 0 0x1000>, 3019 <0 0x17d93000 0 0x1000>; 3020 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3021 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3022 clock-names = "xo", "alternate"; 3023 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3026 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3027 #freq-domain-cells = <1>; 3028 }; 3029 3030 gem_noc: interconnect@19100000 { 3031 compatible = "qcom,sm8450-gem-noc"; 3032 reg = <0 0x19100000 0 0xbb800>; 3033 #interconnect-cells = <2>; 3034 qcom,bcm-voters = <&apps_bcm_voter>; 3035 }; 3036 3037 system-cache-controller@19200000 { 3038 compatible = "qcom,sm8450-llcc"; 3039 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; 3040 reg-names = "llcc_base", "llcc_broadcast_base"; 3041 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3042 }; 3043 3044 ufs_mem_hc: ufshc@1d84000 { 3045 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 3046 "jedec,ufs-2.0"; 3047 reg = <0 0x01d84000 0 0x3000>; 3048 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3049 phys = <&ufs_mem_phy_lanes>; 3050 phy-names = "ufsphy"; 3051 lanes-per-direction = <2>; 3052 #reset-cells = <1>; 3053 resets = <&gcc GCC_UFS_PHY_BCR>; 3054 reset-names = "rst"; 3055 3056 power-domains = <&gcc UFS_PHY_GDSC>; 3057 3058 iommus = <&apps_smmu 0xe0 0x0>; 3059 3060 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 3061 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 3062 interconnect-names = "ufs-ddr", "cpu-ufs"; 3063 clock-names = 3064 "core_clk", 3065 "bus_aggr_clk", 3066 "iface_clk", 3067 "core_clk_unipro", 3068 "ref_clk", 3069 "tx_lane0_sync_clk", 3070 "rx_lane0_sync_clk", 3071 "rx_lane1_sync_clk"; 3072 clocks = 3073 <&gcc GCC_UFS_PHY_AXI_CLK>, 3074 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3075 <&gcc GCC_UFS_PHY_AHB_CLK>, 3076 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3077 <&rpmhcc RPMH_CXO_CLK>, 3078 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3079 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3080 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3081 freq-table-hz = 3082 <75000000 300000000>, 3083 <0 0>, 3084 <0 0>, 3085 <75000000 300000000>, 3086 <75000000 300000000>, 3087 <0 0>, 3088 <0 0>, 3089 <0 0>; 3090 status = "disabled"; 3091 }; 3092 3093 ufs_mem_phy: phy@1d87000 { 3094 compatible = "qcom,sm8450-qmp-ufs-phy"; 3095 reg = <0 0x01d87000 0 0xe10>; 3096 #address-cells = <2>; 3097 #size-cells = <2>; 3098 ranges; 3099 clock-names = "ref", "ref_aux", "qref"; 3100 clocks = <&rpmhcc RPMH_CXO_CLK>, 3101 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3102 <&gcc GCC_UFS_0_CLKREF_EN>; 3103 3104 resets = <&ufs_mem_hc 0>; 3105 reset-names = "ufsphy"; 3106 status = "disabled"; 3107 3108 ufs_mem_phy_lanes: phy@1d87400 { 3109 reg = <0 0x01d87400 0 0x108>, 3110 <0 0x01d87600 0 0x1e0>, 3111 <0 0x01d87c00 0 0x1dc>, 3112 <0 0x01d87800 0 0x108>, 3113 <0 0x01d87a00 0 0x1e0>; 3114 #phy-cells = <0>; 3115 #clock-cells = <0>; 3116 }; 3117 }; 3118 3119 usb_1: usb@a6f8800 { 3120 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 3121 reg = <0 0x0a6f8800 0 0x400>; 3122 status = "disabled"; 3123 #address-cells = <2>; 3124 #size-cells = <2>; 3125 ranges; 3126 3127 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3128 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3129 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3130 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3131 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3132 <&gcc GCC_USB3_0_CLKREF_EN>; 3133 clock-names = "cfg_noc", 3134 "core", 3135 "iface", 3136 "sleep", 3137 "mock_utmi", 3138 "xo"; 3139 3140 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3141 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3142 assigned-clock-rates = <19200000>, <200000000>; 3143 3144 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3145 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3146 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3147 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3148 interrupt-names = "hs_phy_irq", 3149 "ss_phy_irq", 3150 "dm_hs_phy_irq", 3151 "dp_hs_phy_irq"; 3152 3153 power-domains = <&gcc USB30_PRIM_GDSC>; 3154 3155 resets = <&gcc GCC_USB30_PRIM_BCR>; 3156 3157 usb_1_dwc3: usb@a600000 { 3158 compatible = "snps,dwc3"; 3159 reg = <0 0x0a600000 0 0xcd00>; 3160 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3161 iommus = <&apps_smmu 0x0 0x0>; 3162 snps,dis_u2_susphy_quirk; 3163 snps,dis_enblslpm_quirk; 3164 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3165 phy-names = "usb2-phy", "usb3-phy"; 3166 }; 3167 }; 3168 3169 nsp_noc: interconnect@320c0000 { 3170 compatible = "qcom,sm8450-nsp-noc"; 3171 reg = <0 0x320c0000 0 0x10000>; 3172 #interconnect-cells = <2>; 3173 qcom,bcm-voters = <&apps_bcm_voter>; 3174 }; 3175 3176 lpass_ag_noc: interconnect@3c40000 { 3177 compatible = "qcom,sm8450-lpass-ag-noc"; 3178 reg = <0 0x3c40000 0 0x17200>; 3179 #interconnect-cells = <2>; 3180 qcom,bcm-voters = <&apps_bcm_voter>; 3181 }; 3182 }; 3183 3184 thermal-zones { 3185 aoss0-thermal { 3186 polling-delay-passive = <0>; 3187 polling-delay = <0>; 3188 thermal-sensors = <&tsens0 0>; 3189 3190 trips { 3191 thermal-engine-config { 3192 temperature = <125000>; 3193 hysteresis = <1000>; 3194 type = "passive"; 3195 }; 3196 3197 reset-mon-cfg { 3198 temperature = <115000>; 3199 hysteresis = <5000>; 3200 type = "passive"; 3201 }; 3202 }; 3203 }; 3204 3205 cpuss0-thermal { 3206 polling-delay-passive = <0>; 3207 polling-delay = <0>; 3208 thermal-sensors = <&tsens0 1>; 3209 3210 trips { 3211 thermal-engine-config { 3212 temperature = <125000>; 3213 hysteresis = <1000>; 3214 type = "passive"; 3215 }; 3216 3217 reset-mon-cfg { 3218 temperature = <115000>; 3219 hysteresis = <5000>; 3220 type = "passive"; 3221 }; 3222 }; 3223 }; 3224 3225 cpuss1-thermal { 3226 polling-delay-passive = <0>; 3227 polling-delay = <0>; 3228 thermal-sensors = <&tsens0 2>; 3229 3230 trips { 3231 thermal-engine-config { 3232 temperature = <125000>; 3233 hysteresis = <1000>; 3234 type = "passive"; 3235 }; 3236 3237 reset-mon-cfg { 3238 temperature = <115000>; 3239 hysteresis = <5000>; 3240 type = "passive"; 3241 }; 3242 }; 3243 }; 3244 3245 cpuss3-thermal { 3246 polling-delay-passive = <0>; 3247 polling-delay = <0>; 3248 thermal-sensors = <&tsens0 3>; 3249 3250 trips { 3251 thermal-engine-config { 3252 temperature = <125000>; 3253 hysteresis = <1000>; 3254 type = "passive"; 3255 }; 3256 3257 reset-mon-cfg { 3258 temperature = <115000>; 3259 hysteresis = <5000>; 3260 type = "passive"; 3261 }; 3262 }; 3263 }; 3264 3265 cpuss4-thermal { 3266 polling-delay-passive = <0>; 3267 polling-delay = <0>; 3268 thermal-sensors = <&tsens0 4>; 3269 3270 trips { 3271 thermal-engine-config { 3272 temperature = <125000>; 3273 hysteresis = <1000>; 3274 type = "passive"; 3275 }; 3276 3277 reset-mon-cfg { 3278 temperature = <115000>; 3279 hysteresis = <5000>; 3280 type = "passive"; 3281 }; 3282 }; 3283 }; 3284 3285 cpu4-top-thermal { 3286 polling-delay-passive = <0>; 3287 polling-delay = <0>; 3288 thermal-sensors = <&tsens0 5>; 3289 3290 trips { 3291 cpu4_top_alert0: trip-point0 { 3292 temperature = <90000>; 3293 hysteresis = <2000>; 3294 type = "passive"; 3295 }; 3296 3297 cpu4_top_alert1: trip-point1 { 3298 temperature = <95000>; 3299 hysteresis = <2000>; 3300 type = "passive"; 3301 }; 3302 3303 cpu4_top_crit: cpu_crit { 3304 temperature = <110000>; 3305 hysteresis = <1000>; 3306 type = "critical"; 3307 }; 3308 }; 3309 }; 3310 3311 cpu4-bottom-thermal { 3312 polling-delay-passive = <0>; 3313 polling-delay = <0>; 3314 thermal-sensors = <&tsens0 6>; 3315 3316 trips { 3317 cpu4_bottom_alert0: trip-point0 { 3318 temperature = <90000>; 3319 hysteresis = <2000>; 3320 type = "passive"; 3321 }; 3322 3323 cpu4_bottom_alert1: trip-point1 { 3324 temperature = <95000>; 3325 hysteresis = <2000>; 3326 type = "passive"; 3327 }; 3328 3329 cpu4_bottom_crit: cpu_crit { 3330 temperature = <110000>; 3331 hysteresis = <1000>; 3332 type = "critical"; 3333 }; 3334 }; 3335 }; 3336 3337 cpu5-top-thermal { 3338 polling-delay-passive = <0>; 3339 polling-delay = <0>; 3340 thermal-sensors = <&tsens0 7>; 3341 3342 trips { 3343 cpu5_top_alert0: trip-point0 { 3344 temperature = <90000>; 3345 hysteresis = <2000>; 3346 type = "passive"; 3347 }; 3348 3349 cpu5_top_alert1: trip-point1 { 3350 temperature = <95000>; 3351 hysteresis = <2000>; 3352 type = "passive"; 3353 }; 3354 3355 cpu5_top_crit: cpu_crit { 3356 temperature = <110000>; 3357 hysteresis = <1000>; 3358 type = "critical"; 3359 }; 3360 }; 3361 }; 3362 3363 cpu5-bottom-thermal { 3364 polling-delay-passive = <0>; 3365 polling-delay = <0>; 3366 thermal-sensors = <&tsens0 8>; 3367 3368 trips { 3369 cpu5_bottom_alert0: trip-point0 { 3370 temperature = <90000>; 3371 hysteresis = <2000>; 3372 type = "passive"; 3373 }; 3374 3375 cpu5_bottom_alert1: trip-point1 { 3376 temperature = <95000>; 3377 hysteresis = <2000>; 3378 type = "passive"; 3379 }; 3380 3381 cpu5_bottom_crit: cpu_crit { 3382 temperature = <110000>; 3383 hysteresis = <1000>; 3384 type = "critical"; 3385 }; 3386 }; 3387 }; 3388 3389 cpu6-top-thermal { 3390 polling-delay-passive = <0>; 3391 polling-delay = <0>; 3392 thermal-sensors = <&tsens0 9>; 3393 3394 trips { 3395 cpu6_top_alert0: trip-point0 { 3396 temperature = <90000>; 3397 hysteresis = <2000>; 3398 type = "passive"; 3399 }; 3400 3401 cpu6_top_alert1: trip-point1 { 3402 temperature = <95000>; 3403 hysteresis = <2000>; 3404 type = "passive"; 3405 }; 3406 3407 cpu6_top_crit: cpu_crit { 3408 temperature = <110000>; 3409 hysteresis = <1000>; 3410 type = "critical"; 3411 }; 3412 }; 3413 }; 3414 3415 cpu6-bottom-thermal { 3416 polling-delay-passive = <0>; 3417 polling-delay = <0>; 3418 thermal-sensors = <&tsens0 10>; 3419 3420 trips { 3421 cpu6_bottom_alert0: trip-point0 { 3422 temperature = <90000>; 3423 hysteresis = <2000>; 3424 type = "passive"; 3425 }; 3426 3427 cpu6_bottom_alert1: trip-point1 { 3428 temperature = <95000>; 3429 hysteresis = <2000>; 3430 type = "passive"; 3431 }; 3432 3433 cpu6_bottom_crit: cpu_crit { 3434 temperature = <110000>; 3435 hysteresis = <1000>; 3436 type = "critical"; 3437 }; 3438 }; 3439 }; 3440 3441 cpu7-top-thermal { 3442 polling-delay-passive = <0>; 3443 polling-delay = <0>; 3444 thermal-sensors = <&tsens0 11>; 3445 3446 trips { 3447 cpu7_top_alert0: trip-point0 { 3448 temperature = <90000>; 3449 hysteresis = <2000>; 3450 type = "passive"; 3451 }; 3452 3453 cpu7_top_alert1: trip-point1 { 3454 temperature = <95000>; 3455 hysteresis = <2000>; 3456 type = "passive"; 3457 }; 3458 3459 cpu7_top_crit: cpu_crit { 3460 temperature = <110000>; 3461 hysteresis = <1000>; 3462 type = "critical"; 3463 }; 3464 }; 3465 }; 3466 3467 cpu7-middle-thermal { 3468 polling-delay-passive = <0>; 3469 polling-delay = <0>; 3470 thermal-sensors = <&tsens0 12>; 3471 3472 trips { 3473 cpu7_middle_alert0: trip-point0 { 3474 temperature = <90000>; 3475 hysteresis = <2000>; 3476 type = "passive"; 3477 }; 3478 3479 cpu7_middle_alert1: trip-point1 { 3480 temperature = <95000>; 3481 hysteresis = <2000>; 3482 type = "passive"; 3483 }; 3484 3485 cpu7_middle_crit: cpu_crit { 3486 temperature = <110000>; 3487 hysteresis = <1000>; 3488 type = "critical"; 3489 }; 3490 }; 3491 }; 3492 3493 cpu7-bottom-thermal { 3494 polling-delay-passive = <0>; 3495 polling-delay = <0>; 3496 thermal-sensors = <&tsens0 13>; 3497 3498 trips { 3499 cpu7_bottom_alert0: trip-point0 { 3500 temperature = <90000>; 3501 hysteresis = <2000>; 3502 type = "passive"; 3503 }; 3504 3505 cpu7_bottom_alert1: trip-point1 { 3506 temperature = <95000>; 3507 hysteresis = <2000>; 3508 type = "passive"; 3509 }; 3510 3511 cpu7_bottom_crit: cpu_crit { 3512 temperature = <110000>; 3513 hysteresis = <1000>; 3514 type = "critical"; 3515 }; 3516 }; 3517 }; 3518 3519 gpu-top-thermal { 3520 polling-delay-passive = <10>; 3521 polling-delay = <0>; 3522 thermal-sensors = <&tsens0 14>; 3523 3524 trips { 3525 thermal-engine-config { 3526 temperature = <125000>; 3527 hysteresis = <1000>; 3528 type = "passive"; 3529 }; 3530 3531 thermal-hal-config { 3532 temperature = <125000>; 3533 hysteresis = <1000>; 3534 type = "passive"; 3535 }; 3536 3537 reset-mon-cfg { 3538 temperature = <115000>; 3539 hysteresis = <5000>; 3540 type = "passive"; 3541 }; 3542 3543 gpu0_tj_cfg: tj_cfg { 3544 temperature = <95000>; 3545 hysteresis = <5000>; 3546 type = "passive"; 3547 }; 3548 }; 3549 }; 3550 3551 gpu-bottom-thermal { 3552 polling-delay-passive = <10>; 3553 polling-delay = <0>; 3554 thermal-sensors = <&tsens0 15>; 3555 3556 trips { 3557 thermal-engine-config { 3558 temperature = <125000>; 3559 hysteresis = <1000>; 3560 type = "passive"; 3561 }; 3562 3563 thermal-hal-config { 3564 temperature = <125000>; 3565 hysteresis = <1000>; 3566 type = "passive"; 3567 }; 3568 3569 reset-mon-cfg { 3570 temperature = <115000>; 3571 hysteresis = <5000>; 3572 type = "passive"; 3573 }; 3574 3575 gpu1_tj_cfg: tj_cfg { 3576 temperature = <95000>; 3577 hysteresis = <5000>; 3578 type = "passive"; 3579 }; 3580 }; 3581 }; 3582 3583 aoss1-thermal { 3584 polling-delay-passive = <0>; 3585 polling-delay = <0>; 3586 thermal-sensors = <&tsens1 0>; 3587 3588 trips { 3589 thermal-engine-config { 3590 temperature = <125000>; 3591 hysteresis = <1000>; 3592 type = "passive"; 3593 }; 3594 3595 reset-mon-cfg { 3596 temperature = <115000>; 3597 hysteresis = <5000>; 3598 type = "passive"; 3599 }; 3600 }; 3601 }; 3602 3603 cpu0-thermal { 3604 polling-delay-passive = <0>; 3605 polling-delay = <0>; 3606 thermal-sensors = <&tsens1 1>; 3607 3608 trips { 3609 cpu0_alert0: trip-point0 { 3610 temperature = <90000>; 3611 hysteresis = <2000>; 3612 type = "passive"; 3613 }; 3614 3615 cpu0_alert1: trip-point1 { 3616 temperature = <95000>; 3617 hysteresis = <2000>; 3618 type = "passive"; 3619 }; 3620 3621 cpu0_crit: cpu_crit { 3622 temperature = <110000>; 3623 hysteresis = <1000>; 3624 type = "critical"; 3625 }; 3626 }; 3627 }; 3628 3629 cpu1-thermal { 3630 polling-delay-passive = <0>; 3631 polling-delay = <0>; 3632 thermal-sensors = <&tsens1 2>; 3633 3634 trips { 3635 cpu1_alert0: trip-point0 { 3636 temperature = <90000>; 3637 hysteresis = <2000>; 3638 type = "passive"; 3639 }; 3640 3641 cpu1_alert1: trip-point1 { 3642 temperature = <95000>; 3643 hysteresis = <2000>; 3644 type = "passive"; 3645 }; 3646 3647 cpu1_crit: cpu_crit { 3648 temperature = <110000>; 3649 hysteresis = <1000>; 3650 type = "critical"; 3651 }; 3652 }; 3653 }; 3654 3655 cpu2-thermal { 3656 polling-delay-passive = <0>; 3657 polling-delay = <0>; 3658 thermal-sensors = <&tsens1 3>; 3659 3660 trips { 3661 cpu2_alert0: trip-point0 { 3662 temperature = <90000>; 3663 hysteresis = <2000>; 3664 type = "passive"; 3665 }; 3666 3667 cpu2_alert1: trip-point1 { 3668 temperature = <95000>; 3669 hysteresis = <2000>; 3670 type = "passive"; 3671 }; 3672 3673 cpu2_crit: cpu_crit { 3674 temperature = <110000>; 3675 hysteresis = <1000>; 3676 type = "critical"; 3677 }; 3678 }; 3679 }; 3680 3681 cpu3-thermal { 3682 polling-delay-passive = <0>; 3683 polling-delay = <0>; 3684 thermal-sensors = <&tsens1 4>; 3685 3686 trips { 3687 cpu3_alert0: trip-point0 { 3688 temperature = <90000>; 3689 hysteresis = <2000>; 3690 type = "passive"; 3691 }; 3692 3693 cpu3_alert1: trip-point1 { 3694 temperature = <95000>; 3695 hysteresis = <2000>; 3696 type = "passive"; 3697 }; 3698 3699 cpu3_crit: cpu_crit { 3700 temperature = <110000>; 3701 hysteresis = <1000>; 3702 type = "critical"; 3703 }; 3704 }; 3705 }; 3706 3707 cdsp0-thermal { 3708 polling-delay-passive = <10>; 3709 polling-delay = <0>; 3710 thermal-sensors = <&tsens1 5>; 3711 3712 trips { 3713 thermal-engine-config { 3714 temperature = <125000>; 3715 hysteresis = <1000>; 3716 type = "passive"; 3717 }; 3718 3719 thermal-hal-config { 3720 temperature = <125000>; 3721 hysteresis = <1000>; 3722 type = "passive"; 3723 }; 3724 3725 reset-mon-cfg { 3726 temperature = <115000>; 3727 hysteresis = <5000>; 3728 type = "passive"; 3729 }; 3730 3731 cdsp_0_config: junction-config { 3732 temperature = <95000>; 3733 hysteresis = <5000>; 3734 type = "passive"; 3735 }; 3736 }; 3737 }; 3738 3739 cdsp1-thermal { 3740 polling-delay-passive = <10>; 3741 polling-delay = <0>; 3742 thermal-sensors = <&tsens1 6>; 3743 3744 trips { 3745 thermal-engine-config { 3746 temperature = <125000>; 3747 hysteresis = <1000>; 3748 type = "passive"; 3749 }; 3750 3751 thermal-hal-config { 3752 temperature = <125000>; 3753 hysteresis = <1000>; 3754 type = "passive"; 3755 }; 3756 3757 reset-mon-cfg { 3758 temperature = <115000>; 3759 hysteresis = <5000>; 3760 type = "passive"; 3761 }; 3762 3763 cdsp_1_config: junction-config { 3764 temperature = <95000>; 3765 hysteresis = <5000>; 3766 type = "passive"; 3767 }; 3768 }; 3769 }; 3770 3771 cdsp2-thermal { 3772 polling-delay-passive = <10>; 3773 polling-delay = <0>; 3774 thermal-sensors = <&tsens1 7>; 3775 3776 trips { 3777 thermal-engine-config { 3778 temperature = <125000>; 3779 hysteresis = <1000>; 3780 type = "passive"; 3781 }; 3782 3783 thermal-hal-config { 3784 temperature = <125000>; 3785 hysteresis = <1000>; 3786 type = "passive"; 3787 }; 3788 3789 reset-mon-cfg { 3790 temperature = <115000>; 3791 hysteresis = <5000>; 3792 type = "passive"; 3793 }; 3794 3795 cdsp_2_config: junction-config { 3796 temperature = <95000>; 3797 hysteresis = <5000>; 3798 type = "passive"; 3799 }; 3800 }; 3801 }; 3802 3803 video-thermal { 3804 polling-delay-passive = <0>; 3805 polling-delay = <0>; 3806 thermal-sensors = <&tsens1 8>; 3807 3808 trips { 3809 thermal-engine-config { 3810 temperature = <125000>; 3811 hysteresis = <1000>; 3812 type = "passive"; 3813 }; 3814 3815 reset-mon-cfg { 3816 temperature = <115000>; 3817 hysteresis = <5000>; 3818 type = "passive"; 3819 }; 3820 }; 3821 }; 3822 3823 mem-thermal { 3824 polling-delay-passive = <10>; 3825 polling-delay = <0>; 3826 thermal-sensors = <&tsens1 9>; 3827 3828 trips { 3829 thermal-engine-config { 3830 temperature = <125000>; 3831 hysteresis = <1000>; 3832 type = "passive"; 3833 }; 3834 3835 ddr_config0: ddr0-config { 3836 temperature = <90000>; 3837 hysteresis = <5000>; 3838 type = "passive"; 3839 }; 3840 3841 reset-mon-cfg { 3842 temperature = <115000>; 3843 hysteresis = <5000>; 3844 type = "passive"; 3845 }; 3846 }; 3847 }; 3848 3849 modem0-thermal { 3850 polling-delay-passive = <0>; 3851 polling-delay = <0>; 3852 thermal-sensors = <&tsens1 10>; 3853 3854 trips { 3855 thermal-engine-config { 3856 temperature = <125000>; 3857 hysteresis = <1000>; 3858 type = "passive"; 3859 }; 3860 3861 mdmss0_config0: mdmss0-config0 { 3862 temperature = <102000>; 3863 hysteresis = <3000>; 3864 type = "passive"; 3865 }; 3866 3867 mdmss0_config1: mdmss0-config1 { 3868 temperature = <105000>; 3869 hysteresis = <3000>; 3870 type = "passive"; 3871 }; 3872 3873 reset-mon-cfg { 3874 temperature = <115000>; 3875 hysteresis = <5000>; 3876 type = "passive"; 3877 }; 3878 }; 3879 }; 3880 3881 modem1-thermal { 3882 polling-delay-passive = <0>; 3883 polling-delay = <0>; 3884 thermal-sensors = <&tsens1 11>; 3885 3886 trips { 3887 thermal-engine-config { 3888 temperature = <125000>; 3889 hysteresis = <1000>; 3890 type = "passive"; 3891 }; 3892 3893 mdmss1_config0: mdmss1-config0 { 3894 temperature = <102000>; 3895 hysteresis = <3000>; 3896 type = "passive"; 3897 }; 3898 3899 mdmss1_config1: mdmss1-config1 { 3900 temperature = <105000>; 3901 hysteresis = <3000>; 3902 type = "passive"; 3903 }; 3904 3905 reset-mon-cfg { 3906 temperature = <115000>; 3907 hysteresis = <5000>; 3908 type = "passive"; 3909 }; 3910 }; 3911 }; 3912 3913 modem2-thermal { 3914 polling-delay-passive = <0>; 3915 polling-delay = <0>; 3916 thermal-sensors = <&tsens1 12>; 3917 3918 trips { 3919 thermal-engine-config { 3920 temperature = <125000>; 3921 hysteresis = <1000>; 3922 type = "passive"; 3923 }; 3924 3925 mdmss2_config0: mdmss2-config0 { 3926 temperature = <102000>; 3927 hysteresis = <3000>; 3928 type = "passive"; 3929 }; 3930 3931 mdmss2_config1: mdmss2-config1 { 3932 temperature = <105000>; 3933 hysteresis = <3000>; 3934 type = "passive"; 3935 }; 3936 3937 reset-mon-cfg { 3938 temperature = <115000>; 3939 hysteresis = <5000>; 3940 type = "passive"; 3941 }; 3942 }; 3943 }; 3944 3945 modem3-thermal { 3946 polling-delay-passive = <0>; 3947 polling-delay = <0>; 3948 thermal-sensors = <&tsens1 13>; 3949 3950 trips { 3951 thermal-engine-config { 3952 temperature = <125000>; 3953 hysteresis = <1000>; 3954 type = "passive"; 3955 }; 3956 3957 mdmss3_config0: mdmss3-config0 { 3958 temperature = <102000>; 3959 hysteresis = <3000>; 3960 type = "passive"; 3961 }; 3962 3963 mdmss3_config1: mdmss3-config1 { 3964 temperature = <105000>; 3965 hysteresis = <3000>; 3966 type = "passive"; 3967 }; 3968 3969 reset-mon-cfg { 3970 temperature = <115000>; 3971 hysteresis = <5000>; 3972 type = "passive"; 3973 }; 3974 }; 3975 }; 3976 3977 camera0-thermal { 3978 polling-delay-passive = <0>; 3979 polling-delay = <0>; 3980 thermal-sensors = <&tsens1 14>; 3981 3982 trips { 3983 thermal-engine-config { 3984 temperature = <125000>; 3985 hysteresis = <1000>; 3986 type = "passive"; 3987 }; 3988 3989 reset-mon-cfg { 3990 temperature = <115000>; 3991 hysteresis = <5000>; 3992 type = "passive"; 3993 }; 3994 }; 3995 }; 3996 3997 camera1-thermal { 3998 polling-delay-passive = <0>; 3999 polling-delay = <0>; 4000 thermal-sensors = <&tsens1 15>; 4001 4002 trips { 4003 thermal-engine-config { 4004 temperature = <125000>; 4005 hysteresis = <1000>; 4006 type = "passive"; 4007 }; 4008 4009 reset-mon-cfg { 4010 temperature = <115000>; 4011 hysteresis = <5000>; 4012 type = "passive"; 4013 }; 4014 }; 4015 }; 4016 }; 4017 4018 timer { 4019 compatible = "arm,armv8-timer"; 4020 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4021 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4022 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4023 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4024 clock-frequency = <19200000>; 4025 }; 4026}; 4027