1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/interconnect/qcom,sm8450.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <76800000>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32000>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo780"; 52 reg = <0x0 0x0>; 53 enable-method = "psci"; 54 next-level-cache = <&L2_0>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 #cooling-cells = <2>; 59 clocks = <&cpufreq_hw 0>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo780"; 74 reg = <0x0 0x100>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_100>; 77 power-domains = <&CPU_PD1>; 78 power-domain-names = "psci"; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 #cooling-cells = <2>; 81 clocks = <&cpufreq_hw 0>; 82 L2_100: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU2: cpu@200 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo780"; 92 reg = <0x0 0x200>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_200>; 95 power-domains = <&CPU_PD2>; 96 power-domain-names = "psci"; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 #cooling-cells = <2>; 99 clocks = <&cpufreq_hw 0>; 100 L2_200: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 next-level-cache = <&L3_0>; 104 }; 105 }; 106 107 CPU3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "qcom,kryo780"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 next-level-cache = <&L2_300>; 113 power-domains = <&CPU_PD3>; 114 power-domain-names = "psci"; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 clocks = <&cpufreq_hw 0>; 118 L2_300: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU4: cpu@400 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo780"; 128 reg = <0x0 0x400>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_400>; 131 power-domains = <&CPU_PD4>; 132 power-domain-names = "psci"; 133 qcom,freq-domain = <&cpufreq_hw 1>; 134 #cooling-cells = <2>; 135 clocks = <&cpufreq_hw 1>; 136 L2_400: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU5: cpu@500 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo780"; 146 reg = <0x0 0x500>; 147 enable-method = "psci"; 148 next-level-cache = <&L2_500>; 149 power-domains = <&CPU_PD5>; 150 power-domain-names = "psci"; 151 qcom,freq-domain = <&cpufreq_hw 1>; 152 #cooling-cells = <2>; 153 clocks = <&cpufreq_hw 1>; 154 L2_500: l2-cache { 155 compatible = "cache"; 156 cache-level = <2>; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU6: cpu@600 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo780"; 164 reg = <0x0 0x600>; 165 enable-method = "psci"; 166 next-level-cache = <&L2_600>; 167 power-domains = <&CPU_PD6>; 168 power-domain-names = "psci"; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 #cooling-cells = <2>; 171 clocks = <&cpufreq_hw 1>; 172 L2_600: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 CPU7: cpu@700 { 180 device_type = "cpu"; 181 compatible = "qcom,kryo780"; 182 reg = <0x0 0x700>; 183 enable-method = "psci"; 184 next-level-cache = <&L2_700>; 185 power-domains = <&CPU_PD7>; 186 power-domain-names = "psci"; 187 qcom,freq-domain = <&cpufreq_hw 2>; 188 #cooling-cells = <2>; 189 clocks = <&cpufreq_hw 2>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 cpu-map { 198 cluster0 { 199 core0 { 200 cpu = <&CPU0>; 201 }; 202 203 core1 { 204 cpu = <&CPU1>; 205 }; 206 207 core2 { 208 cpu = <&CPU2>; 209 }; 210 211 core3 { 212 cpu = <&CPU3>; 213 }; 214 215 core4 { 216 cpu = <&CPU4>; 217 }; 218 219 core5 { 220 cpu = <&CPU5>; 221 }; 222 223 core6 { 224 cpu = <&CPU6>; 225 }; 226 227 core7 { 228 cpu = <&CPU7>; 229 }; 230 }; 231 }; 232 233 idle-states { 234 entry-method = "psci"; 235 236 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "silver-rail-power-collapse"; 239 arm,psci-suspend-param = <0x40000004>; 240 entry-latency-us = <800>; 241 exit-latency-us = <750>; 242 min-residency-us = <4090>; 243 local-timer-stop; 244 }; 245 246 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "gold-rail-power-collapse"; 249 arm,psci-suspend-param = <0x40000004>; 250 entry-latency-us = <600>; 251 exit-latency-us = <1550>; 252 min-residency-us = <4791>; 253 local-timer-stop; 254 }; 255 }; 256 257 domain-idle-states { 258 CLUSTER_SLEEP_0: cluster-sleep-0 { 259 compatible = "domain-idle-state"; 260 arm,psci-suspend-param = <0x41000044>; 261 entry-latency-us = <1050>; 262 exit-latency-us = <2500>; 263 min-residency-us = <5309>; 264 }; 265 266 CLUSTER_SLEEP_1: cluster-sleep-1 { 267 compatible = "domain-idle-state"; 268 arm,psci-suspend-param = <0x4100c344>; 269 entry-latency-us = <2700>; 270 exit-latency-us = <3500>; 271 min-residency-us = <13959>; 272 }; 273 }; 274 }; 275 276 firmware { 277 scm: scm { 278 compatible = "qcom,scm-sm8450", "qcom,scm"; 279 qcom,dload-mode = <&tcsr 0x13000>; 280 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 281 #reset-cells = <1>; 282 }; 283 }; 284 285 clk_virt: interconnect-0 { 286 compatible = "qcom,sm8450-clk-virt"; 287 #interconnect-cells = <2>; 288 qcom,bcm-voters = <&apps_bcm_voter>; 289 }; 290 291 mc_virt: interconnect-1 { 292 compatible = "qcom,sm8450-mc-virt"; 293 #interconnect-cells = <2>; 294 qcom,bcm-voters = <&apps_bcm_voter>; 295 }; 296 297 memory@a0000000 { 298 device_type = "memory"; 299 /* We expect the bootloader to fill in the size */ 300 reg = <0x0 0xa0000000 0x0 0x0>; 301 }; 302 303 pmu { 304 compatible = "arm,armv8-pmuv3"; 305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 306 }; 307 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 312 CPU_PD0: power-domain-cpu0 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD1: power-domain-cpu1 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD2: power-domain-cpu2 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 328 }; 329 330 CPU_PD3: power-domain-cpu3 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 334 }; 335 336 CPU_PD4: power-domain-cpu4 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0>; 340 }; 341 342 CPU_PD5: power-domain-cpu5 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&BIG_CPU_SLEEP_0>; 346 }; 347 348 CPU_PD6: power-domain-cpu6 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&BIG_CPU_SLEEP_0>; 352 }; 353 354 CPU_PD7: power-domain-cpu7 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0>; 358 }; 359 360 CLUSTER_PD: power-domain-cpu-cluster0 { 361 #power-domain-cells = <0>; 362 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 363 }; 364 }; 365 366 qup_opp_table_100mhz: opp-table-qup { 367 compatible = "operating-points-v2"; 368 369 opp-50000000 { 370 opp-hz = /bits/ 64 <50000000>; 371 required-opps = <&rpmhpd_opp_min_svs>; 372 }; 373 374 opp-75000000 { 375 opp-hz = /bits/ 64 <75000000>; 376 required-opps = <&rpmhpd_opp_low_svs>; 377 }; 378 379 opp-100000000 { 380 opp-hz = /bits/ 64 <100000000>; 381 required-opps = <&rpmhpd_opp_svs>; 382 }; 383 }; 384 385 reserved_memory: reserved-memory { 386 #address-cells = <2>; 387 #size-cells = <2>; 388 ranges; 389 390 hyp_mem: memory@80000000 { 391 reg = <0x0 0x80000000 0x0 0x600000>; 392 no-map; 393 }; 394 395 xbl_dt_log_mem: memory@80600000 { 396 reg = <0x0 0x80600000 0x0 0x40000>; 397 no-map; 398 }; 399 400 xbl_ramdump_mem: memory@80640000 { 401 reg = <0x0 0x80640000 0x0 0x180000>; 402 no-map; 403 }; 404 405 xbl_sc_mem: memory@807c0000 { 406 reg = <0x0 0x807c0000 0x0 0x40000>; 407 no-map; 408 }; 409 410 aop_image_mem: memory@80800000 { 411 reg = <0x0 0x80800000 0x0 0x60000>; 412 no-map; 413 }; 414 415 aop_cmd_db_mem: memory@80860000 { 416 compatible = "qcom,cmd-db"; 417 reg = <0x0 0x80860000 0x0 0x20000>; 418 no-map; 419 }; 420 421 aop_config_mem: memory@80880000 { 422 reg = <0x0 0x80880000 0x0 0x20000>; 423 no-map; 424 }; 425 426 tme_crash_dump_mem: memory@808a0000 { 427 reg = <0x0 0x808a0000 0x0 0x40000>; 428 no-map; 429 }; 430 431 tme_log_mem: memory@808e0000 { 432 reg = <0x0 0x808e0000 0x0 0x4000>; 433 no-map; 434 }; 435 436 uefi_log_mem: memory@808e4000 { 437 reg = <0x0 0x808e4000 0x0 0x10000>; 438 no-map; 439 }; 440 441 /* secdata region can be reused by apps */ 442 smem: memory@80900000 { 443 compatible = "qcom,smem"; 444 reg = <0x0 0x80900000 0x0 0x200000>; 445 hwlocks = <&tcsr_mutex 3>; 446 no-map; 447 }; 448 449 cpucp_fw_mem: memory@80b00000 { 450 reg = <0x0 0x80b00000 0x0 0x100000>; 451 no-map; 452 }; 453 454 cdsp_secure_heap: memory@80c00000 { 455 reg = <0x0 0x80c00000 0x0 0x4600000>; 456 no-map; 457 }; 458 459 video_mem: memory@85700000 { 460 reg = <0x0 0x85700000 0x0 0x700000>; 461 no-map; 462 }; 463 464 adsp_mem: memory@85e00000 { 465 reg = <0x0 0x85e00000 0x0 0x2100000>; 466 no-map; 467 }; 468 469 slpi_mem: memory@88000000 { 470 reg = <0x0 0x88000000 0x0 0x1900000>; 471 no-map; 472 }; 473 474 cdsp_mem: memory@89900000 { 475 reg = <0x0 0x89900000 0x0 0x2000000>; 476 no-map; 477 }; 478 479 ipa_fw_mem: memory@8b900000 { 480 reg = <0x0 0x8b900000 0x0 0x10000>; 481 no-map; 482 }; 483 484 ipa_gsi_mem: memory@8b910000 { 485 reg = <0x0 0x8b910000 0x0 0xa000>; 486 no-map; 487 }; 488 489 gpu_micro_code_mem: memory@8b91a000 { 490 reg = <0x0 0x8b91a000 0x0 0x2000>; 491 no-map; 492 }; 493 494 spss_region_mem: memory@8ba00000 { 495 reg = <0x0 0x8ba00000 0x0 0x180000>; 496 no-map; 497 }; 498 499 /* First part of the "SPU secure shared memory" region */ 500 spu_tz_shared_mem: memory@8bb80000 { 501 reg = <0x0 0x8bb80000 0x0 0x60000>; 502 no-map; 503 }; 504 505 /* Second part of the "SPU secure shared memory" region */ 506 spu_modem_shared_mem: memory@8bbe0000 { 507 reg = <0x0 0x8bbe0000 0x0 0x20000>; 508 no-map; 509 }; 510 511 mpss_mem: memory@8bc00000 { 512 reg = <0x0 0x8bc00000 0x0 0x13200000>; 513 no-map; 514 }; 515 516 cvp_mem: memory@9ee00000 { 517 reg = <0x0 0x9ee00000 0x0 0x700000>; 518 no-map; 519 }; 520 521 camera_mem: memory@9f500000 { 522 reg = <0x0 0x9f500000 0x0 0x800000>; 523 no-map; 524 }; 525 526 rmtfs_mem: memory@9fd00000 { 527 compatible = "qcom,rmtfs-mem"; 528 reg = <0x0 0x9fd00000 0x0 0x280000>; 529 no-map; 530 531 qcom,client-id = <1>; 532 qcom,vmid = <15>; 533 }; 534 535 xbl_sc_mem2: memory@a6e00000 { 536 reg = <0x0 0xa6e00000 0x0 0x40000>; 537 no-map; 538 }; 539 540 global_sync_mem: memory@a6f00000 { 541 reg = <0x0 0xa6f00000 0x0 0x100000>; 542 no-map; 543 }; 544 545 /* uefi region can be reused by APPS */ 546 547 /* Linux kernel image is loaded at 0xa0000000 */ 548 549 oem_vm_mem: memory@bb000000 { 550 reg = <0x0 0xbb000000 0x0 0x5000000>; 551 no-map; 552 }; 553 554 mte_mem: memory@c0000000 { 555 reg = <0x0 0xc0000000 0x0 0x20000000>; 556 no-map; 557 }; 558 559 qheebsp_reserved_mem: memory@e0000000 { 560 reg = <0x0 0xe0000000 0x0 0x600000>; 561 no-map; 562 }; 563 564 cpusys_vm_mem: memory@e0600000 { 565 reg = <0x0 0xe0600000 0x0 0x400000>; 566 no-map; 567 }; 568 569 hyp_reserved_mem: memory@e0a00000 { 570 reg = <0x0 0xe0a00000 0x0 0x100000>; 571 no-map; 572 }; 573 574 trust_ui_vm_mem: memory@e0b00000 { 575 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 576 no-map; 577 }; 578 579 trust_ui_vm_qrtr: memory@e55f3000 { 580 reg = <0x0 0xe55f3000 0x0 0x9000>; 581 no-map; 582 }; 583 584 trust_ui_vm_vblk0_ring: memory@e55fc000 { 585 reg = <0x0 0xe55fc000 0x0 0x4000>; 586 no-map; 587 }; 588 589 trust_ui_vm_swiotlb: memory@e5600000 { 590 reg = <0x0 0xe5600000 0x0 0x100000>; 591 no-map; 592 }; 593 594 tz_stat_mem: memory@e8800000 { 595 reg = <0x0 0xe8800000 0x0 0x100000>; 596 no-map; 597 }; 598 599 tags_mem: memory@e8900000 { 600 reg = <0x0 0xe8900000 0x0 0x1200000>; 601 no-map; 602 }; 603 604 qtee_mem: memory@e9b00000 { 605 reg = <0x0 0xe9b00000 0x0 0x500000>; 606 no-map; 607 }; 608 609 trusted_apps_mem: memory@ea000000 { 610 reg = <0x0 0xea000000 0x0 0x3900000>; 611 no-map; 612 }; 613 614 trusted_apps_ext_mem: memory@ed900000 { 615 reg = <0x0 0xed900000 0x0 0x3b00000>; 616 no-map; 617 }; 618 }; 619 620 smp2p-adsp { 621 compatible = "qcom,smp2p"; 622 qcom,smem = <443>, <429>; 623 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 624 IPCC_MPROC_SIGNAL_SMP2P 625 IRQ_TYPE_EDGE_RISING>; 626 mboxes = <&ipcc IPCC_CLIENT_LPASS 627 IPCC_MPROC_SIGNAL_SMP2P>; 628 629 qcom,local-pid = <0>; 630 qcom,remote-pid = <2>; 631 632 smp2p_adsp_out: master-kernel { 633 qcom,entry-name = "master-kernel"; 634 #qcom,smem-state-cells = <1>; 635 }; 636 637 smp2p_adsp_in: slave-kernel { 638 qcom,entry-name = "slave-kernel"; 639 interrupt-controller; 640 #interrupt-cells = <2>; 641 }; 642 }; 643 644 smp2p-cdsp { 645 compatible = "qcom,smp2p"; 646 qcom,smem = <94>, <432>; 647 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 648 IPCC_MPROC_SIGNAL_SMP2P 649 IRQ_TYPE_EDGE_RISING>; 650 mboxes = <&ipcc IPCC_CLIENT_CDSP 651 IPCC_MPROC_SIGNAL_SMP2P>; 652 653 qcom,local-pid = <0>; 654 qcom,remote-pid = <5>; 655 656 smp2p_cdsp_out: master-kernel { 657 qcom,entry-name = "master-kernel"; 658 #qcom,smem-state-cells = <1>; 659 }; 660 661 smp2p_cdsp_in: slave-kernel { 662 qcom,entry-name = "slave-kernel"; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 }; 666 }; 667 668 smp2p-modem { 669 compatible = "qcom,smp2p"; 670 qcom,smem = <435>, <428>; 671 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 672 IPCC_MPROC_SIGNAL_SMP2P 673 IRQ_TYPE_EDGE_RISING>; 674 mboxes = <&ipcc IPCC_CLIENT_MPSS 675 IPCC_MPROC_SIGNAL_SMP2P>; 676 677 qcom,local-pid = <0>; 678 qcom,remote-pid = <1>; 679 680 smp2p_modem_out: master-kernel { 681 qcom,entry-name = "master-kernel"; 682 #qcom,smem-state-cells = <1>; 683 }; 684 685 smp2p_modem_in: slave-kernel { 686 qcom,entry-name = "slave-kernel"; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 }; 690 691 ipa_smp2p_out: ipa-ap-to-modem { 692 qcom,entry-name = "ipa"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 ipa_smp2p_in: ipa-modem-to-ap { 697 qcom,entry-name = "ipa"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 }; 702 703 smp2p-slpi { 704 compatible = "qcom,smp2p"; 705 qcom,smem = <481>, <430>; 706 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 mboxes = <&ipcc IPCC_CLIENT_SLPI 710 IPCC_MPROC_SIGNAL_SMP2P>; 711 712 qcom,local-pid = <0>; 713 qcom,remote-pid = <3>; 714 715 smp2p_slpi_out: master-kernel { 716 qcom,entry-name = "master-kernel"; 717 #qcom,smem-state-cells = <1>; 718 }; 719 720 smp2p_slpi_in: slave-kernel { 721 qcom,entry-name = "slave-kernel"; 722 interrupt-controller; 723 #interrupt-cells = <2>; 724 }; 725 }; 726 727 soc: soc@0 { 728 #address-cells = <2>; 729 #size-cells = <2>; 730 ranges = <0 0 0 0 0x10 0>; 731 dma-ranges = <0 0 0 0 0x10 0>; 732 compatible = "simple-bus"; 733 734 gcc: clock-controller@100000 { 735 compatible = "qcom,gcc-sm8450"; 736 reg = <0x0 0x00100000 0x0 0x1f4200>; 737 #clock-cells = <1>; 738 #reset-cells = <1>; 739 #power-domain-cells = <1>; 740 clocks = <&rpmhcc RPMH_CXO_CLK>, 741 <&sleep_clk>, 742 <&pcie0_lane>, 743 <&pcie1_lane>, 744 <0>, 745 <&ufs_mem_phy_lanes 0>, 746 <&ufs_mem_phy_lanes 1>, 747 <&ufs_mem_phy_lanes 2>, 748 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 749 clock-names = "bi_tcxo", 750 "sleep_clk", 751 "pcie_0_pipe_clk", 752 "pcie_1_pipe_clk", 753 "pcie_1_phy_aux_clk", 754 "ufs_phy_rx_symbol_0_clk", 755 "ufs_phy_rx_symbol_1_clk", 756 "ufs_phy_tx_symbol_0_clk", 757 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 758 }; 759 760 gpi_dma2: dma-controller@800000 { 761 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 762 #dma-cells = <3>; 763 reg = <0 0x00800000 0 0x60000>; 764 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 776 dma-channels = <12>; 777 dma-channel-mask = <0x7e>; 778 iommus = <&apps_smmu 0x496 0x0>; 779 status = "disabled"; 780 }; 781 782 qupv3_id_2: geniqup@8c0000 { 783 compatible = "qcom,geni-se-qup"; 784 reg = <0x0 0x008c0000 0x0 0x2000>; 785 clock-names = "m-ahb", "s-ahb"; 786 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 787 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 788 iommus = <&apps_smmu 0x483 0x0>; 789 #address-cells = <2>; 790 #size-cells = <2>; 791 ranges; 792 status = "disabled"; 793 794 i2c15: i2c@880000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0x0 0x00880000 0x0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&qup_i2c15_data_clk>; 801 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 805 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 806 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 807 interconnect-names = "qup-core", "qup-config", "qup-memory"; 808 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 809 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 810 dma-names = "tx", "rx"; 811 status = "disabled"; 812 }; 813 814 spi15: spi@880000 { 815 compatible = "qcom,geni-spi"; 816 reg = <0x0 0x00880000 0x0 0x4000>; 817 clock-names = "se"; 818 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 819 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 822 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 823 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 824 interconnect-names = "qup-core", "qup-config"; 825 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 826 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 827 dma-names = "tx", "rx"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 status = "disabled"; 831 }; 832 833 i2c16: i2c@884000 { 834 compatible = "qcom,geni-i2c"; 835 reg = <0x0 0x00884000 0x0 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&qup_i2c16_data_clk>; 840 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 844 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 845 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 846 interconnect-names = "qup-core", "qup-config", "qup-memory"; 847 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 848 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 849 dma-names = "tx", "rx"; 850 status = "disabled"; 851 }; 852 853 spi16: spi@884000 { 854 compatible = "qcom,geni-spi"; 855 reg = <0x0 0x00884000 0x0 0x4000>; 856 clock-names = "se"; 857 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 858 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 861 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 862 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 863 interconnect-names = "qup-core", "qup-config"; 864 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 865 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 i2c17: i2c@888000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0x0 0x00888000 0x0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c17_data_clk>; 879 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 883 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 884 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 885 interconnect-names = "qup-core", "qup-config", "qup-memory"; 886 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 887 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 888 dma-names = "tx", "rx"; 889 status = "disabled"; 890 }; 891 892 spi17: spi@888000 { 893 compatible = "qcom,geni-spi"; 894 reg = <0x0 0x00888000 0x0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 897 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 901 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 902 interconnect-names = "qup-core", "qup-config"; 903 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 904 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 905 dma-names = "tx", "rx"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 status = "disabled"; 909 }; 910 911 i2c18: i2c@88c000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0x0 0x0088c000 0x0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c18_data_clk>; 918 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 922 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 923 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 924 interconnect-names = "qup-core", "qup-config", "qup-memory"; 925 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 926 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 927 dma-names = "tx", "rx"; 928 status = "disabled"; 929 }; 930 931 spi18: spi@88c000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0 0x0088c000 0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 936 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 937 pinctrl-names = "default"; 938 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 939 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 940 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 941 interconnect-names = "qup-core", "qup-config"; 942 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 943 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 944 dma-names = "tx", "rx"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 i2c19: i2c@890000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0x0 0x00890000 0x0 0x4000>; 953 clock-names = "se"; 954 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 955 pinctrl-names = "default"; 956 pinctrl-0 = <&qup_i2c19_data_clk>; 957 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 961 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 962 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 963 interconnect-names = "qup-core", "qup-config", "qup-memory"; 964 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 965 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 966 dma-names = "tx", "rx"; 967 status = "disabled"; 968 }; 969 970 spi19: spi@890000 { 971 compatible = "qcom,geni-spi"; 972 reg = <0 0x00890000 0 0x4000>; 973 clock-names = "se"; 974 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 975 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 978 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 979 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 980 interconnect-names = "qup-core", "qup-config"; 981 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 982 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 983 dma-names = "tx", "rx"; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 i2c20: i2c@894000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0x0 0x00894000 0x0 0x4000>; 992 clock-names = "se"; 993 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c20_data_clk>; 996 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1000 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1001 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1002 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1003 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1004 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1005 dma-names = "tx", "rx"; 1006 status = "disabled"; 1007 }; 1008 1009 uart20: serial@894000 { 1010 compatible = "qcom,geni-uart"; 1011 reg = <0 0x00894000 0 0x4000>; 1012 clock-names = "se"; 1013 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1014 pinctrl-names = "default"; 1015 pinctrl-0 = <&qup_uart20_default>; 1016 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1017 status = "disabled"; 1018 }; 1019 1020 spi20: spi@894000 { 1021 compatible = "qcom,geni-spi"; 1022 reg = <0 0x00894000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1025 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1029 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1030 interconnect-names = "qup-core", "qup-config"; 1031 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1032 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1033 dma-names = "tx", "rx"; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 status = "disabled"; 1037 }; 1038 1039 i2c21: i2c@898000 { 1040 compatible = "qcom,geni-i2c"; 1041 reg = <0x0 0x00898000 0x0 0x4000>; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&qup_i2c21_data_clk>; 1046 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1050 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1051 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1052 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1053 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1054 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1055 dma-names = "tx", "rx"; 1056 status = "disabled"; 1057 }; 1058 1059 spi21: spi@898000 { 1060 compatible = "qcom,geni-spi"; 1061 reg = <0 0x00898000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1064 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1069 interconnect-names = "qup-core", "qup-config"; 1070 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1071 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1072 dma-names = "tx", "rx"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 }; 1078 1079 gpi_dma0: dma-controller@900000 { 1080 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1081 #dma-cells = <3>; 1082 reg = <0 0x00900000 0 0x60000>; 1083 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1095 dma-channels = <12>; 1096 dma-channel-mask = <0x7e>; 1097 iommus = <&apps_smmu 0x5b6 0x0>; 1098 status = "disabled"; 1099 }; 1100 1101 qupv3_id_0: geniqup@9c0000 { 1102 compatible = "qcom,geni-se-qup"; 1103 reg = <0x0 0x009c0000 0x0 0x2000>; 1104 clock-names = "m-ahb", "s-ahb"; 1105 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1106 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1107 iommus = <&apps_smmu 0x5a3 0x0>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1109 interconnect-names = "qup-core"; 1110 #address-cells = <2>; 1111 #size-cells = <2>; 1112 ranges; 1113 status = "disabled"; 1114 1115 i2c0: i2c@980000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0x0 0x00980000 0x0 0x4000>; 1118 clock-names = "se"; 1119 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_i2c0_data_clk>; 1122 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1126 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1127 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1128 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1129 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 status = "disabled"; 1133 }; 1134 1135 spi0: spi@980000 { 1136 compatible = "qcom,geni-spi"; 1137 reg = <0x0 0x00980000 0x0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1140 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1143 power-domains = <&rpmhpd SM8450_CX>; 1144 operating-points-v2 = <&qup_opp_table_100mhz>; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1148 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1150 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1151 dma-names = "tx", "rx"; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c1: i2c@984000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0x0 0x00984000 0x0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c1_data_clk>; 1164 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1168 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1169 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1170 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1171 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1172 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1173 dma-names = "tx", "rx"; 1174 status = "disabled"; 1175 }; 1176 1177 spi1: spi@984000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0x0 0x00984000 0x0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1182 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1185 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1186 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1187 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1188 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1189 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1190 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1191 dma-names = "tx", "rx"; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 i2c2: i2c@988000 { 1198 compatible = "qcom,geni-i2c"; 1199 reg = <0x0 0x00988000 0x0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&qup_i2c2_data_clk>; 1204 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1208 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1209 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1210 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1211 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1212 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1213 dma-names = "tx", "rx"; 1214 status = "disabled"; 1215 }; 1216 1217 spi2: spi@988000 { 1218 compatible = "qcom,geni-spi"; 1219 reg = <0x0 0x00988000 0x0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1226 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1227 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1228 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1229 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1230 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1231 dma-names = "tx", "rx"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 1238 i2c3: i2c@98c000 { 1239 compatible = "qcom,geni-i2c"; 1240 reg = <0x0 0x0098c000 0x0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_i2c3_data_clk>; 1245 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1249 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1250 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1251 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1252 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1253 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1254 dma-names = "tx", "rx"; 1255 status = "disabled"; 1256 }; 1257 1258 spi3: spi@98c000 { 1259 compatible = "qcom,geni-spi"; 1260 reg = <0x0 0x0098c000 0x0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1263 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1267 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1268 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1269 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1270 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1271 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1272 dma-names = "tx", "rx"; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 status = "disabled"; 1276 }; 1277 1278 i2c4: i2c@990000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0x0 0x00990000 0x0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c4_data_clk>; 1285 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1290 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1292 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1293 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1294 dma-names = "tx", "rx"; 1295 status = "disabled"; 1296 }; 1297 1298 spi4: spi@990000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0x0 0x00990000 0x0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1303 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1306 power-domains = <&rpmhpd SM8450_CX>; 1307 operating-points-v2 = <&qup_opp_table_100mhz>; 1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1311 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1313 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1314 dma-names = "tx", "rx"; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 status = "disabled"; 1318 }; 1319 1320 i2c5: i2c@994000 { 1321 compatible = "qcom,geni-i2c"; 1322 reg = <0x0 0x00994000 0x0 0x4000>; 1323 clock-names = "se"; 1324 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&qup_i2c5_data_clk>; 1327 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1331 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1332 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1333 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1334 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1335 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1336 dma-names = "tx", "rx"; 1337 status = "disabled"; 1338 }; 1339 1340 spi5: spi@994000 { 1341 compatible = "qcom,geni-spi"; 1342 reg = <0x0 0x00994000 0x0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1345 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1349 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1350 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1351 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1352 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1353 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 1360 1361 i2c6: i2c@998000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0x0 0x00998000 0x0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_i2c6_data_clk>; 1368 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1372 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1373 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1374 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1375 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1376 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 status = "disabled"; 1379 }; 1380 1381 spi6: spi@998000 { 1382 compatible = "qcom,geni-spi"; 1383 reg = <0x0 0x00998000 0x0 0x4000>; 1384 clock-names = "se"; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1386 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1390 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1391 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1392 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1393 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1394 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1395 dma-names = "tx", "rx"; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 uart7: serial@99c000 { 1402 compatible = "qcom,geni-debug-uart"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 status = "disabled"; 1410 }; 1411 }; 1412 1413 gpi_dma1: dma-controller@a00000 { 1414 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1415 #dma-cells = <3>; 1416 reg = <0 0x00a00000 0 0x60000>; 1417 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1429 dma-channels = <12>; 1430 dma-channel-mask = <0x7e>; 1431 iommus = <&apps_smmu 0x56 0x0>; 1432 status = "disabled"; 1433 }; 1434 1435 qupv3_id_1: geniqup@ac0000 { 1436 compatible = "qcom,geni-se-qup"; 1437 reg = <0x0 0x00ac0000 0x0 0x6000>; 1438 clock-names = "m-ahb", "s-ahb"; 1439 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1440 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1441 iommus = <&apps_smmu 0x43 0x0>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1443 interconnect-names = "qup-core"; 1444 #address-cells = <2>; 1445 #size-cells = <2>; 1446 ranges; 1447 status = "disabled"; 1448 1449 i2c8: i2c@a80000 { 1450 compatible = "qcom,geni-i2c"; 1451 reg = <0x0 0x00a80000 0x0 0x4000>; 1452 clock-names = "se"; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&qup_i2c8_data_clk>; 1456 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1460 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1461 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1462 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1463 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1464 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1465 dma-names = "tx", "rx"; 1466 status = "disabled"; 1467 }; 1468 1469 spi8: spi@a80000 { 1470 compatible = "qcom,geni-spi"; 1471 reg = <0x0 0x00a80000 0x0 0x4000>; 1472 clock-names = "se"; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1474 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1477 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1478 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1479 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1480 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1481 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1482 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1483 dma-names = "tx", "rx"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 i2c9: i2c@a84000 { 1490 compatible = "qcom,geni-i2c"; 1491 reg = <0x0 0x00a84000 0x0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_i2c9_data_clk>; 1496 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1500 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1501 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1502 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1503 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1504 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1505 dma-names = "tx", "rx"; 1506 status = "disabled"; 1507 }; 1508 1509 spi9: spi@a84000 { 1510 compatible = "qcom,geni-spi"; 1511 reg = <0x0 0x00a84000 0x0 0x4000>; 1512 clock-names = "se"; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1518 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1521 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1522 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1523 dma-names = "tx", "rx"; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 status = "disabled"; 1527 }; 1528 1529 i2c10: i2c@a88000 { 1530 compatible = "qcom,geni-i2c"; 1531 reg = <0x0 0x00a88000 0x0 0x4000>; 1532 clock-names = "se"; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1534 pinctrl-names = "default"; 1535 pinctrl-0 = <&qup_i2c10_data_clk>; 1536 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1540 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1541 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1542 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1543 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1544 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1545 dma-names = "tx", "rx"; 1546 status = "disabled"; 1547 }; 1548 1549 spi10: spi@a88000 { 1550 compatible = "qcom,geni-spi"; 1551 reg = <0x0 0x00a88000 0x0 0x4000>; 1552 clock-names = "se"; 1553 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1554 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1557 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1558 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1559 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1560 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1561 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1562 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1563 dma-names = "tx", "rx"; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 status = "disabled"; 1567 }; 1568 1569 i2c11: i2c@a8c000 { 1570 compatible = "qcom,geni-i2c"; 1571 reg = <0x0 0x00a8c000 0x0 0x4000>; 1572 clock-names = "se"; 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_i2c11_data_clk>; 1576 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1580 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1581 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 status = "disabled"; 1587 }; 1588 1589 spi11: spi@a8c000 { 1590 compatible = "qcom,geni-spi"; 1591 reg = <0x0 0x00a8c000 0x0 0x4000>; 1592 clock-names = "se"; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1594 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1597 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1598 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1599 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1600 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1601 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1602 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1603 dma-names = "tx", "rx"; 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 status = "disabled"; 1607 }; 1608 1609 i2c12: i2c@a90000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0x0 0x00a90000 0x0 0x4000>; 1612 clock-names = "se"; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1614 pinctrl-names = "default"; 1615 pinctrl-0 = <&qup_i2c12_data_clk>; 1616 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1620 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1621 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1622 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1623 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1624 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1625 dma-names = "tx", "rx"; 1626 status = "disabled"; 1627 }; 1628 1629 spi12: spi@a90000 { 1630 compatible = "qcom,geni-spi"; 1631 reg = <0x0 0x00a90000 0x0 0x4000>; 1632 clock-names = "se"; 1633 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1634 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1639 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1641 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1642 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1643 dma-names = "tx", "rx"; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 status = "disabled"; 1647 }; 1648 1649 i2c13: i2c@a94000 { 1650 compatible = "qcom,geni-i2c"; 1651 reg = <0 0x00a94000 0 0x4000>; 1652 clock-names = "se"; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&qup_i2c13_data_clk>; 1656 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1658 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1659 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1660 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1661 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1662 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1663 dma-names = "tx", "rx"; 1664 #address-cells = <1>; 1665 #size-cells = <0>; 1666 status = "disabled"; 1667 }; 1668 1669 spi13: spi@a94000 { 1670 compatible = "qcom,geni-spi"; 1671 reg = <0x0 0x00a94000 0x0 0x4000>; 1672 clock-names = "se"; 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1674 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1675 pinctrl-names = "default"; 1676 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1677 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1678 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1679 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1680 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1681 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1682 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1683 dma-names = "tx", "rx"; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 status = "disabled"; 1687 }; 1688 1689 i2c14: i2c@a98000 { 1690 compatible = "qcom,geni-i2c"; 1691 reg = <0 0x00a98000 0 0x4000>; 1692 clock-names = "se"; 1693 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&qup_i2c14_data_clk>; 1696 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1699 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1701 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1702 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1703 dma-names = "tx", "rx"; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 }; 1708 1709 spi14: spi@a98000 { 1710 compatible = "qcom,geni-spi"; 1711 reg = <0x0 0x00a98000 0x0 0x4000>; 1712 clock-names = "se"; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1714 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1719 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1720 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1721 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1722 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1723 dma-names = "tx", "rx"; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 status = "disabled"; 1727 }; 1728 }; 1729 1730 pcie0: pci@1c00000 { 1731 compatible = "qcom,pcie-sm8450-pcie0"; 1732 reg = <0 0x01c00000 0 0x3000>, 1733 <0 0x60000000 0 0xf1d>, 1734 <0 0x60000f20 0 0xa8>, 1735 <0 0x60001000 0 0x1000>, 1736 <0 0x60100000 0 0x100000>; 1737 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1738 device_type = "pci"; 1739 linux,pci-domain = <0>; 1740 bus-range = <0x00 0xff>; 1741 num-lanes = <1>; 1742 1743 #address-cells = <3>; 1744 #size-cells = <2>; 1745 1746 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1747 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1748 1749 /* 1750 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1751 * Hence, the IDs are swapped. 1752 */ 1753 msi-map = <0x0 &gic_its 0x5981 0x1>, 1754 <0x100 &gic_its 0x5980 0x1>; 1755 msi-map-mask = <0xff00>; 1756 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1757 interrupt-names = "msi"; 1758 #interrupt-cells = <1>; 1759 interrupt-map-mask = <0 0 0 0x7>; 1760 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1761 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1762 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1763 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1764 1765 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1766 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1767 <&pcie0_lane>, 1768 <&rpmhcc RPMH_CXO_CLK>, 1769 <&gcc GCC_PCIE_0_AUX_CLK>, 1770 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1771 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1772 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1773 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1774 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1775 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1776 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1777 clock-names = "pipe", 1778 "pipe_mux", 1779 "phy_pipe", 1780 "ref", 1781 "aux", 1782 "cfg", 1783 "bus_master", 1784 "bus_slave", 1785 "slave_q2a", 1786 "ddrss_sf_tbu", 1787 "aggre0", 1788 "aggre1"; 1789 1790 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1791 <0x100 &apps_smmu 0x1c01 0x1>; 1792 1793 resets = <&gcc GCC_PCIE_0_BCR>; 1794 reset-names = "pci"; 1795 1796 power-domains = <&gcc PCIE_0_GDSC>; 1797 1798 phys = <&pcie0_lane>; 1799 phy-names = "pciephy"; 1800 1801 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1802 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1803 1804 pinctrl-names = "default"; 1805 pinctrl-0 = <&pcie0_default_state>; 1806 1807 status = "disabled"; 1808 }; 1809 1810 pcie0_phy: phy@1c06000 { 1811 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1812 reg = <0 0x01c06000 0 0x200>; 1813 #address-cells = <2>; 1814 #size-cells = <2>; 1815 ranges; 1816 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1817 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1818 <&gcc GCC_PCIE_0_CLKREF_EN>, 1819 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1820 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1821 1822 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1823 reset-names = "phy"; 1824 1825 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1826 assigned-clock-rates = <100000000>; 1827 1828 status = "disabled"; 1829 1830 pcie0_lane: phy@1c06200 { 1831 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1832 <0 0x01c07000 0 0x200>, /* rx */ 1833 <0 0x01c06200 0 0x200>, /* pcs */ 1834 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1835 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1836 clock-names = "pipe0"; 1837 1838 #clock-cells = <0>; 1839 #phy-cells = <0>; 1840 clock-output-names = "pcie_0_pipe_clk"; 1841 }; 1842 }; 1843 1844 pcie1: pci@1c08000 { 1845 compatible = "qcom,pcie-sm8450-pcie1"; 1846 reg = <0 0x01c08000 0 0x3000>, 1847 <0 0x40000000 0 0xf1d>, 1848 <0 0x40000f20 0 0xa8>, 1849 <0 0x40001000 0 0x1000>, 1850 <0 0x40100000 0 0x100000>; 1851 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1852 device_type = "pci"; 1853 linux,pci-domain = <1>; 1854 bus-range = <0x00 0xff>; 1855 num-lanes = <2>; 1856 1857 #address-cells = <3>; 1858 #size-cells = <2>; 1859 1860 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1861 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1862 1863 /* 1864 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1865 * Hence, the IDs are swapped. 1866 */ 1867 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1868 <0x100 &gic_its 0x5a00 0x1>; 1869 msi-map-mask = <0xff00>; 1870 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1871 interrupt-names = "msi"; 1872 #interrupt-cells = <1>; 1873 interrupt-map-mask = <0 0 0 0x7>; 1874 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1875 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1876 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1877 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1878 1879 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1880 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1881 <&pcie1_lane>, 1882 <&rpmhcc RPMH_CXO_CLK>, 1883 <&gcc GCC_PCIE_1_AUX_CLK>, 1884 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1885 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1886 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1887 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1888 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1889 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1890 clock-names = "pipe", 1891 "pipe_mux", 1892 "phy_pipe", 1893 "ref", 1894 "aux", 1895 "cfg", 1896 "bus_master", 1897 "bus_slave", 1898 "slave_q2a", 1899 "ddrss_sf_tbu", 1900 "aggre1"; 1901 1902 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1903 <0x100 &apps_smmu 0x1c81 0x1>; 1904 1905 resets = <&gcc GCC_PCIE_1_BCR>; 1906 reset-names = "pci"; 1907 1908 power-domains = <&gcc PCIE_1_GDSC>; 1909 1910 phys = <&pcie1_lane>; 1911 phy-names = "pciephy"; 1912 1913 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1914 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1915 1916 pinctrl-names = "default"; 1917 pinctrl-0 = <&pcie1_default_state>; 1918 1919 status = "disabled"; 1920 }; 1921 1922 pcie1_phy: phy@1c0f000 { 1923 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1924 reg = <0 0x01c0f000 0 0x200>; 1925 #address-cells = <2>; 1926 #size-cells = <2>; 1927 ranges; 1928 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1929 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1930 <&gcc GCC_PCIE_1_CLKREF_EN>, 1931 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1932 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1933 1934 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1935 reset-names = "phy"; 1936 1937 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1938 assigned-clock-rates = <100000000>; 1939 1940 status = "disabled"; 1941 1942 pcie1_lane: phy@1c0e000 { 1943 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1944 <0 0x01c0e200 0 0x300>, /* rx */ 1945 <0 0x01c0f200 0 0x200>, /* pcs */ 1946 <0 0x01c0e800 0 0x200>, /* tx */ 1947 <0 0x01c0ea00 0 0x300>, /* rx */ 1948 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1949 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1950 clock-names = "pipe0"; 1951 1952 #clock-cells = <0>; 1953 #phy-cells = <0>; 1954 clock-output-names = "pcie_1_pipe_clk"; 1955 }; 1956 }; 1957 1958 config_noc: interconnect@1500000 { 1959 compatible = "qcom,sm8450-config-noc"; 1960 reg = <0 0x01500000 0 0x1c000>; 1961 #interconnect-cells = <2>; 1962 qcom,bcm-voters = <&apps_bcm_voter>; 1963 }; 1964 1965 system_noc: interconnect@1680000 { 1966 compatible = "qcom,sm8450-system-noc"; 1967 reg = <0 0x01680000 0 0x1e200>; 1968 #interconnect-cells = <2>; 1969 qcom,bcm-voters = <&apps_bcm_voter>; 1970 }; 1971 1972 pcie_noc: interconnect@16c0000 { 1973 compatible = "qcom,sm8450-pcie-anoc"; 1974 reg = <0 0x016c0000 0 0xe280>; 1975 #interconnect-cells = <2>; 1976 qcom,bcm-voters = <&apps_bcm_voter>; 1977 }; 1978 1979 aggre1_noc: interconnect@16e0000 { 1980 compatible = "qcom,sm8450-aggre1-noc"; 1981 reg = <0 0x016e0000 0 0x1c080>; 1982 #interconnect-cells = <2>; 1983 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1984 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1985 qcom,bcm-voters = <&apps_bcm_voter>; 1986 }; 1987 1988 aggre2_noc: interconnect@1700000 { 1989 compatible = "qcom,sm8450-aggre2-noc"; 1990 reg = <0 0x01700000 0 0x31080>; 1991 #interconnect-cells = <2>; 1992 qcom,bcm-voters = <&apps_bcm_voter>; 1993 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1994 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1995 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1996 <&rpmhcc RPMH_IPA_CLK>; 1997 }; 1998 1999 mmss_noc: interconnect@1740000 { 2000 compatible = "qcom,sm8450-mmss-noc"; 2001 reg = <0 0x01740000 0 0x1f080>; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 }; 2005 2006 tcsr_mutex: hwlock@1f40000 { 2007 compatible = "qcom,tcsr-mutex"; 2008 reg = <0x0 0x01f40000 0x0 0x40000>; 2009 #hwlock-cells = <1>; 2010 }; 2011 2012 tcsr: syscon@1fc0000 { 2013 compatible = "qcom,sm8450-tcsr", "syscon"; 2014 reg = <0x0 0x1fc0000 0x0 0x30000>; 2015 }; 2016 2017 usb_1_hsphy: phy@88e3000 { 2018 compatible = "qcom,sm8450-usb-hs-phy", 2019 "qcom,usb-snps-hs-7nm-phy"; 2020 reg = <0 0x088e3000 0 0x400>; 2021 status = "disabled"; 2022 #phy-cells = <0>; 2023 2024 clocks = <&rpmhcc RPMH_CXO_CLK>; 2025 clock-names = "ref"; 2026 2027 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2028 }; 2029 2030 usb_1_qmpphy: phy@88e8000 { 2031 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2032 reg = <0 0x088e8000 0 0x3000>; 2033 2034 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2035 <&rpmhcc RPMH_CXO_CLK>, 2036 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2037 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2038 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2039 2040 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2041 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2042 reset-names = "phy", "common"; 2043 2044 #clock-cells = <1>; 2045 #phy-cells = <1>; 2046 2047 status = "disabled"; 2048 2049 ports { 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 2053 port@0 { 2054 reg = <0>; 2055 2056 usb_1_qmpphy_out: endpoint { 2057 }; 2058 }; 2059 2060 port@1 { 2061 reg = <1>; 2062 2063 usb_1_qmpphy_usb_ss_in: endpoint { 2064 }; 2065 }; 2066 2067 port@2 { 2068 reg = <2>; 2069 2070 usb_1_qmpphy_dp_in: endpoint { 2071 }; 2072 }; 2073 }; 2074 }; 2075 2076 remoteproc_slpi: remoteproc@2400000 { 2077 compatible = "qcom,sm8450-slpi-pas"; 2078 reg = <0 0x02400000 0 0x4000>; 2079 2080 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2081 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2082 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2083 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2084 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2085 interrupt-names = "wdog", "fatal", "ready", 2086 "handover", "stop-ack"; 2087 2088 clocks = <&rpmhcc RPMH_CXO_CLK>; 2089 clock-names = "xo"; 2090 2091 power-domains = <&rpmhpd SM8450_LCX>, 2092 <&rpmhpd SM8450_LMX>; 2093 power-domain-names = "lcx", "lmx"; 2094 2095 memory-region = <&slpi_mem>; 2096 2097 qcom,qmp = <&aoss_qmp>; 2098 2099 qcom,smem-states = <&smp2p_slpi_out 0>; 2100 qcom,smem-state-names = "stop"; 2101 2102 status = "disabled"; 2103 2104 glink-edge { 2105 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2106 IPCC_MPROC_SIGNAL_GLINK_QMP 2107 IRQ_TYPE_EDGE_RISING>; 2108 mboxes = <&ipcc IPCC_CLIENT_SLPI 2109 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2110 2111 label = "slpi"; 2112 qcom,remote-pid = <3>; 2113 2114 fastrpc { 2115 compatible = "qcom,fastrpc"; 2116 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2117 label = "sdsp"; 2118 #address-cells = <1>; 2119 #size-cells = <0>; 2120 2121 compute-cb@1 { 2122 compatible = "qcom,fastrpc-compute-cb"; 2123 reg = <1>; 2124 iommus = <&apps_smmu 0x0541 0x0>; 2125 }; 2126 2127 compute-cb@2 { 2128 compatible = "qcom,fastrpc-compute-cb"; 2129 reg = <2>; 2130 iommus = <&apps_smmu 0x0542 0x0>; 2131 }; 2132 2133 compute-cb@3 { 2134 compatible = "qcom,fastrpc-compute-cb"; 2135 reg = <3>; 2136 iommus = <&apps_smmu 0x0543 0x0>; 2137 /* note: shared-cb = <4> in downstream */ 2138 }; 2139 }; 2140 }; 2141 }; 2142 2143 wsa2macro: codec@31e0000 { 2144 compatible = "qcom,sm8450-lpass-wsa-macro"; 2145 reg = <0 0x031e0000 0 0x1000>; 2146 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2147 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2148 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2149 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2150 <&vamacro>; 2151 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2152 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2153 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2154 assigned-clock-rates = <19200000>, <19200000>; 2155 2156 #clock-cells = <0>; 2157 clock-output-names = "wsa2-mclk"; 2158 pinctrl-names = "default"; 2159 pinctrl-0 = <&wsa2_swr_active>; 2160 #sound-dai-cells = <1>; 2161 }; 2162 2163 swr4: soundwire-controller@31f0000 { 2164 compatible = "qcom,soundwire-v1.7.0"; 2165 reg = <0 0x031f0000 0 0x2000>; 2166 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2167 clocks = <&wsa2macro>; 2168 clock-names = "iface"; 2169 label = "WSA2"; 2170 2171 qcom,din-ports = <2>; 2172 qcom,dout-ports = <6>; 2173 2174 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2175 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2176 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2177 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2178 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2179 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2180 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2181 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2182 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2183 2184 #address-cells = <2>; 2185 #size-cells = <0>; 2186 #sound-dai-cells = <1>; 2187 status = "disabled"; 2188 }; 2189 2190 rxmacro: codec@3200000 { 2191 compatible = "qcom,sm8450-lpass-rx-macro"; 2192 reg = <0 0x03200000 0 0x1000>; 2193 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2194 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2195 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2196 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2197 <&vamacro>; 2198 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2199 2200 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2201 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2202 assigned-clock-rates = <19200000>, <19200000>; 2203 2204 #clock-cells = <0>; 2205 clock-output-names = "mclk"; 2206 pinctrl-names = "default"; 2207 pinctrl-0 = <&rx_swr_active>; 2208 #sound-dai-cells = <1>; 2209 }; 2210 2211 swr1: soundwire-controller@3210000 { 2212 compatible = "qcom,soundwire-v1.7.0"; 2213 reg = <0 0x03210000 0 0x2000>; 2214 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2215 clocks = <&rxmacro>; 2216 clock-names = "iface"; 2217 label = "RX"; 2218 qcom,din-ports = <0>; 2219 qcom,dout-ports = <5>; 2220 2221 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2222 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2223 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2224 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2225 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2226 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2227 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2228 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2229 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2230 2231 #address-cells = <2>; 2232 #size-cells = <0>; 2233 #sound-dai-cells = <1>; 2234 status = "disabled"; 2235 }; 2236 2237 txmacro: codec@3220000 { 2238 compatible = "qcom,sm8450-lpass-tx-macro"; 2239 reg = <0 0x03220000 0 0x1000>; 2240 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2241 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2242 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2243 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2244 <&vamacro>; 2245 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2246 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2247 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2248 assigned-clock-rates = <19200000>, <19200000>; 2249 2250 #clock-cells = <0>; 2251 clock-output-names = "mclk"; 2252 pinctrl-names = "default"; 2253 pinctrl-0 = <&tx_swr_active>; 2254 #sound-dai-cells = <1>; 2255 }; 2256 2257 wsamacro: codec@3240000 { 2258 compatible = "qcom,sm8450-lpass-wsa-macro"; 2259 reg = <0 0x03240000 0 0x1000>; 2260 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2263 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2264 <&vamacro>; 2265 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2266 2267 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2268 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2269 assigned-clock-rates = <19200000>, <19200000>; 2270 2271 #clock-cells = <0>; 2272 clock-output-names = "mclk"; 2273 pinctrl-names = "default"; 2274 pinctrl-0 = <&wsa_swr_active>; 2275 #sound-dai-cells = <1>; 2276 }; 2277 2278 swr0: soundwire-controller@3250000 { 2279 compatible = "qcom,soundwire-v1.7.0"; 2280 reg = <0 0x03250000 0 0x2000>; 2281 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&wsamacro>; 2283 clock-names = "iface"; 2284 label = "WSA"; 2285 2286 qcom,din-ports = <2>; 2287 qcom,dout-ports = <6>; 2288 2289 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2290 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2291 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2292 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2293 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2294 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2295 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2296 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2297 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2298 2299 #address-cells = <2>; 2300 #size-cells = <0>; 2301 #sound-dai-cells = <1>; 2302 status = "disabled"; 2303 }; 2304 2305 swr2: soundwire-controller@33b0000 { 2306 compatible = "qcom,soundwire-v1.7.0"; 2307 reg = <0 0x033b0000 0 0x2000>; 2308 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2310 interrupt-names = "core", "wakeup"; 2311 2312 clocks = <&vamacro>; 2313 clock-names = "iface"; 2314 label = "TX"; 2315 2316 qcom,din-ports = <4>; 2317 qcom,dout-ports = <0>; 2318 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2319 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2320 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2321 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2322 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2323 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2324 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2325 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2326 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2327 2328 #address-cells = <2>; 2329 #size-cells = <0>; 2330 #sound-dai-cells = <1>; 2331 status = "disabled"; 2332 }; 2333 2334 vamacro: codec@33f0000 { 2335 compatible = "qcom,sm8450-lpass-va-macro"; 2336 reg = <0 0x033f0000 0 0x1000>; 2337 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2338 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2339 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2340 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2341 clock-names = "mclk", "macro", "dcodec", "npl"; 2342 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2343 assigned-clock-rates = <19200000>; 2344 2345 #clock-cells = <0>; 2346 clock-output-names = "fsgen"; 2347 #sound-dai-cells = <1>; 2348 status = "disabled"; 2349 }; 2350 2351 remoteproc_adsp: remoteproc@30000000 { 2352 compatible = "qcom,sm8450-adsp-pas"; 2353 reg = <0 0x30000000 0 0x100>; 2354 2355 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2356 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2357 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2358 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2359 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2360 interrupt-names = "wdog", "fatal", "ready", 2361 "handover", "stop-ack"; 2362 2363 clocks = <&rpmhcc RPMH_CXO_CLK>; 2364 clock-names = "xo"; 2365 2366 power-domains = <&rpmhpd SM8450_LCX>, 2367 <&rpmhpd SM8450_LMX>; 2368 power-domain-names = "lcx", "lmx"; 2369 2370 memory-region = <&adsp_mem>; 2371 2372 qcom,qmp = <&aoss_qmp>; 2373 2374 qcom,smem-states = <&smp2p_adsp_out 0>; 2375 qcom,smem-state-names = "stop"; 2376 2377 status = "disabled"; 2378 2379 remoteproc_adsp_glink: glink-edge { 2380 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2381 IPCC_MPROC_SIGNAL_GLINK_QMP 2382 IRQ_TYPE_EDGE_RISING>; 2383 mboxes = <&ipcc IPCC_CLIENT_LPASS 2384 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2385 2386 label = "lpass"; 2387 qcom,remote-pid = <2>; 2388 2389 gpr { 2390 compatible = "qcom,gpr"; 2391 qcom,glink-channels = "adsp_apps"; 2392 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2393 qcom,intents = <512 20>; 2394 #address-cells = <1>; 2395 #size-cells = <0>; 2396 2397 q6apm: service@1 { 2398 compatible = "qcom,q6apm"; 2399 reg = <GPR_APM_MODULE_IID>; 2400 #sound-dai-cells = <0>; 2401 qcom,protection-domain = "avs/audio", 2402 "msm/adsp/audio_pd"; 2403 2404 q6apmdai: dais { 2405 compatible = "qcom,q6apm-dais"; 2406 iommus = <&apps_smmu 0x1801 0x0>; 2407 }; 2408 2409 q6apmbedai: bedais { 2410 compatible = "qcom,q6apm-lpass-dais"; 2411 #sound-dai-cells = <1>; 2412 }; 2413 }; 2414 2415 q6prm: service@2 { 2416 compatible = "qcom,q6prm"; 2417 reg = <GPR_PRM_MODULE_IID>; 2418 qcom,protection-domain = "avs/audio", 2419 "msm/adsp/audio_pd"; 2420 2421 q6prmcc: clock-controller { 2422 compatible = "qcom,q6prm-lpass-clocks"; 2423 #clock-cells = <2>; 2424 }; 2425 }; 2426 }; 2427 2428 fastrpc { 2429 compatible = "qcom,fastrpc"; 2430 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2431 label = "adsp"; 2432 #address-cells = <1>; 2433 #size-cells = <0>; 2434 2435 compute-cb@3 { 2436 compatible = "qcom,fastrpc-compute-cb"; 2437 reg = <3>; 2438 iommus = <&apps_smmu 0x1803 0x0>; 2439 }; 2440 2441 compute-cb@4 { 2442 compatible = "qcom,fastrpc-compute-cb"; 2443 reg = <4>; 2444 iommus = <&apps_smmu 0x1804 0x0>; 2445 }; 2446 2447 compute-cb@5 { 2448 compatible = "qcom,fastrpc-compute-cb"; 2449 reg = <5>; 2450 iommus = <&apps_smmu 0x1805 0x0>; 2451 }; 2452 }; 2453 }; 2454 }; 2455 2456 remoteproc_cdsp: remoteproc@32300000 { 2457 compatible = "qcom,sm8450-cdsp-pas"; 2458 reg = <0 0x32300000 0 0x1400000>; 2459 2460 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2461 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2462 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2463 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2464 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2465 interrupt-names = "wdog", "fatal", "ready", 2466 "handover", "stop-ack"; 2467 2468 clocks = <&rpmhcc RPMH_CXO_CLK>; 2469 clock-names = "xo"; 2470 2471 power-domains = <&rpmhpd SM8450_CX>, 2472 <&rpmhpd SM8450_MXC>; 2473 power-domain-names = "cx", "mxc"; 2474 2475 memory-region = <&cdsp_mem>; 2476 2477 qcom,qmp = <&aoss_qmp>; 2478 2479 qcom,smem-states = <&smp2p_cdsp_out 0>; 2480 qcom,smem-state-names = "stop"; 2481 2482 status = "disabled"; 2483 2484 glink-edge { 2485 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2486 IPCC_MPROC_SIGNAL_GLINK_QMP 2487 IRQ_TYPE_EDGE_RISING>; 2488 mboxes = <&ipcc IPCC_CLIENT_CDSP 2489 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2490 2491 label = "cdsp"; 2492 qcom,remote-pid = <5>; 2493 2494 fastrpc { 2495 compatible = "qcom,fastrpc"; 2496 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2497 label = "cdsp"; 2498 #address-cells = <1>; 2499 #size-cells = <0>; 2500 2501 compute-cb@1 { 2502 compatible = "qcom,fastrpc-compute-cb"; 2503 reg = <1>; 2504 iommus = <&apps_smmu 0x2161 0x0400>, 2505 <&apps_smmu 0x1021 0x1420>; 2506 }; 2507 2508 compute-cb@2 { 2509 compatible = "qcom,fastrpc-compute-cb"; 2510 reg = <2>; 2511 iommus = <&apps_smmu 0x2162 0x0400>, 2512 <&apps_smmu 0x1022 0x1420>; 2513 }; 2514 2515 compute-cb@3 { 2516 compatible = "qcom,fastrpc-compute-cb"; 2517 reg = <3>; 2518 iommus = <&apps_smmu 0x2163 0x0400>, 2519 <&apps_smmu 0x1023 0x1420>; 2520 }; 2521 2522 compute-cb@4 { 2523 compatible = "qcom,fastrpc-compute-cb"; 2524 reg = <4>; 2525 iommus = <&apps_smmu 0x2164 0x0400>, 2526 <&apps_smmu 0x1024 0x1420>; 2527 }; 2528 2529 compute-cb@5 { 2530 compatible = "qcom,fastrpc-compute-cb"; 2531 reg = <5>; 2532 iommus = <&apps_smmu 0x2165 0x0400>, 2533 <&apps_smmu 0x1025 0x1420>; 2534 }; 2535 2536 compute-cb@6 { 2537 compatible = "qcom,fastrpc-compute-cb"; 2538 reg = <6>; 2539 iommus = <&apps_smmu 0x2166 0x0400>, 2540 <&apps_smmu 0x1026 0x1420>; 2541 }; 2542 2543 compute-cb@7 { 2544 compatible = "qcom,fastrpc-compute-cb"; 2545 reg = <7>; 2546 iommus = <&apps_smmu 0x2167 0x0400>, 2547 <&apps_smmu 0x1027 0x1420>; 2548 }; 2549 2550 compute-cb@8 { 2551 compatible = "qcom,fastrpc-compute-cb"; 2552 reg = <8>; 2553 iommus = <&apps_smmu 0x2168 0x0400>, 2554 <&apps_smmu 0x1028 0x1420>; 2555 }; 2556 2557 /* note: secure cb9 in downstream */ 2558 }; 2559 }; 2560 }; 2561 2562 remoteproc_mpss: remoteproc@4080000 { 2563 compatible = "qcom,sm8450-mpss-pas"; 2564 reg = <0x0 0x04080000 0x0 0x4040>; 2565 2566 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2567 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2568 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2569 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2570 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2571 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2572 interrupt-names = "wdog", "fatal", "ready", "handover", 2573 "stop-ack", "shutdown-ack"; 2574 2575 clocks = <&rpmhcc RPMH_CXO_CLK>; 2576 clock-names = "xo"; 2577 2578 power-domains = <&rpmhpd SM8450_CX>, 2579 <&rpmhpd SM8450_MSS>; 2580 power-domain-names = "cx", "mss"; 2581 2582 memory-region = <&mpss_mem>; 2583 2584 qcom,qmp = <&aoss_qmp>; 2585 2586 qcom,smem-states = <&smp2p_modem_out 0>; 2587 qcom,smem-state-names = "stop"; 2588 2589 status = "disabled"; 2590 2591 glink-edge { 2592 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2593 IPCC_MPROC_SIGNAL_GLINK_QMP 2594 IRQ_TYPE_EDGE_RISING>; 2595 mboxes = <&ipcc IPCC_CLIENT_MPSS 2596 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2597 label = "modem"; 2598 qcom,remote-pid = <1>; 2599 }; 2600 }; 2601 2602 videocc: clock-controller@aaf0000 { 2603 compatible = "qcom,sm8450-videocc"; 2604 reg = <0 0x0aaf0000 0 0x10000>; 2605 clocks = <&rpmhcc RPMH_CXO_CLK>, 2606 <&gcc GCC_VIDEO_AHB_CLK>; 2607 power-domains = <&rpmhpd SM8450_MMCX>; 2608 required-opps = <&rpmhpd_opp_low_svs>; 2609 #clock-cells = <1>; 2610 #reset-cells = <1>; 2611 #power-domain-cells = <1>; 2612 }; 2613 2614 cci0: cci@ac15000 { 2615 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2616 reg = <0 0x0ac15000 0 0x1000>; 2617 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2618 power-domains = <&camcc TITAN_TOP_GDSC>; 2619 2620 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2621 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2622 <&camcc CAM_CC_CPAS_AHB_CLK>, 2623 <&camcc CAM_CC_CCI_0_CLK>, 2624 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2625 clock-names = "camnoc_axi", 2626 "slow_ahb_src", 2627 "cpas_ahb", 2628 "cci", 2629 "cci_src"; 2630 pinctrl-0 = <&cci0_default &cci1_default>; 2631 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2632 pinctrl-names = "default", "sleep"; 2633 2634 status = "disabled"; 2635 #address-cells = <1>; 2636 #size-cells = <0>; 2637 2638 cci0_i2c0: i2c-bus@0 { 2639 reg = <0>; 2640 clock-frequency = <1000000>; 2641 #address-cells = <1>; 2642 #size-cells = <0>; 2643 }; 2644 2645 cci0_i2c1: i2c-bus@1 { 2646 reg = <1>; 2647 clock-frequency = <1000000>; 2648 #address-cells = <1>; 2649 #size-cells = <0>; 2650 }; 2651 }; 2652 2653 cci1: cci@ac16000 { 2654 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2655 reg = <0 0x0ac16000 0 0x1000>; 2656 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2657 power-domains = <&camcc TITAN_TOP_GDSC>; 2658 2659 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2660 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2661 <&camcc CAM_CC_CPAS_AHB_CLK>, 2662 <&camcc CAM_CC_CCI_1_CLK>, 2663 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2664 clock-names = "camnoc_axi", 2665 "slow_ahb_src", 2666 "cpas_ahb", 2667 "cci", 2668 "cci_src"; 2669 pinctrl-0 = <&cci2_default &cci3_default>; 2670 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2671 pinctrl-names = "default", "sleep"; 2672 2673 status = "disabled"; 2674 #address-cells = <1>; 2675 #size-cells = <0>; 2676 2677 cci1_i2c0: i2c-bus@0 { 2678 reg = <0>; 2679 clock-frequency = <1000000>; 2680 #address-cells = <1>; 2681 #size-cells = <0>; 2682 }; 2683 2684 cci1_i2c1: i2c-bus@1 { 2685 reg = <1>; 2686 clock-frequency = <1000000>; 2687 #address-cells = <1>; 2688 #size-cells = <0>; 2689 }; 2690 }; 2691 2692 camcc: clock-controller@ade0000 { 2693 compatible = "qcom,sm8450-camcc"; 2694 reg = <0 0x0ade0000 0 0x20000>; 2695 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2696 <&rpmhcc RPMH_CXO_CLK>, 2697 <&rpmhcc RPMH_CXO_CLK_A>, 2698 <&sleep_clk>; 2699 power-domains = <&rpmhpd SM8450_MMCX>; 2700 required-opps = <&rpmhpd_opp_low_svs>; 2701 #clock-cells = <1>; 2702 #reset-cells = <1>; 2703 #power-domain-cells = <1>; 2704 status = "disabled"; 2705 }; 2706 2707 mdss: display-subsystem@ae00000 { 2708 compatible = "qcom,sm8450-mdss"; 2709 reg = <0 0x0ae00000 0 0x1000>; 2710 reg-names = "mdss"; 2711 2712 /* same path used twice */ 2713 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2714 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; 2715 interconnect-names = "mdp0-mem", "mdp1-mem"; 2716 2717 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2718 2719 power-domains = <&dispcc MDSS_GDSC>; 2720 2721 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2722 <&gcc GCC_DISP_HF_AXI_CLK>, 2723 <&gcc GCC_DISP_SF_AXI_CLK>, 2724 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2725 2726 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2727 interrupt-controller; 2728 #interrupt-cells = <1>; 2729 2730 iommus = <&apps_smmu 0x2800 0x402>; 2731 2732 #address-cells = <2>; 2733 #size-cells = <2>; 2734 ranges; 2735 2736 status = "disabled"; 2737 2738 mdss_mdp: display-controller@ae01000 { 2739 compatible = "qcom,sm8450-dpu"; 2740 reg = <0 0x0ae01000 0 0x8f000>, 2741 <0 0x0aeb0000 0 0x2008>; 2742 reg-names = "mdp", "vbif"; 2743 2744 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2745 <&gcc GCC_DISP_SF_AXI_CLK>, 2746 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2747 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2748 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2749 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2750 clock-names = "bus", 2751 "nrt_bus", 2752 "iface", 2753 "lut", 2754 "core", 2755 "vsync"; 2756 2757 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2758 assigned-clock-rates = <19200000>; 2759 2760 operating-points-v2 = <&mdp_opp_table>; 2761 power-domains = <&rpmhpd SM8450_MMCX>; 2762 2763 interrupt-parent = <&mdss>; 2764 interrupts = <0>; 2765 2766 ports { 2767 #address-cells = <1>; 2768 #size-cells = <0>; 2769 2770 port@0 { 2771 reg = <0>; 2772 dpu_intf1_out: endpoint { 2773 remote-endpoint = <&mdss_dsi0_in>; 2774 }; 2775 }; 2776 2777 port@1 { 2778 reg = <1>; 2779 dpu_intf2_out: endpoint { 2780 remote-endpoint = <&mdss_dsi1_in>; 2781 }; 2782 }; 2783 2784 port@2 { 2785 reg = <2>; 2786 dpu_intf0_out: endpoint { 2787 remote-endpoint = <&mdss_dp0_in>; 2788 }; 2789 }; 2790 }; 2791 2792 mdp_opp_table: opp-table { 2793 compatible = "operating-points-v2"; 2794 2795 opp-172000000 { 2796 opp-hz = /bits/ 64 <172000000>; 2797 required-opps = <&rpmhpd_opp_low_svs_d1>; 2798 }; 2799 2800 opp-200000000 { 2801 opp-hz = /bits/ 64 <200000000>; 2802 required-opps = <&rpmhpd_opp_low_svs>; 2803 }; 2804 2805 opp-325000000 { 2806 opp-hz = /bits/ 64 <325000000>; 2807 required-opps = <&rpmhpd_opp_svs>; 2808 }; 2809 2810 opp-375000000 { 2811 opp-hz = /bits/ 64 <375000000>; 2812 required-opps = <&rpmhpd_opp_svs_l1>; 2813 }; 2814 2815 opp-500000000 { 2816 opp-hz = /bits/ 64 <500000000>; 2817 required-opps = <&rpmhpd_opp_nom>; 2818 }; 2819 }; 2820 }; 2821 2822 mdss_dp0: displayport-controller@ae90000 { 2823 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2824 reg = <0 0xae90000 0 0x200>, 2825 <0 0xae90200 0 0x200>, 2826 <0 0xae90400 0 0xc00>, 2827 <0 0xae91000 0 0x400>, 2828 <0 0xae91400 0 0x400>; 2829 interrupt-parent = <&mdss>; 2830 interrupts = <12>; 2831 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2832 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2833 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2834 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2835 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2836 clock-names = "core_iface", 2837 "core_aux", 2838 "ctrl_link", 2839 "ctrl_link_iface", 2840 "stream_pixel"; 2841 2842 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2843 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2844 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2845 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2846 2847 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2848 phy-names = "dp"; 2849 2850 #sound-dai-cells = <0>; 2851 2852 operating-points-v2 = <&dp_opp_table>; 2853 power-domains = <&rpmhpd SM8450_MMCX>; 2854 2855 status = "disabled"; 2856 2857 ports { 2858 #address-cells = <1>; 2859 #size-cells = <0>; 2860 2861 port@0 { 2862 reg = <0>; 2863 mdss_dp0_in: endpoint { 2864 remote-endpoint = <&dpu_intf0_out>; 2865 }; 2866 }; 2867 }; 2868 2869 dp_opp_table: opp-table { 2870 compatible = "operating-points-v2"; 2871 2872 opp-160000000 { 2873 opp-hz = /bits/ 64 <160000000>; 2874 required-opps = <&rpmhpd_opp_low_svs>; 2875 }; 2876 2877 opp-270000000 { 2878 opp-hz = /bits/ 64 <270000000>; 2879 required-opps = <&rpmhpd_opp_svs>; 2880 }; 2881 2882 opp-540000000 { 2883 opp-hz = /bits/ 64 <540000000>; 2884 required-opps = <&rpmhpd_opp_svs_l1>; 2885 }; 2886 2887 opp-810000000 { 2888 opp-hz = /bits/ 64 <810000000>; 2889 required-opps = <&rpmhpd_opp_nom>; 2890 }; 2891 }; 2892 }; 2893 2894 mdss_dsi0: dsi@ae94000 { 2895 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2896 reg = <0 0x0ae94000 0 0x400>; 2897 reg-names = "dsi_ctrl"; 2898 2899 interrupt-parent = <&mdss>; 2900 interrupts = <4>; 2901 2902 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2903 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2904 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2905 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2906 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2907 <&gcc GCC_DISP_HF_AXI_CLK>; 2908 clock-names = "byte", 2909 "byte_intf", 2910 "pixel", 2911 "core", 2912 "iface", 2913 "bus"; 2914 2915 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2916 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2917 2918 operating-points-v2 = <&mdss_dsi_opp_table>; 2919 power-domains = <&rpmhpd SM8450_MMCX>; 2920 2921 phys = <&mdss_dsi0_phy>; 2922 phy-names = "dsi"; 2923 2924 #address-cells = <1>; 2925 #size-cells = <0>; 2926 2927 status = "disabled"; 2928 2929 ports { 2930 #address-cells = <1>; 2931 #size-cells = <0>; 2932 2933 port@0 { 2934 reg = <0>; 2935 mdss_dsi0_in: endpoint { 2936 remote-endpoint = <&dpu_intf1_out>; 2937 }; 2938 }; 2939 2940 port@1 { 2941 reg = <1>; 2942 mdss_dsi0_out: endpoint { 2943 }; 2944 }; 2945 }; 2946 2947 mdss_dsi_opp_table: opp-table { 2948 compatible = "operating-points-v2"; 2949 2950 opp-187500000 { 2951 opp-hz = /bits/ 64 <187500000>; 2952 required-opps = <&rpmhpd_opp_low_svs>; 2953 }; 2954 2955 opp-300000000 { 2956 opp-hz = /bits/ 64 <300000000>; 2957 required-opps = <&rpmhpd_opp_svs>; 2958 }; 2959 2960 opp-358000000 { 2961 opp-hz = /bits/ 64 <358000000>; 2962 required-opps = <&rpmhpd_opp_svs_l1>; 2963 }; 2964 }; 2965 }; 2966 2967 mdss_dsi0_phy: phy@ae94400 { 2968 compatible = "qcom,sm8450-dsi-phy-5nm"; 2969 reg = <0 0x0ae94400 0 0x200>, 2970 <0 0x0ae94600 0 0x280>, 2971 <0 0x0ae94900 0 0x260>; 2972 reg-names = "dsi_phy", 2973 "dsi_phy_lane", 2974 "dsi_pll"; 2975 2976 #clock-cells = <1>; 2977 #phy-cells = <0>; 2978 2979 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2980 <&rpmhcc RPMH_CXO_CLK>; 2981 clock-names = "iface", "ref"; 2982 2983 status = "disabled"; 2984 }; 2985 2986 mdss_dsi1: dsi@ae96000 { 2987 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2988 reg = <0 0x0ae96000 0 0x400>; 2989 reg-names = "dsi_ctrl"; 2990 2991 interrupt-parent = <&mdss>; 2992 interrupts = <5>; 2993 2994 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2995 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2996 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2997 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2998 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2999 <&gcc GCC_DISP_HF_AXI_CLK>; 3000 clock-names = "byte", 3001 "byte_intf", 3002 "pixel", 3003 "core", 3004 "iface", 3005 "bus"; 3006 3007 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3008 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3009 3010 operating-points-v2 = <&mdss_dsi_opp_table>; 3011 power-domains = <&rpmhpd SM8450_MMCX>; 3012 3013 phys = <&mdss_dsi1_phy>; 3014 phy-names = "dsi"; 3015 3016 #address-cells = <1>; 3017 #size-cells = <0>; 3018 3019 status = "disabled"; 3020 3021 ports { 3022 #address-cells = <1>; 3023 #size-cells = <0>; 3024 3025 port@0 { 3026 reg = <0>; 3027 mdss_dsi1_in: endpoint { 3028 remote-endpoint = <&dpu_intf2_out>; 3029 }; 3030 }; 3031 3032 port@1 { 3033 reg = <1>; 3034 mdss_dsi1_out: endpoint { 3035 }; 3036 }; 3037 }; 3038 }; 3039 3040 mdss_dsi1_phy: phy@ae96400 { 3041 compatible = "qcom,sm8450-dsi-phy-5nm"; 3042 reg = <0 0x0ae96400 0 0x200>, 3043 <0 0x0ae96600 0 0x280>, 3044 <0 0x0ae96900 0 0x260>; 3045 reg-names = "dsi_phy", 3046 "dsi_phy_lane", 3047 "dsi_pll"; 3048 3049 #clock-cells = <1>; 3050 #phy-cells = <0>; 3051 3052 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3053 <&rpmhcc RPMH_CXO_CLK>; 3054 clock-names = "iface", "ref"; 3055 3056 status = "disabled"; 3057 }; 3058 }; 3059 3060 dispcc: clock-controller@af00000 { 3061 compatible = "qcom,sm8450-dispcc"; 3062 reg = <0 0x0af00000 0 0x20000>; 3063 clocks = <&rpmhcc RPMH_CXO_CLK>, 3064 <&rpmhcc RPMH_CXO_CLK_A>, 3065 <&gcc GCC_DISP_AHB_CLK>, 3066 <&sleep_clk>, 3067 <&mdss_dsi0_phy 0>, 3068 <&mdss_dsi0_phy 1>, 3069 <&mdss_dsi1_phy 0>, 3070 <&mdss_dsi1_phy 1>, 3071 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3072 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3073 <0>, /* dp1 */ 3074 <0>, 3075 <0>, /* dp2 */ 3076 <0>, 3077 <0>, /* dp3 */ 3078 <0>; 3079 power-domains = <&rpmhpd SM8450_MMCX>; 3080 required-opps = <&rpmhpd_opp_low_svs>; 3081 #clock-cells = <1>; 3082 #reset-cells = <1>; 3083 #power-domain-cells = <1>; 3084 status = "disabled"; 3085 }; 3086 3087 pdc: interrupt-controller@b220000 { 3088 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3089 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3090 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3091 <94 609 31>, <125 63 1>, <126 716 12>; 3092 #interrupt-cells = <2>; 3093 interrupt-parent = <&intc>; 3094 interrupt-controller; 3095 }; 3096 3097 tsens0: thermal-sensor@c263000 { 3098 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3099 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3100 <0 0x0c222000 0 0x1000>; /* SROT */ 3101 #qcom,sensors = <16>; 3102 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3104 interrupt-names = "uplow", "critical"; 3105 #thermal-sensor-cells = <1>; 3106 }; 3107 3108 tsens1: thermal-sensor@c265000 { 3109 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3110 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3111 <0 0x0c223000 0 0x1000>; /* SROT */ 3112 #qcom,sensors = <16>; 3113 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3115 interrupt-names = "uplow", "critical"; 3116 #thermal-sensor-cells = <1>; 3117 }; 3118 3119 aoss_qmp: power-management@c300000 { 3120 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3121 reg = <0 0x0c300000 0 0x400>; 3122 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3123 IRQ_TYPE_EDGE_RISING>; 3124 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3125 3126 #clock-cells = <0>; 3127 }; 3128 3129 spmi_bus: spmi@c400000 { 3130 compatible = "qcom,spmi-pmic-arb"; 3131 reg = <0 0x0c400000 0 0x00003000>, 3132 <0 0x0c500000 0 0x00400000>, 3133 <0 0x0c440000 0 0x00080000>, 3134 <0 0x0c4c0000 0 0x00010000>, 3135 <0 0x0c42d000 0 0x00010000>; 3136 reg-names = "core", 3137 "chnls", 3138 "obsrvr", 3139 "intr", 3140 "cnfg"; 3141 interrupt-names = "periph_irq"; 3142 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3143 qcom,ee = <0>; 3144 qcom,channel = <0>; 3145 interrupt-controller; 3146 #interrupt-cells = <4>; 3147 #address-cells = <2>; 3148 #size-cells = <0>; 3149 }; 3150 3151 ipcc: mailbox@ed18000 { 3152 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3153 reg = <0 0x0ed18000 0 0x1000>; 3154 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3155 interrupt-controller; 3156 #interrupt-cells = <3>; 3157 #mbox-cells = <2>; 3158 }; 3159 3160 tlmm: pinctrl@f100000 { 3161 compatible = "qcom,sm8450-tlmm"; 3162 reg = <0 0x0f100000 0 0x300000>; 3163 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3164 gpio-controller; 3165 #gpio-cells = <2>; 3166 interrupt-controller; 3167 #interrupt-cells = <2>; 3168 gpio-ranges = <&tlmm 0 0 211>; 3169 wakeup-parent = <&pdc>; 3170 3171 sdc2_default_state: sdc2-default-state { 3172 clk-pins { 3173 pins = "sdc2_clk"; 3174 drive-strength = <16>; 3175 bias-disable; 3176 }; 3177 3178 cmd-pins { 3179 pins = "sdc2_cmd"; 3180 drive-strength = <16>; 3181 bias-pull-up; 3182 }; 3183 3184 data-pins { 3185 pins = "sdc2_data"; 3186 drive-strength = <16>; 3187 bias-pull-up; 3188 }; 3189 }; 3190 3191 sdc2_sleep_state: sdc2-sleep-state { 3192 clk-pins { 3193 pins = "sdc2_clk"; 3194 drive-strength = <2>; 3195 bias-disable; 3196 }; 3197 3198 cmd-pins { 3199 pins = "sdc2_cmd"; 3200 drive-strength = <2>; 3201 bias-pull-up; 3202 }; 3203 3204 data-pins { 3205 pins = "sdc2_data"; 3206 drive-strength = <2>; 3207 bias-pull-up; 3208 }; 3209 }; 3210 3211 cci0_default: cci0-default-state { 3212 /* SDA, SCL */ 3213 pins = "gpio110", "gpio111"; 3214 function = "cci_i2c"; 3215 drive-strength = <2>; 3216 bias-pull-up; 3217 }; 3218 3219 cci0_sleep: cci0-sleep-state { 3220 /* SDA, SCL */ 3221 pins = "gpio110", "gpio111"; 3222 function = "cci_i2c"; 3223 drive-strength = <2>; 3224 bias-pull-down; 3225 }; 3226 3227 cci1_default: cci1-default-state { 3228 /* SDA, SCL */ 3229 pins = "gpio112", "gpio113"; 3230 function = "cci_i2c"; 3231 drive-strength = <2>; 3232 bias-pull-up; 3233 }; 3234 3235 cci1_sleep: cci1-sleep-state { 3236 /* SDA, SCL */ 3237 pins = "gpio112", "gpio113"; 3238 function = "cci_i2c"; 3239 drive-strength = <2>; 3240 bias-pull-down; 3241 }; 3242 3243 cci2_default: cci2-default-state { 3244 /* SDA, SCL */ 3245 pins = "gpio114", "gpio115"; 3246 function = "cci_i2c"; 3247 drive-strength = <2>; 3248 bias-pull-up; 3249 }; 3250 3251 cci2_sleep: cci2-sleep-state { 3252 /* SDA, SCL */ 3253 pins = "gpio114", "gpio115"; 3254 function = "cci_i2c"; 3255 drive-strength = <2>; 3256 bias-pull-down; 3257 }; 3258 3259 cci3_default: cci3-default-state { 3260 /* SDA, SCL */ 3261 pins = "gpio208", "gpio209"; 3262 function = "cci_i2c"; 3263 drive-strength = <2>; 3264 bias-pull-up; 3265 }; 3266 3267 cci3_sleep: cci3-sleep-state { 3268 /* SDA, SCL */ 3269 pins = "gpio208", "gpio209"; 3270 function = "cci_i2c"; 3271 drive-strength = <2>; 3272 bias-pull-down; 3273 }; 3274 3275 pcie0_default_state: pcie0-default-state { 3276 perst-pins { 3277 pins = "gpio94"; 3278 function = "gpio"; 3279 drive-strength = <2>; 3280 bias-pull-down; 3281 }; 3282 3283 clkreq-pins { 3284 pins = "gpio95"; 3285 function = "pcie0_clkreqn"; 3286 drive-strength = <2>; 3287 bias-pull-up; 3288 }; 3289 3290 wake-pins { 3291 pins = "gpio96"; 3292 function = "gpio"; 3293 drive-strength = <2>; 3294 bias-pull-up; 3295 }; 3296 }; 3297 3298 pcie1_default_state: pcie1-default-state { 3299 perst-pins { 3300 pins = "gpio97"; 3301 function = "gpio"; 3302 drive-strength = <2>; 3303 bias-pull-down; 3304 }; 3305 3306 clkreq-pins { 3307 pins = "gpio98"; 3308 function = "pcie1_clkreqn"; 3309 drive-strength = <2>; 3310 bias-pull-up; 3311 }; 3312 3313 wake-pins { 3314 pins = "gpio99"; 3315 function = "gpio"; 3316 drive-strength = <2>; 3317 bias-pull-up; 3318 }; 3319 }; 3320 3321 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3322 pins = "gpio0", "gpio1"; 3323 function = "qup0"; 3324 }; 3325 3326 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3327 pins = "gpio4", "gpio5"; 3328 function = "qup1"; 3329 }; 3330 3331 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3332 pins = "gpio8", "gpio9"; 3333 function = "qup2"; 3334 }; 3335 3336 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3337 pins = "gpio12", "gpio13"; 3338 function = "qup3"; 3339 }; 3340 3341 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3342 pins = "gpio16", "gpio17"; 3343 function = "qup4"; 3344 }; 3345 3346 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3347 pins = "gpio206", "gpio207"; 3348 function = "qup5"; 3349 }; 3350 3351 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3352 pins = "gpio20", "gpio21"; 3353 function = "qup6"; 3354 }; 3355 3356 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3357 pins = "gpio28", "gpio29"; 3358 function = "qup8"; 3359 }; 3360 3361 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3362 pins = "gpio32", "gpio33"; 3363 function = "qup9"; 3364 }; 3365 3366 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3367 pins = "gpio36", "gpio37"; 3368 function = "qup10"; 3369 }; 3370 3371 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3372 pins = "gpio40", "gpio41"; 3373 function = "qup11"; 3374 }; 3375 3376 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3377 pins = "gpio44", "gpio45"; 3378 function = "qup12"; 3379 }; 3380 3381 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3382 pins = "gpio48", "gpio49"; 3383 function = "qup13"; 3384 drive-strength = <2>; 3385 bias-pull-up; 3386 }; 3387 3388 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3389 pins = "gpio52", "gpio53"; 3390 function = "qup14"; 3391 drive-strength = <2>; 3392 bias-pull-up; 3393 }; 3394 3395 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3396 pins = "gpio56", "gpio57"; 3397 function = "qup15"; 3398 }; 3399 3400 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3401 pins = "gpio60", "gpio61"; 3402 function = "qup16"; 3403 }; 3404 3405 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3406 pins = "gpio64", "gpio65"; 3407 function = "qup17"; 3408 }; 3409 3410 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3411 pins = "gpio68", "gpio69"; 3412 function = "qup18"; 3413 }; 3414 3415 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3416 pins = "gpio72", "gpio73"; 3417 function = "qup19"; 3418 }; 3419 3420 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3421 pins = "gpio76", "gpio77"; 3422 function = "qup20"; 3423 }; 3424 3425 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3426 pins = "gpio80", "gpio81"; 3427 function = "qup21"; 3428 }; 3429 3430 qup_spi0_cs: qup-spi0-cs-state { 3431 pins = "gpio3"; 3432 function = "qup0"; 3433 }; 3434 3435 qup_spi0_data_clk: qup-spi0-data-clk-state { 3436 pins = "gpio0", "gpio1", "gpio2"; 3437 function = "qup0"; 3438 }; 3439 3440 qup_spi1_cs: qup-spi1-cs-state { 3441 pins = "gpio7"; 3442 function = "qup1"; 3443 }; 3444 3445 qup_spi1_data_clk: qup-spi1-data-clk-state { 3446 pins = "gpio4", "gpio5", "gpio6"; 3447 function = "qup1"; 3448 }; 3449 3450 qup_spi2_cs: qup-spi2-cs-state { 3451 pins = "gpio11"; 3452 function = "qup2"; 3453 }; 3454 3455 qup_spi2_data_clk: qup-spi2-data-clk-state { 3456 pins = "gpio8", "gpio9", "gpio10"; 3457 function = "qup2"; 3458 }; 3459 3460 qup_spi3_cs: qup-spi3-cs-state { 3461 pins = "gpio15"; 3462 function = "qup3"; 3463 }; 3464 3465 qup_spi3_data_clk: qup-spi3-data-clk-state { 3466 pins = "gpio12", "gpio13", "gpio14"; 3467 function = "qup3"; 3468 }; 3469 3470 qup_spi4_cs: qup-spi4-cs-state { 3471 pins = "gpio19"; 3472 function = "qup4"; 3473 drive-strength = <6>; 3474 bias-disable; 3475 }; 3476 3477 qup_spi4_data_clk: qup-spi4-data-clk-state { 3478 pins = "gpio16", "gpio17", "gpio18"; 3479 function = "qup4"; 3480 }; 3481 3482 qup_spi5_cs: qup-spi5-cs-state { 3483 pins = "gpio85"; 3484 function = "qup5"; 3485 }; 3486 3487 qup_spi5_data_clk: qup-spi5-data-clk-state { 3488 pins = "gpio206", "gpio207", "gpio84"; 3489 function = "qup5"; 3490 }; 3491 3492 qup_spi6_cs: qup-spi6-cs-state { 3493 pins = "gpio23"; 3494 function = "qup6"; 3495 }; 3496 3497 qup_spi6_data_clk: qup-spi6-data-clk-state { 3498 pins = "gpio20", "gpio21", "gpio22"; 3499 function = "qup6"; 3500 }; 3501 3502 qup_spi8_cs: qup-spi8-cs-state { 3503 pins = "gpio31"; 3504 function = "qup8"; 3505 }; 3506 3507 qup_spi8_data_clk: qup-spi8-data-clk-state { 3508 pins = "gpio28", "gpio29", "gpio30"; 3509 function = "qup8"; 3510 }; 3511 3512 qup_spi9_cs: qup-spi9-cs-state { 3513 pins = "gpio35"; 3514 function = "qup9"; 3515 }; 3516 3517 qup_spi9_data_clk: qup-spi9-data-clk-state { 3518 pins = "gpio32", "gpio33", "gpio34"; 3519 function = "qup9"; 3520 }; 3521 3522 qup_spi10_cs: qup-spi10-cs-state { 3523 pins = "gpio39"; 3524 function = "qup10"; 3525 }; 3526 3527 qup_spi10_data_clk: qup-spi10-data-clk-state { 3528 pins = "gpio36", "gpio37", "gpio38"; 3529 function = "qup10"; 3530 }; 3531 3532 qup_spi11_cs: qup-spi11-cs-state { 3533 pins = "gpio43"; 3534 function = "qup11"; 3535 }; 3536 3537 qup_spi11_data_clk: qup-spi11-data-clk-state { 3538 pins = "gpio40", "gpio41", "gpio42"; 3539 function = "qup11"; 3540 }; 3541 3542 qup_spi12_cs: qup-spi12-cs-state { 3543 pins = "gpio47"; 3544 function = "qup12"; 3545 }; 3546 3547 qup_spi12_data_clk: qup-spi12-data-clk-state { 3548 pins = "gpio44", "gpio45", "gpio46"; 3549 function = "qup12"; 3550 }; 3551 3552 qup_spi13_cs: qup-spi13-cs-state { 3553 pins = "gpio51"; 3554 function = "qup13"; 3555 }; 3556 3557 qup_spi13_data_clk: qup-spi13-data-clk-state { 3558 pins = "gpio48", "gpio49", "gpio50"; 3559 function = "qup13"; 3560 }; 3561 3562 qup_spi14_cs: qup-spi14-cs-state { 3563 pins = "gpio55"; 3564 function = "qup14"; 3565 }; 3566 3567 qup_spi14_data_clk: qup-spi14-data-clk-state { 3568 pins = "gpio52", "gpio53", "gpio54"; 3569 function = "qup14"; 3570 }; 3571 3572 qup_spi15_cs: qup-spi15-cs-state { 3573 pins = "gpio59"; 3574 function = "qup15"; 3575 }; 3576 3577 qup_spi15_data_clk: qup-spi15-data-clk-state { 3578 pins = "gpio56", "gpio57", "gpio58"; 3579 function = "qup15"; 3580 }; 3581 3582 qup_spi16_cs: qup-spi16-cs-state { 3583 pins = "gpio63"; 3584 function = "qup16"; 3585 }; 3586 3587 qup_spi16_data_clk: qup-spi16-data-clk-state { 3588 pins = "gpio60", "gpio61", "gpio62"; 3589 function = "qup16"; 3590 }; 3591 3592 qup_spi17_cs: qup-spi17-cs-state { 3593 pins = "gpio67"; 3594 function = "qup17"; 3595 }; 3596 3597 qup_spi17_data_clk: qup-spi17-data-clk-state { 3598 pins = "gpio64", "gpio65", "gpio66"; 3599 function = "qup17"; 3600 }; 3601 3602 qup_spi18_cs: qup-spi18-cs-state { 3603 pins = "gpio71"; 3604 function = "qup18"; 3605 drive-strength = <6>; 3606 bias-disable; 3607 }; 3608 3609 qup_spi18_data_clk: qup-spi18-data-clk-state { 3610 pins = "gpio68", "gpio69", "gpio70"; 3611 function = "qup18"; 3612 drive-strength = <6>; 3613 bias-disable; 3614 }; 3615 3616 qup_spi19_cs: qup-spi19-cs-state { 3617 pins = "gpio75"; 3618 function = "qup19"; 3619 drive-strength = <6>; 3620 bias-disable; 3621 }; 3622 3623 qup_spi19_data_clk: qup-spi19-data-clk-state { 3624 pins = "gpio72", "gpio73", "gpio74"; 3625 function = "qup19"; 3626 drive-strength = <6>; 3627 bias-disable; 3628 }; 3629 3630 qup_spi20_cs: qup-spi20-cs-state { 3631 pins = "gpio79"; 3632 function = "qup20"; 3633 }; 3634 3635 qup_spi20_data_clk: qup-spi20-data-clk-state { 3636 pins = "gpio76", "gpio77", "gpio78"; 3637 function = "qup20"; 3638 }; 3639 3640 qup_spi21_cs: qup-spi21-cs-state { 3641 pins = "gpio83"; 3642 function = "qup21"; 3643 }; 3644 3645 qup_spi21_data_clk: qup-spi21-data-clk-state { 3646 pins = "gpio80", "gpio81", "gpio82"; 3647 function = "qup21"; 3648 }; 3649 3650 qup_uart7_rx: qup-uart7-rx-state { 3651 pins = "gpio26"; 3652 function = "qup7"; 3653 drive-strength = <2>; 3654 bias-disable; 3655 }; 3656 3657 qup_uart7_tx: qup-uart7-tx-state { 3658 pins = "gpio27"; 3659 function = "qup7"; 3660 drive-strength = <2>; 3661 bias-disable; 3662 }; 3663 3664 qup_uart20_default: qup-uart20-default-state { 3665 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3666 function = "qup20"; 3667 }; 3668 }; 3669 3670 lpass_tlmm: pinctrl@3440000 { 3671 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3672 reg = <0 0x03440000 0x0 0x20000>, 3673 <0 0x034d0000 0x0 0x10000>; 3674 gpio-controller; 3675 #gpio-cells = <2>; 3676 gpio-ranges = <&lpass_tlmm 0 0 23>; 3677 3678 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3679 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3680 clock-names = "core", "audio"; 3681 3682 tx_swr_active: tx-swr-active-state { 3683 clk-pins { 3684 pins = "gpio0"; 3685 function = "swr_tx_clk"; 3686 drive-strength = <2>; 3687 slew-rate = <1>; 3688 bias-disable; 3689 }; 3690 3691 data-pins { 3692 pins = "gpio1", "gpio2", "gpio14"; 3693 function = "swr_tx_data"; 3694 drive-strength = <2>; 3695 slew-rate = <1>; 3696 bias-bus-hold; 3697 }; 3698 }; 3699 3700 rx_swr_active: rx-swr-active-state { 3701 clk-pins { 3702 pins = "gpio3"; 3703 function = "swr_rx_clk"; 3704 drive-strength = <2>; 3705 slew-rate = <1>; 3706 bias-disable; 3707 }; 3708 3709 data-pins { 3710 pins = "gpio4", "gpio5"; 3711 function = "swr_rx_data"; 3712 drive-strength = <2>; 3713 slew-rate = <1>; 3714 bias-bus-hold; 3715 }; 3716 }; 3717 3718 dmic01_default: dmic01-default-state { 3719 clk-pins { 3720 pins = "gpio6"; 3721 function = "dmic1_clk"; 3722 drive-strength = <8>; 3723 output-high; 3724 }; 3725 3726 data-pins { 3727 pins = "gpio7"; 3728 function = "dmic1_data"; 3729 drive-strength = <8>; 3730 }; 3731 }; 3732 3733 dmic02_default: dmic02-default-state { 3734 clk-pins { 3735 pins = "gpio8"; 3736 function = "dmic2_clk"; 3737 drive-strength = <8>; 3738 output-high; 3739 }; 3740 3741 data-pins { 3742 pins = "gpio9"; 3743 function = "dmic2_data"; 3744 drive-strength = <8>; 3745 }; 3746 }; 3747 3748 wsa_swr_active: wsa-swr-active-state { 3749 clk-pins { 3750 pins = "gpio10"; 3751 function = "wsa_swr_clk"; 3752 drive-strength = <2>; 3753 slew-rate = <1>; 3754 bias-disable; 3755 }; 3756 3757 data-pins { 3758 pins = "gpio11"; 3759 function = "wsa_swr_data"; 3760 drive-strength = <2>; 3761 slew-rate = <1>; 3762 bias-bus-hold; 3763 }; 3764 }; 3765 3766 wsa2_swr_active: wsa2-swr-active-state { 3767 clk-pins { 3768 pins = "gpio15"; 3769 function = "wsa2_swr_clk"; 3770 drive-strength = <2>; 3771 slew-rate = <1>; 3772 bias-disable; 3773 }; 3774 3775 data-pins { 3776 pins = "gpio16"; 3777 function = "wsa2_swr_data"; 3778 drive-strength = <2>; 3779 slew-rate = <1>; 3780 bias-bus-hold; 3781 }; 3782 }; 3783 }; 3784 3785 sram@146aa000 { 3786 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3787 reg = <0 0x146aa000 0 0x1000>; 3788 ranges = <0 0 0x146aa000 0x1000>; 3789 3790 #address-cells = <1>; 3791 #size-cells = <1>; 3792 3793 pil-reloc@94c { 3794 compatible = "qcom,pil-reloc-info"; 3795 reg = <0x94c 0xc8>; 3796 }; 3797 }; 3798 3799 apps_smmu: iommu@15000000 { 3800 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3801 reg = <0 0x15000000 0 0x100000>; 3802 #iommu-cells = <2>; 3803 #global-interrupts = <1>; 3804 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3901 }; 3902 3903 intc: interrupt-controller@17100000 { 3904 compatible = "arm,gic-v3"; 3905 #interrupt-cells = <3>; 3906 interrupt-controller; 3907 #redistributor-regions = <1>; 3908 redistributor-stride = <0x0 0x40000>; 3909 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3910 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3911 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3912 #address-cells = <2>; 3913 #size-cells = <2>; 3914 ranges; 3915 3916 gic_its: msi-controller@17140000 { 3917 compatible = "arm,gic-v3-its"; 3918 reg = <0x0 0x17140000 0x0 0x20000>; 3919 msi-controller; 3920 #msi-cells = <1>; 3921 }; 3922 }; 3923 3924 timer@17420000 { 3925 compatible = "arm,armv7-timer-mem"; 3926 #address-cells = <1>; 3927 #size-cells = <1>; 3928 ranges = <0 0 0 0x20000000>; 3929 reg = <0x0 0x17420000 0x0 0x1000>; 3930 clock-frequency = <19200000>; 3931 3932 frame@17421000 { 3933 frame-number = <0>; 3934 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3936 reg = <0x17421000 0x1000>, 3937 <0x17422000 0x1000>; 3938 }; 3939 3940 frame@17423000 { 3941 frame-number = <1>; 3942 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3943 reg = <0x17423000 0x1000>; 3944 status = "disabled"; 3945 }; 3946 3947 frame@17425000 { 3948 frame-number = <2>; 3949 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3950 reg = <0x17425000 0x1000>; 3951 status = "disabled"; 3952 }; 3953 3954 frame@17427000 { 3955 frame-number = <3>; 3956 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3957 reg = <0x17427000 0x1000>; 3958 status = "disabled"; 3959 }; 3960 3961 frame@17429000 { 3962 frame-number = <4>; 3963 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3964 reg = <0x17429000 0x1000>; 3965 status = "disabled"; 3966 }; 3967 3968 frame@1742b000 { 3969 frame-number = <5>; 3970 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3971 reg = <0x1742b000 0x1000>; 3972 status = "disabled"; 3973 }; 3974 3975 frame@1742d000 { 3976 frame-number = <6>; 3977 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3978 reg = <0x1742d000 0x1000>; 3979 status = "disabled"; 3980 }; 3981 }; 3982 3983 apps_rsc: rsc@17a00000 { 3984 label = "apps_rsc"; 3985 compatible = "qcom,rpmh-rsc"; 3986 reg = <0x0 0x17a00000 0x0 0x10000>, 3987 <0x0 0x17a10000 0x0 0x10000>, 3988 <0x0 0x17a20000 0x0 0x10000>, 3989 <0x0 0x17a30000 0x0 0x10000>; 3990 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3991 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3994 qcom,tcs-offset = <0xd00>; 3995 qcom,drv-id = <2>; 3996 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3997 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3998 power-domains = <&CLUSTER_PD>; 3999 4000 apps_bcm_voter: bcm-voter { 4001 compatible = "qcom,bcm-voter"; 4002 }; 4003 4004 rpmhcc: clock-controller { 4005 compatible = "qcom,sm8450-rpmh-clk"; 4006 #clock-cells = <1>; 4007 clock-names = "xo"; 4008 clocks = <&xo_board>; 4009 }; 4010 4011 rpmhpd: power-controller { 4012 compatible = "qcom,sm8450-rpmhpd"; 4013 #power-domain-cells = <1>; 4014 operating-points-v2 = <&rpmhpd_opp_table>; 4015 4016 rpmhpd_opp_table: opp-table { 4017 compatible = "operating-points-v2"; 4018 4019 rpmhpd_opp_ret: opp1 { 4020 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4021 }; 4022 4023 rpmhpd_opp_min_svs: opp2 { 4024 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4025 }; 4026 4027 rpmhpd_opp_low_svs_d1: opp3 { 4028 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4029 }; 4030 4031 rpmhpd_opp_low_svs: opp4 { 4032 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4033 }; 4034 4035 rpmhpd_opp_low_svs_l1: opp5 { 4036 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4037 }; 4038 4039 rpmhpd_opp_svs: opp6 { 4040 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4041 }; 4042 4043 rpmhpd_opp_svs_l0: opp7 { 4044 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4045 }; 4046 4047 rpmhpd_opp_svs_l1: opp8 { 4048 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4049 }; 4050 4051 rpmhpd_opp_svs_l2: opp9 { 4052 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4053 }; 4054 4055 rpmhpd_opp_nom: opp10 { 4056 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4057 }; 4058 4059 rpmhpd_opp_nom_l1: opp11 { 4060 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4061 }; 4062 4063 rpmhpd_opp_nom_l2: opp12 { 4064 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4065 }; 4066 4067 rpmhpd_opp_turbo: opp13 { 4068 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4069 }; 4070 4071 rpmhpd_opp_turbo_l1: opp14 { 4072 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4073 }; 4074 }; 4075 }; 4076 }; 4077 4078 cpufreq_hw: cpufreq@17d91000 { 4079 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4080 reg = <0 0x17d91000 0 0x1000>, 4081 <0 0x17d92000 0 0x1000>, 4082 <0 0x17d93000 0 0x1000>; 4083 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4084 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4085 clock-names = "xo", "alternate"; 4086 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4089 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4090 #freq-domain-cells = <1>; 4091 #clock-cells = <1>; 4092 }; 4093 4094 gem_noc: interconnect@19100000 { 4095 compatible = "qcom,sm8450-gem-noc"; 4096 reg = <0 0x19100000 0 0xbb800>; 4097 #interconnect-cells = <2>; 4098 qcom,bcm-voters = <&apps_bcm_voter>; 4099 }; 4100 4101 system-cache-controller@19200000 { 4102 compatible = "qcom,sm8450-llcc"; 4103 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4104 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4105 <0 0x19a00000 0 0x80000>; 4106 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4107 "llcc3_base", "llcc_broadcast_base"; 4108 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4109 }; 4110 4111 ufs_mem_hc: ufshc@1d84000 { 4112 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4113 "jedec,ufs-2.0"; 4114 reg = <0 0x01d84000 0 0x3000>, 4115 <0 0x01d88000 0 0x8000>; 4116 reg-names = "std", "ice"; 4117 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4118 phys = <&ufs_mem_phy_lanes>; 4119 phy-names = "ufsphy"; 4120 lanes-per-direction = <2>; 4121 #reset-cells = <1>; 4122 resets = <&gcc GCC_UFS_PHY_BCR>; 4123 reset-names = "rst"; 4124 4125 power-domains = <&gcc UFS_PHY_GDSC>; 4126 4127 iommus = <&apps_smmu 0xe0 0x0>; 4128 dma-coherent; 4129 4130 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4132 interconnect-names = "ufs-ddr", "cpu-ufs"; 4133 clock-names = 4134 "core_clk", 4135 "bus_aggr_clk", 4136 "iface_clk", 4137 "core_clk_unipro", 4138 "ref_clk", 4139 "tx_lane0_sync_clk", 4140 "rx_lane0_sync_clk", 4141 "rx_lane1_sync_clk", 4142 "ice_core_clk"; 4143 clocks = 4144 <&gcc GCC_UFS_PHY_AXI_CLK>, 4145 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4146 <&gcc GCC_UFS_PHY_AHB_CLK>, 4147 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4148 <&rpmhcc RPMH_CXO_CLK>, 4149 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4150 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4151 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 4152 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4153 freq-table-hz = 4154 <75000000 300000000>, 4155 <0 0>, 4156 <0 0>, 4157 <75000000 300000000>, 4158 <75000000 300000000>, 4159 <0 0>, 4160 <0 0>, 4161 <0 0>, 4162 <75000000 300000000>; 4163 status = "disabled"; 4164 }; 4165 4166 ufs_mem_phy: phy@1d87000 { 4167 compatible = "qcom,sm8450-qmp-ufs-phy"; 4168 reg = <0 0x01d87000 0 0x1c4>; 4169 #address-cells = <2>; 4170 #size-cells = <2>; 4171 ranges; 4172 clock-names = "ref", "ref_aux", "qref"; 4173 clocks = <&rpmhcc RPMH_CXO_CLK>, 4174 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4175 <&gcc GCC_UFS_0_CLKREF_EN>; 4176 4177 resets = <&ufs_mem_hc 0>; 4178 reset-names = "ufsphy"; 4179 status = "disabled"; 4180 4181 ufs_mem_phy_lanes: phy@1d87400 { 4182 reg = <0 0x01d87400 0 0x188>, 4183 <0 0x01d87600 0 0x200>, 4184 <0 0x01d87c00 0 0x200>, 4185 <0 0x01d87800 0 0x188>, 4186 <0 0x01d87a00 0 0x200>; 4187 #clock-cells = <1>; 4188 #phy-cells = <0>; 4189 }; 4190 }; 4191 4192 cryptobam: dma-controller@1dc4000 { 4193 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4194 reg = <0 0x01dc4000 0 0x28000>; 4195 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4196 #dma-cells = <1>; 4197 qcom,ee = <0>; 4198 qcom,controlled-remotely; 4199 iommus = <&apps_smmu 0x584 0x11>, 4200 <&apps_smmu 0x588 0x0>, 4201 <&apps_smmu 0x598 0x5>, 4202 <&apps_smmu 0x59a 0x0>, 4203 <&apps_smmu 0x59f 0x0>; 4204 }; 4205 4206 crypto: crypto@1de0000 { 4207 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4208 reg = <0 0x01dfa000 0 0x6000>; 4209 dmas = <&cryptobam 4>, <&cryptobam 5>; 4210 dma-names = "rx", "tx"; 4211 iommus = <&apps_smmu 0x584 0x11>, 4212 <&apps_smmu 0x588 0x0>, 4213 <&apps_smmu 0x598 0x5>, 4214 <&apps_smmu 0x59a 0x0>, 4215 <&apps_smmu 0x59f 0x0>; 4216 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4217 interconnect-names = "memory"; 4218 }; 4219 4220 sdhc_2: mmc@8804000 { 4221 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4222 reg = <0 0x08804000 0 0x1000>; 4223 4224 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4226 interrupt-names = "hc_irq", "pwr_irq"; 4227 4228 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4229 <&gcc GCC_SDCC2_APPS_CLK>, 4230 <&rpmhcc RPMH_CXO_CLK>; 4231 clock-names = "iface", "core", "xo"; 4232 resets = <&gcc GCC_SDCC2_BCR>; 4233 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4235 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4236 iommus = <&apps_smmu 0x4a0 0x0>; 4237 power-domains = <&rpmhpd SM8450_CX>; 4238 operating-points-v2 = <&sdhc2_opp_table>; 4239 bus-width = <4>; 4240 dma-coherent; 4241 4242 /* Forbid SDR104/SDR50 - broken hw! */ 4243 sdhci-caps-mask = <0x3 0x0>; 4244 4245 status = "disabled"; 4246 4247 sdhc2_opp_table: opp-table { 4248 compatible = "operating-points-v2"; 4249 4250 opp-100000000 { 4251 opp-hz = /bits/ 64 <100000000>; 4252 required-opps = <&rpmhpd_opp_low_svs>; 4253 }; 4254 4255 opp-202000000 { 4256 opp-hz = /bits/ 64 <202000000>; 4257 required-opps = <&rpmhpd_opp_svs_l1>; 4258 }; 4259 }; 4260 }; 4261 4262 usb_1: usb@a6f8800 { 4263 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4264 reg = <0 0x0a6f8800 0 0x400>; 4265 status = "disabled"; 4266 #address-cells = <2>; 4267 #size-cells = <2>; 4268 ranges; 4269 4270 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4271 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4272 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4273 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4274 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4275 <&gcc GCC_USB3_0_CLKREF_EN>; 4276 clock-names = "cfg_noc", 4277 "core", 4278 "iface", 4279 "sleep", 4280 "mock_utmi", 4281 "xo"; 4282 4283 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4284 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4285 assigned-clock-rates = <19200000>, <200000000>; 4286 4287 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4288 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4289 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4290 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4291 interrupt-names = "hs_phy_irq", 4292 "ss_phy_irq", 4293 "dm_hs_phy_irq", 4294 "dp_hs_phy_irq"; 4295 4296 power-domains = <&gcc USB30_PRIM_GDSC>; 4297 4298 resets = <&gcc GCC_USB30_PRIM_BCR>; 4299 4300 usb_1_dwc3: usb@a600000 { 4301 compatible = "snps,dwc3"; 4302 reg = <0 0x0a600000 0 0xcd00>; 4303 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4304 iommus = <&apps_smmu 0x0 0x0>; 4305 snps,dis_u2_susphy_quirk; 4306 snps,dis_enblslpm_quirk; 4307 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4308 phy-names = "usb2-phy", "usb3-phy"; 4309 4310 ports { 4311 #address-cells = <1>; 4312 #size-cells = <0>; 4313 4314 port@0 { 4315 reg = <0>; 4316 4317 usb_1_dwc3_hs: endpoint { 4318 }; 4319 }; 4320 4321 port@1 { 4322 reg = <1>; 4323 4324 usb_1_dwc3_ss: endpoint { 4325 }; 4326 }; 4327 }; 4328 }; 4329 }; 4330 4331 nsp_noc: interconnect@320c0000 { 4332 compatible = "qcom,sm8450-nsp-noc"; 4333 reg = <0 0x320c0000 0 0x10000>; 4334 #interconnect-cells = <2>; 4335 qcom,bcm-voters = <&apps_bcm_voter>; 4336 }; 4337 4338 lpass_ag_noc: interconnect@3c40000 { 4339 compatible = "qcom,sm8450-lpass-ag-noc"; 4340 reg = <0 0x03c40000 0 0x17200>; 4341 #interconnect-cells = <2>; 4342 qcom,bcm-voters = <&apps_bcm_voter>; 4343 }; 4344 }; 4345 4346 sound: sound { 4347 }; 4348 4349 thermal-zones { 4350 aoss0-thermal { 4351 polling-delay-passive = <0>; 4352 polling-delay = <0>; 4353 thermal-sensors = <&tsens0 0>; 4354 4355 trips { 4356 thermal-engine-config { 4357 temperature = <125000>; 4358 hysteresis = <1000>; 4359 type = "passive"; 4360 }; 4361 4362 reset-mon-cfg { 4363 temperature = <115000>; 4364 hysteresis = <5000>; 4365 type = "passive"; 4366 }; 4367 }; 4368 }; 4369 4370 cpuss0-thermal { 4371 polling-delay-passive = <0>; 4372 polling-delay = <0>; 4373 thermal-sensors = <&tsens0 1>; 4374 4375 trips { 4376 thermal-engine-config { 4377 temperature = <125000>; 4378 hysteresis = <1000>; 4379 type = "passive"; 4380 }; 4381 4382 reset-mon-cfg { 4383 temperature = <115000>; 4384 hysteresis = <5000>; 4385 type = "passive"; 4386 }; 4387 }; 4388 }; 4389 4390 cpuss1-thermal { 4391 polling-delay-passive = <0>; 4392 polling-delay = <0>; 4393 thermal-sensors = <&tsens0 2>; 4394 4395 trips { 4396 thermal-engine-config { 4397 temperature = <125000>; 4398 hysteresis = <1000>; 4399 type = "passive"; 4400 }; 4401 4402 reset-mon-cfg { 4403 temperature = <115000>; 4404 hysteresis = <5000>; 4405 type = "passive"; 4406 }; 4407 }; 4408 }; 4409 4410 cpuss3-thermal { 4411 polling-delay-passive = <0>; 4412 polling-delay = <0>; 4413 thermal-sensors = <&tsens0 3>; 4414 4415 trips { 4416 thermal-engine-config { 4417 temperature = <125000>; 4418 hysteresis = <1000>; 4419 type = "passive"; 4420 }; 4421 4422 reset-mon-cfg { 4423 temperature = <115000>; 4424 hysteresis = <5000>; 4425 type = "passive"; 4426 }; 4427 }; 4428 }; 4429 4430 cpuss4-thermal { 4431 polling-delay-passive = <0>; 4432 polling-delay = <0>; 4433 thermal-sensors = <&tsens0 4>; 4434 4435 trips { 4436 thermal-engine-config { 4437 temperature = <125000>; 4438 hysteresis = <1000>; 4439 type = "passive"; 4440 }; 4441 4442 reset-mon-cfg { 4443 temperature = <115000>; 4444 hysteresis = <5000>; 4445 type = "passive"; 4446 }; 4447 }; 4448 }; 4449 4450 cpu4-top-thermal { 4451 polling-delay-passive = <0>; 4452 polling-delay = <0>; 4453 thermal-sensors = <&tsens0 5>; 4454 4455 trips { 4456 cpu4_top_alert0: trip-point0 { 4457 temperature = <90000>; 4458 hysteresis = <2000>; 4459 type = "passive"; 4460 }; 4461 4462 cpu4_top_alert1: trip-point1 { 4463 temperature = <95000>; 4464 hysteresis = <2000>; 4465 type = "passive"; 4466 }; 4467 4468 cpu4_top_crit: cpu-crit { 4469 temperature = <110000>; 4470 hysteresis = <1000>; 4471 type = "critical"; 4472 }; 4473 }; 4474 }; 4475 4476 cpu4-bottom-thermal { 4477 polling-delay-passive = <0>; 4478 polling-delay = <0>; 4479 thermal-sensors = <&tsens0 6>; 4480 4481 trips { 4482 cpu4_bottom_alert0: trip-point0 { 4483 temperature = <90000>; 4484 hysteresis = <2000>; 4485 type = "passive"; 4486 }; 4487 4488 cpu4_bottom_alert1: trip-point1 { 4489 temperature = <95000>; 4490 hysteresis = <2000>; 4491 type = "passive"; 4492 }; 4493 4494 cpu4_bottom_crit: cpu-crit { 4495 temperature = <110000>; 4496 hysteresis = <1000>; 4497 type = "critical"; 4498 }; 4499 }; 4500 }; 4501 4502 cpu5-top-thermal { 4503 polling-delay-passive = <0>; 4504 polling-delay = <0>; 4505 thermal-sensors = <&tsens0 7>; 4506 4507 trips { 4508 cpu5_top_alert0: trip-point0 { 4509 temperature = <90000>; 4510 hysteresis = <2000>; 4511 type = "passive"; 4512 }; 4513 4514 cpu5_top_alert1: trip-point1 { 4515 temperature = <95000>; 4516 hysteresis = <2000>; 4517 type = "passive"; 4518 }; 4519 4520 cpu5_top_crit: cpu-crit { 4521 temperature = <110000>; 4522 hysteresis = <1000>; 4523 type = "critical"; 4524 }; 4525 }; 4526 }; 4527 4528 cpu5-bottom-thermal { 4529 polling-delay-passive = <0>; 4530 polling-delay = <0>; 4531 thermal-sensors = <&tsens0 8>; 4532 4533 trips { 4534 cpu5_bottom_alert0: trip-point0 { 4535 temperature = <90000>; 4536 hysteresis = <2000>; 4537 type = "passive"; 4538 }; 4539 4540 cpu5_bottom_alert1: trip-point1 { 4541 temperature = <95000>; 4542 hysteresis = <2000>; 4543 type = "passive"; 4544 }; 4545 4546 cpu5_bottom_crit: cpu-crit { 4547 temperature = <110000>; 4548 hysteresis = <1000>; 4549 type = "critical"; 4550 }; 4551 }; 4552 }; 4553 4554 cpu6-top-thermal { 4555 polling-delay-passive = <0>; 4556 polling-delay = <0>; 4557 thermal-sensors = <&tsens0 9>; 4558 4559 trips { 4560 cpu6_top_alert0: trip-point0 { 4561 temperature = <90000>; 4562 hysteresis = <2000>; 4563 type = "passive"; 4564 }; 4565 4566 cpu6_top_alert1: trip-point1 { 4567 temperature = <95000>; 4568 hysteresis = <2000>; 4569 type = "passive"; 4570 }; 4571 4572 cpu6_top_crit: cpu-crit { 4573 temperature = <110000>; 4574 hysteresis = <1000>; 4575 type = "critical"; 4576 }; 4577 }; 4578 }; 4579 4580 cpu6-bottom-thermal { 4581 polling-delay-passive = <0>; 4582 polling-delay = <0>; 4583 thermal-sensors = <&tsens0 10>; 4584 4585 trips { 4586 cpu6_bottom_alert0: trip-point0 { 4587 temperature = <90000>; 4588 hysteresis = <2000>; 4589 type = "passive"; 4590 }; 4591 4592 cpu6_bottom_alert1: trip-point1 { 4593 temperature = <95000>; 4594 hysteresis = <2000>; 4595 type = "passive"; 4596 }; 4597 4598 cpu6_bottom_crit: cpu-crit { 4599 temperature = <110000>; 4600 hysteresis = <1000>; 4601 type = "critical"; 4602 }; 4603 }; 4604 }; 4605 4606 cpu7-top-thermal { 4607 polling-delay-passive = <0>; 4608 polling-delay = <0>; 4609 thermal-sensors = <&tsens0 11>; 4610 4611 trips { 4612 cpu7_top_alert0: trip-point0 { 4613 temperature = <90000>; 4614 hysteresis = <2000>; 4615 type = "passive"; 4616 }; 4617 4618 cpu7_top_alert1: trip-point1 { 4619 temperature = <95000>; 4620 hysteresis = <2000>; 4621 type = "passive"; 4622 }; 4623 4624 cpu7_top_crit: cpu-crit { 4625 temperature = <110000>; 4626 hysteresis = <1000>; 4627 type = "critical"; 4628 }; 4629 }; 4630 }; 4631 4632 cpu7-middle-thermal { 4633 polling-delay-passive = <0>; 4634 polling-delay = <0>; 4635 thermal-sensors = <&tsens0 12>; 4636 4637 trips { 4638 cpu7_middle_alert0: trip-point0 { 4639 temperature = <90000>; 4640 hysteresis = <2000>; 4641 type = "passive"; 4642 }; 4643 4644 cpu7_middle_alert1: trip-point1 { 4645 temperature = <95000>; 4646 hysteresis = <2000>; 4647 type = "passive"; 4648 }; 4649 4650 cpu7_middle_crit: cpu-crit { 4651 temperature = <110000>; 4652 hysteresis = <1000>; 4653 type = "critical"; 4654 }; 4655 }; 4656 }; 4657 4658 cpu7-bottom-thermal { 4659 polling-delay-passive = <0>; 4660 polling-delay = <0>; 4661 thermal-sensors = <&tsens0 13>; 4662 4663 trips { 4664 cpu7_bottom_alert0: trip-point0 { 4665 temperature = <90000>; 4666 hysteresis = <2000>; 4667 type = "passive"; 4668 }; 4669 4670 cpu7_bottom_alert1: trip-point1 { 4671 temperature = <95000>; 4672 hysteresis = <2000>; 4673 type = "passive"; 4674 }; 4675 4676 cpu7_bottom_crit: cpu-crit { 4677 temperature = <110000>; 4678 hysteresis = <1000>; 4679 type = "critical"; 4680 }; 4681 }; 4682 }; 4683 4684 gpu-top-thermal { 4685 polling-delay-passive = <10>; 4686 polling-delay = <0>; 4687 thermal-sensors = <&tsens0 14>; 4688 4689 trips { 4690 thermal-engine-config { 4691 temperature = <125000>; 4692 hysteresis = <1000>; 4693 type = "passive"; 4694 }; 4695 4696 thermal-hal-config { 4697 temperature = <125000>; 4698 hysteresis = <1000>; 4699 type = "passive"; 4700 }; 4701 4702 reset-mon-cfg { 4703 temperature = <115000>; 4704 hysteresis = <5000>; 4705 type = "passive"; 4706 }; 4707 4708 gpu0_tj_cfg: tj-cfg { 4709 temperature = <95000>; 4710 hysteresis = <5000>; 4711 type = "passive"; 4712 }; 4713 }; 4714 }; 4715 4716 gpu-bottom-thermal { 4717 polling-delay-passive = <10>; 4718 polling-delay = <0>; 4719 thermal-sensors = <&tsens0 15>; 4720 4721 trips { 4722 thermal-engine-config { 4723 temperature = <125000>; 4724 hysteresis = <1000>; 4725 type = "passive"; 4726 }; 4727 4728 thermal-hal-config { 4729 temperature = <125000>; 4730 hysteresis = <1000>; 4731 type = "passive"; 4732 }; 4733 4734 reset-mon-cfg { 4735 temperature = <115000>; 4736 hysteresis = <5000>; 4737 type = "passive"; 4738 }; 4739 4740 gpu1_tj_cfg: tj-cfg { 4741 temperature = <95000>; 4742 hysteresis = <5000>; 4743 type = "passive"; 4744 }; 4745 }; 4746 }; 4747 4748 aoss1-thermal { 4749 polling-delay-passive = <0>; 4750 polling-delay = <0>; 4751 thermal-sensors = <&tsens1 0>; 4752 4753 trips { 4754 thermal-engine-config { 4755 temperature = <125000>; 4756 hysteresis = <1000>; 4757 type = "passive"; 4758 }; 4759 4760 reset-mon-cfg { 4761 temperature = <115000>; 4762 hysteresis = <5000>; 4763 type = "passive"; 4764 }; 4765 }; 4766 }; 4767 4768 cpu0-thermal { 4769 polling-delay-passive = <0>; 4770 polling-delay = <0>; 4771 thermal-sensors = <&tsens1 1>; 4772 4773 trips { 4774 cpu0_alert0: trip-point0 { 4775 temperature = <90000>; 4776 hysteresis = <2000>; 4777 type = "passive"; 4778 }; 4779 4780 cpu0_alert1: trip-point1 { 4781 temperature = <95000>; 4782 hysteresis = <2000>; 4783 type = "passive"; 4784 }; 4785 4786 cpu0_crit: cpu-crit { 4787 temperature = <110000>; 4788 hysteresis = <1000>; 4789 type = "critical"; 4790 }; 4791 }; 4792 }; 4793 4794 cpu1-thermal { 4795 polling-delay-passive = <0>; 4796 polling-delay = <0>; 4797 thermal-sensors = <&tsens1 2>; 4798 4799 trips { 4800 cpu1_alert0: trip-point0 { 4801 temperature = <90000>; 4802 hysteresis = <2000>; 4803 type = "passive"; 4804 }; 4805 4806 cpu1_alert1: trip-point1 { 4807 temperature = <95000>; 4808 hysteresis = <2000>; 4809 type = "passive"; 4810 }; 4811 4812 cpu1_crit: cpu-crit { 4813 temperature = <110000>; 4814 hysteresis = <1000>; 4815 type = "critical"; 4816 }; 4817 }; 4818 }; 4819 4820 cpu2-thermal { 4821 polling-delay-passive = <0>; 4822 polling-delay = <0>; 4823 thermal-sensors = <&tsens1 3>; 4824 4825 trips { 4826 cpu2_alert0: trip-point0 { 4827 temperature = <90000>; 4828 hysteresis = <2000>; 4829 type = "passive"; 4830 }; 4831 4832 cpu2_alert1: trip-point1 { 4833 temperature = <95000>; 4834 hysteresis = <2000>; 4835 type = "passive"; 4836 }; 4837 4838 cpu2_crit: cpu-crit { 4839 temperature = <110000>; 4840 hysteresis = <1000>; 4841 type = "critical"; 4842 }; 4843 }; 4844 }; 4845 4846 cpu3-thermal { 4847 polling-delay-passive = <0>; 4848 polling-delay = <0>; 4849 thermal-sensors = <&tsens1 4>; 4850 4851 trips { 4852 cpu3_alert0: trip-point0 { 4853 temperature = <90000>; 4854 hysteresis = <2000>; 4855 type = "passive"; 4856 }; 4857 4858 cpu3_alert1: trip-point1 { 4859 temperature = <95000>; 4860 hysteresis = <2000>; 4861 type = "passive"; 4862 }; 4863 4864 cpu3_crit: cpu-crit { 4865 temperature = <110000>; 4866 hysteresis = <1000>; 4867 type = "critical"; 4868 }; 4869 }; 4870 }; 4871 4872 cdsp0-thermal { 4873 polling-delay-passive = <10>; 4874 polling-delay = <0>; 4875 thermal-sensors = <&tsens1 5>; 4876 4877 trips { 4878 thermal-engine-config { 4879 temperature = <125000>; 4880 hysteresis = <1000>; 4881 type = "passive"; 4882 }; 4883 4884 thermal-hal-config { 4885 temperature = <125000>; 4886 hysteresis = <1000>; 4887 type = "passive"; 4888 }; 4889 4890 reset-mon-cfg { 4891 temperature = <115000>; 4892 hysteresis = <5000>; 4893 type = "passive"; 4894 }; 4895 4896 cdsp_0_config: junction-config { 4897 temperature = <95000>; 4898 hysteresis = <5000>; 4899 type = "passive"; 4900 }; 4901 }; 4902 }; 4903 4904 cdsp1-thermal { 4905 polling-delay-passive = <10>; 4906 polling-delay = <0>; 4907 thermal-sensors = <&tsens1 6>; 4908 4909 trips { 4910 thermal-engine-config { 4911 temperature = <125000>; 4912 hysteresis = <1000>; 4913 type = "passive"; 4914 }; 4915 4916 thermal-hal-config { 4917 temperature = <125000>; 4918 hysteresis = <1000>; 4919 type = "passive"; 4920 }; 4921 4922 reset-mon-cfg { 4923 temperature = <115000>; 4924 hysteresis = <5000>; 4925 type = "passive"; 4926 }; 4927 4928 cdsp_1_config: junction-config { 4929 temperature = <95000>; 4930 hysteresis = <5000>; 4931 type = "passive"; 4932 }; 4933 }; 4934 }; 4935 4936 cdsp2-thermal { 4937 polling-delay-passive = <10>; 4938 polling-delay = <0>; 4939 thermal-sensors = <&tsens1 7>; 4940 4941 trips { 4942 thermal-engine-config { 4943 temperature = <125000>; 4944 hysteresis = <1000>; 4945 type = "passive"; 4946 }; 4947 4948 thermal-hal-config { 4949 temperature = <125000>; 4950 hysteresis = <1000>; 4951 type = "passive"; 4952 }; 4953 4954 reset-mon-cfg { 4955 temperature = <115000>; 4956 hysteresis = <5000>; 4957 type = "passive"; 4958 }; 4959 4960 cdsp_2_config: junction-config { 4961 temperature = <95000>; 4962 hysteresis = <5000>; 4963 type = "passive"; 4964 }; 4965 }; 4966 }; 4967 4968 video-thermal { 4969 polling-delay-passive = <0>; 4970 polling-delay = <0>; 4971 thermal-sensors = <&tsens1 8>; 4972 4973 trips { 4974 thermal-engine-config { 4975 temperature = <125000>; 4976 hysteresis = <1000>; 4977 type = "passive"; 4978 }; 4979 4980 reset-mon-cfg { 4981 temperature = <115000>; 4982 hysteresis = <5000>; 4983 type = "passive"; 4984 }; 4985 }; 4986 }; 4987 4988 mem-thermal { 4989 polling-delay-passive = <10>; 4990 polling-delay = <0>; 4991 thermal-sensors = <&tsens1 9>; 4992 4993 trips { 4994 thermal-engine-config { 4995 temperature = <125000>; 4996 hysteresis = <1000>; 4997 type = "passive"; 4998 }; 4999 5000 ddr_config0: ddr0-config { 5001 temperature = <90000>; 5002 hysteresis = <5000>; 5003 type = "passive"; 5004 }; 5005 5006 reset-mon-cfg { 5007 temperature = <115000>; 5008 hysteresis = <5000>; 5009 type = "passive"; 5010 }; 5011 }; 5012 }; 5013 5014 modem0-thermal { 5015 polling-delay-passive = <0>; 5016 polling-delay = <0>; 5017 thermal-sensors = <&tsens1 10>; 5018 5019 trips { 5020 thermal-engine-config { 5021 temperature = <125000>; 5022 hysteresis = <1000>; 5023 type = "passive"; 5024 }; 5025 5026 mdmss0_config0: mdmss0-config0 { 5027 temperature = <102000>; 5028 hysteresis = <3000>; 5029 type = "passive"; 5030 }; 5031 5032 mdmss0_config1: mdmss0-config1 { 5033 temperature = <105000>; 5034 hysteresis = <3000>; 5035 type = "passive"; 5036 }; 5037 5038 reset-mon-cfg { 5039 temperature = <115000>; 5040 hysteresis = <5000>; 5041 type = "passive"; 5042 }; 5043 }; 5044 }; 5045 5046 modem1-thermal { 5047 polling-delay-passive = <0>; 5048 polling-delay = <0>; 5049 thermal-sensors = <&tsens1 11>; 5050 5051 trips { 5052 thermal-engine-config { 5053 temperature = <125000>; 5054 hysteresis = <1000>; 5055 type = "passive"; 5056 }; 5057 5058 mdmss1_config0: mdmss1-config0 { 5059 temperature = <102000>; 5060 hysteresis = <3000>; 5061 type = "passive"; 5062 }; 5063 5064 mdmss1_config1: mdmss1-config1 { 5065 temperature = <105000>; 5066 hysteresis = <3000>; 5067 type = "passive"; 5068 }; 5069 5070 reset-mon-cfg { 5071 temperature = <115000>; 5072 hysteresis = <5000>; 5073 type = "passive"; 5074 }; 5075 }; 5076 }; 5077 5078 modem2-thermal { 5079 polling-delay-passive = <0>; 5080 polling-delay = <0>; 5081 thermal-sensors = <&tsens1 12>; 5082 5083 trips { 5084 thermal-engine-config { 5085 temperature = <125000>; 5086 hysteresis = <1000>; 5087 type = "passive"; 5088 }; 5089 5090 mdmss2_config0: mdmss2-config0 { 5091 temperature = <102000>; 5092 hysteresis = <3000>; 5093 type = "passive"; 5094 }; 5095 5096 mdmss2_config1: mdmss2-config1 { 5097 temperature = <105000>; 5098 hysteresis = <3000>; 5099 type = "passive"; 5100 }; 5101 5102 reset-mon-cfg { 5103 temperature = <115000>; 5104 hysteresis = <5000>; 5105 type = "passive"; 5106 }; 5107 }; 5108 }; 5109 5110 modem3-thermal { 5111 polling-delay-passive = <0>; 5112 polling-delay = <0>; 5113 thermal-sensors = <&tsens1 13>; 5114 5115 trips { 5116 thermal-engine-config { 5117 temperature = <125000>; 5118 hysteresis = <1000>; 5119 type = "passive"; 5120 }; 5121 5122 mdmss3_config0: mdmss3-config0 { 5123 temperature = <102000>; 5124 hysteresis = <3000>; 5125 type = "passive"; 5126 }; 5127 5128 mdmss3_config1: mdmss3-config1 { 5129 temperature = <105000>; 5130 hysteresis = <3000>; 5131 type = "passive"; 5132 }; 5133 5134 reset-mon-cfg { 5135 temperature = <115000>; 5136 hysteresis = <5000>; 5137 type = "passive"; 5138 }; 5139 }; 5140 }; 5141 5142 camera0-thermal { 5143 polling-delay-passive = <0>; 5144 polling-delay = <0>; 5145 thermal-sensors = <&tsens1 14>; 5146 5147 trips { 5148 thermal-engine-config { 5149 temperature = <125000>; 5150 hysteresis = <1000>; 5151 type = "passive"; 5152 }; 5153 5154 reset-mon-cfg { 5155 temperature = <115000>; 5156 hysteresis = <5000>; 5157 type = "passive"; 5158 }; 5159 }; 5160 }; 5161 5162 camera1-thermal { 5163 polling-delay-passive = <0>; 5164 polling-delay = <0>; 5165 thermal-sensors = <&tsens1 15>; 5166 5167 trips { 5168 thermal-engine-config { 5169 temperature = <125000>; 5170 hysteresis = <1000>; 5171 type = "passive"; 5172 }; 5173 5174 reset-mon-cfg { 5175 temperature = <115000>; 5176 hysteresis = <5000>; 5177 type = "passive"; 5178 }; 5179 }; 5180 }; 5181 }; 5182 5183 timer { 5184 compatible = "arm,armv8-timer"; 5185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5189 clock-frequency = <19200000>; 5190 }; 5191}; 5192