1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/interconnect/qcom,sm8450.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <76800000>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32000>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo780"; 52 reg = <0x0 0x0>; 53 enable-method = "psci"; 54 next-level-cache = <&L2_0>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 #cooling-cells = <2>; 59 clocks = <&cpufreq_hw 0>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo780"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_100>; 79 power-domains = <&CPU_PD1>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 clocks = <&cpufreq_hw 0>; 84 L2_100: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo780"; 95 reg = <0x0 0x200>; 96 enable-method = "psci"; 97 next-level-cache = <&L2_200>; 98 power-domains = <&CPU_PD2>; 99 power-domain-names = "psci"; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 #cooling-cells = <2>; 102 clocks = <&cpufreq_hw 0>; 103 L2_200: l2-cache { 104 compatible = "cache"; 105 cache-level = <2>; 106 cache-unified; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo780"; 114 reg = <0x0 0x300>; 115 enable-method = "psci"; 116 next-level-cache = <&L2_300>; 117 power-domains = <&CPU_PD3>; 118 power-domain-names = "psci"; 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 #cooling-cells = <2>; 121 clocks = <&cpufreq_hw 0>; 122 L2_300: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU4: cpu@400 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo780"; 133 reg = <0x0 0x400>; 134 enable-method = "psci"; 135 next-level-cache = <&L2_400>; 136 power-domains = <&CPU_PD4>; 137 power-domain-names = "psci"; 138 qcom,freq-domain = <&cpufreq_hw 1>; 139 #cooling-cells = <2>; 140 clocks = <&cpufreq_hw 1>; 141 L2_400: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-unified; 145 next-level-cache = <&L3_0>; 146 }; 147 }; 148 149 CPU5: cpu@500 { 150 device_type = "cpu"; 151 compatible = "qcom,kryo780"; 152 reg = <0x0 0x500>; 153 enable-method = "psci"; 154 next-level-cache = <&L2_500>; 155 power-domains = <&CPU_PD5>; 156 power-domain-names = "psci"; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 #cooling-cells = <2>; 159 clocks = <&cpufreq_hw 1>; 160 L2_500: l2-cache { 161 compatible = "cache"; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&L3_0>; 165 }; 166 }; 167 168 CPU6: cpu@600 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo780"; 171 reg = <0x0 0x600>; 172 enable-method = "psci"; 173 next-level-cache = <&L2_600>; 174 power-domains = <&CPU_PD6>; 175 power-domain-names = "psci"; 176 qcom,freq-domain = <&cpufreq_hw 1>; 177 #cooling-cells = <2>; 178 clocks = <&cpufreq_hw 1>; 179 L2_600: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 next-level-cache = <&L3_0>; 184 }; 185 }; 186 187 CPU7: cpu@700 { 188 device_type = "cpu"; 189 compatible = "qcom,kryo780"; 190 reg = <0x0 0x700>; 191 enable-method = "psci"; 192 next-level-cache = <&L2_700>; 193 power-domains = <&CPU_PD7>; 194 power-domain-names = "psci"; 195 qcom,freq-domain = <&cpufreq_hw 2>; 196 #cooling-cells = <2>; 197 clocks = <&cpufreq_hw 2>; 198 L2_700: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 cpu-map { 207 cluster0 { 208 core0 { 209 cpu = <&CPU0>; 210 }; 211 212 core1 { 213 cpu = <&CPU1>; 214 }; 215 216 core2 { 217 cpu = <&CPU2>; 218 }; 219 220 core3 { 221 cpu = <&CPU3>; 222 }; 223 224 core4 { 225 cpu = <&CPU4>; 226 }; 227 228 core5 { 229 cpu = <&CPU5>; 230 }; 231 232 core6 { 233 cpu = <&CPU6>; 234 }; 235 236 core7 { 237 cpu = <&CPU7>; 238 }; 239 }; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "silver-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <800>; 250 exit-latency-us = <750>; 251 min-residency-us = <4090>; 252 local-timer-stop; 253 }; 254 255 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "gold-rail-power-collapse"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <600>; 260 exit-latency-us = <1550>; 261 min-residency-us = <4791>; 262 local-timer-stop; 263 }; 264 }; 265 266 domain-idle-states { 267 CLUSTER_SLEEP_0: cluster-sleep-0 { 268 compatible = "domain-idle-state"; 269 arm,psci-suspend-param = <0x41000044>; 270 entry-latency-us = <1050>; 271 exit-latency-us = <2500>; 272 min-residency-us = <5309>; 273 }; 274 275 CLUSTER_SLEEP_1: cluster-sleep-1 { 276 compatible = "domain-idle-state"; 277 arm,psci-suspend-param = <0x4100c344>; 278 entry-latency-us = <2700>; 279 exit-latency-us = <3500>; 280 min-residency-us = <13959>; 281 }; 282 }; 283 }; 284 285 firmware { 286 scm: scm { 287 compatible = "qcom,scm-sm8450", "qcom,scm"; 288 qcom,dload-mode = <&tcsr 0x13000>; 289 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 290 #reset-cells = <1>; 291 }; 292 }; 293 294 clk_virt: interconnect-0 { 295 compatible = "qcom,sm8450-clk-virt"; 296 #interconnect-cells = <2>; 297 qcom,bcm-voters = <&apps_bcm_voter>; 298 }; 299 300 mc_virt: interconnect-1 { 301 compatible = "qcom,sm8450-mc-virt"; 302 #interconnect-cells = <2>; 303 qcom,bcm-voters = <&apps_bcm_voter>; 304 }; 305 306 memory@a0000000 { 307 device_type = "memory"; 308 /* We expect the bootloader to fill in the size */ 309 reg = <0x0 0xa0000000 0x0 0x0>; 310 }; 311 312 pmu { 313 compatible = "arm,armv8-pmuv3"; 314 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 315 }; 316 317 psci { 318 compatible = "arm,psci-1.0"; 319 method = "smc"; 320 321 CPU_PD0: power-domain-cpu0 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_PD>; 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD1: power-domain-cpu1 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_PD>; 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD2: power-domain-cpu2 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_PD>; 336 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 337 }; 338 339 CPU_PD3: power-domain-cpu3 { 340 #power-domain-cells = <0>; 341 power-domains = <&CLUSTER_PD>; 342 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 343 }; 344 345 CPU_PD4: power-domain-cpu4 { 346 #power-domain-cells = <0>; 347 power-domains = <&CLUSTER_PD>; 348 domain-idle-states = <&BIG_CPU_SLEEP_0>; 349 }; 350 351 CPU_PD5: power-domain-cpu5 { 352 #power-domain-cells = <0>; 353 power-domains = <&CLUSTER_PD>; 354 domain-idle-states = <&BIG_CPU_SLEEP_0>; 355 }; 356 357 CPU_PD6: power-domain-cpu6 { 358 #power-domain-cells = <0>; 359 power-domains = <&CLUSTER_PD>; 360 domain-idle-states = <&BIG_CPU_SLEEP_0>; 361 }; 362 363 CPU_PD7: power-domain-cpu7 { 364 #power-domain-cells = <0>; 365 power-domains = <&CLUSTER_PD>; 366 domain-idle-states = <&BIG_CPU_SLEEP_0>; 367 }; 368 369 CLUSTER_PD: power-domain-cpu-cluster0 { 370 #power-domain-cells = <0>; 371 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 372 }; 373 }; 374 375 qup_opp_table_100mhz: opp-table-qup { 376 compatible = "operating-points-v2"; 377 378 opp-50000000 { 379 opp-hz = /bits/ 64 <50000000>; 380 required-opps = <&rpmhpd_opp_min_svs>; 381 }; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-100000000 { 389 opp-hz = /bits/ 64 <100000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 }; 393 394 reserved_memory: reserved-memory { 395 #address-cells = <2>; 396 #size-cells = <2>; 397 ranges; 398 399 hyp_mem: memory@80000000 { 400 reg = <0x0 0x80000000 0x0 0x600000>; 401 no-map; 402 }; 403 404 xbl_dt_log_mem: memory@80600000 { 405 reg = <0x0 0x80600000 0x0 0x40000>; 406 no-map; 407 }; 408 409 xbl_ramdump_mem: memory@80640000 { 410 reg = <0x0 0x80640000 0x0 0x180000>; 411 no-map; 412 }; 413 414 xbl_sc_mem: memory@807c0000 { 415 reg = <0x0 0x807c0000 0x0 0x40000>; 416 no-map; 417 }; 418 419 aop_image_mem: memory@80800000 { 420 reg = <0x0 0x80800000 0x0 0x60000>; 421 no-map; 422 }; 423 424 aop_cmd_db_mem: memory@80860000 { 425 compatible = "qcom,cmd-db"; 426 reg = <0x0 0x80860000 0x0 0x20000>; 427 no-map; 428 }; 429 430 aop_config_mem: memory@80880000 { 431 reg = <0x0 0x80880000 0x0 0x20000>; 432 no-map; 433 }; 434 435 tme_crash_dump_mem: memory@808a0000 { 436 reg = <0x0 0x808a0000 0x0 0x40000>; 437 no-map; 438 }; 439 440 tme_log_mem: memory@808e0000 { 441 reg = <0x0 0x808e0000 0x0 0x4000>; 442 no-map; 443 }; 444 445 uefi_log_mem: memory@808e4000 { 446 reg = <0x0 0x808e4000 0x0 0x10000>; 447 no-map; 448 }; 449 450 /* secdata region can be reused by apps */ 451 smem: memory@80900000 { 452 compatible = "qcom,smem"; 453 reg = <0x0 0x80900000 0x0 0x200000>; 454 hwlocks = <&tcsr_mutex 3>; 455 no-map; 456 }; 457 458 cpucp_fw_mem: memory@80b00000 { 459 reg = <0x0 0x80b00000 0x0 0x100000>; 460 no-map; 461 }; 462 463 cdsp_secure_heap: memory@80c00000 { 464 reg = <0x0 0x80c00000 0x0 0x4600000>; 465 no-map; 466 }; 467 468 video_mem: memory@85700000 { 469 reg = <0x0 0x85700000 0x0 0x700000>; 470 no-map; 471 }; 472 473 adsp_mem: memory@85e00000 { 474 reg = <0x0 0x85e00000 0x0 0x2100000>; 475 no-map; 476 }; 477 478 slpi_mem: memory@88000000 { 479 reg = <0x0 0x88000000 0x0 0x1900000>; 480 no-map; 481 }; 482 483 cdsp_mem: memory@89900000 { 484 reg = <0x0 0x89900000 0x0 0x2000000>; 485 no-map; 486 }; 487 488 ipa_fw_mem: memory@8b900000 { 489 reg = <0x0 0x8b900000 0x0 0x10000>; 490 no-map; 491 }; 492 493 ipa_gsi_mem: memory@8b910000 { 494 reg = <0x0 0x8b910000 0x0 0xa000>; 495 no-map; 496 }; 497 498 gpu_micro_code_mem: memory@8b91a000 { 499 reg = <0x0 0x8b91a000 0x0 0x2000>; 500 no-map; 501 }; 502 503 spss_region_mem: memory@8ba00000 { 504 reg = <0x0 0x8ba00000 0x0 0x180000>; 505 no-map; 506 }; 507 508 /* First part of the "SPU secure shared memory" region */ 509 spu_tz_shared_mem: memory@8bb80000 { 510 reg = <0x0 0x8bb80000 0x0 0x60000>; 511 no-map; 512 }; 513 514 /* Second part of the "SPU secure shared memory" region */ 515 spu_modem_shared_mem: memory@8bbe0000 { 516 reg = <0x0 0x8bbe0000 0x0 0x20000>; 517 no-map; 518 }; 519 520 mpss_mem: memory@8bc00000 { 521 reg = <0x0 0x8bc00000 0x0 0x13200000>; 522 no-map; 523 }; 524 525 cvp_mem: memory@9ee00000 { 526 reg = <0x0 0x9ee00000 0x0 0x700000>; 527 no-map; 528 }; 529 530 camera_mem: memory@9f500000 { 531 reg = <0x0 0x9f500000 0x0 0x800000>; 532 no-map; 533 }; 534 535 rmtfs_mem: memory@9fd00000 { 536 compatible = "qcom,rmtfs-mem"; 537 reg = <0x0 0x9fd00000 0x0 0x280000>; 538 no-map; 539 540 qcom,client-id = <1>; 541 qcom,vmid = <15>; 542 }; 543 544 xbl_sc_mem2: memory@a6e00000 { 545 reg = <0x0 0xa6e00000 0x0 0x40000>; 546 no-map; 547 }; 548 549 global_sync_mem: memory@a6f00000 { 550 reg = <0x0 0xa6f00000 0x0 0x100000>; 551 no-map; 552 }; 553 554 /* uefi region can be reused by APPS */ 555 556 /* Linux kernel image is loaded at 0xa0000000 */ 557 558 oem_vm_mem: memory@bb000000 { 559 reg = <0x0 0xbb000000 0x0 0x5000000>; 560 no-map; 561 }; 562 563 mte_mem: memory@c0000000 { 564 reg = <0x0 0xc0000000 0x0 0x20000000>; 565 no-map; 566 }; 567 568 qheebsp_reserved_mem: memory@e0000000 { 569 reg = <0x0 0xe0000000 0x0 0x600000>; 570 no-map; 571 }; 572 573 cpusys_vm_mem: memory@e0600000 { 574 reg = <0x0 0xe0600000 0x0 0x400000>; 575 no-map; 576 }; 577 578 hyp_reserved_mem: memory@e0a00000 { 579 reg = <0x0 0xe0a00000 0x0 0x100000>; 580 no-map; 581 }; 582 583 trust_ui_vm_mem: memory@e0b00000 { 584 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 585 no-map; 586 }; 587 588 trust_ui_vm_qrtr: memory@e55f3000 { 589 reg = <0x0 0xe55f3000 0x0 0x9000>; 590 no-map; 591 }; 592 593 trust_ui_vm_vblk0_ring: memory@e55fc000 { 594 reg = <0x0 0xe55fc000 0x0 0x4000>; 595 no-map; 596 }; 597 598 trust_ui_vm_swiotlb: memory@e5600000 { 599 reg = <0x0 0xe5600000 0x0 0x100000>; 600 no-map; 601 }; 602 603 tz_stat_mem: memory@e8800000 { 604 reg = <0x0 0xe8800000 0x0 0x100000>; 605 no-map; 606 }; 607 608 tags_mem: memory@e8900000 { 609 reg = <0x0 0xe8900000 0x0 0x1200000>; 610 no-map; 611 }; 612 613 qtee_mem: memory@e9b00000 { 614 reg = <0x0 0xe9b00000 0x0 0x500000>; 615 no-map; 616 }; 617 618 trusted_apps_mem: memory@ea000000 { 619 reg = <0x0 0xea000000 0x0 0x3900000>; 620 no-map; 621 }; 622 623 trusted_apps_ext_mem: memory@ed900000 { 624 reg = <0x0 0xed900000 0x0 0x3b00000>; 625 no-map; 626 }; 627 }; 628 629 smp2p-adsp { 630 compatible = "qcom,smp2p"; 631 qcom,smem = <443>, <429>; 632 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 633 IPCC_MPROC_SIGNAL_SMP2P 634 IRQ_TYPE_EDGE_RISING>; 635 mboxes = <&ipcc IPCC_CLIENT_LPASS 636 IPCC_MPROC_SIGNAL_SMP2P>; 637 638 qcom,local-pid = <0>; 639 qcom,remote-pid = <2>; 640 641 smp2p_adsp_out: master-kernel { 642 qcom,entry-name = "master-kernel"; 643 #qcom,smem-state-cells = <1>; 644 }; 645 646 smp2p_adsp_in: slave-kernel { 647 qcom,entry-name = "slave-kernel"; 648 interrupt-controller; 649 #interrupt-cells = <2>; 650 }; 651 }; 652 653 smp2p-cdsp { 654 compatible = "qcom,smp2p"; 655 qcom,smem = <94>, <432>; 656 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 657 IPCC_MPROC_SIGNAL_SMP2P 658 IRQ_TYPE_EDGE_RISING>; 659 mboxes = <&ipcc IPCC_CLIENT_CDSP 660 IPCC_MPROC_SIGNAL_SMP2P>; 661 662 qcom,local-pid = <0>; 663 qcom,remote-pid = <5>; 664 665 smp2p_cdsp_out: master-kernel { 666 qcom,entry-name = "master-kernel"; 667 #qcom,smem-state-cells = <1>; 668 }; 669 670 smp2p_cdsp_in: slave-kernel { 671 qcom,entry-name = "slave-kernel"; 672 interrupt-controller; 673 #interrupt-cells = <2>; 674 }; 675 }; 676 677 smp2p-modem { 678 compatible = "qcom,smp2p"; 679 qcom,smem = <435>, <428>; 680 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 681 IPCC_MPROC_SIGNAL_SMP2P 682 IRQ_TYPE_EDGE_RISING>; 683 mboxes = <&ipcc IPCC_CLIENT_MPSS 684 IPCC_MPROC_SIGNAL_SMP2P>; 685 686 qcom,local-pid = <0>; 687 qcom,remote-pid = <1>; 688 689 smp2p_modem_out: master-kernel { 690 qcom,entry-name = "master-kernel"; 691 #qcom,smem-state-cells = <1>; 692 }; 693 694 smp2p_modem_in: slave-kernel { 695 qcom,entry-name = "slave-kernel"; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 700 ipa_smp2p_out: ipa-ap-to-modem { 701 qcom,entry-name = "ipa"; 702 #qcom,smem-state-cells = <1>; 703 }; 704 705 ipa_smp2p_in: ipa-modem-to-ap { 706 qcom,entry-name = "ipa"; 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 }; 710 }; 711 712 smp2p-slpi { 713 compatible = "qcom,smp2p"; 714 qcom,smem = <481>, <430>; 715 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 716 IPCC_MPROC_SIGNAL_SMP2P 717 IRQ_TYPE_EDGE_RISING>; 718 mboxes = <&ipcc IPCC_CLIENT_SLPI 719 IPCC_MPROC_SIGNAL_SMP2P>; 720 721 qcom,local-pid = <0>; 722 qcom,remote-pid = <3>; 723 724 smp2p_slpi_out: master-kernel { 725 qcom,entry-name = "master-kernel"; 726 #qcom,smem-state-cells = <1>; 727 }; 728 729 smp2p_slpi_in: slave-kernel { 730 qcom,entry-name = "slave-kernel"; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 }; 734 }; 735 736 soc: soc@0 { 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges = <0 0 0 0 0x10 0>; 740 dma-ranges = <0 0 0 0 0x10 0>; 741 compatible = "simple-bus"; 742 743 gcc: clock-controller@100000 { 744 compatible = "qcom,gcc-sm8450"; 745 reg = <0x0 0x00100000 0x0 0x1f4200>; 746 #clock-cells = <1>; 747 #reset-cells = <1>; 748 #power-domain-cells = <1>; 749 clocks = <&rpmhcc RPMH_CXO_CLK>, 750 <&sleep_clk>, 751 <&pcie0_lane>, 752 <&pcie1_lane>, 753 <0>, 754 <&ufs_mem_phy_lanes 0>, 755 <&ufs_mem_phy_lanes 1>, 756 <&ufs_mem_phy_lanes 2>, 757 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 758 clock-names = "bi_tcxo", 759 "sleep_clk", 760 "pcie_0_pipe_clk", 761 "pcie_1_pipe_clk", 762 "pcie_1_phy_aux_clk", 763 "ufs_phy_rx_symbol_0_clk", 764 "ufs_phy_rx_symbol_1_clk", 765 "ufs_phy_tx_symbol_0_clk", 766 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 767 }; 768 769 gpi_dma2: dma-controller@800000 { 770 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 771 #dma-cells = <3>; 772 reg = <0 0x00800000 0 0x60000>; 773 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 785 dma-channels = <12>; 786 dma-channel-mask = <0x7e>; 787 iommus = <&apps_smmu 0x496 0x0>; 788 status = "disabled"; 789 }; 790 791 qupv3_id_2: geniqup@8c0000 { 792 compatible = "qcom,geni-se-qup"; 793 reg = <0x0 0x008c0000 0x0 0x2000>; 794 clock-names = "m-ahb", "s-ahb"; 795 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 796 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 797 iommus = <&apps_smmu 0x483 0x0>; 798 #address-cells = <2>; 799 #size-cells = <2>; 800 ranges; 801 status = "disabled"; 802 803 i2c15: i2c@880000 { 804 compatible = "qcom,geni-i2c"; 805 reg = <0x0 0x00880000 0x0 0x4000>; 806 clock-names = "se"; 807 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&qup_i2c15_data_clk>; 810 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 814 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 815 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 816 interconnect-names = "qup-core", "qup-config", "qup-memory"; 817 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 818 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 819 dma-names = "tx", "rx"; 820 status = "disabled"; 821 }; 822 823 spi15: spi@880000 { 824 compatible = "qcom,geni-spi"; 825 reg = <0x0 0x00880000 0x0 0x4000>; 826 clock-names = "se"; 827 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 828 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 831 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 832 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 833 interconnect-names = "qup-core", "qup-config"; 834 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 835 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 836 dma-names = "tx", "rx"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 i2c16: i2c@884000 { 843 compatible = "qcom,geni-i2c"; 844 reg = <0x0 0x00884000 0x0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_i2c16_data_clk>; 849 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 853 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 854 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 855 interconnect-names = "qup-core", "qup-config", "qup-memory"; 856 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 857 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 858 dma-names = "tx", "rx"; 859 status = "disabled"; 860 }; 861 862 spi16: spi@884000 { 863 compatible = "qcom,geni-spi"; 864 reg = <0x0 0x00884000 0x0 0x4000>; 865 clock-names = "se"; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 867 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 872 interconnect-names = "qup-core", "qup-config"; 873 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 874 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 875 dma-names = "tx", "rx"; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 i2c17: i2c@888000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0x0 0x00888000 0x0 0x4000>; 884 clock-names = "se"; 885 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&qup_i2c17_data_clk>; 888 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 892 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 893 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 894 interconnect-names = "qup-core", "qup-config", "qup-memory"; 895 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 896 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 897 dma-names = "tx", "rx"; 898 status = "disabled"; 899 }; 900 901 spi17: spi@888000 { 902 compatible = "qcom,geni-spi"; 903 reg = <0x0 0x00888000 0x0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 906 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 910 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 911 interconnect-names = "qup-core", "qup-config"; 912 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 913 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 914 dma-names = "tx", "rx"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 920 i2c18: i2c@88c000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0x0 0x0088c000 0x0 0x4000>; 923 clock-names = "se"; 924 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_i2c18_data_clk>; 927 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 931 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 932 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 933 interconnect-names = "qup-core", "qup-config", "qup-memory"; 934 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 935 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 936 dma-names = "tx", "rx"; 937 status = "disabled"; 938 }; 939 940 spi18: spi@88c000 { 941 compatible = "qcom,geni-spi"; 942 reg = <0 0x0088c000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 945 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 948 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 949 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 950 interconnect-names = "qup-core", "qup-config"; 951 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 952 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 959 i2c19: i2c@890000 { 960 compatible = "qcom,geni-i2c"; 961 reg = <0x0 0x00890000 0x0 0x4000>; 962 clock-names = "se"; 963 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&qup_i2c19_data_clk>; 966 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 970 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 971 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 973 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 974 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 975 dma-names = "tx", "rx"; 976 status = "disabled"; 977 }; 978 979 spi19: spi@890000 { 980 compatible = "qcom,geni-spi"; 981 reg = <0 0x00890000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 984 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 989 interconnect-names = "qup-core", "qup-config"; 990 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 991 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 998 i2c20: i2c@894000 { 999 compatible = "qcom,geni-i2c"; 1000 reg = <0x0 0x00894000 0x0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c20_data_clk>; 1005 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1009 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1010 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1011 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1012 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1013 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1014 dma-names = "tx", "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 uart20: serial@894000 { 1019 compatible = "qcom,geni-uart"; 1020 reg = <0 0x00894000 0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&qup_uart20_default>; 1025 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1026 status = "disabled"; 1027 }; 1028 1029 spi20: spi@894000 { 1030 compatible = "qcom,geni-spi"; 1031 reg = <0 0x00894000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1034 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1038 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1039 interconnect-names = "qup-core", "qup-config"; 1040 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1041 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1042 dma-names = "tx", "rx"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 i2c21: i2c@898000 { 1049 compatible = "qcom,geni-i2c"; 1050 reg = <0x0 0x00898000 0x0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&qup_i2c21_data_clk>; 1055 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1059 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1060 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1061 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1062 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1063 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1064 dma-names = "tx", "rx"; 1065 status = "disabled"; 1066 }; 1067 1068 spi21: spi@898000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x00898000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1073 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1077 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1078 interconnect-names = "qup-core", "qup-config"; 1079 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1080 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1081 dma-names = "tx", "rx"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 }; 1087 1088 gpi_dma0: dma-controller@900000 { 1089 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1090 #dma-cells = <3>; 1091 reg = <0 0x00900000 0 0x60000>; 1092 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1104 dma-channels = <12>; 1105 dma-channel-mask = <0x7e>; 1106 iommus = <&apps_smmu 0x5b6 0x0>; 1107 status = "disabled"; 1108 }; 1109 1110 qupv3_id_0: geniqup@9c0000 { 1111 compatible = "qcom,geni-se-qup"; 1112 reg = <0x0 0x009c0000 0x0 0x2000>; 1113 clock-names = "m-ahb", "s-ahb"; 1114 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1115 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1116 iommus = <&apps_smmu 0x5a3 0x0>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1118 interconnect-names = "qup-core"; 1119 #address-cells = <2>; 1120 #size-cells = <2>; 1121 ranges; 1122 status = "disabled"; 1123 1124 i2c0: i2c@980000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0x0 0x00980000 0x0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_i2c0_data_clk>; 1131 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1135 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1136 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1137 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1138 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1139 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1140 dma-names = "tx", "rx"; 1141 status = "disabled"; 1142 }; 1143 1144 spi0: spi@980000 { 1145 compatible = "qcom,geni-spi"; 1146 reg = <0x0 0x00980000 0x0 0x4000>; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1150 pinctrl-names = "default"; 1151 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1152 power-domains = <&rpmhpd SM8450_CX>; 1153 operating-points-v2 = <&qup_opp_table_100mhz>; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1155 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1156 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1157 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1158 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1159 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1160 dma-names = "tx", "rx"; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 status = "disabled"; 1164 }; 1165 1166 i2c1: i2c@984000 { 1167 compatible = "qcom,geni-i2c"; 1168 reg = <0x0 0x00984000 0x0 0x4000>; 1169 clock-names = "se"; 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1171 pinctrl-names = "default"; 1172 pinctrl-0 = <&qup_i2c1_data_clk>; 1173 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1177 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1178 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1179 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1180 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1181 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1182 dma-names = "tx", "rx"; 1183 status = "disabled"; 1184 }; 1185 1186 spi1: spi@984000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0x0 0x00984000 0x0 0x4000>; 1189 clock-names = "se"; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1191 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1195 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1196 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1197 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1198 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1199 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1200 dma-names = "tx", "rx"; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c2: i2c@988000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0x0 0x00988000 0x0 0x4000>; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c2_data_clk>; 1213 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1218 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1219 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1220 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1221 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1222 dma-names = "tx", "rx"; 1223 status = "disabled"; 1224 }; 1225 1226 spi2: spi@988000 { 1227 compatible = "qcom,geni-spi"; 1228 reg = <0x0 0x00988000 0x0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1231 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1235 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1236 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1237 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1238 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1239 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1240 dma-names = "tx", "rx"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 1247 i2c3: i2c@98c000 { 1248 compatible = "qcom,geni-i2c"; 1249 reg = <0x0 0x0098c000 0x0 0x4000>; 1250 clock-names = "se"; 1251 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&qup_i2c3_data_clk>; 1254 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1258 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1259 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1260 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1261 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1262 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1263 dma-names = "tx", "rx"; 1264 status = "disabled"; 1265 }; 1266 1267 spi3: spi@98c000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0x0 0x0098c000 0x0 0x4000>; 1270 clock-names = "se"; 1271 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1272 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1275 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1276 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1277 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1278 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1279 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 i2c4: i2c@990000 { 1288 compatible = "qcom,geni-i2c"; 1289 reg = <0x0 0x00990000 0x0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_i2c4_data_clk>; 1294 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1299 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1300 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1301 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1302 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1303 dma-names = "tx", "rx"; 1304 status = "disabled"; 1305 }; 1306 1307 spi4: spi@990000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0x0 0x00990000 0x0 0x4000>; 1310 clock-names = "se"; 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1312 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1315 power-domains = <&rpmhpd SM8450_CX>; 1316 operating-points-v2 = <&qup_opp_table_100mhz>; 1317 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1318 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1319 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1320 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1321 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1322 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1323 dma-names = "tx", "rx"; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 status = "disabled"; 1327 }; 1328 1329 i2c5: i2c@994000 { 1330 compatible = "qcom,geni-i2c"; 1331 reg = <0x0 0x00994000 0x0 0x4000>; 1332 clock-names = "se"; 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1334 pinctrl-names = "default"; 1335 pinctrl-0 = <&qup_i2c5_data_clk>; 1336 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1340 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1341 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1342 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1343 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1344 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 status = "disabled"; 1347 }; 1348 1349 spi5: spi@994000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0x0 0x00994000 0x0 0x4000>; 1352 clock-names = "se"; 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1354 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1358 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1359 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1360 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1361 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1362 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1363 dma-names = "tx", "rx"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 1370 i2c6: i2c@998000 { 1371 compatible = "qcom,geni-i2c"; 1372 reg = <0x0 0x00998000 0x0 0x4000>; 1373 clock-names = "se"; 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_i2c6_data_clk>; 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1381 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1382 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1383 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1384 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1385 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1386 dma-names = "tx", "rx"; 1387 status = "disabled"; 1388 }; 1389 1390 spi6: spi@998000 { 1391 compatible = "qcom,geni-spi"; 1392 reg = <0x0 0x00998000 0x0 0x4000>; 1393 clock-names = "se"; 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1395 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1399 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1400 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1401 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1402 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1403 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1404 dma-names = "tx", "rx"; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 uart7: serial@99c000 { 1411 compatible = "qcom,geni-debug-uart"; 1412 reg = <0 0x0099c000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1417 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1418 status = "disabled"; 1419 }; 1420 }; 1421 1422 gpi_dma1: dma-controller@a00000 { 1423 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1424 #dma-cells = <3>; 1425 reg = <0 0x00a00000 0 0x60000>; 1426 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1438 dma-channels = <12>; 1439 dma-channel-mask = <0x7e>; 1440 iommus = <&apps_smmu 0x56 0x0>; 1441 status = "disabled"; 1442 }; 1443 1444 qupv3_id_1: geniqup@ac0000 { 1445 compatible = "qcom,geni-se-qup"; 1446 reg = <0x0 0x00ac0000 0x0 0x6000>; 1447 clock-names = "m-ahb", "s-ahb"; 1448 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1449 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1450 iommus = <&apps_smmu 0x43 0x0>; 1451 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1452 interconnect-names = "qup-core"; 1453 #address-cells = <2>; 1454 #size-cells = <2>; 1455 ranges; 1456 status = "disabled"; 1457 1458 i2c8: i2c@a80000 { 1459 compatible = "qcom,geni-i2c"; 1460 reg = <0x0 0x00a80000 0x0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c8_data_clk>; 1465 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1469 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1470 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1471 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1472 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1473 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1474 dma-names = "tx", "rx"; 1475 status = "disabled"; 1476 }; 1477 1478 spi8: spi@a80000 { 1479 compatible = "qcom,geni-spi"; 1480 reg = <0x0 0x00a80000 0x0 0x4000>; 1481 clock-names = "se"; 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1483 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1484 pinctrl-names = "default"; 1485 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1488 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1489 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1490 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1491 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1492 dma-names = "tx", "rx"; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 status = "disabled"; 1496 }; 1497 1498 i2c9: i2c@a84000 { 1499 compatible = "qcom,geni-i2c"; 1500 reg = <0x0 0x00a84000 0x0 0x4000>; 1501 clock-names = "se"; 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_i2c9_data_clk>; 1505 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1509 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1510 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1511 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1512 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1513 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1514 dma-names = "tx", "rx"; 1515 status = "disabled"; 1516 }; 1517 1518 spi9: spi@a84000 { 1519 compatible = "qcom,geni-spi"; 1520 reg = <0x0 0x00a84000 0x0 0x4000>; 1521 clock-names = "se"; 1522 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1523 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1524 pinctrl-names = "default"; 1525 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1527 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1528 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1529 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1530 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1531 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1532 dma-names = "tx", "rx"; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 status = "disabled"; 1536 }; 1537 1538 i2c10: i2c@a88000 { 1539 compatible = "qcom,geni-i2c"; 1540 reg = <0x0 0x00a88000 0x0 0x4000>; 1541 clock-names = "se"; 1542 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1543 pinctrl-names = "default"; 1544 pinctrl-0 = <&qup_i2c10_data_clk>; 1545 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1549 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1550 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1551 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1552 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1553 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1554 dma-names = "tx", "rx"; 1555 status = "disabled"; 1556 }; 1557 1558 spi10: spi@a88000 { 1559 compatible = "qcom,geni-spi"; 1560 reg = <0x0 0x00a88000 0x0 0x4000>; 1561 clock-names = "se"; 1562 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1563 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1566 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1567 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1568 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1569 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1570 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1571 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1572 dma-names = "tx", "rx"; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 status = "disabled"; 1576 }; 1577 1578 i2c11: i2c@a8c000 { 1579 compatible = "qcom,geni-i2c"; 1580 reg = <0x0 0x00a8c000 0x0 0x4000>; 1581 clock-names = "se"; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_i2c11_data_clk>; 1585 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1589 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1590 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1591 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1592 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1593 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1594 dma-names = "tx", "rx"; 1595 status = "disabled"; 1596 }; 1597 1598 spi11: spi@a8c000 { 1599 compatible = "qcom,geni-spi"; 1600 reg = <0x0 0x00a8c000 0x0 0x4000>; 1601 clock-names = "se"; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1603 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1604 pinctrl-names = "default"; 1605 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1606 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1607 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1608 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1609 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1610 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1611 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1612 dma-names = "tx", "rx"; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 status = "disabled"; 1616 }; 1617 1618 i2c12: i2c@a90000 { 1619 compatible = "qcom,geni-i2c"; 1620 reg = <0x0 0x00a90000 0x0 0x4000>; 1621 clock-names = "se"; 1622 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1623 pinctrl-names = "default"; 1624 pinctrl-0 = <&qup_i2c12_data_clk>; 1625 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1629 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1630 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1631 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1632 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1633 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1634 dma-names = "tx", "rx"; 1635 status = "disabled"; 1636 }; 1637 1638 spi12: spi@a90000 { 1639 compatible = "qcom,geni-spi"; 1640 reg = <0x0 0x00a90000 0x0 0x4000>; 1641 clock-names = "se"; 1642 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1643 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1644 pinctrl-names = "default"; 1645 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1646 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1647 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1648 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1649 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1650 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1651 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1652 dma-names = "tx", "rx"; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 status = "disabled"; 1656 }; 1657 1658 i2c13: i2c@a94000 { 1659 compatible = "qcom,geni-i2c"; 1660 reg = <0 0x00a94000 0 0x4000>; 1661 clock-names = "se"; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&qup_i2c13_data_clk>; 1665 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1666 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1667 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1668 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1669 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1670 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1671 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1672 dma-names = "tx", "rx"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 spi13: spi@a94000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0x0 0x00a94000 0x0 0x4000>; 1681 clock-names = "se"; 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1683 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1687 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1688 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1689 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1690 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1691 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1692 dma-names = "tx", "rx"; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 status = "disabled"; 1696 }; 1697 1698 i2c14: i2c@a98000 { 1699 compatible = "qcom,geni-i2c"; 1700 reg = <0 0x00a98000 0 0x4000>; 1701 clock-names = "se"; 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&qup_i2c14_data_clk>; 1705 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1706 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1707 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1708 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1709 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1710 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1711 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1712 dma-names = "tx", "rx"; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 status = "disabled"; 1716 }; 1717 1718 spi14: spi@a98000 { 1719 compatible = "qcom,geni-spi"; 1720 reg = <0x0 0x00a98000 0x0 0x4000>; 1721 clock-names = "se"; 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1723 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1724 pinctrl-names = "default"; 1725 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1727 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1728 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1729 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1730 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1731 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1732 dma-names = "tx", "rx"; 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 status = "disabled"; 1736 }; 1737 }; 1738 1739 pcie0: pci@1c00000 { 1740 compatible = "qcom,pcie-sm8450-pcie0"; 1741 reg = <0 0x01c00000 0 0x3000>, 1742 <0 0x60000000 0 0xf1d>, 1743 <0 0x60000f20 0 0xa8>, 1744 <0 0x60001000 0 0x1000>, 1745 <0 0x60100000 0 0x100000>; 1746 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1747 device_type = "pci"; 1748 linux,pci-domain = <0>; 1749 bus-range = <0x00 0xff>; 1750 num-lanes = <1>; 1751 1752 #address-cells = <3>; 1753 #size-cells = <2>; 1754 1755 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1756 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1757 1758 /* 1759 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1760 * Hence, the IDs are swapped. 1761 */ 1762 msi-map = <0x0 &gic_its 0x5981 0x1>, 1763 <0x100 &gic_its 0x5980 0x1>; 1764 msi-map-mask = <0xff00>; 1765 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1766 interrupt-names = "msi"; 1767 #interrupt-cells = <1>; 1768 interrupt-map-mask = <0 0 0 0x7>; 1769 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1770 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1771 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1772 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1773 1774 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1775 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1776 <&pcie0_lane>, 1777 <&rpmhcc RPMH_CXO_CLK>, 1778 <&gcc GCC_PCIE_0_AUX_CLK>, 1779 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1780 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1781 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1782 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1783 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1784 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1785 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1786 clock-names = "pipe", 1787 "pipe_mux", 1788 "phy_pipe", 1789 "ref", 1790 "aux", 1791 "cfg", 1792 "bus_master", 1793 "bus_slave", 1794 "slave_q2a", 1795 "ddrss_sf_tbu", 1796 "aggre0", 1797 "aggre1"; 1798 1799 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1800 <0x100 &apps_smmu 0x1c01 0x1>; 1801 1802 resets = <&gcc GCC_PCIE_0_BCR>; 1803 reset-names = "pci"; 1804 1805 power-domains = <&gcc PCIE_0_GDSC>; 1806 1807 phys = <&pcie0_lane>; 1808 phy-names = "pciephy"; 1809 1810 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1811 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1812 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&pcie0_default_state>; 1815 1816 status = "disabled"; 1817 }; 1818 1819 pcie0_phy: phy@1c06000 { 1820 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1821 reg = <0 0x01c06000 0 0x200>; 1822 #address-cells = <2>; 1823 #size-cells = <2>; 1824 ranges; 1825 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1826 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1827 <&gcc GCC_PCIE_0_CLKREF_EN>, 1828 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1829 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1830 1831 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1832 reset-names = "phy"; 1833 1834 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1835 assigned-clock-rates = <100000000>; 1836 1837 status = "disabled"; 1838 1839 pcie0_lane: phy@1c06200 { 1840 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1841 <0 0x01c07000 0 0x200>, /* rx */ 1842 <0 0x01c06200 0 0x200>, /* pcs */ 1843 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1844 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1845 clock-names = "pipe0"; 1846 1847 #clock-cells = <0>; 1848 #phy-cells = <0>; 1849 clock-output-names = "pcie_0_pipe_clk"; 1850 }; 1851 }; 1852 1853 pcie1: pci@1c08000 { 1854 compatible = "qcom,pcie-sm8450-pcie1"; 1855 reg = <0 0x01c08000 0 0x3000>, 1856 <0 0x40000000 0 0xf1d>, 1857 <0 0x40000f20 0 0xa8>, 1858 <0 0x40001000 0 0x1000>, 1859 <0 0x40100000 0 0x100000>; 1860 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1861 device_type = "pci"; 1862 linux,pci-domain = <1>; 1863 bus-range = <0x00 0xff>; 1864 num-lanes = <2>; 1865 1866 #address-cells = <3>; 1867 #size-cells = <2>; 1868 1869 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1870 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1871 1872 /* 1873 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1874 * Hence, the IDs are swapped. 1875 */ 1876 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1877 <0x100 &gic_its 0x5a00 0x1>; 1878 msi-map-mask = <0xff00>; 1879 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1880 interrupt-names = "msi"; 1881 #interrupt-cells = <1>; 1882 interrupt-map-mask = <0 0 0 0x7>; 1883 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1884 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1885 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1886 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1887 1888 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1889 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1890 <&pcie1_lane>, 1891 <&rpmhcc RPMH_CXO_CLK>, 1892 <&gcc GCC_PCIE_1_AUX_CLK>, 1893 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1894 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1895 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1896 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1897 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1898 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1899 clock-names = "pipe", 1900 "pipe_mux", 1901 "phy_pipe", 1902 "ref", 1903 "aux", 1904 "cfg", 1905 "bus_master", 1906 "bus_slave", 1907 "slave_q2a", 1908 "ddrss_sf_tbu", 1909 "aggre1"; 1910 1911 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1912 <0x100 &apps_smmu 0x1c81 0x1>; 1913 1914 resets = <&gcc GCC_PCIE_1_BCR>; 1915 reset-names = "pci"; 1916 1917 power-domains = <&gcc PCIE_1_GDSC>; 1918 1919 phys = <&pcie1_lane>; 1920 phy-names = "pciephy"; 1921 1922 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1923 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1924 1925 pinctrl-names = "default"; 1926 pinctrl-0 = <&pcie1_default_state>; 1927 1928 status = "disabled"; 1929 }; 1930 1931 pcie1_phy: phy@1c0f000 { 1932 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1933 reg = <0 0x01c0f000 0 0x200>; 1934 #address-cells = <2>; 1935 #size-cells = <2>; 1936 ranges; 1937 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1938 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1939 <&gcc GCC_PCIE_1_CLKREF_EN>, 1940 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1941 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1942 1943 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1944 reset-names = "phy"; 1945 1946 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1947 assigned-clock-rates = <100000000>; 1948 1949 status = "disabled"; 1950 1951 pcie1_lane: phy@1c0e000 { 1952 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1953 <0 0x01c0e200 0 0x300>, /* rx */ 1954 <0 0x01c0f200 0 0x200>, /* pcs */ 1955 <0 0x01c0e800 0 0x200>, /* tx */ 1956 <0 0x01c0ea00 0 0x300>, /* rx */ 1957 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1958 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1959 clock-names = "pipe0"; 1960 1961 #clock-cells = <0>; 1962 #phy-cells = <0>; 1963 clock-output-names = "pcie_1_pipe_clk"; 1964 }; 1965 }; 1966 1967 config_noc: interconnect@1500000 { 1968 compatible = "qcom,sm8450-config-noc"; 1969 reg = <0 0x01500000 0 0x1c000>; 1970 #interconnect-cells = <2>; 1971 qcom,bcm-voters = <&apps_bcm_voter>; 1972 }; 1973 1974 system_noc: interconnect@1680000 { 1975 compatible = "qcom,sm8450-system-noc"; 1976 reg = <0 0x01680000 0 0x1e200>; 1977 #interconnect-cells = <2>; 1978 qcom,bcm-voters = <&apps_bcm_voter>; 1979 }; 1980 1981 pcie_noc: interconnect@16c0000 { 1982 compatible = "qcom,sm8450-pcie-anoc"; 1983 reg = <0 0x016c0000 0 0xe280>; 1984 #interconnect-cells = <2>; 1985 qcom,bcm-voters = <&apps_bcm_voter>; 1986 }; 1987 1988 aggre1_noc: interconnect@16e0000 { 1989 compatible = "qcom,sm8450-aggre1-noc"; 1990 reg = <0 0x016e0000 0 0x1c080>; 1991 #interconnect-cells = <2>; 1992 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1993 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 aggre2_noc: interconnect@1700000 { 1998 compatible = "qcom,sm8450-aggre2-noc"; 1999 reg = <0 0x01700000 0 0x31080>; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2003 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2004 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2005 <&rpmhcc RPMH_IPA_CLK>; 2006 }; 2007 2008 mmss_noc: interconnect@1740000 { 2009 compatible = "qcom,sm8450-mmss-noc"; 2010 reg = <0 0x01740000 0 0x1f080>; 2011 #interconnect-cells = <2>; 2012 qcom,bcm-voters = <&apps_bcm_voter>; 2013 }; 2014 2015 tcsr_mutex: hwlock@1f40000 { 2016 compatible = "qcom,tcsr-mutex"; 2017 reg = <0x0 0x01f40000 0x0 0x40000>; 2018 #hwlock-cells = <1>; 2019 }; 2020 2021 tcsr: syscon@1fc0000 { 2022 compatible = "qcom,sm8450-tcsr", "syscon"; 2023 reg = <0x0 0x1fc0000 0x0 0x30000>; 2024 }; 2025 2026 usb_1_hsphy: phy@88e3000 { 2027 compatible = "qcom,sm8450-usb-hs-phy", 2028 "qcom,usb-snps-hs-7nm-phy"; 2029 reg = <0 0x088e3000 0 0x400>; 2030 status = "disabled"; 2031 #phy-cells = <0>; 2032 2033 clocks = <&rpmhcc RPMH_CXO_CLK>; 2034 clock-names = "ref"; 2035 2036 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2037 }; 2038 2039 usb_1_qmpphy: phy@88e8000 { 2040 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2041 reg = <0 0x088e8000 0 0x3000>; 2042 2043 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2044 <&rpmhcc RPMH_CXO_CLK>, 2045 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2046 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2047 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2048 2049 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2050 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2051 reset-names = "phy", "common"; 2052 2053 #clock-cells = <1>; 2054 #phy-cells = <1>; 2055 2056 status = "disabled"; 2057 2058 ports { 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 2062 port@0 { 2063 reg = <0>; 2064 2065 usb_1_qmpphy_out: endpoint { 2066 }; 2067 }; 2068 2069 port@1 { 2070 reg = <1>; 2071 2072 usb_1_qmpphy_usb_ss_in: endpoint { 2073 }; 2074 }; 2075 2076 port@2 { 2077 reg = <2>; 2078 2079 usb_1_qmpphy_dp_in: endpoint { 2080 }; 2081 }; 2082 }; 2083 }; 2084 2085 remoteproc_slpi: remoteproc@2400000 { 2086 compatible = "qcom,sm8450-slpi-pas"; 2087 reg = <0 0x02400000 0 0x4000>; 2088 2089 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2090 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2091 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2092 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2093 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2094 interrupt-names = "wdog", "fatal", "ready", 2095 "handover", "stop-ack"; 2096 2097 clocks = <&rpmhcc RPMH_CXO_CLK>; 2098 clock-names = "xo"; 2099 2100 power-domains = <&rpmhpd SM8450_LCX>, 2101 <&rpmhpd SM8450_LMX>; 2102 power-domain-names = "lcx", "lmx"; 2103 2104 memory-region = <&slpi_mem>; 2105 2106 qcom,qmp = <&aoss_qmp>; 2107 2108 qcom,smem-states = <&smp2p_slpi_out 0>; 2109 qcom,smem-state-names = "stop"; 2110 2111 status = "disabled"; 2112 2113 glink-edge { 2114 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2115 IPCC_MPROC_SIGNAL_GLINK_QMP 2116 IRQ_TYPE_EDGE_RISING>; 2117 mboxes = <&ipcc IPCC_CLIENT_SLPI 2118 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2119 2120 label = "slpi"; 2121 qcom,remote-pid = <3>; 2122 2123 fastrpc { 2124 compatible = "qcom,fastrpc"; 2125 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2126 label = "sdsp"; 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 2130 compute-cb@1 { 2131 compatible = "qcom,fastrpc-compute-cb"; 2132 reg = <1>; 2133 iommus = <&apps_smmu 0x0541 0x0>; 2134 }; 2135 2136 compute-cb@2 { 2137 compatible = "qcom,fastrpc-compute-cb"; 2138 reg = <2>; 2139 iommus = <&apps_smmu 0x0542 0x0>; 2140 }; 2141 2142 compute-cb@3 { 2143 compatible = "qcom,fastrpc-compute-cb"; 2144 reg = <3>; 2145 iommus = <&apps_smmu 0x0543 0x0>; 2146 /* note: shared-cb = <4> in downstream */ 2147 }; 2148 }; 2149 }; 2150 }; 2151 2152 wsa2macro: codec@31e0000 { 2153 compatible = "qcom,sm8450-lpass-wsa-macro"; 2154 reg = <0 0x031e0000 0 0x1000>; 2155 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2156 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2157 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2158 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2159 <&vamacro>; 2160 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2161 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2162 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2163 assigned-clock-rates = <19200000>, <19200000>; 2164 2165 #clock-cells = <0>; 2166 clock-output-names = "wsa2-mclk"; 2167 pinctrl-names = "default"; 2168 pinctrl-0 = <&wsa2_swr_active>; 2169 #sound-dai-cells = <1>; 2170 }; 2171 2172 swr4: soundwire-controller@31f0000 { 2173 compatible = "qcom,soundwire-v1.7.0"; 2174 reg = <0 0x031f0000 0 0x2000>; 2175 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2176 clocks = <&wsa2macro>; 2177 clock-names = "iface"; 2178 label = "WSA2"; 2179 2180 qcom,din-ports = <2>; 2181 qcom,dout-ports = <6>; 2182 2183 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2184 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2185 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2186 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2187 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2188 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2189 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2190 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2191 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2192 2193 #address-cells = <2>; 2194 #size-cells = <0>; 2195 #sound-dai-cells = <1>; 2196 status = "disabled"; 2197 }; 2198 2199 rxmacro: codec@3200000 { 2200 compatible = "qcom,sm8450-lpass-rx-macro"; 2201 reg = <0 0x03200000 0 0x1000>; 2202 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2203 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2204 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2205 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2206 <&vamacro>; 2207 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2208 2209 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2210 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2211 assigned-clock-rates = <19200000>, <19200000>; 2212 2213 #clock-cells = <0>; 2214 clock-output-names = "mclk"; 2215 pinctrl-names = "default"; 2216 pinctrl-0 = <&rx_swr_active>; 2217 #sound-dai-cells = <1>; 2218 }; 2219 2220 swr1: soundwire-controller@3210000 { 2221 compatible = "qcom,soundwire-v1.7.0"; 2222 reg = <0 0x03210000 0 0x2000>; 2223 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2224 clocks = <&rxmacro>; 2225 clock-names = "iface"; 2226 label = "RX"; 2227 qcom,din-ports = <0>; 2228 qcom,dout-ports = <5>; 2229 2230 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2231 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2232 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2233 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2234 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2235 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2236 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2237 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2238 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2239 2240 #address-cells = <2>; 2241 #size-cells = <0>; 2242 #sound-dai-cells = <1>; 2243 status = "disabled"; 2244 }; 2245 2246 txmacro: codec@3220000 { 2247 compatible = "qcom,sm8450-lpass-tx-macro"; 2248 reg = <0 0x03220000 0 0x1000>; 2249 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2250 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2251 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2252 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2253 <&vamacro>; 2254 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2255 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2256 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2257 assigned-clock-rates = <19200000>, <19200000>; 2258 2259 #clock-cells = <0>; 2260 clock-output-names = "mclk"; 2261 pinctrl-names = "default"; 2262 pinctrl-0 = <&tx_swr_active>; 2263 #sound-dai-cells = <1>; 2264 }; 2265 2266 wsamacro: codec@3240000 { 2267 compatible = "qcom,sm8450-lpass-wsa-macro"; 2268 reg = <0 0x03240000 0 0x1000>; 2269 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2270 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2271 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2272 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2273 <&vamacro>; 2274 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2275 2276 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2277 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2278 assigned-clock-rates = <19200000>, <19200000>; 2279 2280 #clock-cells = <0>; 2281 clock-output-names = "mclk"; 2282 pinctrl-names = "default"; 2283 pinctrl-0 = <&wsa_swr_active>; 2284 #sound-dai-cells = <1>; 2285 }; 2286 2287 swr0: soundwire-controller@3250000 { 2288 compatible = "qcom,soundwire-v1.7.0"; 2289 reg = <0 0x03250000 0 0x2000>; 2290 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2291 clocks = <&wsamacro>; 2292 clock-names = "iface"; 2293 label = "WSA"; 2294 2295 qcom,din-ports = <2>; 2296 qcom,dout-ports = <6>; 2297 2298 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2299 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2300 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2301 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2302 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2303 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2304 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2305 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2306 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2307 2308 #address-cells = <2>; 2309 #size-cells = <0>; 2310 #sound-dai-cells = <1>; 2311 status = "disabled"; 2312 }; 2313 2314 swr2: soundwire-controller@33b0000 { 2315 compatible = "qcom,soundwire-v1.7.0"; 2316 reg = <0 0x033b0000 0 0x2000>; 2317 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2319 interrupt-names = "core", "wakeup"; 2320 2321 clocks = <&vamacro>; 2322 clock-names = "iface"; 2323 label = "TX"; 2324 2325 qcom,din-ports = <4>; 2326 qcom,dout-ports = <0>; 2327 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2328 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2329 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2330 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2331 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2332 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2333 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2334 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2335 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2336 2337 #address-cells = <2>; 2338 #size-cells = <0>; 2339 #sound-dai-cells = <1>; 2340 status = "disabled"; 2341 }; 2342 2343 vamacro: codec@33f0000 { 2344 compatible = "qcom,sm8450-lpass-va-macro"; 2345 reg = <0 0x033f0000 0 0x1000>; 2346 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2347 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2348 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2349 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2350 clock-names = "mclk", "macro", "dcodec", "npl"; 2351 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2352 assigned-clock-rates = <19200000>; 2353 2354 #clock-cells = <0>; 2355 clock-output-names = "fsgen"; 2356 #sound-dai-cells = <1>; 2357 status = "disabled"; 2358 }; 2359 2360 remoteproc_adsp: remoteproc@30000000 { 2361 compatible = "qcom,sm8450-adsp-pas"; 2362 reg = <0 0x30000000 0 0x100>; 2363 2364 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2365 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2366 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2367 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2368 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2369 interrupt-names = "wdog", "fatal", "ready", 2370 "handover", "stop-ack"; 2371 2372 clocks = <&rpmhcc RPMH_CXO_CLK>; 2373 clock-names = "xo"; 2374 2375 power-domains = <&rpmhpd SM8450_LCX>, 2376 <&rpmhpd SM8450_LMX>; 2377 power-domain-names = "lcx", "lmx"; 2378 2379 memory-region = <&adsp_mem>; 2380 2381 qcom,qmp = <&aoss_qmp>; 2382 2383 qcom,smem-states = <&smp2p_adsp_out 0>; 2384 qcom,smem-state-names = "stop"; 2385 2386 status = "disabled"; 2387 2388 remoteproc_adsp_glink: glink-edge { 2389 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2390 IPCC_MPROC_SIGNAL_GLINK_QMP 2391 IRQ_TYPE_EDGE_RISING>; 2392 mboxes = <&ipcc IPCC_CLIENT_LPASS 2393 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2394 2395 label = "lpass"; 2396 qcom,remote-pid = <2>; 2397 2398 gpr { 2399 compatible = "qcom,gpr"; 2400 qcom,glink-channels = "adsp_apps"; 2401 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2402 qcom,intents = <512 20>; 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 q6apm: service@1 { 2407 compatible = "qcom,q6apm"; 2408 reg = <GPR_APM_MODULE_IID>; 2409 #sound-dai-cells = <0>; 2410 qcom,protection-domain = "avs/audio", 2411 "msm/adsp/audio_pd"; 2412 2413 q6apmdai: dais { 2414 compatible = "qcom,q6apm-dais"; 2415 iommus = <&apps_smmu 0x1801 0x0>; 2416 }; 2417 2418 q6apmbedai: bedais { 2419 compatible = "qcom,q6apm-lpass-dais"; 2420 #sound-dai-cells = <1>; 2421 }; 2422 }; 2423 2424 q6prm: service@2 { 2425 compatible = "qcom,q6prm"; 2426 reg = <GPR_PRM_MODULE_IID>; 2427 qcom,protection-domain = "avs/audio", 2428 "msm/adsp/audio_pd"; 2429 2430 q6prmcc: clock-controller { 2431 compatible = "qcom,q6prm-lpass-clocks"; 2432 #clock-cells = <2>; 2433 }; 2434 }; 2435 }; 2436 2437 fastrpc { 2438 compatible = "qcom,fastrpc"; 2439 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2440 label = "adsp"; 2441 #address-cells = <1>; 2442 #size-cells = <0>; 2443 2444 compute-cb@3 { 2445 compatible = "qcom,fastrpc-compute-cb"; 2446 reg = <3>; 2447 iommus = <&apps_smmu 0x1803 0x0>; 2448 }; 2449 2450 compute-cb@4 { 2451 compatible = "qcom,fastrpc-compute-cb"; 2452 reg = <4>; 2453 iommus = <&apps_smmu 0x1804 0x0>; 2454 }; 2455 2456 compute-cb@5 { 2457 compatible = "qcom,fastrpc-compute-cb"; 2458 reg = <5>; 2459 iommus = <&apps_smmu 0x1805 0x0>; 2460 }; 2461 }; 2462 }; 2463 }; 2464 2465 remoteproc_cdsp: remoteproc@32300000 { 2466 compatible = "qcom,sm8450-cdsp-pas"; 2467 reg = <0 0x32300000 0 0x1400000>; 2468 2469 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2470 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2471 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2472 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2473 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2474 interrupt-names = "wdog", "fatal", "ready", 2475 "handover", "stop-ack"; 2476 2477 clocks = <&rpmhcc RPMH_CXO_CLK>; 2478 clock-names = "xo"; 2479 2480 power-domains = <&rpmhpd SM8450_CX>, 2481 <&rpmhpd SM8450_MXC>; 2482 power-domain-names = "cx", "mxc"; 2483 2484 memory-region = <&cdsp_mem>; 2485 2486 qcom,qmp = <&aoss_qmp>; 2487 2488 qcom,smem-states = <&smp2p_cdsp_out 0>; 2489 qcom,smem-state-names = "stop"; 2490 2491 status = "disabled"; 2492 2493 glink-edge { 2494 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2495 IPCC_MPROC_SIGNAL_GLINK_QMP 2496 IRQ_TYPE_EDGE_RISING>; 2497 mboxes = <&ipcc IPCC_CLIENT_CDSP 2498 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2499 2500 label = "cdsp"; 2501 qcom,remote-pid = <5>; 2502 2503 fastrpc { 2504 compatible = "qcom,fastrpc"; 2505 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2506 label = "cdsp"; 2507 #address-cells = <1>; 2508 #size-cells = <0>; 2509 2510 compute-cb@1 { 2511 compatible = "qcom,fastrpc-compute-cb"; 2512 reg = <1>; 2513 iommus = <&apps_smmu 0x2161 0x0400>, 2514 <&apps_smmu 0x1021 0x1420>; 2515 }; 2516 2517 compute-cb@2 { 2518 compatible = "qcom,fastrpc-compute-cb"; 2519 reg = <2>; 2520 iommus = <&apps_smmu 0x2162 0x0400>, 2521 <&apps_smmu 0x1022 0x1420>; 2522 }; 2523 2524 compute-cb@3 { 2525 compatible = "qcom,fastrpc-compute-cb"; 2526 reg = <3>; 2527 iommus = <&apps_smmu 0x2163 0x0400>, 2528 <&apps_smmu 0x1023 0x1420>; 2529 }; 2530 2531 compute-cb@4 { 2532 compatible = "qcom,fastrpc-compute-cb"; 2533 reg = <4>; 2534 iommus = <&apps_smmu 0x2164 0x0400>, 2535 <&apps_smmu 0x1024 0x1420>; 2536 }; 2537 2538 compute-cb@5 { 2539 compatible = "qcom,fastrpc-compute-cb"; 2540 reg = <5>; 2541 iommus = <&apps_smmu 0x2165 0x0400>, 2542 <&apps_smmu 0x1025 0x1420>; 2543 }; 2544 2545 compute-cb@6 { 2546 compatible = "qcom,fastrpc-compute-cb"; 2547 reg = <6>; 2548 iommus = <&apps_smmu 0x2166 0x0400>, 2549 <&apps_smmu 0x1026 0x1420>; 2550 }; 2551 2552 compute-cb@7 { 2553 compatible = "qcom,fastrpc-compute-cb"; 2554 reg = <7>; 2555 iommus = <&apps_smmu 0x2167 0x0400>, 2556 <&apps_smmu 0x1027 0x1420>; 2557 }; 2558 2559 compute-cb@8 { 2560 compatible = "qcom,fastrpc-compute-cb"; 2561 reg = <8>; 2562 iommus = <&apps_smmu 0x2168 0x0400>, 2563 <&apps_smmu 0x1028 0x1420>; 2564 }; 2565 2566 /* note: secure cb9 in downstream */ 2567 }; 2568 }; 2569 }; 2570 2571 remoteproc_mpss: remoteproc@4080000 { 2572 compatible = "qcom,sm8450-mpss-pas"; 2573 reg = <0x0 0x04080000 0x0 0x4040>; 2574 2575 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2576 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2577 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2578 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2579 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2580 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2581 interrupt-names = "wdog", "fatal", "ready", "handover", 2582 "stop-ack", "shutdown-ack"; 2583 2584 clocks = <&rpmhcc RPMH_CXO_CLK>; 2585 clock-names = "xo"; 2586 2587 power-domains = <&rpmhpd SM8450_CX>, 2588 <&rpmhpd SM8450_MSS>; 2589 power-domain-names = "cx", "mss"; 2590 2591 memory-region = <&mpss_mem>; 2592 2593 qcom,qmp = <&aoss_qmp>; 2594 2595 qcom,smem-states = <&smp2p_modem_out 0>; 2596 qcom,smem-state-names = "stop"; 2597 2598 status = "disabled"; 2599 2600 glink-edge { 2601 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2602 IPCC_MPROC_SIGNAL_GLINK_QMP 2603 IRQ_TYPE_EDGE_RISING>; 2604 mboxes = <&ipcc IPCC_CLIENT_MPSS 2605 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2606 label = "modem"; 2607 qcom,remote-pid = <1>; 2608 }; 2609 }; 2610 2611 videocc: clock-controller@aaf0000 { 2612 compatible = "qcom,sm8450-videocc"; 2613 reg = <0 0x0aaf0000 0 0x10000>; 2614 clocks = <&rpmhcc RPMH_CXO_CLK>, 2615 <&gcc GCC_VIDEO_AHB_CLK>; 2616 power-domains = <&rpmhpd SM8450_MMCX>; 2617 required-opps = <&rpmhpd_opp_low_svs>; 2618 #clock-cells = <1>; 2619 #reset-cells = <1>; 2620 #power-domain-cells = <1>; 2621 }; 2622 2623 cci0: cci@ac15000 { 2624 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2625 reg = <0 0x0ac15000 0 0x1000>; 2626 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2627 power-domains = <&camcc TITAN_TOP_GDSC>; 2628 2629 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2630 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2631 <&camcc CAM_CC_CPAS_AHB_CLK>, 2632 <&camcc CAM_CC_CCI_0_CLK>, 2633 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2634 clock-names = "camnoc_axi", 2635 "slow_ahb_src", 2636 "cpas_ahb", 2637 "cci", 2638 "cci_src"; 2639 pinctrl-0 = <&cci0_default &cci1_default>; 2640 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2641 pinctrl-names = "default", "sleep"; 2642 2643 status = "disabled"; 2644 #address-cells = <1>; 2645 #size-cells = <0>; 2646 2647 cci0_i2c0: i2c-bus@0 { 2648 reg = <0>; 2649 clock-frequency = <1000000>; 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 }; 2653 2654 cci0_i2c1: i2c-bus@1 { 2655 reg = <1>; 2656 clock-frequency = <1000000>; 2657 #address-cells = <1>; 2658 #size-cells = <0>; 2659 }; 2660 }; 2661 2662 cci1: cci@ac16000 { 2663 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2664 reg = <0 0x0ac16000 0 0x1000>; 2665 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2666 power-domains = <&camcc TITAN_TOP_GDSC>; 2667 2668 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2669 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2670 <&camcc CAM_CC_CPAS_AHB_CLK>, 2671 <&camcc CAM_CC_CCI_1_CLK>, 2672 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2673 clock-names = "camnoc_axi", 2674 "slow_ahb_src", 2675 "cpas_ahb", 2676 "cci", 2677 "cci_src"; 2678 pinctrl-0 = <&cci2_default &cci3_default>; 2679 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2680 pinctrl-names = "default", "sleep"; 2681 2682 status = "disabled"; 2683 #address-cells = <1>; 2684 #size-cells = <0>; 2685 2686 cci1_i2c0: i2c-bus@0 { 2687 reg = <0>; 2688 clock-frequency = <1000000>; 2689 #address-cells = <1>; 2690 #size-cells = <0>; 2691 }; 2692 2693 cci1_i2c1: i2c-bus@1 { 2694 reg = <1>; 2695 clock-frequency = <1000000>; 2696 #address-cells = <1>; 2697 #size-cells = <0>; 2698 }; 2699 }; 2700 2701 camcc: clock-controller@ade0000 { 2702 compatible = "qcom,sm8450-camcc"; 2703 reg = <0 0x0ade0000 0 0x20000>; 2704 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2705 <&rpmhcc RPMH_CXO_CLK>, 2706 <&rpmhcc RPMH_CXO_CLK_A>, 2707 <&sleep_clk>; 2708 power-domains = <&rpmhpd SM8450_MMCX>; 2709 required-opps = <&rpmhpd_opp_low_svs>; 2710 #clock-cells = <1>; 2711 #reset-cells = <1>; 2712 #power-domain-cells = <1>; 2713 status = "disabled"; 2714 }; 2715 2716 mdss: display-subsystem@ae00000 { 2717 compatible = "qcom,sm8450-mdss"; 2718 reg = <0 0x0ae00000 0 0x1000>; 2719 reg-names = "mdss"; 2720 2721 /* same path used twice */ 2722 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2723 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; 2724 interconnect-names = "mdp0-mem", "mdp1-mem"; 2725 2726 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2727 2728 power-domains = <&dispcc MDSS_GDSC>; 2729 2730 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2731 <&gcc GCC_DISP_HF_AXI_CLK>, 2732 <&gcc GCC_DISP_SF_AXI_CLK>, 2733 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2734 2735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2736 interrupt-controller; 2737 #interrupt-cells = <1>; 2738 2739 iommus = <&apps_smmu 0x2800 0x402>; 2740 2741 #address-cells = <2>; 2742 #size-cells = <2>; 2743 ranges; 2744 2745 status = "disabled"; 2746 2747 mdss_mdp: display-controller@ae01000 { 2748 compatible = "qcom,sm8450-dpu"; 2749 reg = <0 0x0ae01000 0 0x8f000>, 2750 <0 0x0aeb0000 0 0x2008>; 2751 reg-names = "mdp", "vbif"; 2752 2753 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2754 <&gcc GCC_DISP_SF_AXI_CLK>, 2755 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2756 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2757 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2758 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2759 clock-names = "bus", 2760 "nrt_bus", 2761 "iface", 2762 "lut", 2763 "core", 2764 "vsync"; 2765 2766 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2767 assigned-clock-rates = <19200000>; 2768 2769 operating-points-v2 = <&mdp_opp_table>; 2770 power-domains = <&rpmhpd SM8450_MMCX>; 2771 2772 interrupt-parent = <&mdss>; 2773 interrupts = <0>; 2774 2775 ports { 2776 #address-cells = <1>; 2777 #size-cells = <0>; 2778 2779 port@0 { 2780 reg = <0>; 2781 dpu_intf1_out: endpoint { 2782 remote-endpoint = <&mdss_dsi0_in>; 2783 }; 2784 }; 2785 2786 port@1 { 2787 reg = <1>; 2788 dpu_intf2_out: endpoint { 2789 remote-endpoint = <&mdss_dsi1_in>; 2790 }; 2791 }; 2792 2793 port@2 { 2794 reg = <2>; 2795 dpu_intf0_out: endpoint { 2796 remote-endpoint = <&mdss_dp0_in>; 2797 }; 2798 }; 2799 }; 2800 2801 mdp_opp_table: opp-table { 2802 compatible = "operating-points-v2"; 2803 2804 opp-172000000 { 2805 opp-hz = /bits/ 64 <172000000>; 2806 required-opps = <&rpmhpd_opp_low_svs_d1>; 2807 }; 2808 2809 opp-200000000 { 2810 opp-hz = /bits/ 64 <200000000>; 2811 required-opps = <&rpmhpd_opp_low_svs>; 2812 }; 2813 2814 opp-325000000 { 2815 opp-hz = /bits/ 64 <325000000>; 2816 required-opps = <&rpmhpd_opp_svs>; 2817 }; 2818 2819 opp-375000000 { 2820 opp-hz = /bits/ 64 <375000000>; 2821 required-opps = <&rpmhpd_opp_svs_l1>; 2822 }; 2823 2824 opp-500000000 { 2825 opp-hz = /bits/ 64 <500000000>; 2826 required-opps = <&rpmhpd_opp_nom>; 2827 }; 2828 }; 2829 }; 2830 2831 mdss_dp0: displayport-controller@ae90000 { 2832 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2833 reg = <0 0xae90000 0 0x200>, 2834 <0 0xae90200 0 0x200>, 2835 <0 0xae90400 0 0xc00>, 2836 <0 0xae91000 0 0x400>, 2837 <0 0xae91400 0 0x400>; 2838 interrupt-parent = <&mdss>; 2839 interrupts = <12>; 2840 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2841 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2842 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2843 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2844 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2845 clock-names = "core_iface", 2846 "core_aux", 2847 "ctrl_link", 2848 "ctrl_link_iface", 2849 "stream_pixel"; 2850 2851 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2852 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2853 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2854 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2855 2856 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2857 phy-names = "dp"; 2858 2859 #sound-dai-cells = <0>; 2860 2861 operating-points-v2 = <&dp_opp_table>; 2862 power-domains = <&rpmhpd SM8450_MMCX>; 2863 2864 status = "disabled"; 2865 2866 ports { 2867 #address-cells = <1>; 2868 #size-cells = <0>; 2869 2870 port@0 { 2871 reg = <0>; 2872 mdss_dp0_in: endpoint { 2873 remote-endpoint = <&dpu_intf0_out>; 2874 }; 2875 }; 2876 }; 2877 2878 dp_opp_table: opp-table { 2879 compatible = "operating-points-v2"; 2880 2881 opp-160000000 { 2882 opp-hz = /bits/ 64 <160000000>; 2883 required-opps = <&rpmhpd_opp_low_svs>; 2884 }; 2885 2886 opp-270000000 { 2887 opp-hz = /bits/ 64 <270000000>; 2888 required-opps = <&rpmhpd_opp_svs>; 2889 }; 2890 2891 opp-540000000 { 2892 opp-hz = /bits/ 64 <540000000>; 2893 required-opps = <&rpmhpd_opp_svs_l1>; 2894 }; 2895 2896 opp-810000000 { 2897 opp-hz = /bits/ 64 <810000000>; 2898 required-opps = <&rpmhpd_opp_nom>; 2899 }; 2900 }; 2901 }; 2902 2903 mdss_dsi0: dsi@ae94000 { 2904 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2905 reg = <0 0x0ae94000 0 0x400>; 2906 reg-names = "dsi_ctrl"; 2907 2908 interrupt-parent = <&mdss>; 2909 interrupts = <4>; 2910 2911 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2912 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2913 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2914 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2915 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2916 <&gcc GCC_DISP_HF_AXI_CLK>; 2917 clock-names = "byte", 2918 "byte_intf", 2919 "pixel", 2920 "core", 2921 "iface", 2922 "bus"; 2923 2924 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2925 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2926 2927 operating-points-v2 = <&mdss_dsi_opp_table>; 2928 power-domains = <&rpmhpd SM8450_MMCX>; 2929 2930 phys = <&mdss_dsi0_phy>; 2931 phy-names = "dsi"; 2932 2933 #address-cells = <1>; 2934 #size-cells = <0>; 2935 2936 status = "disabled"; 2937 2938 ports { 2939 #address-cells = <1>; 2940 #size-cells = <0>; 2941 2942 port@0 { 2943 reg = <0>; 2944 mdss_dsi0_in: endpoint { 2945 remote-endpoint = <&dpu_intf1_out>; 2946 }; 2947 }; 2948 2949 port@1 { 2950 reg = <1>; 2951 mdss_dsi0_out: endpoint { 2952 }; 2953 }; 2954 }; 2955 2956 mdss_dsi_opp_table: opp-table { 2957 compatible = "operating-points-v2"; 2958 2959 opp-187500000 { 2960 opp-hz = /bits/ 64 <187500000>; 2961 required-opps = <&rpmhpd_opp_low_svs>; 2962 }; 2963 2964 opp-300000000 { 2965 opp-hz = /bits/ 64 <300000000>; 2966 required-opps = <&rpmhpd_opp_svs>; 2967 }; 2968 2969 opp-358000000 { 2970 opp-hz = /bits/ 64 <358000000>; 2971 required-opps = <&rpmhpd_opp_svs_l1>; 2972 }; 2973 }; 2974 }; 2975 2976 mdss_dsi0_phy: phy@ae94400 { 2977 compatible = "qcom,sm8450-dsi-phy-5nm"; 2978 reg = <0 0x0ae94400 0 0x200>, 2979 <0 0x0ae94600 0 0x280>, 2980 <0 0x0ae94900 0 0x260>; 2981 reg-names = "dsi_phy", 2982 "dsi_phy_lane", 2983 "dsi_pll"; 2984 2985 #clock-cells = <1>; 2986 #phy-cells = <0>; 2987 2988 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2989 <&rpmhcc RPMH_CXO_CLK>; 2990 clock-names = "iface", "ref"; 2991 2992 status = "disabled"; 2993 }; 2994 2995 mdss_dsi1: dsi@ae96000 { 2996 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2997 reg = <0 0x0ae96000 0 0x400>; 2998 reg-names = "dsi_ctrl"; 2999 3000 interrupt-parent = <&mdss>; 3001 interrupts = <5>; 3002 3003 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3004 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3005 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3006 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3007 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3008 <&gcc GCC_DISP_HF_AXI_CLK>; 3009 clock-names = "byte", 3010 "byte_intf", 3011 "pixel", 3012 "core", 3013 "iface", 3014 "bus"; 3015 3016 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3017 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3018 3019 operating-points-v2 = <&mdss_dsi_opp_table>; 3020 power-domains = <&rpmhpd SM8450_MMCX>; 3021 3022 phys = <&mdss_dsi1_phy>; 3023 phy-names = "dsi"; 3024 3025 #address-cells = <1>; 3026 #size-cells = <0>; 3027 3028 status = "disabled"; 3029 3030 ports { 3031 #address-cells = <1>; 3032 #size-cells = <0>; 3033 3034 port@0 { 3035 reg = <0>; 3036 mdss_dsi1_in: endpoint { 3037 remote-endpoint = <&dpu_intf2_out>; 3038 }; 3039 }; 3040 3041 port@1 { 3042 reg = <1>; 3043 mdss_dsi1_out: endpoint { 3044 }; 3045 }; 3046 }; 3047 }; 3048 3049 mdss_dsi1_phy: phy@ae96400 { 3050 compatible = "qcom,sm8450-dsi-phy-5nm"; 3051 reg = <0 0x0ae96400 0 0x200>, 3052 <0 0x0ae96600 0 0x280>, 3053 <0 0x0ae96900 0 0x260>; 3054 reg-names = "dsi_phy", 3055 "dsi_phy_lane", 3056 "dsi_pll"; 3057 3058 #clock-cells = <1>; 3059 #phy-cells = <0>; 3060 3061 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3062 <&rpmhcc RPMH_CXO_CLK>; 3063 clock-names = "iface", "ref"; 3064 3065 status = "disabled"; 3066 }; 3067 }; 3068 3069 dispcc: clock-controller@af00000 { 3070 compatible = "qcom,sm8450-dispcc"; 3071 reg = <0 0x0af00000 0 0x20000>; 3072 clocks = <&rpmhcc RPMH_CXO_CLK>, 3073 <&rpmhcc RPMH_CXO_CLK_A>, 3074 <&gcc GCC_DISP_AHB_CLK>, 3075 <&sleep_clk>, 3076 <&mdss_dsi0_phy 0>, 3077 <&mdss_dsi0_phy 1>, 3078 <&mdss_dsi1_phy 0>, 3079 <&mdss_dsi1_phy 1>, 3080 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3081 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3082 <0>, /* dp1 */ 3083 <0>, 3084 <0>, /* dp2 */ 3085 <0>, 3086 <0>, /* dp3 */ 3087 <0>; 3088 power-domains = <&rpmhpd SM8450_MMCX>; 3089 required-opps = <&rpmhpd_opp_low_svs>; 3090 #clock-cells = <1>; 3091 #reset-cells = <1>; 3092 #power-domain-cells = <1>; 3093 status = "disabled"; 3094 }; 3095 3096 pdc: interrupt-controller@b220000 { 3097 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3098 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3099 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3100 <94 609 31>, <125 63 1>, <126 716 12>; 3101 #interrupt-cells = <2>; 3102 interrupt-parent = <&intc>; 3103 interrupt-controller; 3104 }; 3105 3106 tsens0: thermal-sensor@c263000 { 3107 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3108 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3109 <0 0x0c222000 0 0x1000>; /* SROT */ 3110 #qcom,sensors = <16>; 3111 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3113 interrupt-names = "uplow", "critical"; 3114 #thermal-sensor-cells = <1>; 3115 }; 3116 3117 tsens1: thermal-sensor@c265000 { 3118 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3119 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3120 <0 0x0c223000 0 0x1000>; /* SROT */ 3121 #qcom,sensors = <16>; 3122 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3124 interrupt-names = "uplow", "critical"; 3125 #thermal-sensor-cells = <1>; 3126 }; 3127 3128 aoss_qmp: power-management@c300000 { 3129 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3130 reg = <0 0x0c300000 0 0x400>; 3131 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3132 IRQ_TYPE_EDGE_RISING>; 3133 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3134 3135 #clock-cells = <0>; 3136 }; 3137 3138 spmi_bus: spmi@c400000 { 3139 compatible = "qcom,spmi-pmic-arb"; 3140 reg = <0 0x0c400000 0 0x00003000>, 3141 <0 0x0c500000 0 0x00400000>, 3142 <0 0x0c440000 0 0x00080000>, 3143 <0 0x0c4c0000 0 0x00010000>, 3144 <0 0x0c42d000 0 0x00010000>; 3145 reg-names = "core", 3146 "chnls", 3147 "obsrvr", 3148 "intr", 3149 "cnfg"; 3150 interrupt-names = "periph_irq"; 3151 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3152 qcom,ee = <0>; 3153 qcom,channel = <0>; 3154 interrupt-controller; 3155 #interrupt-cells = <4>; 3156 #address-cells = <2>; 3157 #size-cells = <0>; 3158 }; 3159 3160 ipcc: mailbox@ed18000 { 3161 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3162 reg = <0 0x0ed18000 0 0x1000>; 3163 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3164 interrupt-controller; 3165 #interrupt-cells = <3>; 3166 #mbox-cells = <2>; 3167 }; 3168 3169 tlmm: pinctrl@f100000 { 3170 compatible = "qcom,sm8450-tlmm"; 3171 reg = <0 0x0f100000 0 0x300000>; 3172 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3173 gpio-controller; 3174 #gpio-cells = <2>; 3175 interrupt-controller; 3176 #interrupt-cells = <2>; 3177 gpio-ranges = <&tlmm 0 0 211>; 3178 wakeup-parent = <&pdc>; 3179 3180 sdc2_default_state: sdc2-default-state { 3181 clk-pins { 3182 pins = "sdc2_clk"; 3183 drive-strength = <16>; 3184 bias-disable; 3185 }; 3186 3187 cmd-pins { 3188 pins = "sdc2_cmd"; 3189 drive-strength = <16>; 3190 bias-pull-up; 3191 }; 3192 3193 data-pins { 3194 pins = "sdc2_data"; 3195 drive-strength = <16>; 3196 bias-pull-up; 3197 }; 3198 }; 3199 3200 sdc2_sleep_state: sdc2-sleep-state { 3201 clk-pins { 3202 pins = "sdc2_clk"; 3203 drive-strength = <2>; 3204 bias-disable; 3205 }; 3206 3207 cmd-pins { 3208 pins = "sdc2_cmd"; 3209 drive-strength = <2>; 3210 bias-pull-up; 3211 }; 3212 3213 data-pins { 3214 pins = "sdc2_data"; 3215 drive-strength = <2>; 3216 bias-pull-up; 3217 }; 3218 }; 3219 3220 cci0_default: cci0-default-state { 3221 /* SDA, SCL */ 3222 pins = "gpio110", "gpio111"; 3223 function = "cci_i2c"; 3224 drive-strength = <2>; 3225 bias-pull-up; 3226 }; 3227 3228 cci0_sleep: cci0-sleep-state { 3229 /* SDA, SCL */ 3230 pins = "gpio110", "gpio111"; 3231 function = "cci_i2c"; 3232 drive-strength = <2>; 3233 bias-pull-down; 3234 }; 3235 3236 cci1_default: cci1-default-state { 3237 /* SDA, SCL */ 3238 pins = "gpio112", "gpio113"; 3239 function = "cci_i2c"; 3240 drive-strength = <2>; 3241 bias-pull-up; 3242 }; 3243 3244 cci1_sleep: cci1-sleep-state { 3245 /* SDA, SCL */ 3246 pins = "gpio112", "gpio113"; 3247 function = "cci_i2c"; 3248 drive-strength = <2>; 3249 bias-pull-down; 3250 }; 3251 3252 cci2_default: cci2-default-state { 3253 /* SDA, SCL */ 3254 pins = "gpio114", "gpio115"; 3255 function = "cci_i2c"; 3256 drive-strength = <2>; 3257 bias-pull-up; 3258 }; 3259 3260 cci2_sleep: cci2-sleep-state { 3261 /* SDA, SCL */ 3262 pins = "gpio114", "gpio115"; 3263 function = "cci_i2c"; 3264 drive-strength = <2>; 3265 bias-pull-down; 3266 }; 3267 3268 cci3_default: cci3-default-state { 3269 /* SDA, SCL */ 3270 pins = "gpio208", "gpio209"; 3271 function = "cci_i2c"; 3272 drive-strength = <2>; 3273 bias-pull-up; 3274 }; 3275 3276 cci3_sleep: cci3-sleep-state { 3277 /* SDA, SCL */ 3278 pins = "gpio208", "gpio209"; 3279 function = "cci_i2c"; 3280 drive-strength = <2>; 3281 bias-pull-down; 3282 }; 3283 3284 pcie0_default_state: pcie0-default-state { 3285 perst-pins { 3286 pins = "gpio94"; 3287 function = "gpio"; 3288 drive-strength = <2>; 3289 bias-pull-down; 3290 }; 3291 3292 clkreq-pins { 3293 pins = "gpio95"; 3294 function = "pcie0_clkreqn"; 3295 drive-strength = <2>; 3296 bias-pull-up; 3297 }; 3298 3299 wake-pins { 3300 pins = "gpio96"; 3301 function = "gpio"; 3302 drive-strength = <2>; 3303 bias-pull-up; 3304 }; 3305 }; 3306 3307 pcie1_default_state: pcie1-default-state { 3308 perst-pins { 3309 pins = "gpio97"; 3310 function = "gpio"; 3311 drive-strength = <2>; 3312 bias-pull-down; 3313 }; 3314 3315 clkreq-pins { 3316 pins = "gpio98"; 3317 function = "pcie1_clkreqn"; 3318 drive-strength = <2>; 3319 bias-pull-up; 3320 }; 3321 3322 wake-pins { 3323 pins = "gpio99"; 3324 function = "gpio"; 3325 drive-strength = <2>; 3326 bias-pull-up; 3327 }; 3328 }; 3329 3330 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3331 pins = "gpio0", "gpio1"; 3332 function = "qup0"; 3333 }; 3334 3335 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3336 pins = "gpio4", "gpio5"; 3337 function = "qup1"; 3338 }; 3339 3340 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3341 pins = "gpio8", "gpio9"; 3342 function = "qup2"; 3343 }; 3344 3345 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3346 pins = "gpio12", "gpio13"; 3347 function = "qup3"; 3348 }; 3349 3350 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3351 pins = "gpio16", "gpio17"; 3352 function = "qup4"; 3353 }; 3354 3355 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3356 pins = "gpio206", "gpio207"; 3357 function = "qup5"; 3358 }; 3359 3360 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3361 pins = "gpio20", "gpio21"; 3362 function = "qup6"; 3363 }; 3364 3365 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3366 pins = "gpio28", "gpio29"; 3367 function = "qup8"; 3368 }; 3369 3370 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3371 pins = "gpio32", "gpio33"; 3372 function = "qup9"; 3373 }; 3374 3375 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3376 pins = "gpio36", "gpio37"; 3377 function = "qup10"; 3378 }; 3379 3380 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3381 pins = "gpio40", "gpio41"; 3382 function = "qup11"; 3383 }; 3384 3385 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3386 pins = "gpio44", "gpio45"; 3387 function = "qup12"; 3388 }; 3389 3390 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3391 pins = "gpio48", "gpio49"; 3392 function = "qup13"; 3393 drive-strength = <2>; 3394 bias-pull-up; 3395 }; 3396 3397 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3398 pins = "gpio52", "gpio53"; 3399 function = "qup14"; 3400 drive-strength = <2>; 3401 bias-pull-up; 3402 }; 3403 3404 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3405 pins = "gpio56", "gpio57"; 3406 function = "qup15"; 3407 }; 3408 3409 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3410 pins = "gpio60", "gpio61"; 3411 function = "qup16"; 3412 }; 3413 3414 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3415 pins = "gpio64", "gpio65"; 3416 function = "qup17"; 3417 }; 3418 3419 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3420 pins = "gpio68", "gpio69"; 3421 function = "qup18"; 3422 }; 3423 3424 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3425 pins = "gpio72", "gpio73"; 3426 function = "qup19"; 3427 }; 3428 3429 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3430 pins = "gpio76", "gpio77"; 3431 function = "qup20"; 3432 }; 3433 3434 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3435 pins = "gpio80", "gpio81"; 3436 function = "qup21"; 3437 }; 3438 3439 qup_spi0_cs: qup-spi0-cs-state { 3440 pins = "gpio3"; 3441 function = "qup0"; 3442 }; 3443 3444 qup_spi0_data_clk: qup-spi0-data-clk-state { 3445 pins = "gpio0", "gpio1", "gpio2"; 3446 function = "qup0"; 3447 }; 3448 3449 qup_spi1_cs: qup-spi1-cs-state { 3450 pins = "gpio7"; 3451 function = "qup1"; 3452 }; 3453 3454 qup_spi1_data_clk: qup-spi1-data-clk-state { 3455 pins = "gpio4", "gpio5", "gpio6"; 3456 function = "qup1"; 3457 }; 3458 3459 qup_spi2_cs: qup-spi2-cs-state { 3460 pins = "gpio11"; 3461 function = "qup2"; 3462 }; 3463 3464 qup_spi2_data_clk: qup-spi2-data-clk-state { 3465 pins = "gpio8", "gpio9", "gpio10"; 3466 function = "qup2"; 3467 }; 3468 3469 qup_spi3_cs: qup-spi3-cs-state { 3470 pins = "gpio15"; 3471 function = "qup3"; 3472 }; 3473 3474 qup_spi3_data_clk: qup-spi3-data-clk-state { 3475 pins = "gpio12", "gpio13", "gpio14"; 3476 function = "qup3"; 3477 }; 3478 3479 qup_spi4_cs: qup-spi4-cs-state { 3480 pins = "gpio19"; 3481 function = "qup4"; 3482 drive-strength = <6>; 3483 bias-disable; 3484 }; 3485 3486 qup_spi4_data_clk: qup-spi4-data-clk-state { 3487 pins = "gpio16", "gpio17", "gpio18"; 3488 function = "qup4"; 3489 }; 3490 3491 qup_spi5_cs: qup-spi5-cs-state { 3492 pins = "gpio85"; 3493 function = "qup5"; 3494 }; 3495 3496 qup_spi5_data_clk: qup-spi5-data-clk-state { 3497 pins = "gpio206", "gpio207", "gpio84"; 3498 function = "qup5"; 3499 }; 3500 3501 qup_spi6_cs: qup-spi6-cs-state { 3502 pins = "gpio23"; 3503 function = "qup6"; 3504 }; 3505 3506 qup_spi6_data_clk: qup-spi6-data-clk-state { 3507 pins = "gpio20", "gpio21", "gpio22"; 3508 function = "qup6"; 3509 }; 3510 3511 qup_spi8_cs: qup-spi8-cs-state { 3512 pins = "gpio31"; 3513 function = "qup8"; 3514 }; 3515 3516 qup_spi8_data_clk: qup-spi8-data-clk-state { 3517 pins = "gpio28", "gpio29", "gpio30"; 3518 function = "qup8"; 3519 }; 3520 3521 qup_spi9_cs: qup-spi9-cs-state { 3522 pins = "gpio35"; 3523 function = "qup9"; 3524 }; 3525 3526 qup_spi9_data_clk: qup-spi9-data-clk-state { 3527 pins = "gpio32", "gpio33", "gpio34"; 3528 function = "qup9"; 3529 }; 3530 3531 qup_spi10_cs: qup-spi10-cs-state { 3532 pins = "gpio39"; 3533 function = "qup10"; 3534 }; 3535 3536 qup_spi10_data_clk: qup-spi10-data-clk-state { 3537 pins = "gpio36", "gpio37", "gpio38"; 3538 function = "qup10"; 3539 }; 3540 3541 qup_spi11_cs: qup-spi11-cs-state { 3542 pins = "gpio43"; 3543 function = "qup11"; 3544 }; 3545 3546 qup_spi11_data_clk: qup-spi11-data-clk-state { 3547 pins = "gpio40", "gpio41", "gpio42"; 3548 function = "qup11"; 3549 }; 3550 3551 qup_spi12_cs: qup-spi12-cs-state { 3552 pins = "gpio47"; 3553 function = "qup12"; 3554 }; 3555 3556 qup_spi12_data_clk: qup-spi12-data-clk-state { 3557 pins = "gpio44", "gpio45", "gpio46"; 3558 function = "qup12"; 3559 }; 3560 3561 qup_spi13_cs: qup-spi13-cs-state { 3562 pins = "gpio51"; 3563 function = "qup13"; 3564 }; 3565 3566 qup_spi13_data_clk: qup-spi13-data-clk-state { 3567 pins = "gpio48", "gpio49", "gpio50"; 3568 function = "qup13"; 3569 }; 3570 3571 qup_spi14_cs: qup-spi14-cs-state { 3572 pins = "gpio55"; 3573 function = "qup14"; 3574 }; 3575 3576 qup_spi14_data_clk: qup-spi14-data-clk-state { 3577 pins = "gpio52", "gpio53", "gpio54"; 3578 function = "qup14"; 3579 }; 3580 3581 qup_spi15_cs: qup-spi15-cs-state { 3582 pins = "gpio59"; 3583 function = "qup15"; 3584 }; 3585 3586 qup_spi15_data_clk: qup-spi15-data-clk-state { 3587 pins = "gpio56", "gpio57", "gpio58"; 3588 function = "qup15"; 3589 }; 3590 3591 qup_spi16_cs: qup-spi16-cs-state { 3592 pins = "gpio63"; 3593 function = "qup16"; 3594 }; 3595 3596 qup_spi16_data_clk: qup-spi16-data-clk-state { 3597 pins = "gpio60", "gpio61", "gpio62"; 3598 function = "qup16"; 3599 }; 3600 3601 qup_spi17_cs: qup-spi17-cs-state { 3602 pins = "gpio67"; 3603 function = "qup17"; 3604 }; 3605 3606 qup_spi17_data_clk: qup-spi17-data-clk-state { 3607 pins = "gpio64", "gpio65", "gpio66"; 3608 function = "qup17"; 3609 }; 3610 3611 qup_spi18_cs: qup-spi18-cs-state { 3612 pins = "gpio71"; 3613 function = "qup18"; 3614 drive-strength = <6>; 3615 bias-disable; 3616 }; 3617 3618 qup_spi18_data_clk: qup-spi18-data-clk-state { 3619 pins = "gpio68", "gpio69", "gpio70"; 3620 function = "qup18"; 3621 drive-strength = <6>; 3622 bias-disable; 3623 }; 3624 3625 qup_spi19_cs: qup-spi19-cs-state { 3626 pins = "gpio75"; 3627 function = "qup19"; 3628 drive-strength = <6>; 3629 bias-disable; 3630 }; 3631 3632 qup_spi19_data_clk: qup-spi19-data-clk-state { 3633 pins = "gpio72", "gpio73", "gpio74"; 3634 function = "qup19"; 3635 drive-strength = <6>; 3636 bias-disable; 3637 }; 3638 3639 qup_spi20_cs: qup-spi20-cs-state { 3640 pins = "gpio79"; 3641 function = "qup20"; 3642 }; 3643 3644 qup_spi20_data_clk: qup-spi20-data-clk-state { 3645 pins = "gpio76", "gpio77", "gpio78"; 3646 function = "qup20"; 3647 }; 3648 3649 qup_spi21_cs: qup-spi21-cs-state { 3650 pins = "gpio83"; 3651 function = "qup21"; 3652 }; 3653 3654 qup_spi21_data_clk: qup-spi21-data-clk-state { 3655 pins = "gpio80", "gpio81", "gpio82"; 3656 function = "qup21"; 3657 }; 3658 3659 qup_uart7_rx: qup-uart7-rx-state { 3660 pins = "gpio26"; 3661 function = "qup7"; 3662 drive-strength = <2>; 3663 bias-disable; 3664 }; 3665 3666 qup_uart7_tx: qup-uart7-tx-state { 3667 pins = "gpio27"; 3668 function = "qup7"; 3669 drive-strength = <2>; 3670 bias-disable; 3671 }; 3672 3673 qup_uart20_default: qup-uart20-default-state { 3674 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3675 function = "qup20"; 3676 }; 3677 }; 3678 3679 lpass_tlmm: pinctrl@3440000 { 3680 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3681 reg = <0 0x03440000 0x0 0x20000>, 3682 <0 0x034d0000 0x0 0x10000>; 3683 gpio-controller; 3684 #gpio-cells = <2>; 3685 gpio-ranges = <&lpass_tlmm 0 0 23>; 3686 3687 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3688 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3689 clock-names = "core", "audio"; 3690 3691 tx_swr_active: tx-swr-active-state { 3692 clk-pins { 3693 pins = "gpio0"; 3694 function = "swr_tx_clk"; 3695 drive-strength = <2>; 3696 slew-rate = <1>; 3697 bias-disable; 3698 }; 3699 3700 data-pins { 3701 pins = "gpio1", "gpio2", "gpio14"; 3702 function = "swr_tx_data"; 3703 drive-strength = <2>; 3704 slew-rate = <1>; 3705 bias-bus-hold; 3706 }; 3707 }; 3708 3709 rx_swr_active: rx-swr-active-state { 3710 clk-pins { 3711 pins = "gpio3"; 3712 function = "swr_rx_clk"; 3713 drive-strength = <2>; 3714 slew-rate = <1>; 3715 bias-disable; 3716 }; 3717 3718 data-pins { 3719 pins = "gpio4", "gpio5"; 3720 function = "swr_rx_data"; 3721 drive-strength = <2>; 3722 slew-rate = <1>; 3723 bias-bus-hold; 3724 }; 3725 }; 3726 3727 dmic01_default: dmic01-default-state { 3728 clk-pins { 3729 pins = "gpio6"; 3730 function = "dmic1_clk"; 3731 drive-strength = <8>; 3732 output-high; 3733 }; 3734 3735 data-pins { 3736 pins = "gpio7"; 3737 function = "dmic1_data"; 3738 drive-strength = <8>; 3739 }; 3740 }; 3741 3742 dmic02_default: dmic02-default-state { 3743 clk-pins { 3744 pins = "gpio8"; 3745 function = "dmic2_clk"; 3746 drive-strength = <8>; 3747 output-high; 3748 }; 3749 3750 data-pins { 3751 pins = "gpio9"; 3752 function = "dmic2_data"; 3753 drive-strength = <8>; 3754 }; 3755 }; 3756 3757 wsa_swr_active: wsa-swr-active-state { 3758 clk-pins { 3759 pins = "gpio10"; 3760 function = "wsa_swr_clk"; 3761 drive-strength = <2>; 3762 slew-rate = <1>; 3763 bias-disable; 3764 }; 3765 3766 data-pins { 3767 pins = "gpio11"; 3768 function = "wsa_swr_data"; 3769 drive-strength = <2>; 3770 slew-rate = <1>; 3771 bias-bus-hold; 3772 }; 3773 }; 3774 3775 wsa2_swr_active: wsa2-swr-active-state { 3776 clk-pins { 3777 pins = "gpio15"; 3778 function = "wsa2_swr_clk"; 3779 drive-strength = <2>; 3780 slew-rate = <1>; 3781 bias-disable; 3782 }; 3783 3784 data-pins { 3785 pins = "gpio16"; 3786 function = "wsa2_swr_data"; 3787 drive-strength = <2>; 3788 slew-rate = <1>; 3789 bias-bus-hold; 3790 }; 3791 }; 3792 }; 3793 3794 sram@146aa000 { 3795 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3796 reg = <0 0x146aa000 0 0x1000>; 3797 ranges = <0 0 0x146aa000 0x1000>; 3798 3799 #address-cells = <1>; 3800 #size-cells = <1>; 3801 3802 pil-reloc@94c { 3803 compatible = "qcom,pil-reloc-info"; 3804 reg = <0x94c 0xc8>; 3805 }; 3806 }; 3807 3808 apps_smmu: iommu@15000000 { 3809 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3810 reg = <0 0x15000000 0 0x100000>; 3811 #iommu-cells = <2>; 3812 #global-interrupts = <1>; 3813 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3910 }; 3911 3912 intc: interrupt-controller@17100000 { 3913 compatible = "arm,gic-v3"; 3914 #interrupt-cells = <3>; 3915 interrupt-controller; 3916 #redistributor-regions = <1>; 3917 redistributor-stride = <0x0 0x40000>; 3918 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3919 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3920 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3921 #address-cells = <2>; 3922 #size-cells = <2>; 3923 ranges; 3924 3925 gic_its: msi-controller@17140000 { 3926 compatible = "arm,gic-v3-its"; 3927 reg = <0x0 0x17140000 0x0 0x20000>; 3928 msi-controller; 3929 #msi-cells = <1>; 3930 }; 3931 }; 3932 3933 timer@17420000 { 3934 compatible = "arm,armv7-timer-mem"; 3935 #address-cells = <1>; 3936 #size-cells = <1>; 3937 ranges = <0 0 0 0x20000000>; 3938 reg = <0x0 0x17420000 0x0 0x1000>; 3939 clock-frequency = <19200000>; 3940 3941 frame@17421000 { 3942 frame-number = <0>; 3943 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3945 reg = <0x17421000 0x1000>, 3946 <0x17422000 0x1000>; 3947 }; 3948 3949 frame@17423000 { 3950 frame-number = <1>; 3951 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3952 reg = <0x17423000 0x1000>; 3953 status = "disabled"; 3954 }; 3955 3956 frame@17425000 { 3957 frame-number = <2>; 3958 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3959 reg = <0x17425000 0x1000>; 3960 status = "disabled"; 3961 }; 3962 3963 frame@17427000 { 3964 frame-number = <3>; 3965 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3966 reg = <0x17427000 0x1000>; 3967 status = "disabled"; 3968 }; 3969 3970 frame@17429000 { 3971 frame-number = <4>; 3972 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3973 reg = <0x17429000 0x1000>; 3974 status = "disabled"; 3975 }; 3976 3977 frame@1742b000 { 3978 frame-number = <5>; 3979 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3980 reg = <0x1742b000 0x1000>; 3981 status = "disabled"; 3982 }; 3983 3984 frame@1742d000 { 3985 frame-number = <6>; 3986 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3987 reg = <0x1742d000 0x1000>; 3988 status = "disabled"; 3989 }; 3990 }; 3991 3992 apps_rsc: rsc@17a00000 { 3993 label = "apps_rsc"; 3994 compatible = "qcom,rpmh-rsc"; 3995 reg = <0x0 0x17a00000 0x0 0x10000>, 3996 <0x0 0x17a10000 0x0 0x10000>, 3997 <0x0 0x17a20000 0x0 0x10000>, 3998 <0x0 0x17a30000 0x0 0x10000>; 3999 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4000 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4003 qcom,tcs-offset = <0xd00>; 4004 qcom,drv-id = <2>; 4005 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4006 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4007 power-domains = <&CLUSTER_PD>; 4008 4009 apps_bcm_voter: bcm-voter { 4010 compatible = "qcom,bcm-voter"; 4011 }; 4012 4013 rpmhcc: clock-controller { 4014 compatible = "qcom,sm8450-rpmh-clk"; 4015 #clock-cells = <1>; 4016 clock-names = "xo"; 4017 clocks = <&xo_board>; 4018 }; 4019 4020 rpmhpd: power-controller { 4021 compatible = "qcom,sm8450-rpmhpd"; 4022 #power-domain-cells = <1>; 4023 operating-points-v2 = <&rpmhpd_opp_table>; 4024 4025 rpmhpd_opp_table: opp-table { 4026 compatible = "operating-points-v2"; 4027 4028 rpmhpd_opp_ret: opp1 { 4029 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4030 }; 4031 4032 rpmhpd_opp_min_svs: opp2 { 4033 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4034 }; 4035 4036 rpmhpd_opp_low_svs_d1: opp3 { 4037 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4038 }; 4039 4040 rpmhpd_opp_low_svs: opp4 { 4041 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4042 }; 4043 4044 rpmhpd_opp_low_svs_l1: opp5 { 4045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4046 }; 4047 4048 rpmhpd_opp_svs: opp6 { 4049 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4050 }; 4051 4052 rpmhpd_opp_svs_l0: opp7 { 4053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4054 }; 4055 4056 rpmhpd_opp_svs_l1: opp8 { 4057 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4058 }; 4059 4060 rpmhpd_opp_svs_l2: opp9 { 4061 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4062 }; 4063 4064 rpmhpd_opp_nom: opp10 { 4065 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4066 }; 4067 4068 rpmhpd_opp_nom_l1: opp11 { 4069 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4070 }; 4071 4072 rpmhpd_opp_nom_l2: opp12 { 4073 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4074 }; 4075 4076 rpmhpd_opp_turbo: opp13 { 4077 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4078 }; 4079 4080 rpmhpd_opp_turbo_l1: opp14 { 4081 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4082 }; 4083 }; 4084 }; 4085 }; 4086 4087 cpufreq_hw: cpufreq@17d91000 { 4088 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4089 reg = <0 0x17d91000 0 0x1000>, 4090 <0 0x17d92000 0 0x1000>, 4091 <0 0x17d93000 0 0x1000>; 4092 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4093 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4094 clock-names = "xo", "alternate"; 4095 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4098 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4099 #freq-domain-cells = <1>; 4100 #clock-cells = <1>; 4101 }; 4102 4103 gem_noc: interconnect@19100000 { 4104 compatible = "qcom,sm8450-gem-noc"; 4105 reg = <0 0x19100000 0 0xbb800>; 4106 #interconnect-cells = <2>; 4107 qcom,bcm-voters = <&apps_bcm_voter>; 4108 }; 4109 4110 system-cache-controller@19200000 { 4111 compatible = "qcom,sm8450-llcc"; 4112 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4113 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4114 <0 0x19a00000 0 0x80000>; 4115 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4116 "llcc3_base", "llcc_broadcast_base"; 4117 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4118 }; 4119 4120 ufs_mem_hc: ufshc@1d84000 { 4121 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4122 "jedec,ufs-2.0"; 4123 reg = <0 0x01d84000 0 0x3000>, 4124 <0 0x01d88000 0 0x8000>; 4125 reg-names = "std", "ice"; 4126 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4127 phys = <&ufs_mem_phy_lanes>; 4128 phy-names = "ufsphy"; 4129 lanes-per-direction = <2>; 4130 #reset-cells = <1>; 4131 resets = <&gcc GCC_UFS_PHY_BCR>; 4132 reset-names = "rst"; 4133 4134 power-domains = <&gcc UFS_PHY_GDSC>; 4135 4136 iommus = <&apps_smmu 0xe0 0x0>; 4137 dma-coherent; 4138 4139 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4141 interconnect-names = "ufs-ddr", "cpu-ufs"; 4142 clock-names = 4143 "core_clk", 4144 "bus_aggr_clk", 4145 "iface_clk", 4146 "core_clk_unipro", 4147 "ref_clk", 4148 "tx_lane0_sync_clk", 4149 "rx_lane0_sync_clk", 4150 "rx_lane1_sync_clk", 4151 "ice_core_clk"; 4152 clocks = 4153 <&gcc GCC_UFS_PHY_AXI_CLK>, 4154 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4155 <&gcc GCC_UFS_PHY_AHB_CLK>, 4156 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4157 <&rpmhcc RPMH_CXO_CLK>, 4158 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4159 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4160 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 4161 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4162 freq-table-hz = 4163 <75000000 300000000>, 4164 <0 0>, 4165 <0 0>, 4166 <75000000 300000000>, 4167 <75000000 300000000>, 4168 <0 0>, 4169 <0 0>, 4170 <0 0>, 4171 <75000000 300000000>; 4172 status = "disabled"; 4173 }; 4174 4175 ufs_mem_phy: phy@1d87000 { 4176 compatible = "qcom,sm8450-qmp-ufs-phy"; 4177 reg = <0 0x01d87000 0 0x1c4>; 4178 #address-cells = <2>; 4179 #size-cells = <2>; 4180 ranges; 4181 clock-names = "ref", "ref_aux", "qref"; 4182 clocks = <&rpmhcc RPMH_CXO_CLK>, 4183 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4184 <&gcc GCC_UFS_0_CLKREF_EN>; 4185 4186 resets = <&ufs_mem_hc 0>; 4187 reset-names = "ufsphy"; 4188 status = "disabled"; 4189 4190 ufs_mem_phy_lanes: phy@1d87400 { 4191 reg = <0 0x01d87400 0 0x188>, 4192 <0 0x01d87600 0 0x200>, 4193 <0 0x01d87c00 0 0x200>, 4194 <0 0x01d87800 0 0x188>, 4195 <0 0x01d87a00 0 0x200>; 4196 #clock-cells = <1>; 4197 #phy-cells = <0>; 4198 }; 4199 }; 4200 4201 cryptobam: dma-controller@1dc4000 { 4202 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4203 reg = <0 0x01dc4000 0 0x28000>; 4204 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4205 #dma-cells = <1>; 4206 qcom,ee = <0>; 4207 qcom,controlled-remotely; 4208 iommus = <&apps_smmu 0x584 0x11>, 4209 <&apps_smmu 0x588 0x0>, 4210 <&apps_smmu 0x598 0x5>, 4211 <&apps_smmu 0x59a 0x0>, 4212 <&apps_smmu 0x59f 0x0>; 4213 }; 4214 4215 crypto: crypto@1de0000 { 4216 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4217 reg = <0 0x01dfa000 0 0x6000>; 4218 dmas = <&cryptobam 4>, <&cryptobam 5>; 4219 dma-names = "rx", "tx"; 4220 iommus = <&apps_smmu 0x584 0x11>, 4221 <&apps_smmu 0x588 0x0>, 4222 <&apps_smmu 0x598 0x5>, 4223 <&apps_smmu 0x59a 0x0>, 4224 <&apps_smmu 0x59f 0x0>; 4225 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4226 interconnect-names = "memory"; 4227 }; 4228 4229 sdhc_2: mmc@8804000 { 4230 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4231 reg = <0 0x08804000 0 0x1000>; 4232 4233 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4235 interrupt-names = "hc_irq", "pwr_irq"; 4236 4237 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4238 <&gcc GCC_SDCC2_APPS_CLK>, 4239 <&rpmhcc RPMH_CXO_CLK>; 4240 clock-names = "iface", "core", "xo"; 4241 resets = <&gcc GCC_SDCC2_BCR>; 4242 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4243 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4244 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4245 iommus = <&apps_smmu 0x4a0 0x0>; 4246 power-domains = <&rpmhpd SM8450_CX>; 4247 operating-points-v2 = <&sdhc2_opp_table>; 4248 bus-width = <4>; 4249 dma-coherent; 4250 4251 /* Forbid SDR104/SDR50 - broken hw! */ 4252 sdhci-caps-mask = <0x3 0x0>; 4253 4254 status = "disabled"; 4255 4256 sdhc2_opp_table: opp-table { 4257 compatible = "operating-points-v2"; 4258 4259 opp-100000000 { 4260 opp-hz = /bits/ 64 <100000000>; 4261 required-opps = <&rpmhpd_opp_low_svs>; 4262 }; 4263 4264 opp-202000000 { 4265 opp-hz = /bits/ 64 <202000000>; 4266 required-opps = <&rpmhpd_opp_svs_l1>; 4267 }; 4268 }; 4269 }; 4270 4271 usb_1: usb@a6f8800 { 4272 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4273 reg = <0 0x0a6f8800 0 0x400>; 4274 status = "disabled"; 4275 #address-cells = <2>; 4276 #size-cells = <2>; 4277 ranges; 4278 4279 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4280 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4281 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4282 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4283 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4284 <&gcc GCC_USB3_0_CLKREF_EN>; 4285 clock-names = "cfg_noc", 4286 "core", 4287 "iface", 4288 "sleep", 4289 "mock_utmi", 4290 "xo"; 4291 4292 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4293 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4294 assigned-clock-rates = <19200000>, <200000000>; 4295 4296 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4297 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4298 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4299 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4300 interrupt-names = "hs_phy_irq", 4301 "ss_phy_irq", 4302 "dm_hs_phy_irq", 4303 "dp_hs_phy_irq"; 4304 4305 power-domains = <&gcc USB30_PRIM_GDSC>; 4306 4307 resets = <&gcc GCC_USB30_PRIM_BCR>; 4308 4309 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4311 interconnect-names = "usb-ddr", "apps-usb"; 4312 4313 usb_1_dwc3: usb@a600000 { 4314 compatible = "snps,dwc3"; 4315 reg = <0 0x0a600000 0 0xcd00>; 4316 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4317 iommus = <&apps_smmu 0x0 0x0>; 4318 snps,dis_u2_susphy_quirk; 4319 snps,dis_enblslpm_quirk; 4320 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4321 phy-names = "usb2-phy", "usb3-phy"; 4322 4323 ports { 4324 #address-cells = <1>; 4325 #size-cells = <0>; 4326 4327 port@0 { 4328 reg = <0>; 4329 4330 usb_1_dwc3_hs: endpoint { 4331 }; 4332 }; 4333 4334 port@1 { 4335 reg = <1>; 4336 4337 usb_1_dwc3_ss: endpoint { 4338 }; 4339 }; 4340 }; 4341 }; 4342 }; 4343 4344 nsp_noc: interconnect@320c0000 { 4345 compatible = "qcom,sm8450-nsp-noc"; 4346 reg = <0 0x320c0000 0 0x10000>; 4347 #interconnect-cells = <2>; 4348 qcom,bcm-voters = <&apps_bcm_voter>; 4349 }; 4350 4351 lpass_ag_noc: interconnect@3c40000 { 4352 compatible = "qcom,sm8450-lpass-ag-noc"; 4353 reg = <0 0x03c40000 0 0x17200>; 4354 #interconnect-cells = <2>; 4355 qcom,bcm-voters = <&apps_bcm_voter>; 4356 }; 4357 }; 4358 4359 sound: sound { 4360 }; 4361 4362 thermal-zones { 4363 aoss0-thermal { 4364 polling-delay-passive = <0>; 4365 polling-delay = <0>; 4366 thermal-sensors = <&tsens0 0>; 4367 4368 trips { 4369 thermal-engine-config { 4370 temperature = <125000>; 4371 hysteresis = <1000>; 4372 type = "passive"; 4373 }; 4374 4375 reset-mon-cfg { 4376 temperature = <115000>; 4377 hysteresis = <5000>; 4378 type = "passive"; 4379 }; 4380 }; 4381 }; 4382 4383 cpuss0-thermal { 4384 polling-delay-passive = <0>; 4385 polling-delay = <0>; 4386 thermal-sensors = <&tsens0 1>; 4387 4388 trips { 4389 thermal-engine-config { 4390 temperature = <125000>; 4391 hysteresis = <1000>; 4392 type = "passive"; 4393 }; 4394 4395 reset-mon-cfg { 4396 temperature = <115000>; 4397 hysteresis = <5000>; 4398 type = "passive"; 4399 }; 4400 }; 4401 }; 4402 4403 cpuss1-thermal { 4404 polling-delay-passive = <0>; 4405 polling-delay = <0>; 4406 thermal-sensors = <&tsens0 2>; 4407 4408 trips { 4409 thermal-engine-config { 4410 temperature = <125000>; 4411 hysteresis = <1000>; 4412 type = "passive"; 4413 }; 4414 4415 reset-mon-cfg { 4416 temperature = <115000>; 4417 hysteresis = <5000>; 4418 type = "passive"; 4419 }; 4420 }; 4421 }; 4422 4423 cpuss3-thermal { 4424 polling-delay-passive = <0>; 4425 polling-delay = <0>; 4426 thermal-sensors = <&tsens0 3>; 4427 4428 trips { 4429 thermal-engine-config { 4430 temperature = <125000>; 4431 hysteresis = <1000>; 4432 type = "passive"; 4433 }; 4434 4435 reset-mon-cfg { 4436 temperature = <115000>; 4437 hysteresis = <5000>; 4438 type = "passive"; 4439 }; 4440 }; 4441 }; 4442 4443 cpuss4-thermal { 4444 polling-delay-passive = <0>; 4445 polling-delay = <0>; 4446 thermal-sensors = <&tsens0 4>; 4447 4448 trips { 4449 thermal-engine-config { 4450 temperature = <125000>; 4451 hysteresis = <1000>; 4452 type = "passive"; 4453 }; 4454 4455 reset-mon-cfg { 4456 temperature = <115000>; 4457 hysteresis = <5000>; 4458 type = "passive"; 4459 }; 4460 }; 4461 }; 4462 4463 cpu4-top-thermal { 4464 polling-delay-passive = <0>; 4465 polling-delay = <0>; 4466 thermal-sensors = <&tsens0 5>; 4467 4468 trips { 4469 cpu4_top_alert0: trip-point0 { 4470 temperature = <90000>; 4471 hysteresis = <2000>; 4472 type = "passive"; 4473 }; 4474 4475 cpu4_top_alert1: trip-point1 { 4476 temperature = <95000>; 4477 hysteresis = <2000>; 4478 type = "passive"; 4479 }; 4480 4481 cpu4_top_crit: cpu-crit { 4482 temperature = <110000>; 4483 hysteresis = <1000>; 4484 type = "critical"; 4485 }; 4486 }; 4487 }; 4488 4489 cpu4-bottom-thermal { 4490 polling-delay-passive = <0>; 4491 polling-delay = <0>; 4492 thermal-sensors = <&tsens0 6>; 4493 4494 trips { 4495 cpu4_bottom_alert0: trip-point0 { 4496 temperature = <90000>; 4497 hysteresis = <2000>; 4498 type = "passive"; 4499 }; 4500 4501 cpu4_bottom_alert1: trip-point1 { 4502 temperature = <95000>; 4503 hysteresis = <2000>; 4504 type = "passive"; 4505 }; 4506 4507 cpu4_bottom_crit: cpu-crit { 4508 temperature = <110000>; 4509 hysteresis = <1000>; 4510 type = "critical"; 4511 }; 4512 }; 4513 }; 4514 4515 cpu5-top-thermal { 4516 polling-delay-passive = <0>; 4517 polling-delay = <0>; 4518 thermal-sensors = <&tsens0 7>; 4519 4520 trips { 4521 cpu5_top_alert0: trip-point0 { 4522 temperature = <90000>; 4523 hysteresis = <2000>; 4524 type = "passive"; 4525 }; 4526 4527 cpu5_top_alert1: trip-point1 { 4528 temperature = <95000>; 4529 hysteresis = <2000>; 4530 type = "passive"; 4531 }; 4532 4533 cpu5_top_crit: cpu-crit { 4534 temperature = <110000>; 4535 hysteresis = <1000>; 4536 type = "critical"; 4537 }; 4538 }; 4539 }; 4540 4541 cpu5-bottom-thermal { 4542 polling-delay-passive = <0>; 4543 polling-delay = <0>; 4544 thermal-sensors = <&tsens0 8>; 4545 4546 trips { 4547 cpu5_bottom_alert0: trip-point0 { 4548 temperature = <90000>; 4549 hysteresis = <2000>; 4550 type = "passive"; 4551 }; 4552 4553 cpu5_bottom_alert1: trip-point1 { 4554 temperature = <95000>; 4555 hysteresis = <2000>; 4556 type = "passive"; 4557 }; 4558 4559 cpu5_bottom_crit: cpu-crit { 4560 temperature = <110000>; 4561 hysteresis = <1000>; 4562 type = "critical"; 4563 }; 4564 }; 4565 }; 4566 4567 cpu6-top-thermal { 4568 polling-delay-passive = <0>; 4569 polling-delay = <0>; 4570 thermal-sensors = <&tsens0 9>; 4571 4572 trips { 4573 cpu6_top_alert0: trip-point0 { 4574 temperature = <90000>; 4575 hysteresis = <2000>; 4576 type = "passive"; 4577 }; 4578 4579 cpu6_top_alert1: trip-point1 { 4580 temperature = <95000>; 4581 hysteresis = <2000>; 4582 type = "passive"; 4583 }; 4584 4585 cpu6_top_crit: cpu-crit { 4586 temperature = <110000>; 4587 hysteresis = <1000>; 4588 type = "critical"; 4589 }; 4590 }; 4591 }; 4592 4593 cpu6-bottom-thermal { 4594 polling-delay-passive = <0>; 4595 polling-delay = <0>; 4596 thermal-sensors = <&tsens0 10>; 4597 4598 trips { 4599 cpu6_bottom_alert0: trip-point0 { 4600 temperature = <90000>; 4601 hysteresis = <2000>; 4602 type = "passive"; 4603 }; 4604 4605 cpu6_bottom_alert1: trip-point1 { 4606 temperature = <95000>; 4607 hysteresis = <2000>; 4608 type = "passive"; 4609 }; 4610 4611 cpu6_bottom_crit: cpu-crit { 4612 temperature = <110000>; 4613 hysteresis = <1000>; 4614 type = "critical"; 4615 }; 4616 }; 4617 }; 4618 4619 cpu7-top-thermal { 4620 polling-delay-passive = <0>; 4621 polling-delay = <0>; 4622 thermal-sensors = <&tsens0 11>; 4623 4624 trips { 4625 cpu7_top_alert0: trip-point0 { 4626 temperature = <90000>; 4627 hysteresis = <2000>; 4628 type = "passive"; 4629 }; 4630 4631 cpu7_top_alert1: trip-point1 { 4632 temperature = <95000>; 4633 hysteresis = <2000>; 4634 type = "passive"; 4635 }; 4636 4637 cpu7_top_crit: cpu-crit { 4638 temperature = <110000>; 4639 hysteresis = <1000>; 4640 type = "critical"; 4641 }; 4642 }; 4643 }; 4644 4645 cpu7-middle-thermal { 4646 polling-delay-passive = <0>; 4647 polling-delay = <0>; 4648 thermal-sensors = <&tsens0 12>; 4649 4650 trips { 4651 cpu7_middle_alert0: trip-point0 { 4652 temperature = <90000>; 4653 hysteresis = <2000>; 4654 type = "passive"; 4655 }; 4656 4657 cpu7_middle_alert1: trip-point1 { 4658 temperature = <95000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu7_middle_crit: cpu-crit { 4664 temperature = <110000>; 4665 hysteresis = <1000>; 4666 type = "critical"; 4667 }; 4668 }; 4669 }; 4670 4671 cpu7-bottom-thermal { 4672 polling-delay-passive = <0>; 4673 polling-delay = <0>; 4674 thermal-sensors = <&tsens0 13>; 4675 4676 trips { 4677 cpu7_bottom_alert0: trip-point0 { 4678 temperature = <90000>; 4679 hysteresis = <2000>; 4680 type = "passive"; 4681 }; 4682 4683 cpu7_bottom_alert1: trip-point1 { 4684 temperature = <95000>; 4685 hysteresis = <2000>; 4686 type = "passive"; 4687 }; 4688 4689 cpu7_bottom_crit: cpu-crit { 4690 temperature = <110000>; 4691 hysteresis = <1000>; 4692 type = "critical"; 4693 }; 4694 }; 4695 }; 4696 4697 gpu-top-thermal { 4698 polling-delay-passive = <10>; 4699 polling-delay = <0>; 4700 thermal-sensors = <&tsens0 14>; 4701 4702 trips { 4703 thermal-engine-config { 4704 temperature = <125000>; 4705 hysteresis = <1000>; 4706 type = "passive"; 4707 }; 4708 4709 thermal-hal-config { 4710 temperature = <125000>; 4711 hysteresis = <1000>; 4712 type = "passive"; 4713 }; 4714 4715 reset-mon-cfg { 4716 temperature = <115000>; 4717 hysteresis = <5000>; 4718 type = "passive"; 4719 }; 4720 4721 gpu0_tj_cfg: tj-cfg { 4722 temperature = <95000>; 4723 hysteresis = <5000>; 4724 type = "passive"; 4725 }; 4726 }; 4727 }; 4728 4729 gpu-bottom-thermal { 4730 polling-delay-passive = <10>; 4731 polling-delay = <0>; 4732 thermal-sensors = <&tsens0 15>; 4733 4734 trips { 4735 thermal-engine-config { 4736 temperature = <125000>; 4737 hysteresis = <1000>; 4738 type = "passive"; 4739 }; 4740 4741 thermal-hal-config { 4742 temperature = <125000>; 4743 hysteresis = <1000>; 4744 type = "passive"; 4745 }; 4746 4747 reset-mon-cfg { 4748 temperature = <115000>; 4749 hysteresis = <5000>; 4750 type = "passive"; 4751 }; 4752 4753 gpu1_tj_cfg: tj-cfg { 4754 temperature = <95000>; 4755 hysteresis = <5000>; 4756 type = "passive"; 4757 }; 4758 }; 4759 }; 4760 4761 aoss1-thermal { 4762 polling-delay-passive = <0>; 4763 polling-delay = <0>; 4764 thermal-sensors = <&tsens1 0>; 4765 4766 trips { 4767 thermal-engine-config { 4768 temperature = <125000>; 4769 hysteresis = <1000>; 4770 type = "passive"; 4771 }; 4772 4773 reset-mon-cfg { 4774 temperature = <115000>; 4775 hysteresis = <5000>; 4776 type = "passive"; 4777 }; 4778 }; 4779 }; 4780 4781 cpu0-thermal { 4782 polling-delay-passive = <0>; 4783 polling-delay = <0>; 4784 thermal-sensors = <&tsens1 1>; 4785 4786 trips { 4787 cpu0_alert0: trip-point0 { 4788 temperature = <90000>; 4789 hysteresis = <2000>; 4790 type = "passive"; 4791 }; 4792 4793 cpu0_alert1: trip-point1 { 4794 temperature = <95000>; 4795 hysteresis = <2000>; 4796 type = "passive"; 4797 }; 4798 4799 cpu0_crit: cpu-crit { 4800 temperature = <110000>; 4801 hysteresis = <1000>; 4802 type = "critical"; 4803 }; 4804 }; 4805 }; 4806 4807 cpu1-thermal { 4808 polling-delay-passive = <0>; 4809 polling-delay = <0>; 4810 thermal-sensors = <&tsens1 2>; 4811 4812 trips { 4813 cpu1_alert0: trip-point0 { 4814 temperature = <90000>; 4815 hysteresis = <2000>; 4816 type = "passive"; 4817 }; 4818 4819 cpu1_alert1: trip-point1 { 4820 temperature = <95000>; 4821 hysteresis = <2000>; 4822 type = "passive"; 4823 }; 4824 4825 cpu1_crit: cpu-crit { 4826 temperature = <110000>; 4827 hysteresis = <1000>; 4828 type = "critical"; 4829 }; 4830 }; 4831 }; 4832 4833 cpu2-thermal { 4834 polling-delay-passive = <0>; 4835 polling-delay = <0>; 4836 thermal-sensors = <&tsens1 3>; 4837 4838 trips { 4839 cpu2_alert0: trip-point0 { 4840 temperature = <90000>; 4841 hysteresis = <2000>; 4842 type = "passive"; 4843 }; 4844 4845 cpu2_alert1: trip-point1 { 4846 temperature = <95000>; 4847 hysteresis = <2000>; 4848 type = "passive"; 4849 }; 4850 4851 cpu2_crit: cpu-crit { 4852 temperature = <110000>; 4853 hysteresis = <1000>; 4854 type = "critical"; 4855 }; 4856 }; 4857 }; 4858 4859 cpu3-thermal { 4860 polling-delay-passive = <0>; 4861 polling-delay = <0>; 4862 thermal-sensors = <&tsens1 4>; 4863 4864 trips { 4865 cpu3_alert0: trip-point0 { 4866 temperature = <90000>; 4867 hysteresis = <2000>; 4868 type = "passive"; 4869 }; 4870 4871 cpu3_alert1: trip-point1 { 4872 temperature = <95000>; 4873 hysteresis = <2000>; 4874 type = "passive"; 4875 }; 4876 4877 cpu3_crit: cpu-crit { 4878 temperature = <110000>; 4879 hysteresis = <1000>; 4880 type = "critical"; 4881 }; 4882 }; 4883 }; 4884 4885 cdsp0-thermal { 4886 polling-delay-passive = <10>; 4887 polling-delay = <0>; 4888 thermal-sensors = <&tsens1 5>; 4889 4890 trips { 4891 thermal-engine-config { 4892 temperature = <125000>; 4893 hysteresis = <1000>; 4894 type = "passive"; 4895 }; 4896 4897 thermal-hal-config { 4898 temperature = <125000>; 4899 hysteresis = <1000>; 4900 type = "passive"; 4901 }; 4902 4903 reset-mon-cfg { 4904 temperature = <115000>; 4905 hysteresis = <5000>; 4906 type = "passive"; 4907 }; 4908 4909 cdsp_0_config: junction-config { 4910 temperature = <95000>; 4911 hysteresis = <5000>; 4912 type = "passive"; 4913 }; 4914 }; 4915 }; 4916 4917 cdsp1-thermal { 4918 polling-delay-passive = <10>; 4919 polling-delay = <0>; 4920 thermal-sensors = <&tsens1 6>; 4921 4922 trips { 4923 thermal-engine-config { 4924 temperature = <125000>; 4925 hysteresis = <1000>; 4926 type = "passive"; 4927 }; 4928 4929 thermal-hal-config { 4930 temperature = <125000>; 4931 hysteresis = <1000>; 4932 type = "passive"; 4933 }; 4934 4935 reset-mon-cfg { 4936 temperature = <115000>; 4937 hysteresis = <5000>; 4938 type = "passive"; 4939 }; 4940 4941 cdsp_1_config: junction-config { 4942 temperature = <95000>; 4943 hysteresis = <5000>; 4944 type = "passive"; 4945 }; 4946 }; 4947 }; 4948 4949 cdsp2-thermal { 4950 polling-delay-passive = <10>; 4951 polling-delay = <0>; 4952 thermal-sensors = <&tsens1 7>; 4953 4954 trips { 4955 thermal-engine-config { 4956 temperature = <125000>; 4957 hysteresis = <1000>; 4958 type = "passive"; 4959 }; 4960 4961 thermal-hal-config { 4962 temperature = <125000>; 4963 hysteresis = <1000>; 4964 type = "passive"; 4965 }; 4966 4967 reset-mon-cfg { 4968 temperature = <115000>; 4969 hysteresis = <5000>; 4970 type = "passive"; 4971 }; 4972 4973 cdsp_2_config: junction-config { 4974 temperature = <95000>; 4975 hysteresis = <5000>; 4976 type = "passive"; 4977 }; 4978 }; 4979 }; 4980 4981 video-thermal { 4982 polling-delay-passive = <0>; 4983 polling-delay = <0>; 4984 thermal-sensors = <&tsens1 8>; 4985 4986 trips { 4987 thermal-engine-config { 4988 temperature = <125000>; 4989 hysteresis = <1000>; 4990 type = "passive"; 4991 }; 4992 4993 reset-mon-cfg { 4994 temperature = <115000>; 4995 hysteresis = <5000>; 4996 type = "passive"; 4997 }; 4998 }; 4999 }; 5000 5001 mem-thermal { 5002 polling-delay-passive = <10>; 5003 polling-delay = <0>; 5004 thermal-sensors = <&tsens1 9>; 5005 5006 trips { 5007 thermal-engine-config { 5008 temperature = <125000>; 5009 hysteresis = <1000>; 5010 type = "passive"; 5011 }; 5012 5013 ddr_config0: ddr0-config { 5014 temperature = <90000>; 5015 hysteresis = <5000>; 5016 type = "passive"; 5017 }; 5018 5019 reset-mon-cfg { 5020 temperature = <115000>; 5021 hysteresis = <5000>; 5022 type = "passive"; 5023 }; 5024 }; 5025 }; 5026 5027 modem0-thermal { 5028 polling-delay-passive = <0>; 5029 polling-delay = <0>; 5030 thermal-sensors = <&tsens1 10>; 5031 5032 trips { 5033 thermal-engine-config { 5034 temperature = <125000>; 5035 hysteresis = <1000>; 5036 type = "passive"; 5037 }; 5038 5039 mdmss0_config0: mdmss0-config0 { 5040 temperature = <102000>; 5041 hysteresis = <3000>; 5042 type = "passive"; 5043 }; 5044 5045 mdmss0_config1: mdmss0-config1 { 5046 temperature = <105000>; 5047 hysteresis = <3000>; 5048 type = "passive"; 5049 }; 5050 5051 reset-mon-cfg { 5052 temperature = <115000>; 5053 hysteresis = <5000>; 5054 type = "passive"; 5055 }; 5056 }; 5057 }; 5058 5059 modem1-thermal { 5060 polling-delay-passive = <0>; 5061 polling-delay = <0>; 5062 thermal-sensors = <&tsens1 11>; 5063 5064 trips { 5065 thermal-engine-config { 5066 temperature = <125000>; 5067 hysteresis = <1000>; 5068 type = "passive"; 5069 }; 5070 5071 mdmss1_config0: mdmss1-config0 { 5072 temperature = <102000>; 5073 hysteresis = <3000>; 5074 type = "passive"; 5075 }; 5076 5077 mdmss1_config1: mdmss1-config1 { 5078 temperature = <105000>; 5079 hysteresis = <3000>; 5080 type = "passive"; 5081 }; 5082 5083 reset-mon-cfg { 5084 temperature = <115000>; 5085 hysteresis = <5000>; 5086 type = "passive"; 5087 }; 5088 }; 5089 }; 5090 5091 modem2-thermal { 5092 polling-delay-passive = <0>; 5093 polling-delay = <0>; 5094 thermal-sensors = <&tsens1 12>; 5095 5096 trips { 5097 thermal-engine-config { 5098 temperature = <125000>; 5099 hysteresis = <1000>; 5100 type = "passive"; 5101 }; 5102 5103 mdmss2_config0: mdmss2-config0 { 5104 temperature = <102000>; 5105 hysteresis = <3000>; 5106 type = "passive"; 5107 }; 5108 5109 mdmss2_config1: mdmss2-config1 { 5110 temperature = <105000>; 5111 hysteresis = <3000>; 5112 type = "passive"; 5113 }; 5114 5115 reset-mon-cfg { 5116 temperature = <115000>; 5117 hysteresis = <5000>; 5118 type = "passive"; 5119 }; 5120 }; 5121 }; 5122 5123 modem3-thermal { 5124 polling-delay-passive = <0>; 5125 polling-delay = <0>; 5126 thermal-sensors = <&tsens1 13>; 5127 5128 trips { 5129 thermal-engine-config { 5130 temperature = <125000>; 5131 hysteresis = <1000>; 5132 type = "passive"; 5133 }; 5134 5135 mdmss3_config0: mdmss3-config0 { 5136 temperature = <102000>; 5137 hysteresis = <3000>; 5138 type = "passive"; 5139 }; 5140 5141 mdmss3_config1: mdmss3-config1 { 5142 temperature = <105000>; 5143 hysteresis = <3000>; 5144 type = "passive"; 5145 }; 5146 5147 reset-mon-cfg { 5148 temperature = <115000>; 5149 hysteresis = <5000>; 5150 type = "passive"; 5151 }; 5152 }; 5153 }; 5154 5155 camera0-thermal { 5156 polling-delay-passive = <0>; 5157 polling-delay = <0>; 5158 thermal-sensors = <&tsens1 14>; 5159 5160 trips { 5161 thermal-engine-config { 5162 temperature = <125000>; 5163 hysteresis = <1000>; 5164 type = "passive"; 5165 }; 5166 5167 reset-mon-cfg { 5168 temperature = <115000>; 5169 hysteresis = <5000>; 5170 type = "passive"; 5171 }; 5172 }; 5173 }; 5174 5175 camera1-thermal { 5176 polling-delay-passive = <0>; 5177 polling-delay = <0>; 5178 thermal-sensors = <&tsens1 15>; 5179 5180 trips { 5181 thermal-engine-config { 5182 temperature = <125000>; 5183 hysteresis = <1000>; 5184 type = "passive"; 5185 }; 5186 5187 reset-mon-cfg { 5188 temperature = <115000>; 5189 hysteresis = <5000>; 5190 type = "passive"; 5191 }; 5192 }; 5193 }; 5194 }; 5195 5196 timer { 5197 compatible = "arm,armv8-timer"; 5198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5202 clock-frequency = <19200000>; 5203 }; 5204}; 5205