xref: /openbmc/linux/arch/arm64/boot/dts/qcom/sm8350.dtsi (revision f16fe2d3) 
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, Linaro Limited
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-sm8350.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interconnect/qcom,sm8350.h>
11#include <dt-bindings/mailbox/qcom-ipcc.h>
12#include <dt-bindings/power/qcom-rpmpd.h>
13#include <dt-bindings/soc/qcom,rpmh-rsc.h>
14#include <dt-bindings/thermal/thermal.h>
15#include <dt-bindings/interconnect/qcom,sm8350.h>
16
17/ {
18	interrupt-parent = <&intc>;
19
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	chosen { };
24
25	clocks {
26		xo_board: xo-board {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <38400000>;
30			clock-output-names = "xo_board";
31		};
32
33		sleep_clk: sleep-clk {
34			compatible = "fixed-clock";
35			clock-frequency = <32000>;
36			#clock-cells = <0>;
37		};
38	};
39
40	cpus {
41		#address-cells = <2>;
42		#size-cells = <0>;
43
44		CPU0: cpu@0 {
45			device_type = "cpu";
46			compatible = "qcom,kryo685";
47			reg = <0x0 0x0>;
48			enable-method = "psci";
49			next-level-cache = <&L2_0>;
50			qcom,freq-domain = <&cpufreq_hw 0>;
51			power-domains = <&CPU_PD0>;
52			power-domain-names = "psci";
53			#cooling-cells = <2>;
54			L2_0: l2-cache {
55			      compatible = "cache";
56			      next-level-cache = <&L3_0>;
57				L3_0: l3-cache {
58				      compatible = "cache";
59				};
60			};
61		};
62
63		CPU1: cpu@100 {
64			device_type = "cpu";
65			compatible = "qcom,kryo685";
66			reg = <0x0 0x100>;
67			enable-method = "psci";
68			next-level-cache = <&L2_100>;
69			qcom,freq-domain = <&cpufreq_hw 0>;
70			power-domains = <&CPU_PD1>;
71			power-domain-names = "psci";
72			#cooling-cells = <2>;
73			L2_100: l2-cache {
74			      compatible = "cache";
75			      next-level-cache = <&L3_0>;
76			};
77		};
78
79		CPU2: cpu@200 {
80			device_type = "cpu";
81			compatible = "qcom,kryo685";
82			reg = <0x0 0x200>;
83			enable-method = "psci";
84			next-level-cache = <&L2_200>;
85			qcom,freq-domain = <&cpufreq_hw 0>;
86			power-domains = <&CPU_PD2>;
87			power-domain-names = "psci";
88			#cooling-cells = <2>;
89			L2_200: l2-cache {
90			      compatible = "cache";
91			      next-level-cache = <&L3_0>;
92			};
93		};
94
95		CPU3: cpu@300 {
96			device_type = "cpu";
97			compatible = "qcom,kryo685";
98			reg = <0x0 0x300>;
99			enable-method = "psci";
100			next-level-cache = <&L2_300>;
101			qcom,freq-domain = <&cpufreq_hw 0>;
102			power-domains = <&CPU_PD3>;
103			power-domain-names = "psci";
104			#cooling-cells = <2>;
105			L2_300: l2-cache {
106			      compatible = "cache";
107			      next-level-cache = <&L3_0>;
108			};
109		};
110
111		CPU4: cpu@400 {
112			device_type = "cpu";
113			compatible = "qcom,kryo685";
114			reg = <0x0 0x400>;
115			enable-method = "psci";
116			next-level-cache = <&L2_400>;
117			qcom,freq-domain = <&cpufreq_hw 1>;
118			power-domains = <&CPU_PD4>;
119			power-domain-names = "psci";
120			#cooling-cells = <2>;
121			L2_400: l2-cache {
122			      compatible = "cache";
123			      next-level-cache = <&L3_0>;
124			};
125		};
126
127		CPU5: cpu@500 {
128			device_type = "cpu";
129			compatible = "qcom,kryo685";
130			reg = <0x0 0x500>;
131			enable-method = "psci";
132			next-level-cache = <&L2_500>;
133			qcom,freq-domain = <&cpufreq_hw 1>;
134			power-domains = <&CPU_PD5>;
135			power-domain-names = "psci";
136			#cooling-cells = <2>;
137			L2_500: l2-cache {
138			      compatible = "cache";
139			      next-level-cache = <&L3_0>;
140			};
141
142		};
143
144		CPU6: cpu@600 {
145			device_type = "cpu";
146			compatible = "qcom,kryo685";
147			reg = <0x0 0x600>;
148			enable-method = "psci";
149			next-level-cache = <&L2_600>;
150			qcom,freq-domain = <&cpufreq_hw 1>;
151			power-domains = <&CPU_PD6>;
152			power-domain-names = "psci";
153			#cooling-cells = <2>;
154			L2_600: l2-cache {
155			      compatible = "cache";
156			      next-level-cache = <&L3_0>;
157			};
158		};
159
160		CPU7: cpu@700 {
161			device_type = "cpu";
162			compatible = "qcom,kryo685";
163			reg = <0x0 0x700>;
164			enable-method = "psci";
165			next-level-cache = <&L2_700>;
166			qcom,freq-domain = <&cpufreq_hw 2>;
167			power-domains = <&CPU_PD7>;
168			power-domain-names = "psci";
169			#cooling-cells = <2>;
170			L2_700: l2-cache {
171			      compatible = "cache";
172			      next-level-cache = <&L3_0>;
173			};
174		};
175
176		cpu-map {
177			cluster0 {
178				core0 {
179					cpu = <&CPU0>;
180				};
181
182				core1 {
183					cpu = <&CPU1>;
184				};
185
186				core2 {
187					cpu = <&CPU2>;
188				};
189
190				core3 {
191					cpu = <&CPU3>;
192				};
193
194				core4 {
195					cpu = <&CPU4>;
196				};
197
198				core5 {
199					cpu = <&CPU5>;
200				};
201
202				core6 {
203					cpu = <&CPU6>;
204				};
205
206				core7 {
207					cpu = <&CPU7>;
208				};
209			};
210		};
211
212		idle-states {
213			entry-method = "psci";
214
215			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
216				compatible = "arm,idle-state";
217				idle-state-name = "silver-rail-power-collapse";
218				arm,psci-suspend-param = <0x40000004>;
219				entry-latency-us = <355>;
220				exit-latency-us = <909>;
221				min-residency-us = <3934>;
222				local-timer-stop;
223			};
224
225			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
226				compatible = "arm,idle-state";
227				idle-state-name = "gold-rail-power-collapse";
228				arm,psci-suspend-param = <0x40000004>;
229				entry-latency-us = <241>;
230				exit-latency-us = <1461>;
231				min-residency-us = <4488>;
232				local-timer-stop;
233			};
234		};
235
236		domain-idle-states {
237			CLUSTER_SLEEP_0: cluster-sleep-0 {
238				compatible = "domain-idle-state";
239				idle-state-name = "cluster-power-collapse";
240				arm,psci-suspend-param = <0x4100c344>;
241				entry-latency-us = <3263>;
242				exit-latency-us = <6562>;
243				min-residency-us = <9987>;
244				local-timer-stop;
245			};
246		};
247	};
248
249	firmware {
250		scm: scm {
251			compatible = "qcom,scm-sm8350", "qcom,scm";
252			#reset-cells = <1>;
253		};
254	};
255
256	memory@80000000 {
257		device_type = "memory";
258		/* We expect the bootloader to fill in the size */
259		reg = <0x0 0x80000000 0x0 0x0>;
260	};
261
262	pmu {
263		compatible = "arm,armv8-pmuv3";
264		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
265	};
266
267	psci {
268		compatible = "arm,psci-1.0";
269		method = "smc";
270
271		CPU_PD0: cpu0 {
272			#power-domain-cells = <0>;
273			power-domains = <&CLUSTER_PD>;
274			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
275		};
276
277		CPU_PD1: cpu1 {
278			#power-domain-cells = <0>;
279			power-domains = <&CLUSTER_PD>;
280			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
281		};
282
283		CPU_PD2: cpu2 {
284			#power-domain-cells = <0>;
285			power-domains = <&CLUSTER_PD>;
286			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
287		};
288
289		CPU_PD3: cpu3 {
290			#power-domain-cells = <0>;
291			power-domains = <&CLUSTER_PD>;
292			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
293		};
294
295		CPU_PD4: cpu4 {
296			#power-domain-cells = <0>;
297			power-domains = <&CLUSTER_PD>;
298			domain-idle-states = <&BIG_CPU_SLEEP_0>;
299		};
300
301		CPU_PD5: cpu5 {
302			#power-domain-cells = <0>;
303			power-domains = <&CLUSTER_PD>;
304			domain-idle-states = <&BIG_CPU_SLEEP_0>;
305		};
306
307		CPU_PD6: cpu6 {
308			#power-domain-cells = <0>;
309			power-domains = <&CLUSTER_PD>;
310			domain-idle-states = <&BIG_CPU_SLEEP_0>;
311		};
312
313		CPU_PD7: cpu7 {
314			#power-domain-cells = <0>;
315			power-domains = <&CLUSTER_PD>;
316			domain-idle-states = <&BIG_CPU_SLEEP_0>;
317		};
318
319		CLUSTER_PD: cpu-cluster0 {
320			#power-domain-cells = <0>;
321			domain-idle-states = <&CLUSTER_SLEEP_0>;
322		};
323	};
324
325	reserved_memory: reserved-memory {
326		#address-cells = <2>;
327		#size-cells = <2>;
328		ranges;
329
330		hyp_mem: memory@80000000 {
331			reg = <0x0 0x80000000 0x0 0x600000>;
332			no-map;
333		};
334
335		xbl_aop_mem: memory@80700000 {
336			no-map;
337			reg = <0x0 0x80700000 0x0 0x160000>;
338		};
339
340		cmd_db: memory@80860000 {
341			compatible = "qcom,cmd-db";
342			reg = <0x0 0x80860000 0x0 0x20000>;
343			no-map;
344		};
345
346		reserved_xbl_uefi_log: memory@80880000 {
347			reg = <0x0 0x80880000 0x0 0x14000>;
348			no-map;
349		};
350
351		smem_mem: memory@80900000 {
352			reg = <0x0 0x80900000 0x0 0x200000>;
353			no-map;
354		};
355
356		cpucp_fw_mem: memory@80b00000 {
357			reg = <0x0 0x80b00000 0x0 0x100000>;
358			no-map;
359		};
360
361		cdsp_secure_heap: memory@80c00000 {
362			reg = <0x0 0x80c00000 0x0 0x4600000>;
363			no-map;
364		};
365
366		pil_camera_mem: mmeory@85200000 {
367			reg = <0x0 0x85200000 0x0 0x500000>;
368			no-map;
369		};
370
371		pil_video_mem: memory@85700000 {
372			reg = <0x0 0x85700000 0x0 0x500000>;
373			no-map;
374		};
375
376		pil_cvp_mem: memory@85c00000 {
377			reg = <0x0 0x85c00000 0x0 0x500000>;
378			no-map;
379		};
380
381		pil_adsp_mem: memory@86100000 {
382			reg = <0x0 0x86100000 0x0 0x2100000>;
383			no-map;
384		};
385
386		pil_slpi_mem: memory@88200000 {
387			reg = <0x0 0x88200000 0x0 0x1500000>;
388			no-map;
389		};
390
391		pil_cdsp_mem: memory@89700000 {
392			reg = <0x0 0x89700000 0x0 0x1e00000>;
393			no-map;
394		};
395
396		pil_ipa_fw_mem: memory@8b500000 {
397			reg = <0x0 0x8b500000 0x0 0x10000>;
398			no-map;
399		};
400
401		pil_ipa_gsi_mem: memory@8b510000 {
402			reg = <0x0 0x8b510000 0x0 0xa000>;
403			no-map;
404		};
405
406		pil_gpu_mem: memory@8b51a000 {
407			reg = <0x0 0x8b51a000 0x0 0x2000>;
408			no-map;
409		};
410
411		pil_spss_mem: memory@8b600000 {
412			reg = <0x0 0x8b600000 0x0 0x100000>;
413			no-map;
414		};
415
416		pil_modem_mem: memory@8b800000 {
417			reg = <0x0 0x8b800000 0x0 0x10000000>;
418			no-map;
419		};
420
421		rmtfs_mem: memory@9b800000 {
422			compatible = "qcom,rmtfs-mem";
423			reg = <0x0 0x9b800000 0x0 0x280000>;
424			no-map;
425
426			qcom,client-id = <1>;
427			qcom,vmid = <15>;
428		};
429
430		hyp_reserved_mem: memory@d0000000 {
431			reg = <0x0 0xd0000000 0x0 0x800000>;
432			no-map;
433		};
434
435		pil_trustedvm_mem: memory@d0800000 {
436			reg = <0x0 0xd0800000 0x0 0x76f7000>;
437			no-map;
438		};
439
440		qrtr_shbuf: memory@d7ef7000 {
441			reg = <0x0 0xd7ef7000 0x0 0x9000>;
442			no-map;
443		};
444
445		chan0_shbuf: memory@d7f00000 {
446			reg = <0x0 0xd7f00000 0x0 0x80000>;
447			no-map;
448		};
449
450		chan1_shbuf: memory@d7f80000 {
451			reg = <0x0 0xd7f80000 0x0 0x80000>;
452			no-map;
453		};
454
455		removed_mem: memory@d8800000 {
456			reg = <0x0 0xd8800000 0x0 0x6800000>;
457			no-map;
458		};
459	};
460
461	smem: qcom,smem {
462		compatible = "qcom,smem";
463		memory-region = <&smem_mem>;
464		hwlocks = <&tcsr_mutex 3>;
465	};
466
467	smp2p-adsp {
468		compatible = "qcom,smp2p";
469		qcom,smem = <443>, <429>;
470		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
471					     IPCC_MPROC_SIGNAL_SMP2P
472					     IRQ_TYPE_EDGE_RISING>;
473		mboxes = <&ipcc IPCC_CLIENT_LPASS
474				IPCC_MPROC_SIGNAL_SMP2P>;
475
476		qcom,local-pid = <0>;
477		qcom,remote-pid = <2>;
478
479		smp2p_adsp_out: master-kernel {
480			qcom,entry-name = "master-kernel";
481			#qcom,smem-state-cells = <1>;
482		};
483
484		smp2p_adsp_in: slave-kernel {
485			qcom,entry-name = "slave-kernel";
486			interrupt-controller;
487			#interrupt-cells = <2>;
488		};
489	};
490
491	smp2p-cdsp {
492		compatible = "qcom,smp2p";
493		qcom,smem = <94>, <432>;
494		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
495					     IPCC_MPROC_SIGNAL_SMP2P
496					     IRQ_TYPE_EDGE_RISING>;
497		mboxes = <&ipcc IPCC_CLIENT_CDSP
498				IPCC_MPROC_SIGNAL_SMP2P>;
499
500		qcom,local-pid = <0>;
501		qcom,remote-pid = <5>;
502
503		smp2p_cdsp_out: master-kernel {
504			qcom,entry-name = "master-kernel";
505			#qcom,smem-state-cells = <1>;
506		};
507
508		smp2p_cdsp_in: slave-kernel {
509			qcom,entry-name = "slave-kernel";
510			interrupt-controller;
511			#interrupt-cells = <2>;
512		};
513	};
514
515	smp2p-modem {
516		compatible = "qcom,smp2p";
517		qcom,smem = <435>, <428>;
518		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
519					     IPCC_MPROC_SIGNAL_SMP2P
520					     IRQ_TYPE_EDGE_RISING>;
521		mboxes = <&ipcc IPCC_CLIENT_MPSS
522				IPCC_MPROC_SIGNAL_SMP2P>;
523
524		qcom,local-pid = <0>;
525		qcom,remote-pid = <1>;
526
527		smp2p_modem_out: master-kernel {
528			qcom,entry-name = "master-kernel";
529			#qcom,smem-state-cells = <1>;
530		};
531
532		smp2p_modem_in: slave-kernel {
533			qcom,entry-name = "slave-kernel";
534			interrupt-controller;
535			#interrupt-cells = <2>;
536		};
537
538		ipa_smp2p_out: ipa-ap-to-modem {
539			qcom,entry-name = "ipa";
540			#qcom,smem-state-cells = <1>;
541		};
542
543		ipa_smp2p_in: ipa-modem-to-ap {
544			qcom,entry-name = "ipa";
545			interrupt-controller;
546			#interrupt-cells = <2>;
547		};
548	};
549
550	smp2p-slpi {
551		compatible = "qcom,smp2p";
552		qcom,smem = <481>, <430>;
553		interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
554					     IPCC_MPROC_SIGNAL_SMP2P
555					     IRQ_TYPE_EDGE_RISING>;
556		mboxes = <&ipcc IPCC_CLIENT_SLPI
557				IPCC_MPROC_SIGNAL_SMP2P>;
558
559		qcom,local-pid = <0>;
560		qcom,remote-pid = <3>;
561
562		smp2p_slpi_out: master-kernel {
563			qcom,entry-name = "master-kernel";
564			#qcom,smem-state-cells = <1>;
565		};
566
567		smp2p_slpi_in: slave-kernel {
568			qcom,entry-name = "slave-kernel";
569			interrupt-controller;
570			#interrupt-cells = <2>;
571		};
572	};
573
574	soc: soc@0 {
575		#address-cells = <2>;
576		#size-cells = <2>;
577		ranges = <0 0 0 0 0x10 0>;
578		dma-ranges = <0 0 0 0 0x10 0>;
579		compatible = "simple-bus";
580
581		gcc: clock-controller@100000 {
582			compatible = "qcom,gcc-sm8350";
583			reg = <0x0 0x00100000 0x0 0x1f0000>;
584			#clock-cells = <1>;
585			#reset-cells = <1>;
586			#power-domain-cells = <1>;
587			clock-names = "bi_tcxo",
588				      "sleep_clk",
589				      "pcie_0_pipe_clk",
590				      "pcie_1_pipe_clk",
591				      "ufs_card_rx_symbol_0_clk",
592				      "ufs_card_rx_symbol_1_clk",
593				      "ufs_card_tx_symbol_0_clk",
594				      "ufs_phy_rx_symbol_0_clk",
595				      "ufs_phy_rx_symbol_1_clk",
596				      "ufs_phy_tx_symbol_0_clk",
597				      "usb3_phy_wrapper_gcc_usb30_pipe_clk",
598				      "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
599			clocks = <&rpmhcc RPMH_CXO_CLK>,
600				 <&sleep_clk>,
601				 <0>,
602				 <0>,
603				 <0>,
604				 <0>,
605				 <0>,
606				 <0>,
607				 <0>,
608				 <0>,
609				 <0>,
610				 <0>;
611		};
612
613		ipcc: mailbox@408000 {
614			compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
615			reg = <0 0x00408000 0 0x1000>;
616			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
617			interrupt-controller;
618			#interrupt-cells = <3>;
619			#mbox-cells = <2>;
620		};
621
622		qup_opp_table_100mhz: qup-100mhz-opp-table {
623			compatible = "operating-points-v2";
624
625			opp-50000000 {
626				opp-hz = /bits/ 64 <50000000>;
627				required-opps = <&rpmhpd_opp_min_svs>;
628			};
629
630			opp-75000000 {
631				opp-hz = /bits/ 64 <75000000>;
632				required-opps = <&rpmhpd_opp_low_svs>;
633			};
634
635			opp-100000000 {
636				opp-hz = /bits/ 64 <100000000>;
637				required-opps = <&rpmhpd_opp_svs>;
638			};
639		};
640
641		qup_opp_table_120mhz: qup-120mhz-opp-table {
642			compatible = "operating-points-v2";
643
644			opp-50000000 {
645				opp-hz = /bits/ 64 <50000000>;
646				required-opps = <&rpmhpd_opp_min_svs>;
647			};
648
649			opp-75000000 {
650				opp-hz = /bits/ 64 <75000000>;
651				required-opps = <&rpmhpd_opp_low_svs>;
652			};
653
654			opp-120000000 {
655				opp-hz = /bits/ 64 <120000000>;
656				required-opps = <&rpmhpd_opp_svs>;
657			};
658		};
659
660		qupv3_id_2: geniqup@8c0000 {
661			compatible = "qcom,geni-se-qup";
662			reg = <0x0 0x008c0000 0x0 0x6000>;
663			clock-names = "m-ahb", "s-ahb";
664			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
665				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
666			iommus = <&apps_smmu 0x5e3 0x0>;
667			#address-cells = <2>;
668			#size-cells = <2>;
669			ranges;
670			status = "disabled";
671
672			i2c14: i2c@880000 {
673				compatible = "qcom,geni-i2c";
674				reg = <0 0x00880000 0 0x4000>;
675				clock-names = "se";
676				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
677				pinctrl-names = "default";
678				pinctrl-0 = <&qup_i2c14_default>;
679				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
680				#address-cells = <1>;
681				#size-cells = <0>;
682				status = "disabled";
683			};
684
685			spi14: spi@880000 {
686				compatible = "qcom,geni-spi";
687				reg = <0 0x00880000 0 0x4000>;
688				clock-names = "se";
689				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
690				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
691				power-domains = <&rpmhpd SM8350_CX>;
692				operating-points-v2 = <&qup_opp_table_120mhz>;
693				#address-cells = <1>;
694				#size-cells = <0>;
695				status = "disabled";
696			};
697
698			i2c15: i2c@884000 {
699				compatible = "qcom,geni-i2c";
700				reg = <0 0x00884000 0 0x4000>;
701				clock-names = "se";
702				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
703				pinctrl-names = "default";
704				pinctrl-0 = <&qup_i2c15_default>;
705				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
706				#address-cells = <1>;
707				#size-cells = <0>;
708				status = "disabled";
709			};
710
711			spi15: spi@884000 {
712				compatible = "qcom,geni-spi";
713				reg = <0 0x00884000 0 0x4000>;
714				clock-names = "se";
715				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
716				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
717				power-domains = <&rpmhpd SM8350_CX>;
718				operating-points-v2 = <&qup_opp_table_120mhz>;
719				#address-cells = <1>;
720				#size-cells = <0>;
721				status = "disabled";
722			};
723
724			i2c16: i2c@888000 {
725				compatible = "qcom,geni-i2c";
726				reg = <0 0x00888000 0 0x4000>;
727				clock-names = "se";
728				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
729				pinctrl-names = "default";
730				pinctrl-0 = <&qup_i2c16_default>;
731				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
732				#address-cells = <1>;
733				#size-cells = <0>;
734				status = "disabled";
735			};
736
737			spi16: spi@888000 {
738				compatible = "qcom,geni-spi";
739				reg = <0 0x00888000 0 0x4000>;
740				clock-names = "se";
741				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
742				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
743				power-domains = <&rpmhpd SM8350_CX>;
744				operating-points-v2 = <&qup_opp_table_100mhz>;
745				#address-cells = <1>;
746				#size-cells = <0>;
747				status = "disabled";
748			};
749
750			i2c17: i2c@88c000 {
751				compatible = "qcom,geni-i2c";
752				reg = <0 0x0088c000 0 0x4000>;
753				clock-names = "se";
754				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
755				pinctrl-names = "default";
756				pinctrl-0 = <&qup_i2c17_default>;
757				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
758				#address-cells = <1>;
759				#size-cells = <0>;
760				status = "disabled";
761			};
762
763			spi17: spi@88c000 {
764				compatible = "qcom,geni-spi";
765				reg = <0 0x0088c000 0 0x4000>;
766				clock-names = "se";
767				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
768				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
769				power-domains = <&rpmhpd SM8350_CX>;
770				operating-points-v2 = <&qup_opp_table_100mhz>;
771				#address-cells = <1>;
772				#size-cells = <0>;
773				status = "disabled";
774			};
775
776			/* QUP no. 18 seems to be strictly SPI/UART-only */
777
778			spi18: spi@890000 {
779				compatible = "qcom,geni-spi";
780				reg = <0 0x00890000 0 0x4000>;
781				clock-names = "se";
782				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
783				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
784				power-domains = <&rpmhpd SM8350_CX>;
785				operating-points-v2 = <&qup_opp_table_100mhz>;
786				#address-cells = <1>;
787				#size-cells = <0>;
788				status = "disabled";
789			};
790
791			uart18: serial@890000 {
792				compatible = "qcom,geni-uart";
793				reg = <0 0x00890000 0 0x4000>;
794				clock-names = "se";
795				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
796				pinctrl-names = "default";
797				pinctrl-0 = <&qup_uart18_default>;
798				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
799				power-domains = <&rpmhpd SM8350_CX>;
800				operating-points-v2 = <&qup_opp_table_100mhz>;
801				status = "disabled";
802			};
803
804			i2c19: i2c@894000 {
805				compatible = "qcom,geni-i2c";
806				reg = <0 0x00894000 0 0x4000>;
807				clock-names = "se";
808				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
809				pinctrl-names = "default";
810				pinctrl-0 = <&qup_i2c19_default>;
811				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
812				#address-cells = <1>;
813				#size-cells = <0>;
814				status = "disabled";
815			};
816
817			spi19: spi@894000 {
818				compatible = "qcom,geni-spi";
819				reg = <0 0x00894000 0 0x4000>;
820				clock-names = "se";
821				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
822				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
823				power-domains = <&rpmhpd SM8350_CX>;
824				operating-points-v2 = <&qup_opp_table_100mhz>;
825				#address-cells = <1>;
826				#size-cells = <0>;
827				status = "disabled";
828			};
829		};
830
831		qupv3_id_0: geniqup@9c0000 {
832			compatible = "qcom,geni-se-qup";
833			reg = <0x0 0x009c0000 0x0 0x6000>;
834			clock-names = "m-ahb", "s-ahb";
835			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
836				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
837			iommus = <&apps_smmu 0x5a3 0>;
838			#address-cells = <2>;
839			#size-cells = <2>;
840			ranges;
841			status = "disabled";
842
843			i2c0: i2c@980000 {
844				compatible = "qcom,geni-i2c";
845				reg = <0 0x00980000 0 0x4000>;
846				clock-names = "se";
847				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
848				pinctrl-names = "default";
849				pinctrl-0 = <&qup_i2c0_default>;
850				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
851				#address-cells = <1>;
852				#size-cells = <0>;
853				status = "disabled";
854			};
855
856			spi0: spi@980000 {
857				compatible = "qcom,geni-spi";
858				reg = <0 0x00980000 0 0x4000>;
859				clock-names = "se";
860				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
861				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
862				power-domains = <&rpmhpd SM8350_CX>;
863				operating-points-v2 = <&qup_opp_table_100mhz>;
864				#address-cells = <1>;
865				#size-cells = <0>;
866				status = "disabled";
867			};
868
869			i2c1: i2c@984000 {
870				compatible = "qcom,geni-i2c";
871				reg = <0 0x00984000 0 0x4000>;
872				clock-names = "se";
873				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
874				pinctrl-names = "default";
875				pinctrl-0 = <&qup_i2c1_default>;
876				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
877				#address-cells = <1>;
878				#size-cells = <0>;
879				status = "disabled";
880			};
881
882			spi1: spi@984000 {
883				compatible = "qcom,geni-spi";
884				reg = <0 0x00984000 0 0x4000>;
885				clock-names = "se";
886				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
887				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
888				power-domains = <&rpmhpd SM8350_CX>;
889				operating-points-v2 = <&qup_opp_table_100mhz>;
890				#address-cells = <1>;
891				#size-cells = <0>;
892				status = "disabled";
893			};
894
895			i2c2: i2c@988000 {
896				compatible = "qcom,geni-i2c";
897				reg = <0 0x00988000 0 0x4000>;
898				clock-names = "se";
899				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
900				pinctrl-names = "default";
901				pinctrl-0 = <&qup_i2c2_default>;
902				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
903				#address-cells = <1>;
904				#size-cells = <0>;
905				status = "disabled";
906			};
907
908			spi2: spi@988000 {
909				compatible = "qcom,geni-spi";
910				reg = <0 0x00988000 0 0x4000>;
911				clock-names = "se";
912				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
913				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
914				power-domains = <&rpmhpd SM8350_CX>;
915				operating-points-v2 = <&qup_opp_table_100mhz>;
916				#address-cells = <1>;
917				#size-cells = <0>;
918				status = "disabled";
919			};
920
921			uart2: serial@98c000 {
922				compatible = "qcom,geni-debug-uart";
923				reg = <0 0x0098c000 0 0x4000>;
924				clock-names = "se";
925				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
926				pinctrl-names = "default";
927				pinctrl-0 = <&qup_uart3_default_state>;
928				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
929				power-domains = <&rpmhpd SM8350_CX>;
930				operating-points-v2 = <&qup_opp_table_100mhz>;
931				#address-cells = <1>;
932				#size-cells = <0>;
933				status = "disabled";
934			};
935
936			/* QUP no. 3 seems to be strictly SPI-only */
937
938			spi3: spi@98c000 {
939				compatible = "qcom,geni-spi";
940				reg = <0 0x0098c000 0 0x4000>;
941				clock-names = "se";
942				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
943				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
944				power-domains = <&rpmhpd SM8350_CX>;
945				operating-points-v2 = <&qup_opp_table_100mhz>;
946				#address-cells = <1>;
947				#size-cells = <0>;
948				status = "disabled";
949			};
950
951			i2c4: i2c@990000 {
952				compatible = "qcom,geni-i2c";
953				reg = <0 0x00990000 0 0x4000>;
954				clock-names = "se";
955				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
956				pinctrl-names = "default";
957				pinctrl-0 = <&qup_i2c4_default>;
958				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
959				#address-cells = <1>;
960				#size-cells = <0>;
961				status = "disabled";
962			};
963
964			spi4: spi@990000 {
965				compatible = "qcom,geni-spi";
966				reg = <0 0x00990000 0 0x4000>;
967				clock-names = "se";
968				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
969				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
970				power-domains = <&rpmhpd SM8350_CX>;
971				operating-points-v2 = <&qup_opp_table_100mhz>;
972				#address-cells = <1>;
973				#size-cells = <0>;
974				status = "disabled";
975			};
976
977			i2c5: i2c@994000 {
978				compatible = "qcom,geni-i2c";
979				reg = <0 0x00994000 0 0x4000>;
980				clock-names = "se";
981				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
982				pinctrl-names = "default";
983				pinctrl-0 = <&qup_i2c5_default>;
984				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
985				#address-cells = <1>;
986				#size-cells = <0>;
987				status = "disabled";
988			};
989
990			spi5: spi@994000 {
991				compatible = "qcom,geni-spi";
992				reg = <0 0x00994000 0 0x4000>;
993				clock-names = "se";
994				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
995				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
996				power-domains = <&rpmhpd SM8350_CX>;
997				operating-points-v2 = <&qup_opp_table_100mhz>;
998				#address-cells = <1>;
999				#size-cells = <0>;
1000				status = "disabled";
1001			};
1002
1003			i2c6: i2c@998000 {
1004				compatible = "qcom,geni-i2c";
1005				reg = <0 0x00998000 0 0x4000>;
1006				clock-names = "se";
1007				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1008				pinctrl-names = "default";
1009				pinctrl-0 = <&qup_i2c6_default>;
1010				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1011				#address-cells = <1>;
1012				#size-cells = <0>;
1013				status = "disabled";
1014			};
1015
1016			spi6: spi@998000 {
1017				compatible = "qcom,geni-spi";
1018				reg = <0 0x00998000 0 0x4000>;
1019				clock-names = "se";
1020				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1021				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1022				power-domains = <&rpmhpd SM8350_CX>;
1023				operating-points-v2 = <&qup_opp_table_100mhz>;
1024				#address-cells = <1>;
1025				#size-cells = <0>;
1026				status = "disabled";
1027			};
1028
1029			uart6: serial@998000 {
1030				compatible = "qcom,geni-uart";
1031				reg = <0 0x00998000 0 0x4000>;
1032				clock-names = "se";
1033				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1034				pinctrl-names = "default";
1035				pinctrl-0 = <&qup_uart6_default>;
1036				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1037				power-domains = <&rpmhpd SM8350_CX>;
1038				operating-points-v2 = <&qup_opp_table_100mhz>;
1039				status = "disabled";
1040			};
1041
1042			i2c7: i2c@99c000 {
1043				compatible = "qcom,geni-i2c";
1044				reg = <0 0x0099c000 0 0x4000>;
1045				clock-names = "se";
1046				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1047				pinctrl-names = "default";
1048				pinctrl-0 = <&qup_i2c7_default>;
1049				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1050				#address-cells = <1>;
1051				#size-cells = <0>;
1052				status = "disabled";
1053			};
1054
1055			spi7: spi@99c000 {
1056				compatible = "qcom,geni-spi";
1057				reg = <0 0x0099c000 0 0x4000>;
1058				clock-names = "se";
1059				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1060				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1061				power-domains = <&rpmhpd SM8350_CX>;
1062				operating-points-v2 = <&qup_opp_table_100mhz>;
1063				#address-cells = <1>;
1064				#size-cells = <0>;
1065				status = "disabled";
1066			};
1067		};
1068
1069		qupv3_id_1: geniqup@ac0000 {
1070			compatible = "qcom,geni-se-qup";
1071			reg = <0x0 0x00ac0000 0x0 0x6000>;
1072			clock-names = "m-ahb", "s-ahb";
1073			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1074				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1075			iommus = <&apps_smmu 0x43 0>;
1076			#address-cells = <2>;
1077			#size-cells = <2>;
1078			ranges;
1079			status = "disabled";
1080
1081			i2c8: i2c@a80000 {
1082				compatible = "qcom,geni-i2c";
1083				reg = <0 0x00a80000 0 0x4000>;
1084				clock-names = "se";
1085				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1086				pinctrl-names = "default";
1087				pinctrl-0 = <&qup_i2c8_default>;
1088				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1089				#address-cells = <1>;
1090				#size-cells = <0>;
1091				status = "disabled";
1092			};
1093
1094			spi8: spi@a80000 {
1095				compatible = "qcom,geni-spi";
1096				reg = <0 0x00a80000 0 0x4000>;
1097				clock-names = "se";
1098				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1099				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1100				power-domains = <&rpmhpd SM8350_CX>;
1101				operating-points-v2 = <&qup_opp_table_120mhz>;
1102				#address-cells = <1>;
1103				#size-cells = <0>;
1104				status = "disabled";
1105			};
1106
1107			i2c9: i2c@a84000 {
1108				compatible = "qcom,geni-i2c";
1109				reg = <0 0x00a84000 0 0x4000>;
1110				clock-names = "se";
1111				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1112				pinctrl-names = "default";
1113				pinctrl-0 = <&qup_i2c9_default>;
1114				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1115				#address-cells = <1>;
1116				#size-cells = <0>;
1117				status = "disabled";
1118			};
1119
1120			spi9: spi@a84000 {
1121				compatible = "qcom,geni-spi";
1122				reg = <0 0x00a84000 0 0x4000>;
1123				clock-names = "se";
1124				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1125				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1126				power-domains = <&rpmhpd SM8350_CX>;
1127				operating-points-v2 = <&qup_opp_table_100mhz>;
1128				#address-cells = <1>;
1129				#size-cells = <0>;
1130				status = "disabled";
1131			};
1132
1133			i2c10: i2c@a88000 {
1134				compatible = "qcom,geni-i2c";
1135				reg = <0 0x00a88000 0 0x4000>;
1136				clock-names = "se";
1137				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1138				pinctrl-names = "default";
1139				pinctrl-0 = <&qup_i2c10_default>;
1140				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1141				#address-cells = <1>;
1142				#size-cells = <0>;
1143				status = "disabled";
1144			};
1145
1146			spi10: spi@a88000 {
1147				compatible = "qcom,geni-spi";
1148				reg = <0 0x00a88000 0 0x4000>;
1149				clock-names = "se";
1150				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1151				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1152				power-domains = <&rpmhpd SM8350_CX>;
1153				operating-points-v2 = <&qup_opp_table_100mhz>;
1154				#address-cells = <1>;
1155				#size-cells = <0>;
1156				status = "disabled";
1157			};
1158
1159			i2c11: i2c@a8c000 {
1160				compatible = "qcom,geni-i2c";
1161				reg = <0 0x00a8c000 0 0x4000>;
1162				clock-names = "se";
1163				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1164				pinctrl-names = "default";
1165				pinctrl-0 = <&qup_i2c11_default>;
1166				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1167				#address-cells = <1>;
1168				#size-cells = <0>;
1169				status = "disabled";
1170			};
1171
1172			spi11: spi@a8c000 {
1173				compatible = "qcom,geni-spi";
1174				reg = <0 0x00a8c000 0 0x4000>;
1175				clock-names = "se";
1176				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1177				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1178				power-domains = <&rpmhpd SM8350_CX>;
1179				operating-points-v2 = <&qup_opp_table_100mhz>;
1180				#address-cells = <1>;
1181				#size-cells = <0>;
1182				status = "disabled";
1183			};
1184
1185			i2c12: i2c@a90000 {
1186				compatible = "qcom,geni-i2c";
1187				reg = <0 0x00a90000 0 0x4000>;
1188				clock-names = "se";
1189				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1190				pinctrl-names = "default";
1191				pinctrl-0 = <&qup_i2c12_default>;
1192				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1193				#address-cells = <1>;
1194				#size-cells = <0>;
1195				status = "disabled";
1196			};
1197
1198			spi12: spi@a90000 {
1199				compatible = "qcom,geni-spi";
1200				reg = <0 0x00a90000 0 0x4000>;
1201				clock-names = "se";
1202				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1203				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1204				power-domains = <&rpmhpd SM8350_CX>;
1205				operating-points-v2 = <&qup_opp_table_100mhz>;
1206				#address-cells = <1>;
1207				#size-cells = <0>;
1208				status = "disabled";
1209			};
1210
1211			i2c13: i2c@a94000 {
1212				compatible = "qcom,geni-i2c";
1213				reg = <0 0x00a94000 0 0x4000>;
1214				clock-names = "se";
1215				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1216				pinctrl-names = "default";
1217				pinctrl-0 = <&qup_i2c13_default>;
1218				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1219				#address-cells = <1>;
1220				#size-cells = <0>;
1221				status = "disabled";
1222			};
1223
1224			spi13: spi@a94000 {
1225				compatible = "qcom,geni-spi";
1226				reg = <0 0x00a94000 0 0x4000>;
1227				clock-names = "se";
1228				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1229				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1230				power-domains = <&rpmhpd SM8350_CX>;
1231				operating-points-v2 = <&qup_opp_table_100mhz>;
1232				#address-cells = <1>;
1233				#size-cells = <0>;
1234				status = "disabled";
1235			};
1236		};
1237
1238		apps_smmu: iommu@15000000 {
1239			compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1240			reg = <0 0x15000000 0 0x100000>;
1241			#iommu-cells = <2>;
1242			#global-interrupts = <2>;
1243			interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1244					<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1245					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1246					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1247					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1248					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1249					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1250					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1251					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1252					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1253					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1254					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1255					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1256					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1257					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1258					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1259					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1260					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1261					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1262					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1263					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1264					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1265					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1266					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1267					<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1268					<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1269					<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1270					<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1271					<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1272					<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1273					<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1274					<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1275					<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1276					<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1277					<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1278					<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1279					<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1280					<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1281					<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1282					<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1283					<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1284					<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1285					<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1286					<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1287					<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1288					<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1289					<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1290					<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1291					<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1292					<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1293					<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1294					<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1295					<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1296					<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1297					<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1298					<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1299					<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1300					<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1301					<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1302					<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1303					<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1304					<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1305					<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1306					<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1307					<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1308					<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1309					<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1310					<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1311					<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1312					<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1313					<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1314					<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1315					<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1316					<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1317					<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1318					<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1319					<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1320					<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1321					<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1322					<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1323					<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1324					<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1325					<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1326					<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1327					<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1328					<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1329					<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1330					<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1331					<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1332					<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1333					<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1334					<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1335					<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1336					<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1337					<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1338					<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1339					<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
1340					<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
1341		};
1342
1343		config_noc: interconnect@1500000 {
1344			compatible = "qcom,sm8350-config-noc";
1345			reg = <0 0x01500000 0 0xa580>;
1346			#interconnect-cells = <1>;
1347			qcom,bcm-voters = <&apps_bcm_voter>;
1348		};
1349
1350		mc_virt: interconnect@1580000 {
1351			compatible = "qcom,sm8350-mc-virt";
1352			reg = <0 0x01580000 0 0x1000>;
1353			#interconnect-cells = <1>;
1354			qcom,bcm-voters = <&apps_bcm_voter>;
1355		};
1356
1357		system_noc: interconnect@1680000 {
1358			compatible = "qcom,sm8350-system-noc";
1359			reg = <0 0x01680000 0 0x1c200>;
1360			#interconnect-cells = <1>;
1361			qcom,bcm-voters = <&apps_bcm_voter>;
1362		};
1363
1364		aggre1_noc: interconnect@16e0000 {
1365			compatible = "qcom,sm8350-aggre1-noc";
1366			reg = <0 0x016e0000 0 0x1f180>;
1367			#interconnect-cells = <1>;
1368			qcom,bcm-voters = <&apps_bcm_voter>;
1369		};
1370
1371		aggre2_noc: interconnect@1700000 {
1372			compatible = "qcom,sm8350-aggre2-noc";
1373			reg = <0 0x01700000 0 0x33000>;
1374			#interconnect-cells = <1>;
1375			qcom,bcm-voters = <&apps_bcm_voter>;
1376		};
1377
1378		mmss_noc: interconnect@1740000 {
1379			compatible = "qcom,sm8350-mmss-noc";
1380			reg = <0 0x01740000 0 0x1f080>;
1381			#interconnect-cells = <1>;
1382			qcom,bcm-voters = <&apps_bcm_voter>;
1383		};
1384
1385		lpass_ag_noc: interconnect@3c40000 {
1386			compatible = "qcom,sm8350-lpass-ag-noc";
1387			reg = <0 0x03c40000 0 0xf080>;
1388			#interconnect-cells = <1>;
1389			qcom,bcm-voters = <&apps_bcm_voter>;
1390		};
1391
1392		compute_noc: interconnect@a0c0000{
1393			compatible = "qcom,sm8350-compute-noc";
1394			reg = <0 0x0a0c0000 0 0xa180>;
1395			#interconnect-cells = <1>;
1396			qcom,bcm-voters = <&apps_bcm_voter>;
1397		};
1398
1399		ipa: ipa@1e40000 {
1400			compatible = "qcom,sm8350-ipa";
1401
1402			iommus = <&apps_smmu 0x5c0 0x0>,
1403				 <&apps_smmu 0x5c2 0x0>;
1404			reg = <0 0x1e40000 0 0x8000>,
1405			      <0 0x1e50000 0 0x4b20>,
1406			      <0 0x1e04000 0 0x23000>;
1407			reg-names = "ipa-reg",
1408				    "ipa-shared",
1409				    "gsi";
1410
1411			interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1412					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1413					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1414					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1415			interrupt-names = "ipa",
1416					  "gsi",
1417					  "ipa-clock-query",
1418					  "ipa-setup-ready";
1419
1420			clocks = <&rpmhcc RPMH_IPA_CLK>;
1421			clock-names = "core";
1422
1423			interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1424					<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1425			interconnect-names = "memory",
1426					     "config";
1427
1428			qcom,smem-states = <&ipa_smp2p_out 0>,
1429					   <&ipa_smp2p_out 1>;
1430			qcom,smem-state-names = "ipa-clock-enabled-valid",
1431						"ipa-clock-enabled";
1432
1433			status = "disabled";
1434		};
1435
1436		tcsr_mutex: hwlock@1f40000 {
1437			compatible = "qcom,tcsr-mutex";
1438			reg = <0x0 0x01f40000 0x0 0x40000>;
1439			#hwlock-cells = <1>;
1440		};
1441
1442		mpss: remoteproc@4080000 {
1443			compatible = "qcom,sm8350-mpss-pas";
1444			reg = <0x0 0x04080000 0x0 0x4040>;
1445
1446			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1447					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1448					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1449					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1450					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1451					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1452			interrupt-names = "wdog", "fatal", "ready", "handover",
1453					  "stop-ack", "shutdown-ack";
1454
1455			clocks = <&rpmhcc RPMH_CXO_CLK>;
1456			clock-names = "xo";
1457
1458			power-domains = <&rpmhpd 0>,
1459					<&rpmhpd 12>;
1460			power-domain-names = "cx", "mss";
1461
1462			interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
1463
1464			memory-region = <&pil_modem_mem>;
1465
1466			qcom,qmp = <&aoss_qmp>;
1467
1468			qcom,smem-states = <&smp2p_modem_out 0>;
1469			qcom,smem-state-names = "stop";
1470
1471			status = "disabled";
1472
1473			glink-edge {
1474				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1475							     IPCC_MPROC_SIGNAL_GLINK_QMP
1476							     IRQ_TYPE_EDGE_RISING>;
1477				mboxes = <&ipcc IPCC_CLIENT_MPSS
1478						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1479				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1480				label = "modem";
1481				qcom,remote-pid = <1>;
1482			};
1483		};
1484
1485		pdc: interrupt-controller@b220000 {
1486			compatible = "qcom,sm8350-pdc", "qcom,pdc";
1487			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1488			qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
1489					  <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
1490					  <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
1491					  <156 716 12>;
1492			#interrupt-cells = <2>;
1493			interrupt-parent = <&intc>;
1494			interrupt-controller;
1495		};
1496
1497		tsens0: thermal-sensor@c263000 {
1498			compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1499			reg = <0 0x0c263000 0 0x1ff>, /* TM */
1500			      <0 0x0c222000 0 0x8>; /* SROT */
1501			#qcom,sensors = <15>;
1502			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1503				     <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1504			interrupt-names = "uplow", "critical";
1505			#thermal-sensor-cells = <1>;
1506		};
1507
1508		tsens1: thermal-sensor@c265000 {
1509			compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1510			reg = <0 0x0c265000 0 0x1ff>, /* TM */
1511			      <0 0x0c223000 0 0x8>; /* SROT */
1512			#qcom,sensors = <14>;
1513			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1514				     <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1515			interrupt-names = "uplow", "critical";
1516			#thermal-sensor-cells = <1>;
1517		};
1518
1519		aoss_qmp: power-controller@c300000 {
1520			compatible = "qcom,sm8350-aoss-qmp";
1521			reg = <0 0x0c300000 0 0x400>;
1522			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1523						     IRQ_TYPE_EDGE_RISING>;
1524			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1525
1526			#clock-cells = <0>;
1527		};
1528
1529		sram@c3f0000 {
1530			compatible = "qcom,rpmh-stats";
1531			reg = <0 0x0c3f0000 0 0x400>;
1532		};
1533
1534		spmi_bus: spmi@c440000 {
1535			compatible = "qcom,spmi-pmic-arb";
1536			reg = <0x0 0xc440000 0x0 0x1100>,
1537			      <0x0 0xc600000 0x0 0x2000000>,
1538			      <0x0 0xe600000 0x0 0x100000>,
1539			      <0x0 0xe700000 0x0 0xa0000>,
1540			      <0x0 0xc40a000 0x0 0x26000>;
1541			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1542			interrupt-names = "periph_irq";
1543			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1544			qcom,ee = <0>;
1545			qcom,channel = <0>;
1546			#address-cells = <2>;
1547			#size-cells = <0>;
1548			interrupt-controller;
1549			#interrupt-cells = <4>;
1550		};
1551
1552		tlmm: pinctrl@f100000 {
1553			compatible = "qcom,sm8350-tlmm";
1554			reg = <0 0x0f100000 0 0x300000>;
1555			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1556			gpio-controller;
1557			#gpio-cells = <2>;
1558			interrupt-controller;
1559			#interrupt-cells = <2>;
1560			gpio-ranges = <&tlmm 0 0 204>;
1561			wakeup-parent = <&pdc>;
1562
1563			qup_uart3_default_state: qup-uart3-default-state {
1564				rx {
1565					pins = "gpio18";
1566					function = "qup3";
1567				};
1568				tx {
1569					pins = "gpio19";
1570					function = "qup3";
1571				};
1572			};
1573
1574			qup_uart6_default: qup-uart6-default {
1575				pins = "gpio30", "gpio31";
1576				function = "qup6";
1577				drive-strength = <2>;
1578				bias-disable;
1579			};
1580
1581			qup_uart18_default: qup-uart18-default {
1582				pins = "gpio58", "gpio59";
1583				function = "qup18";
1584				drive-strength = <2>;
1585				bias-disable;
1586			};
1587
1588			qup_i2c0_default: qup-i2c0-default {
1589				pins = "gpio4", "gpio5";
1590				function = "qup0";
1591				drive-strength = <2>;
1592				bias-pull-up;
1593			};
1594
1595			qup_i2c1_default: qup-i2c1-default {
1596				pins = "gpio8", "gpio9";
1597				function = "qup1";
1598				drive-strength = <2>;
1599				bias-pull-up;
1600			};
1601
1602			qup_i2c2_default: qup-i2c2-default {
1603				pins = "gpio12", "gpio13";
1604				function = "qup2";
1605				drive-strength = <2>;
1606				bias-pull-up;
1607			};
1608
1609			qup_i2c4_default: qup-i2c4-default {
1610				pins = "gpio20", "gpio21";
1611				function = "qup4";
1612				drive-strength = <2>;
1613				bias-pull-up;
1614			};
1615
1616			qup_i2c5_default: qup-i2c5-default {
1617				pins = "gpio24", "gpio25";
1618				function = "qup5";
1619				drive-strength = <2>;
1620				bias-pull-up;
1621			};
1622
1623			qup_i2c6_default: qup-i2c6-default {
1624				pins = "gpio28", "gpio29";
1625				function = "qup6";
1626				drive-strength = <2>;
1627				bias-pull-up;
1628			};
1629
1630			qup_i2c7_default: qup-i2c7-default {
1631				pins = "gpio32", "gpio33";
1632				function = "qup7";
1633				drive-strength = <2>;
1634				bias-disable;
1635			};
1636
1637			qup_i2c8_default: qup-i2c8-default {
1638				pins = "gpio36", "gpio37";
1639				function = "qup8";
1640				drive-strength = <2>;
1641				bias-pull-up;
1642			};
1643
1644			qup_i2c9_default: qup-i2c9-default {
1645				pins = "gpio40", "gpio41";
1646				function = "qup9";
1647				drive-strength = <2>;
1648				bias-pull-up;
1649			};
1650
1651			qup_i2c10_default: qup-i2c10-default {
1652				pins = "gpio44", "gpio45";
1653				function = "qup10";
1654				drive-strength = <2>;
1655				bias-pull-up;
1656			};
1657
1658			qup_i2c11_default: qup-i2c11-default {
1659				pins = "gpio48", "gpio49";
1660				function = "qup11";
1661				drive-strength = <2>;
1662				bias-pull-up;
1663			};
1664
1665			qup_i2c12_default: qup-i2c12-default {
1666				pins = "gpio52", "gpio53";
1667				function = "qup12";
1668				drive-strength = <2>;
1669				bias-pull-up;
1670			};
1671
1672			qup_i2c13_default: qup-i2c13-default {
1673				pins = "gpio0", "gpio1";
1674				function = "qup13";
1675				drive-strength = <2>;
1676				bias-pull-up;
1677			};
1678
1679			qup_i2c14_default: qup-i2c14-default {
1680				pins = "gpio56", "gpio57";
1681				function = "qup14";
1682				drive-strength = <2>;
1683				bias-disable;
1684			};
1685
1686			qup_i2c15_default: qup-i2c15-default {
1687				pins = "gpio60", "gpio61";
1688				function = "qup15";
1689				drive-strength = <2>;
1690				bias-disable;
1691			};
1692
1693			qup_i2c16_default: qup-i2c16-default {
1694				pins = "gpio64", "gpio65";
1695				function = "qup16";
1696				drive-strength = <2>;
1697				bias-disable;
1698			};
1699
1700			qup_i2c17_default: qup-i2c17-default {
1701				pins = "gpio72", "gpio73";
1702				function = "qup17";
1703				drive-strength = <2>;
1704				bias-disable;
1705			};
1706
1707			qup_i2c19_default: qup-i2c19-default {
1708				pins = "gpio76", "gpio77";
1709				function = "qup19";
1710				drive-strength = <2>;
1711				bias-disable;
1712			};
1713		};
1714
1715		rng: rng@10d3000 {
1716			compatible = "qcom,prng-ee";
1717			reg = <0 0x010d3000 0 0x1000>;
1718			clocks = <&rpmhcc RPMH_HWKM_CLK>;
1719			clock-names = "core";
1720		};
1721
1722		intc: interrupt-controller@17a00000 {
1723			compatible = "arm,gic-v3";
1724			#interrupt-cells = <3>;
1725			interrupt-controller;
1726			#redistributor-regions = <1>;
1727			redistributor-stride = <0 0x20000>;
1728			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1729			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1730			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1731		};
1732
1733		timer@17c20000 {
1734			compatible = "arm,armv7-timer-mem";
1735			#address-cells = <2>;
1736			#size-cells = <2>;
1737			ranges;
1738			reg = <0x0 0x17c20000 0x0 0x1000>;
1739			clock-frequency = <19200000>;
1740
1741			frame@17c21000 {
1742				frame-number = <0>;
1743				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1744					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1745				reg = <0x0 0x17c21000 0x0 0x1000>,
1746				      <0x0 0x17c22000 0x0 0x1000>;
1747			};
1748
1749			frame@17c23000 {
1750				frame-number = <1>;
1751				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1752				reg = <0x0 0x17c23000 0x0 0x1000>;
1753				status = "disabled";
1754			};
1755
1756			frame@17c25000 {
1757				frame-number = <2>;
1758				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1759				reg = <0x0 0x17c25000 0x0 0x1000>;
1760				status = "disabled";
1761			};
1762
1763			frame@17c27000 {
1764				frame-number = <3>;
1765				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1766				reg = <0x0 0x17c27000 0x0 0x1000>;
1767				status = "disabled";
1768			};
1769
1770			frame@17c29000 {
1771				frame-number = <4>;
1772				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1773				reg = <0x0 0x17c29000 0x0 0x1000>;
1774				status = "disabled";
1775			};
1776
1777			frame@17c2b000 {
1778				frame-number = <5>;
1779				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1780				reg = <0x0 0x17c2b000 0x0 0x1000>;
1781				status = "disabled";
1782			};
1783
1784			frame@17c2d000 {
1785				frame-number = <6>;
1786				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1787				reg = <0x0 0x17c2d000 0x0 0x1000>;
1788				status = "disabled";
1789			};
1790		};
1791
1792		apps_rsc: rsc@18200000 {
1793			label = "apps_rsc";
1794			compatible = "qcom,rpmh-rsc";
1795			reg = <0x0 0x18200000 0x0 0x10000>,
1796				<0x0 0x18210000 0x0 0x10000>,
1797				<0x0 0x18220000 0x0 0x10000>;
1798			reg-names = "drv-0", "drv-1", "drv-2";
1799			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1800				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1801				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1802			qcom,tcs-offset = <0xd00>;
1803			qcom,drv-id = <2>;
1804			qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
1805					  <WAKE_TCS    3>, <CONTROL_TCS 1>;
1806
1807			rpmhcc: clock-controller {
1808				compatible = "qcom,sm8350-rpmh-clk";
1809				#clock-cells = <1>;
1810				clock-names = "xo";
1811				clocks = <&xo_board>;
1812			};
1813
1814			rpmhpd: power-controller {
1815				compatible = "qcom,sm8350-rpmhpd";
1816				#power-domain-cells = <1>;
1817				operating-points-v2 = <&rpmhpd_opp_table>;
1818
1819				rpmhpd_opp_table: opp-table {
1820					compatible = "operating-points-v2";
1821
1822					rpmhpd_opp_ret: opp1 {
1823						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1824					};
1825
1826					rpmhpd_opp_min_svs: opp2 {
1827						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1828					};
1829
1830					rpmhpd_opp_low_svs: opp3 {
1831						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1832					};
1833
1834					rpmhpd_opp_svs: opp4 {
1835						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1836					};
1837
1838					rpmhpd_opp_svs_l1: opp5 {
1839						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1840					};
1841
1842					rpmhpd_opp_nom: opp6 {
1843						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1844					};
1845
1846					rpmhpd_opp_nom_l1: opp7 {
1847						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1848					};
1849
1850					rpmhpd_opp_nom_l2: opp8 {
1851						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1852					};
1853
1854					rpmhpd_opp_turbo: opp9 {
1855						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1856					};
1857
1858					rpmhpd_opp_turbo_l1: opp10 {
1859						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1860					};
1861				};
1862			};
1863
1864			apps_bcm_voter: bcm_voter {
1865				compatible = "qcom,bcm-voter";
1866			};
1867		};
1868
1869		cpufreq_hw: cpufreq@18591000 {
1870			compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
1871			reg = <0 0x18591000 0 0x1000>,
1872			      <0 0x18592000 0 0x1000>,
1873			      <0 0x18593000 0 0x1000>;
1874			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
1875
1876			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1877			clock-names = "xo", "alternate";
1878
1879			#freq-domain-cells = <1>;
1880		};
1881
1882		ufs_mem_hc: ufshc@1d84000 {
1883			compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1884				     "jedec,ufs-2.0";
1885			reg = <0 0x01d84000 0 0x3000>;
1886			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1887			phys = <&ufs_mem_phy_lanes>;
1888			phy-names = "ufsphy";
1889			lanes-per-direction = <2>;
1890			#reset-cells = <1>;
1891			resets = <&gcc GCC_UFS_PHY_BCR>;
1892			reset-names = "rst";
1893
1894			power-domains = <&gcc UFS_PHY_GDSC>;
1895
1896			iommus = <&apps_smmu 0xe0 0x0>;
1897
1898			clock-names =
1899				"ref_clk",
1900				"core_clk",
1901				"bus_aggr_clk",
1902				"iface_clk",
1903				"core_clk_unipro",
1904				"ref_clk",
1905				"tx_lane0_sync_clk",
1906				"rx_lane0_sync_clk",
1907				"rx_lane1_sync_clk";
1908			clocks =
1909				<&rpmhcc RPMH_CXO_CLK>,
1910				<&gcc GCC_UFS_PHY_AXI_CLK>,
1911				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1912				<&gcc GCC_UFS_PHY_AHB_CLK>,
1913				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1914				<&rpmhcc RPMH_CXO_CLK>,
1915				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1916				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1917				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1918			freq-table-hz =
1919				<75000000 300000000>,
1920				<75000000 300000000>,
1921				<0 0>,
1922				<0 0>,
1923				<75000000 300000000>,
1924				<0 0>,
1925				<0 0>,
1926				<75000000 300000000>,
1927				<75000000 300000000>;
1928			status = "disabled";
1929		};
1930
1931		ufs_mem_phy: phy@1d87000 {
1932			compatible = "qcom,sm8350-qmp-ufs-phy";
1933			reg = <0 0x01d87000 0 0xe10>;
1934			#address-cells = <2>;
1935			#size-cells = <2>;
1936			ranges;
1937			clock-names = "ref",
1938				      "ref_aux";
1939			clocks = <&rpmhcc RPMH_CXO_CLK>,
1940				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1941
1942			resets = <&ufs_mem_hc 0>;
1943			reset-names = "ufsphy";
1944			status = "disabled";
1945
1946			ufs_mem_phy_lanes: phy@1d87400 {
1947				reg = <0 0x01d87400 0 0x108>,
1948				      <0 0x01d87600 0 0x1e0>,
1949				      <0 0x01d87c00 0 0x1dc>,
1950				      <0 0x01d87800 0 0x108>,
1951				      <0 0x01d87a00 0 0x1e0>;
1952				#phy-cells = <0>;
1953				#clock-cells = <0>;
1954			};
1955		};
1956
1957		slpi: remoteproc@5c00000 {
1958			compatible = "qcom,sm8350-slpi-pas";
1959			reg = <0 0x05c00000 0 0x4000>;
1960
1961			interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1962					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1963					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1964					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1965					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1966			interrupt-names = "wdog", "fatal", "ready",
1967					  "handover", "stop-ack";
1968
1969			clocks = <&rpmhcc RPMH_CXO_CLK>;
1970			clock-names = "xo";
1971
1972			power-domains = <&rpmhpd 4>,
1973					<&rpmhpd 5>;
1974			power-domain-names = "lcx", "lmx";
1975
1976			memory-region = <&pil_slpi_mem>;
1977
1978			qcom,qmp = <&aoss_qmp>;
1979
1980			qcom,smem-states = <&smp2p_slpi_out 0>;
1981			qcom,smem-state-names = "stop";
1982
1983			status = "disabled";
1984
1985			glink-edge {
1986				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1987							     IPCC_MPROC_SIGNAL_GLINK_QMP
1988							     IRQ_TYPE_EDGE_RISING>;
1989				mboxes = <&ipcc IPCC_CLIENT_SLPI
1990						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1991
1992				label = "slpi";
1993				qcom,remote-pid = <3>;
1994
1995				fastrpc {
1996					compatible = "qcom,fastrpc";
1997					qcom,glink-channels = "fastrpcglink-apps-dsp";
1998					label = "sdsp";
1999					#address-cells = <1>;
2000					#size-cells = <0>;
2001
2002					compute-cb@1 {
2003						compatible = "qcom,fastrpc-compute-cb";
2004						reg = <1>;
2005						iommus = <&apps_smmu 0x0541 0x0>;
2006					};
2007
2008					compute-cb@2 {
2009						compatible = "qcom,fastrpc-compute-cb";
2010						reg = <2>;
2011						iommus = <&apps_smmu 0x0542 0x0>;
2012					};
2013
2014					compute-cb@3 {
2015						compatible = "qcom,fastrpc-compute-cb";
2016						reg = <3>;
2017						iommus = <&apps_smmu 0x0543 0x0>;
2018						/* note: shared-cb = <4> in downstream */
2019					};
2020				};
2021			};
2022		};
2023
2024		cdsp: remoteproc@98900000 {
2025			compatible = "qcom,sm8350-cdsp-pas";
2026			reg = <0 0x098900000 0 0x1400000>;
2027
2028			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2029					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2030					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2031					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2032					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2033			interrupt-names = "wdog", "fatal", "ready",
2034					  "handover", "stop-ack";
2035
2036			clocks = <&rpmhcc RPMH_CXO_CLK>;
2037			clock-names = "xo";
2038
2039			power-domains = <&rpmhpd 0>,
2040					<&rpmhpd 10>;
2041			power-domain-names = "cx", "mxc";
2042
2043			interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
2044
2045			memory-region = <&pil_cdsp_mem>;
2046
2047			qcom,qmp = <&aoss_qmp>;
2048
2049			qcom,smem-states = <&smp2p_cdsp_out 0>;
2050			qcom,smem-state-names = "stop";
2051
2052			status = "disabled";
2053
2054			glink-edge {
2055				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2056							     IPCC_MPROC_SIGNAL_GLINK_QMP
2057							     IRQ_TYPE_EDGE_RISING>;
2058				mboxes = <&ipcc IPCC_CLIENT_CDSP
2059						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2060
2061				label = "cdsp";
2062				qcom,remote-pid = <5>;
2063
2064				fastrpc {
2065					compatible = "qcom,fastrpc";
2066					qcom,glink-channels = "fastrpcglink-apps-dsp";
2067					label = "cdsp";
2068					#address-cells = <1>;
2069					#size-cells = <0>;
2070
2071					compute-cb@1 {
2072						compatible = "qcom,fastrpc-compute-cb";
2073						reg = <1>;
2074						iommus = <&apps_smmu 0x2161 0x0400>,
2075							 <&apps_smmu 0x1181 0x0420>;
2076					};
2077
2078					compute-cb@2 {
2079						compatible = "qcom,fastrpc-compute-cb";
2080						reg = <2>;
2081						iommus = <&apps_smmu 0x2162 0x0400>,
2082							 <&apps_smmu 0x1182 0x0420>;
2083					};
2084
2085					compute-cb@3 {
2086						compatible = "qcom,fastrpc-compute-cb";
2087						reg = <3>;
2088						iommus = <&apps_smmu 0x2163 0x0400>,
2089							 <&apps_smmu 0x1183 0x0420>;
2090					};
2091
2092					compute-cb@4 {
2093						compatible = "qcom,fastrpc-compute-cb";
2094						reg = <4>;
2095						iommus = <&apps_smmu 0x2164 0x0400>,
2096							 <&apps_smmu 0x1184 0x0420>;
2097					};
2098
2099					compute-cb@5 {
2100						compatible = "qcom,fastrpc-compute-cb";
2101						reg = <5>;
2102						iommus = <&apps_smmu 0x2165 0x0400>,
2103							 <&apps_smmu 0x1185 0x0420>;
2104					};
2105
2106					compute-cb@6 {
2107						compatible = "qcom,fastrpc-compute-cb";
2108						reg = <6>;
2109						iommus = <&apps_smmu 0x2166 0x0400>,
2110							 <&apps_smmu 0x1186 0x0420>;
2111					};
2112
2113					compute-cb@7 {
2114						compatible = "qcom,fastrpc-compute-cb";
2115						reg = <7>;
2116						iommus = <&apps_smmu 0x2167 0x0400>,
2117							 <&apps_smmu 0x1187 0x0420>;
2118					};
2119
2120					compute-cb@8 {
2121						compatible = "qcom,fastrpc-compute-cb";
2122						reg = <8>;
2123						iommus = <&apps_smmu 0x2168 0x0400>,
2124							 <&apps_smmu 0x1188 0x0420>;
2125					};
2126
2127					/* note: secure cb9 in downstream */
2128				};
2129			};
2130		};
2131
2132		usb_1_hsphy: phy@88e3000 {
2133			compatible = "qcom,sm8350-usb-hs-phy",
2134				     "qcom,usb-snps-hs-7nm-phy";
2135			reg = <0 0x088e3000 0 0x400>;
2136			status = "disabled";
2137			#phy-cells = <0>;
2138
2139			clocks = <&rpmhcc RPMH_CXO_CLK>;
2140			clock-names = "ref";
2141
2142			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2143		};
2144
2145		usb_2_hsphy: phy@88e4000 {
2146			compatible = "qcom,sm8250-usb-hs-phy",
2147				     "qcom,usb-snps-hs-7nm-phy";
2148			reg = <0 0x088e4000 0 0x400>;
2149			status = "disabled";
2150			#phy-cells = <0>;
2151
2152			clocks = <&rpmhcc RPMH_CXO_CLK>;
2153			clock-names = "ref";
2154
2155			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2156		};
2157
2158		usb_1_qmpphy: phy-wrapper@88e9000 {
2159			compatible = "qcom,sm8350-qmp-usb3-phy";
2160			reg = <0 0x088e9000 0 0x200>,
2161			      <0 0x088e8000 0 0x20>;
2162			status = "disabled";
2163			#address-cells = <2>;
2164			#size-cells = <2>;
2165			ranges;
2166
2167			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2168				 <&rpmhcc RPMH_CXO_CLK>,
2169				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2170			clock-names = "aux", "ref_clk_src", "com_aux";
2171
2172			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2173				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2174			reset-names = "phy", "common";
2175
2176			usb_1_ssphy: phy@88e9200 {
2177				reg = <0 0x088e9200 0 0x200>,
2178				      <0 0x088e9400 0 0x200>,
2179				      <0 0x088e9c00 0 0x400>,
2180				      <0 0x088e9600 0 0x200>,
2181				      <0 0x088e9800 0 0x200>,
2182				      <0 0x088e9a00 0 0x100>;
2183				#phy-cells = <0>;
2184				#clock-cells = <1>;
2185				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2186				clock-names = "pipe0";
2187				clock-output-names = "usb3_phy_pipe_clk_src";
2188			};
2189		};
2190
2191		usb_2_qmpphy: phy-wrapper@88eb000 {
2192			compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2193			reg = <0 0x088eb000 0 0x200>;
2194			status = "disabled";
2195			#address-cells = <2>;
2196			#size-cells = <2>;
2197			ranges;
2198
2199			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2200				 <&rpmhcc RPMH_CXO_CLK>,
2201				 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2202				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2203			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2204
2205			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2206				 <&gcc GCC_USB3_PHY_SEC_BCR>;
2207			reset-names = "phy", "common";
2208
2209			usb_2_ssphy: phy@88ebe00 {
2210				reg = <0 0x088ebe00 0 0x200>,
2211				      <0 0x088ec000 0 0x200>,
2212				      <0 0x088eb200 0 0x1100>;
2213				#phy-cells = <0>;
2214				#clock-cells = <1>;
2215				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2216				clock-names = "pipe0";
2217				clock-output-names = "usb3_uni_phy_pipe_clk_src";
2218			};
2219		};
2220
2221		dc_noc: interconnect@90c0000 {
2222			compatible = "qcom,sm8350-dc-noc";
2223			reg = <0 0x090c0000 0 0x4200>;
2224			#interconnect-cells = <1>;
2225			qcom,bcm-voters = <&apps_bcm_voter>;
2226		};
2227
2228		gem_noc: interconnect@9100000 {
2229			compatible = "qcom,sm8350-gem-noc";
2230			reg = <0 0x09100000 0 0xb4000>;
2231			#interconnect-cells = <1>;
2232			qcom,bcm-voters = <&apps_bcm_voter>;
2233		};
2234
2235		system-cache-controller@9200000 {
2236			compatible = "qcom,sm8350-llcc";
2237			reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2238			reg-names = "llcc_base", "llcc_broadcast_base";
2239		};
2240
2241		usb_1: usb@a6f8800 {
2242			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2243			reg = <0 0x0a6f8800 0 0x400>;
2244			status = "disabled";
2245			#address-cells = <2>;
2246			#size-cells = <2>;
2247			ranges;
2248
2249			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2250				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2251				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2252				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2253				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2254			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2255				      "sleep";
2256
2257			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2258					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2259			assigned-clock-rates = <19200000>, <200000000>;
2260
2261			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2262					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2263					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2264					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2265			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2266					  "dm_hs_phy_irq", "ss_phy_irq";
2267
2268			power-domains = <&gcc USB30_PRIM_GDSC>;
2269
2270			resets = <&gcc GCC_USB30_PRIM_BCR>;
2271
2272			usb_1_dwc3: usb@a600000 {
2273				compatible = "snps,dwc3";
2274				reg = <0 0x0a600000 0 0xcd00>;
2275				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2276				iommus = <&apps_smmu 0x0 0x0>;
2277				snps,dis_u2_susphy_quirk;
2278				snps,dis_enblslpm_quirk;
2279				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2280				phy-names = "usb2-phy", "usb3-phy";
2281			};
2282		};
2283
2284		usb_2: usb@a8f8800 {
2285			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2286			reg = <0 0x0a8f8800 0 0x400>;
2287			status = "disabled";
2288			#address-cells = <2>;
2289			#size-cells = <2>;
2290			ranges;
2291
2292			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2293				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2294				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2295				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2296				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2297				 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2298			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2299				      "sleep", "xo";
2300
2301			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2302					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
2303			assigned-clock-rates = <19200000>, <200000000>;
2304
2305			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2306					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2307					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2308					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2309			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2310					  "dm_hs_phy_irq", "ss_phy_irq";
2311
2312			power-domains = <&gcc USB30_SEC_GDSC>;
2313
2314			resets = <&gcc GCC_USB30_SEC_BCR>;
2315
2316			usb_2_dwc3: usb@a800000 {
2317				compatible = "snps,dwc3";
2318				reg = <0 0x0a800000 0 0xcd00>;
2319				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2320				iommus = <&apps_smmu 0x20 0x0>;
2321				snps,dis_u2_susphy_quirk;
2322				snps,dis_enblslpm_quirk;
2323				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2324				phy-names = "usb2-phy", "usb3-phy";
2325			};
2326		};
2327
2328		adsp: remoteproc@17300000 {
2329			compatible = "qcom,sm8350-adsp-pas";
2330			reg = <0 0x17300000 0 0x100>;
2331
2332			interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2333					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2334					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2335					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2336					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2337			interrupt-names = "wdog", "fatal", "ready",
2338					  "handover", "stop-ack";
2339
2340			clocks = <&rpmhcc RPMH_CXO_CLK>;
2341			clock-names = "xo";
2342
2343			power-domains = <&rpmhpd 4>,
2344					<&rpmhpd 5>;
2345			power-domain-names = "lcx", "lmx";
2346
2347			memory-region = <&pil_adsp_mem>;
2348
2349			qcom,qmp = <&aoss_qmp>;
2350
2351			qcom,smem-states = <&smp2p_adsp_out 0>;
2352			qcom,smem-state-names = "stop";
2353
2354			status = "disabled";
2355
2356			glink-edge {
2357				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2358							     IPCC_MPROC_SIGNAL_GLINK_QMP
2359							     IRQ_TYPE_EDGE_RISING>;
2360				mboxes = <&ipcc IPCC_CLIENT_LPASS
2361						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2362
2363				label = "lpass";
2364				qcom,remote-pid = <2>;
2365
2366				fastrpc {
2367					compatible = "qcom,fastrpc";
2368					qcom,glink-channels = "fastrpcglink-apps-dsp";
2369					label = "adsp";
2370					#address-cells = <1>;
2371					#size-cells = <0>;
2372
2373					compute-cb@3 {
2374						compatible = "qcom,fastrpc-compute-cb";
2375						reg = <3>;
2376						iommus = <&apps_smmu 0x1803 0x0>;
2377					};
2378
2379					compute-cb@4 {
2380						compatible = "qcom,fastrpc-compute-cb";
2381						reg = <4>;
2382						iommus = <&apps_smmu 0x1804 0x0>;
2383					};
2384
2385					compute-cb@5 {
2386						compatible = "qcom,fastrpc-compute-cb";
2387						reg = <5>;
2388						iommus = <&apps_smmu 0x1805 0x0>;
2389					};
2390				};
2391			};
2392		};
2393	};
2394
2395	thermal_zones: thermal-zones {
2396		cpu0-thermal {
2397			polling-delay-passive = <250>;
2398			polling-delay = <1000>;
2399
2400			thermal-sensors = <&tsens0 1>;
2401
2402			trips {
2403				cpu0_alert0: trip-point0 {
2404					temperature = <90000>;
2405					hysteresis = <2000>;
2406					type = "passive";
2407				};
2408
2409				cpu0_alert1: trip-point1 {
2410					temperature = <95000>;
2411					hysteresis = <2000>;
2412					type = "passive";
2413				};
2414
2415				cpu0_crit: cpu_crit {
2416					temperature = <110000>;
2417					hysteresis = <1000>;
2418					type = "critical";
2419				};
2420			};
2421
2422			cooling-maps {
2423				map0 {
2424					trip = <&cpu0_alert0>;
2425					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2426							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2427							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2428							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2429				};
2430				map1 {
2431					trip = <&cpu0_alert1>;
2432					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2433							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2434							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2435							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2436				};
2437			};
2438		};
2439
2440		cpu1-thermal {
2441			polling-delay-passive = <250>;
2442			polling-delay = <1000>;
2443
2444			thermal-sensors = <&tsens0 2>;
2445
2446			trips {
2447				cpu1_alert0: trip-point0 {
2448					temperature = <90000>;
2449					hysteresis = <2000>;
2450					type = "passive";
2451				};
2452
2453				cpu1_alert1: trip-point1 {
2454					temperature = <95000>;
2455					hysteresis = <2000>;
2456					type = "passive";
2457				};
2458
2459				cpu1_crit: cpu_crit {
2460					temperature = <110000>;
2461					hysteresis = <1000>;
2462					type = "critical";
2463				};
2464			};
2465
2466			cooling-maps {
2467				map0 {
2468					trip = <&cpu1_alert0>;
2469					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2470							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2471							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2472							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2473				};
2474				map1 {
2475					trip = <&cpu1_alert1>;
2476					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2477							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2478							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2479							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2480				};
2481			};
2482		};
2483
2484		cpu2-thermal {
2485			polling-delay-passive = <250>;
2486			polling-delay = <1000>;
2487
2488			thermal-sensors = <&tsens0 3>;
2489
2490			trips {
2491				cpu2_alert0: trip-point0 {
2492					temperature = <90000>;
2493					hysteresis = <2000>;
2494					type = "passive";
2495				};
2496
2497				cpu2_alert1: trip-point1 {
2498					temperature = <95000>;
2499					hysteresis = <2000>;
2500					type = "passive";
2501				};
2502
2503				cpu2_crit: cpu_crit {
2504					temperature = <110000>;
2505					hysteresis = <1000>;
2506					type = "critical";
2507				};
2508			};
2509
2510			cooling-maps {
2511				map0 {
2512					trip = <&cpu2_alert0>;
2513					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2514							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2515							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2516							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2517				};
2518				map1 {
2519					trip = <&cpu2_alert1>;
2520					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2521							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2522							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2523							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2524				};
2525			};
2526		};
2527
2528		cpu3-thermal {
2529			polling-delay-passive = <250>;
2530			polling-delay = <1000>;
2531
2532			thermal-sensors = <&tsens0 4>;
2533
2534			trips {
2535				cpu3_alert0: trip-point0 {
2536					temperature = <90000>;
2537					hysteresis = <2000>;
2538					type = "passive";
2539				};
2540
2541				cpu3_alert1: trip-point1 {
2542					temperature = <95000>;
2543					hysteresis = <2000>;
2544					type = "passive";
2545				};
2546
2547				cpu3_crit: cpu_crit {
2548					temperature = <110000>;
2549					hysteresis = <1000>;
2550					type = "critical";
2551				};
2552			};
2553
2554			cooling-maps {
2555				map0 {
2556					trip = <&cpu3_alert0>;
2557					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2558							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2559							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2560							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2561				};
2562				map1 {
2563					trip = <&cpu3_alert1>;
2564					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2565							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2566							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2567							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2568				};
2569			};
2570		};
2571
2572		cpu4-top-thermal {
2573			polling-delay-passive = <250>;
2574			polling-delay = <1000>;
2575
2576			thermal-sensors = <&tsens0 7>;
2577
2578			trips {
2579				cpu4_top_alert0: trip-point0 {
2580					temperature = <90000>;
2581					hysteresis = <2000>;
2582					type = "passive";
2583				};
2584
2585				cpu4_top_alert1: trip-point1 {
2586					temperature = <95000>;
2587					hysteresis = <2000>;
2588					type = "passive";
2589				};
2590
2591				cpu4_top_crit: cpu_crit {
2592					temperature = <110000>;
2593					hysteresis = <1000>;
2594					type = "critical";
2595				};
2596			};
2597
2598			cooling-maps {
2599				map0 {
2600					trip = <&cpu4_top_alert0>;
2601					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2602							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2603							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2604							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2605				};
2606				map1 {
2607					trip = <&cpu4_top_alert1>;
2608					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2609							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2610							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2611							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2612				};
2613			};
2614		};
2615
2616		cpu5-top-thermal {
2617			polling-delay-passive = <250>;
2618			polling-delay = <1000>;
2619
2620			thermal-sensors = <&tsens0 8>;
2621
2622			trips {
2623				cpu5_top_alert0: trip-point0 {
2624					temperature = <90000>;
2625					hysteresis = <2000>;
2626					type = "passive";
2627				};
2628
2629				cpu5_top_alert1: trip-point1 {
2630					temperature = <95000>;
2631					hysteresis = <2000>;
2632					type = "passive";
2633				};
2634
2635				cpu5_top_crit: cpu_crit {
2636					temperature = <110000>;
2637					hysteresis = <1000>;
2638					type = "critical";
2639				};
2640			};
2641
2642			cooling-maps {
2643				map0 {
2644					trip = <&cpu5_top_alert0>;
2645					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2646							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2647							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2648							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2649				};
2650				map1 {
2651					trip = <&cpu5_top_alert1>;
2652					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2653							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2654							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2655							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2656				};
2657			};
2658		};
2659
2660		cpu6-top-thermal {
2661			polling-delay-passive = <250>;
2662			polling-delay = <1000>;
2663
2664			thermal-sensors = <&tsens0 9>;
2665
2666			trips {
2667				cpu6_top_alert0: trip-point0 {
2668					temperature = <90000>;
2669					hysteresis = <2000>;
2670					type = "passive";
2671				};
2672
2673				cpu6_top_alert1: trip-point1 {
2674					temperature = <95000>;
2675					hysteresis = <2000>;
2676					type = "passive";
2677				};
2678
2679				cpu6_top_crit: cpu_crit {
2680					temperature = <110000>;
2681					hysteresis = <1000>;
2682					type = "critical";
2683				};
2684			};
2685
2686			cooling-maps {
2687				map0 {
2688					trip = <&cpu6_top_alert0>;
2689					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2690							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2691							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2692							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2693				};
2694				map1 {
2695					trip = <&cpu6_top_alert1>;
2696					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2697							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2698							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2699							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2700				};
2701			};
2702		};
2703
2704		cpu7-top-thermal {
2705			polling-delay-passive = <250>;
2706			polling-delay = <1000>;
2707
2708			thermal-sensors = <&tsens0 10>;
2709
2710			trips {
2711				cpu7_top_alert0: trip-point0 {
2712					temperature = <90000>;
2713					hysteresis = <2000>;
2714					type = "passive";
2715				};
2716
2717				cpu7_top_alert1: trip-point1 {
2718					temperature = <95000>;
2719					hysteresis = <2000>;
2720					type = "passive";
2721				};
2722
2723				cpu7_top_crit: cpu_crit {
2724					temperature = <110000>;
2725					hysteresis = <1000>;
2726					type = "critical";
2727				};
2728			};
2729
2730			cooling-maps {
2731				map0 {
2732					trip = <&cpu7_top_alert0>;
2733					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2734							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2735							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2736							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2737				};
2738				map1 {
2739					trip = <&cpu7_top_alert1>;
2740					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2741							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2742							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2743							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2744				};
2745			};
2746		};
2747
2748		cpu4-bottom-thermal {
2749			polling-delay-passive = <250>;
2750			polling-delay = <1000>;
2751
2752			thermal-sensors = <&tsens0 11>;
2753
2754			trips {
2755				cpu4_bottom_alert0: trip-point0 {
2756					temperature = <90000>;
2757					hysteresis = <2000>;
2758					type = "passive";
2759				};
2760
2761				cpu4_bottom_alert1: trip-point1 {
2762					temperature = <95000>;
2763					hysteresis = <2000>;
2764					type = "passive";
2765				};
2766
2767				cpu4_bottom_crit: cpu_crit {
2768					temperature = <110000>;
2769					hysteresis = <1000>;
2770					type = "critical";
2771				};
2772			};
2773
2774			cooling-maps {
2775				map0 {
2776					trip = <&cpu4_bottom_alert0>;
2777					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2778							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2779							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2780							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2781				};
2782				map1 {
2783					trip = <&cpu4_bottom_alert1>;
2784					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2785							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2786							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2787							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2788				};
2789			};
2790		};
2791
2792		cpu5-bottom-thermal {
2793			polling-delay-passive = <250>;
2794			polling-delay = <1000>;
2795
2796			thermal-sensors = <&tsens0 12>;
2797
2798			trips {
2799				cpu5_bottom_alert0: trip-point0 {
2800					temperature = <90000>;
2801					hysteresis = <2000>;
2802					type = "passive";
2803				};
2804
2805				cpu5_bottom_alert1: trip-point1 {
2806					temperature = <95000>;
2807					hysteresis = <2000>;
2808					type = "passive";
2809				};
2810
2811				cpu5_bottom_crit: cpu_crit {
2812					temperature = <110000>;
2813					hysteresis = <1000>;
2814					type = "critical";
2815				};
2816			};
2817
2818			cooling-maps {
2819				map0 {
2820					trip = <&cpu5_bottom_alert0>;
2821					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2822							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2823							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2824							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2825				};
2826				map1 {
2827					trip = <&cpu5_bottom_alert1>;
2828					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2829							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2830							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2831							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2832				};
2833			};
2834		};
2835
2836		cpu6-bottom-thermal {
2837			polling-delay-passive = <250>;
2838			polling-delay = <1000>;
2839
2840			thermal-sensors = <&tsens0 13>;
2841
2842			trips {
2843				cpu6_bottom_alert0: trip-point0 {
2844					temperature = <90000>;
2845					hysteresis = <2000>;
2846					type = "passive";
2847				};
2848
2849				cpu6_bottom_alert1: trip-point1 {
2850					temperature = <95000>;
2851					hysteresis = <2000>;
2852					type = "passive";
2853				};
2854
2855				cpu6_bottom_crit: cpu_crit {
2856					temperature = <110000>;
2857					hysteresis = <1000>;
2858					type = "critical";
2859				};
2860			};
2861
2862			cooling-maps {
2863				map0 {
2864					trip = <&cpu6_bottom_alert0>;
2865					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2866							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2867							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2868							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2869				};
2870				map1 {
2871					trip = <&cpu6_bottom_alert1>;
2872					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2873							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2874							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2875							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2876				};
2877			};
2878		};
2879
2880		cpu7-bottom-thermal {
2881			polling-delay-passive = <250>;
2882			polling-delay = <1000>;
2883
2884			thermal-sensors = <&tsens0 14>;
2885
2886			trips {
2887				cpu7_bottom_alert0: trip-point0 {
2888					temperature = <90000>;
2889					hysteresis = <2000>;
2890					type = "passive";
2891				};
2892
2893				cpu7_bottom_alert1: trip-point1 {
2894					temperature = <95000>;
2895					hysteresis = <2000>;
2896					type = "passive";
2897				};
2898
2899				cpu7_bottom_crit: cpu_crit {
2900					temperature = <110000>;
2901					hysteresis = <1000>;
2902					type = "critical";
2903				};
2904			};
2905
2906			cooling-maps {
2907				map0 {
2908					trip = <&cpu7_bottom_alert0>;
2909					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2910							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2911							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2912							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2913				};
2914				map1 {
2915					trip = <&cpu7_bottom_alert1>;
2916					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2917							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2918							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2919							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2920				};
2921			};
2922		};
2923
2924		aoss0-thermal {
2925			polling-delay-passive = <250>;
2926			polling-delay = <1000>;
2927
2928			thermal-sensors = <&tsens0 0>;
2929
2930			trips {
2931				aoss0_alert0: trip-point0 {
2932					temperature = <90000>;
2933					hysteresis = <2000>;
2934					type = "hot";
2935				};
2936			};
2937		};
2938
2939		cluster0-thermal {
2940			polling-delay-passive = <250>;
2941			polling-delay = <1000>;
2942
2943			thermal-sensors = <&tsens0 5>;
2944
2945			trips {
2946				cluster0_alert0: trip-point0 {
2947					temperature = <90000>;
2948					hysteresis = <2000>;
2949					type = "hot";
2950				};
2951				cluster0_crit: cluster0_crit {
2952					temperature = <110000>;
2953					hysteresis = <2000>;
2954					type = "critical";
2955				};
2956			};
2957		};
2958
2959		cluster1-thermal {
2960			polling-delay-passive = <250>;
2961			polling-delay = <1000>;
2962
2963			thermal-sensors = <&tsens0 6>;
2964
2965			trips {
2966				cluster1_alert0: trip-point0 {
2967					temperature = <90000>;
2968					hysteresis = <2000>;
2969					type = "hot";
2970				};
2971				cluster1_crit: cluster1_crit {
2972					temperature = <110000>;
2973					hysteresis = <2000>;
2974					type = "critical";
2975				};
2976			};
2977		};
2978
2979		aoss1-thermal {
2980			polling-delay-passive = <250>;
2981			polling-delay = <1000>;
2982
2983			thermal-sensors = <&tsens1 0>;
2984
2985			trips {
2986				aoss1_alert0: trip-point0 {
2987					temperature = <90000>;
2988					hysteresis = <2000>;
2989					type = "hot";
2990				};
2991			};
2992		};
2993
2994		gpu-thermal-top {
2995			polling-delay-passive = <250>;
2996			polling-delay = <1000>;
2997
2998			thermal-sensors = <&tsens1 1>;
2999
3000			trips {
3001				gpu1_alert0: trip-point0 {
3002					temperature = <90000>;
3003					hysteresis = <1000>;
3004					type = "hot";
3005				};
3006			};
3007		};
3008
3009		gpu-thermal-bottom {
3010			polling-delay-passive = <250>;
3011			polling-delay = <1000>;
3012
3013			thermal-sensors = <&tsens1 2>;
3014
3015			trips {
3016				gpu2_alert0: trip-point0 {
3017					temperature = <90000>;
3018					hysteresis = <1000>;
3019					type = "hot";
3020				};
3021			};
3022		};
3023
3024		nspss1-thermal {
3025			polling-delay-passive = <250>;
3026			polling-delay = <1000>;
3027
3028			thermal-sensors = <&tsens1 3>;
3029
3030			trips {
3031				nspss1_alert0: trip-point0 {
3032					temperature = <90000>;
3033					hysteresis = <1000>;
3034					type = "hot";
3035				};
3036			};
3037		};
3038
3039		nspss2-thermal {
3040			polling-delay-passive = <250>;
3041			polling-delay = <1000>;
3042
3043			thermal-sensors = <&tsens1 4>;
3044
3045			trips {
3046				nspss2_alert0: trip-point0 {
3047					temperature = <90000>;
3048					hysteresis = <1000>;
3049					type = "hot";
3050				};
3051			};
3052		};
3053
3054		nspss3-thermal {
3055			polling-delay-passive = <250>;
3056			polling-delay = <1000>;
3057
3058			thermal-sensors = <&tsens1 5>;
3059
3060			trips {
3061				nspss3_alert0: trip-point0 {
3062					temperature = <90000>;
3063					hysteresis = <1000>;
3064					type = "hot";
3065				};
3066			};
3067		};
3068
3069		video-thermal {
3070			polling-delay-passive = <250>;
3071			polling-delay = <1000>;
3072
3073			thermal-sensors = <&tsens1 6>;
3074
3075			trips {
3076				video_alert0: trip-point0 {
3077					temperature = <90000>;
3078					hysteresis = <2000>;
3079					type = "hot";
3080				};
3081			};
3082		};
3083
3084		mem-thermal {
3085			polling-delay-passive = <250>;
3086			polling-delay = <1000>;
3087
3088			thermal-sensors = <&tsens1 7>;
3089
3090			trips {
3091				mem_alert0: trip-point0 {
3092					temperature = <90000>;
3093					hysteresis = <2000>;
3094					type = "hot";
3095				};
3096			};
3097		};
3098
3099		modem1-thermal-top {
3100			polling-delay-passive = <250>;
3101			polling-delay = <1000>;
3102
3103			thermal-sensors = <&tsens1 8>;
3104
3105			trips {
3106				modem1_alert0: trip-point0 {
3107					temperature = <90000>;
3108					hysteresis = <2000>;
3109					type = "hot";
3110				};
3111			};
3112		};
3113
3114		modem2-thermal-top {
3115			polling-delay-passive = <250>;
3116			polling-delay = <1000>;
3117
3118			thermal-sensors = <&tsens1 9>;
3119
3120			trips {
3121				modem2_alert0: trip-point0 {
3122					temperature = <90000>;
3123					hysteresis = <2000>;
3124					type = "hot";
3125				};
3126			};
3127		};
3128
3129		modem3-thermal-top {
3130			polling-delay-passive = <250>;
3131			polling-delay = <1000>;
3132
3133			thermal-sensors = <&tsens1 10>;
3134
3135			trips {
3136				modem3_alert0: trip-point0 {
3137					temperature = <90000>;
3138					hysteresis = <2000>;
3139					type = "hot";
3140				};
3141			};
3142		};
3143
3144		modem4-thermal-top {
3145			polling-delay-passive = <250>;
3146			polling-delay = <1000>;
3147
3148			thermal-sensors = <&tsens1 11>;
3149
3150			trips {
3151				modem4_alert0: trip-point0 {
3152					temperature = <90000>;
3153					hysteresis = <2000>;
3154					type = "hot";
3155				};
3156			};
3157		};
3158
3159		camera-thermal-top {
3160			polling-delay-passive = <250>;
3161			polling-delay = <1000>;
3162
3163			thermal-sensors = <&tsens1 12>;
3164
3165			trips {
3166				camera1_alert0: trip-point0 {
3167					temperature = <90000>;
3168					hysteresis = <2000>;
3169					type = "hot";
3170				};
3171			};
3172		};
3173
3174		cam-thermal-bottom {
3175			polling-delay-passive = <250>;
3176			polling-delay = <1000>;
3177
3178			thermal-sensors = <&tsens1 13>;
3179
3180			trips {
3181				camera2_alert0: trip-point0 {
3182					temperature = <90000>;
3183					hysteresis = <2000>;
3184					type = "hot";
3185				};
3186			};
3187		};
3188	};
3189
3190	timer {
3191		compatible = "arm,armv8-timer";
3192		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3193			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3194			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3195			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3196	};
3197};
3198