1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limaited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/mailbox/qcom-ipcc.h> 9#include <dt-bindings/power/qcom-aoss-qmp.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <38400000>; 26 clock-output-names = "xo_board"; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 clock-frequency = <32000>; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo685"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 L2_0: l2-cache { 47 compatible = "cache"; 48 next-level-cache = <&L3_0>; 49 L3_0: l3-cache { 50 compatible = "cache"; 51 }; 52 }; 53 }; 54 55 CPU1: cpu@100 { 56 device_type = "cpu"; 57 compatible = "qcom,kryo685"; 58 reg = <0x0 0x100>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_100>; 61 L2_100: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 }; 65 }; 66 67 CPU2: cpu@200 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo685"; 70 reg = <0x0 0x200>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_200>; 73 L2_200: l2-cache { 74 compatible = "cache"; 75 next-level-cache = <&L3_0>; 76 }; 77 }; 78 79 CPU3: cpu@300 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo685"; 82 reg = <0x0 0x300>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_300>; 85 L2_300: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU4: cpu@400 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo685"; 94 reg = <0x0 0x400>; 95 enable-method = "psci"; 96 next-level-cache = <&L2_400>; 97 L2_400: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU5: cpu@500 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo685"; 106 reg = <0x0 0x500>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_500>; 109 L2_500: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 114 }; 115 116 CPU6: cpu@600 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo685"; 119 reg = <0x0 0x600>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_600>; 122 L2_600: l2-cache { 123 compatible = "cache"; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU7: cpu@700 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo685"; 131 reg = <0x0 0x700>; 132 enable-method = "psci"; 133 next-level-cache = <&L2_700>; 134 L2_700: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 }; 140 141 firmware { 142 scm: scm { 143 compatible = "qcom,scm-sm8350", "qcom,scm"; 144 #reset-cells = <1>; 145 }; 146 }; 147 148 memory@80000000 { 149 device_type = "memory"; 150 /* We expect the bootloader to fill in the size */ 151 reg = <0x0 0x80000000 0x0 0x0>; 152 }; 153 154 pmu { 155 compatible = "arm,armv8-pmuv3"; 156 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0"; 161 method = "smc"; 162 }; 163 164 reserved_memory: reserved-memory { 165 #address-cells = <2>; 166 #size-cells = <2>; 167 ranges; 168 169 hyp_mem: memory@80000000 { 170 reg = <0x0 0x80000000 0x0 0x600000>; 171 no-map; 172 }; 173 174 xbl_aop_mem: memory@80700000 { 175 no-map; 176 reg = <0x0 0x80700000 0x0 0x160000>; 177 }; 178 179 cmd_db: memory@80860000 { 180 compatible = "qcom,cmd-db"; 181 reg = <0x0 0x80860000 0x0 0x20000>; 182 no-map; 183 }; 184 185 reserved_xbl_uefi_log: memory@80880000 { 186 reg = <0x0 0x80880000 0x0 0x14000>; 187 no-map; 188 }; 189 190 smem_mem: memory@80900000 { 191 reg = <0x0 0x80900000 0x0 0x200000>; 192 no-map; 193 }; 194 195 cpucp_fw_mem: memory@80b00000 { 196 reg = <0x0 0x80b00000 0x0 0x100000>; 197 no-map; 198 }; 199 200 cdsp_secure_heap: memory@80c00000 { 201 reg = <0x0 0x80c00000 0x0 0x4600000>; 202 no-map; 203 }; 204 205 pil_camera_mem: mmeory@85200000 { 206 reg = <0x0 0x85200000 0x0 0x500000>; 207 no-map; 208 }; 209 210 pil_video_mem: memory@85700000 { 211 reg = <0x0 0x85700000 0x0 0x500000>; 212 no-map; 213 }; 214 215 pil_cvp_mem: memory@85c00000 { 216 reg = <0x0 0x85c00000 0x0 0x500000>; 217 no-map; 218 }; 219 220 pil_adsp_mem: memory@86100000 { 221 reg = <0x0 0x86100000 0x0 0x2100000>; 222 no-map; 223 }; 224 225 pil_slpi_mem: memory@88200000 { 226 reg = <0x0 0x88200000 0x0 0x1500000>; 227 no-map; 228 }; 229 230 pil_cdsp_mem: memory@89700000 { 231 reg = <0x0 0x89700000 0x0 0x1e00000>; 232 no-map; 233 }; 234 235 pil_ipa_fw_mem: memory@8b500000 { 236 reg = <0x0 0x8b500000 0x0 0x10000>; 237 no-map; 238 }; 239 240 pil_ipa_gsi_mem: memory@8b510000 { 241 reg = <0x0 0x8b510000 0x0 0xa000>; 242 no-map; 243 }; 244 245 pil_gpu_mem: memory@8b51a000 { 246 reg = <0x0 0x8b51a000 0x0 0x2000>; 247 no-map; 248 }; 249 250 pil_spss_mem: memory@8b600000 { 251 reg = <0x0 0x8b600000 0x0 0x100000>; 252 no-map; 253 }; 254 255 pil_modem_mem: memory@8b800000 { 256 reg = <0x0 0x8b800000 0x0 0x10000000>; 257 no-map; 258 }; 259 260 hyp_reserved_mem: memory@d0000000 { 261 reg = <0x0 0xd0000000 0x0 0x800000>; 262 no-map; 263 }; 264 265 pil_trustedvm_mem: memory@d0800000 { 266 reg = <0x0 0xd0800000 0x0 0x76f7000>; 267 no-map; 268 }; 269 270 qrtr_shbuf: memory@d7ef7000 { 271 reg = <0x0 0xd7ef7000 0x0 0x9000>; 272 no-map; 273 }; 274 275 chan0_shbuf: memory@d7f00000 { 276 reg = <0x0 0xd7f00000 0x0 0x80000>; 277 no-map; 278 }; 279 280 chan1_shbuf: memory@d7f80000 { 281 reg = <0x0 0xd7f80000 0x0 0x80000>; 282 no-map; 283 }; 284 285 removed_mem: memory@d8800000 { 286 reg = <0x0 0xd8800000 0x0 0x6800000>; 287 no-map; 288 }; 289 }; 290 291 smem: qcom,smem { 292 compatible = "qcom,smem"; 293 memory-region = <&smem_mem>; 294 hwlocks = <&tcsr_mutex 3>; 295 }; 296 297 soc: soc@0 { 298 #address-cells = <2>; 299 #size-cells = <2>; 300 ranges = <0 0 0 0 0x10 0>; 301 dma-ranges = <0 0 0 0 0x10 0>; 302 compatible = "simple-bus"; 303 304 gcc: clock-controller@100000 { 305 compatible = "qcom,gcc-sm8350"; 306 reg = <0x0 0x00100000 0x0 0x1f0000>; 307 #clock-cells = <1>; 308 #reset-cells = <1>; 309 #power-domain-cells = <1>; 310 clock-names = "bi_tcxo", "sleep_clk"; 311 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 312 }; 313 314 ipcc: mailbox@408000 { 315 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 316 reg = <0 0x00408000 0 0x1000>; 317 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-controller; 319 #interrupt-cells = <3>; 320 #mbox-cells = <2>; 321 }; 322 323 qupv3_id_1: geniqup@9c0000 { 324 compatible = "qcom,geni-se-qup"; 325 reg = <0x0 0x009c0000 0x0 0x6000>; 326 clock-names = "m-ahb", "s-ahb"; 327 clocks = <&gcc 121>, 328 <&gcc 122>; 329 #address-cells = <2>; 330 #size-cells = <2>; 331 ranges; 332 status = "disabled"; 333 334 uart2: serial@98c000 { 335 compatible = "qcom,geni-debug-uart"; 336 reg = <0 0x0098c000 0 0x4000>; 337 clock-names = "se"; 338 clocks = <&gcc 83>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&qup_uart3_default_state>; 341 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 status = "disabled"; 345 }; 346 }; 347 348 tcsr_mutex: hwlock@1f40000 { 349 compatible = "qcom,tcsr-mutex"; 350 reg = <0x0 0x01f40000 0x0 0x40000>; 351 #hwlock-cells = <1>; 352 }; 353 354 pdc: interrupt-controller@b220000 { 355 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 356 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 357 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 358 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 359 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 360 <156 716 12>; 361 #interrupt-cells = <2>; 362 interrupt-parent = <&intc>; 363 interrupt-controller; 364 }; 365 366 aoss_qmp: qmp@c300000 { 367 compatible = "qcom,sm8350-aoss-qmp"; 368 reg = <0 0x0c300000 0 0x100000>; 369 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 370 IRQ_TYPE_EDGE_RISING>; 371 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 372 373 #clock-cells = <0>; 374 #power-domain-cells = <1>; 375 }; 376 377 tlmm: pinctrl@f100000 { 378 compatible = "qcom,sm8350-tlmm"; 379 reg = <0 0x0f100000 0 0x300000>; 380 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 gpio-ranges = <&tlmm 0 0 203>; 386 387 qup_uart3_default_state: qup-uart3-default-state { 388 rx { 389 pins = "gpio18"; 390 function = "qup3"; 391 }; 392 tx { 393 pins = "gpio19"; 394 function = "qup3"; 395 }; 396 }; 397 }; 398 399 intc: interrupt-controller@17a00000 { 400 compatible = "arm,gic-v3"; 401 #interrupt-cells = <3>; 402 interrupt-controller; 403 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 404 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 405 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 406 }; 407 408 timer@17c20000 { 409 compatible = "arm,armv7-timer-mem"; 410 #address-cells = <2>; 411 #size-cells = <2>; 412 ranges; 413 reg = <0x0 0x17c20000 0x0 0x1000>; 414 clock-frequency = <19200000>; 415 416 frame@17c21000 { 417 frame-number = <0>; 418 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 420 reg = <0x0 0x17c21000 0x0 0x1000>, 421 <0x0 0x17c22000 0x0 0x1000>; 422 }; 423 424 frame@17c23000 { 425 frame-number = <1>; 426 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 427 reg = <0x0 0x17c23000 0x0 0x1000>; 428 status = "disabled"; 429 }; 430 431 frame@17c25000 { 432 frame-number = <2>; 433 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 434 reg = <0x0 0x17c25000 0x0 0x1000>; 435 status = "disabled"; 436 }; 437 438 frame@17c27000 { 439 frame-number = <3>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 reg = <0x0 0x17c27000 0x0 0x1000>; 442 status = "disabled"; 443 }; 444 445 frame@17c29000 { 446 frame-number = <4>; 447 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 448 reg = <0x0 0x17c29000 0x0 0x1000>; 449 status = "disabled"; 450 }; 451 452 frame@17c2b000 { 453 frame-number = <5>; 454 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 455 reg = <0x0 0x17c2b000 0x0 0x1000>; 456 status = "disabled"; 457 }; 458 459 frame@17c2d000 { 460 frame-number = <6>; 461 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 462 reg = <0x0 0x17c2d000 0x0 0x1000>; 463 status = "disabled"; 464 }; 465 }; 466 467 apps_rsc: rsc@18200000 { 468 label = "apps_rsc"; 469 compatible = "qcom,rpmh-rsc"; 470 reg = <0x0 0x18200000 0x0 0x10000>, 471 <0x0 0x18210000 0x0 0x10000>, 472 <0x0 0x18220000 0x0 0x10000>; 473 reg-names = "drv-0", "drv-1", "drv-2"; 474 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 477 qcom,tcs-offset = <0xd00>; 478 qcom,drv-id = <2>; 479 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 480 <WAKE_TCS 3>, <CONTROL_TCS 1>; 481 482 rpmhcc: clock-controller { 483 compatible = "qcom,sm8350-rpmh-clk"; 484 #clock-cells = <1>; 485 clock-names = "xo"; 486 clocks = <&xo_board>; 487 }; 488 489 }; 490 }; 491 492 timer { 493 compatible = "arm,armv8-timer"; 494 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 495 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 496 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 497 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 498 }; 499}; 500