1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/interconnect/qcom,sm8350.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <38400000>; 38 clock-output-names = "xo_board"; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32000>; 44 #clock-cells = <0>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 CPU0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 L3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_200>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 #cooling-cells = <2>; 106 L2_200: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&L3_0>; 111 }; 112 }; 113 114 CPU3: cpu@300 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a55"; 117 reg = <0x0 0x300>; 118 clocks = <&cpufreq_hw 0>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU4: cpu@400 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a78"; 136 reg = <0x0 0x400>; 137 clocks = <&cpufreq_hw 1>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_400>; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 power-domains = <&CPU_PD4>; 142 power-domain-names = "psci"; 143 #cooling-cells = <2>; 144 L2_400: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a78"; 155 reg = <0x0 0x500>; 156 clocks = <&cpufreq_hw 1>; 157 enable-method = "psci"; 158 next-level-cache = <&L2_500>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 power-domains = <&CPU_PD5>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 L2_500: l2-cache { 164 compatible = "cache"; 165 cache-level = <2>; 166 cache-unified; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU6: cpu@600 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a78"; 174 reg = <0x0 0x600>; 175 clocks = <&cpufreq_hw 1>; 176 enable-method = "psci"; 177 next-level-cache = <&L2_600>; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 power-domains = <&CPU_PD6>; 180 power-domain-names = "psci"; 181 #cooling-cells = <2>; 182 L2_600: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 }; 188 }; 189 190 CPU7: cpu@700 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-x1"; 193 reg = <0x0 0x700>; 194 clocks = <&cpufreq_hw 2>; 195 enable-method = "psci"; 196 next-level-cache = <&L2_700>; 197 qcom,freq-domain = <&cpufreq_hw 2>; 198 power-domains = <&CPU_PD7>; 199 power-domain-names = "psci"; 200 #cooling-cells = <2>; 201 L2_700: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 cpu-map { 210 cluster0 { 211 core0 { 212 cpu = <&CPU0>; 213 }; 214 215 core1 { 216 cpu = <&CPU1>; 217 }; 218 219 core2 { 220 cpu = <&CPU2>; 221 }; 222 223 core3 { 224 cpu = <&CPU3>; 225 }; 226 227 core4 { 228 cpu = <&CPU4>; 229 }; 230 231 core5 { 232 cpu = <&CPU5>; 233 }; 234 235 core6 { 236 cpu = <&CPU6>; 237 }; 238 239 core7 { 240 cpu = <&CPU7>; 241 }; 242 }; 243 }; 244 245 idle-states { 246 entry-method = "psci"; 247 248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 249 compatible = "arm,idle-state"; 250 idle-state-name = "silver-rail-power-collapse"; 251 arm,psci-suspend-param = <0x40000004>; 252 entry-latency-us = <360>; 253 exit-latency-us = <531>; 254 min-residency-us = <3934>; 255 local-timer-stop; 256 }; 257 258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 259 compatible = "arm,idle-state"; 260 idle-state-name = "gold-rail-power-collapse"; 261 arm,psci-suspend-param = <0x40000004>; 262 entry-latency-us = <702>; 263 exit-latency-us = <1061>; 264 min-residency-us = <4488>; 265 local-timer-stop; 266 }; 267 }; 268 269 domain-idle-states { 270 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 271 compatible = "domain-idle-state"; 272 arm,psci-suspend-param = <0x41000044>; 273 entry-latency-us = <2752>; 274 exit-latency-us = <3048>; 275 min-residency-us = <6118>; 276 }; 277 278 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x4100c344>; 281 entry-latency-us = <3263>; 282 exit-latency-us = <6562>; 283 min-residency-us = <9987>; 284 }; 285 }; 286 }; 287 288 firmware { 289 scm: scm { 290 compatible = "qcom,scm-sm8350", "qcom,scm"; 291 #reset-cells = <1>; 292 }; 293 }; 294 295 memory@80000000 { 296 device_type = "memory"; 297 /* We expect the bootloader to fill in the size */ 298 reg = <0x0 0x80000000 0x0 0x0>; 299 }; 300 301 pmu { 302 compatible = "arm,armv8-pmuv3"; 303 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 304 }; 305 306 psci { 307 compatible = "arm,psci-1.0"; 308 method = "smc"; 309 310 CPU_PD0: power-domain-cpu0 { 311 #power-domain-cells = <0>; 312 power-domains = <&CLUSTER_PD>; 313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 314 }; 315 316 CPU_PD1: power-domain-cpu1 { 317 #power-domain-cells = <0>; 318 power-domains = <&CLUSTER_PD>; 319 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 320 }; 321 322 CPU_PD2: power-domain-cpu2 { 323 #power-domain-cells = <0>; 324 power-domains = <&CLUSTER_PD>; 325 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 326 }; 327 328 CPU_PD3: power-domain-cpu3 { 329 #power-domain-cells = <0>; 330 power-domains = <&CLUSTER_PD>; 331 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 332 }; 333 334 CPU_PD4: power-domain-cpu4 { 335 #power-domain-cells = <0>; 336 power-domains = <&CLUSTER_PD>; 337 domain-idle-states = <&BIG_CPU_SLEEP_0>; 338 }; 339 340 CPU_PD5: power-domain-cpu5 { 341 #power-domain-cells = <0>; 342 power-domains = <&CLUSTER_PD>; 343 domain-idle-states = <&BIG_CPU_SLEEP_0>; 344 }; 345 346 CPU_PD6: power-domain-cpu6 { 347 #power-domain-cells = <0>; 348 power-domains = <&CLUSTER_PD>; 349 domain-idle-states = <&BIG_CPU_SLEEP_0>; 350 }; 351 352 CPU_PD7: power-domain-cpu7 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD>; 355 domain-idle-states = <&BIG_CPU_SLEEP_0>; 356 }; 357 358 CLUSTER_PD: power-domain-cpu-cluster0 { 359 #power-domain-cells = <0>; 360 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 361 }; 362 }; 363 364 qup_opp_table_100mhz: opp-table-qup100mhz { 365 compatible = "operating-points-v2"; 366 367 opp-50000000 { 368 opp-hz = /bits/ 64 <50000000>; 369 required-opps = <&rpmhpd_opp_min_svs>; 370 }; 371 372 opp-75000000 { 373 opp-hz = /bits/ 64 <75000000>; 374 required-opps = <&rpmhpd_opp_low_svs>; 375 }; 376 377 opp-100000000 { 378 opp-hz = /bits/ 64 <100000000>; 379 required-opps = <&rpmhpd_opp_svs>; 380 }; 381 }; 382 383 qup_opp_table_120mhz: opp-table-qup120mhz { 384 compatible = "operating-points-v2"; 385 386 opp-50000000 { 387 opp-hz = /bits/ 64 <50000000>; 388 required-opps = <&rpmhpd_opp_min_svs>; 389 }; 390 391 opp-75000000 { 392 opp-hz = /bits/ 64 <75000000>; 393 required-opps = <&rpmhpd_opp_low_svs>; 394 }; 395 396 opp-120000000 { 397 opp-hz = /bits/ 64 <120000000>; 398 required-opps = <&rpmhpd_opp_svs>; 399 }; 400 }; 401 402 reserved_memory: reserved-memory { 403 #address-cells = <2>; 404 #size-cells = <2>; 405 ranges; 406 407 hyp_mem: memory@80000000 { 408 reg = <0x0 0x80000000 0x0 0x600000>; 409 no-map; 410 }; 411 412 xbl_aop_mem: memory@80700000 { 413 no-map; 414 reg = <0x0 0x80700000 0x0 0x160000>; 415 }; 416 417 cmd_db: memory@80860000 { 418 compatible = "qcom,cmd-db"; 419 reg = <0x0 0x80860000 0x0 0x20000>; 420 no-map; 421 }; 422 423 reserved_xbl_uefi_log: memory@80880000 { 424 reg = <0x0 0x80880000 0x0 0x14000>; 425 no-map; 426 }; 427 428 smem@80900000 { 429 compatible = "qcom,smem"; 430 reg = <0x0 0x80900000 0x0 0x200000>; 431 hwlocks = <&tcsr_mutex 3>; 432 no-map; 433 }; 434 435 cpucp_fw_mem: memory@80b00000 { 436 reg = <0x0 0x80b00000 0x0 0x100000>; 437 no-map; 438 }; 439 440 cdsp_secure_heap: memory@80c00000 { 441 reg = <0x0 0x80c00000 0x0 0x4600000>; 442 no-map; 443 }; 444 445 pil_camera_mem: mmeory@85200000 { 446 reg = <0x0 0x85200000 0x0 0x500000>; 447 no-map; 448 }; 449 450 pil_video_mem: memory@85700000 { 451 reg = <0x0 0x85700000 0x0 0x500000>; 452 no-map; 453 }; 454 455 pil_cvp_mem: memory@85c00000 { 456 reg = <0x0 0x85c00000 0x0 0x500000>; 457 no-map; 458 }; 459 460 pil_adsp_mem: memory@86100000 { 461 reg = <0x0 0x86100000 0x0 0x2100000>; 462 no-map; 463 }; 464 465 pil_slpi_mem: memory@88200000 { 466 reg = <0x0 0x88200000 0x0 0x1500000>; 467 no-map; 468 }; 469 470 pil_cdsp_mem: memory@89700000 { 471 reg = <0x0 0x89700000 0x0 0x1e00000>; 472 no-map; 473 }; 474 475 pil_ipa_fw_mem: memory@8b500000 { 476 reg = <0x0 0x8b500000 0x0 0x10000>; 477 no-map; 478 }; 479 480 pil_ipa_gsi_mem: memory@8b510000 { 481 reg = <0x0 0x8b510000 0x0 0xa000>; 482 no-map; 483 }; 484 485 pil_gpu_mem: memory@8b51a000 { 486 reg = <0x0 0x8b51a000 0x0 0x2000>; 487 no-map; 488 }; 489 490 pil_spss_mem: memory@8b600000 { 491 reg = <0x0 0x8b600000 0x0 0x100000>; 492 no-map; 493 }; 494 495 pil_modem_mem: memory@8b800000 { 496 reg = <0x0 0x8b800000 0x0 0x10000000>; 497 no-map; 498 }; 499 500 rmtfs_mem: memory@9b800000 { 501 compatible = "qcom,rmtfs-mem"; 502 reg = <0x0 0x9b800000 0x0 0x280000>; 503 no-map; 504 505 qcom,client-id = <1>; 506 qcom,vmid = <15>; 507 }; 508 509 hyp_reserved_mem: memory@d0000000 { 510 reg = <0x0 0xd0000000 0x0 0x800000>; 511 no-map; 512 }; 513 514 pil_trustedvm_mem: memory@d0800000 { 515 reg = <0x0 0xd0800000 0x0 0x76f7000>; 516 no-map; 517 }; 518 519 qrtr_shbuf: memory@d7ef7000 { 520 reg = <0x0 0xd7ef7000 0x0 0x9000>; 521 no-map; 522 }; 523 524 chan0_shbuf: memory@d7f00000 { 525 reg = <0x0 0xd7f00000 0x0 0x80000>; 526 no-map; 527 }; 528 529 chan1_shbuf: memory@d7f80000 { 530 reg = <0x0 0xd7f80000 0x0 0x80000>; 531 no-map; 532 }; 533 534 removed_mem: memory@d8800000 { 535 reg = <0x0 0xd8800000 0x0 0x6800000>; 536 no-map; 537 }; 538 }; 539 540 smp2p-adsp { 541 compatible = "qcom,smp2p"; 542 qcom,smem = <443>, <429>; 543 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 544 IPCC_MPROC_SIGNAL_SMP2P 545 IRQ_TYPE_EDGE_RISING>; 546 mboxes = <&ipcc IPCC_CLIENT_LPASS 547 IPCC_MPROC_SIGNAL_SMP2P>; 548 549 qcom,local-pid = <0>; 550 qcom,remote-pid = <2>; 551 552 smp2p_adsp_out: master-kernel { 553 qcom,entry-name = "master-kernel"; 554 #qcom,smem-state-cells = <1>; 555 }; 556 557 smp2p_adsp_in: slave-kernel { 558 qcom,entry-name = "slave-kernel"; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 }; 562 }; 563 564 smp2p-cdsp { 565 compatible = "qcom,smp2p"; 566 qcom,smem = <94>, <432>; 567 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 568 IPCC_MPROC_SIGNAL_SMP2P 569 IRQ_TYPE_EDGE_RISING>; 570 mboxes = <&ipcc IPCC_CLIENT_CDSP 571 IPCC_MPROC_SIGNAL_SMP2P>; 572 573 qcom,local-pid = <0>; 574 qcom,remote-pid = <5>; 575 576 smp2p_cdsp_out: master-kernel { 577 qcom,entry-name = "master-kernel"; 578 #qcom,smem-state-cells = <1>; 579 }; 580 581 smp2p_cdsp_in: slave-kernel { 582 qcom,entry-name = "slave-kernel"; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 }; 587 588 smp2p-modem { 589 compatible = "qcom,smp2p"; 590 qcom,smem = <435>, <428>; 591 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 592 IPCC_MPROC_SIGNAL_SMP2P 593 IRQ_TYPE_EDGE_RISING>; 594 mboxes = <&ipcc IPCC_CLIENT_MPSS 595 IPCC_MPROC_SIGNAL_SMP2P>; 596 597 qcom,local-pid = <0>; 598 qcom,remote-pid = <1>; 599 600 smp2p_modem_out: master-kernel { 601 qcom,entry-name = "master-kernel"; 602 #qcom,smem-state-cells = <1>; 603 }; 604 605 smp2p_modem_in: slave-kernel { 606 qcom,entry-name = "slave-kernel"; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 ipa_smp2p_out: ipa-ap-to-modem { 612 qcom,entry-name = "ipa"; 613 #qcom,smem-state-cells = <1>; 614 }; 615 616 ipa_smp2p_in: ipa-modem-to-ap { 617 qcom,entry-name = "ipa"; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 }; 621 }; 622 623 smp2p-slpi { 624 compatible = "qcom,smp2p"; 625 qcom,smem = <481>, <430>; 626 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 627 IPCC_MPROC_SIGNAL_SMP2P 628 IRQ_TYPE_EDGE_RISING>; 629 mboxes = <&ipcc IPCC_CLIENT_SLPI 630 IPCC_MPROC_SIGNAL_SMP2P>; 631 632 qcom,local-pid = <0>; 633 qcom,remote-pid = <3>; 634 635 smp2p_slpi_out: master-kernel { 636 qcom,entry-name = "master-kernel"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 smp2p_slpi_in: slave-kernel { 641 qcom,entry-name = "slave-kernel"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 }; 646 647 soc: soc@0 { 648 #address-cells = <2>; 649 #size-cells = <2>; 650 ranges = <0 0 0 0 0x10 0>; 651 dma-ranges = <0 0 0 0 0x10 0>; 652 compatible = "simple-bus"; 653 654 gcc: clock-controller@100000 { 655 compatible = "qcom,gcc-sm8350"; 656 reg = <0x0 0x00100000 0x0 0x1f0000>; 657 #clock-cells = <1>; 658 #reset-cells = <1>; 659 #power-domain-cells = <1>; 660 clock-names = "bi_tcxo", 661 "sleep_clk", 662 "pcie_0_pipe_clk", 663 "pcie_1_pipe_clk", 664 "ufs_card_rx_symbol_0_clk", 665 "ufs_card_rx_symbol_1_clk", 666 "ufs_card_tx_symbol_0_clk", 667 "ufs_phy_rx_symbol_0_clk", 668 "ufs_phy_rx_symbol_1_clk", 669 "ufs_phy_tx_symbol_0_clk", 670 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 671 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 672 clocks = <&rpmhcc RPMH_CXO_CLK>, 673 <&sleep_clk>, 674 <&pcie0_phy>, 675 <&pcie1_phy>, 676 <0>, 677 <0>, 678 <0>, 679 <&ufs_mem_phy_lanes 0>, 680 <&ufs_mem_phy_lanes 1>, 681 <&ufs_mem_phy_lanes 2>, 682 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 683 <0>; 684 }; 685 686 ipcc: mailbox@408000 { 687 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 688 reg = <0 0x00408000 0 0x1000>; 689 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-controller; 691 #interrupt-cells = <3>; 692 #mbox-cells = <2>; 693 }; 694 695 gpi_dma2: dma-controller@800000 { 696 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 697 reg = <0 0x00800000 0 0x60000>; 698 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 710 dma-channels = <12>; 711 dma-channel-mask = <0xff>; 712 iommus = <&apps_smmu 0x5f6 0x0>; 713 #dma-cells = <3>; 714 status = "disabled"; 715 }; 716 717 qupv3_id_2: geniqup@8c0000 { 718 compatible = "qcom,geni-se-qup"; 719 reg = <0x0 0x008c0000 0x0 0x6000>; 720 clock-names = "m-ahb", "s-ahb"; 721 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 722 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 723 iommus = <&apps_smmu 0x5e3 0x0>; 724 #address-cells = <2>; 725 #size-cells = <2>; 726 ranges; 727 status = "disabled"; 728 729 i2c14: i2c@880000 { 730 compatible = "qcom,geni-i2c"; 731 reg = <0 0x00880000 0 0x4000>; 732 clock-names = "se"; 733 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&qup_i2c14_default>; 736 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 737 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 738 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 739 dma-names = "tx", "rx"; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 spi14: spi@880000 { 746 compatible = "qcom,geni-spi"; 747 reg = <0 0x00880000 0 0x4000>; 748 clock-names = "se"; 749 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 750 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 751 power-domains = <&rpmhpd RPMHPD_CX>; 752 operating-points-v2 = <&qup_opp_table_120mhz>; 753 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 754 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 755 dma-names = "tx", "rx"; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 i2c15: i2c@884000 { 762 compatible = "qcom,geni-i2c"; 763 reg = <0 0x00884000 0 0x4000>; 764 clock-names = "se"; 765 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&qup_i2c15_default>; 768 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 769 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 770 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 771 dma-names = "tx", "rx"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 spi15: spi@884000 { 778 compatible = "qcom,geni-spi"; 779 reg = <0 0x00884000 0 0x4000>; 780 clock-names = "se"; 781 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 782 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 783 power-domains = <&rpmhpd RPMHPD_CX>; 784 operating-points-v2 = <&qup_opp_table_120mhz>; 785 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 786 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 787 dma-names = "tx", "rx"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 i2c16: i2c@888000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0 0x00888000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c16_default>; 800 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 801 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 802 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 803 dma-names = "tx", "rx"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 spi16: spi@888000 { 810 compatible = "qcom,geni-spi"; 811 reg = <0 0x00888000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 814 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 815 power-domains = <&rpmhpd RPMHPD_CX>; 816 operating-points-v2 = <&qup_opp_table_100mhz>; 817 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 818 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 819 dma-names = "tx", "rx"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 i2c17: i2c@88c000 { 826 compatible = "qcom,geni-i2c"; 827 reg = <0 0x0088c000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&qup_i2c17_default>; 832 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 833 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 834 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 835 dma-names = "tx", "rx"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 spi17: spi@88c000 { 842 compatible = "qcom,geni-spi"; 843 reg = <0 0x0088c000 0 0x4000>; 844 clock-names = "se"; 845 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 846 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 847 power-domains = <&rpmhpd RPMHPD_CX>; 848 operating-points-v2 = <&qup_opp_table_100mhz>; 849 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 850 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 /* QUP no. 18 seems to be strictly SPI/UART-only */ 858 859 spi18: spi@890000 { 860 compatible = "qcom,geni-spi"; 861 reg = <0 0x00890000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 864 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 865 power-domains = <&rpmhpd RPMHPD_CX>; 866 operating-points-v2 = <&qup_opp_table_100mhz>; 867 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 869 dma-names = "tx", "rx"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 status = "disabled"; 873 }; 874 875 uart18: serial@890000 { 876 compatible = "qcom,geni-uart"; 877 reg = <0 0x00890000 0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_uart18_default>; 882 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&rpmhpd RPMHPD_CX>; 884 operating-points-v2 = <&qup_opp_table_100mhz>; 885 status = "disabled"; 886 }; 887 888 i2c19: i2c@894000 { 889 compatible = "qcom,geni-i2c"; 890 reg = <0 0x00894000 0 0x4000>; 891 clock-names = "se"; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_i2c19_default>; 895 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 896 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 897 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 898 dma-names = "tx", "rx"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 spi19: spi@894000 { 905 compatible = "qcom,geni-spi"; 906 reg = <0 0x00894000 0 0x4000>; 907 clock-names = "se"; 908 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 909 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 910 power-domains = <&rpmhpd RPMHPD_CX>; 911 operating-points-v2 = <&qup_opp_table_100mhz>; 912 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 913 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 914 dma-names = "tx", "rx"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 }; 920 921 gpi_dma0: dma-controller@900000 { 922 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 923 reg = <0 0x00900000 0 0x60000>; 924 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 936 dma-channels = <12>; 937 dma-channel-mask = <0x7e>; 938 iommus = <&apps_smmu 0x5b6 0x0>; 939 #dma-cells = <3>; 940 status = "disabled"; 941 }; 942 943 qupv3_id_0: geniqup@9c0000 { 944 compatible = "qcom,geni-se-qup"; 945 reg = <0x0 0x009c0000 0x0 0x6000>; 946 clock-names = "m-ahb", "s-ahb"; 947 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 948 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 949 iommus = <&apps_smmu 0x5a3 0>; 950 #address-cells = <2>; 951 #size-cells = <2>; 952 ranges; 953 status = "disabled"; 954 955 i2c0: i2c@980000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00980000 0 0x4000>; 958 clock-names = "se"; 959 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_i2c0_default>; 962 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 963 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 964 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 965 dma-names = "tx", "rx"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi0: spi@980000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x00980000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 976 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 977 power-domains = <&rpmhpd RPMHPD_CX>; 978 operating-points-v2 = <&qup_opp_table_100mhz>; 979 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 980 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c1: i2c@984000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00984000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c1_default>; 994 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 995 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 996 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 spi1: spi@984000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0 0x00984000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1008 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1009 power-domains = <&rpmhpd RPMHPD_CX>; 1010 operating-points-v2 = <&qup_opp_table_100mhz>; 1011 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1012 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c2: i2c@988000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00988000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_i2c2_default>; 1026 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1027 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 spi2: spi@988000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00988000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1040 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1041 power-domains = <&rpmhpd RPMHPD_CX>; 1042 operating-points-v2 = <&qup_opp_table_100mhz>; 1043 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1044 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 uart2: serial@98c000 { 1052 compatible = "qcom,geni-debug-uart"; 1053 reg = <0 0x0098c000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_uart3_default_state>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd RPMHPD_CX>; 1060 operating-points-v2 = <&qup_opp_table_100mhz>; 1061 status = "disabled"; 1062 }; 1063 1064 /* QUP no. 3 seems to be strictly SPI-only */ 1065 1066 spi3: spi@98c000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0 0x0098c000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table_100mhz>; 1074 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1075 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1076 dma-names = "tx", "rx"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 i2c4: i2c@990000 { 1083 compatible = "qcom,geni-i2c"; 1084 reg = <0 0x00990000 0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_i2c4_default>; 1089 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1090 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1091 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 spi4: spi@990000 { 1099 compatible = "qcom,geni-spi"; 1100 reg = <0 0x00990000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1103 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd RPMHPD_CX>; 1105 operating-points-v2 = <&qup_opp_table_100mhz>; 1106 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1107 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1108 dma-names = "tx", "rx"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c5: i2c@994000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00994000 0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c5_default>; 1121 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1122 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1123 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1124 dma-names = "tx", "rx"; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 spi5: spi@994000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00994000 0 0x4000>; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1135 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1136 power-domains = <&rpmhpd RPMHPD_CX>; 1137 operating-points-v2 = <&qup_opp_table_100mhz>; 1138 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1139 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1140 dma-names = "tx", "rx"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 i2c6: i2c@998000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x00998000 0 0x4000>; 1149 clock-names = "se"; 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c6_default>; 1153 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1154 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1155 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 spi6: spi@998000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00998000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1167 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1168 power-domains = <&rpmhpd RPMHPD_CX>; 1169 operating-points-v2 = <&qup_opp_table_100mhz>; 1170 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1171 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1172 dma-names = "tx", "rx"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 uart6: serial@998000 { 1179 compatible = "qcom,geni-uart"; 1180 reg = <0 0x00998000 0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_uart6_default>; 1185 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1186 power-domains = <&rpmhpd RPMHPD_CX>; 1187 operating-points-v2 = <&qup_opp_table_100mhz>; 1188 status = "disabled"; 1189 }; 1190 1191 i2c7: i2c@99c000 { 1192 compatible = "qcom,geni-i2c"; 1193 reg = <0 0x0099c000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c7_default>; 1198 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1199 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1200 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1201 dma-names = "tx", "rx"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 spi7: spi@99c000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x0099c000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1212 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1213 power-domains = <&rpmhpd RPMHPD_CX>; 1214 operating-points-v2 = <&qup_opp_table_100mhz>; 1215 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1216 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1217 dma-names = "tx", "rx"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 gpi_dma1: dma-controller@a00000 { 1225 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1226 reg = <0 0x00a00000 0 0x60000>; 1227 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1239 dma-channels = <12>; 1240 dma-channel-mask = <0xff>; 1241 iommus = <&apps_smmu 0x56 0x0>; 1242 #dma-cells = <3>; 1243 status = "disabled"; 1244 }; 1245 1246 qupv3_id_1: geniqup@ac0000 { 1247 compatible = "qcom,geni-se-qup"; 1248 reg = <0x0 0x00ac0000 0x0 0x6000>; 1249 clock-names = "m-ahb", "s-ahb"; 1250 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1251 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1252 iommus = <&apps_smmu 0x43 0>; 1253 #address-cells = <2>; 1254 #size-cells = <2>; 1255 ranges; 1256 status = "disabled"; 1257 1258 i2c8: i2c@a80000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0 0x00a80000 0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_i2c8_default>; 1265 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1266 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1267 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1268 dma-names = "tx", "rx"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 spi8: spi@a80000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a80000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1279 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd RPMHPD_CX>; 1281 operating-points-v2 = <&qup_opp_table_120mhz>; 1282 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1283 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1284 dma-names = "tx", "rx"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c9: i2c@a84000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0 0x00a84000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c9_default>; 1297 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 spi9: spi@a84000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0 0x00a84000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1311 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1312 power-domains = <&rpmhpd RPMHPD_CX>; 1313 operating-points-v2 = <&qup_opp_table_100mhz>; 1314 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1315 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1316 dma-names = "tx", "rx"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c10: i2c@a88000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a88000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c10_default>; 1329 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1330 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1331 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1332 dma-names = "tx", "rx"; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 spi10: spi@a88000 { 1339 compatible = "qcom,geni-spi"; 1340 reg = <0 0x00a88000 0 0x4000>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1343 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd RPMHPD_CX>; 1345 operating-points-v2 = <&qup_opp_table_100mhz>; 1346 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1347 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1348 dma-names = "tx", "rx"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 status = "disabled"; 1352 }; 1353 1354 i2c11: i2c@a8c000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a8c000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c11_default>; 1361 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1362 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1363 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1364 dma-names = "tx", "rx"; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 status = "disabled"; 1368 }; 1369 1370 spi11: spi@a8c000 { 1371 compatible = "qcom,geni-spi"; 1372 reg = <0 0x00a8c000 0 0x4000>; 1373 clock-names = "se"; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1375 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1376 power-domains = <&rpmhpd RPMHPD_CX>; 1377 operating-points-v2 = <&qup_opp_table_100mhz>; 1378 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1379 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c12: i2c@a90000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x00a90000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c12_default>; 1393 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1394 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1395 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1396 dma-names = "tx", "rx"; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 spi12: spi@a90000 { 1403 compatible = "qcom,geni-spi"; 1404 reg = <0 0x00a90000 0 0x4000>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1407 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 operating-points-v2 = <&qup_opp_table_100mhz>; 1410 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1411 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1412 dma-names = "tx", "rx"; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 i2c13: i2c@a94000 { 1419 compatible = "qcom,geni-i2c"; 1420 reg = <0 0x00a94000 0 0x4000>; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_i2c13_default>; 1425 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1427 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1428 dma-names = "tx", "rx"; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 status = "disabled"; 1432 }; 1433 1434 spi13: spi@a94000 { 1435 compatible = "qcom,geni-spi"; 1436 reg = <0 0x00a94000 0 0x4000>; 1437 clock-names = "se"; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1439 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd RPMHPD_CX>; 1441 operating-points-v2 = <&qup_opp_table_100mhz>; 1442 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1443 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1444 dma-names = "tx", "rx"; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 status = "disabled"; 1448 }; 1449 }; 1450 1451 rng: rng@10d3000 { 1452 compatible = "qcom,prng-ee"; 1453 reg = <0 0x010d3000 0 0x1000>; 1454 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1455 clock-names = "core"; 1456 }; 1457 1458 config_noc: interconnect@1500000 { 1459 compatible = "qcom,sm8350-config-noc"; 1460 reg = <0 0x01500000 0 0xa580>; 1461 #interconnect-cells = <2>; 1462 qcom,bcm-voters = <&apps_bcm_voter>; 1463 }; 1464 1465 mc_virt: interconnect@1580000 { 1466 compatible = "qcom,sm8350-mc-virt"; 1467 reg = <0 0x01580000 0 0x1000>; 1468 #interconnect-cells = <2>; 1469 qcom,bcm-voters = <&apps_bcm_voter>; 1470 }; 1471 1472 system_noc: interconnect@1680000 { 1473 compatible = "qcom,sm8350-system-noc"; 1474 reg = <0 0x01680000 0 0x1c200>; 1475 #interconnect-cells = <2>; 1476 qcom,bcm-voters = <&apps_bcm_voter>; 1477 }; 1478 1479 aggre1_noc: interconnect@16e0000 { 1480 compatible = "qcom,sm8350-aggre1-noc"; 1481 reg = <0 0x016e0000 0 0x1f180>; 1482 #interconnect-cells = <2>; 1483 qcom,bcm-voters = <&apps_bcm_voter>; 1484 }; 1485 1486 aggre2_noc: interconnect@1700000 { 1487 compatible = "qcom,sm8350-aggre2-noc"; 1488 reg = <0 0x01700000 0 0x33000>; 1489 #interconnect-cells = <2>; 1490 qcom,bcm-voters = <&apps_bcm_voter>; 1491 }; 1492 1493 mmss_noc: interconnect@1740000 { 1494 compatible = "qcom,sm8350-mmss-noc"; 1495 reg = <0 0x01740000 0 0x1f080>; 1496 #interconnect-cells = <2>; 1497 qcom,bcm-voters = <&apps_bcm_voter>; 1498 }; 1499 1500 pcie0: pci@1c00000 { 1501 compatible = "qcom,pcie-sm8350"; 1502 reg = <0 0x01c00000 0 0x3000>, 1503 <0 0x60000000 0 0xf1d>, 1504 <0 0x60000f20 0 0xa8>, 1505 <0 0x60001000 0 0x1000>, 1506 <0 0x60100000 0 0x100000>; 1507 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1508 device_type = "pci"; 1509 linux,pci-domain = <0>; 1510 bus-range = <0x00 0xff>; 1511 num-lanes = <1>; 1512 1513 #address-cells = <3>; 1514 #size-cells = <2>; 1515 1516 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1517 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1518 1519 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1527 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1528 "msi4", "msi5", "msi6", "msi7"; 1529 #interrupt-cells = <1>; 1530 interrupt-map-mask = <0 0 0 0x7>; 1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1532 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1533 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1534 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1535 1536 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1537 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1538 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1539 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1540 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1541 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1542 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1543 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1544 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1545 clock-names = "aux", 1546 "cfg", 1547 "bus_master", 1548 "bus_slave", 1549 "slave_q2a", 1550 "tbu", 1551 "ddrss_sf_tbu", 1552 "aggre1", 1553 "aggre0"; 1554 1555 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1556 <0x100 &apps_smmu 0x1c01 0x1>; 1557 1558 resets = <&gcc GCC_PCIE_0_BCR>; 1559 reset-names = "pci"; 1560 1561 power-domains = <&gcc PCIE_0_GDSC>; 1562 1563 phys = <&pcie0_phy>; 1564 phy-names = "pciephy"; 1565 1566 status = "disabled"; 1567 }; 1568 1569 pcie0_phy: phy@1c06000 { 1570 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1571 reg = <0 0x01c06000 0 0x2000>; 1572 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1573 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1574 <&gcc GCC_PCIE_0_CLKREF_EN>, 1575 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1576 <&gcc GCC_PCIE_0_PIPE_CLK>; 1577 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1578 1579 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1580 reset-names = "phy"; 1581 1582 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1583 assigned-clock-rates = <100000000>; 1584 1585 #clock-cells = <0>; 1586 clock-output-names = "pcie_0_pipe_clk"; 1587 1588 #phy-cells = <0>; 1589 1590 status = "disabled"; 1591 }; 1592 1593 pcie1: pci@1c08000 { 1594 compatible = "qcom,pcie-sm8350"; 1595 reg = <0 0x01c08000 0 0x3000>, 1596 <0 0x40000000 0 0xf1d>, 1597 <0 0x40000f20 0 0xa8>, 1598 <0 0x40001000 0 0x1000>, 1599 <0 0x40100000 0 0x100000>; 1600 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1601 device_type = "pci"; 1602 linux,pci-domain = <1>; 1603 bus-range = <0x00 0xff>; 1604 num-lanes = <2>; 1605 1606 #address-cells = <3>; 1607 #size-cells = <2>; 1608 1609 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1610 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1611 1612 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1613 interrupt-names = "msi"; 1614 #interrupt-cells = <1>; 1615 interrupt-map-mask = <0 0 0 0x7>; 1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1617 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1618 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1619 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1620 1621 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1622 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1623 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1624 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1625 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1626 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1627 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1628 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1629 clock-names = "aux", 1630 "cfg", 1631 "bus_master", 1632 "bus_slave", 1633 "slave_q2a", 1634 "tbu", 1635 "ddrss_sf_tbu", 1636 "aggre1"; 1637 1638 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1639 <0x100 &apps_smmu 0x1c81 0x1>; 1640 1641 resets = <&gcc GCC_PCIE_1_BCR>; 1642 reset-names = "pci"; 1643 1644 power-domains = <&gcc PCIE_1_GDSC>; 1645 1646 phys = <&pcie1_phy>; 1647 phy-names = "pciephy"; 1648 1649 status = "disabled"; 1650 }; 1651 1652 pcie1_phy: phy@1c0e000 { 1653 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1654 reg = <0 0x01c0e000 0 0x2000>; 1655 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1656 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1657 <&gcc GCC_PCIE_1_CLKREF_EN>, 1658 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1659 <&gcc GCC_PCIE_1_PIPE_CLK>; 1660 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1661 1662 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1663 reset-names = "phy"; 1664 1665 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1666 assigned-clock-rates = <100000000>; 1667 1668 #clock-cells = <0>; 1669 clock-output-names = "pcie_1_pipe_clk"; 1670 1671 #phy-cells = <0>; 1672 1673 status = "disabled"; 1674 }; 1675 1676 ufs_mem_hc: ufshc@1d84000 { 1677 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1678 "jedec,ufs-2.0"; 1679 reg = <0 0x01d84000 0 0x3000>; 1680 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1681 phys = <&ufs_mem_phy_lanes>; 1682 phy-names = "ufsphy"; 1683 lanes-per-direction = <2>; 1684 #reset-cells = <1>; 1685 resets = <&gcc GCC_UFS_PHY_BCR>; 1686 reset-names = "rst"; 1687 1688 power-domains = <&gcc UFS_PHY_GDSC>; 1689 1690 iommus = <&apps_smmu 0xe0 0x0>; 1691 dma-coherent; 1692 1693 clock-names = 1694 "core_clk", 1695 "bus_aggr_clk", 1696 "iface_clk", 1697 "core_clk_unipro", 1698 "ref_clk", 1699 "tx_lane0_sync_clk", 1700 "rx_lane0_sync_clk", 1701 "rx_lane1_sync_clk"; 1702 clocks = 1703 <&gcc GCC_UFS_PHY_AXI_CLK>, 1704 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1705 <&gcc GCC_UFS_PHY_AHB_CLK>, 1706 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1707 <&rpmhcc RPMH_CXO_CLK>, 1708 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1709 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1710 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1711 freq-table-hz = 1712 <75000000 300000000>, 1713 <0 0>, 1714 <0 0>, 1715 <75000000 300000000>, 1716 <0 0>, 1717 <0 0>, 1718 <0 0>, 1719 <0 0>; 1720 status = "disabled"; 1721 }; 1722 1723 ufs_mem_phy: phy@1d87000 { 1724 compatible = "qcom,sm8350-qmp-ufs-phy"; 1725 reg = <0 0x01d87000 0 0x1c4>; 1726 #address-cells = <2>; 1727 #size-cells = <2>; 1728 ranges; 1729 clock-names = "ref", 1730 "ref_aux"; 1731 clocks = <&rpmhcc RPMH_CXO_CLK>, 1732 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1733 1734 power-domains = <&gcc UFS_PHY_GDSC>; 1735 1736 resets = <&ufs_mem_hc 0>; 1737 reset-names = "ufsphy"; 1738 status = "disabled"; 1739 1740 ufs_mem_phy_lanes: phy@1d87400 { 1741 reg = <0 0x01d87400 0 0x188>, 1742 <0 0x01d87600 0 0x200>, 1743 <0 0x01d87c00 0 0x200>, 1744 <0 0x01d87800 0 0x188>, 1745 <0 0x01d87a00 0 0x200>; 1746 #clock-cells = <1>; 1747 #phy-cells = <0>; 1748 }; 1749 }; 1750 1751 cryptobam: dma-controller@1dc4000 { 1752 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1753 reg = <0 0x01dc4000 0 0x24000>; 1754 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1755 #dma-cells = <1>; 1756 qcom,ee = <0>; 1757 qcom,controlled-remotely; 1758 iommus = <&apps_smmu 0x594 0x0011>, 1759 <&apps_smmu 0x596 0x0011>; 1760 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1761 status = "fail"; 1762 }; 1763 1764 crypto: crypto@1dfa000 { 1765 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1766 reg = <0 0x01dfa000 0 0x6000>; 1767 dmas = <&cryptobam 4>, <&cryptobam 5>; 1768 dma-names = "rx", "tx"; 1769 iommus = <&apps_smmu 0x594 0x0011>, 1770 <&apps_smmu 0x596 0x0011>; 1771 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1772 interconnect-names = "memory"; 1773 /* FIXME: dependency BAM DMA is disabled */ 1774 status = "disabled"; 1775 }; 1776 1777 ipa: ipa@1e40000 { 1778 compatible = "qcom,sm8350-ipa"; 1779 1780 iommus = <&apps_smmu 0x5c0 0x0>, 1781 <&apps_smmu 0x5c2 0x0>; 1782 reg = <0 0x01e40000 0 0x8000>, 1783 <0 0x01e50000 0 0x4b20>, 1784 <0 0x01e04000 0 0x23000>; 1785 reg-names = "ipa-reg", 1786 "ipa-shared", 1787 "gsi"; 1788 1789 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1790 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1791 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1792 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1793 interrupt-names = "ipa", 1794 "gsi", 1795 "ipa-clock-query", 1796 "ipa-setup-ready"; 1797 1798 clocks = <&rpmhcc RPMH_IPA_CLK>; 1799 clock-names = "core"; 1800 1801 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1802 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1803 interconnect-names = "memory", 1804 "config"; 1805 1806 qcom,qmp = <&aoss_qmp>; 1807 1808 qcom,smem-states = <&ipa_smp2p_out 0>, 1809 <&ipa_smp2p_out 1>; 1810 qcom,smem-state-names = "ipa-clock-enabled-valid", 1811 "ipa-clock-enabled"; 1812 1813 status = "disabled"; 1814 }; 1815 1816 tcsr_mutex: hwlock@1f40000 { 1817 compatible = "qcom,tcsr-mutex"; 1818 reg = <0x0 0x01f40000 0x0 0x40000>; 1819 #hwlock-cells = <1>; 1820 }; 1821 1822 lpass_tlmm: pinctrl@33c0000 { 1823 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1824 reg = <0 0x033c0000 0 0x20000>, 1825 <0 0x03550000 0 0x10000>; 1826 1827 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1828 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1829 clock-names = "core", "audio"; 1830 1831 gpio-controller; 1832 #gpio-cells = <2>; 1833 gpio-ranges = <&lpass_tlmm 0 0 15>; 1834 }; 1835 1836 gpu: gpu@3d00000 { 1837 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1838 1839 reg = <0 0x03d00000 0 0x40000>, 1840 <0 0x03d9e000 0 0x1000>, 1841 <0 0x03d61000 0 0x800>; 1842 reg-names = "kgsl_3d0_reg_memory", 1843 "cx_mem", 1844 "cx_dbgc"; 1845 1846 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1847 1848 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1849 1850 operating-points-v2 = <&gpu_opp_table>; 1851 1852 qcom,gmu = <&gmu>; 1853 1854 status = "disabled"; 1855 1856 zap-shader { 1857 memory-region = <&pil_gpu_mem>; 1858 }; 1859 1860 /* note: downstream checks gpu binning for 670 Mhz */ 1861 gpu_opp_table: opp-table { 1862 compatible = "operating-points-v2"; 1863 1864 opp-840000000 { 1865 opp-hz = /bits/ 64 <840000000>; 1866 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1867 }; 1868 1869 opp-778000000 { 1870 opp-hz = /bits/ 64 <778000000>; 1871 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1872 }; 1873 1874 opp-738000000 { 1875 opp-hz = /bits/ 64 <738000000>; 1876 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1877 }; 1878 1879 opp-676000000 { 1880 opp-hz = /bits/ 64 <676000000>; 1881 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1882 }; 1883 1884 opp-608000000 { 1885 opp-hz = /bits/ 64 <608000000>; 1886 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1887 }; 1888 1889 opp-540000000 { 1890 opp-hz = /bits/ 64 <540000000>; 1891 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1892 }; 1893 1894 opp-491000000 { 1895 opp-hz = /bits/ 64 <491000000>; 1896 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1897 }; 1898 1899 opp-443000000 { 1900 opp-hz = /bits/ 64 <443000000>; 1901 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1902 }; 1903 1904 opp-379000000 { 1905 opp-hz = /bits/ 64 <379000000>; 1906 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1907 }; 1908 1909 opp-315000000 { 1910 opp-hz = /bits/ 64 <315000000>; 1911 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1912 }; 1913 }; 1914 }; 1915 1916 gmu: gmu@3d6a000 { 1917 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1918 1919 reg = <0 0x03d6a000 0 0x34000>, 1920 <0 0x03de0000 0 0x10000>, 1921 <0 0x0b290000 0 0x10000>; 1922 reg-names = "gmu", "rscc", "gmu_pdc"; 1923 1924 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1926 interrupt-names = "hfi", "gmu"; 1927 1928 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1929 <&gpucc GPU_CC_CXO_CLK>, 1930 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1931 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1932 <&gpucc GPU_CC_AHB_CLK>, 1933 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1934 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1935 clock-names = "gmu", 1936 "cxo", 1937 "axi", 1938 "memnoc", 1939 "ahb", 1940 "hub", 1941 "smmu_vote"; 1942 1943 power-domains = <&gpucc GPU_CX_GDSC>, 1944 <&gpucc GPU_GX_GDSC>; 1945 power-domain-names = "cx", 1946 "gx"; 1947 1948 iommus = <&adreno_smmu 5 0x400>; 1949 1950 operating-points-v2 = <&gmu_opp_table>; 1951 1952 gmu_opp_table: opp-table { 1953 compatible = "operating-points-v2"; 1954 1955 opp-200000000 { 1956 opp-hz = /bits/ 64 <200000000>; 1957 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1958 }; 1959 }; 1960 }; 1961 1962 gpucc: clock-controller@3d90000 { 1963 compatible = "qcom,sm8350-gpucc"; 1964 reg = <0 0x03d90000 0 0x9000>; 1965 clocks = <&rpmhcc RPMH_CXO_CLK>, 1966 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1967 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1968 clock-names = "bi_tcxo", 1969 "gcc_gpu_gpll0_clk_src", 1970 "gcc_gpu_gpll0_div_clk_src"; 1971 #clock-cells = <1>; 1972 #reset-cells = <1>; 1973 #power-domain-cells = <1>; 1974 }; 1975 1976 adreno_smmu: iommu@3da0000 { 1977 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1978 "qcom,smmu-500", "arm,mmu-500"; 1979 reg = <0 0x03da0000 0 0x20000>; 1980 #iommu-cells = <2>; 1981 #global-interrupts = <2>; 1982 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1994 1995 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1996 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1997 <&gpucc GPU_CC_AHB_CLK>, 1998 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1999 <&gpucc GPU_CC_CX_GMU_CLK>, 2000 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2001 <&gpucc GPU_CC_HUB_AON_CLK>; 2002 clock-names = "bus", 2003 "iface", 2004 "ahb", 2005 "hlos1_vote_gpu_smmu", 2006 "cx_gmu", 2007 "hub_cx_int", 2008 "hub_aon"; 2009 2010 power-domains = <&gpucc GPU_CX_GDSC>; 2011 dma-coherent; 2012 }; 2013 2014 lpass_ag_noc: interconnect@3c40000 { 2015 compatible = "qcom,sm8350-lpass-ag-noc"; 2016 reg = <0 0x03c40000 0 0xf080>; 2017 #interconnect-cells = <2>; 2018 qcom,bcm-voters = <&apps_bcm_voter>; 2019 }; 2020 2021 mpss: remoteproc@4080000 { 2022 compatible = "qcom,sm8350-mpss-pas"; 2023 reg = <0x0 0x04080000 0x0 0x4040>; 2024 2025 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2026 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2027 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2028 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2029 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2030 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2031 interrupt-names = "wdog", "fatal", "ready", "handover", 2032 "stop-ack", "shutdown-ack"; 2033 2034 clocks = <&rpmhcc RPMH_CXO_CLK>; 2035 clock-names = "xo"; 2036 2037 power-domains = <&rpmhpd RPMHPD_CX>, 2038 <&rpmhpd RPMHPD_MSS>; 2039 power-domain-names = "cx", "mss"; 2040 2041 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2042 2043 memory-region = <&pil_modem_mem>; 2044 2045 qcom,qmp = <&aoss_qmp>; 2046 2047 qcom,smem-states = <&smp2p_modem_out 0>; 2048 qcom,smem-state-names = "stop"; 2049 2050 status = "disabled"; 2051 2052 glink-edge { 2053 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2054 IPCC_MPROC_SIGNAL_GLINK_QMP 2055 IRQ_TYPE_EDGE_RISING>; 2056 mboxes = <&ipcc IPCC_CLIENT_MPSS 2057 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2058 label = "modem"; 2059 qcom,remote-pid = <1>; 2060 }; 2061 }; 2062 2063 slpi: remoteproc@5c00000 { 2064 compatible = "qcom,sm8350-slpi-pas"; 2065 reg = <0 0x05c00000 0 0x4000>; 2066 2067 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2068 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2069 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2070 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2071 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2072 interrupt-names = "wdog", "fatal", "ready", 2073 "handover", "stop-ack"; 2074 2075 clocks = <&rpmhcc RPMH_CXO_CLK>; 2076 clock-names = "xo"; 2077 2078 power-domains = <&rpmhpd RPMHPD_LCX>, 2079 <&rpmhpd RPMHPD_LMX>; 2080 power-domain-names = "lcx", "lmx"; 2081 2082 memory-region = <&pil_slpi_mem>; 2083 2084 qcom,qmp = <&aoss_qmp>; 2085 2086 qcom,smem-states = <&smp2p_slpi_out 0>; 2087 qcom,smem-state-names = "stop"; 2088 2089 status = "disabled"; 2090 2091 glink-edge { 2092 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2093 IPCC_MPROC_SIGNAL_GLINK_QMP 2094 IRQ_TYPE_EDGE_RISING>; 2095 mboxes = <&ipcc IPCC_CLIENT_SLPI 2096 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2097 2098 label = "slpi"; 2099 qcom,remote-pid = <3>; 2100 2101 fastrpc { 2102 compatible = "qcom,fastrpc"; 2103 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2104 label = "sdsp"; 2105 qcom,non-secure-domain; 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 2109 compute-cb@1 { 2110 compatible = "qcom,fastrpc-compute-cb"; 2111 reg = <1>; 2112 iommus = <&apps_smmu 0x0541 0x0>; 2113 }; 2114 2115 compute-cb@2 { 2116 compatible = "qcom,fastrpc-compute-cb"; 2117 reg = <2>; 2118 iommus = <&apps_smmu 0x0542 0x0>; 2119 }; 2120 2121 compute-cb@3 { 2122 compatible = "qcom,fastrpc-compute-cb"; 2123 reg = <3>; 2124 iommus = <&apps_smmu 0x0543 0x0>; 2125 /* note: shared-cb = <4> in downstream */ 2126 }; 2127 }; 2128 }; 2129 }; 2130 2131 sdhc_2: mmc@8804000 { 2132 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2133 reg = <0 0x08804000 0 0x1000>; 2134 2135 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2137 interrupt-names = "hc_irq", "pwr_irq"; 2138 2139 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2140 <&gcc GCC_SDCC2_APPS_CLK>, 2141 <&rpmhcc RPMH_CXO_CLK>; 2142 clock-names = "iface", "core", "xo"; 2143 resets = <&gcc GCC_SDCC2_BCR>; 2144 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2145 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2146 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2147 iommus = <&apps_smmu 0x4a0 0x0>; 2148 power-domains = <&rpmhpd RPMHPD_CX>; 2149 operating-points-v2 = <&sdhc2_opp_table>; 2150 bus-width = <4>; 2151 dma-coherent; 2152 2153 status = "disabled"; 2154 2155 sdhc2_opp_table: opp-table { 2156 compatible = "operating-points-v2"; 2157 2158 opp-100000000 { 2159 opp-hz = /bits/ 64 <100000000>; 2160 required-opps = <&rpmhpd_opp_low_svs>; 2161 }; 2162 2163 opp-202000000 { 2164 opp-hz = /bits/ 64 <202000000>; 2165 required-opps = <&rpmhpd_opp_svs_l1>; 2166 }; 2167 }; 2168 }; 2169 2170 usb_1_hsphy: phy@88e3000 { 2171 compatible = "qcom,sm8350-usb-hs-phy", 2172 "qcom,usb-snps-hs-7nm-phy"; 2173 reg = <0 0x088e3000 0 0x400>; 2174 status = "disabled"; 2175 #phy-cells = <0>; 2176 2177 clocks = <&rpmhcc RPMH_CXO_CLK>; 2178 clock-names = "ref"; 2179 2180 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2181 }; 2182 2183 usb_2_hsphy: phy@88e4000 { 2184 compatible = "qcom,sm8250-usb-hs-phy", 2185 "qcom,usb-snps-hs-7nm-phy"; 2186 reg = <0 0x088e4000 0 0x400>; 2187 status = "disabled"; 2188 #phy-cells = <0>; 2189 2190 clocks = <&rpmhcc RPMH_CXO_CLK>; 2191 clock-names = "ref"; 2192 2193 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2194 }; 2195 2196 usb_1_qmpphy: phy@88e8000 { 2197 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2198 reg = <0 0x088e8000 0 0x3000>; 2199 2200 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2201 <&rpmhcc RPMH_CXO_CLK>, 2202 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2203 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2204 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2205 2206 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2207 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2208 reset-names = "phy", "common"; 2209 2210 #clock-cells = <1>; 2211 #phy-cells = <1>; 2212 2213 status = "disabled"; 2214 2215 ports { 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 2219 port@0 { 2220 reg = <0>; 2221 2222 usb_1_qmpphy_out: endpoint { 2223 }; 2224 }; 2225 2226 port@1 { 2227 reg = <1>; 2228 2229 usb_1_qmpphy_usb_ss_in: endpoint { 2230 }; 2231 }; 2232 2233 port@2 { 2234 reg = <2>; 2235 2236 usb_1_qmpphy_dp_in: endpoint { 2237 }; 2238 }; 2239 }; 2240 }; 2241 2242 usb_2_qmpphy: phy-wrapper@88eb000 { 2243 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2244 reg = <0 0x088eb000 0 0x200>; 2245 status = "disabled"; 2246 #address-cells = <2>; 2247 #size-cells = <2>; 2248 ranges; 2249 2250 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2251 <&rpmhcc RPMH_CXO_CLK>, 2252 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2253 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2254 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2255 2256 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2257 <&gcc GCC_USB3_PHY_SEC_BCR>; 2258 reset-names = "phy", "common"; 2259 2260 usb_2_ssphy: phy@88ebe00 { 2261 reg = <0 0x088ebe00 0 0x200>, 2262 <0 0x088ec000 0 0x200>, 2263 <0 0x088eb200 0 0x1100>; 2264 #phy-cells = <0>; 2265 #clock-cells = <0>; 2266 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2267 clock-names = "pipe0"; 2268 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2269 }; 2270 }; 2271 2272 dc_noc: interconnect@90c0000 { 2273 compatible = "qcom,sm8350-dc-noc"; 2274 reg = <0 0x090c0000 0 0x4200>; 2275 #interconnect-cells = <2>; 2276 qcom,bcm-voters = <&apps_bcm_voter>; 2277 }; 2278 2279 gem_noc: interconnect@9100000 { 2280 compatible = "qcom,sm8350-gem-noc"; 2281 reg = <0 0x09100000 0 0xb4000>; 2282 #interconnect-cells = <2>; 2283 qcom,bcm-voters = <&apps_bcm_voter>; 2284 }; 2285 2286 system-cache-controller@9200000 { 2287 compatible = "qcom,sm8350-llcc"; 2288 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2289 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2290 <0 0x09600000 0 0x58000>; 2291 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2292 "llcc3_base", "llcc_broadcast_base"; 2293 }; 2294 2295 compute_noc: interconnect@a0c0000 { 2296 compatible = "qcom,sm8350-compute-noc"; 2297 reg = <0 0x0a0c0000 0 0xa180>; 2298 #interconnect-cells = <2>; 2299 qcom,bcm-voters = <&apps_bcm_voter>; 2300 }; 2301 2302 usb_1: usb@a6f8800 { 2303 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2304 reg = <0 0x0a6f8800 0 0x400>; 2305 status = "disabled"; 2306 #address-cells = <2>; 2307 #size-cells = <2>; 2308 ranges; 2309 2310 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2311 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2312 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2313 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2314 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2315 clock-names = "cfg_noc", 2316 "core", 2317 "iface", 2318 "sleep", 2319 "mock_utmi"; 2320 2321 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2322 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2323 assigned-clock-rates = <19200000>, <200000000>; 2324 2325 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2326 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2327 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2328 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2329 interrupt-names = "hs_phy_irq", 2330 "ss_phy_irq", 2331 "dm_hs_phy_irq", 2332 "dp_hs_phy_irq"; 2333 2334 power-domains = <&gcc USB30_PRIM_GDSC>; 2335 2336 resets = <&gcc GCC_USB30_PRIM_BCR>; 2337 2338 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2340 interconnect-names = "usb-ddr", "apps-usb"; 2341 2342 usb_1_dwc3: usb@a600000 { 2343 compatible = "snps,dwc3"; 2344 reg = <0 0x0a600000 0 0xcd00>; 2345 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2346 iommus = <&apps_smmu 0x0 0x0>; 2347 snps,dis_u2_susphy_quirk; 2348 snps,dis_enblslpm_quirk; 2349 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2350 phy-names = "usb2-phy", "usb3-phy"; 2351 2352 ports { 2353 #address-cells = <1>; 2354 #size-cells = <0>; 2355 2356 port@0 { 2357 reg = <0>; 2358 2359 usb_1_dwc3_hs: endpoint { 2360 }; 2361 }; 2362 2363 port@1 { 2364 reg = <1>; 2365 2366 usb_1_dwc3_ss: endpoint { 2367 }; 2368 }; 2369 }; 2370 }; 2371 }; 2372 2373 usb_2: usb@a8f8800 { 2374 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2375 reg = <0 0x0a8f8800 0 0x400>; 2376 status = "disabled"; 2377 #address-cells = <2>; 2378 #size-cells = <2>; 2379 ranges; 2380 2381 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2382 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2383 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2384 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2385 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2386 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2387 clock-names = "cfg_noc", 2388 "core", 2389 "iface", 2390 "sleep", 2391 "mock_utmi", 2392 "xo"; 2393 2394 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2395 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2396 assigned-clock-rates = <19200000>, <200000000>; 2397 2398 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2399 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2400 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2401 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2402 interrupt-names = "hs_phy_irq", 2403 "ss_phy_irq", 2404 "dm_hs_phy_irq", 2405 "dp_hs_phy_irq"; 2406 2407 power-domains = <&gcc USB30_SEC_GDSC>; 2408 2409 resets = <&gcc GCC_USB30_SEC_BCR>; 2410 2411 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2413 interconnect-names = "usb-ddr", "apps-usb"; 2414 2415 usb_2_dwc3: usb@a800000 { 2416 compatible = "snps,dwc3"; 2417 reg = <0 0x0a800000 0 0xcd00>; 2418 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2419 iommus = <&apps_smmu 0x20 0x0>; 2420 snps,dis_u2_susphy_quirk; 2421 snps,dis_enblslpm_quirk; 2422 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2423 phy-names = "usb2-phy", "usb3-phy"; 2424 }; 2425 }; 2426 2427 mdss: display-subsystem@ae00000 { 2428 compatible = "qcom,sm8350-mdss"; 2429 reg = <0 0x0ae00000 0 0x1000>; 2430 reg-names = "mdss"; 2431 2432 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2433 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2434 interconnect-names = "mdp0-mem", "mdp1-mem"; 2435 2436 power-domains = <&dispcc MDSS_GDSC>; 2437 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2438 2439 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2440 <&gcc GCC_DISP_HF_AXI_CLK>, 2441 <&gcc GCC_DISP_SF_AXI_CLK>, 2442 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2443 clock-names = "iface", "bus", "nrt_bus", "core"; 2444 2445 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2446 interrupt-controller; 2447 #interrupt-cells = <1>; 2448 2449 iommus = <&apps_smmu 0x820 0x402>; 2450 2451 status = "disabled"; 2452 2453 #address-cells = <2>; 2454 #size-cells = <2>; 2455 ranges; 2456 2457 dpu_opp_table: opp-table { 2458 compatible = "operating-points-v2"; 2459 2460 /* TODO: opp-200000000 should work with 2461 * &rpmhpd_opp_low_svs, but one some of 2462 * sm8350_hdk boards reboot using this 2463 * opp. 2464 */ 2465 opp-200000000 { 2466 opp-hz = /bits/ 64 <200000000>; 2467 required-opps = <&rpmhpd_opp_svs>; 2468 }; 2469 2470 opp-300000000 { 2471 opp-hz = /bits/ 64 <300000000>; 2472 required-opps = <&rpmhpd_opp_svs>; 2473 }; 2474 2475 opp-345000000 { 2476 opp-hz = /bits/ 64 <345000000>; 2477 required-opps = <&rpmhpd_opp_svs_l1>; 2478 }; 2479 2480 opp-460000000 { 2481 opp-hz = /bits/ 64 <460000000>; 2482 required-opps = <&rpmhpd_opp_nom>; 2483 }; 2484 }; 2485 2486 mdss_mdp: display-controller@ae01000 { 2487 compatible = "qcom,sm8350-dpu"; 2488 reg = <0 0x0ae01000 0 0x8f000>, 2489 <0 0x0aeb0000 0 0x2008>; 2490 reg-names = "mdp", "vbif"; 2491 2492 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2493 <&gcc GCC_DISP_SF_AXI_CLK>, 2494 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2495 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2496 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2497 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2498 clock-names = "bus", 2499 "nrt_bus", 2500 "iface", 2501 "lut", 2502 "core", 2503 "vsync"; 2504 2505 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2506 assigned-clock-rates = <19200000>; 2507 2508 operating-points-v2 = <&dpu_opp_table>; 2509 power-domains = <&rpmhpd RPMHPD_MMCX>; 2510 2511 interrupt-parent = <&mdss>; 2512 interrupts = <0>; 2513 2514 ports { 2515 #address-cells = <1>; 2516 #size-cells = <0>; 2517 2518 port@0 { 2519 reg = <0>; 2520 dpu_intf1_out: endpoint { 2521 remote-endpoint = <&mdss_dsi0_in>; 2522 }; 2523 }; 2524 2525 port@1 { 2526 reg = <1>; 2527 dpu_intf2_out: endpoint { 2528 remote-endpoint = <&mdss_dsi1_in>; 2529 }; 2530 }; 2531 2532 port@2 { 2533 reg = <2>; 2534 dpu_intf0_out: endpoint { 2535 remote-endpoint = <&mdss_dp_in>; 2536 }; 2537 }; 2538 }; 2539 }; 2540 2541 mdss_dp: displayport-controller@ae90000 { 2542 compatible = "qcom,sm8350-dp"; 2543 reg = <0 0xae90000 0 0x200>, 2544 <0 0xae90200 0 0x200>, 2545 <0 0xae90400 0 0x600>, 2546 <0 0xae91000 0 0x400>, 2547 <0 0xae91400 0 0x400>; 2548 interrupt-parent = <&mdss>; 2549 interrupts = <12>; 2550 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2551 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2552 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2553 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2554 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2555 clock-names = "core_iface", 2556 "core_aux", 2557 "ctrl_link", 2558 "ctrl_link_iface", 2559 "stream_pixel"; 2560 2561 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2562 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2563 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2564 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2565 2566 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2567 phy-names = "dp"; 2568 2569 #sound-dai-cells = <0>; 2570 2571 operating-points-v2 = <&dp_opp_table>; 2572 power-domains = <&rpmhpd RPMHPD_MMCX>; 2573 2574 status = "disabled"; 2575 2576 ports { 2577 #address-cells = <1>; 2578 #size-cells = <0>; 2579 2580 port@0 { 2581 reg = <0>; 2582 mdss_dp_in: endpoint { 2583 remote-endpoint = <&dpu_intf0_out>; 2584 }; 2585 }; 2586 }; 2587 2588 dp_opp_table: opp-table { 2589 compatible = "operating-points-v2"; 2590 2591 opp-160000000 { 2592 opp-hz = /bits/ 64 <160000000>; 2593 required-opps = <&rpmhpd_opp_low_svs>; 2594 }; 2595 2596 opp-270000000 { 2597 opp-hz = /bits/ 64 <270000000>; 2598 required-opps = <&rpmhpd_opp_svs>; 2599 }; 2600 2601 opp-540000000 { 2602 opp-hz = /bits/ 64 <540000000>; 2603 required-opps = <&rpmhpd_opp_svs_l1>; 2604 }; 2605 2606 opp-810000000 { 2607 opp-hz = /bits/ 64 <810000000>; 2608 required-opps = <&rpmhpd_opp_nom>; 2609 }; 2610 }; 2611 }; 2612 2613 mdss_dsi0: dsi@ae94000 { 2614 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2615 reg = <0 0x0ae94000 0 0x400>; 2616 reg-names = "dsi_ctrl"; 2617 2618 interrupt-parent = <&mdss>; 2619 interrupts = <4>; 2620 2621 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2622 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2623 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2624 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2625 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2626 <&gcc GCC_DISP_HF_AXI_CLK>; 2627 clock-names = "byte", 2628 "byte_intf", 2629 "pixel", 2630 "core", 2631 "iface", 2632 "bus"; 2633 2634 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2635 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2636 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2637 <&mdss_dsi0_phy 1>; 2638 2639 operating-points-v2 = <&dsi0_opp_table>; 2640 power-domains = <&rpmhpd RPMHPD_MMCX>; 2641 2642 phys = <&mdss_dsi0_phy>; 2643 2644 #address-cells = <1>; 2645 #size-cells = <0>; 2646 2647 status = "disabled"; 2648 2649 dsi0_opp_table: opp-table { 2650 compatible = "operating-points-v2"; 2651 2652 /* TODO: opp-187500000 should work with 2653 * &rpmhpd_opp_low_svs, but one some of 2654 * sm8350_hdk boards reboot using this 2655 * opp. 2656 */ 2657 opp-187500000 { 2658 opp-hz = /bits/ 64 <187500000>; 2659 required-opps = <&rpmhpd_opp_svs>; 2660 }; 2661 2662 opp-300000000 { 2663 opp-hz = /bits/ 64 <300000000>; 2664 required-opps = <&rpmhpd_opp_svs>; 2665 }; 2666 2667 opp-358000000 { 2668 opp-hz = /bits/ 64 <358000000>; 2669 required-opps = <&rpmhpd_opp_svs_l1>; 2670 }; 2671 }; 2672 2673 ports { 2674 #address-cells = <1>; 2675 #size-cells = <0>; 2676 2677 port@0 { 2678 reg = <0>; 2679 mdss_dsi0_in: endpoint { 2680 remote-endpoint = <&dpu_intf1_out>; 2681 }; 2682 }; 2683 2684 port@1 { 2685 reg = <1>; 2686 mdss_dsi0_out: endpoint { 2687 }; 2688 }; 2689 }; 2690 }; 2691 2692 mdss_dsi0_phy: phy@ae94400 { 2693 compatible = "qcom,sm8350-dsi-phy-5nm"; 2694 reg = <0 0x0ae94400 0 0x200>, 2695 <0 0x0ae94600 0 0x280>, 2696 <0 0x0ae94900 0 0x27c>; 2697 reg-names = "dsi_phy", 2698 "dsi_phy_lane", 2699 "dsi_pll"; 2700 2701 #clock-cells = <1>; 2702 #phy-cells = <0>; 2703 2704 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2705 <&rpmhcc RPMH_CXO_CLK>; 2706 clock-names = "iface", "ref"; 2707 2708 status = "disabled"; 2709 }; 2710 2711 mdss_dsi1: dsi@ae96000 { 2712 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2713 reg = <0 0x0ae96000 0 0x400>; 2714 reg-names = "dsi_ctrl"; 2715 2716 interrupt-parent = <&mdss>; 2717 interrupts = <5>; 2718 2719 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2720 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2721 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2722 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2723 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2724 <&gcc GCC_DISP_HF_AXI_CLK>; 2725 clock-names = "byte", 2726 "byte_intf", 2727 "pixel", 2728 "core", 2729 "iface", 2730 "bus"; 2731 2732 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2733 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2734 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2735 <&mdss_dsi1_phy 1>; 2736 2737 operating-points-v2 = <&dsi1_opp_table>; 2738 power-domains = <&rpmhpd RPMHPD_MMCX>; 2739 2740 phys = <&mdss_dsi1_phy>; 2741 2742 #address-cells = <1>; 2743 #size-cells = <0>; 2744 2745 status = "disabled"; 2746 2747 dsi1_opp_table: opp-table { 2748 compatible = "operating-points-v2"; 2749 2750 /* TODO: opp-187500000 should work with 2751 * &rpmhpd_opp_low_svs, but one some of 2752 * sm8350_hdk boards reboot using this 2753 * opp. 2754 */ 2755 opp-187500000 { 2756 opp-hz = /bits/ 64 <187500000>; 2757 required-opps = <&rpmhpd_opp_svs>; 2758 }; 2759 2760 opp-300000000 { 2761 opp-hz = /bits/ 64 <300000000>; 2762 required-opps = <&rpmhpd_opp_svs>; 2763 }; 2764 2765 opp-358000000 { 2766 opp-hz = /bits/ 64 <358000000>; 2767 required-opps = <&rpmhpd_opp_svs_l1>; 2768 }; 2769 }; 2770 2771 ports { 2772 #address-cells = <1>; 2773 #size-cells = <0>; 2774 2775 port@0 { 2776 reg = <0>; 2777 mdss_dsi1_in: endpoint { 2778 remote-endpoint = <&dpu_intf2_out>; 2779 }; 2780 }; 2781 2782 port@1 { 2783 reg = <1>; 2784 mdss_dsi1_out: endpoint { 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 mdss_dsi1_phy: phy@ae96400 { 2791 compatible = "qcom,sm8350-dsi-phy-5nm"; 2792 reg = <0 0x0ae96400 0 0x200>, 2793 <0 0x0ae96600 0 0x280>, 2794 <0 0x0ae96900 0 0x27c>; 2795 reg-names = "dsi_phy", 2796 "dsi_phy_lane", 2797 "dsi_pll"; 2798 2799 #clock-cells = <1>; 2800 #phy-cells = <0>; 2801 2802 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2803 <&rpmhcc RPMH_CXO_CLK>; 2804 clock-names = "iface", "ref"; 2805 2806 status = "disabled"; 2807 }; 2808 }; 2809 2810 dispcc: clock-controller@af00000 { 2811 compatible = "qcom,sm8350-dispcc"; 2812 reg = <0 0x0af00000 0 0x10000>; 2813 clocks = <&rpmhcc RPMH_CXO_CLK>, 2814 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2815 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2816 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2817 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2818 clock-names = "bi_tcxo", 2819 "dsi0_phy_pll_out_byteclk", 2820 "dsi0_phy_pll_out_dsiclk", 2821 "dsi1_phy_pll_out_byteclk", 2822 "dsi1_phy_pll_out_dsiclk", 2823 "dp_phy_pll_link_clk", 2824 "dp_phy_pll_vco_div_clk"; 2825 #clock-cells = <1>; 2826 #reset-cells = <1>; 2827 #power-domain-cells = <1>; 2828 2829 power-domains = <&rpmhpd RPMHPD_MMCX>; 2830 }; 2831 2832 pdc: interrupt-controller@b220000 { 2833 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2834 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2835 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2836 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2837 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2838 <156 716 12>; 2839 #interrupt-cells = <2>; 2840 interrupt-parent = <&intc>; 2841 interrupt-controller; 2842 }; 2843 2844 tsens0: thermal-sensor@c263000 { 2845 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2846 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2847 <0 0x0c222000 0 0x8>; /* SROT */ 2848 #qcom,sensors = <15>; 2849 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2850 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2851 interrupt-names = "uplow", "critical"; 2852 #thermal-sensor-cells = <1>; 2853 }; 2854 2855 tsens1: thermal-sensor@c265000 { 2856 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2857 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2858 <0 0x0c223000 0 0x8>; /* SROT */ 2859 #qcom,sensors = <14>; 2860 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2861 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2862 interrupt-names = "uplow", "critical"; 2863 #thermal-sensor-cells = <1>; 2864 }; 2865 2866 aoss_qmp: power-management@c300000 { 2867 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2868 reg = <0 0x0c300000 0 0x400>; 2869 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2870 IRQ_TYPE_EDGE_RISING>; 2871 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2872 2873 #clock-cells = <0>; 2874 }; 2875 2876 sram@c3f0000 { 2877 compatible = "qcom,rpmh-stats"; 2878 reg = <0 0x0c3f0000 0 0x400>; 2879 }; 2880 2881 spmi_bus: spmi@c440000 { 2882 compatible = "qcom,spmi-pmic-arb"; 2883 reg = <0x0 0x0c440000 0x0 0x1100>, 2884 <0x0 0x0c600000 0x0 0x2000000>, 2885 <0x0 0x0e600000 0x0 0x100000>, 2886 <0x0 0x0e700000 0x0 0xa0000>, 2887 <0x0 0x0c40a000 0x0 0x26000>; 2888 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2889 interrupt-names = "periph_irq"; 2890 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2891 qcom,ee = <0>; 2892 qcom,channel = <0>; 2893 #address-cells = <2>; 2894 #size-cells = <0>; 2895 interrupt-controller; 2896 #interrupt-cells = <4>; 2897 }; 2898 2899 tlmm: pinctrl@f100000 { 2900 compatible = "qcom,sm8350-tlmm"; 2901 reg = <0 0x0f100000 0 0x300000>; 2902 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2903 gpio-controller; 2904 #gpio-cells = <2>; 2905 interrupt-controller; 2906 #interrupt-cells = <2>; 2907 gpio-ranges = <&tlmm 0 0 204>; 2908 wakeup-parent = <&pdc>; 2909 2910 sdc2_default_state: sdc2-default-state { 2911 clk-pins { 2912 pins = "sdc2_clk"; 2913 drive-strength = <16>; 2914 bias-disable; 2915 }; 2916 2917 cmd-pins { 2918 pins = "sdc2_cmd"; 2919 drive-strength = <16>; 2920 bias-pull-up; 2921 }; 2922 2923 data-pins { 2924 pins = "sdc2_data"; 2925 drive-strength = <16>; 2926 bias-pull-up; 2927 }; 2928 }; 2929 2930 sdc2_sleep_state: sdc2-sleep-state { 2931 clk-pins { 2932 pins = "sdc2_clk"; 2933 drive-strength = <2>; 2934 bias-disable; 2935 }; 2936 2937 cmd-pins { 2938 pins = "sdc2_cmd"; 2939 drive-strength = <2>; 2940 bias-pull-up; 2941 }; 2942 2943 data-pins { 2944 pins = "sdc2_data"; 2945 drive-strength = <2>; 2946 bias-pull-up; 2947 }; 2948 }; 2949 2950 qup_uart3_default_state: qup-uart3-default-state { 2951 rx-pins { 2952 pins = "gpio18"; 2953 function = "qup3"; 2954 }; 2955 tx-pins { 2956 pins = "gpio19"; 2957 function = "qup3"; 2958 }; 2959 }; 2960 2961 qup_uart6_default: qup-uart6-default-state { 2962 pins = "gpio30", "gpio31"; 2963 function = "qup6"; 2964 drive-strength = <2>; 2965 bias-disable; 2966 }; 2967 2968 qup_uart18_default: qup-uart18-default-state { 2969 pins = "gpio68", "gpio69"; 2970 function = "qup18"; 2971 drive-strength = <2>; 2972 bias-disable; 2973 }; 2974 2975 qup_i2c0_default: qup-i2c0-default-state { 2976 pins = "gpio4", "gpio5"; 2977 function = "qup0"; 2978 drive-strength = <2>; 2979 bias-pull-up; 2980 }; 2981 2982 qup_i2c1_default: qup-i2c1-default-state { 2983 pins = "gpio8", "gpio9"; 2984 function = "qup1"; 2985 drive-strength = <2>; 2986 bias-pull-up; 2987 }; 2988 2989 qup_i2c2_default: qup-i2c2-default-state { 2990 pins = "gpio12", "gpio13"; 2991 function = "qup2"; 2992 drive-strength = <2>; 2993 bias-pull-up; 2994 }; 2995 2996 qup_i2c4_default: qup-i2c4-default-state { 2997 pins = "gpio20", "gpio21"; 2998 function = "qup4"; 2999 drive-strength = <2>; 3000 bias-pull-up; 3001 }; 3002 3003 qup_i2c5_default: qup-i2c5-default-state { 3004 pins = "gpio24", "gpio25"; 3005 function = "qup5"; 3006 drive-strength = <2>; 3007 bias-pull-up; 3008 }; 3009 3010 qup_i2c6_default: qup-i2c6-default-state { 3011 pins = "gpio28", "gpio29"; 3012 function = "qup6"; 3013 drive-strength = <2>; 3014 bias-pull-up; 3015 }; 3016 3017 qup_i2c7_default: qup-i2c7-default-state { 3018 pins = "gpio32", "gpio33"; 3019 function = "qup7"; 3020 drive-strength = <2>; 3021 bias-disable; 3022 }; 3023 3024 qup_i2c8_default: qup-i2c8-default-state { 3025 pins = "gpio36", "gpio37"; 3026 function = "qup8"; 3027 drive-strength = <2>; 3028 bias-pull-up; 3029 }; 3030 3031 qup_i2c9_default: qup-i2c9-default-state { 3032 pins = "gpio40", "gpio41"; 3033 function = "qup9"; 3034 drive-strength = <2>; 3035 bias-pull-up; 3036 }; 3037 3038 qup_i2c10_default: qup-i2c10-default-state { 3039 pins = "gpio44", "gpio45"; 3040 function = "qup10"; 3041 drive-strength = <2>; 3042 bias-pull-up; 3043 }; 3044 3045 qup_i2c11_default: qup-i2c11-default-state { 3046 pins = "gpio48", "gpio49"; 3047 function = "qup11"; 3048 drive-strength = <2>; 3049 bias-pull-up; 3050 }; 3051 3052 qup_i2c12_default: qup-i2c12-default-state { 3053 pins = "gpio52", "gpio53"; 3054 function = "qup12"; 3055 drive-strength = <2>; 3056 bias-pull-up; 3057 }; 3058 3059 qup_i2c13_default: qup-i2c13-default-state { 3060 pins = "gpio0", "gpio1"; 3061 function = "qup13"; 3062 drive-strength = <2>; 3063 bias-pull-up; 3064 }; 3065 3066 qup_i2c14_default: qup-i2c14-default-state { 3067 pins = "gpio56", "gpio57"; 3068 function = "qup14"; 3069 drive-strength = <2>; 3070 bias-disable; 3071 }; 3072 3073 qup_i2c15_default: qup-i2c15-default-state { 3074 pins = "gpio60", "gpio61"; 3075 function = "qup15"; 3076 drive-strength = <2>; 3077 bias-disable; 3078 }; 3079 3080 qup_i2c16_default: qup-i2c16-default-state { 3081 pins = "gpio64", "gpio65"; 3082 function = "qup16"; 3083 drive-strength = <2>; 3084 bias-disable; 3085 }; 3086 3087 qup_i2c17_default: qup-i2c17-default-state { 3088 pins = "gpio72", "gpio73"; 3089 function = "qup17"; 3090 drive-strength = <2>; 3091 bias-disable; 3092 }; 3093 3094 qup_i2c19_default: qup-i2c19-default-state { 3095 pins = "gpio76", "gpio77"; 3096 function = "qup19"; 3097 drive-strength = <2>; 3098 bias-disable; 3099 }; 3100 }; 3101 3102 apps_smmu: iommu@15000000 { 3103 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3104 reg = <0 0x15000000 0 0x100000>; 3105 #iommu-cells = <2>; 3106 #global-interrupts = <2>; 3107 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3205 }; 3206 3207 adsp: remoteproc@17300000 { 3208 compatible = "qcom,sm8350-adsp-pas"; 3209 reg = <0 0x17300000 0 0x100>; 3210 3211 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3212 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3213 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3214 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3215 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3216 interrupt-names = "wdog", "fatal", "ready", 3217 "handover", "stop-ack"; 3218 3219 clocks = <&rpmhcc RPMH_CXO_CLK>; 3220 clock-names = "xo"; 3221 3222 power-domains = <&rpmhpd RPMHPD_LCX>, 3223 <&rpmhpd RPMHPD_LMX>; 3224 power-domain-names = "lcx", "lmx"; 3225 3226 memory-region = <&pil_adsp_mem>; 3227 3228 qcom,qmp = <&aoss_qmp>; 3229 3230 qcom,smem-states = <&smp2p_adsp_out 0>; 3231 qcom,smem-state-names = "stop"; 3232 3233 status = "disabled"; 3234 3235 glink-edge { 3236 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3237 IPCC_MPROC_SIGNAL_GLINK_QMP 3238 IRQ_TYPE_EDGE_RISING>; 3239 mboxes = <&ipcc IPCC_CLIENT_LPASS 3240 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3241 3242 label = "lpass"; 3243 qcom,remote-pid = <2>; 3244 3245 apr { 3246 compatible = "qcom,apr-v2"; 3247 qcom,glink-channels = "apr_audio_svc"; 3248 qcom,domain = <APR_DOMAIN_ADSP>; 3249 #address-cells = <1>; 3250 #size-cells = <0>; 3251 3252 service@3 { 3253 reg = <APR_SVC_ADSP_CORE>; 3254 compatible = "qcom,q6core"; 3255 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3256 }; 3257 3258 q6afe: service@4 { 3259 compatible = "qcom,q6afe"; 3260 reg = <APR_SVC_AFE>; 3261 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3262 3263 q6afedai: dais { 3264 compatible = "qcom,q6afe-dais"; 3265 #address-cells = <1>; 3266 #size-cells = <0>; 3267 #sound-dai-cells = <1>; 3268 }; 3269 3270 q6afecc: clock-controller { 3271 compatible = "qcom,q6afe-clocks"; 3272 #clock-cells = <2>; 3273 }; 3274 }; 3275 3276 q6asm: service@7 { 3277 compatible = "qcom,q6asm"; 3278 reg = <APR_SVC_ASM>; 3279 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3280 3281 q6asmdai: dais { 3282 compatible = "qcom,q6asm-dais"; 3283 #address-cells = <1>; 3284 #size-cells = <0>; 3285 #sound-dai-cells = <1>; 3286 iommus = <&apps_smmu 0x1801 0x0>; 3287 3288 dai@0 { 3289 reg = <0>; 3290 }; 3291 3292 dai@1 { 3293 reg = <1>; 3294 }; 3295 3296 dai@2 { 3297 reg = <2>; 3298 }; 3299 }; 3300 }; 3301 3302 q6adm: service@8 { 3303 compatible = "qcom,q6adm"; 3304 reg = <APR_SVC_ADM>; 3305 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3306 3307 q6routing: routing { 3308 compatible = "qcom,q6adm-routing"; 3309 #sound-dai-cells = <0>; 3310 }; 3311 }; 3312 }; 3313 3314 fastrpc { 3315 compatible = "qcom,fastrpc"; 3316 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3317 label = "adsp"; 3318 qcom,non-secure-domain; 3319 #address-cells = <1>; 3320 #size-cells = <0>; 3321 3322 compute-cb@3 { 3323 compatible = "qcom,fastrpc-compute-cb"; 3324 reg = <3>; 3325 iommus = <&apps_smmu 0x1803 0x0>; 3326 }; 3327 3328 compute-cb@4 { 3329 compatible = "qcom,fastrpc-compute-cb"; 3330 reg = <4>; 3331 iommus = <&apps_smmu 0x1804 0x0>; 3332 }; 3333 3334 compute-cb@5 { 3335 compatible = "qcom,fastrpc-compute-cb"; 3336 reg = <5>; 3337 iommus = <&apps_smmu 0x1805 0x0>; 3338 }; 3339 }; 3340 }; 3341 }; 3342 3343 intc: interrupt-controller@17a00000 { 3344 compatible = "arm,gic-v3"; 3345 #interrupt-cells = <3>; 3346 interrupt-controller; 3347 #redistributor-regions = <1>; 3348 redistributor-stride = <0 0x20000>; 3349 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3350 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3351 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3352 }; 3353 3354 timer@17c20000 { 3355 compatible = "arm,armv7-timer-mem"; 3356 #address-cells = <1>; 3357 #size-cells = <1>; 3358 ranges = <0 0 0 0x20000000>; 3359 reg = <0x0 0x17c20000 0x0 0x1000>; 3360 clock-frequency = <19200000>; 3361 3362 frame@17c21000 { 3363 frame-number = <0>; 3364 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3366 reg = <0x17c21000 0x1000>, 3367 <0x17c22000 0x1000>; 3368 }; 3369 3370 frame@17c23000 { 3371 frame-number = <1>; 3372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3373 reg = <0x17c23000 0x1000>; 3374 status = "disabled"; 3375 }; 3376 3377 frame@17c25000 { 3378 frame-number = <2>; 3379 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3380 reg = <0x17c25000 0x1000>; 3381 status = "disabled"; 3382 }; 3383 3384 frame@17c27000 { 3385 frame-number = <3>; 3386 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3387 reg = <0x17c27000 0x1000>; 3388 status = "disabled"; 3389 }; 3390 3391 frame@17c29000 { 3392 frame-number = <4>; 3393 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3394 reg = <0x17c29000 0x1000>; 3395 status = "disabled"; 3396 }; 3397 3398 frame@17c2b000 { 3399 frame-number = <5>; 3400 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3401 reg = <0x17c2b000 0x1000>; 3402 status = "disabled"; 3403 }; 3404 3405 frame@17c2d000 { 3406 frame-number = <6>; 3407 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3408 reg = <0x17c2d000 0x1000>; 3409 status = "disabled"; 3410 }; 3411 }; 3412 3413 apps_rsc: rsc@18200000 { 3414 label = "apps_rsc"; 3415 compatible = "qcom,rpmh-rsc"; 3416 reg = <0x0 0x18200000 0x0 0x10000>, 3417 <0x0 0x18210000 0x0 0x10000>, 3418 <0x0 0x18220000 0x0 0x10000>; 3419 reg-names = "drv-0", "drv-1", "drv-2"; 3420 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3423 qcom,tcs-offset = <0xd00>; 3424 qcom,drv-id = <2>; 3425 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3426 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3427 power-domains = <&CLUSTER_PD>; 3428 3429 rpmhcc: clock-controller { 3430 compatible = "qcom,sm8350-rpmh-clk"; 3431 #clock-cells = <1>; 3432 clock-names = "xo"; 3433 clocks = <&xo_board>; 3434 }; 3435 3436 rpmhpd: power-controller { 3437 compatible = "qcom,sm8350-rpmhpd"; 3438 #power-domain-cells = <1>; 3439 operating-points-v2 = <&rpmhpd_opp_table>; 3440 3441 rpmhpd_opp_table: opp-table { 3442 compatible = "operating-points-v2"; 3443 3444 rpmhpd_opp_ret: opp1 { 3445 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3446 }; 3447 3448 rpmhpd_opp_min_svs: opp2 { 3449 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3450 }; 3451 3452 rpmhpd_opp_low_svs: opp3 { 3453 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3454 }; 3455 3456 rpmhpd_opp_svs: opp4 { 3457 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3458 }; 3459 3460 rpmhpd_opp_svs_l1: opp5 { 3461 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3462 }; 3463 3464 rpmhpd_opp_nom: opp6 { 3465 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3466 }; 3467 3468 rpmhpd_opp_nom_l1: opp7 { 3469 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3470 }; 3471 3472 rpmhpd_opp_nom_l2: opp8 { 3473 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3474 }; 3475 3476 rpmhpd_opp_turbo: opp9 { 3477 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3478 }; 3479 3480 rpmhpd_opp_turbo_l1: opp10 { 3481 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3482 }; 3483 }; 3484 }; 3485 3486 apps_bcm_voter: bcm-voter { 3487 compatible = "qcom,bcm-voter"; 3488 }; 3489 }; 3490 3491 cpufreq_hw: cpufreq@18591000 { 3492 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3493 reg = <0 0x18591000 0 0x1000>, 3494 <0 0x18592000 0 0x1000>, 3495 <0 0x18593000 0 0x1000>; 3496 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3497 3498 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3501 interrupt-names = "dcvsh-irq-0", 3502 "dcvsh-irq-1", 3503 "dcvsh-irq-2"; 3504 3505 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3506 clock-names = "xo", "alternate"; 3507 3508 #freq-domain-cells = <1>; 3509 #clock-cells = <1>; 3510 }; 3511 3512 cdsp: remoteproc@98900000 { 3513 compatible = "qcom,sm8350-cdsp-pas"; 3514 reg = <0 0x98900000 0 0x1400000>; 3515 3516 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3517 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3518 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3519 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3520 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3521 interrupt-names = "wdog", "fatal", "ready", 3522 "handover", "stop-ack"; 3523 3524 clocks = <&rpmhcc RPMH_CXO_CLK>; 3525 clock-names = "xo"; 3526 3527 power-domains = <&rpmhpd RPMHPD_CX>, 3528 <&rpmhpd RPMHPD_MXC>; 3529 power-domain-names = "cx", "mxc"; 3530 3531 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3532 3533 memory-region = <&pil_cdsp_mem>; 3534 3535 qcom,qmp = <&aoss_qmp>; 3536 3537 qcom,smem-states = <&smp2p_cdsp_out 0>; 3538 qcom,smem-state-names = "stop"; 3539 3540 status = "disabled"; 3541 3542 glink-edge { 3543 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3544 IPCC_MPROC_SIGNAL_GLINK_QMP 3545 IRQ_TYPE_EDGE_RISING>; 3546 mboxes = <&ipcc IPCC_CLIENT_CDSP 3547 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3548 3549 label = "cdsp"; 3550 qcom,remote-pid = <5>; 3551 3552 fastrpc { 3553 compatible = "qcom,fastrpc"; 3554 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3555 label = "cdsp"; 3556 qcom,non-secure-domain; 3557 #address-cells = <1>; 3558 #size-cells = <0>; 3559 3560 compute-cb@1 { 3561 compatible = "qcom,fastrpc-compute-cb"; 3562 reg = <1>; 3563 iommus = <&apps_smmu 0x2161 0x0400>, 3564 <&apps_smmu 0x1181 0x0420>; 3565 }; 3566 3567 compute-cb@2 { 3568 compatible = "qcom,fastrpc-compute-cb"; 3569 reg = <2>; 3570 iommus = <&apps_smmu 0x2162 0x0400>, 3571 <&apps_smmu 0x1182 0x0420>; 3572 }; 3573 3574 compute-cb@3 { 3575 compatible = "qcom,fastrpc-compute-cb"; 3576 reg = <3>; 3577 iommus = <&apps_smmu 0x2163 0x0400>, 3578 <&apps_smmu 0x1183 0x0420>; 3579 }; 3580 3581 compute-cb@4 { 3582 compatible = "qcom,fastrpc-compute-cb"; 3583 reg = <4>; 3584 iommus = <&apps_smmu 0x2164 0x0400>, 3585 <&apps_smmu 0x1184 0x0420>; 3586 }; 3587 3588 compute-cb@5 { 3589 compatible = "qcom,fastrpc-compute-cb"; 3590 reg = <5>; 3591 iommus = <&apps_smmu 0x2165 0x0400>, 3592 <&apps_smmu 0x1185 0x0420>; 3593 }; 3594 3595 compute-cb@6 { 3596 compatible = "qcom,fastrpc-compute-cb"; 3597 reg = <6>; 3598 iommus = <&apps_smmu 0x2166 0x0400>, 3599 <&apps_smmu 0x1186 0x0420>; 3600 }; 3601 3602 compute-cb@7 { 3603 compatible = "qcom,fastrpc-compute-cb"; 3604 reg = <7>; 3605 iommus = <&apps_smmu 0x2167 0x0400>, 3606 <&apps_smmu 0x1187 0x0420>; 3607 }; 3608 3609 compute-cb@8 { 3610 compatible = "qcom,fastrpc-compute-cb"; 3611 reg = <8>; 3612 iommus = <&apps_smmu 0x2168 0x0400>, 3613 <&apps_smmu 0x1188 0x0420>; 3614 }; 3615 3616 /* note: secure cb9 in downstream */ 3617 }; 3618 }; 3619 }; 3620 }; 3621 3622 thermal_zones: thermal-zones { 3623 cpu0-thermal { 3624 polling-delay-passive = <250>; 3625 polling-delay = <1000>; 3626 3627 thermal-sensors = <&tsens0 1>; 3628 3629 trips { 3630 cpu0_alert0: trip-point0 { 3631 temperature = <90000>; 3632 hysteresis = <2000>; 3633 type = "passive"; 3634 }; 3635 3636 cpu0_alert1: trip-point1 { 3637 temperature = <95000>; 3638 hysteresis = <2000>; 3639 type = "passive"; 3640 }; 3641 3642 cpu0_crit: cpu-crit { 3643 temperature = <110000>; 3644 hysteresis = <1000>; 3645 type = "critical"; 3646 }; 3647 }; 3648 3649 cooling-maps { 3650 map0 { 3651 trip = <&cpu0_alert0>; 3652 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3653 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3654 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3655 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3656 }; 3657 map1 { 3658 trip = <&cpu0_alert1>; 3659 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3660 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3661 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3662 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3663 }; 3664 }; 3665 }; 3666 3667 cpu1-thermal { 3668 polling-delay-passive = <250>; 3669 polling-delay = <1000>; 3670 3671 thermal-sensors = <&tsens0 2>; 3672 3673 trips { 3674 cpu1_alert0: trip-point0 { 3675 temperature = <90000>; 3676 hysteresis = <2000>; 3677 type = "passive"; 3678 }; 3679 3680 cpu1_alert1: trip-point1 { 3681 temperature = <95000>; 3682 hysteresis = <2000>; 3683 type = "passive"; 3684 }; 3685 3686 cpu1_crit: cpu-crit { 3687 temperature = <110000>; 3688 hysteresis = <1000>; 3689 type = "critical"; 3690 }; 3691 }; 3692 3693 cooling-maps { 3694 map0 { 3695 trip = <&cpu1_alert0>; 3696 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3700 }; 3701 map1 { 3702 trip = <&cpu1_alert1>; 3703 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3705 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3706 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3707 }; 3708 }; 3709 }; 3710 3711 cpu2-thermal { 3712 polling-delay-passive = <250>; 3713 polling-delay = <1000>; 3714 3715 thermal-sensors = <&tsens0 3>; 3716 3717 trips { 3718 cpu2_alert0: trip-point0 { 3719 temperature = <90000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 3724 cpu2_alert1: trip-point1 { 3725 temperature = <95000>; 3726 hysteresis = <2000>; 3727 type = "passive"; 3728 }; 3729 3730 cpu2_crit: cpu-crit { 3731 temperature = <110000>; 3732 hysteresis = <1000>; 3733 type = "critical"; 3734 }; 3735 }; 3736 3737 cooling-maps { 3738 map0 { 3739 trip = <&cpu2_alert0>; 3740 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3743 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3744 }; 3745 map1 { 3746 trip = <&cpu2_alert1>; 3747 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3750 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3751 }; 3752 }; 3753 }; 3754 3755 cpu3-thermal { 3756 polling-delay-passive = <250>; 3757 polling-delay = <1000>; 3758 3759 thermal-sensors = <&tsens0 4>; 3760 3761 trips { 3762 cpu3_alert0: trip-point0 { 3763 temperature = <90000>; 3764 hysteresis = <2000>; 3765 type = "passive"; 3766 }; 3767 3768 cpu3_alert1: trip-point1 { 3769 temperature = <95000>; 3770 hysteresis = <2000>; 3771 type = "passive"; 3772 }; 3773 3774 cpu3_crit: cpu-crit { 3775 temperature = <110000>; 3776 hysteresis = <1000>; 3777 type = "critical"; 3778 }; 3779 }; 3780 3781 cooling-maps { 3782 map0 { 3783 trip = <&cpu3_alert0>; 3784 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3788 }; 3789 map1 { 3790 trip = <&cpu3_alert1>; 3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3795 }; 3796 }; 3797 }; 3798 3799 cpu4-top-thermal { 3800 polling-delay-passive = <250>; 3801 polling-delay = <1000>; 3802 3803 thermal-sensors = <&tsens0 7>; 3804 3805 trips { 3806 cpu4_top_alert0: trip-point0 { 3807 temperature = <90000>; 3808 hysteresis = <2000>; 3809 type = "passive"; 3810 }; 3811 3812 cpu4_top_alert1: trip-point1 { 3813 temperature = <95000>; 3814 hysteresis = <2000>; 3815 type = "passive"; 3816 }; 3817 3818 cpu4_top_crit: cpu-crit { 3819 temperature = <110000>; 3820 hysteresis = <1000>; 3821 type = "critical"; 3822 }; 3823 }; 3824 3825 cooling-maps { 3826 map0 { 3827 trip = <&cpu4_top_alert0>; 3828 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3831 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3832 }; 3833 map1 { 3834 trip = <&cpu4_top_alert1>; 3835 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3839 }; 3840 }; 3841 }; 3842 3843 cpu5-top-thermal { 3844 polling-delay-passive = <250>; 3845 polling-delay = <1000>; 3846 3847 thermal-sensors = <&tsens0 8>; 3848 3849 trips { 3850 cpu5_top_alert0: trip-point0 { 3851 temperature = <90000>; 3852 hysteresis = <2000>; 3853 type = "passive"; 3854 }; 3855 3856 cpu5_top_alert1: trip-point1 { 3857 temperature = <95000>; 3858 hysteresis = <2000>; 3859 type = "passive"; 3860 }; 3861 3862 cpu5_top_crit: cpu-crit { 3863 temperature = <110000>; 3864 hysteresis = <1000>; 3865 type = "critical"; 3866 }; 3867 }; 3868 3869 cooling-maps { 3870 map0 { 3871 trip = <&cpu5_top_alert0>; 3872 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3876 }; 3877 map1 { 3878 trip = <&cpu5_top_alert1>; 3879 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3883 }; 3884 }; 3885 }; 3886 3887 cpu6-top-thermal { 3888 polling-delay-passive = <250>; 3889 polling-delay = <1000>; 3890 3891 thermal-sensors = <&tsens0 9>; 3892 3893 trips { 3894 cpu6_top_alert0: trip-point0 { 3895 temperature = <90000>; 3896 hysteresis = <2000>; 3897 type = "passive"; 3898 }; 3899 3900 cpu6_top_alert1: trip-point1 { 3901 temperature = <95000>; 3902 hysteresis = <2000>; 3903 type = "passive"; 3904 }; 3905 3906 cpu6_top_crit: cpu-crit { 3907 temperature = <110000>; 3908 hysteresis = <1000>; 3909 type = "critical"; 3910 }; 3911 }; 3912 3913 cooling-maps { 3914 map0 { 3915 trip = <&cpu6_top_alert0>; 3916 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3920 }; 3921 map1 { 3922 trip = <&cpu6_top_alert1>; 3923 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3926 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3927 }; 3928 }; 3929 }; 3930 3931 cpu7-top-thermal { 3932 polling-delay-passive = <250>; 3933 polling-delay = <1000>; 3934 3935 thermal-sensors = <&tsens0 10>; 3936 3937 trips { 3938 cpu7_top_alert0: trip-point0 { 3939 temperature = <90000>; 3940 hysteresis = <2000>; 3941 type = "passive"; 3942 }; 3943 3944 cpu7_top_alert1: trip-point1 { 3945 temperature = <95000>; 3946 hysteresis = <2000>; 3947 type = "passive"; 3948 }; 3949 3950 cpu7_top_crit: cpu-crit { 3951 temperature = <110000>; 3952 hysteresis = <1000>; 3953 type = "critical"; 3954 }; 3955 }; 3956 3957 cooling-maps { 3958 map0 { 3959 trip = <&cpu7_top_alert0>; 3960 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3964 }; 3965 map1 { 3966 trip = <&cpu7_top_alert1>; 3967 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3971 }; 3972 }; 3973 }; 3974 3975 cpu4-bottom-thermal { 3976 polling-delay-passive = <250>; 3977 polling-delay = <1000>; 3978 3979 thermal-sensors = <&tsens0 11>; 3980 3981 trips { 3982 cpu4_bottom_alert0: trip-point0 { 3983 temperature = <90000>; 3984 hysteresis = <2000>; 3985 type = "passive"; 3986 }; 3987 3988 cpu4_bottom_alert1: trip-point1 { 3989 temperature = <95000>; 3990 hysteresis = <2000>; 3991 type = "passive"; 3992 }; 3993 3994 cpu4_bottom_crit: cpu-crit { 3995 temperature = <110000>; 3996 hysteresis = <1000>; 3997 type = "critical"; 3998 }; 3999 }; 4000 4001 cooling-maps { 4002 map0 { 4003 trip = <&cpu4_bottom_alert0>; 4004 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4005 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4008 }; 4009 map1 { 4010 trip = <&cpu4_bottom_alert1>; 4011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4015 }; 4016 }; 4017 }; 4018 4019 cpu5-bottom-thermal { 4020 polling-delay-passive = <250>; 4021 polling-delay = <1000>; 4022 4023 thermal-sensors = <&tsens0 12>; 4024 4025 trips { 4026 cpu5_bottom_alert0: trip-point0 { 4027 temperature = <90000>; 4028 hysteresis = <2000>; 4029 type = "passive"; 4030 }; 4031 4032 cpu5_bottom_alert1: trip-point1 { 4033 temperature = <95000>; 4034 hysteresis = <2000>; 4035 type = "passive"; 4036 }; 4037 4038 cpu5_bottom_crit: cpu-crit { 4039 temperature = <110000>; 4040 hysteresis = <1000>; 4041 type = "critical"; 4042 }; 4043 }; 4044 4045 cooling-maps { 4046 map0 { 4047 trip = <&cpu5_bottom_alert0>; 4048 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4049 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4052 }; 4053 map1 { 4054 trip = <&cpu5_bottom_alert1>; 4055 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4058 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4059 }; 4060 }; 4061 }; 4062 4063 cpu6-bottom-thermal { 4064 polling-delay-passive = <250>; 4065 polling-delay = <1000>; 4066 4067 thermal-sensors = <&tsens0 13>; 4068 4069 trips { 4070 cpu6_bottom_alert0: trip-point0 { 4071 temperature = <90000>; 4072 hysteresis = <2000>; 4073 type = "passive"; 4074 }; 4075 4076 cpu6_bottom_alert1: trip-point1 { 4077 temperature = <95000>; 4078 hysteresis = <2000>; 4079 type = "passive"; 4080 }; 4081 4082 cpu6_bottom_crit: cpu-crit { 4083 temperature = <110000>; 4084 hysteresis = <1000>; 4085 type = "critical"; 4086 }; 4087 }; 4088 4089 cooling-maps { 4090 map0 { 4091 trip = <&cpu6_bottom_alert0>; 4092 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4093 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4096 }; 4097 map1 { 4098 trip = <&cpu6_bottom_alert1>; 4099 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4100 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4102 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4103 }; 4104 }; 4105 }; 4106 4107 cpu7-bottom-thermal { 4108 polling-delay-passive = <250>; 4109 polling-delay = <1000>; 4110 4111 thermal-sensors = <&tsens0 14>; 4112 4113 trips { 4114 cpu7_bottom_alert0: trip-point0 { 4115 temperature = <90000>; 4116 hysteresis = <2000>; 4117 type = "passive"; 4118 }; 4119 4120 cpu7_bottom_alert1: trip-point1 { 4121 temperature = <95000>; 4122 hysteresis = <2000>; 4123 type = "passive"; 4124 }; 4125 4126 cpu7_bottom_crit: cpu-crit { 4127 temperature = <110000>; 4128 hysteresis = <1000>; 4129 type = "critical"; 4130 }; 4131 }; 4132 4133 cooling-maps { 4134 map0 { 4135 trip = <&cpu7_bottom_alert0>; 4136 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4140 }; 4141 map1 { 4142 trip = <&cpu7_bottom_alert1>; 4143 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4146 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4147 }; 4148 }; 4149 }; 4150 4151 aoss0-thermal { 4152 polling-delay-passive = <250>; 4153 polling-delay = <1000>; 4154 4155 thermal-sensors = <&tsens0 0>; 4156 4157 trips { 4158 aoss0_alert0: trip-point0 { 4159 temperature = <90000>; 4160 hysteresis = <2000>; 4161 type = "hot"; 4162 }; 4163 }; 4164 }; 4165 4166 cluster0-thermal { 4167 polling-delay-passive = <250>; 4168 polling-delay = <1000>; 4169 4170 thermal-sensors = <&tsens0 5>; 4171 4172 trips { 4173 cluster0_alert0: trip-point0 { 4174 temperature = <90000>; 4175 hysteresis = <2000>; 4176 type = "hot"; 4177 }; 4178 cluster0_crit: cluster0_crit { 4179 temperature = <110000>; 4180 hysteresis = <2000>; 4181 type = "critical"; 4182 }; 4183 }; 4184 }; 4185 4186 cluster1-thermal { 4187 polling-delay-passive = <250>; 4188 polling-delay = <1000>; 4189 4190 thermal-sensors = <&tsens0 6>; 4191 4192 trips { 4193 cluster1_alert0: trip-point0 { 4194 temperature = <90000>; 4195 hysteresis = <2000>; 4196 type = "hot"; 4197 }; 4198 cluster1_crit: cluster1_crit { 4199 temperature = <110000>; 4200 hysteresis = <2000>; 4201 type = "critical"; 4202 }; 4203 }; 4204 }; 4205 4206 aoss1-thermal { 4207 polling-delay-passive = <250>; 4208 polling-delay = <1000>; 4209 4210 thermal-sensors = <&tsens1 0>; 4211 4212 trips { 4213 aoss1_alert0: trip-point0 { 4214 temperature = <90000>; 4215 hysteresis = <2000>; 4216 type = "hot"; 4217 }; 4218 }; 4219 }; 4220 4221 gpu-top-thermal { 4222 polling-delay-passive = <250>; 4223 polling-delay = <1000>; 4224 4225 thermal-sensors = <&tsens1 1>; 4226 4227 trips { 4228 gpu1_alert0: trip-point0 { 4229 temperature = <90000>; 4230 hysteresis = <1000>; 4231 type = "hot"; 4232 }; 4233 }; 4234 }; 4235 4236 gpu-bottom-thermal { 4237 polling-delay-passive = <250>; 4238 polling-delay = <1000>; 4239 4240 thermal-sensors = <&tsens1 2>; 4241 4242 trips { 4243 gpu2_alert0: trip-point0 { 4244 temperature = <90000>; 4245 hysteresis = <1000>; 4246 type = "hot"; 4247 }; 4248 }; 4249 }; 4250 4251 nspss1-thermal { 4252 polling-delay-passive = <250>; 4253 polling-delay = <1000>; 4254 4255 thermal-sensors = <&tsens1 3>; 4256 4257 trips { 4258 nspss1_alert0: trip-point0 { 4259 temperature = <90000>; 4260 hysteresis = <1000>; 4261 type = "hot"; 4262 }; 4263 }; 4264 }; 4265 4266 nspss2-thermal { 4267 polling-delay-passive = <250>; 4268 polling-delay = <1000>; 4269 4270 thermal-sensors = <&tsens1 4>; 4271 4272 trips { 4273 nspss2_alert0: trip-point0 { 4274 temperature = <90000>; 4275 hysteresis = <1000>; 4276 type = "hot"; 4277 }; 4278 }; 4279 }; 4280 4281 nspss3-thermal { 4282 polling-delay-passive = <250>; 4283 polling-delay = <1000>; 4284 4285 thermal-sensors = <&tsens1 5>; 4286 4287 trips { 4288 nspss3_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <1000>; 4291 type = "hot"; 4292 }; 4293 }; 4294 }; 4295 4296 video-thermal { 4297 polling-delay-passive = <250>; 4298 polling-delay = <1000>; 4299 4300 thermal-sensors = <&tsens1 6>; 4301 4302 trips { 4303 video_alert0: trip-point0 { 4304 temperature = <90000>; 4305 hysteresis = <2000>; 4306 type = "hot"; 4307 }; 4308 }; 4309 }; 4310 4311 mem-thermal { 4312 polling-delay-passive = <250>; 4313 polling-delay = <1000>; 4314 4315 thermal-sensors = <&tsens1 7>; 4316 4317 trips { 4318 mem_alert0: trip-point0 { 4319 temperature = <90000>; 4320 hysteresis = <2000>; 4321 type = "hot"; 4322 }; 4323 }; 4324 }; 4325 4326 modem1-top-thermal { 4327 polling-delay-passive = <250>; 4328 polling-delay = <1000>; 4329 4330 thermal-sensors = <&tsens1 8>; 4331 4332 trips { 4333 modem1_alert0: trip-point0 { 4334 temperature = <90000>; 4335 hysteresis = <2000>; 4336 type = "hot"; 4337 }; 4338 }; 4339 }; 4340 4341 modem2-top-thermal { 4342 polling-delay-passive = <250>; 4343 polling-delay = <1000>; 4344 4345 thermal-sensors = <&tsens1 9>; 4346 4347 trips { 4348 modem2_alert0: trip-point0 { 4349 temperature = <90000>; 4350 hysteresis = <2000>; 4351 type = "hot"; 4352 }; 4353 }; 4354 }; 4355 4356 modem3-top-thermal { 4357 polling-delay-passive = <250>; 4358 polling-delay = <1000>; 4359 4360 thermal-sensors = <&tsens1 10>; 4361 4362 trips { 4363 modem3_alert0: trip-point0 { 4364 temperature = <90000>; 4365 hysteresis = <2000>; 4366 type = "hot"; 4367 }; 4368 }; 4369 }; 4370 4371 modem4-top-thermal { 4372 polling-delay-passive = <250>; 4373 polling-delay = <1000>; 4374 4375 thermal-sensors = <&tsens1 11>; 4376 4377 trips { 4378 modem4_alert0: trip-point0 { 4379 temperature = <90000>; 4380 hysteresis = <2000>; 4381 type = "hot"; 4382 }; 4383 }; 4384 }; 4385 4386 camera-top-thermal { 4387 polling-delay-passive = <250>; 4388 polling-delay = <1000>; 4389 4390 thermal-sensors = <&tsens1 12>; 4391 4392 trips { 4393 camera1_alert0: trip-point0 { 4394 temperature = <90000>; 4395 hysteresis = <2000>; 4396 type = "hot"; 4397 }; 4398 }; 4399 }; 4400 4401 cam-bottom-thermal { 4402 polling-delay-passive = <250>; 4403 polling-delay = <1000>; 4404 4405 thermal-sensors = <&tsens1 13>; 4406 4407 trips { 4408 camera2_alert0: trip-point0 { 4409 temperature = <90000>; 4410 hysteresis = <2000>; 4411 type = "hot"; 4412 }; 4413 }; 4414 }; 4415 }; 4416 4417 timer { 4418 compatible = "arm,armv8-timer"; 4419 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4420 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4421 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4422 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4423 }; 4424}; 4425