1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/thermal/thermal.h> 20#include <dt-bindings/interconnect/qcom,sm8350.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32000>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo685"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&CPU_PD0>; 58 power-domain-names = "psci"; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo685"; 74 reg = <0x0 0x100>; 75 clocks = <&cpufreq_hw 0>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_100>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 power-domains = <&CPU_PD1>; 80 power-domain-names = "psci"; 81 #cooling-cells = <2>; 82 L2_100: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU2: cpu@200 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo685"; 92 reg = <0x0 0x200>; 93 clocks = <&cpufreq_hw 0>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_200>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD2>; 98 power-domain-names = "psci"; 99 #cooling-cells = <2>; 100 L2_200: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 next-level-cache = <&L3_0>; 104 }; 105 }; 106 107 CPU3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "qcom,kryo685"; 110 reg = <0x0 0x300>; 111 clocks = <&cpufreq_hw 0>; 112 enable-method = "psci"; 113 next-level-cache = <&L2_300>; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 power-domains = <&CPU_PD3>; 116 power-domain-names = "psci"; 117 #cooling-cells = <2>; 118 L2_300: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU4: cpu@400 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo685"; 128 reg = <0x0 0x400>; 129 clocks = <&cpufreq_hw 1>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_400>; 132 qcom,freq-domain = <&cpufreq_hw 1>; 133 power-domains = <&CPU_PD4>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 L2_400: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU5: cpu@500 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo685"; 146 reg = <0x0 0x500>; 147 clocks = <&cpufreq_hw 1>; 148 enable-method = "psci"; 149 next-level-cache = <&L2_500>; 150 qcom,freq-domain = <&cpufreq_hw 1>; 151 power-domains = <&CPU_PD5>; 152 power-domain-names = "psci"; 153 #cooling-cells = <2>; 154 L2_500: l2-cache { 155 compatible = "cache"; 156 cache-level = <2>; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU6: cpu@600 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo685"; 164 reg = <0x0 0x600>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_600>; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 power-domains = <&CPU_PD6>; 170 power-domain-names = "psci"; 171 #cooling-cells = <2>; 172 L2_600: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 CPU7: cpu@700 { 180 device_type = "cpu"; 181 compatible = "qcom,kryo685"; 182 reg = <0x0 0x700>; 183 clocks = <&cpufreq_hw 2>; 184 enable-method = "psci"; 185 next-level-cache = <&L2_700>; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 power-domains = <&CPU_PD7>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 next-level-cache = <&L3_0>; 194 }; 195 }; 196 197 cpu-map { 198 cluster0 { 199 core0 { 200 cpu = <&CPU0>; 201 }; 202 203 core1 { 204 cpu = <&CPU1>; 205 }; 206 207 core2 { 208 cpu = <&CPU2>; 209 }; 210 211 core3 { 212 cpu = <&CPU3>; 213 }; 214 215 core4 { 216 cpu = <&CPU4>; 217 }; 218 219 core5 { 220 cpu = <&CPU5>; 221 }; 222 223 core6 { 224 cpu = <&CPU6>; 225 }; 226 227 core7 { 228 cpu = <&CPU7>; 229 }; 230 }; 231 }; 232 233 idle-states { 234 entry-method = "psci"; 235 236 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "silver-rail-power-collapse"; 239 arm,psci-suspend-param = <0x40000004>; 240 entry-latency-us = <355>; 241 exit-latency-us = <909>; 242 min-residency-us = <3934>; 243 local-timer-stop; 244 }; 245 246 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "gold-rail-power-collapse"; 249 arm,psci-suspend-param = <0x40000004>; 250 entry-latency-us = <241>; 251 exit-latency-us = <1461>; 252 min-residency-us = <4488>; 253 local-timer-stop; 254 }; 255 }; 256 257 domain-idle-states { 258 CLUSTER_SLEEP_0: cluster-sleep-0 { 259 compatible = "domain-idle-state"; 260 arm,psci-suspend-param = <0x4100c344>; 261 entry-latency-us = <3263>; 262 exit-latency-us = <6562>; 263 min-residency-us = <9987>; 264 }; 265 }; 266 }; 267 268 firmware { 269 scm: scm { 270 compatible = "qcom,scm-sm8350", "qcom,scm"; 271 #reset-cells = <1>; 272 }; 273 }; 274 275 memory@80000000 { 276 device_type = "memory"; 277 /* We expect the bootloader to fill in the size */ 278 reg = <0x0 0x80000000 0x0 0x0>; 279 }; 280 281 pmu { 282 compatible = "arm,armv8-pmuv3"; 283 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 284 }; 285 286 psci { 287 compatible = "arm,psci-1.0"; 288 method = "smc"; 289 290 CPU_PD0: power-domain-cpu0 { 291 #power-domain-cells = <0>; 292 power-domains = <&CLUSTER_PD>; 293 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 294 }; 295 296 CPU_PD1: power-domain-cpu1 { 297 #power-domain-cells = <0>; 298 power-domains = <&CLUSTER_PD>; 299 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 300 }; 301 302 CPU_PD2: power-domain-cpu2 { 303 #power-domain-cells = <0>; 304 power-domains = <&CLUSTER_PD>; 305 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 306 }; 307 308 CPU_PD3: power-domain-cpu3 { 309 #power-domain-cells = <0>; 310 power-domains = <&CLUSTER_PD>; 311 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 312 }; 313 314 CPU_PD4: power-domain-cpu4 { 315 #power-domain-cells = <0>; 316 power-domains = <&CLUSTER_PD>; 317 domain-idle-states = <&BIG_CPU_SLEEP_0>; 318 }; 319 320 CPU_PD5: power-domain-cpu5 { 321 #power-domain-cells = <0>; 322 power-domains = <&CLUSTER_PD>; 323 domain-idle-states = <&BIG_CPU_SLEEP_0>; 324 }; 325 326 CPU_PD6: power-domain-cpu6 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&BIG_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD7: power-domain-cpu7 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_PD>; 335 domain-idle-states = <&BIG_CPU_SLEEP_0>; 336 }; 337 338 CLUSTER_PD: power-domain-cpu-cluster0 { 339 #power-domain-cells = <0>; 340 domain-idle-states = <&CLUSTER_SLEEP_0>; 341 }; 342 }; 343 344 qup_opp_table_100mhz: opp-table-qup100mhz { 345 compatible = "operating-points-v2"; 346 347 opp-50000000 { 348 opp-hz = /bits/ 64 <50000000>; 349 required-opps = <&rpmhpd_opp_min_svs>; 350 }; 351 352 opp-75000000 { 353 opp-hz = /bits/ 64 <75000000>; 354 required-opps = <&rpmhpd_opp_low_svs>; 355 }; 356 357 opp-100000000 { 358 opp-hz = /bits/ 64 <100000000>; 359 required-opps = <&rpmhpd_opp_svs>; 360 }; 361 }; 362 363 qup_opp_table_120mhz: opp-table-qup120mhz { 364 compatible = "operating-points-v2"; 365 366 opp-50000000 { 367 opp-hz = /bits/ 64 <50000000>; 368 required-opps = <&rpmhpd_opp_min_svs>; 369 }; 370 371 opp-75000000 { 372 opp-hz = /bits/ 64 <75000000>; 373 required-opps = <&rpmhpd_opp_low_svs>; 374 }; 375 376 opp-120000000 { 377 opp-hz = /bits/ 64 <120000000>; 378 required-opps = <&rpmhpd_opp_svs>; 379 }; 380 }; 381 382 reserved_memory: reserved-memory { 383 #address-cells = <2>; 384 #size-cells = <2>; 385 ranges; 386 387 hyp_mem: memory@80000000 { 388 reg = <0x0 0x80000000 0x0 0x600000>; 389 no-map; 390 }; 391 392 xbl_aop_mem: memory@80700000 { 393 no-map; 394 reg = <0x0 0x80700000 0x0 0x160000>; 395 }; 396 397 cmd_db: memory@80860000 { 398 compatible = "qcom,cmd-db"; 399 reg = <0x0 0x80860000 0x0 0x20000>; 400 no-map; 401 }; 402 403 reserved_xbl_uefi_log: memory@80880000 { 404 reg = <0x0 0x80880000 0x0 0x14000>; 405 no-map; 406 }; 407 408 smem@80900000 { 409 compatible = "qcom,smem"; 410 reg = <0x0 0x80900000 0x0 0x200000>; 411 hwlocks = <&tcsr_mutex 3>; 412 no-map; 413 }; 414 415 cpucp_fw_mem: memory@80b00000 { 416 reg = <0x0 0x80b00000 0x0 0x100000>; 417 no-map; 418 }; 419 420 cdsp_secure_heap: memory@80c00000 { 421 reg = <0x0 0x80c00000 0x0 0x4600000>; 422 no-map; 423 }; 424 425 pil_camera_mem: mmeory@85200000 { 426 reg = <0x0 0x85200000 0x0 0x500000>; 427 no-map; 428 }; 429 430 pil_video_mem: memory@85700000 { 431 reg = <0x0 0x85700000 0x0 0x500000>; 432 no-map; 433 }; 434 435 pil_cvp_mem: memory@85c00000 { 436 reg = <0x0 0x85c00000 0x0 0x500000>; 437 no-map; 438 }; 439 440 pil_adsp_mem: memory@86100000 { 441 reg = <0x0 0x86100000 0x0 0x2100000>; 442 no-map; 443 }; 444 445 pil_slpi_mem: memory@88200000 { 446 reg = <0x0 0x88200000 0x0 0x1500000>; 447 no-map; 448 }; 449 450 pil_cdsp_mem: memory@89700000 { 451 reg = <0x0 0x89700000 0x0 0x1e00000>; 452 no-map; 453 }; 454 455 pil_ipa_fw_mem: memory@8b500000 { 456 reg = <0x0 0x8b500000 0x0 0x10000>; 457 no-map; 458 }; 459 460 pil_ipa_gsi_mem: memory@8b510000 { 461 reg = <0x0 0x8b510000 0x0 0xa000>; 462 no-map; 463 }; 464 465 pil_gpu_mem: memory@8b51a000 { 466 reg = <0x0 0x8b51a000 0x0 0x2000>; 467 no-map; 468 }; 469 470 pil_spss_mem: memory@8b600000 { 471 reg = <0x0 0x8b600000 0x0 0x100000>; 472 no-map; 473 }; 474 475 pil_modem_mem: memory@8b800000 { 476 reg = <0x0 0x8b800000 0x0 0x10000000>; 477 no-map; 478 }; 479 480 rmtfs_mem: memory@9b800000 { 481 compatible = "qcom,rmtfs-mem"; 482 reg = <0x0 0x9b800000 0x0 0x280000>; 483 no-map; 484 485 qcom,client-id = <1>; 486 qcom,vmid = <15>; 487 }; 488 489 hyp_reserved_mem: memory@d0000000 { 490 reg = <0x0 0xd0000000 0x0 0x800000>; 491 no-map; 492 }; 493 494 pil_trustedvm_mem: memory@d0800000 { 495 reg = <0x0 0xd0800000 0x0 0x76f7000>; 496 no-map; 497 }; 498 499 qrtr_shbuf: memory@d7ef7000 { 500 reg = <0x0 0xd7ef7000 0x0 0x9000>; 501 no-map; 502 }; 503 504 chan0_shbuf: memory@d7f00000 { 505 reg = <0x0 0xd7f00000 0x0 0x80000>; 506 no-map; 507 }; 508 509 chan1_shbuf: memory@d7f80000 { 510 reg = <0x0 0xd7f80000 0x0 0x80000>; 511 no-map; 512 }; 513 514 removed_mem: memory@d8800000 { 515 reg = <0x0 0xd8800000 0x0 0x6800000>; 516 no-map; 517 }; 518 }; 519 520 smp2p-adsp { 521 compatible = "qcom,smp2p"; 522 qcom,smem = <443>, <429>; 523 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 524 IPCC_MPROC_SIGNAL_SMP2P 525 IRQ_TYPE_EDGE_RISING>; 526 mboxes = <&ipcc IPCC_CLIENT_LPASS 527 IPCC_MPROC_SIGNAL_SMP2P>; 528 529 qcom,local-pid = <0>; 530 qcom,remote-pid = <2>; 531 532 smp2p_adsp_out: master-kernel { 533 qcom,entry-name = "master-kernel"; 534 #qcom,smem-state-cells = <1>; 535 }; 536 537 smp2p_adsp_in: slave-kernel { 538 qcom,entry-name = "slave-kernel"; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 }; 542 }; 543 544 smp2p-cdsp { 545 compatible = "qcom,smp2p"; 546 qcom,smem = <94>, <432>; 547 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 548 IPCC_MPROC_SIGNAL_SMP2P 549 IRQ_TYPE_EDGE_RISING>; 550 mboxes = <&ipcc IPCC_CLIENT_CDSP 551 IPCC_MPROC_SIGNAL_SMP2P>; 552 553 qcom,local-pid = <0>; 554 qcom,remote-pid = <5>; 555 556 smp2p_cdsp_out: master-kernel { 557 qcom,entry-name = "master-kernel"; 558 #qcom,smem-state-cells = <1>; 559 }; 560 561 smp2p_cdsp_in: slave-kernel { 562 qcom,entry-name = "slave-kernel"; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 }; 566 }; 567 568 smp2p-modem { 569 compatible = "qcom,smp2p"; 570 qcom,smem = <435>, <428>; 571 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 572 IPCC_MPROC_SIGNAL_SMP2P 573 IRQ_TYPE_EDGE_RISING>; 574 mboxes = <&ipcc IPCC_CLIENT_MPSS 575 IPCC_MPROC_SIGNAL_SMP2P>; 576 577 qcom,local-pid = <0>; 578 qcom,remote-pid = <1>; 579 580 smp2p_modem_out: master-kernel { 581 qcom,entry-name = "master-kernel"; 582 #qcom,smem-state-cells = <1>; 583 }; 584 585 smp2p_modem_in: slave-kernel { 586 qcom,entry-name = "slave-kernel"; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 }; 590 591 ipa_smp2p_out: ipa-ap-to-modem { 592 qcom,entry-name = "ipa"; 593 #qcom,smem-state-cells = <1>; 594 }; 595 596 ipa_smp2p_in: ipa-modem-to-ap { 597 qcom,entry-name = "ipa"; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 }; 602 603 smp2p-slpi { 604 compatible = "qcom,smp2p"; 605 qcom,smem = <481>, <430>; 606 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 607 IPCC_MPROC_SIGNAL_SMP2P 608 IRQ_TYPE_EDGE_RISING>; 609 mboxes = <&ipcc IPCC_CLIENT_SLPI 610 IPCC_MPROC_SIGNAL_SMP2P>; 611 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <3>; 614 615 smp2p_slpi_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 smp2p_slpi_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 }; 626 627 soc: soc@0 { 628 #address-cells = <2>; 629 #size-cells = <2>; 630 ranges = <0 0 0 0 0x10 0>; 631 dma-ranges = <0 0 0 0 0x10 0>; 632 compatible = "simple-bus"; 633 634 gcc: clock-controller@100000 { 635 compatible = "qcom,gcc-sm8350"; 636 reg = <0x0 0x00100000 0x0 0x1f0000>; 637 #clock-cells = <1>; 638 #reset-cells = <1>; 639 #power-domain-cells = <1>; 640 clock-names = "bi_tcxo", 641 "sleep_clk", 642 "pcie_0_pipe_clk", 643 "pcie_1_pipe_clk", 644 "ufs_card_rx_symbol_0_clk", 645 "ufs_card_rx_symbol_1_clk", 646 "ufs_card_tx_symbol_0_clk", 647 "ufs_phy_rx_symbol_0_clk", 648 "ufs_phy_rx_symbol_1_clk", 649 "ufs_phy_tx_symbol_0_clk", 650 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 651 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 652 clocks = <&rpmhcc RPMH_CXO_CLK>, 653 <&sleep_clk>, 654 <&pcie0_phy>, 655 <&pcie1_phy>, 656 <0>, 657 <0>, 658 <0>, 659 <&ufs_mem_phy_lanes 0>, 660 <&ufs_mem_phy_lanes 1>, 661 <&ufs_mem_phy_lanes 2>, 662 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 663 <0>; 664 }; 665 666 ipcc: mailbox@408000 { 667 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 668 reg = <0 0x00408000 0 0x1000>; 669 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-controller; 671 #interrupt-cells = <3>; 672 #mbox-cells = <2>; 673 }; 674 675 gpi_dma2: dma-controller@800000 { 676 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 677 reg = <0 0x00800000 0 0x60000>; 678 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 690 dma-channels = <12>; 691 dma-channel-mask = <0xff>; 692 iommus = <&apps_smmu 0x5f6 0x0>; 693 #dma-cells = <3>; 694 status = "disabled"; 695 }; 696 697 qupv3_id_2: geniqup@8c0000 { 698 compatible = "qcom,geni-se-qup"; 699 reg = <0x0 0x008c0000 0x0 0x6000>; 700 clock-names = "m-ahb", "s-ahb"; 701 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 702 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 703 iommus = <&apps_smmu 0x5e3 0x0>; 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges; 707 status = "disabled"; 708 709 i2c14: i2c@880000 { 710 compatible = "qcom,geni-i2c"; 711 reg = <0 0x00880000 0 0x4000>; 712 clock-names = "se"; 713 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&qup_i2c14_default>; 716 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 717 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 718 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 719 dma-names = "tx", "rx"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 spi14: spi@880000 { 726 compatible = "qcom,geni-spi"; 727 reg = <0 0x00880000 0 0x4000>; 728 clock-names = "se"; 729 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 730 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 731 power-domains = <&rpmhpd SM8350_CX>; 732 operating-points-v2 = <&qup_opp_table_120mhz>; 733 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 734 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 735 dma-names = "tx", "rx"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 status = "disabled"; 739 }; 740 741 i2c15: i2c@884000 { 742 compatible = "qcom,geni-i2c"; 743 reg = <0 0x00884000 0 0x4000>; 744 clock-names = "se"; 745 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_i2c15_default>; 748 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 749 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 750 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 751 dma-names = "tx", "rx"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 spi15: spi@884000 { 758 compatible = "qcom,geni-spi"; 759 reg = <0 0x00884000 0 0x4000>; 760 clock-names = "se"; 761 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 762 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 763 power-domains = <&rpmhpd SM8350_CX>; 764 operating-points-v2 = <&qup_opp_table_120mhz>; 765 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 766 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 767 dma-names = "tx", "rx"; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 i2c16: i2c@888000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00888000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c16_default>; 780 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 781 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 782 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 783 dma-names = "tx", "rx"; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 spi16: spi@888000 { 790 compatible = "qcom,geni-spi"; 791 reg = <0 0x00888000 0 0x4000>; 792 clock-names = "se"; 793 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 794 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 795 power-domains = <&rpmhpd SM8350_CX>; 796 operating-points-v2 = <&qup_opp_table_100mhz>; 797 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 798 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 799 dma-names = "tx", "rx"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 i2c17: i2c@88c000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0 0x0088c000 0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_i2c17_default>; 812 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 813 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 814 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 815 dma-names = "tx", "rx"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 status = "disabled"; 819 }; 820 821 spi17: spi@88c000 { 822 compatible = "qcom,geni-spi"; 823 reg = <0 0x0088c000 0 0x4000>; 824 clock-names = "se"; 825 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 826 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 827 power-domains = <&rpmhpd SM8350_CX>; 828 operating-points-v2 = <&qup_opp_table_100mhz>; 829 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 830 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 831 dma-names = "tx", "rx"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 /* QUP no. 18 seems to be strictly SPI/UART-only */ 838 839 spi18: spi@890000 { 840 compatible = "qcom,geni-spi"; 841 reg = <0 0x00890000 0 0x4000>; 842 clock-names = "se"; 843 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 844 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 845 power-domains = <&rpmhpd SM8350_CX>; 846 operating-points-v2 = <&qup_opp_table_100mhz>; 847 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 848 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 849 dma-names = "tx", "rx"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 uart18: serial@890000 { 856 compatible = "qcom,geni-uart"; 857 reg = <0 0x00890000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_uart18_default>; 862 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 863 power-domains = <&rpmhpd SM8350_CX>; 864 operating-points-v2 = <&qup_opp_table_100mhz>; 865 status = "disabled"; 866 }; 867 868 i2c19: i2c@894000 { 869 compatible = "qcom,geni-i2c"; 870 reg = <0 0x00894000 0 0x4000>; 871 clock-names = "se"; 872 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_i2c19_default>; 875 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 876 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 877 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 878 dma-names = "tx", "rx"; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 status = "disabled"; 882 }; 883 884 spi19: spi@894000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00894000 0 0x4000>; 887 clock-names = "se"; 888 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 889 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 890 power-domains = <&rpmhpd SM8350_CX>; 891 operating-points-v2 = <&qup_opp_table_100mhz>; 892 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 893 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 894 dma-names = "tx", "rx"; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 status = "disabled"; 898 }; 899 }; 900 901 gpi_dma0: dma-controller@900000 { 902 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 903 reg = <0 0x09800000 0 0x60000>; 904 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 916 dma-channels = <12>; 917 dma-channel-mask = <0x7e>; 918 iommus = <&apps_smmu 0x5b6 0x0>; 919 #dma-cells = <3>; 920 status = "disabled"; 921 }; 922 923 qupv3_id_0: geniqup@9c0000 { 924 compatible = "qcom,geni-se-qup"; 925 reg = <0x0 0x009c0000 0x0 0x6000>; 926 clock-names = "m-ahb", "s-ahb"; 927 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 928 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 929 iommus = <&apps_smmu 0x5a3 0>; 930 #address-cells = <2>; 931 #size-cells = <2>; 932 ranges; 933 status = "disabled"; 934 935 i2c0: i2c@980000 { 936 compatible = "qcom,geni-i2c"; 937 reg = <0 0x00980000 0 0x4000>; 938 clock-names = "se"; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&qup_i2c0_default>; 942 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 943 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 944 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 945 dma-names = "tx", "rx"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 spi0: spi@980000 { 952 compatible = "qcom,geni-spi"; 953 reg = <0 0x00980000 0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 957 power-domains = <&rpmhpd SM8350_CX>; 958 operating-points-v2 = <&qup_opp_table_100mhz>; 959 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 960 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 961 dma-names = "tx", "rx"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 i2c1: i2c@984000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0 0x00984000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_i2c1_default>; 974 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 975 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 976 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 spi1: spi@984000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x00984000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 988 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 989 power-domains = <&rpmhpd SM8350_CX>; 990 operating-points-v2 = <&qup_opp_table_100mhz>; 991 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 992 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 993 dma-names = "tx", "rx"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 i2c2: i2c@988000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00988000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c2_default>; 1006 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1007 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1008 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1009 dma-names = "tx", "rx"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 spi2: spi@988000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00988000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1021 power-domains = <&rpmhpd SM8350_CX>; 1022 operating-points-v2 = <&qup_opp_table_100mhz>; 1023 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1024 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 uart2: serial@98c000 { 1032 compatible = "qcom,geni-debug-uart"; 1033 reg = <0 0x0098c000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_uart3_default_state>; 1038 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1039 power-domains = <&rpmhpd SM8350_CX>; 1040 operating-points-v2 = <&qup_opp_table_100mhz>; 1041 status = "disabled"; 1042 }; 1043 1044 /* QUP no. 3 seems to be strictly SPI-only */ 1045 1046 spi3: spi@98c000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0 0x0098c000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1051 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1052 power-domains = <&rpmhpd SM8350_CX>; 1053 operating-points-v2 = <&qup_opp_table_100mhz>; 1054 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1055 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1056 dma-names = "tx", "rx"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 i2c4: i2c@990000 { 1063 compatible = "qcom,geni-i2c"; 1064 reg = <0 0x00990000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c4_default>; 1069 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1070 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1071 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 spi4: spi@990000 { 1079 compatible = "qcom,geni-spi"; 1080 reg = <0 0x00990000 0 0x4000>; 1081 clock-names = "se"; 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1083 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1084 power-domains = <&rpmhpd SM8350_CX>; 1085 operating-points-v2 = <&qup_opp_table_100mhz>; 1086 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1087 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1088 dma-names = "tx", "rx"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 i2c5: i2c@994000 { 1095 compatible = "qcom,geni-i2c"; 1096 reg = <0 0x00994000 0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&qup_i2c5_default>; 1101 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1102 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1103 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1104 dma-names = "tx", "rx"; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 spi5: spi@994000 { 1111 compatible = "qcom,geni-spi"; 1112 reg = <0 0x00994000 0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1115 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1116 power-domains = <&rpmhpd SM8350_CX>; 1117 operating-points-v2 = <&qup_opp_table_100mhz>; 1118 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1119 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 i2c6: i2c@998000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x00998000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_i2c6_default>; 1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1134 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1135 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1136 dma-names = "tx", "rx"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 spi6: spi@998000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0 0x00998000 0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1147 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SM8350_CX>; 1149 operating-points-v2 = <&qup_opp_table_100mhz>; 1150 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1151 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1152 dma-names = "tx", "rx"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 uart6: serial@998000 { 1159 compatible = "qcom,geni-uart"; 1160 reg = <0 0x00998000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_uart6_default>; 1165 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1166 power-domains = <&rpmhpd SM8350_CX>; 1167 operating-points-v2 = <&qup_opp_table_100mhz>; 1168 status = "disabled"; 1169 }; 1170 1171 i2c7: i2c@99c000 { 1172 compatible = "qcom,geni-i2c"; 1173 reg = <0 0x0099c000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_i2c7_default>; 1178 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1179 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1180 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1181 dma-names = "tx", "rx"; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 spi7: spi@99c000 { 1188 compatible = "qcom,geni-spi"; 1189 reg = <0 0x0099c000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1192 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1193 power-domains = <&rpmhpd SM8350_CX>; 1194 operating-points-v2 = <&qup_opp_table_100mhz>; 1195 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1196 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1197 dma-names = "tx", "rx"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 }; 1203 1204 gpi_dma1: dma-controller@a00000 { 1205 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1206 reg = <0 0x00a00000 0 0x60000>; 1207 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1219 dma-channels = <12>; 1220 dma-channel-mask = <0xff>; 1221 iommus = <&apps_smmu 0x56 0x0>; 1222 #dma-cells = <3>; 1223 status = "disabled"; 1224 }; 1225 1226 qupv3_id_1: geniqup@ac0000 { 1227 compatible = "qcom,geni-se-qup"; 1228 reg = <0x0 0x00ac0000 0x0 0x6000>; 1229 clock-names = "m-ahb", "s-ahb"; 1230 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1231 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1232 iommus = <&apps_smmu 0x43 0>; 1233 #address-cells = <2>; 1234 #size-cells = <2>; 1235 ranges; 1236 status = "disabled"; 1237 1238 i2c8: i2c@a80000 { 1239 compatible = "qcom,geni-i2c"; 1240 reg = <0 0x00a80000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_i2c8_default>; 1245 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1246 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1247 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1248 dma-names = "tx", "rx"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 spi8: spi@a80000 { 1255 compatible = "qcom,geni-spi"; 1256 reg = <0 0x00a80000 0 0x4000>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1259 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1260 power-domains = <&rpmhpd SM8350_CX>; 1261 operating-points-v2 = <&qup_opp_table_120mhz>; 1262 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1263 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1264 dma-names = "tx", "rx"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 i2c9: i2c@a84000 { 1271 compatible = "qcom,geni-i2c"; 1272 reg = <0 0x00a84000 0 0x4000>; 1273 clock-names = "se"; 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&qup_i2c9_default>; 1277 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1278 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1279 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1280 dma-names = "tx", "rx"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 spi9: spi@a84000 { 1287 compatible = "qcom,geni-spi"; 1288 reg = <0 0x00a84000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1291 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1292 power-domains = <&rpmhpd SM8350_CX>; 1293 operating-points-v2 = <&qup_opp_table_100mhz>; 1294 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1295 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1296 dma-names = "tx", "rx"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 status = "disabled"; 1300 }; 1301 1302 i2c10: i2c@a88000 { 1303 compatible = "qcom,geni-i2c"; 1304 reg = <0 0x00a88000 0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c10_default>; 1309 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1310 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1311 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 spi10: spi@a88000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0 0x00a88000 0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1323 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SM8350_CX>; 1325 operating-points-v2 = <&qup_opp_table_100mhz>; 1326 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1327 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1328 dma-names = "tx", "rx"; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c11: i2c@a8c000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x00a8c000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c11_default>; 1341 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1343 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1344 dma-names = "tx", "rx"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 spi11: spi@a8c000 { 1351 compatible = "qcom,geni-spi"; 1352 reg = <0 0x00a8c000 0 0x4000>; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1355 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1356 power-domains = <&rpmhpd SM8350_CX>; 1357 operating-points-v2 = <&qup_opp_table_100mhz>; 1358 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1359 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1360 dma-names = "tx", "rx"; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c12: i2c@a90000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0 0x00a90000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c12_default>; 1373 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1374 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1375 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 spi12: spi@a90000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x00a90000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1387 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1388 power-domains = <&rpmhpd SM8350_CX>; 1389 operating-points-v2 = <&qup_opp_table_100mhz>; 1390 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1391 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1392 dma-names = "tx", "rx"; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 i2c13: i2c@a94000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00a94000 0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_i2c13_default>; 1405 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1407 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1408 dma-names = "tx", "rx"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 spi13: spi@a94000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00a94000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1419 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1420 power-domains = <&rpmhpd SM8350_CX>; 1421 operating-points-v2 = <&qup_opp_table_100mhz>; 1422 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1423 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1424 dma-names = "tx", "rx"; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 }; 1430 1431 rng: rng@10d3000 { 1432 compatible = "qcom,prng-ee"; 1433 reg = <0 0x010d3000 0 0x1000>; 1434 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1435 clock-names = "core"; 1436 }; 1437 1438 config_noc: interconnect@1500000 { 1439 compatible = "qcom,sm8350-config-noc"; 1440 reg = <0 0x01500000 0 0xa580>; 1441 #interconnect-cells = <2>; 1442 qcom,bcm-voters = <&apps_bcm_voter>; 1443 }; 1444 1445 mc_virt: interconnect@1580000 { 1446 compatible = "qcom,sm8350-mc-virt"; 1447 reg = <0 0x01580000 0 0x1000>; 1448 #interconnect-cells = <2>; 1449 qcom,bcm-voters = <&apps_bcm_voter>; 1450 }; 1451 1452 system_noc: interconnect@1680000 { 1453 compatible = "qcom,sm8350-system-noc"; 1454 reg = <0 0x01680000 0 0x1c200>; 1455 #interconnect-cells = <2>; 1456 qcom,bcm-voters = <&apps_bcm_voter>; 1457 }; 1458 1459 aggre1_noc: interconnect@16e0000 { 1460 compatible = "qcom,sm8350-aggre1-noc"; 1461 reg = <0 0x016e0000 0 0x1f180>; 1462 #interconnect-cells = <2>; 1463 qcom,bcm-voters = <&apps_bcm_voter>; 1464 }; 1465 1466 aggre2_noc: interconnect@1700000 { 1467 compatible = "qcom,sm8350-aggre2-noc"; 1468 reg = <0 0x01700000 0 0x33000>; 1469 #interconnect-cells = <2>; 1470 qcom,bcm-voters = <&apps_bcm_voter>; 1471 }; 1472 1473 mmss_noc: interconnect@1740000 { 1474 compatible = "qcom,sm8350-mmss-noc"; 1475 reg = <0 0x01740000 0 0x1f080>; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 pcie0: pci@1c00000 { 1481 compatible = "qcom,pcie-sm8350"; 1482 reg = <0 0x01c00000 0 0x3000>, 1483 <0 0x60000000 0 0xf1d>, 1484 <0 0x60000f20 0 0xa8>, 1485 <0 0x60001000 0 0x1000>, 1486 <0 0x60100000 0 0x100000>; 1487 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1488 device_type = "pci"; 1489 linux,pci-domain = <0>; 1490 bus-range = <0x00 0xff>; 1491 num-lanes = <1>; 1492 1493 #address-cells = <3>; 1494 #size-cells = <2>; 1495 1496 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1497 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1498 1499 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1507 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1508 "msi4", "msi5", "msi6", "msi7"; 1509 #interrupt-cells = <1>; 1510 interrupt-map-mask = <0 0 0 0x7>; 1511 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1512 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1513 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1514 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1515 1516 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1517 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1518 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1519 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1520 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1521 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1522 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1523 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1524 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1525 clock-names = "aux", 1526 "cfg", 1527 "bus_master", 1528 "bus_slave", 1529 "slave_q2a", 1530 "tbu", 1531 "ddrss_sf_tbu", 1532 "aggre1", 1533 "aggre0"; 1534 1535 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1536 <0x100 &apps_smmu 0x1c01 0x1>; 1537 1538 resets = <&gcc GCC_PCIE_0_BCR>; 1539 reset-names = "pci"; 1540 1541 power-domains = <&gcc PCIE_0_GDSC>; 1542 1543 phys = <&pcie0_phy>; 1544 phy-names = "pciephy"; 1545 1546 status = "disabled"; 1547 }; 1548 1549 pcie0_phy: phy@1c06000 { 1550 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1551 reg = <0 0x01c06000 0 0x2000>; 1552 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1553 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1554 <&gcc GCC_PCIE_0_CLKREF_EN>, 1555 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1556 <&gcc GCC_PCIE_0_PIPE_CLK>; 1557 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1558 1559 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1560 reset-names = "phy"; 1561 1562 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1563 assigned-clock-rates = <100000000>; 1564 1565 #clock-cells = <0>; 1566 clock-output-names = "pcie_0_pipe_clk"; 1567 1568 #phy-cells = <0>; 1569 1570 status = "disabled"; 1571 }; 1572 1573 pcie1: pci@1c08000 { 1574 compatible = "qcom,pcie-sm8350"; 1575 reg = <0 0x01c08000 0 0x3000>, 1576 <0 0x40000000 0 0xf1d>, 1577 <0 0x40000f20 0 0xa8>, 1578 <0 0x40001000 0 0x1000>, 1579 <0 0x40100000 0 0x100000>; 1580 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1581 device_type = "pci"; 1582 linux,pci-domain = <1>; 1583 bus-range = <0x00 0xff>; 1584 num-lanes = <2>; 1585 1586 #address-cells = <3>; 1587 #size-cells = <2>; 1588 1589 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1590 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1591 1592 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1593 interrupt-names = "msi"; 1594 #interrupt-cells = <1>; 1595 interrupt-map-mask = <0 0 0 0x7>; 1596 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1597 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1598 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1599 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1600 1601 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1602 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1603 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1604 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1605 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1606 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1607 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1608 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1609 clock-names = "aux", 1610 "cfg", 1611 "bus_master", 1612 "bus_slave", 1613 "slave_q2a", 1614 "tbu", 1615 "ddrss_sf_tbu", 1616 "aggre1"; 1617 1618 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1619 <0x100 &apps_smmu 0x1c81 0x1>; 1620 1621 resets = <&gcc GCC_PCIE_1_BCR>; 1622 reset-names = "pci"; 1623 1624 power-domains = <&gcc PCIE_1_GDSC>; 1625 1626 phys = <&pcie1_phy>; 1627 phy-names = "pciephy"; 1628 1629 status = "disabled"; 1630 }; 1631 1632 pcie1_phy: phy@1c0f000 { 1633 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1634 reg = <0 0x01c0e000 0 0x2000>; 1635 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1636 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1637 <&gcc GCC_PCIE_1_CLKREF_EN>, 1638 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1639 <&gcc GCC_PCIE_1_PIPE_CLK>; 1640 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1641 1642 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1643 reset-names = "phy"; 1644 1645 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1646 assigned-clock-rates = <100000000>; 1647 1648 #clock-cells = <0>; 1649 clock-output-names = "pcie_1_pipe_clk"; 1650 1651 #phy-cells = <0>; 1652 1653 status = "disabled"; 1654 }; 1655 1656 ufs_mem_hc: ufshc@1d84000 { 1657 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1658 "jedec,ufs-2.0"; 1659 reg = <0 0x01d84000 0 0x3000>; 1660 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1661 phys = <&ufs_mem_phy_lanes>; 1662 phy-names = "ufsphy"; 1663 lanes-per-direction = <2>; 1664 #reset-cells = <1>; 1665 resets = <&gcc GCC_UFS_PHY_BCR>; 1666 reset-names = "rst"; 1667 1668 power-domains = <&gcc UFS_PHY_GDSC>; 1669 1670 iommus = <&apps_smmu 0xe0 0x0>; 1671 dma-coherent; 1672 1673 clock-names = 1674 "core_clk", 1675 "bus_aggr_clk", 1676 "iface_clk", 1677 "core_clk_unipro", 1678 "ref_clk", 1679 "tx_lane0_sync_clk", 1680 "rx_lane0_sync_clk", 1681 "rx_lane1_sync_clk"; 1682 clocks = 1683 <&gcc GCC_UFS_PHY_AXI_CLK>, 1684 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1685 <&gcc GCC_UFS_PHY_AHB_CLK>, 1686 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1687 <&rpmhcc RPMH_CXO_CLK>, 1688 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1689 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1690 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1691 freq-table-hz = 1692 <75000000 300000000>, 1693 <0 0>, 1694 <0 0>, 1695 <75000000 300000000>, 1696 <0 0>, 1697 <0 0>, 1698 <0 0>, 1699 <0 0>; 1700 status = "disabled"; 1701 }; 1702 1703 ufs_mem_phy: phy@1d87000 { 1704 compatible = "qcom,sm8350-qmp-ufs-phy"; 1705 reg = <0 0x01d87000 0 0x1c4>; 1706 #address-cells = <2>; 1707 #size-cells = <2>; 1708 ranges; 1709 clock-names = "ref", 1710 "ref_aux"; 1711 clocks = <&rpmhcc RPMH_CXO_CLK>, 1712 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1713 1714 resets = <&ufs_mem_hc 0>; 1715 reset-names = "ufsphy"; 1716 status = "disabled"; 1717 1718 ufs_mem_phy_lanes: phy@1d87400 { 1719 reg = <0 0x01d87400 0 0x188>, 1720 <0 0x01d87600 0 0x200>, 1721 <0 0x01d87c00 0 0x200>, 1722 <0 0x01d87800 0 0x188>, 1723 <0 0x01d87a00 0 0x200>; 1724 #clock-cells = <1>; 1725 #phy-cells = <0>; 1726 }; 1727 }; 1728 1729 ipa: ipa@1e40000 { 1730 compatible = "qcom,sm8350-ipa"; 1731 1732 iommus = <&apps_smmu 0x5c0 0x0>, 1733 <&apps_smmu 0x5c2 0x0>; 1734 reg = <0 0x01e40000 0 0x8000>, 1735 <0 0x01e50000 0 0x4b20>, 1736 <0 0x01e04000 0 0x23000>; 1737 reg-names = "ipa-reg", 1738 "ipa-shared", 1739 "gsi"; 1740 1741 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1742 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1743 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1744 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1745 interrupt-names = "ipa", 1746 "gsi", 1747 "ipa-clock-query", 1748 "ipa-setup-ready"; 1749 1750 clocks = <&rpmhcc RPMH_IPA_CLK>; 1751 clock-names = "core"; 1752 1753 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1754 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1755 interconnect-names = "memory", 1756 "config"; 1757 1758 qcom,qmp = <&aoss_qmp>; 1759 1760 qcom,smem-states = <&ipa_smp2p_out 0>, 1761 <&ipa_smp2p_out 1>; 1762 qcom,smem-state-names = "ipa-clock-enabled-valid", 1763 "ipa-clock-enabled"; 1764 1765 status = "disabled"; 1766 }; 1767 1768 tcsr_mutex: hwlock@1f40000 { 1769 compatible = "qcom,tcsr-mutex"; 1770 reg = <0x0 0x01f40000 0x0 0x40000>; 1771 #hwlock-cells = <1>; 1772 }; 1773 1774 gpu: gpu@3d00000 { 1775 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1776 1777 reg = <0 0x03d00000 0 0x40000>, 1778 <0 0x03d9e000 0 0x1000>, 1779 <0 0x03d61000 0 0x800>; 1780 reg-names = "kgsl_3d0_reg_memory", 1781 "cx_mem", 1782 "cx_dbgc"; 1783 1784 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1785 1786 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1787 1788 operating-points-v2 = <&gpu_opp_table>; 1789 1790 qcom,gmu = <&gmu>; 1791 1792 status = "disabled"; 1793 1794 zap-shader { 1795 memory-region = <&pil_gpu_mem>; 1796 }; 1797 1798 /* note: downstream checks gpu binning for 670 Mhz */ 1799 gpu_opp_table: opp-table { 1800 compatible = "operating-points-v2"; 1801 1802 opp-840000000 { 1803 opp-hz = /bits/ 64 <840000000>; 1804 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1805 }; 1806 1807 opp-778000000 { 1808 opp-hz = /bits/ 64 <778000000>; 1809 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1810 }; 1811 1812 opp-738000000 { 1813 opp-hz = /bits/ 64 <738000000>; 1814 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1815 }; 1816 1817 opp-676000000 { 1818 opp-hz = /bits/ 64 <676000000>; 1819 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1820 }; 1821 1822 opp-608000000 { 1823 opp-hz = /bits/ 64 <608000000>; 1824 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1825 }; 1826 1827 opp-540000000 { 1828 opp-hz = /bits/ 64 <540000000>; 1829 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1830 }; 1831 1832 opp-491000000 { 1833 opp-hz = /bits/ 64 <491000000>; 1834 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1835 }; 1836 1837 opp-443000000 { 1838 opp-hz = /bits/ 64 <443000000>; 1839 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1840 }; 1841 1842 opp-379000000 { 1843 opp-hz = /bits/ 64 <379000000>; 1844 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1845 }; 1846 1847 opp-315000000 { 1848 opp-hz = /bits/ 64 <315000000>; 1849 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1850 }; 1851 }; 1852 }; 1853 1854 gmu: gmu@3d6a000 { 1855 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1856 1857 reg = <0 0x03d6a000 0 0x34000>, 1858 <0 0x03de0000 0 0x10000>, 1859 <0 0x0b290000 0 0x10000>; 1860 reg-names = "gmu", "rscc", "gmu_pdc"; 1861 1862 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1864 interrupt-names = "hfi", "gmu"; 1865 1866 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1867 <&gpucc GPU_CC_CXO_CLK>, 1868 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1869 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1870 <&gpucc GPU_CC_AHB_CLK>, 1871 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1872 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1873 clock-names = "gmu", 1874 "cxo", 1875 "axi", 1876 "memnoc", 1877 "ahb", 1878 "hub", 1879 "smmu_vote"; 1880 1881 power-domains = <&gpucc GPU_CX_GDSC>, 1882 <&gpucc GPU_GX_GDSC>; 1883 power-domain-names = "cx", 1884 "gx"; 1885 1886 iommus = <&adreno_smmu 5 0x400>; 1887 1888 operating-points-v2 = <&gmu_opp_table>; 1889 1890 gmu_opp_table: opp-table { 1891 compatible = "operating-points-v2"; 1892 1893 opp-200000000 { 1894 opp-hz = /bits/ 64 <200000000>; 1895 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1896 }; 1897 }; 1898 }; 1899 1900 gpucc: clock-controller@3d90000 { 1901 compatible = "qcom,sm8350-gpucc"; 1902 reg = <0 0x03d90000 0 0x9000>; 1903 clocks = <&rpmhcc RPMH_CXO_CLK>, 1904 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1905 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1906 clock-names = "bi_tcxo", 1907 "gcc_gpu_gpll0_clk_src", 1908 "gcc_gpu_gpll0_div_clk_src"; 1909 #clock-cells = <1>; 1910 #reset-cells = <1>; 1911 #power-domain-cells = <1>; 1912 }; 1913 1914 adreno_smmu: iommu@3da0000 { 1915 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1916 "qcom,smmu-500", "arm,mmu-500"; 1917 reg = <0 0x03da0000 0 0x20000>; 1918 #iommu-cells = <2>; 1919 #global-interrupts = <2>; 1920 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1932 1933 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1934 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1935 <&gpucc GPU_CC_AHB_CLK>, 1936 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1937 <&gpucc GPU_CC_CX_GMU_CLK>, 1938 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1939 <&gpucc GPU_CC_HUB_AON_CLK>; 1940 clock-names = "bus", 1941 "iface", 1942 "ahb", 1943 "hlos1_vote_gpu_smmu", 1944 "cx_gmu", 1945 "hub_cx_int", 1946 "hub_aon"; 1947 1948 power-domains = <&gpucc GPU_CX_GDSC>; 1949 dma-coherent; 1950 }; 1951 1952 lpass_ag_noc: interconnect@3c40000 { 1953 compatible = "qcom,sm8350-lpass-ag-noc"; 1954 reg = <0 0x03c40000 0 0xf080>; 1955 #interconnect-cells = <2>; 1956 qcom,bcm-voters = <&apps_bcm_voter>; 1957 }; 1958 1959 mpss: remoteproc@4080000 { 1960 compatible = "qcom,sm8350-mpss-pas"; 1961 reg = <0x0 0x04080000 0x0 0x4040>; 1962 1963 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1964 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1965 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1966 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1967 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1968 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1969 interrupt-names = "wdog", "fatal", "ready", "handover", 1970 "stop-ack", "shutdown-ack"; 1971 1972 clocks = <&rpmhcc RPMH_CXO_CLK>; 1973 clock-names = "xo"; 1974 1975 power-domains = <&rpmhpd SM8350_CX>, 1976 <&rpmhpd SM8350_MSS>; 1977 power-domain-names = "cx", "mss"; 1978 1979 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1980 1981 memory-region = <&pil_modem_mem>; 1982 1983 qcom,qmp = <&aoss_qmp>; 1984 1985 qcom,smem-states = <&smp2p_modem_out 0>; 1986 qcom,smem-state-names = "stop"; 1987 1988 status = "disabled"; 1989 1990 glink-edge { 1991 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1992 IPCC_MPROC_SIGNAL_GLINK_QMP 1993 IRQ_TYPE_EDGE_RISING>; 1994 mboxes = <&ipcc IPCC_CLIENT_MPSS 1995 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1996 label = "modem"; 1997 qcom,remote-pid = <1>; 1998 }; 1999 }; 2000 2001 slpi: remoteproc@5c00000 { 2002 compatible = "qcom,sm8350-slpi-pas"; 2003 reg = <0 0x05c00000 0 0x4000>; 2004 2005 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2006 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2007 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2008 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2009 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2010 interrupt-names = "wdog", "fatal", "ready", 2011 "handover", "stop-ack"; 2012 2013 clocks = <&rpmhcc RPMH_CXO_CLK>; 2014 clock-names = "xo"; 2015 2016 power-domains = <&rpmhpd SM8350_LCX>, 2017 <&rpmhpd SM8350_LMX>; 2018 power-domain-names = "lcx", "lmx"; 2019 2020 memory-region = <&pil_slpi_mem>; 2021 2022 qcom,qmp = <&aoss_qmp>; 2023 2024 qcom,smem-states = <&smp2p_slpi_out 0>; 2025 qcom,smem-state-names = "stop"; 2026 2027 status = "disabled"; 2028 2029 glink-edge { 2030 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2031 IPCC_MPROC_SIGNAL_GLINK_QMP 2032 IRQ_TYPE_EDGE_RISING>; 2033 mboxes = <&ipcc IPCC_CLIENT_SLPI 2034 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2035 2036 label = "slpi"; 2037 qcom,remote-pid = <3>; 2038 2039 fastrpc { 2040 compatible = "qcom,fastrpc"; 2041 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2042 label = "sdsp"; 2043 qcom,non-secure-domain; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 2047 compute-cb@1 { 2048 compatible = "qcom,fastrpc-compute-cb"; 2049 reg = <1>; 2050 iommus = <&apps_smmu 0x0541 0x0>; 2051 }; 2052 2053 compute-cb@2 { 2054 compatible = "qcom,fastrpc-compute-cb"; 2055 reg = <2>; 2056 iommus = <&apps_smmu 0x0542 0x0>; 2057 }; 2058 2059 compute-cb@3 { 2060 compatible = "qcom,fastrpc-compute-cb"; 2061 reg = <3>; 2062 iommus = <&apps_smmu 0x0543 0x0>; 2063 /* note: shared-cb = <4> in downstream */ 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 sdhc_2: mmc@8804000 { 2070 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2071 reg = <0 0x08804000 0 0x1000>; 2072 2073 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "hc_irq", "pwr_irq"; 2076 2077 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2078 <&gcc GCC_SDCC2_APPS_CLK>, 2079 <&rpmhcc RPMH_CXO_CLK>; 2080 clock-names = "iface", "core", "xo"; 2081 resets = <&gcc GCC_SDCC2_BCR>; 2082 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2084 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2085 iommus = <&apps_smmu 0x4a0 0x0>; 2086 power-domains = <&rpmhpd SM8350_CX>; 2087 operating-points-v2 = <&sdhc2_opp_table>; 2088 bus-width = <4>; 2089 dma-coherent; 2090 2091 status = "disabled"; 2092 2093 sdhc2_opp_table: opp-table { 2094 compatible = "operating-points-v2"; 2095 2096 opp-100000000 { 2097 opp-hz = /bits/ 64 <100000000>; 2098 required-opps = <&rpmhpd_opp_low_svs>; 2099 }; 2100 2101 opp-202000000 { 2102 opp-hz = /bits/ 64 <202000000>; 2103 required-opps = <&rpmhpd_opp_svs_l1>; 2104 }; 2105 }; 2106 }; 2107 2108 usb_1_hsphy: phy@88e3000 { 2109 compatible = "qcom,sm8350-usb-hs-phy", 2110 "qcom,usb-snps-hs-7nm-phy"; 2111 reg = <0 0x088e3000 0 0x400>; 2112 status = "disabled"; 2113 #phy-cells = <0>; 2114 2115 clocks = <&rpmhcc RPMH_CXO_CLK>; 2116 clock-names = "ref"; 2117 2118 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2119 }; 2120 2121 usb_2_hsphy: phy@88e4000 { 2122 compatible = "qcom,sm8250-usb-hs-phy", 2123 "qcom,usb-snps-hs-7nm-phy"; 2124 reg = <0 0x088e4000 0 0x400>; 2125 status = "disabled"; 2126 #phy-cells = <0>; 2127 2128 clocks = <&rpmhcc RPMH_CXO_CLK>; 2129 clock-names = "ref"; 2130 2131 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2132 }; 2133 2134 usb_1_qmpphy: phy@88e9000 { 2135 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2136 reg = <0 0x088e8000 0 0x3000>; 2137 2138 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2139 <&rpmhcc RPMH_CXO_CLK>, 2140 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2141 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2142 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2143 2144 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2145 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2146 reset-names = "phy", "common"; 2147 2148 #clock-cells = <1>; 2149 #phy-cells = <1>; 2150 2151 status = "disabled"; 2152 }; 2153 2154 usb_2_qmpphy: phy-wrapper@88eb000 { 2155 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2156 reg = <0 0x088eb000 0 0x200>; 2157 status = "disabled"; 2158 #address-cells = <2>; 2159 #size-cells = <2>; 2160 ranges; 2161 2162 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2163 <&rpmhcc RPMH_CXO_CLK>, 2164 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2165 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2166 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2167 2168 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2169 <&gcc GCC_USB3_PHY_SEC_BCR>; 2170 reset-names = "phy", "common"; 2171 2172 usb_2_ssphy: phy@88ebe00 { 2173 reg = <0 0x088ebe00 0 0x200>, 2174 <0 0x088ec000 0 0x200>, 2175 <0 0x088eb200 0 0x1100>; 2176 #phy-cells = <0>; 2177 #clock-cells = <0>; 2178 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2179 clock-names = "pipe0"; 2180 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2181 }; 2182 }; 2183 2184 dc_noc: interconnect@90c0000 { 2185 compatible = "qcom,sm8350-dc-noc"; 2186 reg = <0 0x090c0000 0 0x4200>; 2187 #interconnect-cells = <2>; 2188 qcom,bcm-voters = <&apps_bcm_voter>; 2189 }; 2190 2191 gem_noc: interconnect@9100000 { 2192 compatible = "qcom,sm8350-gem-noc"; 2193 reg = <0 0x09100000 0 0xb4000>; 2194 #interconnect-cells = <2>; 2195 qcom,bcm-voters = <&apps_bcm_voter>; 2196 }; 2197 2198 system-cache-controller@9200000 { 2199 compatible = "qcom,sm8350-llcc"; 2200 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2201 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2202 <0 0x09600000 0 0x58000>; 2203 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2204 "llcc3_base", "llcc_broadcast_base"; 2205 }; 2206 2207 compute_noc: interconnect@a0c0000 { 2208 compatible = "qcom,sm8350-compute-noc"; 2209 reg = <0 0x0a0c0000 0 0xa180>; 2210 #interconnect-cells = <2>; 2211 qcom,bcm-voters = <&apps_bcm_voter>; 2212 }; 2213 2214 usb_1: usb@a6f8800 { 2215 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2216 reg = <0 0x0a6f8800 0 0x400>; 2217 status = "disabled"; 2218 #address-cells = <2>; 2219 #size-cells = <2>; 2220 ranges; 2221 2222 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2223 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2224 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2225 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2226 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2227 clock-names = "cfg_noc", 2228 "core", 2229 "iface", 2230 "sleep", 2231 "mock_utmi"; 2232 2233 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2234 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2235 assigned-clock-rates = <19200000>, <200000000>; 2236 2237 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2238 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2239 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2240 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2241 interrupt-names = "hs_phy_irq", 2242 "ss_phy_irq", 2243 "dm_hs_phy_irq", 2244 "dp_hs_phy_irq"; 2245 2246 power-domains = <&gcc USB30_PRIM_GDSC>; 2247 2248 resets = <&gcc GCC_USB30_PRIM_BCR>; 2249 2250 usb_1_dwc3: usb@a600000 { 2251 compatible = "snps,dwc3"; 2252 reg = <0 0x0a600000 0 0xcd00>; 2253 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2254 iommus = <&apps_smmu 0x0 0x0>; 2255 snps,dis_u2_susphy_quirk; 2256 snps,dis_enblslpm_quirk; 2257 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2258 phy-names = "usb2-phy", "usb3-phy"; 2259 2260 ports { 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 2264 port@0 { 2265 reg = <0>; 2266 2267 usb_1_dwc3_hs: endpoint { 2268 }; 2269 }; 2270 2271 port@1 { 2272 reg = <1>; 2273 2274 usb_1_dwc3_ss: endpoint { 2275 }; 2276 }; 2277 }; 2278 }; 2279 }; 2280 2281 usb_2: usb@a8f8800 { 2282 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2283 reg = <0 0x0a8f8800 0 0x400>; 2284 status = "disabled"; 2285 #address-cells = <2>; 2286 #size-cells = <2>; 2287 ranges; 2288 2289 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2290 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2291 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2292 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2293 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2294 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2295 clock-names = "cfg_noc", 2296 "core", 2297 "iface", 2298 "sleep", 2299 "mock_utmi", 2300 "xo"; 2301 2302 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2303 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2304 assigned-clock-rates = <19200000>, <200000000>; 2305 2306 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2307 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2308 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2309 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2310 interrupt-names = "hs_phy_irq", 2311 "ss_phy_irq", 2312 "dm_hs_phy_irq", 2313 "dp_hs_phy_irq"; 2314 2315 power-domains = <&gcc USB30_SEC_GDSC>; 2316 2317 resets = <&gcc GCC_USB30_SEC_BCR>; 2318 2319 usb_2_dwc3: usb@a800000 { 2320 compatible = "snps,dwc3"; 2321 reg = <0 0x0a800000 0 0xcd00>; 2322 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2323 iommus = <&apps_smmu 0x20 0x0>; 2324 snps,dis_u2_susphy_quirk; 2325 snps,dis_enblslpm_quirk; 2326 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2327 phy-names = "usb2-phy", "usb3-phy"; 2328 }; 2329 }; 2330 2331 mdss: display-subsystem@ae00000 { 2332 compatible = "qcom,sm8350-mdss"; 2333 reg = <0 0x0ae00000 0 0x1000>; 2334 reg-names = "mdss"; 2335 2336 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2337 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2338 interconnect-names = "mdp0-mem", "mdp1-mem"; 2339 2340 power-domains = <&dispcc MDSS_GDSC>; 2341 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2342 2343 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2344 <&gcc GCC_DISP_HF_AXI_CLK>, 2345 <&gcc GCC_DISP_SF_AXI_CLK>, 2346 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2347 clock-names = "iface", "bus", "nrt_bus", "core"; 2348 2349 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2350 interrupt-controller; 2351 #interrupt-cells = <1>; 2352 2353 iommus = <&apps_smmu 0x820 0x402>; 2354 2355 status = "disabled"; 2356 2357 #address-cells = <2>; 2358 #size-cells = <2>; 2359 ranges; 2360 2361 dpu_opp_table: opp-table { 2362 compatible = "operating-points-v2"; 2363 2364 /* TODO: opp-200000000 should work with 2365 * &rpmhpd_opp_low_svs, but one some of 2366 * sm8350_hdk boards reboot using this 2367 * opp. 2368 */ 2369 opp-200000000 { 2370 opp-hz = /bits/ 64 <200000000>; 2371 required-opps = <&rpmhpd_opp_svs>; 2372 }; 2373 2374 opp-300000000 { 2375 opp-hz = /bits/ 64 <300000000>; 2376 required-opps = <&rpmhpd_opp_svs>; 2377 }; 2378 2379 opp-345000000 { 2380 opp-hz = /bits/ 64 <345000000>; 2381 required-opps = <&rpmhpd_opp_svs_l1>; 2382 }; 2383 2384 opp-460000000 { 2385 opp-hz = /bits/ 64 <460000000>; 2386 required-opps = <&rpmhpd_opp_nom>; 2387 }; 2388 }; 2389 2390 mdss_mdp: display-controller@ae01000 { 2391 compatible = "qcom,sm8350-dpu"; 2392 reg = <0 0x0ae01000 0 0x8f000>, 2393 <0 0x0aeb0000 0 0x2008>; 2394 reg-names = "mdp", "vbif"; 2395 2396 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2397 <&gcc GCC_DISP_SF_AXI_CLK>, 2398 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2399 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2400 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2401 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2402 clock-names = "bus", 2403 "nrt_bus", 2404 "iface", 2405 "lut", 2406 "core", 2407 "vsync"; 2408 2409 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2410 assigned-clock-rates = <19200000>; 2411 2412 operating-points-v2 = <&dpu_opp_table>; 2413 power-domains = <&rpmhpd SM8350_MMCX>; 2414 2415 interrupt-parent = <&mdss>; 2416 interrupts = <0>; 2417 2418 ports { 2419 #address-cells = <1>; 2420 #size-cells = <0>; 2421 2422 port@0 { 2423 reg = <0>; 2424 dpu_intf1_out: endpoint { 2425 remote-endpoint = <&mdss_dsi0_in>; 2426 }; 2427 }; 2428 2429 port@1 { 2430 reg = <1>; 2431 dpu_intf2_out: endpoint { 2432 remote-endpoint = <&mdss_dsi1_in>; 2433 }; 2434 }; 2435 2436 port@2 { 2437 reg = <2>; 2438 dpu_intf0_out: endpoint { 2439 remote-endpoint = <&mdss_dp_in>; 2440 }; 2441 }; 2442 }; 2443 }; 2444 2445 mdss_dp: displayport-controller@ae90000 { 2446 compatible = "qcom,sm8350-dp"; 2447 reg = <0 0xae90000 0 0x200>, 2448 <0 0xae90200 0 0x200>, 2449 <0 0xae90400 0 0x600>, 2450 <0 0xae91000 0 0x400>, 2451 <0 0xae91400 0 0x400>; 2452 interrupt-parent = <&mdss>; 2453 interrupts = <12>; 2454 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2455 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2456 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2457 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2458 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2459 clock-names = "core_iface", 2460 "core_aux", 2461 "ctrl_link", 2462 "ctrl_link_iface", 2463 "stream_pixel"; 2464 2465 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2466 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2467 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2468 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2469 2470 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2471 phy-names = "dp"; 2472 2473 #sound-dai-cells = <0>; 2474 2475 operating-points-v2 = <&dp_opp_table>; 2476 power-domains = <&rpmhpd SM8350_MMCX>; 2477 2478 status = "disabled"; 2479 2480 ports { 2481 #address-cells = <1>; 2482 #size-cells = <0>; 2483 2484 port@0 { 2485 reg = <0>; 2486 mdss_dp_in: endpoint { 2487 remote-endpoint = <&dpu_intf0_out>; 2488 }; 2489 }; 2490 }; 2491 2492 dp_opp_table: opp-table { 2493 compatible = "operating-points-v2"; 2494 2495 opp-160000000 { 2496 opp-hz = /bits/ 64 <160000000>; 2497 required-opps = <&rpmhpd_opp_low_svs>; 2498 }; 2499 2500 opp-270000000 { 2501 opp-hz = /bits/ 64 <270000000>; 2502 required-opps = <&rpmhpd_opp_svs>; 2503 }; 2504 2505 opp-540000000 { 2506 opp-hz = /bits/ 64 <540000000>; 2507 required-opps = <&rpmhpd_opp_svs_l1>; 2508 }; 2509 2510 opp-810000000 { 2511 opp-hz = /bits/ 64 <810000000>; 2512 required-opps = <&rpmhpd_opp_nom>; 2513 }; 2514 }; 2515 }; 2516 2517 mdss_dsi0: dsi@ae94000 { 2518 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2519 reg = <0 0x0ae94000 0 0x400>; 2520 reg-names = "dsi_ctrl"; 2521 2522 interrupt-parent = <&mdss>; 2523 interrupts = <4>; 2524 2525 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2526 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2527 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2528 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2529 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2530 <&gcc GCC_DISP_HF_AXI_CLK>; 2531 clock-names = "byte", 2532 "byte_intf", 2533 "pixel", 2534 "core", 2535 "iface", 2536 "bus"; 2537 2538 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2539 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2540 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2541 <&mdss_dsi0_phy 1>; 2542 2543 operating-points-v2 = <&dsi0_opp_table>; 2544 power-domains = <&rpmhpd SM8350_MMCX>; 2545 2546 phys = <&mdss_dsi0_phy>; 2547 2548 #address-cells = <1>; 2549 #size-cells = <0>; 2550 2551 status = "disabled"; 2552 2553 dsi0_opp_table: opp-table { 2554 compatible = "operating-points-v2"; 2555 2556 /* TODO: opp-187500000 should work with 2557 * &rpmhpd_opp_low_svs, but one some of 2558 * sm8350_hdk boards reboot using this 2559 * opp. 2560 */ 2561 opp-187500000 { 2562 opp-hz = /bits/ 64 <187500000>; 2563 required-opps = <&rpmhpd_opp_svs>; 2564 }; 2565 2566 opp-300000000 { 2567 opp-hz = /bits/ 64 <300000000>; 2568 required-opps = <&rpmhpd_opp_svs>; 2569 }; 2570 2571 opp-358000000 { 2572 opp-hz = /bits/ 64 <358000000>; 2573 required-opps = <&rpmhpd_opp_svs_l1>; 2574 }; 2575 }; 2576 2577 ports { 2578 #address-cells = <1>; 2579 #size-cells = <0>; 2580 2581 port@0 { 2582 reg = <0>; 2583 mdss_dsi0_in: endpoint { 2584 remote-endpoint = <&dpu_intf1_out>; 2585 }; 2586 }; 2587 2588 port@1 { 2589 reg = <1>; 2590 mdss_dsi0_out: endpoint { 2591 }; 2592 }; 2593 }; 2594 }; 2595 2596 mdss_dsi0_phy: phy@ae94400 { 2597 compatible = "qcom,sm8350-dsi-phy-5nm"; 2598 reg = <0 0x0ae94400 0 0x200>, 2599 <0 0x0ae94600 0 0x280>, 2600 <0 0x0ae94900 0 0x27c>; 2601 reg-names = "dsi_phy", 2602 "dsi_phy_lane", 2603 "dsi_pll"; 2604 2605 #clock-cells = <1>; 2606 #phy-cells = <0>; 2607 2608 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2609 <&rpmhcc RPMH_CXO_CLK>; 2610 clock-names = "iface", "ref"; 2611 2612 status = "disabled"; 2613 }; 2614 2615 mdss_dsi1: dsi@ae96000 { 2616 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2617 reg = <0 0x0ae96000 0 0x400>; 2618 reg-names = "dsi_ctrl"; 2619 2620 interrupt-parent = <&mdss>; 2621 interrupts = <5>; 2622 2623 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2624 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2625 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2626 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2627 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2628 <&gcc GCC_DISP_HF_AXI_CLK>; 2629 clock-names = "byte", 2630 "byte_intf", 2631 "pixel", 2632 "core", 2633 "iface", 2634 "bus"; 2635 2636 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2637 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2638 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2639 <&mdss_dsi1_phy 1>; 2640 2641 operating-points-v2 = <&dsi1_opp_table>; 2642 power-domains = <&rpmhpd SM8350_MMCX>; 2643 2644 phys = <&mdss_dsi1_phy>; 2645 2646 #address-cells = <1>; 2647 #size-cells = <0>; 2648 2649 status = "disabled"; 2650 2651 dsi1_opp_table: opp-table { 2652 compatible = "operating-points-v2"; 2653 2654 /* TODO: opp-187500000 should work with 2655 * &rpmhpd_opp_low_svs, but one some of 2656 * sm8350_hdk boards reboot using this 2657 * opp. 2658 */ 2659 opp-187500000 { 2660 opp-hz = /bits/ 64 <187500000>; 2661 required-opps = <&rpmhpd_opp_svs>; 2662 }; 2663 2664 opp-300000000 { 2665 opp-hz = /bits/ 64 <300000000>; 2666 required-opps = <&rpmhpd_opp_svs>; 2667 }; 2668 2669 opp-358000000 { 2670 opp-hz = /bits/ 64 <358000000>; 2671 required-opps = <&rpmhpd_opp_svs_l1>; 2672 }; 2673 }; 2674 2675 ports { 2676 #address-cells = <1>; 2677 #size-cells = <0>; 2678 2679 port@0 { 2680 reg = <0>; 2681 mdss_dsi1_in: endpoint { 2682 remote-endpoint = <&dpu_intf2_out>; 2683 }; 2684 }; 2685 2686 port@1 { 2687 reg = <1>; 2688 mdss_dsi1_out: endpoint { 2689 }; 2690 }; 2691 }; 2692 }; 2693 2694 mdss_dsi1_phy: phy@ae96400 { 2695 compatible = "qcom,sm8350-dsi-phy-5nm"; 2696 reg = <0 0x0ae96400 0 0x200>, 2697 <0 0x0ae96600 0 0x280>, 2698 <0 0x0ae96900 0 0x27c>; 2699 reg-names = "dsi_phy", 2700 "dsi_phy_lane", 2701 "dsi_pll"; 2702 2703 #clock-cells = <1>; 2704 #phy-cells = <0>; 2705 2706 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2707 <&rpmhcc RPMH_CXO_CLK>; 2708 clock-names = "iface", "ref"; 2709 2710 status = "disabled"; 2711 }; 2712 }; 2713 2714 dispcc: clock-controller@af00000 { 2715 compatible = "qcom,sm8350-dispcc"; 2716 reg = <0 0x0af00000 0 0x10000>; 2717 clocks = <&rpmhcc RPMH_CXO_CLK>, 2718 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2719 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2720 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2721 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2722 clock-names = "bi_tcxo", 2723 "dsi0_phy_pll_out_byteclk", 2724 "dsi0_phy_pll_out_dsiclk", 2725 "dsi1_phy_pll_out_byteclk", 2726 "dsi1_phy_pll_out_dsiclk", 2727 "dp_phy_pll_link_clk", 2728 "dp_phy_pll_vco_div_clk"; 2729 #clock-cells = <1>; 2730 #reset-cells = <1>; 2731 #power-domain-cells = <1>; 2732 2733 power-domains = <&rpmhpd SM8350_MMCX>; 2734 }; 2735 2736 pdc: interrupt-controller@b220000 { 2737 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2738 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2739 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2740 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2741 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2742 <156 716 12>; 2743 #interrupt-cells = <2>; 2744 interrupt-parent = <&intc>; 2745 interrupt-controller; 2746 }; 2747 2748 tsens0: thermal-sensor@c263000 { 2749 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2750 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2751 <0 0x0c222000 0 0x8>; /* SROT */ 2752 #qcom,sensors = <15>; 2753 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2754 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2755 interrupt-names = "uplow", "critical"; 2756 #thermal-sensor-cells = <1>; 2757 }; 2758 2759 tsens1: thermal-sensor@c265000 { 2760 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2761 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2762 <0 0x0c223000 0 0x8>; /* SROT */ 2763 #qcom,sensors = <14>; 2764 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2765 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2766 interrupt-names = "uplow", "critical"; 2767 #thermal-sensor-cells = <1>; 2768 }; 2769 2770 aoss_qmp: power-management@c300000 { 2771 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2772 reg = <0 0x0c300000 0 0x400>; 2773 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2774 IRQ_TYPE_EDGE_RISING>; 2775 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2776 2777 #clock-cells = <0>; 2778 }; 2779 2780 sram@c3f0000 { 2781 compatible = "qcom,rpmh-stats"; 2782 reg = <0 0x0c3f0000 0 0x400>; 2783 }; 2784 2785 spmi_bus: spmi@c440000 { 2786 compatible = "qcom,spmi-pmic-arb"; 2787 reg = <0x0 0x0c440000 0x0 0x1100>, 2788 <0x0 0x0c600000 0x0 0x2000000>, 2789 <0x0 0x0e600000 0x0 0x100000>, 2790 <0x0 0x0e700000 0x0 0xa0000>, 2791 <0x0 0x0c40a000 0x0 0x26000>; 2792 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2793 interrupt-names = "periph_irq"; 2794 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2795 qcom,ee = <0>; 2796 qcom,channel = <0>; 2797 #address-cells = <2>; 2798 #size-cells = <0>; 2799 interrupt-controller; 2800 #interrupt-cells = <4>; 2801 }; 2802 2803 tlmm: pinctrl@f100000 { 2804 compatible = "qcom,sm8350-tlmm"; 2805 reg = <0 0x0f100000 0 0x300000>; 2806 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2807 gpio-controller; 2808 #gpio-cells = <2>; 2809 interrupt-controller; 2810 #interrupt-cells = <2>; 2811 gpio-ranges = <&tlmm 0 0 204>; 2812 wakeup-parent = <&pdc>; 2813 2814 sdc2_default_state: sdc2-default-state { 2815 clk-pins { 2816 pins = "sdc2_clk"; 2817 drive-strength = <16>; 2818 bias-disable; 2819 }; 2820 2821 cmd-pins { 2822 pins = "sdc2_cmd"; 2823 drive-strength = <16>; 2824 bias-pull-up; 2825 }; 2826 2827 data-pins { 2828 pins = "sdc2_data"; 2829 drive-strength = <16>; 2830 bias-pull-up; 2831 }; 2832 }; 2833 2834 sdc2_sleep_state: sdc2-sleep-state { 2835 clk-pins { 2836 pins = "sdc2_clk"; 2837 drive-strength = <2>; 2838 bias-disable; 2839 }; 2840 2841 cmd-pins { 2842 pins = "sdc2_cmd"; 2843 drive-strength = <2>; 2844 bias-pull-up; 2845 }; 2846 2847 data-pins { 2848 pins = "sdc2_data"; 2849 drive-strength = <2>; 2850 bias-pull-up; 2851 }; 2852 }; 2853 2854 qup_uart3_default_state: qup-uart3-default-state { 2855 rx-pins { 2856 pins = "gpio18"; 2857 function = "qup3"; 2858 }; 2859 tx-pins { 2860 pins = "gpio19"; 2861 function = "qup3"; 2862 }; 2863 }; 2864 2865 qup_uart6_default: qup-uart6-default-state { 2866 pins = "gpio30", "gpio31"; 2867 function = "qup6"; 2868 drive-strength = <2>; 2869 bias-disable; 2870 }; 2871 2872 qup_uart18_default: qup-uart18-default-state { 2873 pins = "gpio58", "gpio59"; 2874 function = "qup18"; 2875 drive-strength = <2>; 2876 bias-disable; 2877 }; 2878 2879 qup_i2c0_default: qup-i2c0-default-state { 2880 pins = "gpio4", "gpio5"; 2881 function = "qup0"; 2882 drive-strength = <2>; 2883 bias-pull-up; 2884 }; 2885 2886 qup_i2c1_default: qup-i2c1-default-state { 2887 pins = "gpio8", "gpio9"; 2888 function = "qup1"; 2889 drive-strength = <2>; 2890 bias-pull-up; 2891 }; 2892 2893 qup_i2c2_default: qup-i2c2-default-state { 2894 pins = "gpio12", "gpio13"; 2895 function = "qup2"; 2896 drive-strength = <2>; 2897 bias-pull-up; 2898 }; 2899 2900 qup_i2c4_default: qup-i2c4-default-state { 2901 pins = "gpio20", "gpio21"; 2902 function = "qup4"; 2903 drive-strength = <2>; 2904 bias-pull-up; 2905 }; 2906 2907 qup_i2c5_default: qup-i2c5-default-state { 2908 pins = "gpio24", "gpio25"; 2909 function = "qup5"; 2910 drive-strength = <2>; 2911 bias-pull-up; 2912 }; 2913 2914 qup_i2c6_default: qup-i2c6-default-state { 2915 pins = "gpio28", "gpio29"; 2916 function = "qup6"; 2917 drive-strength = <2>; 2918 bias-pull-up; 2919 }; 2920 2921 qup_i2c7_default: qup-i2c7-default-state { 2922 pins = "gpio32", "gpio33"; 2923 function = "qup7"; 2924 drive-strength = <2>; 2925 bias-disable; 2926 }; 2927 2928 qup_i2c8_default: qup-i2c8-default-state { 2929 pins = "gpio36", "gpio37"; 2930 function = "qup8"; 2931 drive-strength = <2>; 2932 bias-pull-up; 2933 }; 2934 2935 qup_i2c9_default: qup-i2c9-default-state { 2936 pins = "gpio40", "gpio41"; 2937 function = "qup9"; 2938 drive-strength = <2>; 2939 bias-pull-up; 2940 }; 2941 2942 qup_i2c10_default: qup-i2c10-default-state { 2943 pins = "gpio44", "gpio45"; 2944 function = "qup10"; 2945 drive-strength = <2>; 2946 bias-pull-up; 2947 }; 2948 2949 qup_i2c11_default: qup-i2c11-default-state { 2950 pins = "gpio48", "gpio49"; 2951 function = "qup11"; 2952 drive-strength = <2>; 2953 bias-pull-up; 2954 }; 2955 2956 qup_i2c12_default: qup-i2c12-default-state { 2957 pins = "gpio52", "gpio53"; 2958 function = "qup12"; 2959 drive-strength = <2>; 2960 bias-pull-up; 2961 }; 2962 2963 qup_i2c13_default: qup-i2c13-default-state { 2964 pins = "gpio0", "gpio1"; 2965 function = "qup13"; 2966 drive-strength = <2>; 2967 bias-pull-up; 2968 }; 2969 2970 qup_i2c14_default: qup-i2c14-default-state { 2971 pins = "gpio56", "gpio57"; 2972 function = "qup14"; 2973 drive-strength = <2>; 2974 bias-disable; 2975 }; 2976 2977 qup_i2c15_default: qup-i2c15-default-state { 2978 pins = "gpio60", "gpio61"; 2979 function = "qup15"; 2980 drive-strength = <2>; 2981 bias-disable; 2982 }; 2983 2984 qup_i2c16_default: qup-i2c16-default-state { 2985 pins = "gpio64", "gpio65"; 2986 function = "qup16"; 2987 drive-strength = <2>; 2988 bias-disable; 2989 }; 2990 2991 qup_i2c17_default: qup-i2c17-default-state { 2992 pins = "gpio72", "gpio73"; 2993 function = "qup17"; 2994 drive-strength = <2>; 2995 bias-disable; 2996 }; 2997 2998 qup_i2c19_default: qup-i2c19-default-state { 2999 pins = "gpio76", "gpio77"; 3000 function = "qup19"; 3001 drive-strength = <2>; 3002 bias-disable; 3003 }; 3004 }; 3005 3006 apps_smmu: iommu@15000000 { 3007 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3008 reg = <0 0x15000000 0 0x100000>; 3009 #iommu-cells = <2>; 3010 #global-interrupts = <2>; 3011 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3012 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3013 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3014 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3017 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3018 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3019 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3026 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3027 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3037 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3038 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3039 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3040 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3041 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3042 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3043 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3044 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3045 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3046 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3047 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3048 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3051 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3052 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3109 }; 3110 3111 adsp: remoteproc@17300000 { 3112 compatible = "qcom,sm8350-adsp-pas"; 3113 reg = <0 0x17300000 0 0x100>; 3114 3115 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3116 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3117 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3118 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3119 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3120 interrupt-names = "wdog", "fatal", "ready", 3121 "handover", "stop-ack"; 3122 3123 clocks = <&rpmhcc RPMH_CXO_CLK>; 3124 clock-names = "xo"; 3125 3126 power-domains = <&rpmhpd SM8350_LCX>, 3127 <&rpmhpd SM8350_LMX>; 3128 power-domain-names = "lcx", "lmx"; 3129 3130 memory-region = <&pil_adsp_mem>; 3131 3132 qcom,qmp = <&aoss_qmp>; 3133 3134 qcom,smem-states = <&smp2p_adsp_out 0>; 3135 qcom,smem-state-names = "stop"; 3136 3137 status = "disabled"; 3138 3139 glink-edge { 3140 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3141 IPCC_MPROC_SIGNAL_GLINK_QMP 3142 IRQ_TYPE_EDGE_RISING>; 3143 mboxes = <&ipcc IPCC_CLIENT_LPASS 3144 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3145 3146 label = "lpass"; 3147 qcom,remote-pid = <2>; 3148 3149 fastrpc { 3150 compatible = "qcom,fastrpc"; 3151 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3152 label = "adsp"; 3153 qcom,non-secure-domain; 3154 #address-cells = <1>; 3155 #size-cells = <0>; 3156 3157 compute-cb@3 { 3158 compatible = "qcom,fastrpc-compute-cb"; 3159 reg = <3>; 3160 iommus = <&apps_smmu 0x1803 0x0>; 3161 }; 3162 3163 compute-cb@4 { 3164 compatible = "qcom,fastrpc-compute-cb"; 3165 reg = <4>; 3166 iommus = <&apps_smmu 0x1804 0x0>; 3167 }; 3168 3169 compute-cb@5 { 3170 compatible = "qcom,fastrpc-compute-cb"; 3171 reg = <5>; 3172 iommus = <&apps_smmu 0x1805 0x0>; 3173 }; 3174 }; 3175 }; 3176 }; 3177 3178 intc: interrupt-controller@17a00000 { 3179 compatible = "arm,gic-v3"; 3180 #interrupt-cells = <3>; 3181 interrupt-controller; 3182 #redistributor-regions = <1>; 3183 redistributor-stride = <0 0x20000>; 3184 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3185 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3186 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3187 }; 3188 3189 timer@17c20000 { 3190 compatible = "arm,armv7-timer-mem"; 3191 #address-cells = <1>; 3192 #size-cells = <1>; 3193 ranges = <0 0 0 0x20000000>; 3194 reg = <0x0 0x17c20000 0x0 0x1000>; 3195 clock-frequency = <19200000>; 3196 3197 frame@17c21000 { 3198 frame-number = <0>; 3199 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3201 reg = <0x17c21000 0x1000>, 3202 <0x17c22000 0x1000>; 3203 }; 3204 3205 frame@17c23000 { 3206 frame-number = <1>; 3207 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3208 reg = <0x17c23000 0x1000>; 3209 status = "disabled"; 3210 }; 3211 3212 frame@17c25000 { 3213 frame-number = <2>; 3214 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3215 reg = <0x17c25000 0x1000>; 3216 status = "disabled"; 3217 }; 3218 3219 frame@17c27000 { 3220 frame-number = <3>; 3221 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3222 reg = <0x17c27000 0x1000>; 3223 status = "disabled"; 3224 }; 3225 3226 frame@17c29000 { 3227 frame-number = <4>; 3228 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3229 reg = <0x17c29000 0x1000>; 3230 status = "disabled"; 3231 }; 3232 3233 frame@17c2b000 { 3234 frame-number = <5>; 3235 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3236 reg = <0x17c2b000 0x1000>; 3237 status = "disabled"; 3238 }; 3239 3240 frame@17c2d000 { 3241 frame-number = <6>; 3242 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3243 reg = <0x17c2d000 0x1000>; 3244 status = "disabled"; 3245 }; 3246 }; 3247 3248 apps_rsc: rsc@18200000 { 3249 label = "apps_rsc"; 3250 compatible = "qcom,rpmh-rsc"; 3251 reg = <0x0 0x18200000 0x0 0x10000>, 3252 <0x0 0x18210000 0x0 0x10000>, 3253 <0x0 0x18220000 0x0 0x10000>; 3254 reg-names = "drv-0", "drv-1", "drv-2"; 3255 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3258 qcom,tcs-offset = <0xd00>; 3259 qcom,drv-id = <2>; 3260 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3261 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3262 power-domains = <&CLUSTER_PD>; 3263 3264 rpmhcc: clock-controller { 3265 compatible = "qcom,sm8350-rpmh-clk"; 3266 #clock-cells = <1>; 3267 clock-names = "xo"; 3268 clocks = <&xo_board>; 3269 }; 3270 3271 rpmhpd: power-controller { 3272 compatible = "qcom,sm8350-rpmhpd"; 3273 #power-domain-cells = <1>; 3274 operating-points-v2 = <&rpmhpd_opp_table>; 3275 3276 rpmhpd_opp_table: opp-table { 3277 compatible = "operating-points-v2"; 3278 3279 rpmhpd_opp_ret: opp1 { 3280 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3281 }; 3282 3283 rpmhpd_opp_min_svs: opp2 { 3284 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3285 }; 3286 3287 rpmhpd_opp_low_svs: opp3 { 3288 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3289 }; 3290 3291 rpmhpd_opp_svs: opp4 { 3292 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3293 }; 3294 3295 rpmhpd_opp_svs_l1: opp5 { 3296 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3297 }; 3298 3299 rpmhpd_opp_nom: opp6 { 3300 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3301 }; 3302 3303 rpmhpd_opp_nom_l1: opp7 { 3304 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3305 }; 3306 3307 rpmhpd_opp_nom_l2: opp8 { 3308 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3309 }; 3310 3311 rpmhpd_opp_turbo: opp9 { 3312 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3313 }; 3314 3315 rpmhpd_opp_turbo_l1: opp10 { 3316 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3317 }; 3318 }; 3319 }; 3320 3321 apps_bcm_voter: bcm-voter { 3322 compatible = "qcom,bcm-voter"; 3323 }; 3324 }; 3325 3326 cpufreq_hw: cpufreq@18591000 { 3327 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3328 reg = <0 0x18591000 0 0x1000>, 3329 <0 0x18592000 0 0x1000>, 3330 <0 0x18593000 0 0x1000>; 3331 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3332 3333 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3334 clock-names = "xo", "alternate"; 3335 3336 #freq-domain-cells = <1>; 3337 #clock-cells = <1>; 3338 }; 3339 3340 cdsp: remoteproc@98900000 { 3341 compatible = "qcom,sm8350-cdsp-pas"; 3342 reg = <0 0x98900000 0 0x1400000>; 3343 3344 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3345 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3346 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3347 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3348 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3349 interrupt-names = "wdog", "fatal", "ready", 3350 "handover", "stop-ack"; 3351 3352 clocks = <&rpmhcc RPMH_CXO_CLK>; 3353 clock-names = "xo"; 3354 3355 power-domains = <&rpmhpd SM8350_CX>, 3356 <&rpmhpd SM8350_MXC>; 3357 power-domain-names = "cx", "mxc"; 3358 3359 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3360 3361 memory-region = <&pil_cdsp_mem>; 3362 3363 qcom,qmp = <&aoss_qmp>; 3364 3365 qcom,smem-states = <&smp2p_cdsp_out 0>; 3366 qcom,smem-state-names = "stop"; 3367 3368 status = "disabled"; 3369 3370 glink-edge { 3371 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3372 IPCC_MPROC_SIGNAL_GLINK_QMP 3373 IRQ_TYPE_EDGE_RISING>; 3374 mboxes = <&ipcc IPCC_CLIENT_CDSP 3375 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3376 3377 label = "cdsp"; 3378 qcom,remote-pid = <5>; 3379 3380 fastrpc { 3381 compatible = "qcom,fastrpc"; 3382 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3383 label = "cdsp"; 3384 qcom,non-secure-domain; 3385 #address-cells = <1>; 3386 #size-cells = <0>; 3387 3388 compute-cb@1 { 3389 compatible = "qcom,fastrpc-compute-cb"; 3390 reg = <1>; 3391 iommus = <&apps_smmu 0x2161 0x0400>, 3392 <&apps_smmu 0x1181 0x0420>; 3393 }; 3394 3395 compute-cb@2 { 3396 compatible = "qcom,fastrpc-compute-cb"; 3397 reg = <2>; 3398 iommus = <&apps_smmu 0x2162 0x0400>, 3399 <&apps_smmu 0x1182 0x0420>; 3400 }; 3401 3402 compute-cb@3 { 3403 compatible = "qcom,fastrpc-compute-cb"; 3404 reg = <3>; 3405 iommus = <&apps_smmu 0x2163 0x0400>, 3406 <&apps_smmu 0x1183 0x0420>; 3407 }; 3408 3409 compute-cb@4 { 3410 compatible = "qcom,fastrpc-compute-cb"; 3411 reg = <4>; 3412 iommus = <&apps_smmu 0x2164 0x0400>, 3413 <&apps_smmu 0x1184 0x0420>; 3414 }; 3415 3416 compute-cb@5 { 3417 compatible = "qcom,fastrpc-compute-cb"; 3418 reg = <5>; 3419 iommus = <&apps_smmu 0x2165 0x0400>, 3420 <&apps_smmu 0x1185 0x0420>; 3421 }; 3422 3423 compute-cb@6 { 3424 compatible = "qcom,fastrpc-compute-cb"; 3425 reg = <6>; 3426 iommus = <&apps_smmu 0x2166 0x0400>, 3427 <&apps_smmu 0x1186 0x0420>; 3428 }; 3429 3430 compute-cb@7 { 3431 compatible = "qcom,fastrpc-compute-cb"; 3432 reg = <7>; 3433 iommus = <&apps_smmu 0x2167 0x0400>, 3434 <&apps_smmu 0x1187 0x0420>; 3435 }; 3436 3437 compute-cb@8 { 3438 compatible = "qcom,fastrpc-compute-cb"; 3439 reg = <8>; 3440 iommus = <&apps_smmu 0x2168 0x0400>, 3441 <&apps_smmu 0x1188 0x0420>; 3442 }; 3443 3444 /* note: secure cb9 in downstream */ 3445 }; 3446 }; 3447 }; 3448 }; 3449 3450 thermal_zones: thermal-zones { 3451 cpu0-thermal { 3452 polling-delay-passive = <250>; 3453 polling-delay = <1000>; 3454 3455 thermal-sensors = <&tsens0 1>; 3456 3457 trips { 3458 cpu0_alert0: trip-point0 { 3459 temperature = <90000>; 3460 hysteresis = <2000>; 3461 type = "passive"; 3462 }; 3463 3464 cpu0_alert1: trip-point1 { 3465 temperature = <95000>; 3466 hysteresis = <2000>; 3467 type = "passive"; 3468 }; 3469 3470 cpu0_crit: cpu-crit { 3471 temperature = <110000>; 3472 hysteresis = <1000>; 3473 type = "critical"; 3474 }; 3475 }; 3476 3477 cooling-maps { 3478 map0 { 3479 trip = <&cpu0_alert0>; 3480 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3481 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3482 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3483 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3484 }; 3485 map1 { 3486 trip = <&cpu0_alert1>; 3487 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3488 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3489 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3490 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3491 }; 3492 }; 3493 }; 3494 3495 cpu1-thermal { 3496 polling-delay-passive = <250>; 3497 polling-delay = <1000>; 3498 3499 thermal-sensors = <&tsens0 2>; 3500 3501 trips { 3502 cpu1_alert0: trip-point0 { 3503 temperature = <90000>; 3504 hysteresis = <2000>; 3505 type = "passive"; 3506 }; 3507 3508 cpu1_alert1: trip-point1 { 3509 temperature = <95000>; 3510 hysteresis = <2000>; 3511 type = "passive"; 3512 }; 3513 3514 cpu1_crit: cpu-crit { 3515 temperature = <110000>; 3516 hysteresis = <1000>; 3517 type = "critical"; 3518 }; 3519 }; 3520 3521 cooling-maps { 3522 map0 { 3523 trip = <&cpu1_alert0>; 3524 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3525 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3526 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3527 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3528 }; 3529 map1 { 3530 trip = <&cpu1_alert1>; 3531 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3532 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3533 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3534 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3535 }; 3536 }; 3537 }; 3538 3539 cpu2-thermal { 3540 polling-delay-passive = <250>; 3541 polling-delay = <1000>; 3542 3543 thermal-sensors = <&tsens0 3>; 3544 3545 trips { 3546 cpu2_alert0: trip-point0 { 3547 temperature = <90000>; 3548 hysteresis = <2000>; 3549 type = "passive"; 3550 }; 3551 3552 cpu2_alert1: trip-point1 { 3553 temperature = <95000>; 3554 hysteresis = <2000>; 3555 type = "passive"; 3556 }; 3557 3558 cpu2_crit: cpu-crit { 3559 temperature = <110000>; 3560 hysteresis = <1000>; 3561 type = "critical"; 3562 }; 3563 }; 3564 3565 cooling-maps { 3566 map0 { 3567 trip = <&cpu2_alert0>; 3568 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3569 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3570 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3571 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3572 }; 3573 map1 { 3574 trip = <&cpu2_alert1>; 3575 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3576 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3577 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3578 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3579 }; 3580 }; 3581 }; 3582 3583 cpu3-thermal { 3584 polling-delay-passive = <250>; 3585 polling-delay = <1000>; 3586 3587 thermal-sensors = <&tsens0 4>; 3588 3589 trips { 3590 cpu3_alert0: trip-point0 { 3591 temperature = <90000>; 3592 hysteresis = <2000>; 3593 type = "passive"; 3594 }; 3595 3596 cpu3_alert1: trip-point1 { 3597 temperature = <95000>; 3598 hysteresis = <2000>; 3599 type = "passive"; 3600 }; 3601 3602 cpu3_crit: cpu-crit { 3603 temperature = <110000>; 3604 hysteresis = <1000>; 3605 type = "critical"; 3606 }; 3607 }; 3608 3609 cooling-maps { 3610 map0 { 3611 trip = <&cpu3_alert0>; 3612 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3613 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3614 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3615 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3616 }; 3617 map1 { 3618 trip = <&cpu3_alert1>; 3619 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3620 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3621 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3622 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3623 }; 3624 }; 3625 }; 3626 3627 cpu4-top-thermal { 3628 polling-delay-passive = <250>; 3629 polling-delay = <1000>; 3630 3631 thermal-sensors = <&tsens0 7>; 3632 3633 trips { 3634 cpu4_top_alert0: trip-point0 { 3635 temperature = <90000>; 3636 hysteresis = <2000>; 3637 type = "passive"; 3638 }; 3639 3640 cpu4_top_alert1: trip-point1 { 3641 temperature = <95000>; 3642 hysteresis = <2000>; 3643 type = "passive"; 3644 }; 3645 3646 cpu4_top_crit: cpu-crit { 3647 temperature = <110000>; 3648 hysteresis = <1000>; 3649 type = "critical"; 3650 }; 3651 }; 3652 3653 cooling-maps { 3654 map0 { 3655 trip = <&cpu4_top_alert0>; 3656 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3657 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3658 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3659 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3660 }; 3661 map1 { 3662 trip = <&cpu4_top_alert1>; 3663 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3664 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3665 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3666 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3667 }; 3668 }; 3669 }; 3670 3671 cpu5-top-thermal { 3672 polling-delay-passive = <250>; 3673 polling-delay = <1000>; 3674 3675 thermal-sensors = <&tsens0 8>; 3676 3677 trips { 3678 cpu5_top_alert0: trip-point0 { 3679 temperature = <90000>; 3680 hysteresis = <2000>; 3681 type = "passive"; 3682 }; 3683 3684 cpu5_top_alert1: trip-point1 { 3685 temperature = <95000>; 3686 hysteresis = <2000>; 3687 type = "passive"; 3688 }; 3689 3690 cpu5_top_crit: cpu-crit { 3691 temperature = <110000>; 3692 hysteresis = <1000>; 3693 type = "critical"; 3694 }; 3695 }; 3696 3697 cooling-maps { 3698 map0 { 3699 trip = <&cpu5_top_alert0>; 3700 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3701 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3702 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3703 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3704 }; 3705 map1 { 3706 trip = <&cpu5_top_alert1>; 3707 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3708 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3709 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3710 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3711 }; 3712 }; 3713 }; 3714 3715 cpu6-top-thermal { 3716 polling-delay-passive = <250>; 3717 polling-delay = <1000>; 3718 3719 thermal-sensors = <&tsens0 9>; 3720 3721 trips { 3722 cpu6_top_alert0: trip-point0 { 3723 temperature = <90000>; 3724 hysteresis = <2000>; 3725 type = "passive"; 3726 }; 3727 3728 cpu6_top_alert1: trip-point1 { 3729 temperature = <95000>; 3730 hysteresis = <2000>; 3731 type = "passive"; 3732 }; 3733 3734 cpu6_top_crit: cpu-crit { 3735 temperature = <110000>; 3736 hysteresis = <1000>; 3737 type = "critical"; 3738 }; 3739 }; 3740 3741 cooling-maps { 3742 map0 { 3743 trip = <&cpu6_top_alert0>; 3744 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3745 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3748 }; 3749 map1 { 3750 trip = <&cpu6_top_alert1>; 3751 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3752 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3753 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3755 }; 3756 }; 3757 }; 3758 3759 cpu7-top-thermal { 3760 polling-delay-passive = <250>; 3761 polling-delay = <1000>; 3762 3763 thermal-sensors = <&tsens0 10>; 3764 3765 trips { 3766 cpu7_top_alert0: trip-point0 { 3767 temperature = <90000>; 3768 hysteresis = <2000>; 3769 type = "passive"; 3770 }; 3771 3772 cpu7_top_alert1: trip-point1 { 3773 temperature = <95000>; 3774 hysteresis = <2000>; 3775 type = "passive"; 3776 }; 3777 3778 cpu7_top_crit: cpu-crit { 3779 temperature = <110000>; 3780 hysteresis = <1000>; 3781 type = "critical"; 3782 }; 3783 }; 3784 3785 cooling-maps { 3786 map0 { 3787 trip = <&cpu7_top_alert0>; 3788 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3789 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3790 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3792 }; 3793 map1 { 3794 trip = <&cpu7_top_alert1>; 3795 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3796 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3797 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3799 }; 3800 }; 3801 }; 3802 3803 cpu4-bottom-thermal { 3804 polling-delay-passive = <250>; 3805 polling-delay = <1000>; 3806 3807 thermal-sensors = <&tsens0 11>; 3808 3809 trips { 3810 cpu4_bottom_alert0: trip-point0 { 3811 temperature = <90000>; 3812 hysteresis = <2000>; 3813 type = "passive"; 3814 }; 3815 3816 cpu4_bottom_alert1: trip-point1 { 3817 temperature = <95000>; 3818 hysteresis = <2000>; 3819 type = "passive"; 3820 }; 3821 3822 cpu4_bottom_crit: cpu-crit { 3823 temperature = <110000>; 3824 hysteresis = <1000>; 3825 type = "critical"; 3826 }; 3827 }; 3828 3829 cooling-maps { 3830 map0 { 3831 trip = <&cpu4_bottom_alert0>; 3832 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3833 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3836 }; 3837 map1 { 3838 trip = <&cpu4_bottom_alert1>; 3839 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3840 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3841 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3843 }; 3844 }; 3845 }; 3846 3847 cpu5-bottom-thermal { 3848 polling-delay-passive = <250>; 3849 polling-delay = <1000>; 3850 3851 thermal-sensors = <&tsens0 12>; 3852 3853 trips { 3854 cpu5_bottom_alert0: trip-point0 { 3855 temperature = <90000>; 3856 hysteresis = <2000>; 3857 type = "passive"; 3858 }; 3859 3860 cpu5_bottom_alert1: trip-point1 { 3861 temperature = <95000>; 3862 hysteresis = <2000>; 3863 type = "passive"; 3864 }; 3865 3866 cpu5_bottom_crit: cpu-crit { 3867 temperature = <110000>; 3868 hysteresis = <1000>; 3869 type = "critical"; 3870 }; 3871 }; 3872 3873 cooling-maps { 3874 map0 { 3875 trip = <&cpu5_bottom_alert0>; 3876 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3877 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3880 }; 3881 map1 { 3882 trip = <&cpu5_bottom_alert1>; 3883 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3884 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3885 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3887 }; 3888 }; 3889 }; 3890 3891 cpu6-bottom-thermal { 3892 polling-delay-passive = <250>; 3893 polling-delay = <1000>; 3894 3895 thermal-sensors = <&tsens0 13>; 3896 3897 trips { 3898 cpu6_bottom_alert0: trip-point0 { 3899 temperature = <90000>; 3900 hysteresis = <2000>; 3901 type = "passive"; 3902 }; 3903 3904 cpu6_bottom_alert1: trip-point1 { 3905 temperature = <95000>; 3906 hysteresis = <2000>; 3907 type = "passive"; 3908 }; 3909 3910 cpu6_bottom_crit: cpu-crit { 3911 temperature = <110000>; 3912 hysteresis = <1000>; 3913 type = "critical"; 3914 }; 3915 }; 3916 3917 cooling-maps { 3918 map0 { 3919 trip = <&cpu6_bottom_alert0>; 3920 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3924 }; 3925 map1 { 3926 trip = <&cpu6_bottom_alert1>; 3927 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3928 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3929 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3931 }; 3932 }; 3933 }; 3934 3935 cpu7-bottom-thermal { 3936 polling-delay-passive = <250>; 3937 polling-delay = <1000>; 3938 3939 thermal-sensors = <&tsens0 14>; 3940 3941 trips { 3942 cpu7_bottom_alert0: trip-point0 { 3943 temperature = <90000>; 3944 hysteresis = <2000>; 3945 type = "passive"; 3946 }; 3947 3948 cpu7_bottom_alert1: trip-point1 { 3949 temperature = <95000>; 3950 hysteresis = <2000>; 3951 type = "passive"; 3952 }; 3953 3954 cpu7_bottom_crit: cpu-crit { 3955 temperature = <110000>; 3956 hysteresis = <1000>; 3957 type = "critical"; 3958 }; 3959 }; 3960 3961 cooling-maps { 3962 map0 { 3963 trip = <&cpu7_bottom_alert0>; 3964 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3966 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3967 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3968 }; 3969 map1 { 3970 trip = <&cpu7_bottom_alert1>; 3971 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3975 }; 3976 }; 3977 }; 3978 3979 aoss0-thermal { 3980 polling-delay-passive = <250>; 3981 polling-delay = <1000>; 3982 3983 thermal-sensors = <&tsens0 0>; 3984 3985 trips { 3986 aoss0_alert0: trip-point0 { 3987 temperature = <90000>; 3988 hysteresis = <2000>; 3989 type = "hot"; 3990 }; 3991 }; 3992 }; 3993 3994 cluster0-thermal { 3995 polling-delay-passive = <250>; 3996 polling-delay = <1000>; 3997 3998 thermal-sensors = <&tsens0 5>; 3999 4000 trips { 4001 cluster0_alert0: trip-point0 { 4002 temperature = <90000>; 4003 hysteresis = <2000>; 4004 type = "hot"; 4005 }; 4006 cluster0_crit: cluster0_crit { 4007 temperature = <110000>; 4008 hysteresis = <2000>; 4009 type = "critical"; 4010 }; 4011 }; 4012 }; 4013 4014 cluster1-thermal { 4015 polling-delay-passive = <250>; 4016 polling-delay = <1000>; 4017 4018 thermal-sensors = <&tsens0 6>; 4019 4020 trips { 4021 cluster1_alert0: trip-point0 { 4022 temperature = <90000>; 4023 hysteresis = <2000>; 4024 type = "hot"; 4025 }; 4026 cluster1_crit: cluster1_crit { 4027 temperature = <110000>; 4028 hysteresis = <2000>; 4029 type = "critical"; 4030 }; 4031 }; 4032 }; 4033 4034 aoss1-thermal { 4035 polling-delay-passive = <250>; 4036 polling-delay = <1000>; 4037 4038 thermal-sensors = <&tsens1 0>; 4039 4040 trips { 4041 aoss1_alert0: trip-point0 { 4042 temperature = <90000>; 4043 hysteresis = <2000>; 4044 type = "hot"; 4045 }; 4046 }; 4047 }; 4048 4049 gpu-top-thermal { 4050 polling-delay-passive = <250>; 4051 polling-delay = <1000>; 4052 4053 thermal-sensors = <&tsens1 1>; 4054 4055 trips { 4056 gpu1_alert0: trip-point0 { 4057 temperature = <90000>; 4058 hysteresis = <1000>; 4059 type = "hot"; 4060 }; 4061 }; 4062 }; 4063 4064 gpu-bottom-thermal { 4065 polling-delay-passive = <250>; 4066 polling-delay = <1000>; 4067 4068 thermal-sensors = <&tsens1 2>; 4069 4070 trips { 4071 gpu2_alert0: trip-point0 { 4072 temperature = <90000>; 4073 hysteresis = <1000>; 4074 type = "hot"; 4075 }; 4076 }; 4077 }; 4078 4079 nspss1-thermal { 4080 polling-delay-passive = <250>; 4081 polling-delay = <1000>; 4082 4083 thermal-sensors = <&tsens1 3>; 4084 4085 trips { 4086 nspss1_alert0: trip-point0 { 4087 temperature = <90000>; 4088 hysteresis = <1000>; 4089 type = "hot"; 4090 }; 4091 }; 4092 }; 4093 4094 nspss2-thermal { 4095 polling-delay-passive = <250>; 4096 polling-delay = <1000>; 4097 4098 thermal-sensors = <&tsens1 4>; 4099 4100 trips { 4101 nspss2_alert0: trip-point0 { 4102 temperature = <90000>; 4103 hysteresis = <1000>; 4104 type = "hot"; 4105 }; 4106 }; 4107 }; 4108 4109 nspss3-thermal { 4110 polling-delay-passive = <250>; 4111 polling-delay = <1000>; 4112 4113 thermal-sensors = <&tsens1 5>; 4114 4115 trips { 4116 nspss3_alert0: trip-point0 { 4117 temperature = <90000>; 4118 hysteresis = <1000>; 4119 type = "hot"; 4120 }; 4121 }; 4122 }; 4123 4124 video-thermal { 4125 polling-delay-passive = <250>; 4126 polling-delay = <1000>; 4127 4128 thermal-sensors = <&tsens1 6>; 4129 4130 trips { 4131 video_alert0: trip-point0 { 4132 temperature = <90000>; 4133 hysteresis = <2000>; 4134 type = "hot"; 4135 }; 4136 }; 4137 }; 4138 4139 mem-thermal { 4140 polling-delay-passive = <250>; 4141 polling-delay = <1000>; 4142 4143 thermal-sensors = <&tsens1 7>; 4144 4145 trips { 4146 mem_alert0: trip-point0 { 4147 temperature = <90000>; 4148 hysteresis = <2000>; 4149 type = "hot"; 4150 }; 4151 }; 4152 }; 4153 4154 modem1-top-thermal { 4155 polling-delay-passive = <250>; 4156 polling-delay = <1000>; 4157 4158 thermal-sensors = <&tsens1 8>; 4159 4160 trips { 4161 modem1_alert0: trip-point0 { 4162 temperature = <90000>; 4163 hysteresis = <2000>; 4164 type = "hot"; 4165 }; 4166 }; 4167 }; 4168 4169 modem2-top-thermal { 4170 polling-delay-passive = <250>; 4171 polling-delay = <1000>; 4172 4173 thermal-sensors = <&tsens1 9>; 4174 4175 trips { 4176 modem2_alert0: trip-point0 { 4177 temperature = <90000>; 4178 hysteresis = <2000>; 4179 type = "hot"; 4180 }; 4181 }; 4182 }; 4183 4184 modem3-top-thermal { 4185 polling-delay-passive = <250>; 4186 polling-delay = <1000>; 4187 4188 thermal-sensors = <&tsens1 10>; 4189 4190 trips { 4191 modem3_alert0: trip-point0 { 4192 temperature = <90000>; 4193 hysteresis = <2000>; 4194 type = "hot"; 4195 }; 4196 }; 4197 }; 4198 4199 modem4-top-thermal { 4200 polling-delay-passive = <250>; 4201 polling-delay = <1000>; 4202 4203 thermal-sensors = <&tsens1 11>; 4204 4205 trips { 4206 modem4_alert0: trip-point0 { 4207 temperature = <90000>; 4208 hysteresis = <2000>; 4209 type = "hot"; 4210 }; 4211 }; 4212 }; 4213 4214 camera-top-thermal { 4215 polling-delay-passive = <250>; 4216 polling-delay = <1000>; 4217 4218 thermal-sensors = <&tsens1 12>; 4219 4220 trips { 4221 camera1_alert0: trip-point0 { 4222 temperature = <90000>; 4223 hysteresis = <2000>; 4224 type = "hot"; 4225 }; 4226 }; 4227 }; 4228 4229 cam-bottom-thermal { 4230 polling-delay-passive = <250>; 4231 polling-delay = <1000>; 4232 4233 thermal-sensors = <&tsens1 13>; 4234 4235 trips { 4236 camera2_alert0: trip-point0 { 4237 temperature = <90000>; 4238 hysteresis = <2000>; 4239 type = "hot"; 4240 }; 4241 }; 4242 }; 4243 }; 4244 4245 timer { 4246 compatible = "arm,armv8-timer"; 4247 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4248 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4249 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4250 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4251 }; 4252}; 4253