1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/thermal/thermal.h> 20#include <dt-bindings/interconnect/qcom,sm8350.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32000>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo685"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&CPU_PD0>; 58 power-domain-names = "psci"; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo685"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 next-level-cache = <&L2_100>; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 #cooling-cells = <2>; 84 L2_100: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo685"; 95 reg = <0x0 0x200>; 96 clocks = <&cpufreq_hw 0>; 97 enable-method = "psci"; 98 next-level-cache = <&L2_200>; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 power-domains = <&CPU_PD2>; 101 power-domain-names = "psci"; 102 #cooling-cells = <2>; 103 L2_200: l2-cache { 104 compatible = "cache"; 105 cache-level = <2>; 106 cache-unified; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo685"; 114 reg = <0x0 0x300>; 115 clocks = <&cpufreq_hw 0>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_300>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 #cooling-cells = <2>; 122 L2_300: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU4: cpu@400 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo685"; 133 reg = <0x0 0x400>; 134 clocks = <&cpufreq_hw 1>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_400>; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 power-domains = <&CPU_PD4>; 139 power-domain-names = "psci"; 140 #cooling-cells = <2>; 141 L2_400: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-unified; 145 next-level-cache = <&L3_0>; 146 }; 147 }; 148 149 CPU5: cpu@500 { 150 device_type = "cpu"; 151 compatible = "qcom,kryo685"; 152 reg = <0x0 0x500>; 153 clocks = <&cpufreq_hw 1>; 154 enable-method = "psci"; 155 next-level-cache = <&L2_500>; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 power-domains = <&CPU_PD5>; 158 power-domain-names = "psci"; 159 #cooling-cells = <2>; 160 L2_500: l2-cache { 161 compatible = "cache"; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&L3_0>; 165 }; 166 }; 167 168 CPU6: cpu@600 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo685"; 171 reg = <0x0 0x600>; 172 clocks = <&cpufreq_hw 1>; 173 enable-method = "psci"; 174 next-level-cache = <&L2_600>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 power-domains = <&CPU_PD6>; 177 power-domain-names = "psci"; 178 #cooling-cells = <2>; 179 L2_600: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 next-level-cache = <&L3_0>; 184 }; 185 }; 186 187 CPU7: cpu@700 { 188 device_type = "cpu"; 189 compatible = "qcom,kryo685"; 190 reg = <0x0 0x700>; 191 clocks = <&cpufreq_hw 2>; 192 enable-method = "psci"; 193 next-level-cache = <&L2_700>; 194 qcom,freq-domain = <&cpufreq_hw 2>; 195 power-domains = <&CPU_PD7>; 196 power-domain-names = "psci"; 197 #cooling-cells = <2>; 198 L2_700: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 cpu-map { 207 cluster0 { 208 core0 { 209 cpu = <&CPU0>; 210 }; 211 212 core1 { 213 cpu = <&CPU1>; 214 }; 215 216 core2 { 217 cpu = <&CPU2>; 218 }; 219 220 core3 { 221 cpu = <&CPU3>; 222 }; 223 224 core4 { 225 cpu = <&CPU4>; 226 }; 227 228 core5 { 229 cpu = <&CPU5>; 230 }; 231 232 core6 { 233 cpu = <&CPU6>; 234 }; 235 236 core7 { 237 cpu = <&CPU7>; 238 }; 239 }; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "silver-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <355>; 250 exit-latency-us = <909>; 251 min-residency-us = <3934>; 252 local-timer-stop; 253 }; 254 255 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "gold-rail-power-collapse"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <241>; 260 exit-latency-us = <1461>; 261 min-residency-us = <4488>; 262 local-timer-stop; 263 }; 264 }; 265 266 domain-idle-states { 267 CLUSTER_SLEEP_0: cluster-sleep-0 { 268 compatible = "domain-idle-state"; 269 arm,psci-suspend-param = <0x4100c344>; 270 entry-latency-us = <3263>; 271 exit-latency-us = <6562>; 272 min-residency-us = <9987>; 273 }; 274 }; 275 }; 276 277 firmware { 278 scm: scm { 279 compatible = "qcom,scm-sm8350", "qcom,scm"; 280 #reset-cells = <1>; 281 }; 282 }; 283 284 memory@80000000 { 285 device_type = "memory"; 286 /* We expect the bootloader to fill in the size */ 287 reg = <0x0 0x80000000 0x0 0x0>; 288 }; 289 290 pmu { 291 compatible = "arm,armv8-pmuv3"; 292 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 293 }; 294 295 psci { 296 compatible = "arm,psci-1.0"; 297 method = "smc"; 298 299 CPU_PD0: power-domain-cpu0 { 300 #power-domain-cells = <0>; 301 power-domains = <&CLUSTER_PD>; 302 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 303 }; 304 305 CPU_PD1: power-domain-cpu1 { 306 #power-domain-cells = <0>; 307 power-domains = <&CLUSTER_PD>; 308 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 309 }; 310 311 CPU_PD2: power-domain-cpu2 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 315 }; 316 317 CPU_PD3: power-domain-cpu3 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 321 }; 322 323 CPU_PD4: power-domain-cpu4 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&BIG_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD5: power-domain-cpu5 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&BIG_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD6: power-domain-cpu6 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&BIG_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD7: power-domain-cpu7 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&BIG_CPU_SLEEP_0>; 345 }; 346 347 CLUSTER_PD: power-domain-cpu-cluster0 { 348 #power-domain-cells = <0>; 349 domain-idle-states = <&CLUSTER_SLEEP_0>; 350 }; 351 }; 352 353 qup_opp_table_100mhz: opp-table-qup100mhz { 354 compatible = "operating-points-v2"; 355 356 opp-50000000 { 357 opp-hz = /bits/ 64 <50000000>; 358 required-opps = <&rpmhpd_opp_min_svs>; 359 }; 360 361 opp-75000000 { 362 opp-hz = /bits/ 64 <75000000>; 363 required-opps = <&rpmhpd_opp_low_svs>; 364 }; 365 366 opp-100000000 { 367 opp-hz = /bits/ 64 <100000000>; 368 required-opps = <&rpmhpd_opp_svs>; 369 }; 370 }; 371 372 qup_opp_table_120mhz: opp-table-qup120mhz { 373 compatible = "operating-points-v2"; 374 375 opp-50000000 { 376 opp-hz = /bits/ 64 <50000000>; 377 required-opps = <&rpmhpd_opp_min_svs>; 378 }; 379 380 opp-75000000 { 381 opp-hz = /bits/ 64 <75000000>; 382 required-opps = <&rpmhpd_opp_low_svs>; 383 }; 384 385 opp-120000000 { 386 opp-hz = /bits/ 64 <120000000>; 387 required-opps = <&rpmhpd_opp_svs>; 388 }; 389 }; 390 391 reserved_memory: reserved-memory { 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 396 hyp_mem: memory@80000000 { 397 reg = <0x0 0x80000000 0x0 0x600000>; 398 no-map; 399 }; 400 401 xbl_aop_mem: memory@80700000 { 402 no-map; 403 reg = <0x0 0x80700000 0x0 0x160000>; 404 }; 405 406 cmd_db: memory@80860000 { 407 compatible = "qcom,cmd-db"; 408 reg = <0x0 0x80860000 0x0 0x20000>; 409 no-map; 410 }; 411 412 reserved_xbl_uefi_log: memory@80880000 { 413 reg = <0x0 0x80880000 0x0 0x14000>; 414 no-map; 415 }; 416 417 smem@80900000 { 418 compatible = "qcom,smem"; 419 reg = <0x0 0x80900000 0x0 0x200000>; 420 hwlocks = <&tcsr_mutex 3>; 421 no-map; 422 }; 423 424 cpucp_fw_mem: memory@80b00000 { 425 reg = <0x0 0x80b00000 0x0 0x100000>; 426 no-map; 427 }; 428 429 cdsp_secure_heap: memory@80c00000 { 430 reg = <0x0 0x80c00000 0x0 0x4600000>; 431 no-map; 432 }; 433 434 pil_camera_mem: mmeory@85200000 { 435 reg = <0x0 0x85200000 0x0 0x500000>; 436 no-map; 437 }; 438 439 pil_video_mem: memory@85700000 { 440 reg = <0x0 0x85700000 0x0 0x500000>; 441 no-map; 442 }; 443 444 pil_cvp_mem: memory@85c00000 { 445 reg = <0x0 0x85c00000 0x0 0x500000>; 446 no-map; 447 }; 448 449 pil_adsp_mem: memory@86100000 { 450 reg = <0x0 0x86100000 0x0 0x2100000>; 451 no-map; 452 }; 453 454 pil_slpi_mem: memory@88200000 { 455 reg = <0x0 0x88200000 0x0 0x1500000>; 456 no-map; 457 }; 458 459 pil_cdsp_mem: memory@89700000 { 460 reg = <0x0 0x89700000 0x0 0x1e00000>; 461 no-map; 462 }; 463 464 pil_ipa_fw_mem: memory@8b500000 { 465 reg = <0x0 0x8b500000 0x0 0x10000>; 466 no-map; 467 }; 468 469 pil_ipa_gsi_mem: memory@8b510000 { 470 reg = <0x0 0x8b510000 0x0 0xa000>; 471 no-map; 472 }; 473 474 pil_gpu_mem: memory@8b51a000 { 475 reg = <0x0 0x8b51a000 0x0 0x2000>; 476 no-map; 477 }; 478 479 pil_spss_mem: memory@8b600000 { 480 reg = <0x0 0x8b600000 0x0 0x100000>; 481 no-map; 482 }; 483 484 pil_modem_mem: memory@8b800000 { 485 reg = <0x0 0x8b800000 0x0 0x10000000>; 486 no-map; 487 }; 488 489 rmtfs_mem: memory@9b800000 { 490 compatible = "qcom,rmtfs-mem"; 491 reg = <0x0 0x9b800000 0x0 0x280000>; 492 no-map; 493 494 qcom,client-id = <1>; 495 qcom,vmid = <15>; 496 }; 497 498 hyp_reserved_mem: memory@d0000000 { 499 reg = <0x0 0xd0000000 0x0 0x800000>; 500 no-map; 501 }; 502 503 pil_trustedvm_mem: memory@d0800000 { 504 reg = <0x0 0xd0800000 0x0 0x76f7000>; 505 no-map; 506 }; 507 508 qrtr_shbuf: memory@d7ef7000 { 509 reg = <0x0 0xd7ef7000 0x0 0x9000>; 510 no-map; 511 }; 512 513 chan0_shbuf: memory@d7f00000 { 514 reg = <0x0 0xd7f00000 0x0 0x80000>; 515 no-map; 516 }; 517 518 chan1_shbuf: memory@d7f80000 { 519 reg = <0x0 0xd7f80000 0x0 0x80000>; 520 no-map; 521 }; 522 523 removed_mem: memory@d8800000 { 524 reg = <0x0 0xd8800000 0x0 0x6800000>; 525 no-map; 526 }; 527 }; 528 529 smp2p-adsp { 530 compatible = "qcom,smp2p"; 531 qcom,smem = <443>, <429>; 532 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 533 IPCC_MPROC_SIGNAL_SMP2P 534 IRQ_TYPE_EDGE_RISING>; 535 mboxes = <&ipcc IPCC_CLIENT_LPASS 536 IPCC_MPROC_SIGNAL_SMP2P>; 537 538 qcom,local-pid = <0>; 539 qcom,remote-pid = <2>; 540 541 smp2p_adsp_out: master-kernel { 542 qcom,entry-name = "master-kernel"; 543 #qcom,smem-state-cells = <1>; 544 }; 545 546 smp2p_adsp_in: slave-kernel { 547 qcom,entry-name = "slave-kernel"; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 }; 552 553 smp2p-cdsp { 554 compatible = "qcom,smp2p"; 555 qcom,smem = <94>, <432>; 556 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 557 IPCC_MPROC_SIGNAL_SMP2P 558 IRQ_TYPE_EDGE_RISING>; 559 mboxes = <&ipcc IPCC_CLIENT_CDSP 560 IPCC_MPROC_SIGNAL_SMP2P>; 561 562 qcom,local-pid = <0>; 563 qcom,remote-pid = <5>; 564 565 smp2p_cdsp_out: master-kernel { 566 qcom,entry-name = "master-kernel"; 567 #qcom,smem-state-cells = <1>; 568 }; 569 570 smp2p_cdsp_in: slave-kernel { 571 qcom,entry-name = "slave-kernel"; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 }; 576 577 smp2p-modem { 578 compatible = "qcom,smp2p"; 579 qcom,smem = <435>, <428>; 580 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 581 IPCC_MPROC_SIGNAL_SMP2P 582 IRQ_TYPE_EDGE_RISING>; 583 mboxes = <&ipcc IPCC_CLIENT_MPSS 584 IPCC_MPROC_SIGNAL_SMP2P>; 585 586 qcom,local-pid = <0>; 587 qcom,remote-pid = <1>; 588 589 smp2p_modem_out: master-kernel { 590 qcom,entry-name = "master-kernel"; 591 #qcom,smem-state-cells = <1>; 592 }; 593 594 smp2p_modem_in: slave-kernel { 595 qcom,entry-name = "slave-kernel"; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 600 ipa_smp2p_out: ipa-ap-to-modem { 601 qcom,entry-name = "ipa"; 602 #qcom,smem-state-cells = <1>; 603 }; 604 605 ipa_smp2p_in: ipa-modem-to-ap { 606 qcom,entry-name = "ipa"; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 }; 611 612 smp2p-slpi { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <481>, <430>; 615 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 616 IPCC_MPROC_SIGNAL_SMP2P 617 IRQ_TYPE_EDGE_RISING>; 618 mboxes = <&ipcc IPCC_CLIENT_SLPI 619 IPCC_MPROC_SIGNAL_SMP2P>; 620 621 qcom,local-pid = <0>; 622 qcom,remote-pid = <3>; 623 624 smp2p_slpi_out: master-kernel { 625 qcom,entry-name = "master-kernel"; 626 #qcom,smem-state-cells = <1>; 627 }; 628 629 smp2p_slpi_in: slave-kernel { 630 qcom,entry-name = "slave-kernel"; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 soc: soc@0 { 637 #address-cells = <2>; 638 #size-cells = <2>; 639 ranges = <0 0 0 0 0x10 0>; 640 dma-ranges = <0 0 0 0 0x10 0>; 641 compatible = "simple-bus"; 642 643 gcc: clock-controller@100000 { 644 compatible = "qcom,gcc-sm8350"; 645 reg = <0x0 0x00100000 0x0 0x1f0000>; 646 #clock-cells = <1>; 647 #reset-cells = <1>; 648 #power-domain-cells = <1>; 649 clock-names = "bi_tcxo", 650 "sleep_clk", 651 "pcie_0_pipe_clk", 652 "pcie_1_pipe_clk", 653 "ufs_card_rx_symbol_0_clk", 654 "ufs_card_rx_symbol_1_clk", 655 "ufs_card_tx_symbol_0_clk", 656 "ufs_phy_rx_symbol_0_clk", 657 "ufs_phy_rx_symbol_1_clk", 658 "ufs_phy_tx_symbol_0_clk", 659 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 660 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 661 clocks = <&rpmhcc RPMH_CXO_CLK>, 662 <&sleep_clk>, 663 <&pcie0_phy>, 664 <&pcie1_phy>, 665 <0>, 666 <0>, 667 <0>, 668 <&ufs_mem_phy_lanes 0>, 669 <&ufs_mem_phy_lanes 1>, 670 <&ufs_mem_phy_lanes 2>, 671 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 672 <0>; 673 }; 674 675 ipcc: mailbox@408000 { 676 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 677 reg = <0 0x00408000 0 0x1000>; 678 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-controller; 680 #interrupt-cells = <3>; 681 #mbox-cells = <2>; 682 }; 683 684 gpi_dma2: dma-controller@800000 { 685 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 686 reg = <0 0x00800000 0 0x60000>; 687 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 699 dma-channels = <12>; 700 dma-channel-mask = <0xff>; 701 iommus = <&apps_smmu 0x5f6 0x0>; 702 #dma-cells = <3>; 703 status = "disabled"; 704 }; 705 706 qupv3_id_2: geniqup@8c0000 { 707 compatible = "qcom,geni-se-qup"; 708 reg = <0x0 0x008c0000 0x0 0x6000>; 709 clock-names = "m-ahb", "s-ahb"; 710 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 711 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 712 iommus = <&apps_smmu 0x5e3 0x0>; 713 #address-cells = <2>; 714 #size-cells = <2>; 715 ranges; 716 status = "disabled"; 717 718 i2c14: i2c@880000 { 719 compatible = "qcom,geni-i2c"; 720 reg = <0 0x00880000 0 0x4000>; 721 clock-names = "se"; 722 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&qup_i2c14_default>; 725 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 726 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 727 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 728 dma-names = "tx", "rx"; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 spi14: spi@880000 { 735 compatible = "qcom,geni-spi"; 736 reg = <0 0x00880000 0 0x4000>; 737 clock-names = "se"; 738 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 739 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 740 power-domains = <&rpmhpd SM8350_CX>; 741 operating-points-v2 = <&qup_opp_table_120mhz>; 742 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 743 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 744 dma-names = "tx", "rx"; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 i2c15: i2c@884000 { 751 compatible = "qcom,geni-i2c"; 752 reg = <0 0x00884000 0 0x4000>; 753 clock-names = "se"; 754 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&qup_i2c15_default>; 757 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 758 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 759 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 760 dma-names = "tx", "rx"; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 spi15: spi@884000 { 767 compatible = "qcom,geni-spi"; 768 reg = <0 0x00884000 0 0x4000>; 769 clock-names = "se"; 770 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 771 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 772 power-domains = <&rpmhpd SM8350_CX>; 773 operating-points-v2 = <&qup_opp_table_120mhz>; 774 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 775 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 776 dma-names = "tx", "rx"; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 status = "disabled"; 780 }; 781 782 i2c16: i2c@888000 { 783 compatible = "qcom,geni-i2c"; 784 reg = <0 0x00888000 0 0x4000>; 785 clock-names = "se"; 786 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&qup_i2c16_default>; 789 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 790 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 791 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 792 dma-names = "tx", "rx"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 status = "disabled"; 796 }; 797 798 spi16: spi@888000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0 0x00888000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 803 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 804 power-domains = <&rpmhpd SM8350_CX>; 805 operating-points-v2 = <&qup_opp_table_100mhz>; 806 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 807 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 808 dma-names = "tx", "rx"; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 status = "disabled"; 812 }; 813 814 i2c17: i2c@88c000 { 815 compatible = "qcom,geni-i2c"; 816 reg = <0 0x0088c000 0 0x4000>; 817 clock-names = "se"; 818 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&qup_i2c17_default>; 821 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 822 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 823 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 824 dma-names = "tx", "rx"; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 status = "disabled"; 828 }; 829 830 spi17: spi@88c000 { 831 compatible = "qcom,geni-spi"; 832 reg = <0 0x0088c000 0 0x4000>; 833 clock-names = "se"; 834 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 835 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 836 power-domains = <&rpmhpd SM8350_CX>; 837 operating-points-v2 = <&qup_opp_table_100mhz>; 838 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 839 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 840 dma-names = "tx", "rx"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 status = "disabled"; 844 }; 845 846 /* QUP no. 18 seems to be strictly SPI/UART-only */ 847 848 spi18: spi@890000 { 849 compatible = "qcom,geni-spi"; 850 reg = <0 0x00890000 0 0x4000>; 851 clock-names = "se"; 852 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 853 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 854 power-domains = <&rpmhpd SM8350_CX>; 855 operating-points-v2 = <&qup_opp_table_100mhz>; 856 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 857 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 858 dma-names = "tx", "rx"; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 uart18: serial@890000 { 865 compatible = "qcom,geni-uart"; 866 reg = <0 0x00890000 0 0x4000>; 867 clock-names = "se"; 868 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&qup_uart18_default>; 871 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 872 power-domains = <&rpmhpd SM8350_CX>; 873 operating-points-v2 = <&qup_opp_table_100mhz>; 874 status = "disabled"; 875 }; 876 877 i2c19: i2c@894000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0 0x00894000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_i2c19_default>; 884 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 885 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 886 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 887 dma-names = "tx", "rx"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 status = "disabled"; 891 }; 892 893 spi19: spi@894000 { 894 compatible = "qcom,geni-spi"; 895 reg = <0 0x00894000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 898 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 899 power-domains = <&rpmhpd SM8350_CX>; 900 operating-points-v2 = <&qup_opp_table_100mhz>; 901 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 902 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 903 dma-names = "tx", "rx"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 status = "disabled"; 907 }; 908 }; 909 910 gpi_dma0: dma-controller@900000 { 911 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 912 reg = <0 0x09800000 0 0x60000>; 913 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 925 dma-channels = <12>; 926 dma-channel-mask = <0x7e>; 927 iommus = <&apps_smmu 0x5b6 0x0>; 928 #dma-cells = <3>; 929 status = "disabled"; 930 }; 931 932 qupv3_id_0: geniqup@9c0000 { 933 compatible = "qcom,geni-se-qup"; 934 reg = <0x0 0x009c0000 0x0 0x6000>; 935 clock-names = "m-ahb", "s-ahb"; 936 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 937 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 938 iommus = <&apps_smmu 0x5a3 0>; 939 #address-cells = <2>; 940 #size-cells = <2>; 941 ranges; 942 status = "disabled"; 943 944 i2c0: i2c@980000 { 945 compatible = "qcom,geni-i2c"; 946 reg = <0 0x00980000 0 0x4000>; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_i2c0_default>; 951 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 952 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 953 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 954 dma-names = "tx", "rx"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 status = "disabled"; 958 }; 959 960 spi0: spi@980000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00980000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 965 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 966 power-domains = <&rpmhpd SM8350_CX>; 967 operating-points-v2 = <&qup_opp_table_100mhz>; 968 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 969 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 970 dma-names = "tx", "rx"; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 status = "disabled"; 974 }; 975 976 i2c1: i2c@984000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00984000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c1_default>; 983 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 984 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 985 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 spi1: spi@984000 { 993 compatible = "qcom,geni-spi"; 994 reg = <0 0x00984000 0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 997 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 998 power-domains = <&rpmhpd SM8350_CX>; 999 operating-points-v2 = <&qup_opp_table_100mhz>; 1000 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1001 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1002 dma-names = "tx", "rx"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 i2c2: i2c@988000 { 1009 compatible = "qcom,geni-i2c"; 1010 reg = <0 0x00988000 0 0x4000>; 1011 clock-names = "se"; 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_i2c2_default>; 1015 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1016 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1017 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1018 dma-names = "tx", "rx"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 spi2: spi@988000 { 1025 compatible = "qcom,geni-spi"; 1026 reg = <0 0x00988000 0 0x4000>; 1027 clock-names = "se"; 1028 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1029 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1030 power-domains = <&rpmhpd SM8350_CX>; 1031 operating-points-v2 = <&qup_opp_table_100mhz>; 1032 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1033 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1034 dma-names = "tx", "rx"; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 uart2: serial@98c000 { 1041 compatible = "qcom,geni-debug-uart"; 1042 reg = <0 0x0098c000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_uart3_default_state>; 1047 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1048 power-domains = <&rpmhpd SM8350_CX>; 1049 operating-points-v2 = <&qup_opp_table_100mhz>; 1050 status = "disabled"; 1051 }; 1052 1053 /* QUP no. 3 seems to be strictly SPI-only */ 1054 1055 spi3: spi@98c000 { 1056 compatible = "qcom,geni-spi"; 1057 reg = <0 0x0098c000 0 0x4000>; 1058 clock-names = "se"; 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1060 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd SM8350_CX>; 1062 operating-points-v2 = <&qup_opp_table_100mhz>; 1063 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1064 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1065 dma-names = "tx", "rx"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 i2c4: i2c@990000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x00990000 0 0x4000>; 1074 clock-names = "se"; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_i2c4_default>; 1078 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1079 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1080 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1081 dma-names = "tx", "rx"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 spi4: spi@990000 { 1088 compatible = "qcom,geni-spi"; 1089 reg = <0 0x00990000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1092 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&rpmhpd SM8350_CX>; 1094 operating-points-v2 = <&qup_opp_table_100mhz>; 1095 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1096 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1097 dma-names = "tx", "rx"; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 i2c5: i2c@994000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0 0x00994000 0 0x4000>; 1106 clock-names = "se"; 1107 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_i2c5_default>; 1110 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1111 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1112 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1113 dma-names = "tx", "rx"; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "disabled"; 1117 }; 1118 1119 spi5: spi@994000 { 1120 compatible = "qcom,geni-spi"; 1121 reg = <0 0x00994000 0 0x4000>; 1122 clock-names = "se"; 1123 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1124 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SM8350_CX>; 1126 operating-points-v2 = <&qup_opp_table_100mhz>; 1127 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1128 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1129 dma-names = "tx", "rx"; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 status = "disabled"; 1133 }; 1134 1135 i2c6: i2c@998000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0 0x00998000 0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_i2c6_default>; 1142 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1143 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1144 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1145 dma-names = "tx", "rx"; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 status = "disabled"; 1149 }; 1150 1151 spi6: spi@998000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0 0x00998000 0 0x4000>; 1154 clock-names = "se"; 1155 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1156 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1157 power-domains = <&rpmhpd SM8350_CX>; 1158 operating-points-v2 = <&qup_opp_table_100mhz>; 1159 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1160 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1161 dma-names = "tx", "rx"; 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 status = "disabled"; 1165 }; 1166 1167 uart6: serial@998000 { 1168 compatible = "qcom,geni-uart"; 1169 reg = <0 0x00998000 0 0x4000>; 1170 clock-names = "se"; 1171 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_uart6_default>; 1174 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1175 power-domains = <&rpmhpd SM8350_CX>; 1176 operating-points-v2 = <&qup_opp_table_100mhz>; 1177 status = "disabled"; 1178 }; 1179 1180 i2c7: i2c@99c000 { 1181 compatible = "qcom,geni-i2c"; 1182 reg = <0 0x0099c000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&qup_i2c7_default>; 1187 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1188 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 status = "disabled"; 1194 }; 1195 1196 spi7: spi@99c000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x0099c000 0 0x4000>; 1199 clock-names = "se"; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1201 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1202 power-domains = <&rpmhpd SM8350_CX>; 1203 operating-points-v2 = <&qup_opp_table_100mhz>; 1204 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1205 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1206 dma-names = "tx", "rx"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 }; 1212 1213 gpi_dma1: dma-controller@a00000 { 1214 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1215 reg = <0 0x00a00000 0 0x60000>; 1216 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1228 dma-channels = <12>; 1229 dma-channel-mask = <0xff>; 1230 iommus = <&apps_smmu 0x56 0x0>; 1231 #dma-cells = <3>; 1232 status = "disabled"; 1233 }; 1234 1235 qupv3_id_1: geniqup@ac0000 { 1236 compatible = "qcom,geni-se-qup"; 1237 reg = <0x0 0x00ac0000 0x0 0x6000>; 1238 clock-names = "m-ahb", "s-ahb"; 1239 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1240 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1241 iommus = <&apps_smmu 0x43 0>; 1242 #address-cells = <2>; 1243 #size-cells = <2>; 1244 ranges; 1245 status = "disabled"; 1246 1247 i2c8: i2c@a80000 { 1248 compatible = "qcom,geni-i2c"; 1249 reg = <0 0x00a80000 0 0x4000>; 1250 clock-names = "se"; 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&qup_i2c8_default>; 1254 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1255 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1256 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1257 dma-names = "tx", "rx"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 spi8: spi@a80000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0 0x00a80000 0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1268 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1269 power-domains = <&rpmhpd SM8350_CX>; 1270 operating-points-v2 = <&qup_opp_table_120mhz>; 1271 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1272 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1273 dma-names = "tx", "rx"; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 i2c9: i2c@a84000 { 1280 compatible = "qcom,geni-i2c"; 1281 reg = <0 0x00a84000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_i2c9_default>; 1286 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1287 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1288 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1289 dma-names = "tx", "rx"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 spi9: spi@a84000 { 1296 compatible = "qcom,geni-spi"; 1297 reg = <0 0x00a84000 0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1300 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1301 power-domains = <&rpmhpd SM8350_CX>; 1302 operating-points-v2 = <&qup_opp_table_100mhz>; 1303 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1304 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1305 dma-names = "tx", "rx"; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 i2c10: i2c@a88000 { 1312 compatible = "qcom,geni-i2c"; 1313 reg = <0 0x00a88000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_i2c10_default>; 1318 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1319 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1320 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1321 dma-names = "tx", "rx"; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 1327 spi10: spi@a88000 { 1328 compatible = "qcom,geni-spi"; 1329 reg = <0 0x00a88000 0 0x4000>; 1330 clock-names = "se"; 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1332 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1333 power-domains = <&rpmhpd SM8350_CX>; 1334 operating-points-v2 = <&qup_opp_table_100mhz>; 1335 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1336 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1337 dma-names = "tx", "rx"; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 i2c11: i2c@a8c000 { 1344 compatible = "qcom,geni-i2c"; 1345 reg = <0 0x00a8c000 0 0x4000>; 1346 clock-names = "se"; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_i2c11_default>; 1350 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1351 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1352 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1353 dma-names = "tx", "rx"; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 1359 spi11: spi@a8c000 { 1360 compatible = "qcom,geni-spi"; 1361 reg = <0 0x00a8c000 0 0x4000>; 1362 clock-names = "se"; 1363 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1364 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1365 power-domains = <&rpmhpd SM8350_CX>; 1366 operating-points-v2 = <&qup_opp_table_100mhz>; 1367 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1368 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1369 dma-names = "tx", "rx"; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 status = "disabled"; 1373 }; 1374 1375 i2c12: i2c@a90000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0 0x00a90000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_i2c12_default>; 1382 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1383 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1384 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1385 dma-names = "tx", "rx"; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 spi12: spi@a90000 { 1392 compatible = "qcom,geni-spi"; 1393 reg = <0 0x00a90000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1396 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1397 power-domains = <&rpmhpd SM8350_CX>; 1398 operating-points-v2 = <&qup_opp_table_100mhz>; 1399 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1400 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1401 dma-names = "tx", "rx"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 i2c13: i2c@a94000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00a94000 0 0x4000>; 1410 clock-names = "se"; 1411 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c13_default>; 1414 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1415 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1416 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1417 dma-names = "tx", "rx"; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 spi13: spi@a94000 { 1424 compatible = "qcom,geni-spi"; 1425 reg = <0 0x00a94000 0 0x4000>; 1426 clock-names = "se"; 1427 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1428 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1429 power-domains = <&rpmhpd SM8350_CX>; 1430 operating-points-v2 = <&qup_opp_table_100mhz>; 1431 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1432 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 status = "disabled"; 1437 }; 1438 }; 1439 1440 rng: rng@10d3000 { 1441 compatible = "qcom,prng-ee"; 1442 reg = <0 0x010d3000 0 0x1000>; 1443 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1444 clock-names = "core"; 1445 }; 1446 1447 config_noc: interconnect@1500000 { 1448 compatible = "qcom,sm8350-config-noc"; 1449 reg = <0 0x01500000 0 0xa580>; 1450 #interconnect-cells = <2>; 1451 qcom,bcm-voters = <&apps_bcm_voter>; 1452 }; 1453 1454 mc_virt: interconnect@1580000 { 1455 compatible = "qcom,sm8350-mc-virt"; 1456 reg = <0 0x01580000 0 0x1000>; 1457 #interconnect-cells = <2>; 1458 qcom,bcm-voters = <&apps_bcm_voter>; 1459 }; 1460 1461 system_noc: interconnect@1680000 { 1462 compatible = "qcom,sm8350-system-noc"; 1463 reg = <0 0x01680000 0 0x1c200>; 1464 #interconnect-cells = <2>; 1465 qcom,bcm-voters = <&apps_bcm_voter>; 1466 }; 1467 1468 aggre1_noc: interconnect@16e0000 { 1469 compatible = "qcom,sm8350-aggre1-noc"; 1470 reg = <0 0x016e0000 0 0x1f180>; 1471 #interconnect-cells = <2>; 1472 qcom,bcm-voters = <&apps_bcm_voter>; 1473 }; 1474 1475 aggre2_noc: interconnect@1700000 { 1476 compatible = "qcom,sm8350-aggre2-noc"; 1477 reg = <0 0x01700000 0 0x33000>; 1478 #interconnect-cells = <2>; 1479 qcom,bcm-voters = <&apps_bcm_voter>; 1480 }; 1481 1482 mmss_noc: interconnect@1740000 { 1483 compatible = "qcom,sm8350-mmss-noc"; 1484 reg = <0 0x01740000 0 0x1f080>; 1485 #interconnect-cells = <2>; 1486 qcom,bcm-voters = <&apps_bcm_voter>; 1487 }; 1488 1489 pcie0: pci@1c00000 { 1490 compatible = "qcom,pcie-sm8350"; 1491 reg = <0 0x01c00000 0 0x3000>, 1492 <0 0x60000000 0 0xf1d>, 1493 <0 0x60000f20 0 0xa8>, 1494 <0 0x60001000 0 0x1000>, 1495 <0 0x60100000 0 0x100000>; 1496 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1497 device_type = "pci"; 1498 linux,pci-domain = <0>; 1499 bus-range = <0x00 0xff>; 1500 num-lanes = <1>; 1501 1502 #address-cells = <3>; 1503 #size-cells = <2>; 1504 1505 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1506 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1507 1508 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1516 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1517 "msi4", "msi5", "msi6", "msi7"; 1518 #interrupt-cells = <1>; 1519 interrupt-map-mask = <0 0 0 0x7>; 1520 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1521 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1522 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1523 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1524 1525 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1526 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1527 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1528 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1529 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1530 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1531 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1532 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1533 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1534 clock-names = "aux", 1535 "cfg", 1536 "bus_master", 1537 "bus_slave", 1538 "slave_q2a", 1539 "tbu", 1540 "ddrss_sf_tbu", 1541 "aggre1", 1542 "aggre0"; 1543 1544 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1545 <0x100 &apps_smmu 0x1c01 0x1>; 1546 1547 resets = <&gcc GCC_PCIE_0_BCR>; 1548 reset-names = "pci"; 1549 1550 power-domains = <&gcc PCIE_0_GDSC>; 1551 1552 phys = <&pcie0_phy>; 1553 phy-names = "pciephy"; 1554 1555 status = "disabled"; 1556 }; 1557 1558 pcie0_phy: phy@1c06000 { 1559 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1560 reg = <0 0x01c06000 0 0x2000>; 1561 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1562 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1563 <&gcc GCC_PCIE_0_CLKREF_EN>, 1564 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1565 <&gcc GCC_PCIE_0_PIPE_CLK>; 1566 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1567 1568 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1569 reset-names = "phy"; 1570 1571 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1572 assigned-clock-rates = <100000000>; 1573 1574 #clock-cells = <0>; 1575 clock-output-names = "pcie_0_pipe_clk"; 1576 1577 #phy-cells = <0>; 1578 1579 status = "disabled"; 1580 }; 1581 1582 pcie1: pci@1c08000 { 1583 compatible = "qcom,pcie-sm8350"; 1584 reg = <0 0x01c08000 0 0x3000>, 1585 <0 0x40000000 0 0xf1d>, 1586 <0 0x40000f20 0 0xa8>, 1587 <0 0x40001000 0 0x1000>, 1588 <0 0x40100000 0 0x100000>; 1589 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1590 device_type = "pci"; 1591 linux,pci-domain = <1>; 1592 bus-range = <0x00 0xff>; 1593 num-lanes = <2>; 1594 1595 #address-cells = <3>; 1596 #size-cells = <2>; 1597 1598 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1599 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1600 1601 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1602 interrupt-names = "msi"; 1603 #interrupt-cells = <1>; 1604 interrupt-map-mask = <0 0 0 0x7>; 1605 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1606 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1607 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1608 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1609 1610 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1611 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1612 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1613 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1614 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1615 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1616 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1617 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1618 clock-names = "aux", 1619 "cfg", 1620 "bus_master", 1621 "bus_slave", 1622 "slave_q2a", 1623 "tbu", 1624 "ddrss_sf_tbu", 1625 "aggre1"; 1626 1627 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1628 <0x100 &apps_smmu 0x1c81 0x1>; 1629 1630 resets = <&gcc GCC_PCIE_1_BCR>; 1631 reset-names = "pci"; 1632 1633 power-domains = <&gcc PCIE_1_GDSC>; 1634 1635 phys = <&pcie1_phy>; 1636 phy-names = "pciephy"; 1637 1638 status = "disabled"; 1639 }; 1640 1641 pcie1_phy: phy@1c0f000 { 1642 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1643 reg = <0 0x01c0e000 0 0x2000>; 1644 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1645 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1646 <&gcc GCC_PCIE_1_CLKREF_EN>, 1647 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1648 <&gcc GCC_PCIE_1_PIPE_CLK>; 1649 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1650 1651 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1652 reset-names = "phy"; 1653 1654 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1655 assigned-clock-rates = <100000000>; 1656 1657 #clock-cells = <0>; 1658 clock-output-names = "pcie_1_pipe_clk"; 1659 1660 #phy-cells = <0>; 1661 1662 status = "disabled"; 1663 }; 1664 1665 ufs_mem_hc: ufshc@1d84000 { 1666 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1667 "jedec,ufs-2.0"; 1668 reg = <0 0x01d84000 0 0x3000>; 1669 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1670 phys = <&ufs_mem_phy_lanes>; 1671 phy-names = "ufsphy"; 1672 lanes-per-direction = <2>; 1673 #reset-cells = <1>; 1674 resets = <&gcc GCC_UFS_PHY_BCR>; 1675 reset-names = "rst"; 1676 1677 power-domains = <&gcc UFS_PHY_GDSC>; 1678 1679 iommus = <&apps_smmu 0xe0 0x0>; 1680 dma-coherent; 1681 1682 clock-names = 1683 "core_clk", 1684 "bus_aggr_clk", 1685 "iface_clk", 1686 "core_clk_unipro", 1687 "ref_clk", 1688 "tx_lane0_sync_clk", 1689 "rx_lane0_sync_clk", 1690 "rx_lane1_sync_clk"; 1691 clocks = 1692 <&gcc GCC_UFS_PHY_AXI_CLK>, 1693 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1694 <&gcc GCC_UFS_PHY_AHB_CLK>, 1695 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1696 <&rpmhcc RPMH_CXO_CLK>, 1697 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1698 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1699 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1700 freq-table-hz = 1701 <75000000 300000000>, 1702 <0 0>, 1703 <0 0>, 1704 <75000000 300000000>, 1705 <0 0>, 1706 <0 0>, 1707 <0 0>, 1708 <0 0>; 1709 status = "disabled"; 1710 }; 1711 1712 ufs_mem_phy: phy@1d87000 { 1713 compatible = "qcom,sm8350-qmp-ufs-phy"; 1714 reg = <0 0x01d87000 0 0x1c4>; 1715 #address-cells = <2>; 1716 #size-cells = <2>; 1717 ranges; 1718 clock-names = "ref", 1719 "ref_aux"; 1720 clocks = <&rpmhcc RPMH_CXO_CLK>, 1721 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1722 1723 resets = <&ufs_mem_hc 0>; 1724 reset-names = "ufsphy"; 1725 status = "disabled"; 1726 1727 ufs_mem_phy_lanes: phy@1d87400 { 1728 reg = <0 0x01d87400 0 0x188>, 1729 <0 0x01d87600 0 0x200>, 1730 <0 0x01d87c00 0 0x200>, 1731 <0 0x01d87800 0 0x188>, 1732 <0 0x01d87a00 0 0x200>; 1733 #clock-cells = <1>; 1734 #phy-cells = <0>; 1735 }; 1736 }; 1737 1738 ipa: ipa@1e40000 { 1739 compatible = "qcom,sm8350-ipa"; 1740 1741 iommus = <&apps_smmu 0x5c0 0x0>, 1742 <&apps_smmu 0x5c2 0x0>; 1743 reg = <0 0x01e40000 0 0x8000>, 1744 <0 0x01e50000 0 0x4b20>, 1745 <0 0x01e04000 0 0x23000>; 1746 reg-names = "ipa-reg", 1747 "ipa-shared", 1748 "gsi"; 1749 1750 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1751 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1752 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1753 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1754 interrupt-names = "ipa", 1755 "gsi", 1756 "ipa-clock-query", 1757 "ipa-setup-ready"; 1758 1759 clocks = <&rpmhcc RPMH_IPA_CLK>; 1760 clock-names = "core"; 1761 1762 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1763 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1764 interconnect-names = "memory", 1765 "config"; 1766 1767 qcom,qmp = <&aoss_qmp>; 1768 1769 qcom,smem-states = <&ipa_smp2p_out 0>, 1770 <&ipa_smp2p_out 1>; 1771 qcom,smem-state-names = "ipa-clock-enabled-valid", 1772 "ipa-clock-enabled"; 1773 1774 status = "disabled"; 1775 }; 1776 1777 tcsr_mutex: hwlock@1f40000 { 1778 compatible = "qcom,tcsr-mutex"; 1779 reg = <0x0 0x01f40000 0x0 0x40000>; 1780 #hwlock-cells = <1>; 1781 }; 1782 1783 gpu: gpu@3d00000 { 1784 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1785 1786 reg = <0 0x03d00000 0 0x40000>, 1787 <0 0x03d9e000 0 0x1000>, 1788 <0 0x03d61000 0 0x800>; 1789 reg-names = "kgsl_3d0_reg_memory", 1790 "cx_mem", 1791 "cx_dbgc"; 1792 1793 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1794 1795 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1796 1797 operating-points-v2 = <&gpu_opp_table>; 1798 1799 qcom,gmu = <&gmu>; 1800 1801 status = "disabled"; 1802 1803 zap-shader { 1804 memory-region = <&pil_gpu_mem>; 1805 }; 1806 1807 /* note: downstream checks gpu binning for 670 Mhz */ 1808 gpu_opp_table: opp-table { 1809 compatible = "operating-points-v2"; 1810 1811 opp-840000000 { 1812 opp-hz = /bits/ 64 <840000000>; 1813 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1814 }; 1815 1816 opp-778000000 { 1817 opp-hz = /bits/ 64 <778000000>; 1818 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1819 }; 1820 1821 opp-738000000 { 1822 opp-hz = /bits/ 64 <738000000>; 1823 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1824 }; 1825 1826 opp-676000000 { 1827 opp-hz = /bits/ 64 <676000000>; 1828 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1829 }; 1830 1831 opp-608000000 { 1832 opp-hz = /bits/ 64 <608000000>; 1833 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1834 }; 1835 1836 opp-540000000 { 1837 opp-hz = /bits/ 64 <540000000>; 1838 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1839 }; 1840 1841 opp-491000000 { 1842 opp-hz = /bits/ 64 <491000000>; 1843 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1844 }; 1845 1846 opp-443000000 { 1847 opp-hz = /bits/ 64 <443000000>; 1848 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1849 }; 1850 1851 opp-379000000 { 1852 opp-hz = /bits/ 64 <379000000>; 1853 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1854 }; 1855 1856 opp-315000000 { 1857 opp-hz = /bits/ 64 <315000000>; 1858 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1859 }; 1860 }; 1861 }; 1862 1863 gmu: gmu@3d6a000 { 1864 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1865 1866 reg = <0 0x03d6a000 0 0x34000>, 1867 <0 0x03de0000 0 0x10000>, 1868 <0 0x0b290000 0 0x10000>; 1869 reg-names = "gmu", "rscc", "gmu_pdc"; 1870 1871 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1873 interrupt-names = "hfi", "gmu"; 1874 1875 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1876 <&gpucc GPU_CC_CXO_CLK>, 1877 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1878 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1879 <&gpucc GPU_CC_AHB_CLK>, 1880 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1881 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1882 clock-names = "gmu", 1883 "cxo", 1884 "axi", 1885 "memnoc", 1886 "ahb", 1887 "hub", 1888 "smmu_vote"; 1889 1890 power-domains = <&gpucc GPU_CX_GDSC>, 1891 <&gpucc GPU_GX_GDSC>; 1892 power-domain-names = "cx", 1893 "gx"; 1894 1895 iommus = <&adreno_smmu 5 0x400>; 1896 1897 operating-points-v2 = <&gmu_opp_table>; 1898 1899 gmu_opp_table: opp-table { 1900 compatible = "operating-points-v2"; 1901 1902 opp-200000000 { 1903 opp-hz = /bits/ 64 <200000000>; 1904 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1905 }; 1906 }; 1907 }; 1908 1909 gpucc: clock-controller@3d90000 { 1910 compatible = "qcom,sm8350-gpucc"; 1911 reg = <0 0x03d90000 0 0x9000>; 1912 clocks = <&rpmhcc RPMH_CXO_CLK>, 1913 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1914 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1915 clock-names = "bi_tcxo", 1916 "gcc_gpu_gpll0_clk_src", 1917 "gcc_gpu_gpll0_div_clk_src"; 1918 #clock-cells = <1>; 1919 #reset-cells = <1>; 1920 #power-domain-cells = <1>; 1921 }; 1922 1923 adreno_smmu: iommu@3da0000 { 1924 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1925 "qcom,smmu-500", "arm,mmu-500"; 1926 reg = <0 0x03da0000 0 0x20000>; 1927 #iommu-cells = <2>; 1928 #global-interrupts = <2>; 1929 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1941 1942 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1943 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1944 <&gpucc GPU_CC_AHB_CLK>, 1945 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1946 <&gpucc GPU_CC_CX_GMU_CLK>, 1947 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1948 <&gpucc GPU_CC_HUB_AON_CLK>; 1949 clock-names = "bus", 1950 "iface", 1951 "ahb", 1952 "hlos1_vote_gpu_smmu", 1953 "cx_gmu", 1954 "hub_cx_int", 1955 "hub_aon"; 1956 1957 power-domains = <&gpucc GPU_CX_GDSC>; 1958 dma-coherent; 1959 }; 1960 1961 lpass_ag_noc: interconnect@3c40000 { 1962 compatible = "qcom,sm8350-lpass-ag-noc"; 1963 reg = <0 0x03c40000 0 0xf080>; 1964 #interconnect-cells = <2>; 1965 qcom,bcm-voters = <&apps_bcm_voter>; 1966 }; 1967 1968 mpss: remoteproc@4080000 { 1969 compatible = "qcom,sm8350-mpss-pas"; 1970 reg = <0x0 0x04080000 0x0 0x4040>; 1971 1972 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1973 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1974 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1975 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1976 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1977 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1978 interrupt-names = "wdog", "fatal", "ready", "handover", 1979 "stop-ack", "shutdown-ack"; 1980 1981 clocks = <&rpmhcc RPMH_CXO_CLK>; 1982 clock-names = "xo"; 1983 1984 power-domains = <&rpmhpd SM8350_CX>, 1985 <&rpmhpd SM8350_MSS>; 1986 power-domain-names = "cx", "mss"; 1987 1988 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1989 1990 memory-region = <&pil_modem_mem>; 1991 1992 qcom,qmp = <&aoss_qmp>; 1993 1994 qcom,smem-states = <&smp2p_modem_out 0>; 1995 qcom,smem-state-names = "stop"; 1996 1997 status = "disabled"; 1998 1999 glink-edge { 2000 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2001 IPCC_MPROC_SIGNAL_GLINK_QMP 2002 IRQ_TYPE_EDGE_RISING>; 2003 mboxes = <&ipcc IPCC_CLIENT_MPSS 2004 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2005 label = "modem"; 2006 qcom,remote-pid = <1>; 2007 }; 2008 }; 2009 2010 slpi: remoteproc@5c00000 { 2011 compatible = "qcom,sm8350-slpi-pas"; 2012 reg = <0 0x05c00000 0 0x4000>; 2013 2014 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2015 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2016 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2017 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2018 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2019 interrupt-names = "wdog", "fatal", "ready", 2020 "handover", "stop-ack"; 2021 2022 clocks = <&rpmhcc RPMH_CXO_CLK>; 2023 clock-names = "xo"; 2024 2025 power-domains = <&rpmhpd SM8350_LCX>, 2026 <&rpmhpd SM8350_LMX>; 2027 power-domain-names = "lcx", "lmx"; 2028 2029 memory-region = <&pil_slpi_mem>; 2030 2031 qcom,qmp = <&aoss_qmp>; 2032 2033 qcom,smem-states = <&smp2p_slpi_out 0>; 2034 qcom,smem-state-names = "stop"; 2035 2036 status = "disabled"; 2037 2038 glink-edge { 2039 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2040 IPCC_MPROC_SIGNAL_GLINK_QMP 2041 IRQ_TYPE_EDGE_RISING>; 2042 mboxes = <&ipcc IPCC_CLIENT_SLPI 2043 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2044 2045 label = "slpi"; 2046 qcom,remote-pid = <3>; 2047 2048 fastrpc { 2049 compatible = "qcom,fastrpc"; 2050 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2051 label = "sdsp"; 2052 qcom,non-secure-domain; 2053 #address-cells = <1>; 2054 #size-cells = <0>; 2055 2056 compute-cb@1 { 2057 compatible = "qcom,fastrpc-compute-cb"; 2058 reg = <1>; 2059 iommus = <&apps_smmu 0x0541 0x0>; 2060 }; 2061 2062 compute-cb@2 { 2063 compatible = "qcom,fastrpc-compute-cb"; 2064 reg = <2>; 2065 iommus = <&apps_smmu 0x0542 0x0>; 2066 }; 2067 2068 compute-cb@3 { 2069 compatible = "qcom,fastrpc-compute-cb"; 2070 reg = <3>; 2071 iommus = <&apps_smmu 0x0543 0x0>; 2072 /* note: shared-cb = <4> in downstream */ 2073 }; 2074 }; 2075 }; 2076 }; 2077 2078 sdhc_2: mmc@8804000 { 2079 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2080 reg = <0 0x08804000 0 0x1000>; 2081 2082 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2084 interrupt-names = "hc_irq", "pwr_irq"; 2085 2086 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2087 <&gcc GCC_SDCC2_APPS_CLK>, 2088 <&rpmhcc RPMH_CXO_CLK>; 2089 clock-names = "iface", "core", "xo"; 2090 resets = <&gcc GCC_SDCC2_BCR>; 2091 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2093 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2094 iommus = <&apps_smmu 0x4a0 0x0>; 2095 power-domains = <&rpmhpd SM8350_CX>; 2096 operating-points-v2 = <&sdhc2_opp_table>; 2097 bus-width = <4>; 2098 dma-coherent; 2099 2100 status = "disabled"; 2101 2102 sdhc2_opp_table: opp-table { 2103 compatible = "operating-points-v2"; 2104 2105 opp-100000000 { 2106 opp-hz = /bits/ 64 <100000000>; 2107 required-opps = <&rpmhpd_opp_low_svs>; 2108 }; 2109 2110 opp-202000000 { 2111 opp-hz = /bits/ 64 <202000000>; 2112 required-opps = <&rpmhpd_opp_svs_l1>; 2113 }; 2114 }; 2115 }; 2116 2117 usb_1_hsphy: phy@88e3000 { 2118 compatible = "qcom,sm8350-usb-hs-phy", 2119 "qcom,usb-snps-hs-7nm-phy"; 2120 reg = <0 0x088e3000 0 0x400>; 2121 status = "disabled"; 2122 #phy-cells = <0>; 2123 2124 clocks = <&rpmhcc RPMH_CXO_CLK>; 2125 clock-names = "ref"; 2126 2127 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2128 }; 2129 2130 usb_2_hsphy: phy@88e4000 { 2131 compatible = "qcom,sm8250-usb-hs-phy", 2132 "qcom,usb-snps-hs-7nm-phy"; 2133 reg = <0 0x088e4000 0 0x400>; 2134 status = "disabled"; 2135 #phy-cells = <0>; 2136 2137 clocks = <&rpmhcc RPMH_CXO_CLK>; 2138 clock-names = "ref"; 2139 2140 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2141 }; 2142 2143 usb_1_qmpphy: phy@88e9000 { 2144 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2145 reg = <0 0x088e8000 0 0x3000>; 2146 2147 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2148 <&rpmhcc RPMH_CXO_CLK>, 2149 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2150 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2151 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2152 2153 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2154 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2155 reset-names = "phy", "common"; 2156 2157 #clock-cells = <1>; 2158 #phy-cells = <1>; 2159 2160 status = "disabled"; 2161 }; 2162 2163 usb_2_qmpphy: phy-wrapper@88eb000 { 2164 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2165 reg = <0 0x088eb000 0 0x200>; 2166 status = "disabled"; 2167 #address-cells = <2>; 2168 #size-cells = <2>; 2169 ranges; 2170 2171 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2172 <&rpmhcc RPMH_CXO_CLK>, 2173 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2174 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2175 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2176 2177 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2178 <&gcc GCC_USB3_PHY_SEC_BCR>; 2179 reset-names = "phy", "common"; 2180 2181 usb_2_ssphy: phy@88ebe00 { 2182 reg = <0 0x088ebe00 0 0x200>, 2183 <0 0x088ec000 0 0x200>, 2184 <0 0x088eb200 0 0x1100>; 2185 #phy-cells = <0>; 2186 #clock-cells = <0>; 2187 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2188 clock-names = "pipe0"; 2189 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2190 }; 2191 }; 2192 2193 dc_noc: interconnect@90c0000 { 2194 compatible = "qcom,sm8350-dc-noc"; 2195 reg = <0 0x090c0000 0 0x4200>; 2196 #interconnect-cells = <2>; 2197 qcom,bcm-voters = <&apps_bcm_voter>; 2198 }; 2199 2200 gem_noc: interconnect@9100000 { 2201 compatible = "qcom,sm8350-gem-noc"; 2202 reg = <0 0x09100000 0 0xb4000>; 2203 #interconnect-cells = <2>; 2204 qcom,bcm-voters = <&apps_bcm_voter>; 2205 }; 2206 2207 system-cache-controller@9200000 { 2208 compatible = "qcom,sm8350-llcc"; 2209 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2210 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2211 <0 0x09600000 0 0x58000>; 2212 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2213 "llcc3_base", "llcc_broadcast_base"; 2214 }; 2215 2216 compute_noc: interconnect@a0c0000 { 2217 compatible = "qcom,sm8350-compute-noc"; 2218 reg = <0 0x0a0c0000 0 0xa180>; 2219 #interconnect-cells = <2>; 2220 qcom,bcm-voters = <&apps_bcm_voter>; 2221 }; 2222 2223 usb_1: usb@a6f8800 { 2224 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2225 reg = <0 0x0a6f8800 0 0x400>; 2226 status = "disabled"; 2227 #address-cells = <2>; 2228 #size-cells = <2>; 2229 ranges; 2230 2231 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2232 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2233 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2234 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2235 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2236 clock-names = "cfg_noc", 2237 "core", 2238 "iface", 2239 "sleep", 2240 "mock_utmi"; 2241 2242 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2243 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2244 assigned-clock-rates = <19200000>, <200000000>; 2245 2246 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2247 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2248 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2249 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2250 interrupt-names = "hs_phy_irq", 2251 "ss_phy_irq", 2252 "dm_hs_phy_irq", 2253 "dp_hs_phy_irq"; 2254 2255 power-domains = <&gcc USB30_PRIM_GDSC>; 2256 2257 resets = <&gcc GCC_USB30_PRIM_BCR>; 2258 2259 usb_1_dwc3: usb@a600000 { 2260 compatible = "snps,dwc3"; 2261 reg = <0 0x0a600000 0 0xcd00>; 2262 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2263 iommus = <&apps_smmu 0x0 0x0>; 2264 snps,dis_u2_susphy_quirk; 2265 snps,dis_enblslpm_quirk; 2266 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2267 phy-names = "usb2-phy", "usb3-phy"; 2268 2269 ports { 2270 #address-cells = <1>; 2271 #size-cells = <0>; 2272 2273 port@0 { 2274 reg = <0>; 2275 2276 usb_1_dwc3_hs: endpoint { 2277 }; 2278 }; 2279 2280 port@1 { 2281 reg = <1>; 2282 2283 usb_1_dwc3_ss: endpoint { 2284 }; 2285 }; 2286 }; 2287 }; 2288 }; 2289 2290 usb_2: usb@a8f8800 { 2291 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2292 reg = <0 0x0a8f8800 0 0x400>; 2293 status = "disabled"; 2294 #address-cells = <2>; 2295 #size-cells = <2>; 2296 ranges; 2297 2298 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2299 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2300 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2301 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2302 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2303 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2304 clock-names = "cfg_noc", 2305 "core", 2306 "iface", 2307 "sleep", 2308 "mock_utmi", 2309 "xo"; 2310 2311 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2312 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2313 assigned-clock-rates = <19200000>, <200000000>; 2314 2315 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2316 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2317 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2318 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2319 interrupt-names = "hs_phy_irq", 2320 "ss_phy_irq", 2321 "dm_hs_phy_irq", 2322 "dp_hs_phy_irq"; 2323 2324 power-domains = <&gcc USB30_SEC_GDSC>; 2325 2326 resets = <&gcc GCC_USB30_SEC_BCR>; 2327 2328 usb_2_dwc3: usb@a800000 { 2329 compatible = "snps,dwc3"; 2330 reg = <0 0x0a800000 0 0xcd00>; 2331 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2332 iommus = <&apps_smmu 0x20 0x0>; 2333 snps,dis_u2_susphy_quirk; 2334 snps,dis_enblslpm_quirk; 2335 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2336 phy-names = "usb2-phy", "usb3-phy"; 2337 }; 2338 }; 2339 2340 mdss: display-subsystem@ae00000 { 2341 compatible = "qcom,sm8350-mdss"; 2342 reg = <0 0x0ae00000 0 0x1000>; 2343 reg-names = "mdss"; 2344 2345 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2346 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2347 interconnect-names = "mdp0-mem", "mdp1-mem"; 2348 2349 power-domains = <&dispcc MDSS_GDSC>; 2350 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2351 2352 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2353 <&gcc GCC_DISP_HF_AXI_CLK>, 2354 <&gcc GCC_DISP_SF_AXI_CLK>, 2355 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2356 clock-names = "iface", "bus", "nrt_bus", "core"; 2357 2358 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2359 interrupt-controller; 2360 #interrupt-cells = <1>; 2361 2362 iommus = <&apps_smmu 0x820 0x402>; 2363 2364 status = "disabled"; 2365 2366 #address-cells = <2>; 2367 #size-cells = <2>; 2368 ranges; 2369 2370 dpu_opp_table: opp-table { 2371 compatible = "operating-points-v2"; 2372 2373 /* TODO: opp-200000000 should work with 2374 * &rpmhpd_opp_low_svs, but one some of 2375 * sm8350_hdk boards reboot using this 2376 * opp. 2377 */ 2378 opp-200000000 { 2379 opp-hz = /bits/ 64 <200000000>; 2380 required-opps = <&rpmhpd_opp_svs>; 2381 }; 2382 2383 opp-300000000 { 2384 opp-hz = /bits/ 64 <300000000>; 2385 required-opps = <&rpmhpd_opp_svs>; 2386 }; 2387 2388 opp-345000000 { 2389 opp-hz = /bits/ 64 <345000000>; 2390 required-opps = <&rpmhpd_opp_svs_l1>; 2391 }; 2392 2393 opp-460000000 { 2394 opp-hz = /bits/ 64 <460000000>; 2395 required-opps = <&rpmhpd_opp_nom>; 2396 }; 2397 }; 2398 2399 mdss_mdp: display-controller@ae01000 { 2400 compatible = "qcom,sm8350-dpu"; 2401 reg = <0 0x0ae01000 0 0x8f000>, 2402 <0 0x0aeb0000 0 0x2008>; 2403 reg-names = "mdp", "vbif"; 2404 2405 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2406 <&gcc GCC_DISP_SF_AXI_CLK>, 2407 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2408 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2409 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2410 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2411 clock-names = "bus", 2412 "nrt_bus", 2413 "iface", 2414 "lut", 2415 "core", 2416 "vsync"; 2417 2418 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2419 assigned-clock-rates = <19200000>; 2420 2421 operating-points-v2 = <&dpu_opp_table>; 2422 power-domains = <&rpmhpd SM8350_MMCX>; 2423 2424 interrupt-parent = <&mdss>; 2425 interrupts = <0>; 2426 2427 ports { 2428 #address-cells = <1>; 2429 #size-cells = <0>; 2430 2431 port@0 { 2432 reg = <0>; 2433 dpu_intf1_out: endpoint { 2434 remote-endpoint = <&mdss_dsi0_in>; 2435 }; 2436 }; 2437 2438 port@1 { 2439 reg = <1>; 2440 dpu_intf2_out: endpoint { 2441 remote-endpoint = <&mdss_dsi1_in>; 2442 }; 2443 }; 2444 2445 port@2 { 2446 reg = <2>; 2447 dpu_intf0_out: endpoint { 2448 remote-endpoint = <&mdss_dp_in>; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 mdss_dp: displayport-controller@ae90000 { 2455 compatible = "qcom,sm8350-dp"; 2456 reg = <0 0xae90000 0 0x200>, 2457 <0 0xae90200 0 0x200>, 2458 <0 0xae90400 0 0x600>, 2459 <0 0xae91000 0 0x400>, 2460 <0 0xae91400 0 0x400>; 2461 interrupt-parent = <&mdss>; 2462 interrupts = <12>; 2463 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2464 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2465 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2466 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2467 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2468 clock-names = "core_iface", 2469 "core_aux", 2470 "ctrl_link", 2471 "ctrl_link_iface", 2472 "stream_pixel"; 2473 2474 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2475 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2476 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2477 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2478 2479 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2480 phy-names = "dp"; 2481 2482 #sound-dai-cells = <0>; 2483 2484 operating-points-v2 = <&dp_opp_table>; 2485 power-domains = <&rpmhpd SM8350_MMCX>; 2486 2487 status = "disabled"; 2488 2489 ports { 2490 #address-cells = <1>; 2491 #size-cells = <0>; 2492 2493 port@0 { 2494 reg = <0>; 2495 mdss_dp_in: endpoint { 2496 remote-endpoint = <&dpu_intf0_out>; 2497 }; 2498 }; 2499 }; 2500 2501 dp_opp_table: opp-table { 2502 compatible = "operating-points-v2"; 2503 2504 opp-160000000 { 2505 opp-hz = /bits/ 64 <160000000>; 2506 required-opps = <&rpmhpd_opp_low_svs>; 2507 }; 2508 2509 opp-270000000 { 2510 opp-hz = /bits/ 64 <270000000>; 2511 required-opps = <&rpmhpd_opp_svs>; 2512 }; 2513 2514 opp-540000000 { 2515 opp-hz = /bits/ 64 <540000000>; 2516 required-opps = <&rpmhpd_opp_svs_l1>; 2517 }; 2518 2519 opp-810000000 { 2520 opp-hz = /bits/ 64 <810000000>; 2521 required-opps = <&rpmhpd_opp_nom>; 2522 }; 2523 }; 2524 }; 2525 2526 mdss_dsi0: dsi@ae94000 { 2527 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2528 reg = <0 0x0ae94000 0 0x400>; 2529 reg-names = "dsi_ctrl"; 2530 2531 interrupt-parent = <&mdss>; 2532 interrupts = <4>; 2533 2534 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2535 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2536 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2537 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2538 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2539 <&gcc GCC_DISP_HF_AXI_CLK>; 2540 clock-names = "byte", 2541 "byte_intf", 2542 "pixel", 2543 "core", 2544 "iface", 2545 "bus"; 2546 2547 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2548 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2549 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2550 <&mdss_dsi0_phy 1>; 2551 2552 operating-points-v2 = <&dsi0_opp_table>; 2553 power-domains = <&rpmhpd SM8350_MMCX>; 2554 2555 phys = <&mdss_dsi0_phy>; 2556 2557 #address-cells = <1>; 2558 #size-cells = <0>; 2559 2560 status = "disabled"; 2561 2562 dsi0_opp_table: opp-table { 2563 compatible = "operating-points-v2"; 2564 2565 /* TODO: opp-187500000 should work with 2566 * &rpmhpd_opp_low_svs, but one some of 2567 * sm8350_hdk boards reboot using this 2568 * opp. 2569 */ 2570 opp-187500000 { 2571 opp-hz = /bits/ 64 <187500000>; 2572 required-opps = <&rpmhpd_opp_svs>; 2573 }; 2574 2575 opp-300000000 { 2576 opp-hz = /bits/ 64 <300000000>; 2577 required-opps = <&rpmhpd_opp_svs>; 2578 }; 2579 2580 opp-358000000 { 2581 opp-hz = /bits/ 64 <358000000>; 2582 required-opps = <&rpmhpd_opp_svs_l1>; 2583 }; 2584 }; 2585 2586 ports { 2587 #address-cells = <1>; 2588 #size-cells = <0>; 2589 2590 port@0 { 2591 reg = <0>; 2592 mdss_dsi0_in: endpoint { 2593 remote-endpoint = <&dpu_intf1_out>; 2594 }; 2595 }; 2596 2597 port@1 { 2598 reg = <1>; 2599 mdss_dsi0_out: endpoint { 2600 }; 2601 }; 2602 }; 2603 }; 2604 2605 mdss_dsi0_phy: phy@ae94400 { 2606 compatible = "qcom,sm8350-dsi-phy-5nm"; 2607 reg = <0 0x0ae94400 0 0x200>, 2608 <0 0x0ae94600 0 0x280>, 2609 <0 0x0ae94900 0 0x27c>; 2610 reg-names = "dsi_phy", 2611 "dsi_phy_lane", 2612 "dsi_pll"; 2613 2614 #clock-cells = <1>; 2615 #phy-cells = <0>; 2616 2617 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2618 <&rpmhcc RPMH_CXO_CLK>; 2619 clock-names = "iface", "ref"; 2620 2621 status = "disabled"; 2622 }; 2623 2624 mdss_dsi1: dsi@ae96000 { 2625 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2626 reg = <0 0x0ae96000 0 0x400>; 2627 reg-names = "dsi_ctrl"; 2628 2629 interrupt-parent = <&mdss>; 2630 interrupts = <5>; 2631 2632 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2633 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2634 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2635 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2636 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2637 <&gcc GCC_DISP_HF_AXI_CLK>; 2638 clock-names = "byte", 2639 "byte_intf", 2640 "pixel", 2641 "core", 2642 "iface", 2643 "bus"; 2644 2645 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2646 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2647 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2648 <&mdss_dsi1_phy 1>; 2649 2650 operating-points-v2 = <&dsi1_opp_table>; 2651 power-domains = <&rpmhpd SM8350_MMCX>; 2652 2653 phys = <&mdss_dsi1_phy>; 2654 2655 #address-cells = <1>; 2656 #size-cells = <0>; 2657 2658 status = "disabled"; 2659 2660 dsi1_opp_table: opp-table { 2661 compatible = "operating-points-v2"; 2662 2663 /* TODO: opp-187500000 should work with 2664 * &rpmhpd_opp_low_svs, but one some of 2665 * sm8350_hdk boards reboot using this 2666 * opp. 2667 */ 2668 opp-187500000 { 2669 opp-hz = /bits/ 64 <187500000>; 2670 required-opps = <&rpmhpd_opp_svs>; 2671 }; 2672 2673 opp-300000000 { 2674 opp-hz = /bits/ 64 <300000000>; 2675 required-opps = <&rpmhpd_opp_svs>; 2676 }; 2677 2678 opp-358000000 { 2679 opp-hz = /bits/ 64 <358000000>; 2680 required-opps = <&rpmhpd_opp_svs_l1>; 2681 }; 2682 }; 2683 2684 ports { 2685 #address-cells = <1>; 2686 #size-cells = <0>; 2687 2688 port@0 { 2689 reg = <0>; 2690 mdss_dsi1_in: endpoint { 2691 remote-endpoint = <&dpu_intf2_out>; 2692 }; 2693 }; 2694 2695 port@1 { 2696 reg = <1>; 2697 mdss_dsi1_out: endpoint { 2698 }; 2699 }; 2700 }; 2701 }; 2702 2703 mdss_dsi1_phy: phy@ae96400 { 2704 compatible = "qcom,sm8350-dsi-phy-5nm"; 2705 reg = <0 0x0ae96400 0 0x200>, 2706 <0 0x0ae96600 0 0x280>, 2707 <0 0x0ae96900 0 0x27c>; 2708 reg-names = "dsi_phy", 2709 "dsi_phy_lane", 2710 "dsi_pll"; 2711 2712 #clock-cells = <1>; 2713 #phy-cells = <0>; 2714 2715 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2716 <&rpmhcc RPMH_CXO_CLK>; 2717 clock-names = "iface", "ref"; 2718 2719 status = "disabled"; 2720 }; 2721 }; 2722 2723 dispcc: clock-controller@af00000 { 2724 compatible = "qcom,sm8350-dispcc"; 2725 reg = <0 0x0af00000 0 0x10000>; 2726 clocks = <&rpmhcc RPMH_CXO_CLK>, 2727 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2728 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2729 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2730 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2731 clock-names = "bi_tcxo", 2732 "dsi0_phy_pll_out_byteclk", 2733 "dsi0_phy_pll_out_dsiclk", 2734 "dsi1_phy_pll_out_byteclk", 2735 "dsi1_phy_pll_out_dsiclk", 2736 "dp_phy_pll_link_clk", 2737 "dp_phy_pll_vco_div_clk"; 2738 #clock-cells = <1>; 2739 #reset-cells = <1>; 2740 #power-domain-cells = <1>; 2741 2742 power-domains = <&rpmhpd SM8350_MMCX>; 2743 }; 2744 2745 pdc: interrupt-controller@b220000 { 2746 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2747 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2748 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2749 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2750 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2751 <156 716 12>; 2752 #interrupt-cells = <2>; 2753 interrupt-parent = <&intc>; 2754 interrupt-controller; 2755 }; 2756 2757 tsens0: thermal-sensor@c263000 { 2758 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2759 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2760 <0 0x0c222000 0 0x8>; /* SROT */ 2761 #qcom,sensors = <15>; 2762 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2763 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2764 interrupt-names = "uplow", "critical"; 2765 #thermal-sensor-cells = <1>; 2766 }; 2767 2768 tsens1: thermal-sensor@c265000 { 2769 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2770 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2771 <0 0x0c223000 0 0x8>; /* SROT */ 2772 #qcom,sensors = <14>; 2773 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2774 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2775 interrupt-names = "uplow", "critical"; 2776 #thermal-sensor-cells = <1>; 2777 }; 2778 2779 aoss_qmp: power-management@c300000 { 2780 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2781 reg = <0 0x0c300000 0 0x400>; 2782 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2783 IRQ_TYPE_EDGE_RISING>; 2784 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2785 2786 #clock-cells = <0>; 2787 }; 2788 2789 sram@c3f0000 { 2790 compatible = "qcom,rpmh-stats"; 2791 reg = <0 0x0c3f0000 0 0x400>; 2792 }; 2793 2794 spmi_bus: spmi@c440000 { 2795 compatible = "qcom,spmi-pmic-arb"; 2796 reg = <0x0 0x0c440000 0x0 0x1100>, 2797 <0x0 0x0c600000 0x0 0x2000000>, 2798 <0x0 0x0e600000 0x0 0x100000>, 2799 <0x0 0x0e700000 0x0 0xa0000>, 2800 <0x0 0x0c40a000 0x0 0x26000>; 2801 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2802 interrupt-names = "periph_irq"; 2803 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2804 qcom,ee = <0>; 2805 qcom,channel = <0>; 2806 #address-cells = <2>; 2807 #size-cells = <0>; 2808 interrupt-controller; 2809 #interrupt-cells = <4>; 2810 }; 2811 2812 tlmm: pinctrl@f100000 { 2813 compatible = "qcom,sm8350-tlmm"; 2814 reg = <0 0x0f100000 0 0x300000>; 2815 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2816 gpio-controller; 2817 #gpio-cells = <2>; 2818 interrupt-controller; 2819 #interrupt-cells = <2>; 2820 gpio-ranges = <&tlmm 0 0 204>; 2821 wakeup-parent = <&pdc>; 2822 2823 sdc2_default_state: sdc2-default-state { 2824 clk-pins { 2825 pins = "sdc2_clk"; 2826 drive-strength = <16>; 2827 bias-disable; 2828 }; 2829 2830 cmd-pins { 2831 pins = "sdc2_cmd"; 2832 drive-strength = <16>; 2833 bias-pull-up; 2834 }; 2835 2836 data-pins { 2837 pins = "sdc2_data"; 2838 drive-strength = <16>; 2839 bias-pull-up; 2840 }; 2841 }; 2842 2843 sdc2_sleep_state: sdc2-sleep-state { 2844 clk-pins { 2845 pins = "sdc2_clk"; 2846 drive-strength = <2>; 2847 bias-disable; 2848 }; 2849 2850 cmd-pins { 2851 pins = "sdc2_cmd"; 2852 drive-strength = <2>; 2853 bias-pull-up; 2854 }; 2855 2856 data-pins { 2857 pins = "sdc2_data"; 2858 drive-strength = <2>; 2859 bias-pull-up; 2860 }; 2861 }; 2862 2863 qup_uart3_default_state: qup-uart3-default-state { 2864 rx-pins { 2865 pins = "gpio18"; 2866 function = "qup3"; 2867 }; 2868 tx-pins { 2869 pins = "gpio19"; 2870 function = "qup3"; 2871 }; 2872 }; 2873 2874 qup_uart6_default: qup-uart6-default-state { 2875 pins = "gpio30", "gpio31"; 2876 function = "qup6"; 2877 drive-strength = <2>; 2878 bias-disable; 2879 }; 2880 2881 qup_uart18_default: qup-uart18-default-state { 2882 pins = "gpio58", "gpio59"; 2883 function = "qup18"; 2884 drive-strength = <2>; 2885 bias-disable; 2886 }; 2887 2888 qup_i2c0_default: qup-i2c0-default-state { 2889 pins = "gpio4", "gpio5"; 2890 function = "qup0"; 2891 drive-strength = <2>; 2892 bias-pull-up; 2893 }; 2894 2895 qup_i2c1_default: qup-i2c1-default-state { 2896 pins = "gpio8", "gpio9"; 2897 function = "qup1"; 2898 drive-strength = <2>; 2899 bias-pull-up; 2900 }; 2901 2902 qup_i2c2_default: qup-i2c2-default-state { 2903 pins = "gpio12", "gpio13"; 2904 function = "qup2"; 2905 drive-strength = <2>; 2906 bias-pull-up; 2907 }; 2908 2909 qup_i2c4_default: qup-i2c4-default-state { 2910 pins = "gpio20", "gpio21"; 2911 function = "qup4"; 2912 drive-strength = <2>; 2913 bias-pull-up; 2914 }; 2915 2916 qup_i2c5_default: qup-i2c5-default-state { 2917 pins = "gpio24", "gpio25"; 2918 function = "qup5"; 2919 drive-strength = <2>; 2920 bias-pull-up; 2921 }; 2922 2923 qup_i2c6_default: qup-i2c6-default-state { 2924 pins = "gpio28", "gpio29"; 2925 function = "qup6"; 2926 drive-strength = <2>; 2927 bias-pull-up; 2928 }; 2929 2930 qup_i2c7_default: qup-i2c7-default-state { 2931 pins = "gpio32", "gpio33"; 2932 function = "qup7"; 2933 drive-strength = <2>; 2934 bias-disable; 2935 }; 2936 2937 qup_i2c8_default: qup-i2c8-default-state { 2938 pins = "gpio36", "gpio37"; 2939 function = "qup8"; 2940 drive-strength = <2>; 2941 bias-pull-up; 2942 }; 2943 2944 qup_i2c9_default: qup-i2c9-default-state { 2945 pins = "gpio40", "gpio41"; 2946 function = "qup9"; 2947 drive-strength = <2>; 2948 bias-pull-up; 2949 }; 2950 2951 qup_i2c10_default: qup-i2c10-default-state { 2952 pins = "gpio44", "gpio45"; 2953 function = "qup10"; 2954 drive-strength = <2>; 2955 bias-pull-up; 2956 }; 2957 2958 qup_i2c11_default: qup-i2c11-default-state { 2959 pins = "gpio48", "gpio49"; 2960 function = "qup11"; 2961 drive-strength = <2>; 2962 bias-pull-up; 2963 }; 2964 2965 qup_i2c12_default: qup-i2c12-default-state { 2966 pins = "gpio52", "gpio53"; 2967 function = "qup12"; 2968 drive-strength = <2>; 2969 bias-pull-up; 2970 }; 2971 2972 qup_i2c13_default: qup-i2c13-default-state { 2973 pins = "gpio0", "gpio1"; 2974 function = "qup13"; 2975 drive-strength = <2>; 2976 bias-pull-up; 2977 }; 2978 2979 qup_i2c14_default: qup-i2c14-default-state { 2980 pins = "gpio56", "gpio57"; 2981 function = "qup14"; 2982 drive-strength = <2>; 2983 bias-disable; 2984 }; 2985 2986 qup_i2c15_default: qup-i2c15-default-state { 2987 pins = "gpio60", "gpio61"; 2988 function = "qup15"; 2989 drive-strength = <2>; 2990 bias-disable; 2991 }; 2992 2993 qup_i2c16_default: qup-i2c16-default-state { 2994 pins = "gpio64", "gpio65"; 2995 function = "qup16"; 2996 drive-strength = <2>; 2997 bias-disable; 2998 }; 2999 3000 qup_i2c17_default: qup-i2c17-default-state { 3001 pins = "gpio72", "gpio73"; 3002 function = "qup17"; 3003 drive-strength = <2>; 3004 bias-disable; 3005 }; 3006 3007 qup_i2c19_default: qup-i2c19-default-state { 3008 pins = "gpio76", "gpio77"; 3009 function = "qup19"; 3010 drive-strength = <2>; 3011 bias-disable; 3012 }; 3013 }; 3014 3015 apps_smmu: iommu@15000000 { 3016 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3017 reg = <0 0x15000000 0 0x100000>; 3018 #iommu-cells = <2>; 3019 #global-interrupts = <2>; 3020 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3026 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3027 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3037 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3038 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3039 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3040 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3041 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3042 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3043 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3044 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3045 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3046 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3047 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3048 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3051 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3052 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3118 }; 3119 3120 adsp: remoteproc@17300000 { 3121 compatible = "qcom,sm8350-adsp-pas"; 3122 reg = <0 0x17300000 0 0x100>; 3123 3124 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3125 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3126 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3127 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3128 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3129 interrupt-names = "wdog", "fatal", "ready", 3130 "handover", "stop-ack"; 3131 3132 clocks = <&rpmhcc RPMH_CXO_CLK>; 3133 clock-names = "xo"; 3134 3135 power-domains = <&rpmhpd SM8350_LCX>, 3136 <&rpmhpd SM8350_LMX>; 3137 power-domain-names = "lcx", "lmx"; 3138 3139 memory-region = <&pil_adsp_mem>; 3140 3141 qcom,qmp = <&aoss_qmp>; 3142 3143 qcom,smem-states = <&smp2p_adsp_out 0>; 3144 qcom,smem-state-names = "stop"; 3145 3146 status = "disabled"; 3147 3148 glink-edge { 3149 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3150 IPCC_MPROC_SIGNAL_GLINK_QMP 3151 IRQ_TYPE_EDGE_RISING>; 3152 mboxes = <&ipcc IPCC_CLIENT_LPASS 3153 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3154 3155 label = "lpass"; 3156 qcom,remote-pid = <2>; 3157 3158 fastrpc { 3159 compatible = "qcom,fastrpc"; 3160 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3161 label = "adsp"; 3162 qcom,non-secure-domain; 3163 #address-cells = <1>; 3164 #size-cells = <0>; 3165 3166 compute-cb@3 { 3167 compatible = "qcom,fastrpc-compute-cb"; 3168 reg = <3>; 3169 iommus = <&apps_smmu 0x1803 0x0>; 3170 }; 3171 3172 compute-cb@4 { 3173 compatible = "qcom,fastrpc-compute-cb"; 3174 reg = <4>; 3175 iommus = <&apps_smmu 0x1804 0x0>; 3176 }; 3177 3178 compute-cb@5 { 3179 compatible = "qcom,fastrpc-compute-cb"; 3180 reg = <5>; 3181 iommus = <&apps_smmu 0x1805 0x0>; 3182 }; 3183 }; 3184 }; 3185 }; 3186 3187 intc: interrupt-controller@17a00000 { 3188 compatible = "arm,gic-v3"; 3189 #interrupt-cells = <3>; 3190 interrupt-controller; 3191 #redistributor-regions = <1>; 3192 redistributor-stride = <0 0x20000>; 3193 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3194 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3195 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3196 }; 3197 3198 timer@17c20000 { 3199 compatible = "arm,armv7-timer-mem"; 3200 #address-cells = <1>; 3201 #size-cells = <1>; 3202 ranges = <0 0 0 0x20000000>; 3203 reg = <0x0 0x17c20000 0x0 0x1000>; 3204 clock-frequency = <19200000>; 3205 3206 frame@17c21000 { 3207 frame-number = <0>; 3208 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3210 reg = <0x17c21000 0x1000>, 3211 <0x17c22000 0x1000>; 3212 }; 3213 3214 frame@17c23000 { 3215 frame-number = <1>; 3216 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3217 reg = <0x17c23000 0x1000>; 3218 status = "disabled"; 3219 }; 3220 3221 frame@17c25000 { 3222 frame-number = <2>; 3223 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3224 reg = <0x17c25000 0x1000>; 3225 status = "disabled"; 3226 }; 3227 3228 frame@17c27000 { 3229 frame-number = <3>; 3230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3231 reg = <0x17c27000 0x1000>; 3232 status = "disabled"; 3233 }; 3234 3235 frame@17c29000 { 3236 frame-number = <4>; 3237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3238 reg = <0x17c29000 0x1000>; 3239 status = "disabled"; 3240 }; 3241 3242 frame@17c2b000 { 3243 frame-number = <5>; 3244 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3245 reg = <0x17c2b000 0x1000>; 3246 status = "disabled"; 3247 }; 3248 3249 frame@17c2d000 { 3250 frame-number = <6>; 3251 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3252 reg = <0x17c2d000 0x1000>; 3253 status = "disabled"; 3254 }; 3255 }; 3256 3257 apps_rsc: rsc@18200000 { 3258 label = "apps_rsc"; 3259 compatible = "qcom,rpmh-rsc"; 3260 reg = <0x0 0x18200000 0x0 0x10000>, 3261 <0x0 0x18210000 0x0 0x10000>, 3262 <0x0 0x18220000 0x0 0x10000>; 3263 reg-names = "drv-0", "drv-1", "drv-2"; 3264 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3267 qcom,tcs-offset = <0xd00>; 3268 qcom,drv-id = <2>; 3269 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3270 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3271 power-domains = <&CLUSTER_PD>; 3272 3273 rpmhcc: clock-controller { 3274 compatible = "qcom,sm8350-rpmh-clk"; 3275 #clock-cells = <1>; 3276 clock-names = "xo"; 3277 clocks = <&xo_board>; 3278 }; 3279 3280 rpmhpd: power-controller { 3281 compatible = "qcom,sm8350-rpmhpd"; 3282 #power-domain-cells = <1>; 3283 operating-points-v2 = <&rpmhpd_opp_table>; 3284 3285 rpmhpd_opp_table: opp-table { 3286 compatible = "operating-points-v2"; 3287 3288 rpmhpd_opp_ret: opp1 { 3289 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3290 }; 3291 3292 rpmhpd_opp_min_svs: opp2 { 3293 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3294 }; 3295 3296 rpmhpd_opp_low_svs: opp3 { 3297 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3298 }; 3299 3300 rpmhpd_opp_svs: opp4 { 3301 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3302 }; 3303 3304 rpmhpd_opp_svs_l1: opp5 { 3305 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3306 }; 3307 3308 rpmhpd_opp_nom: opp6 { 3309 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3310 }; 3311 3312 rpmhpd_opp_nom_l1: opp7 { 3313 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3314 }; 3315 3316 rpmhpd_opp_nom_l2: opp8 { 3317 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3318 }; 3319 3320 rpmhpd_opp_turbo: opp9 { 3321 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3322 }; 3323 3324 rpmhpd_opp_turbo_l1: opp10 { 3325 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3326 }; 3327 }; 3328 }; 3329 3330 apps_bcm_voter: bcm-voter { 3331 compatible = "qcom,bcm-voter"; 3332 }; 3333 }; 3334 3335 cpufreq_hw: cpufreq@18591000 { 3336 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3337 reg = <0 0x18591000 0 0x1000>, 3338 <0 0x18592000 0 0x1000>, 3339 <0 0x18593000 0 0x1000>; 3340 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3341 3342 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3343 clock-names = "xo", "alternate"; 3344 3345 #freq-domain-cells = <1>; 3346 #clock-cells = <1>; 3347 }; 3348 3349 cdsp: remoteproc@98900000 { 3350 compatible = "qcom,sm8350-cdsp-pas"; 3351 reg = <0 0x98900000 0 0x1400000>; 3352 3353 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3354 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3355 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3356 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3357 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3358 interrupt-names = "wdog", "fatal", "ready", 3359 "handover", "stop-ack"; 3360 3361 clocks = <&rpmhcc RPMH_CXO_CLK>; 3362 clock-names = "xo"; 3363 3364 power-domains = <&rpmhpd SM8350_CX>, 3365 <&rpmhpd SM8350_MXC>; 3366 power-domain-names = "cx", "mxc"; 3367 3368 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3369 3370 memory-region = <&pil_cdsp_mem>; 3371 3372 qcom,qmp = <&aoss_qmp>; 3373 3374 qcom,smem-states = <&smp2p_cdsp_out 0>; 3375 qcom,smem-state-names = "stop"; 3376 3377 status = "disabled"; 3378 3379 glink-edge { 3380 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3381 IPCC_MPROC_SIGNAL_GLINK_QMP 3382 IRQ_TYPE_EDGE_RISING>; 3383 mboxes = <&ipcc IPCC_CLIENT_CDSP 3384 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3385 3386 label = "cdsp"; 3387 qcom,remote-pid = <5>; 3388 3389 fastrpc { 3390 compatible = "qcom,fastrpc"; 3391 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3392 label = "cdsp"; 3393 qcom,non-secure-domain; 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 compute-cb@1 { 3398 compatible = "qcom,fastrpc-compute-cb"; 3399 reg = <1>; 3400 iommus = <&apps_smmu 0x2161 0x0400>, 3401 <&apps_smmu 0x1181 0x0420>; 3402 }; 3403 3404 compute-cb@2 { 3405 compatible = "qcom,fastrpc-compute-cb"; 3406 reg = <2>; 3407 iommus = <&apps_smmu 0x2162 0x0400>, 3408 <&apps_smmu 0x1182 0x0420>; 3409 }; 3410 3411 compute-cb@3 { 3412 compatible = "qcom,fastrpc-compute-cb"; 3413 reg = <3>; 3414 iommus = <&apps_smmu 0x2163 0x0400>, 3415 <&apps_smmu 0x1183 0x0420>; 3416 }; 3417 3418 compute-cb@4 { 3419 compatible = "qcom,fastrpc-compute-cb"; 3420 reg = <4>; 3421 iommus = <&apps_smmu 0x2164 0x0400>, 3422 <&apps_smmu 0x1184 0x0420>; 3423 }; 3424 3425 compute-cb@5 { 3426 compatible = "qcom,fastrpc-compute-cb"; 3427 reg = <5>; 3428 iommus = <&apps_smmu 0x2165 0x0400>, 3429 <&apps_smmu 0x1185 0x0420>; 3430 }; 3431 3432 compute-cb@6 { 3433 compatible = "qcom,fastrpc-compute-cb"; 3434 reg = <6>; 3435 iommus = <&apps_smmu 0x2166 0x0400>, 3436 <&apps_smmu 0x1186 0x0420>; 3437 }; 3438 3439 compute-cb@7 { 3440 compatible = "qcom,fastrpc-compute-cb"; 3441 reg = <7>; 3442 iommus = <&apps_smmu 0x2167 0x0400>, 3443 <&apps_smmu 0x1187 0x0420>; 3444 }; 3445 3446 compute-cb@8 { 3447 compatible = "qcom,fastrpc-compute-cb"; 3448 reg = <8>; 3449 iommus = <&apps_smmu 0x2168 0x0400>, 3450 <&apps_smmu 0x1188 0x0420>; 3451 }; 3452 3453 /* note: secure cb9 in downstream */ 3454 }; 3455 }; 3456 }; 3457 }; 3458 3459 thermal_zones: thermal-zones { 3460 cpu0-thermal { 3461 polling-delay-passive = <250>; 3462 polling-delay = <1000>; 3463 3464 thermal-sensors = <&tsens0 1>; 3465 3466 trips { 3467 cpu0_alert0: trip-point0 { 3468 temperature = <90000>; 3469 hysteresis = <2000>; 3470 type = "passive"; 3471 }; 3472 3473 cpu0_alert1: trip-point1 { 3474 temperature = <95000>; 3475 hysteresis = <2000>; 3476 type = "passive"; 3477 }; 3478 3479 cpu0_crit: cpu-crit { 3480 temperature = <110000>; 3481 hysteresis = <1000>; 3482 type = "critical"; 3483 }; 3484 }; 3485 3486 cooling-maps { 3487 map0 { 3488 trip = <&cpu0_alert0>; 3489 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3490 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3491 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3492 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3493 }; 3494 map1 { 3495 trip = <&cpu0_alert1>; 3496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3500 }; 3501 }; 3502 }; 3503 3504 cpu1-thermal { 3505 polling-delay-passive = <250>; 3506 polling-delay = <1000>; 3507 3508 thermal-sensors = <&tsens0 2>; 3509 3510 trips { 3511 cpu1_alert0: trip-point0 { 3512 temperature = <90000>; 3513 hysteresis = <2000>; 3514 type = "passive"; 3515 }; 3516 3517 cpu1_alert1: trip-point1 { 3518 temperature = <95000>; 3519 hysteresis = <2000>; 3520 type = "passive"; 3521 }; 3522 3523 cpu1_crit: cpu-crit { 3524 temperature = <110000>; 3525 hysteresis = <1000>; 3526 type = "critical"; 3527 }; 3528 }; 3529 3530 cooling-maps { 3531 map0 { 3532 trip = <&cpu1_alert0>; 3533 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3534 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3535 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3536 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3537 }; 3538 map1 { 3539 trip = <&cpu1_alert1>; 3540 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3541 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3542 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3543 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3544 }; 3545 }; 3546 }; 3547 3548 cpu2-thermal { 3549 polling-delay-passive = <250>; 3550 polling-delay = <1000>; 3551 3552 thermal-sensors = <&tsens0 3>; 3553 3554 trips { 3555 cpu2_alert0: trip-point0 { 3556 temperature = <90000>; 3557 hysteresis = <2000>; 3558 type = "passive"; 3559 }; 3560 3561 cpu2_alert1: trip-point1 { 3562 temperature = <95000>; 3563 hysteresis = <2000>; 3564 type = "passive"; 3565 }; 3566 3567 cpu2_crit: cpu-crit { 3568 temperature = <110000>; 3569 hysteresis = <1000>; 3570 type = "critical"; 3571 }; 3572 }; 3573 3574 cooling-maps { 3575 map0 { 3576 trip = <&cpu2_alert0>; 3577 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3578 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3579 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3580 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3581 }; 3582 map1 { 3583 trip = <&cpu2_alert1>; 3584 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3585 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3586 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3587 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3588 }; 3589 }; 3590 }; 3591 3592 cpu3-thermal { 3593 polling-delay-passive = <250>; 3594 polling-delay = <1000>; 3595 3596 thermal-sensors = <&tsens0 4>; 3597 3598 trips { 3599 cpu3_alert0: trip-point0 { 3600 temperature = <90000>; 3601 hysteresis = <2000>; 3602 type = "passive"; 3603 }; 3604 3605 cpu3_alert1: trip-point1 { 3606 temperature = <95000>; 3607 hysteresis = <2000>; 3608 type = "passive"; 3609 }; 3610 3611 cpu3_crit: cpu-crit { 3612 temperature = <110000>; 3613 hysteresis = <1000>; 3614 type = "critical"; 3615 }; 3616 }; 3617 3618 cooling-maps { 3619 map0 { 3620 trip = <&cpu3_alert0>; 3621 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3622 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3623 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3624 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3625 }; 3626 map1 { 3627 trip = <&cpu3_alert1>; 3628 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3629 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3630 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3631 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3632 }; 3633 }; 3634 }; 3635 3636 cpu4-top-thermal { 3637 polling-delay-passive = <250>; 3638 polling-delay = <1000>; 3639 3640 thermal-sensors = <&tsens0 7>; 3641 3642 trips { 3643 cpu4_top_alert0: trip-point0 { 3644 temperature = <90000>; 3645 hysteresis = <2000>; 3646 type = "passive"; 3647 }; 3648 3649 cpu4_top_alert1: trip-point1 { 3650 temperature = <95000>; 3651 hysteresis = <2000>; 3652 type = "passive"; 3653 }; 3654 3655 cpu4_top_crit: cpu-crit { 3656 temperature = <110000>; 3657 hysteresis = <1000>; 3658 type = "critical"; 3659 }; 3660 }; 3661 3662 cooling-maps { 3663 map0 { 3664 trip = <&cpu4_top_alert0>; 3665 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3666 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3667 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3668 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3669 }; 3670 map1 { 3671 trip = <&cpu4_top_alert1>; 3672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3676 }; 3677 }; 3678 }; 3679 3680 cpu5-top-thermal { 3681 polling-delay-passive = <250>; 3682 polling-delay = <1000>; 3683 3684 thermal-sensors = <&tsens0 8>; 3685 3686 trips { 3687 cpu5_top_alert0: trip-point0 { 3688 temperature = <90000>; 3689 hysteresis = <2000>; 3690 type = "passive"; 3691 }; 3692 3693 cpu5_top_alert1: trip-point1 { 3694 temperature = <95000>; 3695 hysteresis = <2000>; 3696 type = "passive"; 3697 }; 3698 3699 cpu5_top_crit: cpu-crit { 3700 temperature = <110000>; 3701 hysteresis = <1000>; 3702 type = "critical"; 3703 }; 3704 }; 3705 3706 cooling-maps { 3707 map0 { 3708 trip = <&cpu5_top_alert0>; 3709 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3710 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3711 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3712 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3713 }; 3714 map1 { 3715 trip = <&cpu5_top_alert1>; 3716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3720 }; 3721 }; 3722 }; 3723 3724 cpu6-top-thermal { 3725 polling-delay-passive = <250>; 3726 polling-delay = <1000>; 3727 3728 thermal-sensors = <&tsens0 9>; 3729 3730 trips { 3731 cpu6_top_alert0: trip-point0 { 3732 temperature = <90000>; 3733 hysteresis = <2000>; 3734 type = "passive"; 3735 }; 3736 3737 cpu6_top_alert1: trip-point1 { 3738 temperature = <95000>; 3739 hysteresis = <2000>; 3740 type = "passive"; 3741 }; 3742 3743 cpu6_top_crit: cpu-crit { 3744 temperature = <110000>; 3745 hysteresis = <1000>; 3746 type = "critical"; 3747 }; 3748 }; 3749 3750 cooling-maps { 3751 map0 { 3752 trip = <&cpu6_top_alert0>; 3753 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3755 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3756 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3757 }; 3758 map1 { 3759 trip = <&cpu6_top_alert1>; 3760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3764 }; 3765 }; 3766 }; 3767 3768 cpu7-top-thermal { 3769 polling-delay-passive = <250>; 3770 polling-delay = <1000>; 3771 3772 thermal-sensors = <&tsens0 10>; 3773 3774 trips { 3775 cpu7_top_alert0: trip-point0 { 3776 temperature = <90000>; 3777 hysteresis = <2000>; 3778 type = "passive"; 3779 }; 3780 3781 cpu7_top_alert1: trip-point1 { 3782 temperature = <95000>; 3783 hysteresis = <2000>; 3784 type = "passive"; 3785 }; 3786 3787 cpu7_top_crit: cpu-crit { 3788 temperature = <110000>; 3789 hysteresis = <1000>; 3790 type = "critical"; 3791 }; 3792 }; 3793 3794 cooling-maps { 3795 map0 { 3796 trip = <&cpu7_top_alert0>; 3797 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3801 }; 3802 map1 { 3803 trip = <&cpu7_top_alert1>; 3804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3808 }; 3809 }; 3810 }; 3811 3812 cpu4-bottom-thermal { 3813 polling-delay-passive = <250>; 3814 polling-delay = <1000>; 3815 3816 thermal-sensors = <&tsens0 11>; 3817 3818 trips { 3819 cpu4_bottom_alert0: trip-point0 { 3820 temperature = <90000>; 3821 hysteresis = <2000>; 3822 type = "passive"; 3823 }; 3824 3825 cpu4_bottom_alert1: trip-point1 { 3826 temperature = <95000>; 3827 hysteresis = <2000>; 3828 type = "passive"; 3829 }; 3830 3831 cpu4_bottom_crit: cpu-crit { 3832 temperature = <110000>; 3833 hysteresis = <1000>; 3834 type = "critical"; 3835 }; 3836 }; 3837 3838 cooling-maps { 3839 map0 { 3840 trip = <&cpu4_bottom_alert0>; 3841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3845 }; 3846 map1 { 3847 trip = <&cpu4_bottom_alert1>; 3848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3852 }; 3853 }; 3854 }; 3855 3856 cpu5-bottom-thermal { 3857 polling-delay-passive = <250>; 3858 polling-delay = <1000>; 3859 3860 thermal-sensors = <&tsens0 12>; 3861 3862 trips { 3863 cpu5_bottom_alert0: trip-point0 { 3864 temperature = <90000>; 3865 hysteresis = <2000>; 3866 type = "passive"; 3867 }; 3868 3869 cpu5_bottom_alert1: trip-point1 { 3870 temperature = <95000>; 3871 hysteresis = <2000>; 3872 type = "passive"; 3873 }; 3874 3875 cpu5_bottom_crit: cpu-crit { 3876 temperature = <110000>; 3877 hysteresis = <1000>; 3878 type = "critical"; 3879 }; 3880 }; 3881 3882 cooling-maps { 3883 map0 { 3884 trip = <&cpu5_bottom_alert0>; 3885 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3889 }; 3890 map1 { 3891 trip = <&cpu5_bottom_alert1>; 3892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3896 }; 3897 }; 3898 }; 3899 3900 cpu6-bottom-thermal { 3901 polling-delay-passive = <250>; 3902 polling-delay = <1000>; 3903 3904 thermal-sensors = <&tsens0 13>; 3905 3906 trips { 3907 cpu6_bottom_alert0: trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu6_bottom_alert1: trip-point1 { 3914 temperature = <95000>; 3915 hysteresis = <2000>; 3916 type = "passive"; 3917 }; 3918 3919 cpu6_bottom_crit: cpu-crit { 3920 temperature = <110000>; 3921 hysteresis = <1000>; 3922 type = "critical"; 3923 }; 3924 }; 3925 3926 cooling-maps { 3927 map0 { 3928 trip = <&cpu6_bottom_alert0>; 3929 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3933 }; 3934 map1 { 3935 trip = <&cpu6_bottom_alert1>; 3936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3940 }; 3941 }; 3942 }; 3943 3944 cpu7-bottom-thermal { 3945 polling-delay-passive = <250>; 3946 polling-delay = <1000>; 3947 3948 thermal-sensors = <&tsens0 14>; 3949 3950 trips { 3951 cpu7_bottom_alert0: trip-point0 { 3952 temperature = <90000>; 3953 hysteresis = <2000>; 3954 type = "passive"; 3955 }; 3956 3957 cpu7_bottom_alert1: trip-point1 { 3958 temperature = <95000>; 3959 hysteresis = <2000>; 3960 type = "passive"; 3961 }; 3962 3963 cpu7_bottom_crit: cpu-crit { 3964 temperature = <110000>; 3965 hysteresis = <1000>; 3966 type = "critical"; 3967 }; 3968 }; 3969 3970 cooling-maps { 3971 map0 { 3972 trip = <&cpu7_bottom_alert0>; 3973 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3977 }; 3978 map1 { 3979 trip = <&cpu7_bottom_alert1>; 3980 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3984 }; 3985 }; 3986 }; 3987 3988 aoss0-thermal { 3989 polling-delay-passive = <250>; 3990 polling-delay = <1000>; 3991 3992 thermal-sensors = <&tsens0 0>; 3993 3994 trips { 3995 aoss0_alert0: trip-point0 { 3996 temperature = <90000>; 3997 hysteresis = <2000>; 3998 type = "hot"; 3999 }; 4000 }; 4001 }; 4002 4003 cluster0-thermal { 4004 polling-delay-passive = <250>; 4005 polling-delay = <1000>; 4006 4007 thermal-sensors = <&tsens0 5>; 4008 4009 trips { 4010 cluster0_alert0: trip-point0 { 4011 temperature = <90000>; 4012 hysteresis = <2000>; 4013 type = "hot"; 4014 }; 4015 cluster0_crit: cluster0_crit { 4016 temperature = <110000>; 4017 hysteresis = <2000>; 4018 type = "critical"; 4019 }; 4020 }; 4021 }; 4022 4023 cluster1-thermal { 4024 polling-delay-passive = <250>; 4025 polling-delay = <1000>; 4026 4027 thermal-sensors = <&tsens0 6>; 4028 4029 trips { 4030 cluster1_alert0: trip-point0 { 4031 temperature = <90000>; 4032 hysteresis = <2000>; 4033 type = "hot"; 4034 }; 4035 cluster1_crit: cluster1_crit { 4036 temperature = <110000>; 4037 hysteresis = <2000>; 4038 type = "critical"; 4039 }; 4040 }; 4041 }; 4042 4043 aoss1-thermal { 4044 polling-delay-passive = <250>; 4045 polling-delay = <1000>; 4046 4047 thermal-sensors = <&tsens1 0>; 4048 4049 trips { 4050 aoss1_alert0: trip-point0 { 4051 temperature = <90000>; 4052 hysteresis = <2000>; 4053 type = "hot"; 4054 }; 4055 }; 4056 }; 4057 4058 gpu-top-thermal { 4059 polling-delay-passive = <250>; 4060 polling-delay = <1000>; 4061 4062 thermal-sensors = <&tsens1 1>; 4063 4064 trips { 4065 gpu1_alert0: trip-point0 { 4066 temperature = <90000>; 4067 hysteresis = <1000>; 4068 type = "hot"; 4069 }; 4070 }; 4071 }; 4072 4073 gpu-bottom-thermal { 4074 polling-delay-passive = <250>; 4075 polling-delay = <1000>; 4076 4077 thermal-sensors = <&tsens1 2>; 4078 4079 trips { 4080 gpu2_alert0: trip-point0 { 4081 temperature = <90000>; 4082 hysteresis = <1000>; 4083 type = "hot"; 4084 }; 4085 }; 4086 }; 4087 4088 nspss1-thermal { 4089 polling-delay-passive = <250>; 4090 polling-delay = <1000>; 4091 4092 thermal-sensors = <&tsens1 3>; 4093 4094 trips { 4095 nspss1_alert0: trip-point0 { 4096 temperature = <90000>; 4097 hysteresis = <1000>; 4098 type = "hot"; 4099 }; 4100 }; 4101 }; 4102 4103 nspss2-thermal { 4104 polling-delay-passive = <250>; 4105 polling-delay = <1000>; 4106 4107 thermal-sensors = <&tsens1 4>; 4108 4109 trips { 4110 nspss2_alert0: trip-point0 { 4111 temperature = <90000>; 4112 hysteresis = <1000>; 4113 type = "hot"; 4114 }; 4115 }; 4116 }; 4117 4118 nspss3-thermal { 4119 polling-delay-passive = <250>; 4120 polling-delay = <1000>; 4121 4122 thermal-sensors = <&tsens1 5>; 4123 4124 trips { 4125 nspss3_alert0: trip-point0 { 4126 temperature = <90000>; 4127 hysteresis = <1000>; 4128 type = "hot"; 4129 }; 4130 }; 4131 }; 4132 4133 video-thermal { 4134 polling-delay-passive = <250>; 4135 polling-delay = <1000>; 4136 4137 thermal-sensors = <&tsens1 6>; 4138 4139 trips { 4140 video_alert0: trip-point0 { 4141 temperature = <90000>; 4142 hysteresis = <2000>; 4143 type = "hot"; 4144 }; 4145 }; 4146 }; 4147 4148 mem-thermal { 4149 polling-delay-passive = <250>; 4150 polling-delay = <1000>; 4151 4152 thermal-sensors = <&tsens1 7>; 4153 4154 trips { 4155 mem_alert0: trip-point0 { 4156 temperature = <90000>; 4157 hysteresis = <2000>; 4158 type = "hot"; 4159 }; 4160 }; 4161 }; 4162 4163 modem1-top-thermal { 4164 polling-delay-passive = <250>; 4165 polling-delay = <1000>; 4166 4167 thermal-sensors = <&tsens1 8>; 4168 4169 trips { 4170 modem1_alert0: trip-point0 { 4171 temperature = <90000>; 4172 hysteresis = <2000>; 4173 type = "hot"; 4174 }; 4175 }; 4176 }; 4177 4178 modem2-top-thermal { 4179 polling-delay-passive = <250>; 4180 polling-delay = <1000>; 4181 4182 thermal-sensors = <&tsens1 9>; 4183 4184 trips { 4185 modem2_alert0: trip-point0 { 4186 temperature = <90000>; 4187 hysteresis = <2000>; 4188 type = "hot"; 4189 }; 4190 }; 4191 }; 4192 4193 modem3-top-thermal { 4194 polling-delay-passive = <250>; 4195 polling-delay = <1000>; 4196 4197 thermal-sensors = <&tsens1 10>; 4198 4199 trips { 4200 modem3_alert0: trip-point0 { 4201 temperature = <90000>; 4202 hysteresis = <2000>; 4203 type = "hot"; 4204 }; 4205 }; 4206 }; 4207 4208 modem4-top-thermal { 4209 polling-delay-passive = <250>; 4210 polling-delay = <1000>; 4211 4212 thermal-sensors = <&tsens1 11>; 4213 4214 trips { 4215 modem4_alert0: trip-point0 { 4216 temperature = <90000>; 4217 hysteresis = <2000>; 4218 type = "hot"; 4219 }; 4220 }; 4221 }; 4222 4223 camera-top-thermal { 4224 polling-delay-passive = <250>; 4225 polling-delay = <1000>; 4226 4227 thermal-sensors = <&tsens1 12>; 4228 4229 trips { 4230 camera1_alert0: trip-point0 { 4231 temperature = <90000>; 4232 hysteresis = <2000>; 4233 type = "hot"; 4234 }; 4235 }; 4236 }; 4237 4238 cam-bottom-thermal { 4239 polling-delay-passive = <250>; 4240 polling-delay = <1000>; 4241 4242 thermal-sensors = <&tsens1 13>; 4243 4244 trips { 4245 camera2_alert0: trip-point0 { 4246 temperature = <90000>; 4247 hysteresis = <2000>; 4248 type = "hot"; 4249 }; 4250 }; 4251 }; 4252 }; 4253 4254 timer { 4255 compatible = "arm,armv8-timer"; 4256 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4257 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4258 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4259 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4260 }; 4261}; 4262