1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/interconnect/qcom,sm8350.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <38400000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32000>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo685"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 #cooling-cells = <2>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 next-level-cache = <&L3_0>; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 }; 57 }; 58 }; 59 60 CPU1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo685"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 next-level-cache = <&L2_100>; 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 #cooling-cells = <2>; 68 L2_100: l2-cache { 69 compatible = "cache"; 70 next-level-cache = <&L3_0>; 71 }; 72 }; 73 74 CPU2: cpu@200 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo685"; 77 reg = <0x0 0x200>; 78 enable-method = "psci"; 79 next-level-cache = <&L2_200>; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 #cooling-cells = <2>; 82 L2_200: l2-cache { 83 compatible = "cache"; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU3: cpu@300 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo685"; 91 reg = <0x0 0x300>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_300>; 94 qcom,freq-domain = <&cpufreq_hw 0>; 95 #cooling-cells = <2>; 96 L2_300: l2-cache { 97 compatible = "cache"; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU4: cpu@400 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo685"; 105 reg = <0x0 0x400>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_400>; 108 qcom,freq-domain = <&cpufreq_hw 1>; 109 #cooling-cells = <2>; 110 L2_400: l2-cache { 111 compatible = "cache"; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU5: cpu@500 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo685"; 119 reg = <0x0 0x500>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_500>; 122 qcom,freq-domain = <&cpufreq_hw 1>; 123 #cooling-cells = <2>; 124 L2_500: l2-cache { 125 compatible = "cache"; 126 next-level-cache = <&L3_0>; 127 }; 128 129 }; 130 131 CPU6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo685"; 134 reg = <0x0 0x600>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_600>; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 #cooling-cells = <2>; 139 L2_600: l2-cache { 140 compatible = "cache"; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU7: cpu@700 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo685"; 148 reg = <0x0 0x700>; 149 enable-method = "psci"; 150 next-level-cache = <&L2_700>; 151 qcom,freq-domain = <&cpufreq_hw 2>; 152 #cooling-cells = <2>; 153 L2_700: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 }; 159 160 firmware { 161 scm: scm { 162 compatible = "qcom,scm-sm8350", "qcom,scm"; 163 #reset-cells = <1>; 164 }; 165 }; 166 167 memory@80000000 { 168 device_type = "memory"; 169 /* We expect the bootloader to fill in the size */ 170 reg = <0x0 0x80000000 0x0 0x0>; 171 }; 172 173 pmu { 174 compatible = "arm,armv8-pmuv3"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 reserved_memory: reserved-memory { 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges; 187 188 hyp_mem: memory@80000000 { 189 reg = <0x0 0x80000000 0x0 0x600000>; 190 no-map; 191 }; 192 193 xbl_aop_mem: memory@80700000 { 194 no-map; 195 reg = <0x0 0x80700000 0x0 0x160000>; 196 }; 197 198 cmd_db: memory@80860000 { 199 compatible = "qcom,cmd-db"; 200 reg = <0x0 0x80860000 0x0 0x20000>; 201 no-map; 202 }; 203 204 reserved_xbl_uefi_log: memory@80880000 { 205 reg = <0x0 0x80880000 0x0 0x14000>; 206 no-map; 207 }; 208 209 smem_mem: memory@80900000 { 210 reg = <0x0 0x80900000 0x0 0x200000>; 211 no-map; 212 }; 213 214 cpucp_fw_mem: memory@80b00000 { 215 reg = <0x0 0x80b00000 0x0 0x100000>; 216 no-map; 217 }; 218 219 cdsp_secure_heap: memory@80c00000 { 220 reg = <0x0 0x80c00000 0x0 0x4600000>; 221 no-map; 222 }; 223 224 pil_camera_mem: mmeory@85200000 { 225 reg = <0x0 0x85200000 0x0 0x500000>; 226 no-map; 227 }; 228 229 pil_video_mem: memory@85700000 { 230 reg = <0x0 0x85700000 0x0 0x500000>; 231 no-map; 232 }; 233 234 pil_cvp_mem: memory@85c00000 { 235 reg = <0x0 0x85c00000 0x0 0x500000>; 236 no-map; 237 }; 238 239 pil_adsp_mem: memory@86100000 { 240 reg = <0x0 0x86100000 0x0 0x2100000>; 241 no-map; 242 }; 243 244 pil_slpi_mem: memory@88200000 { 245 reg = <0x0 0x88200000 0x0 0x1500000>; 246 no-map; 247 }; 248 249 pil_cdsp_mem: memory@89700000 { 250 reg = <0x0 0x89700000 0x0 0x1e00000>; 251 no-map; 252 }; 253 254 pil_ipa_fw_mem: memory@8b500000 { 255 reg = <0x0 0x8b500000 0x0 0x10000>; 256 no-map; 257 }; 258 259 pil_ipa_gsi_mem: memory@8b510000 { 260 reg = <0x0 0x8b510000 0x0 0xa000>; 261 no-map; 262 }; 263 264 pil_gpu_mem: memory@8b51a000 { 265 reg = <0x0 0x8b51a000 0x0 0x2000>; 266 no-map; 267 }; 268 269 pil_spss_mem: memory@8b600000 { 270 reg = <0x0 0x8b600000 0x0 0x100000>; 271 no-map; 272 }; 273 274 pil_modem_mem: memory@8b800000 { 275 reg = <0x0 0x8b800000 0x0 0x10000000>; 276 no-map; 277 }; 278 279 rmtfs_mem: memory@9b800000 { 280 compatible = "qcom,rmtfs-mem"; 281 reg = <0x0 0x9b800000 0x0 0x280000>; 282 no-map; 283 284 qcom,client-id = <1>; 285 qcom,vmid = <15>; 286 }; 287 288 hyp_reserved_mem: memory@d0000000 { 289 reg = <0x0 0xd0000000 0x0 0x800000>; 290 no-map; 291 }; 292 293 pil_trustedvm_mem: memory@d0800000 { 294 reg = <0x0 0xd0800000 0x0 0x76f7000>; 295 no-map; 296 }; 297 298 qrtr_shbuf: memory@d7ef7000 { 299 reg = <0x0 0xd7ef7000 0x0 0x9000>; 300 no-map; 301 }; 302 303 chan0_shbuf: memory@d7f00000 { 304 reg = <0x0 0xd7f00000 0x0 0x80000>; 305 no-map; 306 }; 307 308 chan1_shbuf: memory@d7f80000 { 309 reg = <0x0 0xd7f80000 0x0 0x80000>; 310 no-map; 311 }; 312 313 removed_mem: memory@d8800000 { 314 reg = <0x0 0xd8800000 0x0 0x6800000>; 315 no-map; 316 }; 317 }; 318 319 smem: qcom,smem { 320 compatible = "qcom,smem"; 321 memory-region = <&smem_mem>; 322 hwlocks = <&tcsr_mutex 3>; 323 }; 324 325 smp2p-adsp { 326 compatible = "qcom,smp2p"; 327 qcom,smem = <443>, <429>; 328 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 329 IPCC_MPROC_SIGNAL_SMP2P 330 IRQ_TYPE_EDGE_RISING>; 331 mboxes = <&ipcc IPCC_CLIENT_LPASS 332 IPCC_MPROC_SIGNAL_SMP2P>; 333 334 qcom,local-pid = <0>; 335 qcom,remote-pid = <2>; 336 337 smp2p_adsp_out: master-kernel { 338 qcom,entry-name = "master-kernel"; 339 #qcom,smem-state-cells = <1>; 340 }; 341 342 smp2p_adsp_in: slave-kernel { 343 qcom,entry-name = "slave-kernel"; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 }; 347 }; 348 349 smp2p-cdsp { 350 compatible = "qcom,smp2p"; 351 qcom,smem = <94>, <432>; 352 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 353 IPCC_MPROC_SIGNAL_SMP2P 354 IRQ_TYPE_EDGE_RISING>; 355 mboxes = <&ipcc IPCC_CLIENT_CDSP 356 IPCC_MPROC_SIGNAL_SMP2P>; 357 358 qcom,local-pid = <0>; 359 qcom,remote-pid = <5>; 360 361 smp2p_cdsp_out: master-kernel { 362 qcom,entry-name = "master-kernel"; 363 #qcom,smem-state-cells = <1>; 364 }; 365 366 smp2p_cdsp_in: slave-kernel { 367 qcom,entry-name = "slave-kernel"; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 }; 372 373 smp2p-modem { 374 compatible = "qcom,smp2p"; 375 qcom,smem = <435>, <428>; 376 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 377 IPCC_MPROC_SIGNAL_SMP2P 378 IRQ_TYPE_EDGE_RISING>; 379 mboxes = <&ipcc IPCC_CLIENT_MPSS 380 IPCC_MPROC_SIGNAL_SMP2P>; 381 382 qcom,local-pid = <0>; 383 qcom,remote-pid = <1>; 384 385 smp2p_modem_out: master-kernel { 386 qcom,entry-name = "master-kernel"; 387 #qcom,smem-state-cells = <1>; 388 }; 389 390 smp2p_modem_in: slave-kernel { 391 qcom,entry-name = "slave-kernel"; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 }; 395 396 ipa_smp2p_out: ipa-ap-to-modem { 397 qcom,entry-name = "ipa"; 398 #qcom,smem-state-cells = <1>; 399 }; 400 401 ipa_smp2p_in: ipa-modem-to-ap { 402 qcom,entry-name = "ipa"; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 smp2p-slpi { 409 compatible = "qcom,smp2p"; 410 qcom,smem = <481>, <430>; 411 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 412 IPCC_MPROC_SIGNAL_SMP2P 413 IRQ_TYPE_EDGE_RISING>; 414 mboxes = <&ipcc IPCC_CLIENT_SLPI 415 IPCC_MPROC_SIGNAL_SMP2P>; 416 417 qcom,local-pid = <0>; 418 qcom,remote-pid = <3>; 419 420 smp2p_slpi_out: master-kernel { 421 qcom,entry-name = "master-kernel"; 422 #qcom,smem-state-cells = <1>; 423 }; 424 425 smp2p_slpi_in: slave-kernel { 426 qcom,entry-name = "slave-kernel"; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 }; 431 432 soc: soc@0 { 433 #address-cells = <2>; 434 #size-cells = <2>; 435 ranges = <0 0 0 0 0x10 0>; 436 dma-ranges = <0 0 0 0 0x10 0>; 437 compatible = "simple-bus"; 438 439 gcc: clock-controller@100000 { 440 compatible = "qcom,gcc-sm8350"; 441 reg = <0x0 0x00100000 0x0 0x1f0000>; 442 #clock-cells = <1>; 443 #reset-cells = <1>; 444 #power-domain-cells = <1>; 445 clock-names = "bi_tcxo", "sleep_clk"; 446 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 447 }; 448 449 ipcc: mailbox@408000 { 450 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 451 reg = <0 0x00408000 0 0x1000>; 452 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-controller; 454 #interrupt-cells = <3>; 455 #mbox-cells = <2>; 456 }; 457 458 qupv3_id_0: geniqup@9c0000 { 459 compatible = "qcom,geni-se-qup"; 460 reg = <0x0 0x009c0000 0x0 0x6000>; 461 clock-names = "m-ahb", "s-ahb"; 462 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 463 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 464 #address-cells = <2>; 465 #size-cells = <2>; 466 ranges; 467 status = "disabled"; 468 469 uart2: serial@98c000 { 470 compatible = "qcom,geni-debug-uart"; 471 reg = <0 0x0098c000 0 0x4000>; 472 clock-names = "se"; 473 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&qup_uart3_default_state>; 476 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 }; 482 483 qupv3_id_1: geniqup@ac0000 { 484 compatible = "qcom,geni-se-qup"; 485 reg = <0x0 0x00ac0000 0x0 0x6000>; 486 clock-names = "m-ahb", "s-ahb"; 487 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 488 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 489 #address-cells = <2>; 490 #size-cells = <2>; 491 ranges; 492 status = "disabled"; 493 494 i2c13: i2c@a94000 { 495 compatible = "qcom,geni-i2c"; 496 reg = <0 0x00a94000 0 0x4000>; 497 clock-names = "se"; 498 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&qup_i2c13_default_state>; 501 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 }; 507 508 apps_smmu: iommu@15000000 { 509 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 510 reg = <0 0x15000000 0 0x100000>; 511 #iommu-cells = <2>; 512 #global-interrupts = <2>; 513 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 611 }; 612 613 config_noc: interconnect@1500000 { 614 compatible = "qcom,sm8350-config-noc"; 615 reg = <0 0x01500000 0 0xa580>; 616 #interconnect-cells = <1>; 617 qcom,bcm-voters = <&apps_bcm_voter>; 618 }; 619 620 mc_virt: interconnect@1580000 { 621 compatible = "qcom,sm8350-mc-virt"; 622 reg = <0 0x01580000 0 0x1000>; 623 #interconnect-cells = <1>; 624 qcom,bcm-voters = <&apps_bcm_voter>; 625 }; 626 627 system_noc: interconnect@1680000 { 628 compatible = "qcom,sm8350-system-noc"; 629 reg = <0 0x01680000 0 0x1c200>; 630 #interconnect-cells = <1>; 631 qcom,bcm-voters = <&apps_bcm_voter>; 632 }; 633 634 aggre1_noc: interconnect@16e0000 { 635 compatible = "qcom,sm8350-aggre1-noc"; 636 reg = <0 0x016e0000 0 0x1f180>; 637 #interconnect-cells = <1>; 638 qcom,bcm-voters = <&apps_bcm_voter>; 639 }; 640 641 aggre2_noc: interconnect@1700000 { 642 compatible = "qcom,sm8350-aggre2-noc"; 643 reg = <0 0x01700000 0 0x33000>; 644 #interconnect-cells = <1>; 645 qcom,bcm-voters = <&apps_bcm_voter>; 646 }; 647 648 mmss_noc: interconnect@1740000 { 649 compatible = "qcom,sm8350-mmss-noc"; 650 reg = <0 0x01740000 0 0x1f080>; 651 #interconnect-cells = <1>; 652 qcom,bcm-voters = <&apps_bcm_voter>; 653 }; 654 655 lpass_ag_noc: interconnect@3c40000 { 656 compatible = "qcom,sm8350-lpass-ag-noc"; 657 reg = <0 0x03c40000 0 0xf080>; 658 #interconnect-cells = <1>; 659 qcom,bcm-voters = <&apps_bcm_voter>; 660 }; 661 662 compute_noc: interconnect@a0c0000{ 663 compatible = "qcom,sm8350-compute-noc"; 664 reg = <0 0x0a0c0000 0 0xa180>; 665 #interconnect-cells = <1>; 666 qcom,bcm-voters = <&apps_bcm_voter>; 667 }; 668 669 ipa: ipa@1e40000 { 670 compatible = "qcom,sm8350-ipa"; 671 672 iommus = <&apps_smmu 0x5c0 0x0>, 673 <&apps_smmu 0x5c2 0x0>; 674 reg = <0 0x1e40000 0 0x8000>, 675 <0 0x1e50000 0 0x4b20>, 676 <0 0x1e04000 0 0x23000>; 677 reg-names = "ipa-reg", 678 "ipa-shared", 679 "gsi"; 680 681 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 682 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 683 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 684 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 685 interrupt-names = "ipa", 686 "gsi", 687 "ipa-clock-query", 688 "ipa-setup-ready"; 689 690 clocks = <&rpmhcc RPMH_IPA_CLK>; 691 clock-names = "core"; 692 693 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 694 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 695 interconnect-names = "memory", 696 "config"; 697 698 qcom,smem-states = <&ipa_smp2p_out 0>, 699 <&ipa_smp2p_out 1>; 700 qcom,smem-state-names = "ipa-clock-enabled-valid", 701 "ipa-clock-enabled"; 702 703 status = "disabled"; 704 }; 705 706 tcsr_mutex: hwlock@1f40000 { 707 compatible = "qcom,tcsr-mutex"; 708 reg = <0x0 0x01f40000 0x0 0x40000>; 709 #hwlock-cells = <1>; 710 }; 711 712 mpss: remoteproc@4080000 { 713 compatible = "qcom,sm8350-mpss-pas"; 714 reg = <0x0 0x04080000 0x0 0x4040>; 715 716 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 717 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 718 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 719 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 720 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 721 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 722 interrupt-names = "wdog", "fatal", "ready", "handover", 723 "stop-ack", "shutdown-ack"; 724 725 clocks = <&rpmhcc RPMH_CXO_CLK>; 726 clock-names = "xo"; 727 728 power-domains = <&rpmhpd 0>, 729 <&rpmhpd 12>; 730 power-domain-names = "cx", "mss"; 731 732 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; 733 734 memory-region = <&pil_modem_mem>; 735 736 qcom,qmp = <&aoss_qmp>; 737 738 qcom,smem-states = <&smp2p_modem_out 0>; 739 qcom,smem-state-names = "stop"; 740 741 status = "disabled"; 742 743 glink-edge { 744 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 745 IPCC_MPROC_SIGNAL_GLINK_QMP 746 IRQ_TYPE_EDGE_RISING>; 747 mboxes = <&ipcc IPCC_CLIENT_MPSS 748 IPCC_MPROC_SIGNAL_GLINK_QMP>; 749 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 750 label = "modem"; 751 qcom,remote-pid = <1>; 752 }; 753 }; 754 755 pdc: interrupt-controller@b220000 { 756 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 757 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 758 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 759 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 760 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 761 <156 716 12>; 762 #interrupt-cells = <2>; 763 interrupt-parent = <&intc>; 764 interrupt-controller; 765 }; 766 767 tsens0: thermal-sensor@c263000 { 768 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 769 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 770 <0 0x0c222000 0 0x8>; /* SROT */ 771 #qcom,sensors = <15>; 772 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 773 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-names = "uplow", "critical"; 775 #thermal-sensor-cells = <1>; 776 }; 777 778 tsens1: thermal-sensor@c265000 { 779 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 780 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 781 <0 0x0c223000 0 0x8>; /* SROT */ 782 #qcom,sensors = <14>; 783 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 784 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 785 interrupt-names = "uplow", "critical"; 786 #thermal-sensor-cells = <1>; 787 }; 788 789 aoss_qmp: power-controller@c300000 { 790 compatible = "qcom,sm8350-aoss-qmp"; 791 reg = <0 0x0c300000 0 0x400>; 792 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 793 IRQ_TYPE_EDGE_RISING>; 794 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 795 796 #clock-cells = <0>; 797 }; 798 799 sram@c3f0000 { 800 compatible = "qcom,rpmh-stats"; 801 reg = <0 0x0c3f0000 0 0x400>; 802 }; 803 804 spmi_bus: spmi@c440000 { 805 compatible = "qcom,spmi-pmic-arb"; 806 reg = <0x0 0xc440000 0x0 0x1100>, 807 <0x0 0xc600000 0x0 0x2000000>, 808 <0x0 0xe600000 0x0 0x100000>, 809 <0x0 0xe700000 0x0 0xa0000>, 810 <0x0 0xc40a000 0x0 0x26000>; 811 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 812 interrupt-names = "periph_irq"; 813 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 814 qcom,ee = <0>; 815 qcom,channel = <0>; 816 #address-cells = <2>; 817 #size-cells = <0>; 818 interrupt-controller; 819 #interrupt-cells = <4>; 820 }; 821 822 tlmm: pinctrl@f100000 { 823 compatible = "qcom,sm8350-tlmm"; 824 reg = <0 0x0f100000 0 0x300000>; 825 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 826 gpio-controller; 827 #gpio-cells = <2>; 828 interrupt-controller; 829 #interrupt-cells = <2>; 830 gpio-ranges = <&tlmm 0 0 204>; 831 wakeup-parent = <&pdc>; 832 833 qup_uart3_default_state: qup-uart3-default-state { 834 rx { 835 pins = "gpio18"; 836 function = "qup3"; 837 }; 838 tx { 839 pins = "gpio19"; 840 function = "qup3"; 841 }; 842 }; 843 844 qup_i2c13_default_state: qup-i2c13-default-state { 845 mux { 846 pins = "gpio0", "gpio1"; 847 function = "qup13"; 848 }; 849 850 config { 851 pins = "gpio0", "gpio1"; 852 drive-strength = <2>; 853 bias-pull-up; 854 }; 855 }; 856 }; 857 858 rng: rng@10d3000 { 859 compatible = "qcom,prng-ee"; 860 reg = <0 0x010d3000 0 0x1000>; 861 clocks = <&rpmhcc RPMH_HWKM_CLK>; 862 clock-names = "core"; 863 }; 864 865 intc: interrupt-controller@17a00000 { 866 compatible = "arm,gic-v3"; 867 #interrupt-cells = <3>; 868 interrupt-controller; 869 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 870 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 871 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 872 }; 873 874 timer@17c20000 { 875 compatible = "arm,armv7-timer-mem"; 876 #address-cells = <2>; 877 #size-cells = <2>; 878 ranges; 879 reg = <0x0 0x17c20000 0x0 0x1000>; 880 clock-frequency = <19200000>; 881 882 frame@17c21000 { 883 frame-number = <0>; 884 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 886 reg = <0x0 0x17c21000 0x0 0x1000>, 887 <0x0 0x17c22000 0x0 0x1000>; 888 }; 889 890 frame@17c23000 { 891 frame-number = <1>; 892 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 893 reg = <0x0 0x17c23000 0x0 0x1000>; 894 status = "disabled"; 895 }; 896 897 frame@17c25000 { 898 frame-number = <2>; 899 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 900 reg = <0x0 0x17c25000 0x0 0x1000>; 901 status = "disabled"; 902 }; 903 904 frame@17c27000 { 905 frame-number = <3>; 906 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 907 reg = <0x0 0x17c27000 0x0 0x1000>; 908 status = "disabled"; 909 }; 910 911 frame@17c29000 { 912 frame-number = <4>; 913 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 914 reg = <0x0 0x17c29000 0x0 0x1000>; 915 status = "disabled"; 916 }; 917 918 frame@17c2b000 { 919 frame-number = <5>; 920 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 921 reg = <0x0 0x17c2b000 0x0 0x1000>; 922 status = "disabled"; 923 }; 924 925 frame@17c2d000 { 926 frame-number = <6>; 927 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 928 reg = <0x0 0x17c2d000 0x0 0x1000>; 929 status = "disabled"; 930 }; 931 }; 932 933 apps_rsc: rsc@18200000 { 934 label = "apps_rsc"; 935 compatible = "qcom,rpmh-rsc"; 936 reg = <0x0 0x18200000 0x0 0x10000>, 937 <0x0 0x18210000 0x0 0x10000>, 938 <0x0 0x18220000 0x0 0x10000>; 939 reg-names = "drv-0", "drv-1", "drv-2"; 940 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 943 qcom,tcs-offset = <0xd00>; 944 qcom,drv-id = <2>; 945 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 946 <WAKE_TCS 3>, <CONTROL_TCS 1>; 947 948 rpmhcc: clock-controller { 949 compatible = "qcom,sm8350-rpmh-clk"; 950 #clock-cells = <1>; 951 clock-names = "xo"; 952 clocks = <&xo_board>; 953 }; 954 955 rpmhpd: power-controller { 956 compatible = "qcom,sm8350-rpmhpd"; 957 #power-domain-cells = <1>; 958 operating-points-v2 = <&rpmhpd_opp_table>; 959 960 rpmhpd_opp_table: opp-table { 961 compatible = "operating-points-v2"; 962 963 rpmhpd_opp_ret: opp1 { 964 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 965 }; 966 967 rpmhpd_opp_min_svs: opp2 { 968 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 969 }; 970 971 rpmhpd_opp_low_svs: opp3 { 972 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 973 }; 974 975 rpmhpd_opp_svs: opp4 { 976 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 977 }; 978 979 rpmhpd_opp_svs_l1: opp5 { 980 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 981 }; 982 983 rpmhpd_opp_nom: opp6 { 984 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 985 }; 986 987 rpmhpd_opp_nom_l1: opp7 { 988 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 989 }; 990 991 rpmhpd_opp_nom_l2: opp8 { 992 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 993 }; 994 995 rpmhpd_opp_turbo: opp9 { 996 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 997 }; 998 999 rpmhpd_opp_turbo_l1: opp10 { 1000 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1001 }; 1002 }; 1003 }; 1004 1005 apps_bcm_voter: bcm_voter { 1006 compatible = "qcom,bcm-voter"; 1007 }; 1008 }; 1009 1010 cpufreq_hw: cpufreq@18591000 { 1011 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 1012 reg = <0 0x18591000 0 0x1000>, 1013 <0 0x18592000 0 0x1000>, 1014 <0 0x18593000 0 0x1000>; 1015 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 1016 1017 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1018 clock-names = "xo", "alternate"; 1019 1020 #freq-domain-cells = <1>; 1021 }; 1022 1023 ufs_mem_hc: ufshc@1d84000 { 1024 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1025 "jedec,ufs-2.0"; 1026 reg = <0 0x01d84000 0 0x3000>; 1027 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1028 phys = <&ufs_mem_phy_lanes>; 1029 phy-names = "ufsphy"; 1030 lanes-per-direction = <2>; 1031 #reset-cells = <1>; 1032 resets = <&gcc GCC_UFS_PHY_BCR>; 1033 reset-names = "rst"; 1034 1035 power-domains = <&gcc UFS_PHY_GDSC>; 1036 1037 iommus = <&apps_smmu 0xe0 0x0>; 1038 1039 clock-names = 1040 "ref_clk", 1041 "core_clk", 1042 "bus_aggr_clk", 1043 "iface_clk", 1044 "core_clk_unipro", 1045 "ref_clk", 1046 "tx_lane0_sync_clk", 1047 "rx_lane0_sync_clk", 1048 "rx_lane1_sync_clk"; 1049 clocks = 1050 <&rpmhcc RPMH_CXO_CLK>, 1051 <&gcc GCC_UFS_PHY_AXI_CLK>, 1052 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1053 <&gcc GCC_UFS_PHY_AHB_CLK>, 1054 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1055 <&rpmhcc RPMH_CXO_CLK>, 1056 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1057 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1058 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1059 freq-table-hz = 1060 <75000000 300000000>, 1061 <75000000 300000000>, 1062 <0 0>, 1063 <0 0>, 1064 <75000000 300000000>, 1065 <0 0>, 1066 <0 0>, 1067 <75000000 300000000>, 1068 <75000000 300000000>; 1069 status = "disabled"; 1070 }; 1071 1072 ufs_mem_phy: phy@1d87000 { 1073 compatible = "qcom,sm8350-qmp-ufs-phy"; 1074 reg = <0 0x01d87000 0 0xe10>; 1075 #address-cells = <2>; 1076 #size-cells = <2>; 1077 #clock-cells = <1>; 1078 ranges; 1079 clock-names = "ref", 1080 "ref_aux"; 1081 clocks = <&rpmhcc RPMH_CXO_CLK>, 1082 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1083 1084 resets = <&ufs_mem_hc 0>; 1085 reset-names = "ufsphy"; 1086 status = "disabled"; 1087 1088 ufs_mem_phy_lanes: lanes@1d87400 { 1089 reg = <0 0x01d87400 0 0x108>, 1090 <0 0x01d87600 0 0x1e0>, 1091 <0 0x01d87c00 0 0x1dc>, 1092 <0 0x01d87800 0 0x108>, 1093 <0 0x01d87a00 0 0x1e0>; 1094 #phy-cells = <0>; 1095 #clock-cells = <0>; 1096 }; 1097 }; 1098 1099 slpi: remoteproc@5c00000 { 1100 compatible = "qcom,sm8350-slpi-pas"; 1101 reg = <0 0x05c00000 0 0x4000>; 1102 1103 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 1104 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 1105 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 1106 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 1107 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 1108 interrupt-names = "wdog", "fatal", "ready", 1109 "handover", "stop-ack"; 1110 1111 clocks = <&rpmhcc RPMH_CXO_CLK>; 1112 clock-names = "xo"; 1113 1114 power-domains = <&rpmhpd 4>, 1115 <&rpmhpd 5>; 1116 power-domain-names = "lcx", "lmx"; 1117 1118 memory-region = <&pil_slpi_mem>; 1119 1120 qcom,qmp = <&aoss_qmp>; 1121 1122 qcom,smem-states = <&smp2p_slpi_out 0>; 1123 qcom,smem-state-names = "stop"; 1124 1125 status = "disabled"; 1126 1127 glink-edge { 1128 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 1129 IPCC_MPROC_SIGNAL_GLINK_QMP 1130 IRQ_TYPE_EDGE_RISING>; 1131 mboxes = <&ipcc IPCC_CLIENT_SLPI 1132 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1133 1134 label = "slpi"; 1135 qcom,remote-pid = <3>; 1136 1137 fastrpc { 1138 compatible = "qcom,fastrpc"; 1139 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1140 label = "sdsp"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 1144 compute-cb@1 { 1145 compatible = "qcom,fastrpc-compute-cb"; 1146 reg = <1>; 1147 iommus = <&apps_smmu 0x0541 0x0>; 1148 }; 1149 1150 compute-cb@2 { 1151 compatible = "qcom,fastrpc-compute-cb"; 1152 reg = <2>; 1153 iommus = <&apps_smmu 0x0542 0x0>; 1154 }; 1155 1156 compute-cb@3 { 1157 compatible = "qcom,fastrpc-compute-cb"; 1158 reg = <3>; 1159 iommus = <&apps_smmu 0x0543 0x0>; 1160 /* note: shared-cb = <4> in downstream */ 1161 }; 1162 }; 1163 }; 1164 }; 1165 1166 cdsp: remoteproc@98900000 { 1167 compatible = "qcom,sm8350-cdsp-pas"; 1168 reg = <0 0x098900000 0 0x1400000>; 1169 1170 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1171 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1172 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1173 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1174 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1175 interrupt-names = "wdog", "fatal", "ready", 1176 "handover", "stop-ack"; 1177 1178 clocks = <&rpmhcc RPMH_CXO_CLK>; 1179 clock-names = "xo"; 1180 1181 power-domains = <&rpmhpd 0>, 1182 <&rpmhpd 10>; 1183 power-domain-names = "cx", "mxc"; 1184 1185 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; 1186 1187 memory-region = <&pil_cdsp_mem>; 1188 1189 qcom,qmp = <&aoss_qmp>; 1190 1191 qcom,smem-states = <&smp2p_cdsp_out 0>; 1192 qcom,smem-state-names = "stop"; 1193 1194 status = "disabled"; 1195 1196 glink-edge { 1197 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1198 IPCC_MPROC_SIGNAL_GLINK_QMP 1199 IRQ_TYPE_EDGE_RISING>; 1200 mboxes = <&ipcc IPCC_CLIENT_CDSP 1201 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1202 1203 label = "cdsp"; 1204 qcom,remote-pid = <5>; 1205 1206 fastrpc { 1207 compatible = "qcom,fastrpc"; 1208 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1209 label = "cdsp"; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 1213 compute-cb@1 { 1214 compatible = "qcom,fastrpc-compute-cb"; 1215 reg = <1>; 1216 iommus = <&apps_smmu 0x2161 0x0400>, 1217 <&apps_smmu 0x1181 0x0420>; 1218 }; 1219 1220 compute-cb@2 { 1221 compatible = "qcom,fastrpc-compute-cb"; 1222 reg = <2>; 1223 iommus = <&apps_smmu 0x2162 0x0400>, 1224 <&apps_smmu 0x1182 0x0420>; 1225 }; 1226 1227 compute-cb@3 { 1228 compatible = "qcom,fastrpc-compute-cb"; 1229 reg = <3>; 1230 iommus = <&apps_smmu 0x2163 0x0400>, 1231 <&apps_smmu 0x1183 0x0420>; 1232 }; 1233 1234 compute-cb@4 { 1235 compatible = "qcom,fastrpc-compute-cb"; 1236 reg = <4>; 1237 iommus = <&apps_smmu 0x2164 0x0400>, 1238 <&apps_smmu 0x1184 0x0420>; 1239 }; 1240 1241 compute-cb@5 { 1242 compatible = "qcom,fastrpc-compute-cb"; 1243 reg = <5>; 1244 iommus = <&apps_smmu 0x2165 0x0400>, 1245 <&apps_smmu 0x1185 0x0420>; 1246 }; 1247 1248 compute-cb@6 { 1249 compatible = "qcom,fastrpc-compute-cb"; 1250 reg = <6>; 1251 iommus = <&apps_smmu 0x2166 0x0400>, 1252 <&apps_smmu 0x1186 0x0420>; 1253 }; 1254 1255 compute-cb@7 { 1256 compatible = "qcom,fastrpc-compute-cb"; 1257 reg = <7>; 1258 iommus = <&apps_smmu 0x2167 0x0400>, 1259 <&apps_smmu 0x1187 0x0420>; 1260 }; 1261 1262 compute-cb@8 { 1263 compatible = "qcom,fastrpc-compute-cb"; 1264 reg = <8>; 1265 iommus = <&apps_smmu 0x2168 0x0400>, 1266 <&apps_smmu 0x1188 0x0420>; 1267 }; 1268 1269 /* note: secure cb9 in downstream */ 1270 }; 1271 }; 1272 }; 1273 1274 usb_1_hsphy: phy@88e3000 { 1275 compatible = "qcom,sm8350-usb-hs-phy", 1276 "qcom,usb-snps-hs-7nm-phy"; 1277 reg = <0 0x088e3000 0 0x400>; 1278 status = "disabled"; 1279 #phy-cells = <0>; 1280 1281 clocks = <&rpmhcc RPMH_CXO_CLK>; 1282 clock-names = "ref"; 1283 1284 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1285 }; 1286 1287 usb_2_hsphy: phy@88e4000 { 1288 compatible = "qcom,sm8250-usb-hs-phy", 1289 "qcom,usb-snps-hs-7nm-phy"; 1290 reg = <0 0x088e4000 0 0x400>; 1291 status = "disabled"; 1292 #phy-cells = <0>; 1293 1294 clocks = <&rpmhcc RPMH_CXO_CLK>; 1295 clock-names = "ref"; 1296 1297 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1298 }; 1299 1300 usb_1_qmpphy: phy-wrapper@88e9000 { 1301 compatible = "qcom,sm8350-qmp-usb3-phy"; 1302 reg = <0 0x088e9000 0 0x200>, 1303 <0 0x088e8000 0 0x20>; 1304 reg-names = "reg-base", "dp_com"; 1305 status = "disabled"; 1306 #clock-cells = <1>; 1307 #address-cells = <2>; 1308 #size-cells = <2>; 1309 ranges; 1310 1311 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1312 <&rpmhcc RPMH_CXO_CLK>, 1313 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1314 clock-names = "aux", "ref_clk_src", "com_aux"; 1315 1316 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1317 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1318 reset-names = "phy", "common"; 1319 1320 usb_1_ssphy: phy@88e9200 { 1321 reg = <0 0x088e9200 0 0x200>, 1322 <0 0x088e9400 0 0x200>, 1323 <0 0x088e9c00 0 0x400>, 1324 <0 0x088e9600 0 0x200>, 1325 <0 0x088e9800 0 0x200>, 1326 <0 0x088e9a00 0 0x100>; 1327 #phy-cells = <0>; 1328 #clock-cells = <1>; 1329 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1330 clock-names = "pipe0"; 1331 clock-output-names = "usb3_phy_pipe_clk_src"; 1332 }; 1333 }; 1334 1335 usb_2_qmpphy: phy-wrapper@88eb000 { 1336 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 1337 reg = <0 0x088eb000 0 0x200>; 1338 status = "disabled"; 1339 #clock-cells = <1>; 1340 #address-cells = <2>; 1341 #size-cells = <2>; 1342 ranges; 1343 1344 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1345 <&rpmhcc RPMH_CXO_CLK>, 1346 <&gcc GCC_USB3_SEC_CLKREF_EN>, 1347 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1348 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1349 1350 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1351 <&gcc GCC_USB3_PHY_SEC_BCR>; 1352 reset-names = "phy", "common"; 1353 1354 usb_2_ssphy: phy@88ebe00 { 1355 reg = <0 0x088ebe00 0 0x200>, 1356 <0 0x088ec000 0 0x200>, 1357 <0 0x088eb200 0 0x1100>; 1358 #phy-cells = <0>; 1359 #clock-cells = <1>; 1360 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1361 clock-names = "pipe0"; 1362 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1363 }; 1364 }; 1365 1366 dc_noc: interconnect@90c0000 { 1367 compatible = "qcom,sm8350-dc-noc"; 1368 reg = <0 0x090c0000 0 0x4200>; 1369 #interconnect-cells = <1>; 1370 qcom,bcm-voters = <&apps_bcm_voter>; 1371 }; 1372 1373 gem_noc: interconnect@9100000 { 1374 compatible = "qcom,sm8350-gem-noc"; 1375 reg = <0 0x09100000 0 0xb4000>; 1376 #interconnect-cells = <1>; 1377 qcom,bcm-voters = <&apps_bcm_voter>; 1378 }; 1379 1380 usb_1: usb@a6f8800 { 1381 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 1382 reg = <0 0x0a6f8800 0 0x400>; 1383 status = "disabled"; 1384 #address-cells = <2>; 1385 #size-cells = <2>; 1386 ranges; 1387 1388 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1389 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1390 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1391 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1392 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1393 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1394 "sleep"; 1395 1396 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1397 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1398 assigned-clock-rates = <19200000>, <200000000>; 1399 1400 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1401 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1402 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1403 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1404 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1405 "dm_hs_phy_irq", "ss_phy_irq"; 1406 1407 power-domains = <&gcc USB30_PRIM_GDSC>; 1408 1409 resets = <&gcc GCC_USB30_PRIM_BCR>; 1410 1411 usb_1_dwc3: usb@a600000 { 1412 compatible = "snps,dwc3"; 1413 reg = <0 0x0a600000 0 0xcd00>; 1414 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1415 iommus = <&apps_smmu 0x0 0x0>; 1416 snps,dis_u2_susphy_quirk; 1417 snps,dis_enblslpm_quirk; 1418 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1419 phy-names = "usb2-phy", "usb3-phy"; 1420 }; 1421 }; 1422 1423 usb_2: usb@a8f8800 { 1424 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 1425 reg = <0 0x0a8f8800 0 0x400>; 1426 status = "disabled"; 1427 #address-cells = <2>; 1428 #size-cells = <2>; 1429 ranges; 1430 1431 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1432 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1433 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1434 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1435 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1436 <&gcc GCC_USB3_SEC_CLKREF_EN>; 1437 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1438 "sleep", "xo"; 1439 1440 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1441 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1442 assigned-clock-rates = <19200000>, <200000000>; 1443 1444 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1445 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 1446 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 1447 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 1448 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1449 "dm_hs_phy_irq", "ss_phy_irq"; 1450 1451 power-domains = <&gcc USB30_SEC_GDSC>; 1452 1453 resets = <&gcc GCC_USB30_SEC_BCR>; 1454 1455 usb_2_dwc3: usb@a800000 { 1456 compatible = "snps,dwc3"; 1457 reg = <0 0x0a800000 0 0xcd00>; 1458 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1459 iommus = <&apps_smmu 0x20 0x0>; 1460 snps,dis_u2_susphy_quirk; 1461 snps,dis_enblslpm_quirk; 1462 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1463 phy-names = "usb2-phy", "usb3-phy"; 1464 }; 1465 }; 1466 1467 adsp: remoteproc@17300000 { 1468 compatible = "qcom,sm8350-adsp-pas"; 1469 reg = <0 0x17300000 0 0x100>; 1470 1471 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1472 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1473 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1474 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1475 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1476 interrupt-names = "wdog", "fatal", "ready", 1477 "handover", "stop-ack"; 1478 1479 clocks = <&rpmhcc RPMH_CXO_CLK>; 1480 clock-names = "xo"; 1481 1482 power-domains = <&rpmhpd 4>, 1483 <&rpmhpd 5>; 1484 power-domain-names = "lcx", "lmx"; 1485 1486 memory-region = <&pil_adsp_mem>; 1487 1488 qcom,qmp = <&aoss_qmp>; 1489 1490 qcom,smem-states = <&smp2p_adsp_out 0>; 1491 qcom,smem-state-names = "stop"; 1492 1493 status = "disabled"; 1494 1495 glink-edge { 1496 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1497 IPCC_MPROC_SIGNAL_GLINK_QMP 1498 IRQ_TYPE_EDGE_RISING>; 1499 mboxes = <&ipcc IPCC_CLIENT_LPASS 1500 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1501 1502 label = "lpass"; 1503 qcom,remote-pid = <2>; 1504 1505 fastrpc { 1506 compatible = "qcom,fastrpc"; 1507 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1508 label = "adsp"; 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 1512 compute-cb@3 { 1513 compatible = "qcom,fastrpc-compute-cb"; 1514 reg = <3>; 1515 iommus = <&apps_smmu 0x1803 0x0>; 1516 }; 1517 1518 compute-cb@4 { 1519 compatible = "qcom,fastrpc-compute-cb"; 1520 reg = <4>; 1521 iommus = <&apps_smmu 0x1804 0x0>; 1522 }; 1523 1524 compute-cb@5 { 1525 compatible = "qcom,fastrpc-compute-cb"; 1526 reg = <5>; 1527 iommus = <&apps_smmu 0x1805 0x0>; 1528 }; 1529 }; 1530 }; 1531 }; 1532 }; 1533 1534 thermal_zones: thermal-zones { 1535 cpu0-thermal { 1536 polling-delay-passive = <250>; 1537 polling-delay = <1000>; 1538 1539 thermal-sensors = <&tsens0 1>; 1540 1541 trips { 1542 cpu0_alert0: trip-point0 { 1543 temperature = <90000>; 1544 hysteresis = <2000>; 1545 type = "passive"; 1546 }; 1547 1548 cpu0_alert1: trip-point1 { 1549 temperature = <95000>; 1550 hysteresis = <2000>; 1551 type = "passive"; 1552 }; 1553 1554 cpu0_crit: cpu_crit { 1555 temperature = <110000>; 1556 hysteresis = <1000>; 1557 type = "critical"; 1558 }; 1559 }; 1560 1561 cooling-maps { 1562 map0 { 1563 trip = <&cpu0_alert0>; 1564 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1565 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1566 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1567 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1568 }; 1569 map1 { 1570 trip = <&cpu0_alert1>; 1571 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1572 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1573 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1574 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1575 }; 1576 }; 1577 }; 1578 1579 cpu1-thermal { 1580 polling-delay-passive = <250>; 1581 polling-delay = <1000>; 1582 1583 thermal-sensors = <&tsens0 2>; 1584 1585 trips { 1586 cpu1_alert0: trip-point0 { 1587 temperature = <90000>; 1588 hysteresis = <2000>; 1589 type = "passive"; 1590 }; 1591 1592 cpu1_alert1: trip-point1 { 1593 temperature = <95000>; 1594 hysteresis = <2000>; 1595 type = "passive"; 1596 }; 1597 1598 cpu1_crit: cpu_crit { 1599 temperature = <110000>; 1600 hysteresis = <1000>; 1601 type = "critical"; 1602 }; 1603 }; 1604 1605 cooling-maps { 1606 map0 { 1607 trip = <&cpu1_alert0>; 1608 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1609 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1610 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1611 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1612 }; 1613 map1 { 1614 trip = <&cpu1_alert1>; 1615 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1616 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1617 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1618 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1619 }; 1620 }; 1621 }; 1622 1623 cpu2-thermal { 1624 polling-delay-passive = <250>; 1625 polling-delay = <1000>; 1626 1627 thermal-sensors = <&tsens0 3>; 1628 1629 trips { 1630 cpu2_alert0: trip-point0 { 1631 temperature = <90000>; 1632 hysteresis = <2000>; 1633 type = "passive"; 1634 }; 1635 1636 cpu2_alert1: trip-point1 { 1637 temperature = <95000>; 1638 hysteresis = <2000>; 1639 type = "passive"; 1640 }; 1641 1642 cpu2_crit: cpu_crit { 1643 temperature = <110000>; 1644 hysteresis = <1000>; 1645 type = "critical"; 1646 }; 1647 }; 1648 1649 cooling-maps { 1650 map0 { 1651 trip = <&cpu2_alert0>; 1652 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1653 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1654 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1655 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1656 }; 1657 map1 { 1658 trip = <&cpu2_alert1>; 1659 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1660 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1661 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1662 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1663 }; 1664 }; 1665 }; 1666 1667 cpu3-thermal { 1668 polling-delay-passive = <250>; 1669 polling-delay = <1000>; 1670 1671 thermal-sensors = <&tsens0 4>; 1672 1673 trips { 1674 cpu3_alert0: trip-point0 { 1675 temperature = <90000>; 1676 hysteresis = <2000>; 1677 type = "passive"; 1678 }; 1679 1680 cpu3_alert1: trip-point1 { 1681 temperature = <95000>; 1682 hysteresis = <2000>; 1683 type = "passive"; 1684 }; 1685 1686 cpu3_crit: cpu_crit { 1687 temperature = <110000>; 1688 hysteresis = <1000>; 1689 type = "critical"; 1690 }; 1691 }; 1692 1693 cooling-maps { 1694 map0 { 1695 trip = <&cpu3_alert0>; 1696 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1697 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1698 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1699 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1700 }; 1701 map1 { 1702 trip = <&cpu3_alert1>; 1703 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1704 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1705 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1706 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1707 }; 1708 }; 1709 }; 1710 1711 cpu4-top-thermal { 1712 polling-delay-passive = <250>; 1713 polling-delay = <1000>; 1714 1715 thermal-sensors = <&tsens0 7>; 1716 1717 trips { 1718 cpu4_top_alert0: trip-point0 { 1719 temperature = <90000>; 1720 hysteresis = <2000>; 1721 type = "passive"; 1722 }; 1723 1724 cpu4_top_alert1: trip-point1 { 1725 temperature = <95000>; 1726 hysteresis = <2000>; 1727 type = "passive"; 1728 }; 1729 1730 cpu4_top_crit: cpu_crit { 1731 temperature = <110000>; 1732 hysteresis = <1000>; 1733 type = "critical"; 1734 }; 1735 }; 1736 1737 cooling-maps { 1738 map0 { 1739 trip = <&cpu4_top_alert0>; 1740 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1741 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1742 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1743 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1744 }; 1745 map1 { 1746 trip = <&cpu4_top_alert1>; 1747 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1748 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1749 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1750 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1751 }; 1752 }; 1753 }; 1754 1755 cpu5-top-thermal { 1756 polling-delay-passive = <250>; 1757 polling-delay = <1000>; 1758 1759 thermal-sensors = <&tsens0 8>; 1760 1761 trips { 1762 cpu5_top_alert0: trip-point0 { 1763 temperature = <90000>; 1764 hysteresis = <2000>; 1765 type = "passive"; 1766 }; 1767 1768 cpu5_top_alert1: trip-point1 { 1769 temperature = <95000>; 1770 hysteresis = <2000>; 1771 type = "passive"; 1772 }; 1773 1774 cpu5_top_crit: cpu_crit { 1775 temperature = <110000>; 1776 hysteresis = <1000>; 1777 type = "critical"; 1778 }; 1779 }; 1780 1781 cooling-maps { 1782 map0 { 1783 trip = <&cpu5_top_alert0>; 1784 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1785 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1786 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1787 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1788 }; 1789 map1 { 1790 trip = <&cpu5_top_alert1>; 1791 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1792 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1793 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1794 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1795 }; 1796 }; 1797 }; 1798 1799 cpu6-top-thermal { 1800 polling-delay-passive = <250>; 1801 polling-delay = <1000>; 1802 1803 thermal-sensors = <&tsens0 9>; 1804 1805 trips { 1806 cpu6_top_alert0: trip-point0 { 1807 temperature = <90000>; 1808 hysteresis = <2000>; 1809 type = "passive"; 1810 }; 1811 1812 cpu6_top_alert1: trip-point1 { 1813 temperature = <95000>; 1814 hysteresis = <2000>; 1815 type = "passive"; 1816 }; 1817 1818 cpu6_top_crit: cpu_crit { 1819 temperature = <110000>; 1820 hysteresis = <1000>; 1821 type = "critical"; 1822 }; 1823 }; 1824 1825 cooling-maps { 1826 map0 { 1827 trip = <&cpu6_top_alert0>; 1828 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1829 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1830 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1831 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1832 }; 1833 map1 { 1834 trip = <&cpu6_top_alert1>; 1835 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1837 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1838 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1839 }; 1840 }; 1841 }; 1842 1843 cpu7-top-thermal { 1844 polling-delay-passive = <250>; 1845 polling-delay = <1000>; 1846 1847 thermal-sensors = <&tsens0 10>; 1848 1849 trips { 1850 cpu7_top_alert0: trip-point0 { 1851 temperature = <90000>; 1852 hysteresis = <2000>; 1853 type = "passive"; 1854 }; 1855 1856 cpu7_top_alert1: trip-point1 { 1857 temperature = <95000>; 1858 hysteresis = <2000>; 1859 type = "passive"; 1860 }; 1861 1862 cpu7_top_crit: cpu_crit { 1863 temperature = <110000>; 1864 hysteresis = <1000>; 1865 type = "critical"; 1866 }; 1867 }; 1868 1869 cooling-maps { 1870 map0 { 1871 trip = <&cpu7_top_alert0>; 1872 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1873 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1874 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1875 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1876 }; 1877 map1 { 1878 trip = <&cpu7_top_alert1>; 1879 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1880 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1881 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1882 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1883 }; 1884 }; 1885 }; 1886 1887 cpu4-bottom-thermal { 1888 polling-delay-passive = <250>; 1889 polling-delay = <1000>; 1890 1891 thermal-sensors = <&tsens0 11>; 1892 1893 trips { 1894 cpu4_bottom_alert0: trip-point0 { 1895 temperature = <90000>; 1896 hysteresis = <2000>; 1897 type = "passive"; 1898 }; 1899 1900 cpu4_bottom_alert1: trip-point1 { 1901 temperature = <95000>; 1902 hysteresis = <2000>; 1903 type = "passive"; 1904 }; 1905 1906 cpu4_bottom_crit: cpu_crit { 1907 temperature = <110000>; 1908 hysteresis = <1000>; 1909 type = "critical"; 1910 }; 1911 }; 1912 1913 cooling-maps { 1914 map0 { 1915 trip = <&cpu4_bottom_alert0>; 1916 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1917 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1918 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1919 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1920 }; 1921 map1 { 1922 trip = <&cpu4_bottom_alert1>; 1923 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1924 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1925 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1926 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1927 }; 1928 }; 1929 }; 1930 1931 cpu5-bottom-thermal { 1932 polling-delay-passive = <250>; 1933 polling-delay = <1000>; 1934 1935 thermal-sensors = <&tsens0 12>; 1936 1937 trips { 1938 cpu5_bottom_alert0: trip-point0 { 1939 temperature = <90000>; 1940 hysteresis = <2000>; 1941 type = "passive"; 1942 }; 1943 1944 cpu5_bottom_alert1: trip-point1 { 1945 temperature = <95000>; 1946 hysteresis = <2000>; 1947 type = "passive"; 1948 }; 1949 1950 cpu5_bottom_crit: cpu_crit { 1951 temperature = <110000>; 1952 hysteresis = <1000>; 1953 type = "critical"; 1954 }; 1955 }; 1956 1957 cooling-maps { 1958 map0 { 1959 trip = <&cpu5_bottom_alert0>; 1960 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1961 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1962 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1963 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1964 }; 1965 map1 { 1966 trip = <&cpu5_bottom_alert1>; 1967 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1968 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1969 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1970 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1971 }; 1972 }; 1973 }; 1974 1975 cpu6-bottom-thermal { 1976 polling-delay-passive = <250>; 1977 polling-delay = <1000>; 1978 1979 thermal-sensors = <&tsens0 13>; 1980 1981 trips { 1982 cpu6_bottom_alert0: trip-point0 { 1983 temperature = <90000>; 1984 hysteresis = <2000>; 1985 type = "passive"; 1986 }; 1987 1988 cpu6_bottom_alert1: trip-point1 { 1989 temperature = <95000>; 1990 hysteresis = <2000>; 1991 type = "passive"; 1992 }; 1993 1994 cpu6_bottom_crit: cpu_crit { 1995 temperature = <110000>; 1996 hysteresis = <1000>; 1997 type = "critical"; 1998 }; 1999 }; 2000 2001 cooling-maps { 2002 map0 { 2003 trip = <&cpu6_bottom_alert0>; 2004 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2005 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2006 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2007 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2008 }; 2009 map1 { 2010 trip = <&cpu6_bottom_alert1>; 2011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2015 }; 2016 }; 2017 }; 2018 2019 cpu7-bottom-thermal { 2020 polling-delay-passive = <250>; 2021 polling-delay = <1000>; 2022 2023 thermal-sensors = <&tsens0 14>; 2024 2025 trips { 2026 cpu7_bottom_alert0: trip-point0 { 2027 temperature = <90000>; 2028 hysteresis = <2000>; 2029 type = "passive"; 2030 }; 2031 2032 cpu7_bottom_alert1: trip-point1 { 2033 temperature = <95000>; 2034 hysteresis = <2000>; 2035 type = "passive"; 2036 }; 2037 2038 cpu7_bottom_crit: cpu_crit { 2039 temperature = <110000>; 2040 hysteresis = <1000>; 2041 type = "critical"; 2042 }; 2043 }; 2044 2045 cooling-maps { 2046 map0 { 2047 trip = <&cpu7_bottom_alert0>; 2048 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2049 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2050 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2051 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2052 }; 2053 map1 { 2054 trip = <&cpu7_bottom_alert1>; 2055 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2057 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2058 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2059 }; 2060 }; 2061 }; 2062 2063 aoss0-thermal { 2064 polling-delay-passive = <250>; 2065 polling-delay = <1000>; 2066 2067 thermal-sensors = <&tsens0 0>; 2068 2069 trips { 2070 aoss0_alert0: trip-point0 { 2071 temperature = <90000>; 2072 hysteresis = <2000>; 2073 type = "hot"; 2074 }; 2075 }; 2076 }; 2077 2078 cluster0-thermal { 2079 polling-delay-passive = <250>; 2080 polling-delay = <1000>; 2081 2082 thermal-sensors = <&tsens0 5>; 2083 2084 trips { 2085 cluster0_alert0: trip-point0 { 2086 temperature = <90000>; 2087 hysteresis = <2000>; 2088 type = "hot"; 2089 }; 2090 cluster0_crit: cluster0_crit { 2091 temperature = <110000>; 2092 hysteresis = <2000>; 2093 type = "critical"; 2094 }; 2095 }; 2096 }; 2097 2098 cluster1-thermal { 2099 polling-delay-passive = <250>; 2100 polling-delay = <1000>; 2101 2102 thermal-sensors = <&tsens0 6>; 2103 2104 trips { 2105 cluster1_alert0: trip-point0 { 2106 temperature = <90000>; 2107 hysteresis = <2000>; 2108 type = "hot"; 2109 }; 2110 cluster1_crit: cluster1_crit { 2111 temperature = <110000>; 2112 hysteresis = <2000>; 2113 type = "critical"; 2114 }; 2115 }; 2116 }; 2117 2118 aoss1-thermal { 2119 polling-delay-passive = <250>; 2120 polling-delay = <1000>; 2121 2122 thermal-sensors = <&tsens1 0>; 2123 2124 trips { 2125 aoss1_alert0: trip-point0 { 2126 temperature = <90000>; 2127 hysteresis = <2000>; 2128 type = "hot"; 2129 }; 2130 }; 2131 }; 2132 2133 gpu-thermal-top { 2134 polling-delay-passive = <250>; 2135 polling-delay = <1000>; 2136 2137 thermal-sensors = <&tsens1 1>; 2138 2139 trips { 2140 gpu1_alert0: trip-point0 { 2141 temperature = <90000>; 2142 hysteresis = <1000>; 2143 type = "hot"; 2144 }; 2145 }; 2146 }; 2147 2148 gpu-thermal-bottom { 2149 polling-delay-passive = <250>; 2150 polling-delay = <1000>; 2151 2152 thermal-sensors = <&tsens1 2>; 2153 2154 trips { 2155 gpu2_alert0: trip-point0 { 2156 temperature = <90000>; 2157 hysteresis = <1000>; 2158 type = "hot"; 2159 }; 2160 }; 2161 }; 2162 2163 nspss1-thermal { 2164 polling-delay-passive = <250>; 2165 polling-delay = <1000>; 2166 2167 thermal-sensors = <&tsens1 3>; 2168 2169 trips { 2170 nspss1_alert0: trip-point0 { 2171 temperature = <90000>; 2172 hysteresis = <1000>; 2173 type = "hot"; 2174 }; 2175 }; 2176 }; 2177 2178 nspss2-thermal { 2179 polling-delay-passive = <250>; 2180 polling-delay = <1000>; 2181 2182 thermal-sensors = <&tsens1 4>; 2183 2184 trips { 2185 nspss2_alert0: trip-point0 { 2186 temperature = <90000>; 2187 hysteresis = <1000>; 2188 type = "hot"; 2189 }; 2190 }; 2191 }; 2192 2193 nspss3-thermal { 2194 polling-delay-passive = <250>; 2195 polling-delay = <1000>; 2196 2197 thermal-sensors = <&tsens1 5>; 2198 2199 trips { 2200 nspss3_alert0: trip-point0 { 2201 temperature = <90000>; 2202 hysteresis = <1000>; 2203 type = "hot"; 2204 }; 2205 }; 2206 }; 2207 2208 video-thermal { 2209 polling-delay-passive = <250>; 2210 polling-delay = <1000>; 2211 2212 thermal-sensors = <&tsens1 6>; 2213 2214 trips { 2215 video_alert0: trip-point0 { 2216 temperature = <90000>; 2217 hysteresis = <2000>; 2218 type = "hot"; 2219 }; 2220 }; 2221 }; 2222 2223 mem-thermal { 2224 polling-delay-passive = <250>; 2225 polling-delay = <1000>; 2226 2227 thermal-sensors = <&tsens1 7>; 2228 2229 trips { 2230 mem_alert0: trip-point0 { 2231 temperature = <90000>; 2232 hysteresis = <2000>; 2233 type = "hot"; 2234 }; 2235 }; 2236 }; 2237 2238 modem1-thermal-top { 2239 polling-delay-passive = <250>; 2240 polling-delay = <1000>; 2241 2242 thermal-sensors = <&tsens1 8>; 2243 2244 trips { 2245 modem1_alert0: trip-point0 { 2246 temperature = <90000>; 2247 hysteresis = <2000>; 2248 type = "hot"; 2249 }; 2250 }; 2251 }; 2252 2253 modem2-thermal-top { 2254 polling-delay-passive = <250>; 2255 polling-delay = <1000>; 2256 2257 thermal-sensors = <&tsens1 9>; 2258 2259 trips { 2260 modem2_alert0: trip-point0 { 2261 temperature = <90000>; 2262 hysteresis = <2000>; 2263 type = "hot"; 2264 }; 2265 }; 2266 }; 2267 2268 modem3-thermal-top { 2269 polling-delay-passive = <250>; 2270 polling-delay = <1000>; 2271 2272 thermal-sensors = <&tsens1 10>; 2273 2274 trips { 2275 modem3_alert0: trip-point0 { 2276 temperature = <90000>; 2277 hysteresis = <2000>; 2278 type = "hot"; 2279 }; 2280 }; 2281 }; 2282 2283 modem4-thermal-top { 2284 polling-delay-passive = <250>; 2285 polling-delay = <1000>; 2286 2287 thermal-sensors = <&tsens1 11>; 2288 2289 trips { 2290 modem4_alert0: trip-point0 { 2291 temperature = <90000>; 2292 hysteresis = <2000>; 2293 type = "hot"; 2294 }; 2295 }; 2296 }; 2297 2298 camera-thermal-top { 2299 polling-delay-passive = <250>; 2300 polling-delay = <1000>; 2301 2302 thermal-sensors = <&tsens1 12>; 2303 2304 trips { 2305 camera1_alert0: trip-point0 { 2306 temperature = <90000>; 2307 hysteresis = <2000>; 2308 type = "hot"; 2309 }; 2310 }; 2311 }; 2312 2313 camera-thermal-bottom { 2314 polling-delay-passive = <250>; 2315 polling-delay = <1000>; 2316 2317 thermal-sensors = <&tsens1 13>; 2318 2319 trips { 2320 camera2_alert0: trip-point0 { 2321 temperature = <90000>; 2322 hysteresis = <2000>; 2323 type = "hot"; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 timer { 2330 compatible = "arm,armv8-timer"; 2331 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2332 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2333 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2334 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2335 }; 2336}; 2337