1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/interconnect/qcom,sm8350.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <38400000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32000>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo685"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 #cooling-cells = <2>; 53 L2_0: l2-cache { 54 compatible = "cache"; 55 next-level-cache = <&L3_0>; 56 L3_0: l3-cache { 57 compatible = "cache"; 58 }; 59 }; 60 }; 61 62 CPU1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo685"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_100>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 #cooling-cells = <2>; 72 L2_100: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 }; 76 }; 77 78 CPU2: cpu@200 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo685"; 81 reg = <0x0 0x200>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_200>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD2>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_200: l2-cache { 89 compatible = "cache"; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo685"; 97 reg = <0x0 0x300>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_300>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 power-domains = <&CPU_PD3>; 102 power-domain-names = "psci"; 103 #cooling-cells = <2>; 104 L2_300: l2-cache { 105 compatible = "cache"; 106 next-level-cache = <&L3_0>; 107 }; 108 }; 109 110 CPU4: cpu@400 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo685"; 113 reg = <0x0 0x400>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_400>; 116 qcom,freq-domain = <&cpufreq_hw 1>; 117 power-domains = <&CPU_PD4>; 118 power-domain-names = "psci"; 119 #cooling-cells = <2>; 120 L2_400: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU5: cpu@500 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo685"; 129 reg = <0x0 0x500>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_500>; 132 qcom,freq-domain = <&cpufreq_hw 1>; 133 power-domains = <&CPU_PD5>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 L2_500: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 }; 140 141 }; 142 143 CPU6: cpu@600 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo685"; 146 reg = <0x0 0x600>; 147 enable-method = "psci"; 148 next-level-cache = <&L2_600>; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 power-domains = <&CPU_PD6>; 151 power-domain-names = "psci"; 152 #cooling-cells = <2>; 153 L2_600: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU7: cpu@700 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo685"; 162 reg = <0x0 0x700>; 163 enable-method = "psci"; 164 next-level-cache = <&L2_700>; 165 qcom,freq-domain = <&cpufreq_hw 2>; 166 power-domains = <&CPU_PD7>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 L2_700: l2-cache { 170 compatible = "cache"; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 cpu-map { 176 cluster0 { 177 core0 { 178 cpu = <&CPU0>; 179 }; 180 181 core1 { 182 cpu = <&CPU1>; 183 }; 184 185 core2 { 186 cpu = <&CPU2>; 187 }; 188 189 core3 { 190 cpu = <&CPU3>; 191 }; 192 193 core4 { 194 cpu = <&CPU4>; 195 }; 196 197 core5 { 198 cpu = <&CPU5>; 199 }; 200 201 core6 { 202 cpu = <&CPU6>; 203 }; 204 205 core7 { 206 cpu = <&CPU7>; 207 }; 208 }; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 215 compatible = "arm,idle-state"; 216 idle-state-name = "silver-rail-power-collapse"; 217 arm,psci-suspend-param = <0x40000004>; 218 entry-latency-us = <355>; 219 exit-latency-us = <909>; 220 min-residency-us = <3934>; 221 local-timer-stop; 222 }; 223 224 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 225 compatible = "arm,idle-state"; 226 idle-state-name = "gold-rail-power-collapse"; 227 arm,psci-suspend-param = <0x40000004>; 228 entry-latency-us = <241>; 229 exit-latency-us = <1461>; 230 min-residency-us = <4488>; 231 local-timer-stop; 232 }; 233 }; 234 235 domain-idle-states { 236 CLUSTER_SLEEP_0: cluster-sleep-0 { 237 compatible = "domain-idle-state"; 238 idle-state-name = "cluster-power-collapse"; 239 arm,psci-suspend-param = <0x4100c344>; 240 entry-latency-us = <3263>; 241 exit-latency-us = <6562>; 242 min-residency-us = <9987>; 243 local-timer-stop; 244 }; 245 }; 246 }; 247 248 firmware { 249 scm: scm { 250 compatible = "qcom,scm-sm8350", "qcom,scm"; 251 #reset-cells = <1>; 252 }; 253 }; 254 255 memory@80000000 { 256 device_type = "memory"; 257 /* We expect the bootloader to fill in the size */ 258 reg = <0x0 0x80000000 0x0 0x0>; 259 }; 260 261 pmu { 262 compatible = "arm,armv8-pmuv3"; 263 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 264 }; 265 266 psci { 267 compatible = "arm,psci-1.0"; 268 method = "smc"; 269 270 CPU_PD0: cpu0 { 271 #power-domain-cells = <0>; 272 power-domains = <&CLUSTER_PD>; 273 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 274 }; 275 276 CPU_PD1: cpu1 { 277 #power-domain-cells = <0>; 278 power-domains = <&CLUSTER_PD>; 279 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 280 }; 281 282 CPU_PD2: cpu2 { 283 #power-domain-cells = <0>; 284 power-domains = <&CLUSTER_PD>; 285 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 286 }; 287 288 CPU_PD3: cpu3 { 289 #power-domain-cells = <0>; 290 power-domains = <&CLUSTER_PD>; 291 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 292 }; 293 294 CPU_PD4: cpu4 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&BIG_CPU_SLEEP_0>; 298 }; 299 300 CPU_PD5: cpu5 { 301 #power-domain-cells = <0>; 302 power-domains = <&CLUSTER_PD>; 303 domain-idle-states = <&BIG_CPU_SLEEP_0>; 304 }; 305 306 CPU_PD6: cpu6 { 307 #power-domain-cells = <0>; 308 power-domains = <&CLUSTER_PD>; 309 domain-idle-states = <&BIG_CPU_SLEEP_0>; 310 }; 311 312 CPU_PD7: cpu7 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&BIG_CPU_SLEEP_0>; 316 }; 317 318 CLUSTER_PD: cpu-cluster0 { 319 #power-domain-cells = <0>; 320 domain-idle-states = <&CLUSTER_SLEEP_0>; 321 }; 322 }; 323 324 reserved_memory: reserved-memory { 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges; 328 329 hyp_mem: memory@80000000 { 330 reg = <0x0 0x80000000 0x0 0x600000>; 331 no-map; 332 }; 333 334 xbl_aop_mem: memory@80700000 { 335 no-map; 336 reg = <0x0 0x80700000 0x0 0x160000>; 337 }; 338 339 cmd_db: memory@80860000 { 340 compatible = "qcom,cmd-db"; 341 reg = <0x0 0x80860000 0x0 0x20000>; 342 no-map; 343 }; 344 345 reserved_xbl_uefi_log: memory@80880000 { 346 reg = <0x0 0x80880000 0x0 0x14000>; 347 no-map; 348 }; 349 350 smem_mem: memory@80900000 { 351 reg = <0x0 0x80900000 0x0 0x200000>; 352 no-map; 353 }; 354 355 cpucp_fw_mem: memory@80b00000 { 356 reg = <0x0 0x80b00000 0x0 0x100000>; 357 no-map; 358 }; 359 360 cdsp_secure_heap: memory@80c00000 { 361 reg = <0x0 0x80c00000 0x0 0x4600000>; 362 no-map; 363 }; 364 365 pil_camera_mem: mmeory@85200000 { 366 reg = <0x0 0x85200000 0x0 0x500000>; 367 no-map; 368 }; 369 370 pil_video_mem: memory@85700000 { 371 reg = <0x0 0x85700000 0x0 0x500000>; 372 no-map; 373 }; 374 375 pil_cvp_mem: memory@85c00000 { 376 reg = <0x0 0x85c00000 0x0 0x500000>; 377 no-map; 378 }; 379 380 pil_adsp_mem: memory@86100000 { 381 reg = <0x0 0x86100000 0x0 0x2100000>; 382 no-map; 383 }; 384 385 pil_slpi_mem: memory@88200000 { 386 reg = <0x0 0x88200000 0x0 0x1500000>; 387 no-map; 388 }; 389 390 pil_cdsp_mem: memory@89700000 { 391 reg = <0x0 0x89700000 0x0 0x1e00000>; 392 no-map; 393 }; 394 395 pil_ipa_fw_mem: memory@8b500000 { 396 reg = <0x0 0x8b500000 0x0 0x10000>; 397 no-map; 398 }; 399 400 pil_ipa_gsi_mem: memory@8b510000 { 401 reg = <0x0 0x8b510000 0x0 0xa000>; 402 no-map; 403 }; 404 405 pil_gpu_mem: memory@8b51a000 { 406 reg = <0x0 0x8b51a000 0x0 0x2000>; 407 no-map; 408 }; 409 410 pil_spss_mem: memory@8b600000 { 411 reg = <0x0 0x8b600000 0x0 0x100000>; 412 no-map; 413 }; 414 415 pil_modem_mem: memory@8b800000 { 416 reg = <0x0 0x8b800000 0x0 0x10000000>; 417 no-map; 418 }; 419 420 rmtfs_mem: memory@9b800000 { 421 compatible = "qcom,rmtfs-mem"; 422 reg = <0x0 0x9b800000 0x0 0x280000>; 423 no-map; 424 425 qcom,client-id = <1>; 426 qcom,vmid = <15>; 427 }; 428 429 hyp_reserved_mem: memory@d0000000 { 430 reg = <0x0 0xd0000000 0x0 0x800000>; 431 no-map; 432 }; 433 434 pil_trustedvm_mem: memory@d0800000 { 435 reg = <0x0 0xd0800000 0x0 0x76f7000>; 436 no-map; 437 }; 438 439 qrtr_shbuf: memory@d7ef7000 { 440 reg = <0x0 0xd7ef7000 0x0 0x9000>; 441 no-map; 442 }; 443 444 chan0_shbuf: memory@d7f00000 { 445 reg = <0x0 0xd7f00000 0x0 0x80000>; 446 no-map; 447 }; 448 449 chan1_shbuf: memory@d7f80000 { 450 reg = <0x0 0xd7f80000 0x0 0x80000>; 451 no-map; 452 }; 453 454 removed_mem: memory@d8800000 { 455 reg = <0x0 0xd8800000 0x0 0x6800000>; 456 no-map; 457 }; 458 }; 459 460 smem: qcom,smem { 461 compatible = "qcom,smem"; 462 memory-region = <&smem_mem>; 463 hwlocks = <&tcsr_mutex 3>; 464 }; 465 466 smp2p-adsp { 467 compatible = "qcom,smp2p"; 468 qcom,smem = <443>, <429>; 469 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 470 IPCC_MPROC_SIGNAL_SMP2P 471 IRQ_TYPE_EDGE_RISING>; 472 mboxes = <&ipcc IPCC_CLIENT_LPASS 473 IPCC_MPROC_SIGNAL_SMP2P>; 474 475 qcom,local-pid = <0>; 476 qcom,remote-pid = <2>; 477 478 smp2p_adsp_out: master-kernel { 479 qcom,entry-name = "master-kernel"; 480 #qcom,smem-state-cells = <1>; 481 }; 482 483 smp2p_adsp_in: slave-kernel { 484 qcom,entry-name = "slave-kernel"; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 }; 488 }; 489 490 smp2p-cdsp { 491 compatible = "qcom,smp2p"; 492 qcom,smem = <94>, <432>; 493 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 494 IPCC_MPROC_SIGNAL_SMP2P 495 IRQ_TYPE_EDGE_RISING>; 496 mboxes = <&ipcc IPCC_CLIENT_CDSP 497 IPCC_MPROC_SIGNAL_SMP2P>; 498 499 qcom,local-pid = <0>; 500 qcom,remote-pid = <5>; 501 502 smp2p_cdsp_out: master-kernel { 503 qcom,entry-name = "master-kernel"; 504 #qcom,smem-state-cells = <1>; 505 }; 506 507 smp2p_cdsp_in: slave-kernel { 508 qcom,entry-name = "slave-kernel"; 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 }; 512 }; 513 514 smp2p-modem { 515 compatible = "qcom,smp2p"; 516 qcom,smem = <435>, <428>; 517 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 518 IPCC_MPROC_SIGNAL_SMP2P 519 IRQ_TYPE_EDGE_RISING>; 520 mboxes = <&ipcc IPCC_CLIENT_MPSS 521 IPCC_MPROC_SIGNAL_SMP2P>; 522 523 qcom,local-pid = <0>; 524 qcom,remote-pid = <1>; 525 526 smp2p_modem_out: master-kernel { 527 qcom,entry-name = "master-kernel"; 528 #qcom,smem-state-cells = <1>; 529 }; 530 531 smp2p_modem_in: slave-kernel { 532 qcom,entry-name = "slave-kernel"; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 }; 536 537 ipa_smp2p_out: ipa-ap-to-modem { 538 qcom,entry-name = "ipa"; 539 #qcom,smem-state-cells = <1>; 540 }; 541 542 ipa_smp2p_in: ipa-modem-to-ap { 543 qcom,entry-name = "ipa"; 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 }; 547 }; 548 549 smp2p-slpi { 550 compatible = "qcom,smp2p"; 551 qcom,smem = <481>, <430>; 552 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 553 IPCC_MPROC_SIGNAL_SMP2P 554 IRQ_TYPE_EDGE_RISING>; 555 mboxes = <&ipcc IPCC_CLIENT_SLPI 556 IPCC_MPROC_SIGNAL_SMP2P>; 557 558 qcom,local-pid = <0>; 559 qcom,remote-pid = <3>; 560 561 smp2p_slpi_out: master-kernel { 562 qcom,entry-name = "master-kernel"; 563 #qcom,smem-state-cells = <1>; 564 }; 565 566 smp2p_slpi_in: slave-kernel { 567 qcom,entry-name = "slave-kernel"; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 }; 571 }; 572 573 soc: soc@0 { 574 #address-cells = <2>; 575 #size-cells = <2>; 576 ranges = <0 0 0 0 0x10 0>; 577 dma-ranges = <0 0 0 0 0x10 0>; 578 compatible = "simple-bus"; 579 580 gcc: clock-controller@100000 { 581 compatible = "qcom,gcc-sm8350"; 582 reg = <0x0 0x00100000 0x0 0x1f0000>; 583 #clock-cells = <1>; 584 #reset-cells = <1>; 585 #power-domain-cells = <1>; 586 clock-names = "bi_tcxo", "sleep_clk"; 587 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 588 }; 589 590 ipcc: mailbox@408000 { 591 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 592 reg = <0 0x00408000 0 0x1000>; 593 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-controller; 595 #interrupt-cells = <3>; 596 #mbox-cells = <2>; 597 }; 598 599 qupv3_id_0: geniqup@9c0000 { 600 compatible = "qcom,geni-se-qup"; 601 reg = <0x0 0x009c0000 0x0 0x6000>; 602 clock-names = "m-ahb", "s-ahb"; 603 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 604 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 605 #address-cells = <2>; 606 #size-cells = <2>; 607 ranges; 608 status = "disabled"; 609 610 uart2: serial@98c000 { 611 compatible = "qcom,geni-debug-uart"; 612 reg = <0 0x0098c000 0 0x4000>; 613 clock-names = "se"; 614 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&qup_uart3_default_state>; 617 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 }; 623 624 qupv3_id_1: geniqup@ac0000 { 625 compatible = "qcom,geni-se-qup"; 626 reg = <0x0 0x00ac0000 0x0 0x6000>; 627 clock-names = "m-ahb", "s-ahb"; 628 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 629 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 630 #address-cells = <2>; 631 #size-cells = <2>; 632 ranges; 633 status = "disabled"; 634 635 i2c13: i2c@a94000 { 636 compatible = "qcom,geni-i2c"; 637 reg = <0 0x00a94000 0 0x4000>; 638 clock-names = "se"; 639 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&qup_i2c13_default_state>; 642 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 }; 648 649 apps_smmu: iommu@15000000 { 650 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 651 reg = <0 0x15000000 0 0x100000>; 652 #iommu-cells = <2>; 653 #global-interrupts = <2>; 654 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 752 }; 753 754 config_noc: interconnect@1500000 { 755 compatible = "qcom,sm8350-config-noc"; 756 reg = <0 0x01500000 0 0xa580>; 757 #interconnect-cells = <1>; 758 qcom,bcm-voters = <&apps_bcm_voter>; 759 }; 760 761 mc_virt: interconnect@1580000 { 762 compatible = "qcom,sm8350-mc-virt"; 763 reg = <0 0x01580000 0 0x1000>; 764 #interconnect-cells = <1>; 765 qcom,bcm-voters = <&apps_bcm_voter>; 766 }; 767 768 system_noc: interconnect@1680000 { 769 compatible = "qcom,sm8350-system-noc"; 770 reg = <0 0x01680000 0 0x1c200>; 771 #interconnect-cells = <1>; 772 qcom,bcm-voters = <&apps_bcm_voter>; 773 }; 774 775 aggre1_noc: interconnect@16e0000 { 776 compatible = "qcom,sm8350-aggre1-noc"; 777 reg = <0 0x016e0000 0 0x1f180>; 778 #interconnect-cells = <1>; 779 qcom,bcm-voters = <&apps_bcm_voter>; 780 }; 781 782 aggre2_noc: interconnect@1700000 { 783 compatible = "qcom,sm8350-aggre2-noc"; 784 reg = <0 0x01700000 0 0x33000>; 785 #interconnect-cells = <1>; 786 qcom,bcm-voters = <&apps_bcm_voter>; 787 }; 788 789 mmss_noc: interconnect@1740000 { 790 compatible = "qcom,sm8350-mmss-noc"; 791 reg = <0 0x01740000 0 0x1f080>; 792 #interconnect-cells = <1>; 793 qcom,bcm-voters = <&apps_bcm_voter>; 794 }; 795 796 lpass_ag_noc: interconnect@3c40000 { 797 compatible = "qcom,sm8350-lpass-ag-noc"; 798 reg = <0 0x03c40000 0 0xf080>; 799 #interconnect-cells = <1>; 800 qcom,bcm-voters = <&apps_bcm_voter>; 801 }; 802 803 compute_noc: interconnect@a0c0000{ 804 compatible = "qcom,sm8350-compute-noc"; 805 reg = <0 0x0a0c0000 0 0xa180>; 806 #interconnect-cells = <1>; 807 qcom,bcm-voters = <&apps_bcm_voter>; 808 }; 809 810 ipa: ipa@1e40000 { 811 compatible = "qcom,sm8350-ipa"; 812 813 iommus = <&apps_smmu 0x5c0 0x0>, 814 <&apps_smmu 0x5c2 0x0>; 815 reg = <0 0x1e40000 0 0x8000>, 816 <0 0x1e50000 0 0x4b20>, 817 <0 0x1e04000 0 0x23000>; 818 reg-names = "ipa-reg", 819 "ipa-shared", 820 "gsi"; 821 822 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 823 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 824 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 825 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 826 interrupt-names = "ipa", 827 "gsi", 828 "ipa-clock-query", 829 "ipa-setup-ready"; 830 831 clocks = <&rpmhcc RPMH_IPA_CLK>; 832 clock-names = "core"; 833 834 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 835 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 836 interconnect-names = "memory", 837 "config"; 838 839 qcom,smem-states = <&ipa_smp2p_out 0>, 840 <&ipa_smp2p_out 1>; 841 qcom,smem-state-names = "ipa-clock-enabled-valid", 842 "ipa-clock-enabled"; 843 844 status = "disabled"; 845 }; 846 847 tcsr_mutex: hwlock@1f40000 { 848 compatible = "qcom,tcsr-mutex"; 849 reg = <0x0 0x01f40000 0x0 0x40000>; 850 #hwlock-cells = <1>; 851 }; 852 853 mpss: remoteproc@4080000 { 854 compatible = "qcom,sm8350-mpss-pas"; 855 reg = <0x0 0x04080000 0x0 0x4040>; 856 857 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 858 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 862 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 863 interrupt-names = "wdog", "fatal", "ready", "handover", 864 "stop-ack", "shutdown-ack"; 865 866 clocks = <&rpmhcc RPMH_CXO_CLK>; 867 clock-names = "xo"; 868 869 power-domains = <&rpmhpd 0>, 870 <&rpmhpd 12>; 871 power-domain-names = "cx", "mss"; 872 873 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; 874 875 memory-region = <&pil_modem_mem>; 876 877 qcom,qmp = <&aoss_qmp>; 878 879 qcom,smem-states = <&smp2p_modem_out 0>; 880 qcom,smem-state-names = "stop"; 881 882 status = "disabled"; 883 884 glink-edge { 885 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 886 IPCC_MPROC_SIGNAL_GLINK_QMP 887 IRQ_TYPE_EDGE_RISING>; 888 mboxes = <&ipcc IPCC_CLIENT_MPSS 889 IPCC_MPROC_SIGNAL_GLINK_QMP>; 890 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 891 label = "modem"; 892 qcom,remote-pid = <1>; 893 }; 894 }; 895 896 pdc: interrupt-controller@b220000 { 897 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 898 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 899 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 900 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 901 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 902 <156 716 12>; 903 #interrupt-cells = <2>; 904 interrupt-parent = <&intc>; 905 interrupt-controller; 906 }; 907 908 tsens0: thermal-sensor@c263000 { 909 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 910 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 911 <0 0x0c222000 0 0x8>; /* SROT */ 912 #qcom,sensors = <15>; 913 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 914 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "uplow", "critical"; 916 #thermal-sensor-cells = <1>; 917 }; 918 919 tsens1: thermal-sensor@c265000 { 920 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 921 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 922 <0 0x0c223000 0 0x8>; /* SROT */ 923 #qcom,sensors = <14>; 924 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 925 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "uplow", "critical"; 927 #thermal-sensor-cells = <1>; 928 }; 929 930 aoss_qmp: power-controller@c300000 { 931 compatible = "qcom,sm8350-aoss-qmp"; 932 reg = <0 0x0c300000 0 0x400>; 933 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 934 IRQ_TYPE_EDGE_RISING>; 935 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 936 937 #clock-cells = <0>; 938 }; 939 940 sram@c3f0000 { 941 compatible = "qcom,rpmh-stats"; 942 reg = <0 0x0c3f0000 0 0x400>; 943 }; 944 945 spmi_bus: spmi@c440000 { 946 compatible = "qcom,spmi-pmic-arb"; 947 reg = <0x0 0xc440000 0x0 0x1100>, 948 <0x0 0xc600000 0x0 0x2000000>, 949 <0x0 0xe600000 0x0 0x100000>, 950 <0x0 0xe700000 0x0 0xa0000>, 951 <0x0 0xc40a000 0x0 0x26000>; 952 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 953 interrupt-names = "periph_irq"; 954 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 955 qcom,ee = <0>; 956 qcom,channel = <0>; 957 #address-cells = <2>; 958 #size-cells = <0>; 959 interrupt-controller; 960 #interrupt-cells = <4>; 961 }; 962 963 tlmm: pinctrl@f100000 { 964 compatible = "qcom,sm8350-tlmm"; 965 reg = <0 0x0f100000 0 0x300000>; 966 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 967 gpio-controller; 968 #gpio-cells = <2>; 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 gpio-ranges = <&tlmm 0 0 204>; 972 wakeup-parent = <&pdc>; 973 974 qup_uart3_default_state: qup-uart3-default-state { 975 rx { 976 pins = "gpio18"; 977 function = "qup3"; 978 }; 979 tx { 980 pins = "gpio19"; 981 function = "qup3"; 982 }; 983 }; 984 985 qup_i2c13_default_state: qup-i2c13-default-state { 986 mux { 987 pins = "gpio0", "gpio1"; 988 function = "qup13"; 989 }; 990 991 config { 992 pins = "gpio0", "gpio1"; 993 drive-strength = <2>; 994 bias-pull-up; 995 }; 996 }; 997 }; 998 999 rng: rng@10d3000 { 1000 compatible = "qcom,prng-ee"; 1001 reg = <0 0x010d3000 0 0x1000>; 1002 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1003 clock-names = "core"; 1004 }; 1005 1006 intc: interrupt-controller@17a00000 { 1007 compatible = "arm,gic-v3"; 1008 #interrupt-cells = <3>; 1009 interrupt-controller; 1010 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1011 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1012 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1013 }; 1014 1015 timer@17c20000 { 1016 compatible = "arm,armv7-timer-mem"; 1017 #address-cells = <2>; 1018 #size-cells = <2>; 1019 ranges; 1020 reg = <0x0 0x17c20000 0x0 0x1000>; 1021 clock-frequency = <19200000>; 1022 1023 frame@17c21000 { 1024 frame-number = <0>; 1025 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1027 reg = <0x0 0x17c21000 0x0 0x1000>, 1028 <0x0 0x17c22000 0x0 0x1000>; 1029 }; 1030 1031 frame@17c23000 { 1032 frame-number = <1>; 1033 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1034 reg = <0x0 0x17c23000 0x0 0x1000>; 1035 status = "disabled"; 1036 }; 1037 1038 frame@17c25000 { 1039 frame-number = <2>; 1040 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1041 reg = <0x0 0x17c25000 0x0 0x1000>; 1042 status = "disabled"; 1043 }; 1044 1045 frame@17c27000 { 1046 frame-number = <3>; 1047 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1048 reg = <0x0 0x17c27000 0x0 0x1000>; 1049 status = "disabled"; 1050 }; 1051 1052 frame@17c29000 { 1053 frame-number = <4>; 1054 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1055 reg = <0x0 0x17c29000 0x0 0x1000>; 1056 status = "disabled"; 1057 }; 1058 1059 frame@17c2b000 { 1060 frame-number = <5>; 1061 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1062 reg = <0x0 0x17c2b000 0x0 0x1000>; 1063 status = "disabled"; 1064 }; 1065 1066 frame@17c2d000 { 1067 frame-number = <6>; 1068 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1069 reg = <0x0 0x17c2d000 0x0 0x1000>; 1070 status = "disabled"; 1071 }; 1072 }; 1073 1074 apps_rsc: rsc@18200000 { 1075 label = "apps_rsc"; 1076 compatible = "qcom,rpmh-rsc"; 1077 reg = <0x0 0x18200000 0x0 0x10000>, 1078 <0x0 0x18210000 0x0 0x10000>, 1079 <0x0 0x18220000 0x0 0x10000>; 1080 reg-names = "drv-0", "drv-1", "drv-2"; 1081 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1084 qcom,tcs-offset = <0xd00>; 1085 qcom,drv-id = <2>; 1086 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1087 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1088 1089 rpmhcc: clock-controller { 1090 compatible = "qcom,sm8350-rpmh-clk"; 1091 #clock-cells = <1>; 1092 clock-names = "xo"; 1093 clocks = <&xo_board>; 1094 }; 1095 1096 rpmhpd: power-controller { 1097 compatible = "qcom,sm8350-rpmhpd"; 1098 #power-domain-cells = <1>; 1099 operating-points-v2 = <&rpmhpd_opp_table>; 1100 1101 rpmhpd_opp_table: opp-table { 1102 compatible = "operating-points-v2"; 1103 1104 rpmhpd_opp_ret: opp1 { 1105 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1106 }; 1107 1108 rpmhpd_opp_min_svs: opp2 { 1109 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1110 }; 1111 1112 rpmhpd_opp_low_svs: opp3 { 1113 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1114 }; 1115 1116 rpmhpd_opp_svs: opp4 { 1117 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1118 }; 1119 1120 rpmhpd_opp_svs_l1: opp5 { 1121 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1122 }; 1123 1124 rpmhpd_opp_nom: opp6 { 1125 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1126 }; 1127 1128 rpmhpd_opp_nom_l1: opp7 { 1129 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1130 }; 1131 1132 rpmhpd_opp_nom_l2: opp8 { 1133 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1134 }; 1135 1136 rpmhpd_opp_turbo: opp9 { 1137 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1138 }; 1139 1140 rpmhpd_opp_turbo_l1: opp10 { 1141 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1142 }; 1143 }; 1144 }; 1145 1146 apps_bcm_voter: bcm_voter { 1147 compatible = "qcom,bcm-voter"; 1148 }; 1149 }; 1150 1151 cpufreq_hw: cpufreq@18591000 { 1152 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 1153 reg = <0 0x18591000 0 0x1000>, 1154 <0 0x18592000 0 0x1000>, 1155 <0 0x18593000 0 0x1000>; 1156 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 1157 1158 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1159 clock-names = "xo", "alternate"; 1160 1161 #freq-domain-cells = <1>; 1162 }; 1163 1164 ufs_mem_hc: ufshc@1d84000 { 1165 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1166 "jedec,ufs-2.0"; 1167 reg = <0 0x01d84000 0 0x3000>; 1168 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1169 phys = <&ufs_mem_phy_lanes>; 1170 phy-names = "ufsphy"; 1171 lanes-per-direction = <2>; 1172 #reset-cells = <1>; 1173 resets = <&gcc GCC_UFS_PHY_BCR>; 1174 reset-names = "rst"; 1175 1176 power-domains = <&gcc UFS_PHY_GDSC>; 1177 1178 iommus = <&apps_smmu 0xe0 0x0>; 1179 1180 clock-names = 1181 "ref_clk", 1182 "core_clk", 1183 "bus_aggr_clk", 1184 "iface_clk", 1185 "core_clk_unipro", 1186 "ref_clk", 1187 "tx_lane0_sync_clk", 1188 "rx_lane0_sync_clk", 1189 "rx_lane1_sync_clk"; 1190 clocks = 1191 <&rpmhcc RPMH_CXO_CLK>, 1192 <&gcc GCC_UFS_PHY_AXI_CLK>, 1193 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1194 <&gcc GCC_UFS_PHY_AHB_CLK>, 1195 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1196 <&rpmhcc RPMH_CXO_CLK>, 1197 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1198 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1199 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1200 freq-table-hz = 1201 <75000000 300000000>, 1202 <75000000 300000000>, 1203 <0 0>, 1204 <0 0>, 1205 <75000000 300000000>, 1206 <0 0>, 1207 <0 0>, 1208 <75000000 300000000>, 1209 <75000000 300000000>; 1210 status = "disabled"; 1211 }; 1212 1213 ufs_mem_phy: phy@1d87000 { 1214 compatible = "qcom,sm8350-qmp-ufs-phy"; 1215 reg = <0 0x01d87000 0 0xe10>; 1216 #address-cells = <2>; 1217 #size-cells = <2>; 1218 ranges; 1219 clock-names = "ref", 1220 "ref_aux"; 1221 clocks = <&rpmhcc RPMH_CXO_CLK>, 1222 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1223 1224 resets = <&ufs_mem_hc 0>; 1225 reset-names = "ufsphy"; 1226 status = "disabled"; 1227 1228 ufs_mem_phy_lanes: phy@1d87400 { 1229 reg = <0 0x01d87400 0 0x108>, 1230 <0 0x01d87600 0 0x1e0>, 1231 <0 0x01d87c00 0 0x1dc>, 1232 <0 0x01d87800 0 0x108>, 1233 <0 0x01d87a00 0 0x1e0>; 1234 #phy-cells = <0>; 1235 #clock-cells = <0>; 1236 }; 1237 }; 1238 1239 slpi: remoteproc@5c00000 { 1240 compatible = "qcom,sm8350-slpi-pas"; 1241 reg = <0 0x05c00000 0 0x4000>; 1242 1243 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 1244 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 1245 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 1246 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 1247 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 1248 interrupt-names = "wdog", "fatal", "ready", 1249 "handover", "stop-ack"; 1250 1251 clocks = <&rpmhcc RPMH_CXO_CLK>; 1252 clock-names = "xo"; 1253 1254 power-domains = <&rpmhpd 4>, 1255 <&rpmhpd 5>; 1256 power-domain-names = "lcx", "lmx"; 1257 1258 memory-region = <&pil_slpi_mem>; 1259 1260 qcom,qmp = <&aoss_qmp>; 1261 1262 qcom,smem-states = <&smp2p_slpi_out 0>; 1263 qcom,smem-state-names = "stop"; 1264 1265 status = "disabled"; 1266 1267 glink-edge { 1268 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 1269 IPCC_MPROC_SIGNAL_GLINK_QMP 1270 IRQ_TYPE_EDGE_RISING>; 1271 mboxes = <&ipcc IPCC_CLIENT_SLPI 1272 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1273 1274 label = "slpi"; 1275 qcom,remote-pid = <3>; 1276 1277 fastrpc { 1278 compatible = "qcom,fastrpc"; 1279 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1280 label = "sdsp"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 compute-cb@1 { 1285 compatible = "qcom,fastrpc-compute-cb"; 1286 reg = <1>; 1287 iommus = <&apps_smmu 0x0541 0x0>; 1288 }; 1289 1290 compute-cb@2 { 1291 compatible = "qcom,fastrpc-compute-cb"; 1292 reg = <2>; 1293 iommus = <&apps_smmu 0x0542 0x0>; 1294 }; 1295 1296 compute-cb@3 { 1297 compatible = "qcom,fastrpc-compute-cb"; 1298 reg = <3>; 1299 iommus = <&apps_smmu 0x0543 0x0>; 1300 /* note: shared-cb = <4> in downstream */ 1301 }; 1302 }; 1303 }; 1304 }; 1305 1306 cdsp: remoteproc@98900000 { 1307 compatible = "qcom,sm8350-cdsp-pas"; 1308 reg = <0 0x098900000 0 0x1400000>; 1309 1310 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1311 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1312 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1313 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1314 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1315 interrupt-names = "wdog", "fatal", "ready", 1316 "handover", "stop-ack"; 1317 1318 clocks = <&rpmhcc RPMH_CXO_CLK>; 1319 clock-names = "xo"; 1320 1321 power-domains = <&rpmhpd 0>, 1322 <&rpmhpd 10>; 1323 power-domain-names = "cx", "mxc"; 1324 1325 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; 1326 1327 memory-region = <&pil_cdsp_mem>; 1328 1329 qcom,qmp = <&aoss_qmp>; 1330 1331 qcom,smem-states = <&smp2p_cdsp_out 0>; 1332 qcom,smem-state-names = "stop"; 1333 1334 status = "disabled"; 1335 1336 glink-edge { 1337 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1338 IPCC_MPROC_SIGNAL_GLINK_QMP 1339 IRQ_TYPE_EDGE_RISING>; 1340 mboxes = <&ipcc IPCC_CLIENT_CDSP 1341 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1342 1343 label = "cdsp"; 1344 qcom,remote-pid = <5>; 1345 1346 fastrpc { 1347 compatible = "qcom,fastrpc"; 1348 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1349 label = "cdsp"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 1353 compute-cb@1 { 1354 compatible = "qcom,fastrpc-compute-cb"; 1355 reg = <1>; 1356 iommus = <&apps_smmu 0x2161 0x0400>, 1357 <&apps_smmu 0x1181 0x0420>; 1358 }; 1359 1360 compute-cb@2 { 1361 compatible = "qcom,fastrpc-compute-cb"; 1362 reg = <2>; 1363 iommus = <&apps_smmu 0x2162 0x0400>, 1364 <&apps_smmu 0x1182 0x0420>; 1365 }; 1366 1367 compute-cb@3 { 1368 compatible = "qcom,fastrpc-compute-cb"; 1369 reg = <3>; 1370 iommus = <&apps_smmu 0x2163 0x0400>, 1371 <&apps_smmu 0x1183 0x0420>; 1372 }; 1373 1374 compute-cb@4 { 1375 compatible = "qcom,fastrpc-compute-cb"; 1376 reg = <4>; 1377 iommus = <&apps_smmu 0x2164 0x0400>, 1378 <&apps_smmu 0x1184 0x0420>; 1379 }; 1380 1381 compute-cb@5 { 1382 compatible = "qcom,fastrpc-compute-cb"; 1383 reg = <5>; 1384 iommus = <&apps_smmu 0x2165 0x0400>, 1385 <&apps_smmu 0x1185 0x0420>; 1386 }; 1387 1388 compute-cb@6 { 1389 compatible = "qcom,fastrpc-compute-cb"; 1390 reg = <6>; 1391 iommus = <&apps_smmu 0x2166 0x0400>, 1392 <&apps_smmu 0x1186 0x0420>; 1393 }; 1394 1395 compute-cb@7 { 1396 compatible = "qcom,fastrpc-compute-cb"; 1397 reg = <7>; 1398 iommus = <&apps_smmu 0x2167 0x0400>, 1399 <&apps_smmu 0x1187 0x0420>; 1400 }; 1401 1402 compute-cb@8 { 1403 compatible = "qcom,fastrpc-compute-cb"; 1404 reg = <8>; 1405 iommus = <&apps_smmu 0x2168 0x0400>, 1406 <&apps_smmu 0x1188 0x0420>; 1407 }; 1408 1409 /* note: secure cb9 in downstream */ 1410 }; 1411 }; 1412 }; 1413 1414 usb_1_hsphy: phy@88e3000 { 1415 compatible = "qcom,sm8350-usb-hs-phy", 1416 "qcom,usb-snps-hs-7nm-phy"; 1417 reg = <0 0x088e3000 0 0x400>; 1418 status = "disabled"; 1419 #phy-cells = <0>; 1420 1421 clocks = <&rpmhcc RPMH_CXO_CLK>; 1422 clock-names = "ref"; 1423 1424 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1425 }; 1426 1427 usb_2_hsphy: phy@88e4000 { 1428 compatible = "qcom,sm8250-usb-hs-phy", 1429 "qcom,usb-snps-hs-7nm-phy"; 1430 reg = <0 0x088e4000 0 0x400>; 1431 status = "disabled"; 1432 #phy-cells = <0>; 1433 1434 clocks = <&rpmhcc RPMH_CXO_CLK>; 1435 clock-names = "ref"; 1436 1437 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1438 }; 1439 1440 usb_1_qmpphy: phy-wrapper@88e9000 { 1441 compatible = "qcom,sm8350-qmp-usb3-phy"; 1442 reg = <0 0x088e9000 0 0x200>, 1443 <0 0x088e8000 0 0x20>; 1444 status = "disabled"; 1445 #address-cells = <2>; 1446 #size-cells = <2>; 1447 ranges; 1448 1449 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1450 <&rpmhcc RPMH_CXO_CLK>, 1451 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1452 clock-names = "aux", "ref_clk_src", "com_aux"; 1453 1454 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1455 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1456 reset-names = "phy", "common"; 1457 1458 usb_1_ssphy: phy@88e9200 { 1459 reg = <0 0x088e9200 0 0x200>, 1460 <0 0x088e9400 0 0x200>, 1461 <0 0x088e9c00 0 0x400>, 1462 <0 0x088e9600 0 0x200>, 1463 <0 0x088e9800 0 0x200>, 1464 <0 0x088e9a00 0 0x100>; 1465 #phy-cells = <0>; 1466 #clock-cells = <1>; 1467 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1468 clock-names = "pipe0"; 1469 clock-output-names = "usb3_phy_pipe_clk_src"; 1470 }; 1471 }; 1472 1473 usb_2_qmpphy: phy-wrapper@88eb000 { 1474 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 1475 reg = <0 0x088eb000 0 0x200>; 1476 status = "disabled"; 1477 #address-cells = <2>; 1478 #size-cells = <2>; 1479 ranges; 1480 1481 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1482 <&rpmhcc RPMH_CXO_CLK>, 1483 <&gcc GCC_USB3_SEC_CLKREF_EN>, 1484 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1485 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1486 1487 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1488 <&gcc GCC_USB3_PHY_SEC_BCR>; 1489 reset-names = "phy", "common"; 1490 1491 usb_2_ssphy: phy@88ebe00 { 1492 reg = <0 0x088ebe00 0 0x200>, 1493 <0 0x088ec000 0 0x200>, 1494 <0 0x088eb200 0 0x1100>; 1495 #phy-cells = <0>; 1496 #clock-cells = <1>; 1497 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1498 clock-names = "pipe0"; 1499 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1500 }; 1501 }; 1502 1503 dc_noc: interconnect@90c0000 { 1504 compatible = "qcom,sm8350-dc-noc"; 1505 reg = <0 0x090c0000 0 0x4200>; 1506 #interconnect-cells = <1>; 1507 qcom,bcm-voters = <&apps_bcm_voter>; 1508 }; 1509 1510 gem_noc: interconnect@9100000 { 1511 compatible = "qcom,sm8350-gem-noc"; 1512 reg = <0 0x09100000 0 0xb4000>; 1513 #interconnect-cells = <1>; 1514 qcom,bcm-voters = <&apps_bcm_voter>; 1515 }; 1516 1517 usb_1: usb@a6f8800 { 1518 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 1519 reg = <0 0x0a6f8800 0 0x400>; 1520 status = "disabled"; 1521 #address-cells = <2>; 1522 #size-cells = <2>; 1523 ranges; 1524 1525 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1526 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1527 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1528 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1529 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1530 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1531 "sleep"; 1532 1533 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1534 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1535 assigned-clock-rates = <19200000>, <200000000>; 1536 1537 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1538 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1539 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1540 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1541 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1542 "dm_hs_phy_irq", "ss_phy_irq"; 1543 1544 power-domains = <&gcc USB30_PRIM_GDSC>; 1545 1546 resets = <&gcc GCC_USB30_PRIM_BCR>; 1547 1548 usb_1_dwc3: usb@a600000 { 1549 compatible = "snps,dwc3"; 1550 reg = <0 0x0a600000 0 0xcd00>; 1551 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1552 iommus = <&apps_smmu 0x0 0x0>; 1553 snps,dis_u2_susphy_quirk; 1554 snps,dis_enblslpm_quirk; 1555 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1556 phy-names = "usb2-phy", "usb3-phy"; 1557 }; 1558 }; 1559 1560 usb_2: usb@a8f8800 { 1561 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 1562 reg = <0 0x0a8f8800 0 0x400>; 1563 status = "disabled"; 1564 #address-cells = <2>; 1565 #size-cells = <2>; 1566 ranges; 1567 1568 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1569 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1570 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1571 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1572 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1573 <&gcc GCC_USB3_SEC_CLKREF_EN>; 1574 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1575 "sleep", "xo"; 1576 1577 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1578 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1579 assigned-clock-rates = <19200000>, <200000000>; 1580 1581 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1582 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 1583 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 1584 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 1585 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1586 "dm_hs_phy_irq", "ss_phy_irq"; 1587 1588 power-domains = <&gcc USB30_SEC_GDSC>; 1589 1590 resets = <&gcc GCC_USB30_SEC_BCR>; 1591 1592 usb_2_dwc3: usb@a800000 { 1593 compatible = "snps,dwc3"; 1594 reg = <0 0x0a800000 0 0xcd00>; 1595 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1596 iommus = <&apps_smmu 0x20 0x0>; 1597 snps,dis_u2_susphy_quirk; 1598 snps,dis_enblslpm_quirk; 1599 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1600 phy-names = "usb2-phy", "usb3-phy"; 1601 }; 1602 }; 1603 1604 adsp: remoteproc@17300000 { 1605 compatible = "qcom,sm8350-adsp-pas"; 1606 reg = <0 0x17300000 0 0x100>; 1607 1608 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1609 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1610 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1611 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1612 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1613 interrupt-names = "wdog", "fatal", "ready", 1614 "handover", "stop-ack"; 1615 1616 clocks = <&rpmhcc RPMH_CXO_CLK>; 1617 clock-names = "xo"; 1618 1619 power-domains = <&rpmhpd 4>, 1620 <&rpmhpd 5>; 1621 power-domain-names = "lcx", "lmx"; 1622 1623 memory-region = <&pil_adsp_mem>; 1624 1625 qcom,qmp = <&aoss_qmp>; 1626 1627 qcom,smem-states = <&smp2p_adsp_out 0>; 1628 qcom,smem-state-names = "stop"; 1629 1630 status = "disabled"; 1631 1632 glink-edge { 1633 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1634 IPCC_MPROC_SIGNAL_GLINK_QMP 1635 IRQ_TYPE_EDGE_RISING>; 1636 mboxes = <&ipcc IPCC_CLIENT_LPASS 1637 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1638 1639 label = "lpass"; 1640 qcom,remote-pid = <2>; 1641 1642 fastrpc { 1643 compatible = "qcom,fastrpc"; 1644 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1645 label = "adsp"; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 compute-cb@3 { 1650 compatible = "qcom,fastrpc-compute-cb"; 1651 reg = <3>; 1652 iommus = <&apps_smmu 0x1803 0x0>; 1653 }; 1654 1655 compute-cb@4 { 1656 compatible = "qcom,fastrpc-compute-cb"; 1657 reg = <4>; 1658 iommus = <&apps_smmu 0x1804 0x0>; 1659 }; 1660 1661 compute-cb@5 { 1662 compatible = "qcom,fastrpc-compute-cb"; 1663 reg = <5>; 1664 iommus = <&apps_smmu 0x1805 0x0>; 1665 }; 1666 }; 1667 }; 1668 }; 1669 }; 1670 1671 thermal_zones: thermal-zones { 1672 cpu0-thermal { 1673 polling-delay-passive = <250>; 1674 polling-delay = <1000>; 1675 1676 thermal-sensors = <&tsens0 1>; 1677 1678 trips { 1679 cpu0_alert0: trip-point0 { 1680 temperature = <90000>; 1681 hysteresis = <2000>; 1682 type = "passive"; 1683 }; 1684 1685 cpu0_alert1: trip-point1 { 1686 temperature = <95000>; 1687 hysteresis = <2000>; 1688 type = "passive"; 1689 }; 1690 1691 cpu0_crit: cpu_crit { 1692 temperature = <110000>; 1693 hysteresis = <1000>; 1694 type = "critical"; 1695 }; 1696 }; 1697 1698 cooling-maps { 1699 map0 { 1700 trip = <&cpu0_alert0>; 1701 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1702 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1703 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1704 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1705 }; 1706 map1 { 1707 trip = <&cpu0_alert1>; 1708 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1709 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1710 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1711 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1712 }; 1713 }; 1714 }; 1715 1716 cpu1-thermal { 1717 polling-delay-passive = <250>; 1718 polling-delay = <1000>; 1719 1720 thermal-sensors = <&tsens0 2>; 1721 1722 trips { 1723 cpu1_alert0: trip-point0 { 1724 temperature = <90000>; 1725 hysteresis = <2000>; 1726 type = "passive"; 1727 }; 1728 1729 cpu1_alert1: trip-point1 { 1730 temperature = <95000>; 1731 hysteresis = <2000>; 1732 type = "passive"; 1733 }; 1734 1735 cpu1_crit: cpu_crit { 1736 temperature = <110000>; 1737 hysteresis = <1000>; 1738 type = "critical"; 1739 }; 1740 }; 1741 1742 cooling-maps { 1743 map0 { 1744 trip = <&cpu1_alert0>; 1745 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1746 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1747 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1748 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1749 }; 1750 map1 { 1751 trip = <&cpu1_alert1>; 1752 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1753 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1754 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1755 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1756 }; 1757 }; 1758 }; 1759 1760 cpu2-thermal { 1761 polling-delay-passive = <250>; 1762 polling-delay = <1000>; 1763 1764 thermal-sensors = <&tsens0 3>; 1765 1766 trips { 1767 cpu2_alert0: trip-point0 { 1768 temperature = <90000>; 1769 hysteresis = <2000>; 1770 type = "passive"; 1771 }; 1772 1773 cpu2_alert1: trip-point1 { 1774 temperature = <95000>; 1775 hysteresis = <2000>; 1776 type = "passive"; 1777 }; 1778 1779 cpu2_crit: cpu_crit { 1780 temperature = <110000>; 1781 hysteresis = <1000>; 1782 type = "critical"; 1783 }; 1784 }; 1785 1786 cooling-maps { 1787 map0 { 1788 trip = <&cpu2_alert0>; 1789 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1790 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1791 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1792 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1793 }; 1794 map1 { 1795 trip = <&cpu2_alert1>; 1796 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1797 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1798 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1799 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1800 }; 1801 }; 1802 }; 1803 1804 cpu3-thermal { 1805 polling-delay-passive = <250>; 1806 polling-delay = <1000>; 1807 1808 thermal-sensors = <&tsens0 4>; 1809 1810 trips { 1811 cpu3_alert0: trip-point0 { 1812 temperature = <90000>; 1813 hysteresis = <2000>; 1814 type = "passive"; 1815 }; 1816 1817 cpu3_alert1: trip-point1 { 1818 temperature = <95000>; 1819 hysteresis = <2000>; 1820 type = "passive"; 1821 }; 1822 1823 cpu3_crit: cpu_crit { 1824 temperature = <110000>; 1825 hysteresis = <1000>; 1826 type = "critical"; 1827 }; 1828 }; 1829 1830 cooling-maps { 1831 map0 { 1832 trip = <&cpu3_alert0>; 1833 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1834 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1835 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1836 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1837 }; 1838 map1 { 1839 trip = <&cpu3_alert1>; 1840 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1841 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1842 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1843 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1844 }; 1845 }; 1846 }; 1847 1848 cpu4-top-thermal { 1849 polling-delay-passive = <250>; 1850 polling-delay = <1000>; 1851 1852 thermal-sensors = <&tsens0 7>; 1853 1854 trips { 1855 cpu4_top_alert0: trip-point0 { 1856 temperature = <90000>; 1857 hysteresis = <2000>; 1858 type = "passive"; 1859 }; 1860 1861 cpu4_top_alert1: trip-point1 { 1862 temperature = <95000>; 1863 hysteresis = <2000>; 1864 type = "passive"; 1865 }; 1866 1867 cpu4_top_crit: cpu_crit { 1868 temperature = <110000>; 1869 hysteresis = <1000>; 1870 type = "critical"; 1871 }; 1872 }; 1873 1874 cooling-maps { 1875 map0 { 1876 trip = <&cpu4_top_alert0>; 1877 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1878 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1879 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1880 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1881 }; 1882 map1 { 1883 trip = <&cpu4_top_alert1>; 1884 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1886 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1887 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1888 }; 1889 }; 1890 }; 1891 1892 cpu5-top-thermal { 1893 polling-delay-passive = <250>; 1894 polling-delay = <1000>; 1895 1896 thermal-sensors = <&tsens0 8>; 1897 1898 trips { 1899 cpu5_top_alert0: trip-point0 { 1900 temperature = <90000>; 1901 hysteresis = <2000>; 1902 type = "passive"; 1903 }; 1904 1905 cpu5_top_alert1: trip-point1 { 1906 temperature = <95000>; 1907 hysteresis = <2000>; 1908 type = "passive"; 1909 }; 1910 1911 cpu5_top_crit: cpu_crit { 1912 temperature = <110000>; 1913 hysteresis = <1000>; 1914 type = "critical"; 1915 }; 1916 }; 1917 1918 cooling-maps { 1919 map0 { 1920 trip = <&cpu5_top_alert0>; 1921 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1922 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1923 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1924 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1925 }; 1926 map1 { 1927 trip = <&cpu5_top_alert1>; 1928 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1929 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1930 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1931 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1932 }; 1933 }; 1934 }; 1935 1936 cpu6-top-thermal { 1937 polling-delay-passive = <250>; 1938 polling-delay = <1000>; 1939 1940 thermal-sensors = <&tsens0 9>; 1941 1942 trips { 1943 cpu6_top_alert0: trip-point0 { 1944 temperature = <90000>; 1945 hysteresis = <2000>; 1946 type = "passive"; 1947 }; 1948 1949 cpu6_top_alert1: trip-point1 { 1950 temperature = <95000>; 1951 hysteresis = <2000>; 1952 type = "passive"; 1953 }; 1954 1955 cpu6_top_crit: cpu_crit { 1956 temperature = <110000>; 1957 hysteresis = <1000>; 1958 type = "critical"; 1959 }; 1960 }; 1961 1962 cooling-maps { 1963 map0 { 1964 trip = <&cpu6_top_alert0>; 1965 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1966 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1967 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1968 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1969 }; 1970 map1 { 1971 trip = <&cpu6_top_alert1>; 1972 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1973 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1974 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1975 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1976 }; 1977 }; 1978 }; 1979 1980 cpu7-top-thermal { 1981 polling-delay-passive = <250>; 1982 polling-delay = <1000>; 1983 1984 thermal-sensors = <&tsens0 10>; 1985 1986 trips { 1987 cpu7_top_alert0: trip-point0 { 1988 temperature = <90000>; 1989 hysteresis = <2000>; 1990 type = "passive"; 1991 }; 1992 1993 cpu7_top_alert1: trip-point1 { 1994 temperature = <95000>; 1995 hysteresis = <2000>; 1996 type = "passive"; 1997 }; 1998 1999 cpu7_top_crit: cpu_crit { 2000 temperature = <110000>; 2001 hysteresis = <1000>; 2002 type = "critical"; 2003 }; 2004 }; 2005 2006 cooling-maps { 2007 map0 { 2008 trip = <&cpu7_top_alert0>; 2009 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2010 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2011 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2012 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2013 }; 2014 map1 { 2015 trip = <&cpu7_top_alert1>; 2016 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2017 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2018 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2020 }; 2021 }; 2022 }; 2023 2024 cpu4-bottom-thermal { 2025 polling-delay-passive = <250>; 2026 polling-delay = <1000>; 2027 2028 thermal-sensors = <&tsens0 11>; 2029 2030 trips { 2031 cpu4_bottom_alert0: trip-point0 { 2032 temperature = <90000>; 2033 hysteresis = <2000>; 2034 type = "passive"; 2035 }; 2036 2037 cpu4_bottom_alert1: trip-point1 { 2038 temperature = <95000>; 2039 hysteresis = <2000>; 2040 type = "passive"; 2041 }; 2042 2043 cpu4_bottom_crit: cpu_crit { 2044 temperature = <110000>; 2045 hysteresis = <1000>; 2046 type = "critical"; 2047 }; 2048 }; 2049 2050 cooling-maps { 2051 map0 { 2052 trip = <&cpu4_bottom_alert0>; 2053 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2054 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2055 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2056 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2057 }; 2058 map1 { 2059 trip = <&cpu4_bottom_alert1>; 2060 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2061 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2062 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2063 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2064 }; 2065 }; 2066 }; 2067 2068 cpu5-bottom-thermal { 2069 polling-delay-passive = <250>; 2070 polling-delay = <1000>; 2071 2072 thermal-sensors = <&tsens0 12>; 2073 2074 trips { 2075 cpu5_bottom_alert0: trip-point0 { 2076 temperature = <90000>; 2077 hysteresis = <2000>; 2078 type = "passive"; 2079 }; 2080 2081 cpu5_bottom_alert1: trip-point1 { 2082 temperature = <95000>; 2083 hysteresis = <2000>; 2084 type = "passive"; 2085 }; 2086 2087 cpu5_bottom_crit: cpu_crit { 2088 temperature = <110000>; 2089 hysteresis = <1000>; 2090 type = "critical"; 2091 }; 2092 }; 2093 2094 cooling-maps { 2095 map0 { 2096 trip = <&cpu5_bottom_alert0>; 2097 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2098 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2099 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2100 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2101 }; 2102 map1 { 2103 trip = <&cpu5_bottom_alert1>; 2104 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2105 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2106 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2107 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2108 }; 2109 }; 2110 }; 2111 2112 cpu6-bottom-thermal { 2113 polling-delay-passive = <250>; 2114 polling-delay = <1000>; 2115 2116 thermal-sensors = <&tsens0 13>; 2117 2118 trips { 2119 cpu6_bottom_alert0: trip-point0 { 2120 temperature = <90000>; 2121 hysteresis = <2000>; 2122 type = "passive"; 2123 }; 2124 2125 cpu6_bottom_alert1: trip-point1 { 2126 temperature = <95000>; 2127 hysteresis = <2000>; 2128 type = "passive"; 2129 }; 2130 2131 cpu6_bottom_crit: cpu_crit { 2132 temperature = <110000>; 2133 hysteresis = <1000>; 2134 type = "critical"; 2135 }; 2136 }; 2137 2138 cooling-maps { 2139 map0 { 2140 trip = <&cpu6_bottom_alert0>; 2141 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2142 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2143 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2144 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2145 }; 2146 map1 { 2147 trip = <&cpu6_bottom_alert1>; 2148 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2149 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2150 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2151 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2152 }; 2153 }; 2154 }; 2155 2156 cpu7-bottom-thermal { 2157 polling-delay-passive = <250>; 2158 polling-delay = <1000>; 2159 2160 thermal-sensors = <&tsens0 14>; 2161 2162 trips { 2163 cpu7_bottom_alert0: trip-point0 { 2164 temperature = <90000>; 2165 hysteresis = <2000>; 2166 type = "passive"; 2167 }; 2168 2169 cpu7_bottom_alert1: trip-point1 { 2170 temperature = <95000>; 2171 hysteresis = <2000>; 2172 type = "passive"; 2173 }; 2174 2175 cpu7_bottom_crit: cpu_crit { 2176 temperature = <110000>; 2177 hysteresis = <1000>; 2178 type = "critical"; 2179 }; 2180 }; 2181 2182 cooling-maps { 2183 map0 { 2184 trip = <&cpu7_bottom_alert0>; 2185 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2186 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2187 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2188 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2189 }; 2190 map1 { 2191 trip = <&cpu7_bottom_alert1>; 2192 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2193 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2194 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2195 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2196 }; 2197 }; 2198 }; 2199 2200 aoss0-thermal { 2201 polling-delay-passive = <250>; 2202 polling-delay = <1000>; 2203 2204 thermal-sensors = <&tsens0 0>; 2205 2206 trips { 2207 aoss0_alert0: trip-point0 { 2208 temperature = <90000>; 2209 hysteresis = <2000>; 2210 type = "hot"; 2211 }; 2212 }; 2213 }; 2214 2215 cluster0-thermal { 2216 polling-delay-passive = <250>; 2217 polling-delay = <1000>; 2218 2219 thermal-sensors = <&tsens0 5>; 2220 2221 trips { 2222 cluster0_alert0: trip-point0 { 2223 temperature = <90000>; 2224 hysteresis = <2000>; 2225 type = "hot"; 2226 }; 2227 cluster0_crit: cluster0_crit { 2228 temperature = <110000>; 2229 hysteresis = <2000>; 2230 type = "critical"; 2231 }; 2232 }; 2233 }; 2234 2235 cluster1-thermal { 2236 polling-delay-passive = <250>; 2237 polling-delay = <1000>; 2238 2239 thermal-sensors = <&tsens0 6>; 2240 2241 trips { 2242 cluster1_alert0: trip-point0 { 2243 temperature = <90000>; 2244 hysteresis = <2000>; 2245 type = "hot"; 2246 }; 2247 cluster1_crit: cluster1_crit { 2248 temperature = <110000>; 2249 hysteresis = <2000>; 2250 type = "critical"; 2251 }; 2252 }; 2253 }; 2254 2255 aoss1-thermal { 2256 polling-delay-passive = <250>; 2257 polling-delay = <1000>; 2258 2259 thermal-sensors = <&tsens1 0>; 2260 2261 trips { 2262 aoss1_alert0: trip-point0 { 2263 temperature = <90000>; 2264 hysteresis = <2000>; 2265 type = "hot"; 2266 }; 2267 }; 2268 }; 2269 2270 gpu-thermal-top { 2271 polling-delay-passive = <250>; 2272 polling-delay = <1000>; 2273 2274 thermal-sensors = <&tsens1 1>; 2275 2276 trips { 2277 gpu1_alert0: trip-point0 { 2278 temperature = <90000>; 2279 hysteresis = <1000>; 2280 type = "hot"; 2281 }; 2282 }; 2283 }; 2284 2285 gpu-thermal-bottom { 2286 polling-delay-passive = <250>; 2287 polling-delay = <1000>; 2288 2289 thermal-sensors = <&tsens1 2>; 2290 2291 trips { 2292 gpu2_alert0: trip-point0 { 2293 temperature = <90000>; 2294 hysteresis = <1000>; 2295 type = "hot"; 2296 }; 2297 }; 2298 }; 2299 2300 nspss1-thermal { 2301 polling-delay-passive = <250>; 2302 polling-delay = <1000>; 2303 2304 thermal-sensors = <&tsens1 3>; 2305 2306 trips { 2307 nspss1_alert0: trip-point0 { 2308 temperature = <90000>; 2309 hysteresis = <1000>; 2310 type = "hot"; 2311 }; 2312 }; 2313 }; 2314 2315 nspss2-thermal { 2316 polling-delay-passive = <250>; 2317 polling-delay = <1000>; 2318 2319 thermal-sensors = <&tsens1 4>; 2320 2321 trips { 2322 nspss2_alert0: trip-point0 { 2323 temperature = <90000>; 2324 hysteresis = <1000>; 2325 type = "hot"; 2326 }; 2327 }; 2328 }; 2329 2330 nspss3-thermal { 2331 polling-delay-passive = <250>; 2332 polling-delay = <1000>; 2333 2334 thermal-sensors = <&tsens1 5>; 2335 2336 trips { 2337 nspss3_alert0: trip-point0 { 2338 temperature = <90000>; 2339 hysteresis = <1000>; 2340 type = "hot"; 2341 }; 2342 }; 2343 }; 2344 2345 video-thermal { 2346 polling-delay-passive = <250>; 2347 polling-delay = <1000>; 2348 2349 thermal-sensors = <&tsens1 6>; 2350 2351 trips { 2352 video_alert0: trip-point0 { 2353 temperature = <90000>; 2354 hysteresis = <2000>; 2355 type = "hot"; 2356 }; 2357 }; 2358 }; 2359 2360 mem-thermal { 2361 polling-delay-passive = <250>; 2362 polling-delay = <1000>; 2363 2364 thermal-sensors = <&tsens1 7>; 2365 2366 trips { 2367 mem_alert0: trip-point0 { 2368 temperature = <90000>; 2369 hysteresis = <2000>; 2370 type = "hot"; 2371 }; 2372 }; 2373 }; 2374 2375 modem1-thermal-top { 2376 polling-delay-passive = <250>; 2377 polling-delay = <1000>; 2378 2379 thermal-sensors = <&tsens1 8>; 2380 2381 trips { 2382 modem1_alert0: trip-point0 { 2383 temperature = <90000>; 2384 hysteresis = <2000>; 2385 type = "hot"; 2386 }; 2387 }; 2388 }; 2389 2390 modem2-thermal-top { 2391 polling-delay-passive = <250>; 2392 polling-delay = <1000>; 2393 2394 thermal-sensors = <&tsens1 9>; 2395 2396 trips { 2397 modem2_alert0: trip-point0 { 2398 temperature = <90000>; 2399 hysteresis = <2000>; 2400 type = "hot"; 2401 }; 2402 }; 2403 }; 2404 2405 modem3-thermal-top { 2406 polling-delay-passive = <250>; 2407 polling-delay = <1000>; 2408 2409 thermal-sensors = <&tsens1 10>; 2410 2411 trips { 2412 modem3_alert0: trip-point0 { 2413 temperature = <90000>; 2414 hysteresis = <2000>; 2415 type = "hot"; 2416 }; 2417 }; 2418 }; 2419 2420 modem4-thermal-top { 2421 polling-delay-passive = <250>; 2422 polling-delay = <1000>; 2423 2424 thermal-sensors = <&tsens1 11>; 2425 2426 trips { 2427 modem4_alert0: trip-point0 { 2428 temperature = <90000>; 2429 hysteresis = <2000>; 2430 type = "hot"; 2431 }; 2432 }; 2433 }; 2434 2435 camera-thermal-top { 2436 polling-delay-passive = <250>; 2437 polling-delay = <1000>; 2438 2439 thermal-sensors = <&tsens1 12>; 2440 2441 trips { 2442 camera1_alert0: trip-point0 { 2443 temperature = <90000>; 2444 hysteresis = <2000>; 2445 type = "hot"; 2446 }; 2447 }; 2448 }; 2449 2450 camera-thermal-bottom { 2451 polling-delay-passive = <250>; 2452 polling-delay = <1000>; 2453 2454 thermal-sensors = <&tsens1 13>; 2455 2456 trips { 2457 camera2_alert0: trip-point0 { 2458 temperature = <90000>; 2459 hysteresis = <2000>; 2460 type = "hot"; 2461 }; 2462 }; 2463 }; 2464 }; 2465 2466 timer { 2467 compatible = "arm,armv8-timer"; 2468 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2469 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2470 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2471 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2472 }; 2473}; 2474