1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/interconnect/qcom,sm8350.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <38400000>; 38 clock-output-names = "xo_board"; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32000>; 44 #clock-cells = <0>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 CPU0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 L3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_200>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 #cooling-cells = <2>; 106 L2_200: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&L3_0>; 111 }; 112 }; 113 114 CPU3: cpu@300 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a55"; 117 reg = <0x0 0x300>; 118 clocks = <&cpufreq_hw 0>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU4: cpu@400 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a78"; 136 reg = <0x0 0x400>; 137 clocks = <&cpufreq_hw 1>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_400>; 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 power-domains = <&CPU_PD4>; 142 power-domain-names = "psci"; 143 #cooling-cells = <2>; 144 L2_400: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a78"; 155 reg = <0x0 0x500>; 156 clocks = <&cpufreq_hw 1>; 157 enable-method = "psci"; 158 next-level-cache = <&L2_500>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 power-domains = <&CPU_PD5>; 161 power-domain-names = "psci"; 162 #cooling-cells = <2>; 163 L2_500: l2-cache { 164 compatible = "cache"; 165 cache-level = <2>; 166 cache-unified; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU6: cpu@600 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a78"; 174 reg = <0x0 0x600>; 175 clocks = <&cpufreq_hw 1>; 176 enable-method = "psci"; 177 next-level-cache = <&L2_600>; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 power-domains = <&CPU_PD6>; 180 power-domain-names = "psci"; 181 #cooling-cells = <2>; 182 L2_600: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 }; 188 }; 189 190 CPU7: cpu@700 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-x1"; 193 reg = <0x0 0x700>; 194 clocks = <&cpufreq_hw 2>; 195 enable-method = "psci"; 196 next-level-cache = <&L2_700>; 197 qcom,freq-domain = <&cpufreq_hw 2>; 198 power-domains = <&CPU_PD7>; 199 power-domain-names = "psci"; 200 #cooling-cells = <2>; 201 L2_700: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 cpu-map { 210 cluster0 { 211 core0 { 212 cpu = <&CPU0>; 213 }; 214 215 core1 { 216 cpu = <&CPU1>; 217 }; 218 219 core2 { 220 cpu = <&CPU2>; 221 }; 222 223 core3 { 224 cpu = <&CPU3>; 225 }; 226 227 core4 { 228 cpu = <&CPU4>; 229 }; 230 231 core5 { 232 cpu = <&CPU5>; 233 }; 234 235 core6 { 236 cpu = <&CPU6>; 237 }; 238 239 core7 { 240 cpu = <&CPU7>; 241 }; 242 }; 243 }; 244 245 idle-states { 246 entry-method = "psci"; 247 248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 249 compatible = "arm,idle-state"; 250 idle-state-name = "silver-rail-power-collapse"; 251 arm,psci-suspend-param = <0x40000004>; 252 entry-latency-us = <360>; 253 exit-latency-us = <531>; 254 min-residency-us = <3934>; 255 local-timer-stop; 256 }; 257 258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 259 compatible = "arm,idle-state"; 260 idle-state-name = "gold-rail-power-collapse"; 261 arm,psci-suspend-param = <0x40000004>; 262 entry-latency-us = <702>; 263 exit-latency-us = <1061>; 264 min-residency-us = <4488>; 265 local-timer-stop; 266 }; 267 }; 268 269 domain-idle-states { 270 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 271 compatible = "domain-idle-state"; 272 arm,psci-suspend-param = <0x41000044>; 273 entry-latency-us = <2752>; 274 exit-latency-us = <3048>; 275 min-residency-us = <6118>; 276 }; 277 278 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x4100c344>; 281 entry-latency-us = <3263>; 282 exit-latency-us = <6562>; 283 min-residency-us = <9987>; 284 }; 285 }; 286 }; 287 288 firmware { 289 scm: scm { 290 compatible = "qcom,scm-sm8350", "qcom,scm"; 291 #reset-cells = <1>; 292 }; 293 }; 294 295 memory@80000000 { 296 device_type = "memory"; 297 /* We expect the bootloader to fill in the size */ 298 reg = <0x0 0x80000000 0x0 0x0>; 299 }; 300 301 pmu { 302 compatible = "arm,armv8-pmuv3"; 303 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 304 }; 305 306 psci { 307 compatible = "arm,psci-1.0"; 308 method = "smc"; 309 310 CPU_PD0: power-domain-cpu0 { 311 #power-domain-cells = <0>; 312 power-domains = <&CLUSTER_PD>; 313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 314 }; 315 316 CPU_PD1: power-domain-cpu1 { 317 #power-domain-cells = <0>; 318 power-domains = <&CLUSTER_PD>; 319 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 320 }; 321 322 CPU_PD2: power-domain-cpu2 { 323 #power-domain-cells = <0>; 324 power-domains = <&CLUSTER_PD>; 325 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 326 }; 327 328 CPU_PD3: power-domain-cpu3 { 329 #power-domain-cells = <0>; 330 power-domains = <&CLUSTER_PD>; 331 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 332 }; 333 334 CPU_PD4: power-domain-cpu4 { 335 #power-domain-cells = <0>; 336 power-domains = <&CLUSTER_PD>; 337 domain-idle-states = <&BIG_CPU_SLEEP_0>; 338 }; 339 340 CPU_PD5: power-domain-cpu5 { 341 #power-domain-cells = <0>; 342 power-domains = <&CLUSTER_PD>; 343 domain-idle-states = <&BIG_CPU_SLEEP_0>; 344 }; 345 346 CPU_PD6: power-domain-cpu6 { 347 #power-domain-cells = <0>; 348 power-domains = <&CLUSTER_PD>; 349 domain-idle-states = <&BIG_CPU_SLEEP_0>; 350 }; 351 352 CPU_PD7: power-domain-cpu7 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD>; 355 domain-idle-states = <&BIG_CPU_SLEEP_0>; 356 }; 357 358 CLUSTER_PD: power-domain-cpu-cluster0 { 359 #power-domain-cells = <0>; 360 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 361 }; 362 }; 363 364 qup_opp_table_100mhz: opp-table-qup100mhz { 365 compatible = "operating-points-v2"; 366 367 opp-50000000 { 368 opp-hz = /bits/ 64 <50000000>; 369 required-opps = <&rpmhpd_opp_min_svs>; 370 }; 371 372 opp-75000000 { 373 opp-hz = /bits/ 64 <75000000>; 374 required-opps = <&rpmhpd_opp_low_svs>; 375 }; 376 377 opp-100000000 { 378 opp-hz = /bits/ 64 <100000000>; 379 required-opps = <&rpmhpd_opp_svs>; 380 }; 381 }; 382 383 qup_opp_table_120mhz: opp-table-qup120mhz { 384 compatible = "operating-points-v2"; 385 386 opp-50000000 { 387 opp-hz = /bits/ 64 <50000000>; 388 required-opps = <&rpmhpd_opp_min_svs>; 389 }; 390 391 opp-75000000 { 392 opp-hz = /bits/ 64 <75000000>; 393 required-opps = <&rpmhpd_opp_low_svs>; 394 }; 395 396 opp-120000000 { 397 opp-hz = /bits/ 64 <120000000>; 398 required-opps = <&rpmhpd_opp_svs>; 399 }; 400 }; 401 402 reserved_memory: reserved-memory { 403 #address-cells = <2>; 404 #size-cells = <2>; 405 ranges; 406 407 hyp_mem: memory@80000000 { 408 reg = <0x0 0x80000000 0x0 0x600000>; 409 no-map; 410 }; 411 412 xbl_aop_mem: memory@80700000 { 413 no-map; 414 reg = <0x0 0x80700000 0x0 0x160000>; 415 }; 416 417 cmd_db: memory@80860000 { 418 compatible = "qcom,cmd-db"; 419 reg = <0x0 0x80860000 0x0 0x20000>; 420 no-map; 421 }; 422 423 reserved_xbl_uefi_log: memory@80880000 { 424 reg = <0x0 0x80880000 0x0 0x14000>; 425 no-map; 426 }; 427 428 smem@80900000 { 429 compatible = "qcom,smem"; 430 reg = <0x0 0x80900000 0x0 0x200000>; 431 hwlocks = <&tcsr_mutex 3>; 432 no-map; 433 }; 434 435 cpucp_fw_mem: memory@80b00000 { 436 reg = <0x0 0x80b00000 0x0 0x100000>; 437 no-map; 438 }; 439 440 cdsp_secure_heap: memory@80c00000 { 441 reg = <0x0 0x80c00000 0x0 0x4600000>; 442 no-map; 443 }; 444 445 pil_camera_mem: mmeory@85200000 { 446 reg = <0x0 0x85200000 0x0 0x500000>; 447 no-map; 448 }; 449 450 pil_video_mem: memory@85700000 { 451 reg = <0x0 0x85700000 0x0 0x500000>; 452 no-map; 453 }; 454 455 pil_cvp_mem: memory@85c00000 { 456 reg = <0x0 0x85c00000 0x0 0x500000>; 457 no-map; 458 }; 459 460 pil_adsp_mem: memory@86100000 { 461 reg = <0x0 0x86100000 0x0 0x2100000>; 462 no-map; 463 }; 464 465 pil_slpi_mem: memory@88200000 { 466 reg = <0x0 0x88200000 0x0 0x1500000>; 467 no-map; 468 }; 469 470 pil_cdsp_mem: memory@89700000 { 471 reg = <0x0 0x89700000 0x0 0x1e00000>; 472 no-map; 473 }; 474 475 pil_ipa_fw_mem: memory@8b500000 { 476 reg = <0x0 0x8b500000 0x0 0x10000>; 477 no-map; 478 }; 479 480 pil_ipa_gsi_mem: memory@8b510000 { 481 reg = <0x0 0x8b510000 0x0 0xa000>; 482 no-map; 483 }; 484 485 pil_gpu_mem: memory@8b51a000 { 486 reg = <0x0 0x8b51a000 0x0 0x2000>; 487 no-map; 488 }; 489 490 pil_spss_mem: memory@8b600000 { 491 reg = <0x0 0x8b600000 0x0 0x100000>; 492 no-map; 493 }; 494 495 pil_modem_mem: memory@8b800000 { 496 reg = <0x0 0x8b800000 0x0 0x10000000>; 497 no-map; 498 }; 499 500 rmtfs_mem: memory@9b800000 { 501 compatible = "qcom,rmtfs-mem"; 502 reg = <0x0 0x9b800000 0x0 0x280000>; 503 no-map; 504 505 qcom,client-id = <1>; 506 qcom,vmid = <15>; 507 }; 508 509 hyp_reserved_mem: memory@d0000000 { 510 reg = <0x0 0xd0000000 0x0 0x800000>; 511 no-map; 512 }; 513 514 pil_trustedvm_mem: memory@d0800000 { 515 reg = <0x0 0xd0800000 0x0 0x76f7000>; 516 no-map; 517 }; 518 519 qrtr_shbuf: memory@d7ef7000 { 520 reg = <0x0 0xd7ef7000 0x0 0x9000>; 521 no-map; 522 }; 523 524 chan0_shbuf: memory@d7f00000 { 525 reg = <0x0 0xd7f00000 0x0 0x80000>; 526 no-map; 527 }; 528 529 chan1_shbuf: memory@d7f80000 { 530 reg = <0x0 0xd7f80000 0x0 0x80000>; 531 no-map; 532 }; 533 534 removed_mem: memory@d8800000 { 535 reg = <0x0 0xd8800000 0x0 0x6800000>; 536 no-map; 537 }; 538 }; 539 540 smp2p-adsp { 541 compatible = "qcom,smp2p"; 542 qcom,smem = <443>, <429>; 543 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 544 IPCC_MPROC_SIGNAL_SMP2P 545 IRQ_TYPE_EDGE_RISING>; 546 mboxes = <&ipcc IPCC_CLIENT_LPASS 547 IPCC_MPROC_SIGNAL_SMP2P>; 548 549 qcom,local-pid = <0>; 550 qcom,remote-pid = <2>; 551 552 smp2p_adsp_out: master-kernel { 553 qcom,entry-name = "master-kernel"; 554 #qcom,smem-state-cells = <1>; 555 }; 556 557 smp2p_adsp_in: slave-kernel { 558 qcom,entry-name = "slave-kernel"; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 }; 562 }; 563 564 smp2p-cdsp { 565 compatible = "qcom,smp2p"; 566 qcom,smem = <94>, <432>; 567 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 568 IPCC_MPROC_SIGNAL_SMP2P 569 IRQ_TYPE_EDGE_RISING>; 570 mboxes = <&ipcc IPCC_CLIENT_CDSP 571 IPCC_MPROC_SIGNAL_SMP2P>; 572 573 qcom,local-pid = <0>; 574 qcom,remote-pid = <5>; 575 576 smp2p_cdsp_out: master-kernel { 577 qcom,entry-name = "master-kernel"; 578 #qcom,smem-state-cells = <1>; 579 }; 580 581 smp2p_cdsp_in: slave-kernel { 582 qcom,entry-name = "slave-kernel"; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 }; 587 588 smp2p-modem { 589 compatible = "qcom,smp2p"; 590 qcom,smem = <435>, <428>; 591 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 592 IPCC_MPROC_SIGNAL_SMP2P 593 IRQ_TYPE_EDGE_RISING>; 594 mboxes = <&ipcc IPCC_CLIENT_MPSS 595 IPCC_MPROC_SIGNAL_SMP2P>; 596 597 qcom,local-pid = <0>; 598 qcom,remote-pid = <1>; 599 600 smp2p_modem_out: master-kernel { 601 qcom,entry-name = "master-kernel"; 602 #qcom,smem-state-cells = <1>; 603 }; 604 605 smp2p_modem_in: slave-kernel { 606 qcom,entry-name = "slave-kernel"; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 ipa_smp2p_out: ipa-ap-to-modem { 612 qcom,entry-name = "ipa"; 613 #qcom,smem-state-cells = <1>; 614 }; 615 616 ipa_smp2p_in: ipa-modem-to-ap { 617 qcom,entry-name = "ipa"; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 }; 621 }; 622 623 smp2p-slpi { 624 compatible = "qcom,smp2p"; 625 qcom,smem = <481>, <430>; 626 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 627 IPCC_MPROC_SIGNAL_SMP2P 628 IRQ_TYPE_EDGE_RISING>; 629 mboxes = <&ipcc IPCC_CLIENT_SLPI 630 IPCC_MPROC_SIGNAL_SMP2P>; 631 632 qcom,local-pid = <0>; 633 qcom,remote-pid = <3>; 634 635 smp2p_slpi_out: master-kernel { 636 qcom,entry-name = "master-kernel"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 smp2p_slpi_in: slave-kernel { 641 qcom,entry-name = "slave-kernel"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 }; 646 647 soc: soc@0 { 648 #address-cells = <2>; 649 #size-cells = <2>; 650 ranges = <0 0 0 0 0x10 0>; 651 dma-ranges = <0 0 0 0 0x10 0>; 652 compatible = "simple-bus"; 653 654 gcc: clock-controller@100000 { 655 compatible = "qcom,gcc-sm8350"; 656 reg = <0x0 0x00100000 0x0 0x1f0000>; 657 #clock-cells = <1>; 658 #reset-cells = <1>; 659 #power-domain-cells = <1>; 660 clock-names = "bi_tcxo", 661 "sleep_clk", 662 "pcie_0_pipe_clk", 663 "pcie_1_pipe_clk", 664 "ufs_card_rx_symbol_0_clk", 665 "ufs_card_rx_symbol_1_clk", 666 "ufs_card_tx_symbol_0_clk", 667 "ufs_phy_rx_symbol_0_clk", 668 "ufs_phy_rx_symbol_1_clk", 669 "ufs_phy_tx_symbol_0_clk", 670 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 671 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 672 clocks = <&rpmhcc RPMH_CXO_CLK>, 673 <&sleep_clk>, 674 <&pcie0_phy>, 675 <&pcie1_phy>, 676 <0>, 677 <0>, 678 <0>, 679 <&ufs_mem_phy_lanes 0>, 680 <&ufs_mem_phy_lanes 1>, 681 <&ufs_mem_phy_lanes 2>, 682 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 683 <0>; 684 }; 685 686 ipcc: mailbox@408000 { 687 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 688 reg = <0 0x00408000 0 0x1000>; 689 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-controller; 691 #interrupt-cells = <3>; 692 #mbox-cells = <2>; 693 }; 694 695 gpi_dma2: dma-controller@800000 { 696 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 697 reg = <0 0x00800000 0 0x60000>; 698 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 710 dma-channels = <12>; 711 dma-channel-mask = <0xff>; 712 iommus = <&apps_smmu 0x5f6 0x0>; 713 #dma-cells = <3>; 714 status = "disabled"; 715 }; 716 717 qupv3_id_2: geniqup@8c0000 { 718 compatible = "qcom,geni-se-qup"; 719 reg = <0x0 0x008c0000 0x0 0x6000>; 720 clock-names = "m-ahb", "s-ahb"; 721 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 722 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 723 iommus = <&apps_smmu 0x5e3 0x0>; 724 #address-cells = <2>; 725 #size-cells = <2>; 726 ranges; 727 status = "disabled"; 728 729 i2c14: i2c@880000 { 730 compatible = "qcom,geni-i2c"; 731 reg = <0 0x00880000 0 0x4000>; 732 clock-names = "se"; 733 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&qup_i2c14_default>; 736 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 737 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 738 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 739 dma-names = "tx", "rx"; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 spi14: spi@880000 { 746 compatible = "qcom,geni-spi"; 747 reg = <0 0x00880000 0 0x4000>; 748 clock-names = "se"; 749 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 750 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 751 power-domains = <&rpmhpd RPMHPD_CX>; 752 operating-points-v2 = <&qup_opp_table_120mhz>; 753 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 754 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 755 dma-names = "tx", "rx"; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 i2c15: i2c@884000 { 762 compatible = "qcom,geni-i2c"; 763 reg = <0 0x00884000 0 0x4000>; 764 clock-names = "se"; 765 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&qup_i2c15_default>; 768 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 769 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 770 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 771 dma-names = "tx", "rx"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 spi15: spi@884000 { 778 compatible = "qcom,geni-spi"; 779 reg = <0 0x00884000 0 0x4000>; 780 clock-names = "se"; 781 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 782 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 783 power-domains = <&rpmhpd RPMHPD_CX>; 784 operating-points-v2 = <&qup_opp_table_120mhz>; 785 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 786 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 787 dma-names = "tx", "rx"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 i2c16: i2c@888000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0 0x00888000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c16_default>; 800 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 801 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 802 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 803 dma-names = "tx", "rx"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 spi16: spi@888000 { 810 compatible = "qcom,geni-spi"; 811 reg = <0 0x00888000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 814 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 815 power-domains = <&rpmhpd RPMHPD_CX>; 816 operating-points-v2 = <&qup_opp_table_100mhz>; 817 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 818 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 819 dma-names = "tx", "rx"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 i2c17: i2c@88c000 { 826 compatible = "qcom,geni-i2c"; 827 reg = <0 0x0088c000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&qup_i2c17_default>; 832 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 833 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 834 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 835 dma-names = "tx", "rx"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 spi17: spi@88c000 { 842 compatible = "qcom,geni-spi"; 843 reg = <0 0x0088c000 0 0x4000>; 844 clock-names = "se"; 845 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 846 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 847 power-domains = <&rpmhpd RPMHPD_CX>; 848 operating-points-v2 = <&qup_opp_table_100mhz>; 849 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 850 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 /* QUP no. 18 seems to be strictly SPI/UART-only */ 858 859 spi18: spi@890000 { 860 compatible = "qcom,geni-spi"; 861 reg = <0 0x00890000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 864 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 865 power-domains = <&rpmhpd RPMHPD_CX>; 866 operating-points-v2 = <&qup_opp_table_100mhz>; 867 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 869 dma-names = "tx", "rx"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 status = "disabled"; 873 }; 874 875 uart18: serial@890000 { 876 compatible = "qcom,geni-uart"; 877 reg = <0 0x00890000 0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_uart18_default>; 882 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&rpmhpd RPMHPD_CX>; 884 operating-points-v2 = <&qup_opp_table_100mhz>; 885 status = "disabled"; 886 }; 887 888 i2c19: i2c@894000 { 889 compatible = "qcom,geni-i2c"; 890 reg = <0 0x00894000 0 0x4000>; 891 clock-names = "se"; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_i2c19_default>; 895 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 896 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 897 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 898 dma-names = "tx", "rx"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 spi19: spi@894000 { 905 compatible = "qcom,geni-spi"; 906 reg = <0 0x00894000 0 0x4000>; 907 clock-names = "se"; 908 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 909 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 910 power-domains = <&rpmhpd RPMHPD_CX>; 911 operating-points-v2 = <&qup_opp_table_100mhz>; 912 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 913 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 914 dma-names = "tx", "rx"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 }; 920 921 gpi_dma0: dma-controller@9800000 { 922 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 923 reg = <0 0x09800000 0 0x60000>; 924 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 936 dma-channels = <12>; 937 dma-channel-mask = <0x7e>; 938 iommus = <&apps_smmu 0x5b6 0x0>; 939 #dma-cells = <3>; 940 status = "disabled"; 941 }; 942 943 qupv3_id_0: geniqup@9c0000 { 944 compatible = "qcom,geni-se-qup"; 945 reg = <0x0 0x009c0000 0x0 0x6000>; 946 clock-names = "m-ahb", "s-ahb"; 947 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 948 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 949 iommus = <&apps_smmu 0x5a3 0>; 950 #address-cells = <2>; 951 #size-cells = <2>; 952 ranges; 953 status = "disabled"; 954 955 i2c0: i2c@980000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00980000 0 0x4000>; 958 clock-names = "se"; 959 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_i2c0_default>; 962 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 963 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 964 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 965 dma-names = "tx", "rx"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi0: spi@980000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x00980000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 976 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 977 power-domains = <&rpmhpd RPMHPD_CX>; 978 operating-points-v2 = <&qup_opp_table_100mhz>; 979 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 980 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c1: i2c@984000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00984000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c1_default>; 994 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 995 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 996 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 spi1: spi@984000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0 0x00984000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1008 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1009 power-domains = <&rpmhpd RPMHPD_CX>; 1010 operating-points-v2 = <&qup_opp_table_100mhz>; 1011 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1012 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c2: i2c@988000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00988000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_i2c2_default>; 1026 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1027 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 spi2: spi@988000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00988000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1040 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1041 power-domains = <&rpmhpd RPMHPD_CX>; 1042 operating-points-v2 = <&qup_opp_table_100mhz>; 1043 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1044 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 uart2: serial@98c000 { 1052 compatible = "qcom,geni-debug-uart"; 1053 reg = <0 0x0098c000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_uart3_default_state>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd RPMHPD_CX>; 1060 operating-points-v2 = <&qup_opp_table_100mhz>; 1061 status = "disabled"; 1062 }; 1063 1064 /* QUP no. 3 seems to be strictly SPI-only */ 1065 1066 spi3: spi@98c000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0 0x0098c000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table_100mhz>; 1074 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1075 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1076 dma-names = "tx", "rx"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 i2c4: i2c@990000 { 1083 compatible = "qcom,geni-i2c"; 1084 reg = <0 0x00990000 0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_i2c4_default>; 1089 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1090 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1091 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 spi4: spi@990000 { 1099 compatible = "qcom,geni-spi"; 1100 reg = <0 0x00990000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1103 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd RPMHPD_CX>; 1105 operating-points-v2 = <&qup_opp_table_100mhz>; 1106 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1107 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1108 dma-names = "tx", "rx"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c5: i2c@994000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00994000 0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c5_default>; 1121 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1122 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1123 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1124 dma-names = "tx", "rx"; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 spi5: spi@994000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00994000 0 0x4000>; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1135 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1136 power-domains = <&rpmhpd RPMHPD_CX>; 1137 operating-points-v2 = <&qup_opp_table_100mhz>; 1138 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1139 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1140 dma-names = "tx", "rx"; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 i2c6: i2c@998000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x00998000 0 0x4000>; 1149 clock-names = "se"; 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c6_default>; 1153 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1154 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1155 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 spi6: spi@998000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00998000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1167 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1168 power-domains = <&rpmhpd RPMHPD_CX>; 1169 operating-points-v2 = <&qup_opp_table_100mhz>; 1170 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1171 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1172 dma-names = "tx", "rx"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 uart6: serial@998000 { 1179 compatible = "qcom,geni-uart"; 1180 reg = <0 0x00998000 0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_uart6_default>; 1185 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1186 power-domains = <&rpmhpd RPMHPD_CX>; 1187 operating-points-v2 = <&qup_opp_table_100mhz>; 1188 status = "disabled"; 1189 }; 1190 1191 i2c7: i2c@99c000 { 1192 compatible = "qcom,geni-i2c"; 1193 reg = <0 0x0099c000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_i2c7_default>; 1198 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1199 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1200 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1201 dma-names = "tx", "rx"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 spi7: spi@99c000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x0099c000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1212 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1213 power-domains = <&rpmhpd RPMHPD_CX>; 1214 operating-points-v2 = <&qup_opp_table_100mhz>; 1215 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1216 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1217 dma-names = "tx", "rx"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 gpi_dma1: dma-controller@a00000 { 1225 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1226 reg = <0 0x00a00000 0 0x60000>; 1227 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1239 dma-channels = <12>; 1240 dma-channel-mask = <0xff>; 1241 iommus = <&apps_smmu 0x56 0x0>; 1242 #dma-cells = <3>; 1243 status = "disabled"; 1244 }; 1245 1246 qupv3_id_1: geniqup@ac0000 { 1247 compatible = "qcom,geni-se-qup"; 1248 reg = <0x0 0x00ac0000 0x0 0x6000>; 1249 clock-names = "m-ahb", "s-ahb"; 1250 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1251 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1252 iommus = <&apps_smmu 0x43 0>; 1253 #address-cells = <2>; 1254 #size-cells = <2>; 1255 ranges; 1256 status = "disabled"; 1257 1258 i2c8: i2c@a80000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0 0x00a80000 0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_i2c8_default>; 1265 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1266 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1267 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1268 dma-names = "tx", "rx"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 spi8: spi@a80000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a80000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1279 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd RPMHPD_CX>; 1281 operating-points-v2 = <&qup_opp_table_120mhz>; 1282 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1283 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1284 dma-names = "tx", "rx"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c9: i2c@a84000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0 0x00a84000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c9_default>; 1297 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 spi9: spi@a84000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0 0x00a84000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1311 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1312 power-domains = <&rpmhpd RPMHPD_CX>; 1313 operating-points-v2 = <&qup_opp_table_100mhz>; 1314 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1315 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1316 dma-names = "tx", "rx"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c10: i2c@a88000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a88000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c10_default>; 1329 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1330 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1331 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1332 dma-names = "tx", "rx"; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 spi10: spi@a88000 { 1339 compatible = "qcom,geni-spi"; 1340 reg = <0 0x00a88000 0 0x4000>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1343 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd RPMHPD_CX>; 1345 operating-points-v2 = <&qup_opp_table_100mhz>; 1346 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1347 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1348 dma-names = "tx", "rx"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 status = "disabled"; 1352 }; 1353 1354 i2c11: i2c@a8c000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a8c000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c11_default>; 1361 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1362 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1363 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1364 dma-names = "tx", "rx"; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 status = "disabled"; 1368 }; 1369 1370 spi11: spi@a8c000 { 1371 compatible = "qcom,geni-spi"; 1372 reg = <0 0x00a8c000 0 0x4000>; 1373 clock-names = "se"; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1375 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1376 power-domains = <&rpmhpd RPMHPD_CX>; 1377 operating-points-v2 = <&qup_opp_table_100mhz>; 1378 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1379 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c12: i2c@a90000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x00a90000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c12_default>; 1393 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1394 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1395 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1396 dma-names = "tx", "rx"; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 spi12: spi@a90000 { 1403 compatible = "qcom,geni-spi"; 1404 reg = <0 0x00a90000 0 0x4000>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1407 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 operating-points-v2 = <&qup_opp_table_100mhz>; 1410 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1411 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1412 dma-names = "tx", "rx"; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 i2c13: i2c@a94000 { 1419 compatible = "qcom,geni-i2c"; 1420 reg = <0 0x00a94000 0 0x4000>; 1421 clock-names = "se"; 1422 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_i2c13_default>; 1425 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1427 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1428 dma-names = "tx", "rx"; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 status = "disabled"; 1432 }; 1433 1434 spi13: spi@a94000 { 1435 compatible = "qcom,geni-spi"; 1436 reg = <0 0x00a94000 0 0x4000>; 1437 clock-names = "se"; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1439 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd RPMHPD_CX>; 1441 operating-points-v2 = <&qup_opp_table_100mhz>; 1442 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1443 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1444 dma-names = "tx", "rx"; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 status = "disabled"; 1448 }; 1449 }; 1450 1451 rng: rng@10d3000 { 1452 compatible = "qcom,prng-ee"; 1453 reg = <0 0x010d3000 0 0x1000>; 1454 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1455 clock-names = "core"; 1456 }; 1457 1458 config_noc: interconnect@1500000 { 1459 compatible = "qcom,sm8350-config-noc"; 1460 reg = <0 0x01500000 0 0xa580>; 1461 #interconnect-cells = <2>; 1462 qcom,bcm-voters = <&apps_bcm_voter>; 1463 }; 1464 1465 mc_virt: interconnect@1580000 { 1466 compatible = "qcom,sm8350-mc-virt"; 1467 reg = <0 0x01580000 0 0x1000>; 1468 #interconnect-cells = <2>; 1469 qcom,bcm-voters = <&apps_bcm_voter>; 1470 }; 1471 1472 system_noc: interconnect@1680000 { 1473 compatible = "qcom,sm8350-system-noc"; 1474 reg = <0 0x01680000 0 0x1c200>; 1475 #interconnect-cells = <2>; 1476 qcom,bcm-voters = <&apps_bcm_voter>; 1477 }; 1478 1479 aggre1_noc: interconnect@16e0000 { 1480 compatible = "qcom,sm8350-aggre1-noc"; 1481 reg = <0 0x016e0000 0 0x1f180>; 1482 #interconnect-cells = <2>; 1483 qcom,bcm-voters = <&apps_bcm_voter>; 1484 }; 1485 1486 aggre2_noc: interconnect@1700000 { 1487 compatible = "qcom,sm8350-aggre2-noc"; 1488 reg = <0 0x01700000 0 0x33000>; 1489 #interconnect-cells = <2>; 1490 qcom,bcm-voters = <&apps_bcm_voter>; 1491 }; 1492 1493 mmss_noc: interconnect@1740000 { 1494 compatible = "qcom,sm8350-mmss-noc"; 1495 reg = <0 0x01740000 0 0x1f080>; 1496 #interconnect-cells = <2>; 1497 qcom,bcm-voters = <&apps_bcm_voter>; 1498 }; 1499 1500 pcie0: pci@1c00000 { 1501 compatible = "qcom,pcie-sm8350"; 1502 reg = <0 0x01c00000 0 0x3000>, 1503 <0 0x60000000 0 0xf1d>, 1504 <0 0x60000f20 0 0xa8>, 1505 <0 0x60001000 0 0x1000>, 1506 <0 0x60100000 0 0x100000>; 1507 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1508 device_type = "pci"; 1509 linux,pci-domain = <0>; 1510 bus-range = <0x00 0xff>; 1511 num-lanes = <1>; 1512 1513 #address-cells = <3>; 1514 #size-cells = <2>; 1515 1516 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1517 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1518 1519 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1527 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1528 "msi4", "msi5", "msi6", "msi7"; 1529 #interrupt-cells = <1>; 1530 interrupt-map-mask = <0 0 0 0x7>; 1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1532 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1533 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1534 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1535 1536 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1537 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1538 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1539 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1540 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1541 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1542 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1543 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1544 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1545 clock-names = "aux", 1546 "cfg", 1547 "bus_master", 1548 "bus_slave", 1549 "slave_q2a", 1550 "tbu", 1551 "ddrss_sf_tbu", 1552 "aggre1", 1553 "aggre0"; 1554 1555 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1556 <0x100 &apps_smmu 0x1c01 0x1>; 1557 1558 resets = <&gcc GCC_PCIE_0_BCR>; 1559 reset-names = "pci"; 1560 1561 power-domains = <&gcc PCIE_0_GDSC>; 1562 1563 phys = <&pcie0_phy>; 1564 phy-names = "pciephy"; 1565 1566 status = "disabled"; 1567 }; 1568 1569 pcie0_phy: phy@1c06000 { 1570 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1571 reg = <0 0x01c06000 0 0x2000>; 1572 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1573 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1574 <&gcc GCC_PCIE_0_CLKREF_EN>, 1575 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1576 <&gcc GCC_PCIE_0_PIPE_CLK>; 1577 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1578 1579 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1580 reset-names = "phy"; 1581 1582 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1583 assigned-clock-rates = <100000000>; 1584 1585 #clock-cells = <0>; 1586 clock-output-names = "pcie_0_pipe_clk"; 1587 1588 #phy-cells = <0>; 1589 1590 status = "disabled"; 1591 }; 1592 1593 pcie1: pci@1c08000 { 1594 compatible = "qcom,pcie-sm8350"; 1595 reg = <0 0x01c08000 0 0x3000>, 1596 <0 0x40000000 0 0xf1d>, 1597 <0 0x40000f20 0 0xa8>, 1598 <0 0x40001000 0 0x1000>, 1599 <0 0x40100000 0 0x100000>; 1600 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1601 device_type = "pci"; 1602 linux,pci-domain = <1>; 1603 bus-range = <0x00 0xff>; 1604 num-lanes = <2>; 1605 1606 #address-cells = <3>; 1607 #size-cells = <2>; 1608 1609 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1610 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1611 1612 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1613 interrupt-names = "msi"; 1614 #interrupt-cells = <1>; 1615 interrupt-map-mask = <0 0 0 0x7>; 1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1617 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1618 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1619 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1620 1621 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1622 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1623 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1624 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1625 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1626 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1627 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1628 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1629 clock-names = "aux", 1630 "cfg", 1631 "bus_master", 1632 "bus_slave", 1633 "slave_q2a", 1634 "tbu", 1635 "ddrss_sf_tbu", 1636 "aggre1"; 1637 1638 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1639 <0x100 &apps_smmu 0x1c81 0x1>; 1640 1641 resets = <&gcc GCC_PCIE_1_BCR>; 1642 reset-names = "pci"; 1643 1644 power-domains = <&gcc PCIE_1_GDSC>; 1645 1646 phys = <&pcie1_phy>; 1647 phy-names = "pciephy"; 1648 1649 status = "disabled"; 1650 }; 1651 1652 pcie1_phy: phy@1c0e000 { 1653 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1654 reg = <0 0x01c0e000 0 0x2000>; 1655 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1656 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1657 <&gcc GCC_PCIE_1_CLKREF_EN>, 1658 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1659 <&gcc GCC_PCIE_1_PIPE_CLK>; 1660 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1661 1662 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1663 reset-names = "phy"; 1664 1665 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1666 assigned-clock-rates = <100000000>; 1667 1668 #clock-cells = <0>; 1669 clock-output-names = "pcie_1_pipe_clk"; 1670 1671 #phy-cells = <0>; 1672 1673 status = "disabled"; 1674 }; 1675 1676 ufs_mem_hc: ufshc@1d84000 { 1677 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1678 "jedec,ufs-2.0"; 1679 reg = <0 0x01d84000 0 0x3000>; 1680 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1681 phys = <&ufs_mem_phy_lanes>; 1682 phy-names = "ufsphy"; 1683 lanes-per-direction = <2>; 1684 #reset-cells = <1>; 1685 resets = <&gcc GCC_UFS_PHY_BCR>; 1686 reset-names = "rst"; 1687 1688 power-domains = <&gcc UFS_PHY_GDSC>; 1689 1690 iommus = <&apps_smmu 0xe0 0x0>; 1691 dma-coherent; 1692 1693 clock-names = 1694 "core_clk", 1695 "bus_aggr_clk", 1696 "iface_clk", 1697 "core_clk_unipro", 1698 "ref_clk", 1699 "tx_lane0_sync_clk", 1700 "rx_lane0_sync_clk", 1701 "rx_lane1_sync_clk"; 1702 clocks = 1703 <&gcc GCC_UFS_PHY_AXI_CLK>, 1704 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1705 <&gcc GCC_UFS_PHY_AHB_CLK>, 1706 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1707 <&rpmhcc RPMH_CXO_CLK>, 1708 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1709 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1710 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1711 freq-table-hz = 1712 <75000000 300000000>, 1713 <0 0>, 1714 <0 0>, 1715 <75000000 300000000>, 1716 <0 0>, 1717 <0 0>, 1718 <0 0>, 1719 <0 0>; 1720 status = "disabled"; 1721 }; 1722 1723 ufs_mem_phy: phy@1d87000 { 1724 compatible = "qcom,sm8350-qmp-ufs-phy"; 1725 reg = <0 0x01d87000 0 0x1c4>; 1726 #address-cells = <2>; 1727 #size-cells = <2>; 1728 ranges; 1729 clock-names = "ref", 1730 "ref_aux"; 1731 clocks = <&rpmhcc RPMH_CXO_CLK>, 1732 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1733 1734 resets = <&ufs_mem_hc 0>; 1735 reset-names = "ufsphy"; 1736 status = "disabled"; 1737 1738 ufs_mem_phy_lanes: phy@1d87400 { 1739 reg = <0 0x01d87400 0 0x188>, 1740 <0 0x01d87600 0 0x200>, 1741 <0 0x01d87c00 0 0x200>, 1742 <0 0x01d87800 0 0x188>, 1743 <0 0x01d87a00 0 0x200>; 1744 #clock-cells = <1>; 1745 #phy-cells = <0>; 1746 }; 1747 }; 1748 1749 cryptobam: dma-controller@1dc4000 { 1750 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1751 reg = <0 0x01dc4000 0 0x24000>; 1752 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1753 #dma-cells = <1>; 1754 qcom,ee = <0>; 1755 qcom,controlled-remotely; 1756 iommus = <&apps_smmu 0x594 0x0011>, 1757 <&apps_smmu 0x596 0x0011>; 1758 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1759 status = "fail"; 1760 }; 1761 1762 crypto: crypto@1dfa000 { 1763 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1764 reg = <0 0x01dfa000 0 0x6000>; 1765 dmas = <&cryptobam 4>, <&cryptobam 5>; 1766 dma-names = "rx", "tx"; 1767 iommus = <&apps_smmu 0x594 0x0011>, 1768 <&apps_smmu 0x596 0x0011>; 1769 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1770 interconnect-names = "memory"; 1771 /* FIXME: dependency BAM DMA is disabled */ 1772 status = "disabled"; 1773 }; 1774 1775 ipa: ipa@1e40000 { 1776 compatible = "qcom,sm8350-ipa"; 1777 1778 iommus = <&apps_smmu 0x5c0 0x0>, 1779 <&apps_smmu 0x5c2 0x0>; 1780 reg = <0 0x01e40000 0 0x8000>, 1781 <0 0x01e50000 0 0x4b20>, 1782 <0 0x01e04000 0 0x23000>; 1783 reg-names = "ipa-reg", 1784 "ipa-shared", 1785 "gsi"; 1786 1787 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1788 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1789 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1790 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1791 interrupt-names = "ipa", 1792 "gsi", 1793 "ipa-clock-query", 1794 "ipa-setup-ready"; 1795 1796 clocks = <&rpmhcc RPMH_IPA_CLK>; 1797 clock-names = "core"; 1798 1799 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1800 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1801 interconnect-names = "memory", 1802 "config"; 1803 1804 qcom,qmp = <&aoss_qmp>; 1805 1806 qcom,smem-states = <&ipa_smp2p_out 0>, 1807 <&ipa_smp2p_out 1>; 1808 qcom,smem-state-names = "ipa-clock-enabled-valid", 1809 "ipa-clock-enabled"; 1810 1811 status = "disabled"; 1812 }; 1813 1814 tcsr_mutex: hwlock@1f40000 { 1815 compatible = "qcom,tcsr-mutex"; 1816 reg = <0x0 0x01f40000 0x0 0x40000>; 1817 #hwlock-cells = <1>; 1818 }; 1819 1820 lpass_tlmm: pinctrl@33c0000 { 1821 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1822 reg = <0 0x033c0000 0 0x20000>, 1823 <0 0x03550000 0 0x10000>; 1824 1825 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1826 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1827 clock-names = "core", "audio"; 1828 1829 gpio-controller; 1830 #gpio-cells = <2>; 1831 gpio-ranges = <&lpass_tlmm 0 0 15>; 1832 }; 1833 1834 gpu: gpu@3d00000 { 1835 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1836 1837 reg = <0 0x03d00000 0 0x40000>, 1838 <0 0x03d9e000 0 0x1000>, 1839 <0 0x03d61000 0 0x800>; 1840 reg-names = "kgsl_3d0_reg_memory", 1841 "cx_mem", 1842 "cx_dbgc"; 1843 1844 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1845 1846 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1847 1848 operating-points-v2 = <&gpu_opp_table>; 1849 1850 qcom,gmu = <&gmu>; 1851 1852 status = "disabled"; 1853 1854 zap-shader { 1855 memory-region = <&pil_gpu_mem>; 1856 }; 1857 1858 /* note: downstream checks gpu binning for 670 Mhz */ 1859 gpu_opp_table: opp-table { 1860 compatible = "operating-points-v2"; 1861 1862 opp-840000000 { 1863 opp-hz = /bits/ 64 <840000000>; 1864 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1865 }; 1866 1867 opp-778000000 { 1868 opp-hz = /bits/ 64 <778000000>; 1869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1870 }; 1871 1872 opp-738000000 { 1873 opp-hz = /bits/ 64 <738000000>; 1874 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1875 }; 1876 1877 opp-676000000 { 1878 opp-hz = /bits/ 64 <676000000>; 1879 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1880 }; 1881 1882 opp-608000000 { 1883 opp-hz = /bits/ 64 <608000000>; 1884 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1885 }; 1886 1887 opp-540000000 { 1888 opp-hz = /bits/ 64 <540000000>; 1889 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1890 }; 1891 1892 opp-491000000 { 1893 opp-hz = /bits/ 64 <491000000>; 1894 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1895 }; 1896 1897 opp-443000000 { 1898 opp-hz = /bits/ 64 <443000000>; 1899 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1900 }; 1901 1902 opp-379000000 { 1903 opp-hz = /bits/ 64 <379000000>; 1904 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1905 }; 1906 1907 opp-315000000 { 1908 opp-hz = /bits/ 64 <315000000>; 1909 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1910 }; 1911 }; 1912 }; 1913 1914 gmu: gmu@3d6a000 { 1915 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1916 1917 reg = <0 0x03d6a000 0 0x34000>, 1918 <0 0x03de0000 0 0x10000>, 1919 <0 0x0b290000 0 0x10000>; 1920 reg-names = "gmu", "rscc", "gmu_pdc"; 1921 1922 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1924 interrupt-names = "hfi", "gmu"; 1925 1926 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1927 <&gpucc GPU_CC_CXO_CLK>, 1928 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1929 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1930 <&gpucc GPU_CC_AHB_CLK>, 1931 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1932 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1933 clock-names = "gmu", 1934 "cxo", 1935 "axi", 1936 "memnoc", 1937 "ahb", 1938 "hub", 1939 "smmu_vote"; 1940 1941 power-domains = <&gpucc GPU_CX_GDSC>, 1942 <&gpucc GPU_GX_GDSC>; 1943 power-domain-names = "cx", 1944 "gx"; 1945 1946 iommus = <&adreno_smmu 5 0x400>; 1947 1948 operating-points-v2 = <&gmu_opp_table>; 1949 1950 gmu_opp_table: opp-table { 1951 compatible = "operating-points-v2"; 1952 1953 opp-200000000 { 1954 opp-hz = /bits/ 64 <200000000>; 1955 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1956 }; 1957 }; 1958 }; 1959 1960 gpucc: clock-controller@3d90000 { 1961 compatible = "qcom,sm8350-gpucc"; 1962 reg = <0 0x03d90000 0 0x9000>; 1963 clocks = <&rpmhcc RPMH_CXO_CLK>, 1964 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1965 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1966 clock-names = "bi_tcxo", 1967 "gcc_gpu_gpll0_clk_src", 1968 "gcc_gpu_gpll0_div_clk_src"; 1969 #clock-cells = <1>; 1970 #reset-cells = <1>; 1971 #power-domain-cells = <1>; 1972 }; 1973 1974 adreno_smmu: iommu@3da0000 { 1975 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1976 "qcom,smmu-500", "arm,mmu-500"; 1977 reg = <0 0x03da0000 0 0x20000>; 1978 #iommu-cells = <2>; 1979 #global-interrupts = <2>; 1980 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1992 1993 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1994 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1995 <&gpucc GPU_CC_AHB_CLK>, 1996 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1997 <&gpucc GPU_CC_CX_GMU_CLK>, 1998 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1999 <&gpucc GPU_CC_HUB_AON_CLK>; 2000 clock-names = "bus", 2001 "iface", 2002 "ahb", 2003 "hlos1_vote_gpu_smmu", 2004 "cx_gmu", 2005 "hub_cx_int", 2006 "hub_aon"; 2007 2008 power-domains = <&gpucc GPU_CX_GDSC>; 2009 dma-coherent; 2010 }; 2011 2012 lpass_ag_noc: interconnect@3c40000 { 2013 compatible = "qcom,sm8350-lpass-ag-noc"; 2014 reg = <0 0x03c40000 0 0xf080>; 2015 #interconnect-cells = <2>; 2016 qcom,bcm-voters = <&apps_bcm_voter>; 2017 }; 2018 2019 mpss: remoteproc@4080000 { 2020 compatible = "qcom,sm8350-mpss-pas"; 2021 reg = <0x0 0x04080000 0x0 0x4040>; 2022 2023 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2024 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2025 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2026 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2027 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2028 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2029 interrupt-names = "wdog", "fatal", "ready", "handover", 2030 "stop-ack", "shutdown-ack"; 2031 2032 clocks = <&rpmhcc RPMH_CXO_CLK>; 2033 clock-names = "xo"; 2034 2035 power-domains = <&rpmhpd RPMHPD_CX>, 2036 <&rpmhpd RPMHPD_MSS>; 2037 power-domain-names = "cx", "mss"; 2038 2039 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2040 2041 memory-region = <&pil_modem_mem>; 2042 2043 qcom,qmp = <&aoss_qmp>; 2044 2045 qcom,smem-states = <&smp2p_modem_out 0>; 2046 qcom,smem-state-names = "stop"; 2047 2048 status = "disabled"; 2049 2050 glink-edge { 2051 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2052 IPCC_MPROC_SIGNAL_GLINK_QMP 2053 IRQ_TYPE_EDGE_RISING>; 2054 mboxes = <&ipcc IPCC_CLIENT_MPSS 2055 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2056 label = "modem"; 2057 qcom,remote-pid = <1>; 2058 }; 2059 }; 2060 2061 slpi: remoteproc@5c00000 { 2062 compatible = "qcom,sm8350-slpi-pas"; 2063 reg = <0 0x05c00000 0 0x4000>; 2064 2065 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2066 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2067 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2068 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2069 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2070 interrupt-names = "wdog", "fatal", "ready", 2071 "handover", "stop-ack"; 2072 2073 clocks = <&rpmhcc RPMH_CXO_CLK>; 2074 clock-names = "xo"; 2075 2076 power-domains = <&rpmhpd RPMHPD_LCX>, 2077 <&rpmhpd RPMHPD_LMX>; 2078 power-domain-names = "lcx", "lmx"; 2079 2080 memory-region = <&pil_slpi_mem>; 2081 2082 qcom,qmp = <&aoss_qmp>; 2083 2084 qcom,smem-states = <&smp2p_slpi_out 0>; 2085 qcom,smem-state-names = "stop"; 2086 2087 status = "disabled"; 2088 2089 glink-edge { 2090 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2091 IPCC_MPROC_SIGNAL_GLINK_QMP 2092 IRQ_TYPE_EDGE_RISING>; 2093 mboxes = <&ipcc IPCC_CLIENT_SLPI 2094 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2095 2096 label = "slpi"; 2097 qcom,remote-pid = <3>; 2098 2099 fastrpc { 2100 compatible = "qcom,fastrpc"; 2101 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2102 label = "sdsp"; 2103 qcom,non-secure-domain; 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 compute-cb@1 { 2108 compatible = "qcom,fastrpc-compute-cb"; 2109 reg = <1>; 2110 iommus = <&apps_smmu 0x0541 0x0>; 2111 }; 2112 2113 compute-cb@2 { 2114 compatible = "qcom,fastrpc-compute-cb"; 2115 reg = <2>; 2116 iommus = <&apps_smmu 0x0542 0x0>; 2117 }; 2118 2119 compute-cb@3 { 2120 compatible = "qcom,fastrpc-compute-cb"; 2121 reg = <3>; 2122 iommus = <&apps_smmu 0x0543 0x0>; 2123 /* note: shared-cb = <4> in downstream */ 2124 }; 2125 }; 2126 }; 2127 }; 2128 2129 sdhc_2: mmc@8804000 { 2130 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2131 reg = <0 0x08804000 0 0x1000>; 2132 2133 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2135 interrupt-names = "hc_irq", "pwr_irq"; 2136 2137 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2138 <&gcc GCC_SDCC2_APPS_CLK>, 2139 <&rpmhcc RPMH_CXO_CLK>; 2140 clock-names = "iface", "core", "xo"; 2141 resets = <&gcc GCC_SDCC2_BCR>; 2142 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2143 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2144 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2145 iommus = <&apps_smmu 0x4a0 0x0>; 2146 power-domains = <&rpmhpd RPMHPD_CX>; 2147 operating-points-v2 = <&sdhc2_opp_table>; 2148 bus-width = <4>; 2149 dma-coherent; 2150 2151 status = "disabled"; 2152 2153 sdhc2_opp_table: opp-table { 2154 compatible = "operating-points-v2"; 2155 2156 opp-100000000 { 2157 opp-hz = /bits/ 64 <100000000>; 2158 required-opps = <&rpmhpd_opp_low_svs>; 2159 }; 2160 2161 opp-202000000 { 2162 opp-hz = /bits/ 64 <202000000>; 2163 required-opps = <&rpmhpd_opp_svs_l1>; 2164 }; 2165 }; 2166 }; 2167 2168 usb_1_hsphy: phy@88e3000 { 2169 compatible = "qcom,sm8350-usb-hs-phy", 2170 "qcom,usb-snps-hs-7nm-phy"; 2171 reg = <0 0x088e3000 0 0x400>; 2172 status = "disabled"; 2173 #phy-cells = <0>; 2174 2175 clocks = <&rpmhcc RPMH_CXO_CLK>; 2176 clock-names = "ref"; 2177 2178 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2179 }; 2180 2181 usb_2_hsphy: phy@88e4000 { 2182 compatible = "qcom,sm8250-usb-hs-phy", 2183 "qcom,usb-snps-hs-7nm-phy"; 2184 reg = <0 0x088e4000 0 0x400>; 2185 status = "disabled"; 2186 #phy-cells = <0>; 2187 2188 clocks = <&rpmhcc RPMH_CXO_CLK>; 2189 clock-names = "ref"; 2190 2191 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2192 }; 2193 2194 usb_1_qmpphy: phy@88e8000 { 2195 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2196 reg = <0 0x088e8000 0 0x3000>; 2197 2198 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2199 <&rpmhcc RPMH_CXO_CLK>, 2200 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2201 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2202 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2203 2204 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2205 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2206 reset-names = "phy", "common"; 2207 2208 #clock-cells = <1>; 2209 #phy-cells = <1>; 2210 2211 status = "disabled"; 2212 2213 ports { 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 2217 port@0 { 2218 reg = <0>; 2219 2220 usb_1_qmpphy_out: endpoint { 2221 }; 2222 }; 2223 2224 port@1 { 2225 reg = <1>; 2226 2227 usb_1_qmpphy_usb_ss_in: endpoint { 2228 }; 2229 }; 2230 2231 port@2 { 2232 reg = <2>; 2233 2234 usb_1_qmpphy_dp_in: endpoint { 2235 }; 2236 }; 2237 }; 2238 }; 2239 2240 usb_2_qmpphy: phy-wrapper@88eb000 { 2241 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2242 reg = <0 0x088eb000 0 0x200>; 2243 status = "disabled"; 2244 #address-cells = <2>; 2245 #size-cells = <2>; 2246 ranges; 2247 2248 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2249 <&rpmhcc RPMH_CXO_CLK>, 2250 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2251 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2252 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2253 2254 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2255 <&gcc GCC_USB3_PHY_SEC_BCR>; 2256 reset-names = "phy", "common"; 2257 2258 usb_2_ssphy: phy@88ebe00 { 2259 reg = <0 0x088ebe00 0 0x200>, 2260 <0 0x088ec000 0 0x200>, 2261 <0 0x088eb200 0 0x1100>; 2262 #phy-cells = <0>; 2263 #clock-cells = <0>; 2264 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2265 clock-names = "pipe0"; 2266 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2267 }; 2268 }; 2269 2270 dc_noc: interconnect@90c0000 { 2271 compatible = "qcom,sm8350-dc-noc"; 2272 reg = <0 0x090c0000 0 0x4200>; 2273 #interconnect-cells = <2>; 2274 qcom,bcm-voters = <&apps_bcm_voter>; 2275 }; 2276 2277 gem_noc: interconnect@9100000 { 2278 compatible = "qcom,sm8350-gem-noc"; 2279 reg = <0 0x09100000 0 0xb4000>; 2280 #interconnect-cells = <2>; 2281 qcom,bcm-voters = <&apps_bcm_voter>; 2282 }; 2283 2284 system-cache-controller@9200000 { 2285 compatible = "qcom,sm8350-llcc"; 2286 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2287 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2288 <0 0x09600000 0 0x58000>; 2289 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2290 "llcc3_base", "llcc_broadcast_base"; 2291 }; 2292 2293 compute_noc: interconnect@a0c0000 { 2294 compatible = "qcom,sm8350-compute-noc"; 2295 reg = <0 0x0a0c0000 0 0xa180>; 2296 #interconnect-cells = <2>; 2297 qcom,bcm-voters = <&apps_bcm_voter>; 2298 }; 2299 2300 usb_1: usb@a6f8800 { 2301 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2302 reg = <0 0x0a6f8800 0 0x400>; 2303 status = "disabled"; 2304 #address-cells = <2>; 2305 #size-cells = <2>; 2306 ranges; 2307 2308 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2309 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2310 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2311 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2312 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2313 clock-names = "cfg_noc", 2314 "core", 2315 "iface", 2316 "sleep", 2317 "mock_utmi"; 2318 2319 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2320 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2321 assigned-clock-rates = <19200000>, <200000000>; 2322 2323 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2324 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2325 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2326 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2327 interrupt-names = "hs_phy_irq", 2328 "ss_phy_irq", 2329 "dm_hs_phy_irq", 2330 "dp_hs_phy_irq"; 2331 2332 power-domains = <&gcc USB30_PRIM_GDSC>; 2333 2334 resets = <&gcc GCC_USB30_PRIM_BCR>; 2335 2336 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2338 interconnect-names = "usb-ddr", "apps-usb"; 2339 2340 usb_1_dwc3: usb@a600000 { 2341 compatible = "snps,dwc3"; 2342 reg = <0 0x0a600000 0 0xcd00>; 2343 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2344 iommus = <&apps_smmu 0x0 0x0>; 2345 snps,dis_u2_susphy_quirk; 2346 snps,dis_enblslpm_quirk; 2347 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2348 phy-names = "usb2-phy", "usb3-phy"; 2349 2350 ports { 2351 #address-cells = <1>; 2352 #size-cells = <0>; 2353 2354 port@0 { 2355 reg = <0>; 2356 2357 usb_1_dwc3_hs: endpoint { 2358 }; 2359 }; 2360 2361 port@1 { 2362 reg = <1>; 2363 2364 usb_1_dwc3_ss: endpoint { 2365 }; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 usb_2: usb@a8f8800 { 2372 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2373 reg = <0 0x0a8f8800 0 0x400>; 2374 status = "disabled"; 2375 #address-cells = <2>; 2376 #size-cells = <2>; 2377 ranges; 2378 2379 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2380 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2381 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2382 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2383 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2384 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2385 clock-names = "cfg_noc", 2386 "core", 2387 "iface", 2388 "sleep", 2389 "mock_utmi", 2390 "xo"; 2391 2392 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2393 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2394 assigned-clock-rates = <19200000>, <200000000>; 2395 2396 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2397 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2398 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2399 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2400 interrupt-names = "hs_phy_irq", 2401 "ss_phy_irq", 2402 "dm_hs_phy_irq", 2403 "dp_hs_phy_irq"; 2404 2405 power-domains = <&gcc USB30_SEC_GDSC>; 2406 2407 resets = <&gcc GCC_USB30_SEC_BCR>; 2408 2409 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2410 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2411 interconnect-names = "usb-ddr", "apps-usb"; 2412 2413 usb_2_dwc3: usb@a800000 { 2414 compatible = "snps,dwc3"; 2415 reg = <0 0x0a800000 0 0xcd00>; 2416 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2417 iommus = <&apps_smmu 0x20 0x0>; 2418 snps,dis_u2_susphy_quirk; 2419 snps,dis_enblslpm_quirk; 2420 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2421 phy-names = "usb2-phy", "usb3-phy"; 2422 }; 2423 }; 2424 2425 mdss: display-subsystem@ae00000 { 2426 compatible = "qcom,sm8350-mdss"; 2427 reg = <0 0x0ae00000 0 0x1000>; 2428 reg-names = "mdss"; 2429 2430 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2431 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2432 interconnect-names = "mdp0-mem", "mdp1-mem"; 2433 2434 power-domains = <&dispcc MDSS_GDSC>; 2435 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2436 2437 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2438 <&gcc GCC_DISP_HF_AXI_CLK>, 2439 <&gcc GCC_DISP_SF_AXI_CLK>, 2440 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2441 clock-names = "iface", "bus", "nrt_bus", "core"; 2442 2443 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2444 interrupt-controller; 2445 #interrupt-cells = <1>; 2446 2447 iommus = <&apps_smmu 0x820 0x402>; 2448 2449 status = "disabled"; 2450 2451 #address-cells = <2>; 2452 #size-cells = <2>; 2453 ranges; 2454 2455 dpu_opp_table: opp-table { 2456 compatible = "operating-points-v2"; 2457 2458 /* TODO: opp-200000000 should work with 2459 * &rpmhpd_opp_low_svs, but one some of 2460 * sm8350_hdk boards reboot using this 2461 * opp. 2462 */ 2463 opp-200000000 { 2464 opp-hz = /bits/ 64 <200000000>; 2465 required-opps = <&rpmhpd_opp_svs>; 2466 }; 2467 2468 opp-300000000 { 2469 opp-hz = /bits/ 64 <300000000>; 2470 required-opps = <&rpmhpd_opp_svs>; 2471 }; 2472 2473 opp-345000000 { 2474 opp-hz = /bits/ 64 <345000000>; 2475 required-opps = <&rpmhpd_opp_svs_l1>; 2476 }; 2477 2478 opp-460000000 { 2479 opp-hz = /bits/ 64 <460000000>; 2480 required-opps = <&rpmhpd_opp_nom>; 2481 }; 2482 }; 2483 2484 mdss_mdp: display-controller@ae01000 { 2485 compatible = "qcom,sm8350-dpu"; 2486 reg = <0 0x0ae01000 0 0x8f000>, 2487 <0 0x0aeb0000 0 0x2008>; 2488 reg-names = "mdp", "vbif"; 2489 2490 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2491 <&gcc GCC_DISP_SF_AXI_CLK>, 2492 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2493 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2494 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2495 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2496 clock-names = "bus", 2497 "nrt_bus", 2498 "iface", 2499 "lut", 2500 "core", 2501 "vsync"; 2502 2503 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2504 assigned-clock-rates = <19200000>; 2505 2506 operating-points-v2 = <&dpu_opp_table>; 2507 power-domains = <&rpmhpd RPMHPD_MMCX>; 2508 2509 interrupt-parent = <&mdss>; 2510 interrupts = <0>; 2511 2512 ports { 2513 #address-cells = <1>; 2514 #size-cells = <0>; 2515 2516 port@0 { 2517 reg = <0>; 2518 dpu_intf1_out: endpoint { 2519 remote-endpoint = <&mdss_dsi0_in>; 2520 }; 2521 }; 2522 2523 port@1 { 2524 reg = <1>; 2525 dpu_intf2_out: endpoint { 2526 remote-endpoint = <&mdss_dsi1_in>; 2527 }; 2528 }; 2529 2530 port@2 { 2531 reg = <2>; 2532 dpu_intf0_out: endpoint { 2533 remote-endpoint = <&mdss_dp_in>; 2534 }; 2535 }; 2536 }; 2537 }; 2538 2539 mdss_dp: displayport-controller@ae90000 { 2540 compatible = "qcom,sm8350-dp"; 2541 reg = <0 0xae90000 0 0x200>, 2542 <0 0xae90200 0 0x200>, 2543 <0 0xae90400 0 0x600>, 2544 <0 0xae91000 0 0x400>, 2545 <0 0xae91400 0 0x400>; 2546 interrupt-parent = <&mdss>; 2547 interrupts = <12>; 2548 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2549 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2550 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2551 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2552 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2553 clock-names = "core_iface", 2554 "core_aux", 2555 "ctrl_link", 2556 "ctrl_link_iface", 2557 "stream_pixel"; 2558 2559 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2560 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2561 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2562 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2563 2564 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2565 phy-names = "dp"; 2566 2567 #sound-dai-cells = <0>; 2568 2569 operating-points-v2 = <&dp_opp_table>; 2570 power-domains = <&rpmhpd RPMHPD_MMCX>; 2571 2572 status = "disabled"; 2573 2574 ports { 2575 #address-cells = <1>; 2576 #size-cells = <0>; 2577 2578 port@0 { 2579 reg = <0>; 2580 mdss_dp_in: endpoint { 2581 remote-endpoint = <&dpu_intf0_out>; 2582 }; 2583 }; 2584 }; 2585 2586 dp_opp_table: opp-table { 2587 compatible = "operating-points-v2"; 2588 2589 opp-160000000 { 2590 opp-hz = /bits/ 64 <160000000>; 2591 required-opps = <&rpmhpd_opp_low_svs>; 2592 }; 2593 2594 opp-270000000 { 2595 opp-hz = /bits/ 64 <270000000>; 2596 required-opps = <&rpmhpd_opp_svs>; 2597 }; 2598 2599 opp-540000000 { 2600 opp-hz = /bits/ 64 <540000000>; 2601 required-opps = <&rpmhpd_opp_svs_l1>; 2602 }; 2603 2604 opp-810000000 { 2605 opp-hz = /bits/ 64 <810000000>; 2606 required-opps = <&rpmhpd_opp_nom>; 2607 }; 2608 }; 2609 }; 2610 2611 mdss_dsi0: dsi@ae94000 { 2612 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2613 reg = <0 0x0ae94000 0 0x400>; 2614 reg-names = "dsi_ctrl"; 2615 2616 interrupt-parent = <&mdss>; 2617 interrupts = <4>; 2618 2619 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2620 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2621 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2622 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2623 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2624 <&gcc GCC_DISP_HF_AXI_CLK>; 2625 clock-names = "byte", 2626 "byte_intf", 2627 "pixel", 2628 "core", 2629 "iface", 2630 "bus"; 2631 2632 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2633 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2634 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2635 <&mdss_dsi0_phy 1>; 2636 2637 operating-points-v2 = <&dsi0_opp_table>; 2638 power-domains = <&rpmhpd RPMHPD_MMCX>; 2639 2640 phys = <&mdss_dsi0_phy>; 2641 2642 #address-cells = <1>; 2643 #size-cells = <0>; 2644 2645 status = "disabled"; 2646 2647 dsi0_opp_table: opp-table { 2648 compatible = "operating-points-v2"; 2649 2650 /* TODO: opp-187500000 should work with 2651 * &rpmhpd_opp_low_svs, but one some of 2652 * sm8350_hdk boards reboot using this 2653 * opp. 2654 */ 2655 opp-187500000 { 2656 opp-hz = /bits/ 64 <187500000>; 2657 required-opps = <&rpmhpd_opp_svs>; 2658 }; 2659 2660 opp-300000000 { 2661 opp-hz = /bits/ 64 <300000000>; 2662 required-opps = <&rpmhpd_opp_svs>; 2663 }; 2664 2665 opp-358000000 { 2666 opp-hz = /bits/ 64 <358000000>; 2667 required-opps = <&rpmhpd_opp_svs_l1>; 2668 }; 2669 }; 2670 2671 ports { 2672 #address-cells = <1>; 2673 #size-cells = <0>; 2674 2675 port@0 { 2676 reg = <0>; 2677 mdss_dsi0_in: endpoint { 2678 remote-endpoint = <&dpu_intf1_out>; 2679 }; 2680 }; 2681 2682 port@1 { 2683 reg = <1>; 2684 mdss_dsi0_out: endpoint { 2685 }; 2686 }; 2687 }; 2688 }; 2689 2690 mdss_dsi0_phy: phy@ae94400 { 2691 compatible = "qcom,sm8350-dsi-phy-5nm"; 2692 reg = <0 0x0ae94400 0 0x200>, 2693 <0 0x0ae94600 0 0x280>, 2694 <0 0x0ae94900 0 0x27c>; 2695 reg-names = "dsi_phy", 2696 "dsi_phy_lane", 2697 "dsi_pll"; 2698 2699 #clock-cells = <1>; 2700 #phy-cells = <0>; 2701 2702 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2703 <&rpmhcc RPMH_CXO_CLK>; 2704 clock-names = "iface", "ref"; 2705 2706 status = "disabled"; 2707 }; 2708 2709 mdss_dsi1: dsi@ae96000 { 2710 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2711 reg = <0 0x0ae96000 0 0x400>; 2712 reg-names = "dsi_ctrl"; 2713 2714 interrupt-parent = <&mdss>; 2715 interrupts = <5>; 2716 2717 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2718 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2719 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2720 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2721 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2722 <&gcc GCC_DISP_HF_AXI_CLK>; 2723 clock-names = "byte", 2724 "byte_intf", 2725 "pixel", 2726 "core", 2727 "iface", 2728 "bus"; 2729 2730 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2731 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2732 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2733 <&mdss_dsi1_phy 1>; 2734 2735 operating-points-v2 = <&dsi1_opp_table>; 2736 power-domains = <&rpmhpd RPMHPD_MMCX>; 2737 2738 phys = <&mdss_dsi1_phy>; 2739 2740 #address-cells = <1>; 2741 #size-cells = <0>; 2742 2743 status = "disabled"; 2744 2745 dsi1_opp_table: opp-table { 2746 compatible = "operating-points-v2"; 2747 2748 /* TODO: opp-187500000 should work with 2749 * &rpmhpd_opp_low_svs, but one some of 2750 * sm8350_hdk boards reboot using this 2751 * opp. 2752 */ 2753 opp-187500000 { 2754 opp-hz = /bits/ 64 <187500000>; 2755 required-opps = <&rpmhpd_opp_svs>; 2756 }; 2757 2758 opp-300000000 { 2759 opp-hz = /bits/ 64 <300000000>; 2760 required-opps = <&rpmhpd_opp_svs>; 2761 }; 2762 2763 opp-358000000 { 2764 opp-hz = /bits/ 64 <358000000>; 2765 required-opps = <&rpmhpd_opp_svs_l1>; 2766 }; 2767 }; 2768 2769 ports { 2770 #address-cells = <1>; 2771 #size-cells = <0>; 2772 2773 port@0 { 2774 reg = <0>; 2775 mdss_dsi1_in: endpoint { 2776 remote-endpoint = <&dpu_intf2_out>; 2777 }; 2778 }; 2779 2780 port@1 { 2781 reg = <1>; 2782 mdss_dsi1_out: endpoint { 2783 }; 2784 }; 2785 }; 2786 }; 2787 2788 mdss_dsi1_phy: phy@ae96400 { 2789 compatible = "qcom,sm8350-dsi-phy-5nm"; 2790 reg = <0 0x0ae96400 0 0x200>, 2791 <0 0x0ae96600 0 0x280>, 2792 <0 0x0ae96900 0 0x27c>; 2793 reg-names = "dsi_phy", 2794 "dsi_phy_lane", 2795 "dsi_pll"; 2796 2797 #clock-cells = <1>; 2798 #phy-cells = <0>; 2799 2800 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2801 <&rpmhcc RPMH_CXO_CLK>; 2802 clock-names = "iface", "ref"; 2803 2804 status = "disabled"; 2805 }; 2806 }; 2807 2808 dispcc: clock-controller@af00000 { 2809 compatible = "qcom,sm8350-dispcc"; 2810 reg = <0 0x0af00000 0 0x10000>; 2811 clocks = <&rpmhcc RPMH_CXO_CLK>, 2812 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2813 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2814 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2815 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2816 clock-names = "bi_tcxo", 2817 "dsi0_phy_pll_out_byteclk", 2818 "dsi0_phy_pll_out_dsiclk", 2819 "dsi1_phy_pll_out_byteclk", 2820 "dsi1_phy_pll_out_dsiclk", 2821 "dp_phy_pll_link_clk", 2822 "dp_phy_pll_vco_div_clk"; 2823 #clock-cells = <1>; 2824 #reset-cells = <1>; 2825 #power-domain-cells = <1>; 2826 2827 power-domains = <&rpmhpd RPMHPD_MMCX>; 2828 }; 2829 2830 pdc: interrupt-controller@b220000 { 2831 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2832 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2833 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2834 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2835 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2836 <156 716 12>; 2837 #interrupt-cells = <2>; 2838 interrupt-parent = <&intc>; 2839 interrupt-controller; 2840 }; 2841 2842 tsens0: thermal-sensor@c263000 { 2843 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2844 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2845 <0 0x0c222000 0 0x8>; /* SROT */ 2846 #qcom,sensors = <15>; 2847 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2848 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2849 interrupt-names = "uplow", "critical"; 2850 #thermal-sensor-cells = <1>; 2851 }; 2852 2853 tsens1: thermal-sensor@c265000 { 2854 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2855 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2856 <0 0x0c223000 0 0x8>; /* SROT */ 2857 #qcom,sensors = <14>; 2858 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2859 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2860 interrupt-names = "uplow", "critical"; 2861 #thermal-sensor-cells = <1>; 2862 }; 2863 2864 aoss_qmp: power-management@c300000 { 2865 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2866 reg = <0 0x0c300000 0 0x400>; 2867 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2868 IRQ_TYPE_EDGE_RISING>; 2869 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2870 2871 #clock-cells = <0>; 2872 }; 2873 2874 sram@c3f0000 { 2875 compatible = "qcom,rpmh-stats"; 2876 reg = <0 0x0c3f0000 0 0x400>; 2877 }; 2878 2879 spmi_bus: spmi@c440000 { 2880 compatible = "qcom,spmi-pmic-arb"; 2881 reg = <0x0 0x0c440000 0x0 0x1100>, 2882 <0x0 0x0c600000 0x0 0x2000000>, 2883 <0x0 0x0e600000 0x0 0x100000>, 2884 <0x0 0x0e700000 0x0 0xa0000>, 2885 <0x0 0x0c40a000 0x0 0x26000>; 2886 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2887 interrupt-names = "periph_irq"; 2888 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2889 qcom,ee = <0>; 2890 qcom,channel = <0>; 2891 #address-cells = <2>; 2892 #size-cells = <0>; 2893 interrupt-controller; 2894 #interrupt-cells = <4>; 2895 }; 2896 2897 tlmm: pinctrl@f100000 { 2898 compatible = "qcom,sm8350-tlmm"; 2899 reg = <0 0x0f100000 0 0x300000>; 2900 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2901 gpio-controller; 2902 #gpio-cells = <2>; 2903 interrupt-controller; 2904 #interrupt-cells = <2>; 2905 gpio-ranges = <&tlmm 0 0 204>; 2906 wakeup-parent = <&pdc>; 2907 2908 sdc2_default_state: sdc2-default-state { 2909 clk-pins { 2910 pins = "sdc2_clk"; 2911 drive-strength = <16>; 2912 bias-disable; 2913 }; 2914 2915 cmd-pins { 2916 pins = "sdc2_cmd"; 2917 drive-strength = <16>; 2918 bias-pull-up; 2919 }; 2920 2921 data-pins { 2922 pins = "sdc2_data"; 2923 drive-strength = <16>; 2924 bias-pull-up; 2925 }; 2926 }; 2927 2928 sdc2_sleep_state: sdc2-sleep-state { 2929 clk-pins { 2930 pins = "sdc2_clk"; 2931 drive-strength = <2>; 2932 bias-disable; 2933 }; 2934 2935 cmd-pins { 2936 pins = "sdc2_cmd"; 2937 drive-strength = <2>; 2938 bias-pull-up; 2939 }; 2940 2941 data-pins { 2942 pins = "sdc2_data"; 2943 drive-strength = <2>; 2944 bias-pull-up; 2945 }; 2946 }; 2947 2948 qup_uart3_default_state: qup-uart3-default-state { 2949 rx-pins { 2950 pins = "gpio18"; 2951 function = "qup3"; 2952 }; 2953 tx-pins { 2954 pins = "gpio19"; 2955 function = "qup3"; 2956 }; 2957 }; 2958 2959 qup_uart6_default: qup-uart6-default-state { 2960 pins = "gpio30", "gpio31"; 2961 function = "qup6"; 2962 drive-strength = <2>; 2963 bias-disable; 2964 }; 2965 2966 qup_uart18_default: qup-uart18-default-state { 2967 pins = "gpio68", "gpio69"; 2968 function = "qup18"; 2969 drive-strength = <2>; 2970 bias-disable; 2971 }; 2972 2973 qup_i2c0_default: qup-i2c0-default-state { 2974 pins = "gpio4", "gpio5"; 2975 function = "qup0"; 2976 drive-strength = <2>; 2977 bias-pull-up; 2978 }; 2979 2980 qup_i2c1_default: qup-i2c1-default-state { 2981 pins = "gpio8", "gpio9"; 2982 function = "qup1"; 2983 drive-strength = <2>; 2984 bias-pull-up; 2985 }; 2986 2987 qup_i2c2_default: qup-i2c2-default-state { 2988 pins = "gpio12", "gpio13"; 2989 function = "qup2"; 2990 drive-strength = <2>; 2991 bias-pull-up; 2992 }; 2993 2994 qup_i2c4_default: qup-i2c4-default-state { 2995 pins = "gpio20", "gpio21"; 2996 function = "qup4"; 2997 drive-strength = <2>; 2998 bias-pull-up; 2999 }; 3000 3001 qup_i2c5_default: qup-i2c5-default-state { 3002 pins = "gpio24", "gpio25"; 3003 function = "qup5"; 3004 drive-strength = <2>; 3005 bias-pull-up; 3006 }; 3007 3008 qup_i2c6_default: qup-i2c6-default-state { 3009 pins = "gpio28", "gpio29"; 3010 function = "qup6"; 3011 drive-strength = <2>; 3012 bias-pull-up; 3013 }; 3014 3015 qup_i2c7_default: qup-i2c7-default-state { 3016 pins = "gpio32", "gpio33"; 3017 function = "qup7"; 3018 drive-strength = <2>; 3019 bias-disable; 3020 }; 3021 3022 qup_i2c8_default: qup-i2c8-default-state { 3023 pins = "gpio36", "gpio37"; 3024 function = "qup8"; 3025 drive-strength = <2>; 3026 bias-pull-up; 3027 }; 3028 3029 qup_i2c9_default: qup-i2c9-default-state { 3030 pins = "gpio40", "gpio41"; 3031 function = "qup9"; 3032 drive-strength = <2>; 3033 bias-pull-up; 3034 }; 3035 3036 qup_i2c10_default: qup-i2c10-default-state { 3037 pins = "gpio44", "gpio45"; 3038 function = "qup10"; 3039 drive-strength = <2>; 3040 bias-pull-up; 3041 }; 3042 3043 qup_i2c11_default: qup-i2c11-default-state { 3044 pins = "gpio48", "gpio49"; 3045 function = "qup11"; 3046 drive-strength = <2>; 3047 bias-pull-up; 3048 }; 3049 3050 qup_i2c12_default: qup-i2c12-default-state { 3051 pins = "gpio52", "gpio53"; 3052 function = "qup12"; 3053 drive-strength = <2>; 3054 bias-pull-up; 3055 }; 3056 3057 qup_i2c13_default: qup-i2c13-default-state { 3058 pins = "gpio0", "gpio1"; 3059 function = "qup13"; 3060 drive-strength = <2>; 3061 bias-pull-up; 3062 }; 3063 3064 qup_i2c14_default: qup-i2c14-default-state { 3065 pins = "gpio56", "gpio57"; 3066 function = "qup14"; 3067 drive-strength = <2>; 3068 bias-disable; 3069 }; 3070 3071 qup_i2c15_default: qup-i2c15-default-state { 3072 pins = "gpio60", "gpio61"; 3073 function = "qup15"; 3074 drive-strength = <2>; 3075 bias-disable; 3076 }; 3077 3078 qup_i2c16_default: qup-i2c16-default-state { 3079 pins = "gpio64", "gpio65"; 3080 function = "qup16"; 3081 drive-strength = <2>; 3082 bias-disable; 3083 }; 3084 3085 qup_i2c17_default: qup-i2c17-default-state { 3086 pins = "gpio72", "gpio73"; 3087 function = "qup17"; 3088 drive-strength = <2>; 3089 bias-disable; 3090 }; 3091 3092 qup_i2c19_default: qup-i2c19-default-state { 3093 pins = "gpio76", "gpio77"; 3094 function = "qup19"; 3095 drive-strength = <2>; 3096 bias-disable; 3097 }; 3098 }; 3099 3100 apps_smmu: iommu@15000000 { 3101 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3102 reg = <0 0x15000000 0 0x100000>; 3103 #iommu-cells = <2>; 3104 #global-interrupts = <2>; 3105 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3203 }; 3204 3205 adsp: remoteproc@17300000 { 3206 compatible = "qcom,sm8350-adsp-pas"; 3207 reg = <0 0x17300000 0 0x100>; 3208 3209 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3210 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3211 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3212 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3213 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3214 interrupt-names = "wdog", "fatal", "ready", 3215 "handover", "stop-ack"; 3216 3217 clocks = <&rpmhcc RPMH_CXO_CLK>; 3218 clock-names = "xo"; 3219 3220 power-domains = <&rpmhpd RPMHPD_LCX>, 3221 <&rpmhpd RPMHPD_LMX>; 3222 power-domain-names = "lcx", "lmx"; 3223 3224 memory-region = <&pil_adsp_mem>; 3225 3226 qcom,qmp = <&aoss_qmp>; 3227 3228 qcom,smem-states = <&smp2p_adsp_out 0>; 3229 qcom,smem-state-names = "stop"; 3230 3231 status = "disabled"; 3232 3233 glink-edge { 3234 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3235 IPCC_MPROC_SIGNAL_GLINK_QMP 3236 IRQ_TYPE_EDGE_RISING>; 3237 mboxes = <&ipcc IPCC_CLIENT_LPASS 3238 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3239 3240 label = "lpass"; 3241 qcom,remote-pid = <2>; 3242 3243 apr { 3244 compatible = "qcom,apr-v2"; 3245 qcom,glink-channels = "apr_audio_svc"; 3246 qcom,domain = <APR_DOMAIN_ADSP>; 3247 #address-cells = <1>; 3248 #size-cells = <0>; 3249 3250 service@3 { 3251 reg = <APR_SVC_ADSP_CORE>; 3252 compatible = "qcom,q6core"; 3253 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3254 }; 3255 3256 q6afe: service@4 { 3257 compatible = "qcom,q6afe"; 3258 reg = <APR_SVC_AFE>; 3259 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3260 3261 q6afedai: dais { 3262 compatible = "qcom,q6afe-dais"; 3263 #address-cells = <1>; 3264 #size-cells = <0>; 3265 #sound-dai-cells = <1>; 3266 }; 3267 3268 q6afecc: clock-controller { 3269 compatible = "qcom,q6afe-clocks"; 3270 #clock-cells = <2>; 3271 }; 3272 }; 3273 3274 q6asm: service@7 { 3275 compatible = "qcom,q6asm"; 3276 reg = <APR_SVC_ASM>; 3277 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3278 3279 q6asmdai: dais { 3280 compatible = "qcom,q6asm-dais"; 3281 #address-cells = <1>; 3282 #size-cells = <0>; 3283 #sound-dai-cells = <1>; 3284 iommus = <&apps_smmu 0x1801 0x0>; 3285 3286 dai@0 { 3287 reg = <0>; 3288 }; 3289 3290 dai@1 { 3291 reg = <1>; 3292 }; 3293 3294 dai@2 { 3295 reg = <2>; 3296 }; 3297 }; 3298 }; 3299 3300 q6adm: service@8 { 3301 compatible = "qcom,q6adm"; 3302 reg = <APR_SVC_ADM>; 3303 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3304 3305 q6routing: routing { 3306 compatible = "qcom,q6adm-routing"; 3307 #sound-dai-cells = <0>; 3308 }; 3309 }; 3310 }; 3311 3312 fastrpc { 3313 compatible = "qcom,fastrpc"; 3314 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3315 label = "adsp"; 3316 qcom,non-secure-domain; 3317 #address-cells = <1>; 3318 #size-cells = <0>; 3319 3320 compute-cb@3 { 3321 compatible = "qcom,fastrpc-compute-cb"; 3322 reg = <3>; 3323 iommus = <&apps_smmu 0x1803 0x0>; 3324 }; 3325 3326 compute-cb@4 { 3327 compatible = "qcom,fastrpc-compute-cb"; 3328 reg = <4>; 3329 iommus = <&apps_smmu 0x1804 0x0>; 3330 }; 3331 3332 compute-cb@5 { 3333 compatible = "qcom,fastrpc-compute-cb"; 3334 reg = <5>; 3335 iommus = <&apps_smmu 0x1805 0x0>; 3336 }; 3337 }; 3338 }; 3339 }; 3340 3341 intc: interrupt-controller@17a00000 { 3342 compatible = "arm,gic-v3"; 3343 #interrupt-cells = <3>; 3344 interrupt-controller; 3345 #redistributor-regions = <1>; 3346 redistributor-stride = <0 0x20000>; 3347 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3348 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3350 }; 3351 3352 timer@17c20000 { 3353 compatible = "arm,armv7-timer-mem"; 3354 #address-cells = <1>; 3355 #size-cells = <1>; 3356 ranges = <0 0 0 0x20000000>; 3357 reg = <0x0 0x17c20000 0x0 0x1000>; 3358 clock-frequency = <19200000>; 3359 3360 frame@17c21000 { 3361 frame-number = <0>; 3362 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3364 reg = <0x17c21000 0x1000>, 3365 <0x17c22000 0x1000>; 3366 }; 3367 3368 frame@17c23000 { 3369 frame-number = <1>; 3370 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3371 reg = <0x17c23000 0x1000>; 3372 status = "disabled"; 3373 }; 3374 3375 frame@17c25000 { 3376 frame-number = <2>; 3377 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3378 reg = <0x17c25000 0x1000>; 3379 status = "disabled"; 3380 }; 3381 3382 frame@17c27000 { 3383 frame-number = <3>; 3384 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3385 reg = <0x17c27000 0x1000>; 3386 status = "disabled"; 3387 }; 3388 3389 frame@17c29000 { 3390 frame-number = <4>; 3391 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3392 reg = <0x17c29000 0x1000>; 3393 status = "disabled"; 3394 }; 3395 3396 frame@17c2b000 { 3397 frame-number = <5>; 3398 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3399 reg = <0x17c2b000 0x1000>; 3400 status = "disabled"; 3401 }; 3402 3403 frame@17c2d000 { 3404 frame-number = <6>; 3405 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3406 reg = <0x17c2d000 0x1000>; 3407 status = "disabled"; 3408 }; 3409 }; 3410 3411 apps_rsc: rsc@18200000 { 3412 label = "apps_rsc"; 3413 compatible = "qcom,rpmh-rsc"; 3414 reg = <0x0 0x18200000 0x0 0x10000>, 3415 <0x0 0x18210000 0x0 0x10000>, 3416 <0x0 0x18220000 0x0 0x10000>; 3417 reg-names = "drv-0", "drv-1", "drv-2"; 3418 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3421 qcom,tcs-offset = <0xd00>; 3422 qcom,drv-id = <2>; 3423 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3424 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3425 power-domains = <&CLUSTER_PD>; 3426 3427 rpmhcc: clock-controller { 3428 compatible = "qcom,sm8350-rpmh-clk"; 3429 #clock-cells = <1>; 3430 clock-names = "xo"; 3431 clocks = <&xo_board>; 3432 }; 3433 3434 rpmhpd: power-controller { 3435 compatible = "qcom,sm8350-rpmhpd"; 3436 #power-domain-cells = <1>; 3437 operating-points-v2 = <&rpmhpd_opp_table>; 3438 3439 rpmhpd_opp_table: opp-table { 3440 compatible = "operating-points-v2"; 3441 3442 rpmhpd_opp_ret: opp1 { 3443 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3444 }; 3445 3446 rpmhpd_opp_min_svs: opp2 { 3447 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3448 }; 3449 3450 rpmhpd_opp_low_svs: opp3 { 3451 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3452 }; 3453 3454 rpmhpd_opp_svs: opp4 { 3455 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3456 }; 3457 3458 rpmhpd_opp_svs_l1: opp5 { 3459 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3460 }; 3461 3462 rpmhpd_opp_nom: opp6 { 3463 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3464 }; 3465 3466 rpmhpd_opp_nom_l1: opp7 { 3467 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3468 }; 3469 3470 rpmhpd_opp_nom_l2: opp8 { 3471 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3472 }; 3473 3474 rpmhpd_opp_turbo: opp9 { 3475 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3476 }; 3477 3478 rpmhpd_opp_turbo_l1: opp10 { 3479 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3480 }; 3481 }; 3482 }; 3483 3484 apps_bcm_voter: bcm-voter { 3485 compatible = "qcom,bcm-voter"; 3486 }; 3487 }; 3488 3489 cpufreq_hw: cpufreq@18591000 { 3490 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3491 reg = <0 0x18591000 0 0x1000>, 3492 <0 0x18592000 0 0x1000>, 3493 <0 0x18593000 0 0x1000>; 3494 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3495 3496 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3499 interrupt-names = "dcvsh-irq-0", 3500 "dcvsh-irq-1", 3501 "dcvsh-irq-2"; 3502 3503 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3504 clock-names = "xo", "alternate"; 3505 3506 #freq-domain-cells = <1>; 3507 #clock-cells = <1>; 3508 }; 3509 3510 cdsp: remoteproc@98900000 { 3511 compatible = "qcom,sm8350-cdsp-pas"; 3512 reg = <0 0x98900000 0 0x1400000>; 3513 3514 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3515 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3516 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3517 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3518 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3519 interrupt-names = "wdog", "fatal", "ready", 3520 "handover", "stop-ack"; 3521 3522 clocks = <&rpmhcc RPMH_CXO_CLK>; 3523 clock-names = "xo"; 3524 3525 power-domains = <&rpmhpd RPMHPD_CX>, 3526 <&rpmhpd RPMHPD_MXC>; 3527 power-domain-names = "cx", "mxc"; 3528 3529 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3530 3531 memory-region = <&pil_cdsp_mem>; 3532 3533 qcom,qmp = <&aoss_qmp>; 3534 3535 qcom,smem-states = <&smp2p_cdsp_out 0>; 3536 qcom,smem-state-names = "stop"; 3537 3538 status = "disabled"; 3539 3540 glink-edge { 3541 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3542 IPCC_MPROC_SIGNAL_GLINK_QMP 3543 IRQ_TYPE_EDGE_RISING>; 3544 mboxes = <&ipcc IPCC_CLIENT_CDSP 3545 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3546 3547 label = "cdsp"; 3548 qcom,remote-pid = <5>; 3549 3550 fastrpc { 3551 compatible = "qcom,fastrpc"; 3552 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3553 label = "cdsp"; 3554 qcom,non-secure-domain; 3555 #address-cells = <1>; 3556 #size-cells = <0>; 3557 3558 compute-cb@1 { 3559 compatible = "qcom,fastrpc-compute-cb"; 3560 reg = <1>; 3561 iommus = <&apps_smmu 0x2161 0x0400>, 3562 <&apps_smmu 0x1181 0x0420>; 3563 }; 3564 3565 compute-cb@2 { 3566 compatible = "qcom,fastrpc-compute-cb"; 3567 reg = <2>; 3568 iommus = <&apps_smmu 0x2162 0x0400>, 3569 <&apps_smmu 0x1182 0x0420>; 3570 }; 3571 3572 compute-cb@3 { 3573 compatible = "qcom,fastrpc-compute-cb"; 3574 reg = <3>; 3575 iommus = <&apps_smmu 0x2163 0x0400>, 3576 <&apps_smmu 0x1183 0x0420>; 3577 }; 3578 3579 compute-cb@4 { 3580 compatible = "qcom,fastrpc-compute-cb"; 3581 reg = <4>; 3582 iommus = <&apps_smmu 0x2164 0x0400>, 3583 <&apps_smmu 0x1184 0x0420>; 3584 }; 3585 3586 compute-cb@5 { 3587 compatible = "qcom,fastrpc-compute-cb"; 3588 reg = <5>; 3589 iommus = <&apps_smmu 0x2165 0x0400>, 3590 <&apps_smmu 0x1185 0x0420>; 3591 }; 3592 3593 compute-cb@6 { 3594 compatible = "qcom,fastrpc-compute-cb"; 3595 reg = <6>; 3596 iommus = <&apps_smmu 0x2166 0x0400>, 3597 <&apps_smmu 0x1186 0x0420>; 3598 }; 3599 3600 compute-cb@7 { 3601 compatible = "qcom,fastrpc-compute-cb"; 3602 reg = <7>; 3603 iommus = <&apps_smmu 0x2167 0x0400>, 3604 <&apps_smmu 0x1187 0x0420>; 3605 }; 3606 3607 compute-cb@8 { 3608 compatible = "qcom,fastrpc-compute-cb"; 3609 reg = <8>; 3610 iommus = <&apps_smmu 0x2168 0x0400>, 3611 <&apps_smmu 0x1188 0x0420>; 3612 }; 3613 3614 /* note: secure cb9 in downstream */ 3615 }; 3616 }; 3617 }; 3618 }; 3619 3620 thermal_zones: thermal-zones { 3621 cpu0-thermal { 3622 polling-delay-passive = <250>; 3623 polling-delay = <1000>; 3624 3625 thermal-sensors = <&tsens0 1>; 3626 3627 trips { 3628 cpu0_alert0: trip-point0 { 3629 temperature = <90000>; 3630 hysteresis = <2000>; 3631 type = "passive"; 3632 }; 3633 3634 cpu0_alert1: trip-point1 { 3635 temperature = <95000>; 3636 hysteresis = <2000>; 3637 type = "passive"; 3638 }; 3639 3640 cpu0_crit: cpu-crit { 3641 temperature = <110000>; 3642 hysteresis = <1000>; 3643 type = "critical"; 3644 }; 3645 }; 3646 3647 cooling-maps { 3648 map0 { 3649 trip = <&cpu0_alert0>; 3650 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3651 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3652 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3653 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3654 }; 3655 map1 { 3656 trip = <&cpu0_alert1>; 3657 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3658 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3659 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3660 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3661 }; 3662 }; 3663 }; 3664 3665 cpu1-thermal { 3666 polling-delay-passive = <250>; 3667 polling-delay = <1000>; 3668 3669 thermal-sensors = <&tsens0 2>; 3670 3671 trips { 3672 cpu1_alert0: trip-point0 { 3673 temperature = <90000>; 3674 hysteresis = <2000>; 3675 type = "passive"; 3676 }; 3677 3678 cpu1_alert1: trip-point1 { 3679 temperature = <95000>; 3680 hysteresis = <2000>; 3681 type = "passive"; 3682 }; 3683 3684 cpu1_crit: cpu-crit { 3685 temperature = <110000>; 3686 hysteresis = <1000>; 3687 type = "critical"; 3688 }; 3689 }; 3690 3691 cooling-maps { 3692 map0 { 3693 trip = <&cpu1_alert0>; 3694 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3695 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3698 }; 3699 map1 { 3700 trip = <&cpu1_alert1>; 3701 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3702 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3703 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3705 }; 3706 }; 3707 }; 3708 3709 cpu2-thermal { 3710 polling-delay-passive = <250>; 3711 polling-delay = <1000>; 3712 3713 thermal-sensors = <&tsens0 3>; 3714 3715 trips { 3716 cpu2_alert0: trip-point0 { 3717 temperature = <90000>; 3718 hysteresis = <2000>; 3719 type = "passive"; 3720 }; 3721 3722 cpu2_alert1: trip-point1 { 3723 temperature = <95000>; 3724 hysteresis = <2000>; 3725 type = "passive"; 3726 }; 3727 3728 cpu2_crit: cpu-crit { 3729 temperature = <110000>; 3730 hysteresis = <1000>; 3731 type = "critical"; 3732 }; 3733 }; 3734 3735 cooling-maps { 3736 map0 { 3737 trip = <&cpu2_alert0>; 3738 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3742 }; 3743 map1 { 3744 trip = <&cpu2_alert1>; 3745 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3749 }; 3750 }; 3751 }; 3752 3753 cpu3-thermal { 3754 polling-delay-passive = <250>; 3755 polling-delay = <1000>; 3756 3757 thermal-sensors = <&tsens0 4>; 3758 3759 trips { 3760 cpu3_alert0: trip-point0 { 3761 temperature = <90000>; 3762 hysteresis = <2000>; 3763 type = "passive"; 3764 }; 3765 3766 cpu3_alert1: trip-point1 { 3767 temperature = <95000>; 3768 hysteresis = <2000>; 3769 type = "passive"; 3770 }; 3771 3772 cpu3_crit: cpu-crit { 3773 temperature = <110000>; 3774 hysteresis = <1000>; 3775 type = "critical"; 3776 }; 3777 }; 3778 3779 cooling-maps { 3780 map0 { 3781 trip = <&cpu3_alert0>; 3782 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3786 }; 3787 map1 { 3788 trip = <&cpu3_alert1>; 3789 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3790 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3793 }; 3794 }; 3795 }; 3796 3797 cpu4-top-thermal { 3798 polling-delay-passive = <250>; 3799 polling-delay = <1000>; 3800 3801 thermal-sensors = <&tsens0 7>; 3802 3803 trips { 3804 cpu4_top_alert0: trip-point0 { 3805 temperature = <90000>; 3806 hysteresis = <2000>; 3807 type = "passive"; 3808 }; 3809 3810 cpu4_top_alert1: trip-point1 { 3811 temperature = <95000>; 3812 hysteresis = <2000>; 3813 type = "passive"; 3814 }; 3815 3816 cpu4_top_crit: cpu-crit { 3817 temperature = <110000>; 3818 hysteresis = <1000>; 3819 type = "critical"; 3820 }; 3821 }; 3822 3823 cooling-maps { 3824 map0 { 3825 trip = <&cpu4_top_alert0>; 3826 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3830 }; 3831 map1 { 3832 trip = <&cpu4_top_alert1>; 3833 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3837 }; 3838 }; 3839 }; 3840 3841 cpu5-top-thermal { 3842 polling-delay-passive = <250>; 3843 polling-delay = <1000>; 3844 3845 thermal-sensors = <&tsens0 8>; 3846 3847 trips { 3848 cpu5_top_alert0: trip-point0 { 3849 temperature = <90000>; 3850 hysteresis = <2000>; 3851 type = "passive"; 3852 }; 3853 3854 cpu5_top_alert1: trip-point1 { 3855 temperature = <95000>; 3856 hysteresis = <2000>; 3857 type = "passive"; 3858 }; 3859 3860 cpu5_top_crit: cpu-crit { 3861 temperature = <110000>; 3862 hysteresis = <1000>; 3863 type = "critical"; 3864 }; 3865 }; 3866 3867 cooling-maps { 3868 map0 { 3869 trip = <&cpu5_top_alert0>; 3870 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3874 }; 3875 map1 { 3876 trip = <&cpu5_top_alert1>; 3877 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3881 }; 3882 }; 3883 }; 3884 3885 cpu6-top-thermal { 3886 polling-delay-passive = <250>; 3887 polling-delay = <1000>; 3888 3889 thermal-sensors = <&tsens0 9>; 3890 3891 trips { 3892 cpu6_top_alert0: trip-point0 { 3893 temperature = <90000>; 3894 hysteresis = <2000>; 3895 type = "passive"; 3896 }; 3897 3898 cpu6_top_alert1: trip-point1 { 3899 temperature = <95000>; 3900 hysteresis = <2000>; 3901 type = "passive"; 3902 }; 3903 3904 cpu6_top_crit: cpu-crit { 3905 temperature = <110000>; 3906 hysteresis = <1000>; 3907 type = "critical"; 3908 }; 3909 }; 3910 3911 cooling-maps { 3912 map0 { 3913 trip = <&cpu6_top_alert0>; 3914 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3915 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3918 }; 3919 map1 { 3920 trip = <&cpu6_top_alert1>; 3921 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3925 }; 3926 }; 3927 }; 3928 3929 cpu7-top-thermal { 3930 polling-delay-passive = <250>; 3931 polling-delay = <1000>; 3932 3933 thermal-sensors = <&tsens0 10>; 3934 3935 trips { 3936 cpu7_top_alert0: trip-point0 { 3937 temperature = <90000>; 3938 hysteresis = <2000>; 3939 type = "passive"; 3940 }; 3941 3942 cpu7_top_alert1: trip-point1 { 3943 temperature = <95000>; 3944 hysteresis = <2000>; 3945 type = "passive"; 3946 }; 3947 3948 cpu7_top_crit: cpu-crit { 3949 temperature = <110000>; 3950 hysteresis = <1000>; 3951 type = "critical"; 3952 }; 3953 }; 3954 3955 cooling-maps { 3956 map0 { 3957 trip = <&cpu7_top_alert0>; 3958 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3959 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3962 }; 3963 map1 { 3964 trip = <&cpu7_top_alert1>; 3965 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3966 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3967 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3969 }; 3970 }; 3971 }; 3972 3973 cpu4-bottom-thermal { 3974 polling-delay-passive = <250>; 3975 polling-delay = <1000>; 3976 3977 thermal-sensors = <&tsens0 11>; 3978 3979 trips { 3980 cpu4_bottom_alert0: trip-point0 { 3981 temperature = <90000>; 3982 hysteresis = <2000>; 3983 type = "passive"; 3984 }; 3985 3986 cpu4_bottom_alert1: trip-point1 { 3987 temperature = <95000>; 3988 hysteresis = <2000>; 3989 type = "passive"; 3990 }; 3991 3992 cpu4_bottom_crit: cpu-crit { 3993 temperature = <110000>; 3994 hysteresis = <1000>; 3995 type = "critical"; 3996 }; 3997 }; 3998 3999 cooling-maps { 4000 map0 { 4001 trip = <&cpu4_bottom_alert0>; 4002 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4003 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4004 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4005 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4006 }; 4007 map1 { 4008 trip = <&cpu4_bottom_alert1>; 4009 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4010 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4011 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4012 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4013 }; 4014 }; 4015 }; 4016 4017 cpu5-bottom-thermal { 4018 polling-delay-passive = <250>; 4019 polling-delay = <1000>; 4020 4021 thermal-sensors = <&tsens0 12>; 4022 4023 trips { 4024 cpu5_bottom_alert0: trip-point0 { 4025 temperature = <90000>; 4026 hysteresis = <2000>; 4027 type = "passive"; 4028 }; 4029 4030 cpu5_bottom_alert1: trip-point1 { 4031 temperature = <95000>; 4032 hysteresis = <2000>; 4033 type = "passive"; 4034 }; 4035 4036 cpu5_bottom_crit: cpu-crit { 4037 temperature = <110000>; 4038 hysteresis = <1000>; 4039 type = "critical"; 4040 }; 4041 }; 4042 4043 cooling-maps { 4044 map0 { 4045 trip = <&cpu5_bottom_alert0>; 4046 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4047 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4048 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4049 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4050 }; 4051 map1 { 4052 trip = <&cpu5_bottom_alert1>; 4053 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4054 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4055 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4057 }; 4058 }; 4059 }; 4060 4061 cpu6-bottom-thermal { 4062 polling-delay-passive = <250>; 4063 polling-delay = <1000>; 4064 4065 thermal-sensors = <&tsens0 13>; 4066 4067 trips { 4068 cpu6_bottom_alert0: trip-point0 { 4069 temperature = <90000>; 4070 hysteresis = <2000>; 4071 type = "passive"; 4072 }; 4073 4074 cpu6_bottom_alert1: trip-point1 { 4075 temperature = <95000>; 4076 hysteresis = <2000>; 4077 type = "passive"; 4078 }; 4079 4080 cpu6_bottom_crit: cpu-crit { 4081 temperature = <110000>; 4082 hysteresis = <1000>; 4083 type = "critical"; 4084 }; 4085 }; 4086 4087 cooling-maps { 4088 map0 { 4089 trip = <&cpu6_bottom_alert0>; 4090 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4091 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4092 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4093 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4094 }; 4095 map1 { 4096 trip = <&cpu6_bottom_alert1>; 4097 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4098 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4099 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4100 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4101 }; 4102 }; 4103 }; 4104 4105 cpu7-bottom-thermal { 4106 polling-delay-passive = <250>; 4107 polling-delay = <1000>; 4108 4109 thermal-sensors = <&tsens0 14>; 4110 4111 trips { 4112 cpu7_bottom_alert0: trip-point0 { 4113 temperature = <90000>; 4114 hysteresis = <2000>; 4115 type = "passive"; 4116 }; 4117 4118 cpu7_bottom_alert1: trip-point1 { 4119 temperature = <95000>; 4120 hysteresis = <2000>; 4121 type = "passive"; 4122 }; 4123 4124 cpu7_bottom_crit: cpu-crit { 4125 temperature = <110000>; 4126 hysteresis = <1000>; 4127 type = "critical"; 4128 }; 4129 }; 4130 4131 cooling-maps { 4132 map0 { 4133 trip = <&cpu7_bottom_alert0>; 4134 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4136 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4138 }; 4139 map1 { 4140 trip = <&cpu7_bottom_alert1>; 4141 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4142 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4143 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4145 }; 4146 }; 4147 }; 4148 4149 aoss0-thermal { 4150 polling-delay-passive = <250>; 4151 polling-delay = <1000>; 4152 4153 thermal-sensors = <&tsens0 0>; 4154 4155 trips { 4156 aoss0_alert0: trip-point0 { 4157 temperature = <90000>; 4158 hysteresis = <2000>; 4159 type = "hot"; 4160 }; 4161 }; 4162 }; 4163 4164 cluster0-thermal { 4165 polling-delay-passive = <250>; 4166 polling-delay = <1000>; 4167 4168 thermal-sensors = <&tsens0 5>; 4169 4170 trips { 4171 cluster0_alert0: trip-point0 { 4172 temperature = <90000>; 4173 hysteresis = <2000>; 4174 type = "hot"; 4175 }; 4176 cluster0_crit: cluster0_crit { 4177 temperature = <110000>; 4178 hysteresis = <2000>; 4179 type = "critical"; 4180 }; 4181 }; 4182 }; 4183 4184 cluster1-thermal { 4185 polling-delay-passive = <250>; 4186 polling-delay = <1000>; 4187 4188 thermal-sensors = <&tsens0 6>; 4189 4190 trips { 4191 cluster1_alert0: trip-point0 { 4192 temperature = <90000>; 4193 hysteresis = <2000>; 4194 type = "hot"; 4195 }; 4196 cluster1_crit: cluster1_crit { 4197 temperature = <110000>; 4198 hysteresis = <2000>; 4199 type = "critical"; 4200 }; 4201 }; 4202 }; 4203 4204 aoss1-thermal { 4205 polling-delay-passive = <250>; 4206 polling-delay = <1000>; 4207 4208 thermal-sensors = <&tsens1 0>; 4209 4210 trips { 4211 aoss1_alert0: trip-point0 { 4212 temperature = <90000>; 4213 hysteresis = <2000>; 4214 type = "hot"; 4215 }; 4216 }; 4217 }; 4218 4219 gpu-top-thermal { 4220 polling-delay-passive = <250>; 4221 polling-delay = <1000>; 4222 4223 thermal-sensors = <&tsens1 1>; 4224 4225 trips { 4226 gpu1_alert0: trip-point0 { 4227 temperature = <90000>; 4228 hysteresis = <1000>; 4229 type = "hot"; 4230 }; 4231 }; 4232 }; 4233 4234 gpu-bottom-thermal { 4235 polling-delay-passive = <250>; 4236 polling-delay = <1000>; 4237 4238 thermal-sensors = <&tsens1 2>; 4239 4240 trips { 4241 gpu2_alert0: trip-point0 { 4242 temperature = <90000>; 4243 hysteresis = <1000>; 4244 type = "hot"; 4245 }; 4246 }; 4247 }; 4248 4249 nspss1-thermal { 4250 polling-delay-passive = <250>; 4251 polling-delay = <1000>; 4252 4253 thermal-sensors = <&tsens1 3>; 4254 4255 trips { 4256 nspss1_alert0: trip-point0 { 4257 temperature = <90000>; 4258 hysteresis = <1000>; 4259 type = "hot"; 4260 }; 4261 }; 4262 }; 4263 4264 nspss2-thermal { 4265 polling-delay-passive = <250>; 4266 polling-delay = <1000>; 4267 4268 thermal-sensors = <&tsens1 4>; 4269 4270 trips { 4271 nspss2_alert0: trip-point0 { 4272 temperature = <90000>; 4273 hysteresis = <1000>; 4274 type = "hot"; 4275 }; 4276 }; 4277 }; 4278 4279 nspss3-thermal { 4280 polling-delay-passive = <250>; 4281 polling-delay = <1000>; 4282 4283 thermal-sensors = <&tsens1 5>; 4284 4285 trips { 4286 nspss3_alert0: trip-point0 { 4287 temperature = <90000>; 4288 hysteresis = <1000>; 4289 type = "hot"; 4290 }; 4291 }; 4292 }; 4293 4294 video-thermal { 4295 polling-delay-passive = <250>; 4296 polling-delay = <1000>; 4297 4298 thermal-sensors = <&tsens1 6>; 4299 4300 trips { 4301 video_alert0: trip-point0 { 4302 temperature = <90000>; 4303 hysteresis = <2000>; 4304 type = "hot"; 4305 }; 4306 }; 4307 }; 4308 4309 mem-thermal { 4310 polling-delay-passive = <250>; 4311 polling-delay = <1000>; 4312 4313 thermal-sensors = <&tsens1 7>; 4314 4315 trips { 4316 mem_alert0: trip-point0 { 4317 temperature = <90000>; 4318 hysteresis = <2000>; 4319 type = "hot"; 4320 }; 4321 }; 4322 }; 4323 4324 modem1-top-thermal { 4325 polling-delay-passive = <250>; 4326 polling-delay = <1000>; 4327 4328 thermal-sensors = <&tsens1 8>; 4329 4330 trips { 4331 modem1_alert0: trip-point0 { 4332 temperature = <90000>; 4333 hysteresis = <2000>; 4334 type = "hot"; 4335 }; 4336 }; 4337 }; 4338 4339 modem2-top-thermal { 4340 polling-delay-passive = <250>; 4341 polling-delay = <1000>; 4342 4343 thermal-sensors = <&tsens1 9>; 4344 4345 trips { 4346 modem2_alert0: trip-point0 { 4347 temperature = <90000>; 4348 hysteresis = <2000>; 4349 type = "hot"; 4350 }; 4351 }; 4352 }; 4353 4354 modem3-top-thermal { 4355 polling-delay-passive = <250>; 4356 polling-delay = <1000>; 4357 4358 thermal-sensors = <&tsens1 10>; 4359 4360 trips { 4361 modem3_alert0: trip-point0 { 4362 temperature = <90000>; 4363 hysteresis = <2000>; 4364 type = "hot"; 4365 }; 4366 }; 4367 }; 4368 4369 modem4-top-thermal { 4370 polling-delay-passive = <250>; 4371 polling-delay = <1000>; 4372 4373 thermal-sensors = <&tsens1 11>; 4374 4375 trips { 4376 modem4_alert0: trip-point0 { 4377 temperature = <90000>; 4378 hysteresis = <2000>; 4379 type = "hot"; 4380 }; 4381 }; 4382 }; 4383 4384 camera-top-thermal { 4385 polling-delay-passive = <250>; 4386 polling-delay = <1000>; 4387 4388 thermal-sensors = <&tsens1 12>; 4389 4390 trips { 4391 camera1_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <2000>; 4394 type = "hot"; 4395 }; 4396 }; 4397 }; 4398 4399 cam-bottom-thermal { 4400 polling-delay-passive = <250>; 4401 polling-delay = <1000>; 4402 4403 thermal-sensors = <&tsens1 13>; 4404 4405 trips { 4406 camera2_alert0: trip-point0 { 4407 temperature = <90000>; 4408 hysteresis = <2000>; 4409 type = "hot"; 4410 }; 4411 }; 4412 }; 4413 }; 4414 4415 timer { 4416 compatible = "arm,armv8-timer"; 4417 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4418 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4419 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4420 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4421 }; 4422}; 4423