1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,sm8350.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19#include <dt-bindings/interconnect/qcom,sm8350.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 clock-output-names = "xo_board"; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 clock-frequency = <32000>; 40 #clock-cells = <0>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 CPU0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo685"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 #cooling-cells = <2>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 next-level-cache = <&L3_0>; 62 L3_0: l3-cache { 63 compatible = "cache"; 64 cache-level = <3>; 65 }; 66 }; 67 }; 68 69 CPU1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "qcom,kryo685"; 72 reg = <0x0 0x100>; 73 enable-method = "psci"; 74 next-level-cache = <&L2_100>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 power-domains = <&CPU_PD1>; 77 power-domain-names = "psci"; 78 #cooling-cells = <2>; 79 L2_100: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 next-level-cache = <&L3_0>; 83 }; 84 }; 85 86 CPU2: cpu@200 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo685"; 89 reg = <0x0 0x200>; 90 enable-method = "psci"; 91 next-level-cache = <&L2_200>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 93 power-domains = <&CPU_PD2>; 94 power-domain-names = "psci"; 95 #cooling-cells = <2>; 96 L2_200: l2-cache { 97 compatible = "cache"; 98 cache-level = <2>; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU3: cpu@300 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo685"; 106 reg = <0x0 0x300>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_300>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 power-domains = <&CPU_PD3>; 111 power-domain-names = "psci"; 112 #cooling-cells = <2>; 113 L2_300: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU4: cpu@400 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo685"; 123 reg = <0x0 0x400>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_400>; 126 qcom,freq-domain = <&cpufreq_hw 1>; 127 power-domains = <&CPU_PD4>; 128 power-domain-names = "psci"; 129 #cooling-cells = <2>; 130 L2_400: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU5: cpu@500 { 138 device_type = "cpu"; 139 compatible = "qcom,kryo685"; 140 reg = <0x0 0x500>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_500>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 power-domains = <&CPU_PD5>; 145 power-domain-names = "psci"; 146 #cooling-cells = <2>; 147 L2_500: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 next-level-cache = <&L3_0>; 151 }; 152 153 }; 154 155 CPU6: cpu@600 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo685"; 158 reg = <0x0 0x600>; 159 enable-method = "psci"; 160 next-level-cache = <&L2_600>; 161 qcom,freq-domain = <&cpufreq_hw 1>; 162 power-domains = <&CPU_PD6>; 163 power-domain-names = "psci"; 164 #cooling-cells = <2>; 165 L2_600: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU7: cpu@700 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo685"; 175 reg = <0x0 0x700>; 176 enable-method = "psci"; 177 next-level-cache = <&L2_700>; 178 qcom,freq-domain = <&cpufreq_hw 2>; 179 power-domains = <&CPU_PD7>; 180 power-domain-names = "psci"; 181 #cooling-cells = <2>; 182 L2_700: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 }; 187 }; 188 189 cpu-map { 190 cluster0 { 191 core0 { 192 cpu = <&CPU0>; 193 }; 194 195 core1 { 196 cpu = <&CPU1>; 197 }; 198 199 core2 { 200 cpu = <&CPU2>; 201 }; 202 203 core3 { 204 cpu = <&CPU3>; 205 }; 206 207 core4 { 208 cpu = <&CPU4>; 209 }; 210 211 core5 { 212 cpu = <&CPU5>; 213 }; 214 215 core6 { 216 cpu = <&CPU6>; 217 }; 218 219 core7 { 220 cpu = <&CPU7>; 221 }; 222 }; 223 }; 224 225 idle-states { 226 entry-method = "psci"; 227 228 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "silver-rail-power-collapse"; 231 arm,psci-suspend-param = <0x40000004>; 232 entry-latency-us = <355>; 233 exit-latency-us = <909>; 234 min-residency-us = <3934>; 235 local-timer-stop; 236 }; 237 238 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "gold-rail-power-collapse"; 241 arm,psci-suspend-param = <0x40000004>; 242 entry-latency-us = <241>; 243 exit-latency-us = <1461>; 244 min-residency-us = <4488>; 245 local-timer-stop; 246 }; 247 }; 248 249 domain-idle-states { 250 CLUSTER_SLEEP_0: cluster-sleep-0 { 251 compatible = "domain-idle-state"; 252 idle-state-name = "cluster-power-collapse"; 253 arm,psci-suspend-param = <0x4100c344>; 254 entry-latency-us = <3263>; 255 exit-latency-us = <6562>; 256 min-residency-us = <9987>; 257 local-timer-stop; 258 }; 259 }; 260 }; 261 262 firmware { 263 scm: scm { 264 compatible = "qcom,scm-sm8350", "qcom,scm"; 265 #reset-cells = <1>; 266 }; 267 }; 268 269 memory@80000000 { 270 device_type = "memory"; 271 /* We expect the bootloader to fill in the size */ 272 reg = <0x0 0x80000000 0x0 0x0>; 273 }; 274 275 pmu { 276 compatible = "arm,armv8-pmuv3"; 277 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 278 }; 279 280 psci { 281 compatible = "arm,psci-1.0"; 282 method = "smc"; 283 284 CPU_PD0: power-domain-cpu0 { 285 #power-domain-cells = <0>; 286 power-domains = <&CLUSTER_PD>; 287 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 288 }; 289 290 CPU_PD1: power-domain-cpu1 { 291 #power-domain-cells = <0>; 292 power-domains = <&CLUSTER_PD>; 293 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 294 }; 295 296 CPU_PD2: power-domain-cpu2 { 297 #power-domain-cells = <0>; 298 power-domains = <&CLUSTER_PD>; 299 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 300 }; 301 302 CPU_PD3: power-domain-cpu3 { 303 #power-domain-cells = <0>; 304 power-domains = <&CLUSTER_PD>; 305 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 306 }; 307 308 CPU_PD4: power-domain-cpu4 { 309 #power-domain-cells = <0>; 310 power-domains = <&CLUSTER_PD>; 311 domain-idle-states = <&BIG_CPU_SLEEP_0>; 312 }; 313 314 CPU_PD5: power-domain-cpu5 { 315 #power-domain-cells = <0>; 316 power-domains = <&CLUSTER_PD>; 317 domain-idle-states = <&BIG_CPU_SLEEP_0>; 318 }; 319 320 CPU_PD6: power-domain-cpu6 { 321 #power-domain-cells = <0>; 322 power-domains = <&CLUSTER_PD>; 323 domain-idle-states = <&BIG_CPU_SLEEP_0>; 324 }; 325 326 CPU_PD7: power-domain-cpu7 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&BIG_CPU_SLEEP_0>; 330 }; 331 332 CLUSTER_PD: power-domain-cpu-cluster0 { 333 #power-domain-cells = <0>; 334 domain-idle-states = <&CLUSTER_SLEEP_0>; 335 }; 336 }; 337 338 qup_opp_table_100mhz: opp-table-qup100mhz { 339 compatible = "operating-points-v2"; 340 341 opp-50000000 { 342 opp-hz = /bits/ 64 <50000000>; 343 required-opps = <&rpmhpd_opp_min_svs>; 344 }; 345 346 opp-75000000 { 347 opp-hz = /bits/ 64 <75000000>; 348 required-opps = <&rpmhpd_opp_low_svs>; 349 }; 350 351 opp-100000000 { 352 opp-hz = /bits/ 64 <100000000>; 353 required-opps = <&rpmhpd_opp_svs>; 354 }; 355 }; 356 357 qup_opp_table_120mhz: opp-table-qup120mhz { 358 compatible = "operating-points-v2"; 359 360 opp-50000000 { 361 opp-hz = /bits/ 64 <50000000>; 362 required-opps = <&rpmhpd_opp_min_svs>; 363 }; 364 365 opp-75000000 { 366 opp-hz = /bits/ 64 <75000000>; 367 required-opps = <&rpmhpd_opp_low_svs>; 368 }; 369 370 opp-120000000 { 371 opp-hz = /bits/ 64 <120000000>; 372 required-opps = <&rpmhpd_opp_svs>; 373 }; 374 }; 375 376 reserved_memory: reserved-memory { 377 #address-cells = <2>; 378 #size-cells = <2>; 379 ranges; 380 381 hyp_mem: memory@80000000 { 382 reg = <0x0 0x80000000 0x0 0x600000>; 383 no-map; 384 }; 385 386 xbl_aop_mem: memory@80700000 { 387 no-map; 388 reg = <0x0 0x80700000 0x0 0x160000>; 389 }; 390 391 cmd_db: memory@80860000 { 392 compatible = "qcom,cmd-db"; 393 reg = <0x0 0x80860000 0x0 0x20000>; 394 no-map; 395 }; 396 397 reserved_xbl_uefi_log: memory@80880000 { 398 reg = <0x0 0x80880000 0x0 0x14000>; 399 no-map; 400 }; 401 402 smem@80900000 { 403 compatible = "qcom,smem"; 404 reg = <0x0 0x80900000 0x0 0x200000>; 405 hwlocks = <&tcsr_mutex 3>; 406 no-map; 407 }; 408 409 cpucp_fw_mem: memory@80b00000 { 410 reg = <0x0 0x80b00000 0x0 0x100000>; 411 no-map; 412 }; 413 414 cdsp_secure_heap: memory@80c00000 { 415 reg = <0x0 0x80c00000 0x0 0x4600000>; 416 no-map; 417 }; 418 419 pil_camera_mem: mmeory@85200000 { 420 reg = <0x0 0x85200000 0x0 0x500000>; 421 no-map; 422 }; 423 424 pil_video_mem: memory@85700000 { 425 reg = <0x0 0x85700000 0x0 0x500000>; 426 no-map; 427 }; 428 429 pil_cvp_mem: memory@85c00000 { 430 reg = <0x0 0x85c00000 0x0 0x500000>; 431 no-map; 432 }; 433 434 pil_adsp_mem: memory@86100000 { 435 reg = <0x0 0x86100000 0x0 0x2100000>; 436 no-map; 437 }; 438 439 pil_slpi_mem: memory@88200000 { 440 reg = <0x0 0x88200000 0x0 0x1500000>; 441 no-map; 442 }; 443 444 pil_cdsp_mem: memory@89700000 { 445 reg = <0x0 0x89700000 0x0 0x1e00000>; 446 no-map; 447 }; 448 449 pil_ipa_fw_mem: memory@8b500000 { 450 reg = <0x0 0x8b500000 0x0 0x10000>; 451 no-map; 452 }; 453 454 pil_ipa_gsi_mem: memory@8b510000 { 455 reg = <0x0 0x8b510000 0x0 0xa000>; 456 no-map; 457 }; 458 459 pil_gpu_mem: memory@8b51a000 { 460 reg = <0x0 0x8b51a000 0x0 0x2000>; 461 no-map; 462 }; 463 464 pil_spss_mem: memory@8b600000 { 465 reg = <0x0 0x8b600000 0x0 0x100000>; 466 no-map; 467 }; 468 469 pil_modem_mem: memory@8b800000 { 470 reg = <0x0 0x8b800000 0x0 0x10000000>; 471 no-map; 472 }; 473 474 rmtfs_mem: memory@9b800000 { 475 compatible = "qcom,rmtfs-mem"; 476 reg = <0x0 0x9b800000 0x0 0x280000>; 477 no-map; 478 479 qcom,client-id = <1>; 480 qcom,vmid = <15>; 481 }; 482 483 hyp_reserved_mem: memory@d0000000 { 484 reg = <0x0 0xd0000000 0x0 0x800000>; 485 no-map; 486 }; 487 488 pil_trustedvm_mem: memory@d0800000 { 489 reg = <0x0 0xd0800000 0x0 0x76f7000>; 490 no-map; 491 }; 492 493 qrtr_shbuf: memory@d7ef7000 { 494 reg = <0x0 0xd7ef7000 0x0 0x9000>; 495 no-map; 496 }; 497 498 chan0_shbuf: memory@d7f00000 { 499 reg = <0x0 0xd7f00000 0x0 0x80000>; 500 no-map; 501 }; 502 503 chan1_shbuf: memory@d7f80000 { 504 reg = <0x0 0xd7f80000 0x0 0x80000>; 505 no-map; 506 }; 507 508 removed_mem: memory@d8800000 { 509 reg = <0x0 0xd8800000 0x0 0x6800000>; 510 no-map; 511 }; 512 }; 513 514 smp2p-adsp { 515 compatible = "qcom,smp2p"; 516 qcom,smem = <443>, <429>; 517 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 518 IPCC_MPROC_SIGNAL_SMP2P 519 IRQ_TYPE_EDGE_RISING>; 520 mboxes = <&ipcc IPCC_CLIENT_LPASS 521 IPCC_MPROC_SIGNAL_SMP2P>; 522 523 qcom,local-pid = <0>; 524 qcom,remote-pid = <2>; 525 526 smp2p_adsp_out: master-kernel { 527 qcom,entry-name = "master-kernel"; 528 #qcom,smem-state-cells = <1>; 529 }; 530 531 smp2p_adsp_in: slave-kernel { 532 qcom,entry-name = "slave-kernel"; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 }; 536 }; 537 538 smp2p-cdsp { 539 compatible = "qcom,smp2p"; 540 qcom,smem = <94>, <432>; 541 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 542 IPCC_MPROC_SIGNAL_SMP2P 543 IRQ_TYPE_EDGE_RISING>; 544 mboxes = <&ipcc IPCC_CLIENT_CDSP 545 IPCC_MPROC_SIGNAL_SMP2P>; 546 547 qcom,local-pid = <0>; 548 qcom,remote-pid = <5>; 549 550 smp2p_cdsp_out: master-kernel { 551 qcom,entry-name = "master-kernel"; 552 #qcom,smem-state-cells = <1>; 553 }; 554 555 smp2p_cdsp_in: slave-kernel { 556 qcom,entry-name = "slave-kernel"; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 }; 560 }; 561 562 smp2p-modem { 563 compatible = "qcom,smp2p"; 564 qcom,smem = <435>, <428>; 565 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 566 IPCC_MPROC_SIGNAL_SMP2P 567 IRQ_TYPE_EDGE_RISING>; 568 mboxes = <&ipcc IPCC_CLIENT_MPSS 569 IPCC_MPROC_SIGNAL_SMP2P>; 570 571 qcom,local-pid = <0>; 572 qcom,remote-pid = <1>; 573 574 smp2p_modem_out: master-kernel { 575 qcom,entry-name = "master-kernel"; 576 #qcom,smem-state-cells = <1>; 577 }; 578 579 smp2p_modem_in: slave-kernel { 580 qcom,entry-name = "slave-kernel"; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 }; 584 585 ipa_smp2p_out: ipa-ap-to-modem { 586 qcom,entry-name = "ipa"; 587 #qcom,smem-state-cells = <1>; 588 }; 589 590 ipa_smp2p_in: ipa-modem-to-ap { 591 qcom,entry-name = "ipa"; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 }; 595 }; 596 597 smp2p-slpi { 598 compatible = "qcom,smp2p"; 599 qcom,smem = <481>, <430>; 600 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 601 IPCC_MPROC_SIGNAL_SMP2P 602 IRQ_TYPE_EDGE_RISING>; 603 mboxes = <&ipcc IPCC_CLIENT_SLPI 604 IPCC_MPROC_SIGNAL_SMP2P>; 605 606 qcom,local-pid = <0>; 607 qcom,remote-pid = <3>; 608 609 smp2p_slpi_out: master-kernel { 610 qcom,entry-name = "master-kernel"; 611 #qcom,smem-state-cells = <1>; 612 }; 613 614 smp2p_slpi_in: slave-kernel { 615 qcom,entry-name = "slave-kernel"; 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 }; 619 }; 620 621 soc: soc@0 { 622 #address-cells = <2>; 623 #size-cells = <2>; 624 ranges = <0 0 0 0 0x10 0>; 625 dma-ranges = <0 0 0 0 0x10 0>; 626 compatible = "simple-bus"; 627 628 gcc: clock-controller@100000 { 629 compatible = "qcom,gcc-sm8350"; 630 reg = <0x0 0x00100000 0x0 0x1f0000>; 631 #clock-cells = <1>; 632 #reset-cells = <1>; 633 #power-domain-cells = <1>; 634 clock-names = "bi_tcxo", 635 "sleep_clk", 636 "pcie_0_pipe_clk", 637 "pcie_1_pipe_clk", 638 "ufs_card_rx_symbol_0_clk", 639 "ufs_card_rx_symbol_1_clk", 640 "ufs_card_tx_symbol_0_clk", 641 "ufs_phy_rx_symbol_0_clk", 642 "ufs_phy_rx_symbol_1_clk", 643 "ufs_phy_tx_symbol_0_clk", 644 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 645 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 646 clocks = <&rpmhcc RPMH_CXO_CLK>, 647 <&sleep_clk>, 648 <&pcie0_phy>, 649 <&pcie1_phy>, 650 <0>, 651 <0>, 652 <0>, 653 <&ufs_mem_phy_lanes 0>, 654 <&ufs_mem_phy_lanes 1>, 655 <&ufs_mem_phy_lanes 2>, 656 <0>, 657 <0>; 658 }; 659 660 ipcc: mailbox@408000 { 661 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 662 reg = <0 0x00408000 0 0x1000>; 663 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 664 interrupt-controller; 665 #interrupt-cells = <3>; 666 #mbox-cells = <2>; 667 }; 668 669 gpi_dma2: dma-controller@800000 { 670 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 671 reg = <0 0x00800000 0 0x60000>; 672 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 684 dma-channels = <12>; 685 dma-channel-mask = <0xff>; 686 iommus = <&apps_smmu 0x5f6 0x0>; 687 #dma-cells = <3>; 688 status = "disabled"; 689 }; 690 691 qupv3_id_2: geniqup@8c0000 { 692 compatible = "qcom,geni-se-qup"; 693 reg = <0x0 0x008c0000 0x0 0x6000>; 694 clock-names = "m-ahb", "s-ahb"; 695 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 696 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 697 iommus = <&apps_smmu 0x5e3 0x0>; 698 #address-cells = <2>; 699 #size-cells = <2>; 700 ranges; 701 status = "disabled"; 702 703 i2c14: i2c@880000 { 704 compatible = "qcom,geni-i2c"; 705 reg = <0 0x00880000 0 0x4000>; 706 clock-names = "se"; 707 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&qup_i2c14_default>; 710 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 711 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 712 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 713 dma-names = "tx", "rx"; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 status = "disabled"; 717 }; 718 719 spi14: spi@880000 { 720 compatible = "qcom,geni-spi"; 721 reg = <0 0x00880000 0 0x4000>; 722 clock-names = "se"; 723 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 724 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 725 power-domains = <&rpmhpd SM8350_CX>; 726 operating-points-v2 = <&qup_opp_table_120mhz>; 727 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 728 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 729 dma-names = "tx", "rx"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "disabled"; 733 }; 734 735 i2c15: i2c@884000 { 736 compatible = "qcom,geni-i2c"; 737 reg = <0 0x00884000 0 0x4000>; 738 clock-names = "se"; 739 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&qup_i2c15_default>; 742 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 743 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 744 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 745 dma-names = "tx", "rx"; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 status = "disabled"; 749 }; 750 751 spi15: spi@884000 { 752 compatible = "qcom,geni-spi"; 753 reg = <0 0x00884000 0 0x4000>; 754 clock-names = "se"; 755 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 756 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 757 power-domains = <&rpmhpd SM8350_CX>; 758 operating-points-v2 = <&qup_opp_table_120mhz>; 759 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 760 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 761 dma-names = "tx", "rx"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 }; 766 767 i2c16: i2c@888000 { 768 compatible = "qcom,geni-i2c"; 769 reg = <0 0x00888000 0 0x4000>; 770 clock-names = "se"; 771 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&qup_i2c16_default>; 774 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 775 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 776 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 777 dma-names = "tx", "rx"; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 783 spi16: spi@888000 { 784 compatible = "qcom,geni-spi"; 785 reg = <0 0x00888000 0 0x4000>; 786 clock-names = "se"; 787 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 788 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 789 power-domains = <&rpmhpd SM8350_CX>; 790 operating-points-v2 = <&qup_opp_table_100mhz>; 791 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 792 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 793 dma-names = "tx", "rx"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 status = "disabled"; 797 }; 798 799 i2c17: i2c@88c000 { 800 compatible = "qcom,geni-i2c"; 801 reg = <0 0x0088c000 0 0x4000>; 802 clock-names = "se"; 803 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&qup_i2c17_default>; 806 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 807 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 808 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 809 dma-names = "tx", "rx"; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 status = "disabled"; 813 }; 814 815 spi17: spi@88c000 { 816 compatible = "qcom,geni-spi"; 817 reg = <0 0x0088c000 0 0x4000>; 818 clock-names = "se"; 819 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 820 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 821 power-domains = <&rpmhpd SM8350_CX>; 822 operating-points-v2 = <&qup_opp_table_100mhz>; 823 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 824 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 825 dma-names = "tx", "rx"; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 status = "disabled"; 829 }; 830 831 /* QUP no. 18 seems to be strictly SPI/UART-only */ 832 833 spi18: spi@890000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0 0x00890000 0 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 838 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 839 power-domains = <&rpmhpd SM8350_CX>; 840 operating-points-v2 = <&qup_opp_table_100mhz>; 841 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 842 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 843 dma-names = "tx", "rx"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 status = "disabled"; 847 }; 848 849 uart18: serial@890000 { 850 compatible = "qcom,geni-uart"; 851 reg = <0 0x00890000 0 0x4000>; 852 clock-names = "se"; 853 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 854 pinctrl-names = "default"; 855 pinctrl-0 = <&qup_uart18_default>; 856 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 857 power-domains = <&rpmhpd SM8350_CX>; 858 operating-points-v2 = <&qup_opp_table_100mhz>; 859 status = "disabled"; 860 }; 861 862 i2c19: i2c@894000 { 863 compatible = "qcom,geni-i2c"; 864 reg = <0 0x00894000 0 0x4000>; 865 clock-names = "se"; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&qup_i2c19_default>; 869 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 870 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 871 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 872 dma-names = "tx", "rx"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 spi19: spi@894000 { 879 compatible = "qcom,geni-spi"; 880 reg = <0 0x00894000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 883 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 884 power-domains = <&rpmhpd SM8350_CX>; 885 operating-points-v2 = <&qup_opp_table_100mhz>; 886 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 887 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 888 dma-names = "tx", "rx"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 }; 894 895 gpi_dma0: dma-controller@900000 { 896 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 897 reg = <0 0x09800000 0 0x60000>; 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 910 dma-channels = <12>; 911 dma-channel-mask = <0x7e>; 912 iommus = <&apps_smmu 0x5b6 0x0>; 913 #dma-cells = <3>; 914 status = "disabled"; 915 }; 916 917 qupv3_id_0: geniqup@9c0000 { 918 compatible = "qcom,geni-se-qup"; 919 reg = <0x0 0x009c0000 0x0 0x6000>; 920 clock-names = "m-ahb", "s-ahb"; 921 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 922 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 923 iommus = <&apps_smmu 0x5a3 0>; 924 #address-cells = <2>; 925 #size-cells = <2>; 926 ranges; 927 status = "disabled"; 928 929 i2c0: i2c@980000 { 930 compatible = "qcom,geni-i2c"; 931 reg = <0 0x00980000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_i2c0_default>; 936 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 937 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 938 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 939 dma-names = "tx", "rx"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 945 spi0: spi@980000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x00980000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 950 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 951 power-domains = <&rpmhpd SM8350_CX>; 952 operating-points-v2 = <&qup_opp_table_100mhz>; 953 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 954 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 955 dma-names = "tx", "rx"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c1: i2c@984000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0 0x00984000 0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_i2c1_default>; 968 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 969 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 970 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 971 dma-names = "tx", "rx"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 spi1: spi@984000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0 0x00984000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 982 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 983 power-domains = <&rpmhpd SM8350_CX>; 984 operating-points-v2 = <&qup_opp_table_100mhz>; 985 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 986 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 987 dma-names = "tx", "rx"; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 i2c2: i2c@988000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0 0x00988000 0 0x4000>; 996 clock-names = "se"; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_i2c2_default>; 1000 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1001 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1002 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1003 dma-names = "tx", "rx"; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 status = "disabled"; 1007 }; 1008 1009 spi2: spi@988000 { 1010 compatible = "qcom,geni-spi"; 1011 reg = <0 0x00988000 0 0x4000>; 1012 clock-names = "se"; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1014 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1015 power-domains = <&rpmhpd SM8350_CX>; 1016 operating-points-v2 = <&qup_opp_table_100mhz>; 1017 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1018 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1019 dma-names = "tx", "rx"; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 uart2: serial@98c000 { 1026 compatible = "qcom,geni-debug-uart"; 1027 reg = <0 0x0098c000 0 0x4000>; 1028 clock-names = "se"; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&qup_uart3_default_state>; 1032 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1033 power-domains = <&rpmhpd SM8350_CX>; 1034 operating-points-v2 = <&qup_opp_table_100mhz>; 1035 status = "disabled"; 1036 }; 1037 1038 /* QUP no. 3 seems to be strictly SPI-only */ 1039 1040 spi3: spi@98c000 { 1041 compatible = "qcom,geni-spi"; 1042 reg = <0 0x0098c000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1045 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1046 power-domains = <&rpmhpd SM8350_CX>; 1047 operating-points-v2 = <&qup_opp_table_100mhz>; 1048 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1049 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c4: i2c@990000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00990000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c4_default>; 1063 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1064 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1065 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi4: spi@990000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00990000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1077 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmhpd SM8350_CX>; 1079 operating-points-v2 = <&qup_opp_table_100mhz>; 1080 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1081 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1082 dma-names = "tx", "rx"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 i2c5: i2c@994000 { 1089 compatible = "qcom,geni-i2c"; 1090 reg = <0 0x00994000 0 0x4000>; 1091 clock-names = "se"; 1092 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&qup_i2c5_default>; 1095 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1096 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1097 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1098 dma-names = "tx", "rx"; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 spi5: spi@994000 { 1105 compatible = "qcom,geni-spi"; 1106 reg = <0 0x00994000 0 0x4000>; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1109 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1110 power-domains = <&rpmhpd SM8350_CX>; 1111 operating-points-v2 = <&qup_opp_table_100mhz>; 1112 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1113 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1114 dma-names = "tx", "rx"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 i2c6: i2c@998000 { 1121 compatible = "qcom,geni-i2c"; 1122 reg = <0 0x00998000 0 0x4000>; 1123 clock-names = "se"; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&qup_i2c6_default>; 1127 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1128 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1129 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1130 dma-names = "tx", "rx"; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "disabled"; 1134 }; 1135 1136 spi6: spi@998000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00998000 0 0x4000>; 1139 clock-names = "se"; 1140 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1141 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1142 power-domains = <&rpmhpd SM8350_CX>; 1143 operating-points-v2 = <&qup_opp_table_100mhz>; 1144 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1145 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1146 dma-names = "tx", "rx"; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 uart6: serial@998000 { 1153 compatible = "qcom,geni-uart"; 1154 reg = <0 0x00998000 0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_uart6_default>; 1159 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1160 power-domains = <&rpmhpd SM8350_CX>; 1161 operating-points-v2 = <&qup_opp_table_100mhz>; 1162 status = "disabled"; 1163 }; 1164 1165 i2c7: i2c@99c000 { 1166 compatible = "qcom,geni-i2c"; 1167 reg = <0 0x0099c000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_i2c7_default>; 1172 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1173 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1174 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1175 dma-names = "tx", "rx"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 spi7: spi@99c000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x0099c000 0 0x4000>; 1184 clock-names = "se"; 1185 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1186 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1187 power-domains = <&rpmhpd SM8350_CX>; 1188 operating-points-v2 = <&qup_opp_table_100mhz>; 1189 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1190 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1191 dma-names = "tx", "rx"; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 }; 1197 1198 gpi_dma1: dma-controller@a00000 { 1199 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1200 reg = <0 0x00a00000 0 0x60000>; 1201 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1213 dma-channels = <12>; 1214 dma-channel-mask = <0xff>; 1215 iommus = <&apps_smmu 0x56 0x0>; 1216 #dma-cells = <3>; 1217 status = "disabled"; 1218 }; 1219 1220 qupv3_id_1: geniqup@ac0000 { 1221 compatible = "qcom,geni-se-qup"; 1222 reg = <0x0 0x00ac0000 0x0 0x6000>; 1223 clock-names = "m-ahb", "s-ahb"; 1224 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1225 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1226 iommus = <&apps_smmu 0x43 0>; 1227 #address-cells = <2>; 1228 #size-cells = <2>; 1229 ranges; 1230 status = "disabled"; 1231 1232 i2c8: i2c@a80000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00a80000 0 0x4000>; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c8_default>; 1239 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1240 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1241 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1242 dma-names = "tx", "rx"; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 status = "disabled"; 1246 }; 1247 1248 spi8: spi@a80000 { 1249 compatible = "qcom,geni-spi"; 1250 reg = <0 0x00a80000 0 0x4000>; 1251 clock-names = "se"; 1252 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1253 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1254 power-domains = <&rpmhpd SM8350_CX>; 1255 operating-points-v2 = <&qup_opp_table_120mhz>; 1256 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1257 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1258 dma-names = "tx", "rx"; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 status = "disabled"; 1262 }; 1263 1264 i2c9: i2c@a84000 { 1265 compatible = "qcom,geni-i2c"; 1266 reg = <0 0x00a84000 0 0x4000>; 1267 clock-names = "se"; 1268 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_i2c9_default>; 1271 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1272 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1273 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1274 dma-names = "tx", "rx"; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 spi9: spi@a84000 { 1281 compatible = "qcom,geni-spi"; 1282 reg = <0 0x00a84000 0 0x4000>; 1283 clock-names = "se"; 1284 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1285 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1286 power-domains = <&rpmhpd SM8350_CX>; 1287 operating-points-v2 = <&qup_opp_table_100mhz>; 1288 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1289 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1290 dma-names = "tx", "rx"; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 status = "disabled"; 1294 }; 1295 1296 i2c10: i2c@a88000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00a88000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_i2c10_default>; 1303 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1304 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1305 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 spi10: spi@a88000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x00a88000 0 0x4000>; 1315 clock-names = "se"; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1317 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1318 power-domains = <&rpmhpd SM8350_CX>; 1319 operating-points-v2 = <&qup_opp_table_100mhz>; 1320 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1321 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1322 dma-names = "tx", "rx"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c11: i2c@a8c000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0 0x00a8c000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_i2c11_default>; 1335 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1336 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1337 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1338 dma-names = "tx", "rx"; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 status = "disabled"; 1342 }; 1343 1344 spi11: spi@a8c000 { 1345 compatible = "qcom,geni-spi"; 1346 reg = <0 0x00a8c000 0 0x4000>; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1349 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1350 power-domains = <&rpmhpd SM8350_CX>; 1351 operating-points-v2 = <&qup_opp_table_100mhz>; 1352 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1353 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 1360 i2c12: i2c@a90000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x00a90000 0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c12_default>; 1367 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1368 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1369 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 spi12: spi@a90000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x00a90000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1381 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1382 power-domains = <&rpmhpd SM8350_CX>; 1383 operating-points-v2 = <&qup_opp_table_100mhz>; 1384 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1385 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1386 dma-names = "tx", "rx"; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c13: i2c@a94000 { 1393 compatible = "qcom,geni-i2c"; 1394 reg = <0 0x00a94000 0 0x4000>; 1395 clock-names = "se"; 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&qup_i2c13_default>; 1399 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1401 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1402 dma-names = "tx", "rx"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 spi13: spi@a94000 { 1409 compatible = "qcom,geni-spi"; 1410 reg = <0 0x00a94000 0 0x4000>; 1411 clock-names = "se"; 1412 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1413 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SM8350_CX>; 1415 operating-points-v2 = <&qup_opp_table_100mhz>; 1416 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1417 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1418 dma-names = "tx", "rx"; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 status = "disabled"; 1422 }; 1423 }; 1424 1425 rng: rng@10d3000 { 1426 compatible = "qcom,prng-ee"; 1427 reg = <0 0x010d3000 0 0x1000>; 1428 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1429 clock-names = "core"; 1430 }; 1431 1432 config_noc: interconnect@1500000 { 1433 compatible = "qcom,sm8350-config-noc"; 1434 reg = <0 0x01500000 0 0xa580>; 1435 #interconnect-cells = <2>; 1436 qcom,bcm-voters = <&apps_bcm_voter>; 1437 }; 1438 1439 mc_virt: interconnect@1580000 { 1440 compatible = "qcom,sm8350-mc-virt"; 1441 reg = <0 0x01580000 0 0x1000>; 1442 #interconnect-cells = <2>; 1443 qcom,bcm-voters = <&apps_bcm_voter>; 1444 }; 1445 1446 system_noc: interconnect@1680000 { 1447 compatible = "qcom,sm8350-system-noc"; 1448 reg = <0 0x01680000 0 0x1c200>; 1449 #interconnect-cells = <2>; 1450 qcom,bcm-voters = <&apps_bcm_voter>; 1451 }; 1452 1453 aggre1_noc: interconnect@16e0000 { 1454 compatible = "qcom,sm8350-aggre1-noc"; 1455 reg = <0 0x016e0000 0 0x1f180>; 1456 #interconnect-cells = <2>; 1457 qcom,bcm-voters = <&apps_bcm_voter>; 1458 }; 1459 1460 aggre2_noc: interconnect@1700000 { 1461 compatible = "qcom,sm8350-aggre2-noc"; 1462 reg = <0 0x01700000 0 0x33000>; 1463 #interconnect-cells = <2>; 1464 qcom,bcm-voters = <&apps_bcm_voter>; 1465 }; 1466 1467 mmss_noc: interconnect@1740000 { 1468 compatible = "qcom,sm8350-mmss-noc"; 1469 reg = <0 0x01740000 0 0x1f080>; 1470 #interconnect-cells = <2>; 1471 qcom,bcm-voters = <&apps_bcm_voter>; 1472 }; 1473 1474 pcie0: pci@1c00000 { 1475 compatible = "qcom,pcie-sm8350"; 1476 reg = <0 0x01c00000 0 0x3000>, 1477 <0 0x60000000 0 0xf1d>, 1478 <0 0x60000f20 0 0xa8>, 1479 <0 0x60001000 0 0x1000>, 1480 <0 0x60100000 0 0x100000>; 1481 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1482 device_type = "pci"; 1483 linux,pci-domain = <0>; 1484 bus-range = <0x00 0xff>; 1485 num-lanes = <1>; 1486 1487 #address-cells = <3>; 1488 #size-cells = <2>; 1489 1490 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1491 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1492 1493 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1501 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1502 "msi4", "msi5", "msi6", "msi7"; 1503 #interrupt-cells = <1>; 1504 interrupt-map-mask = <0 0 0 0x7>; 1505 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1506 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1507 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1508 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1509 1510 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1511 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1512 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1513 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1514 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1515 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1516 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1517 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1518 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1519 clock-names = "aux", 1520 "cfg", 1521 "bus_master", 1522 "bus_slave", 1523 "slave_q2a", 1524 "tbu", 1525 "ddrss_sf_tbu", 1526 "aggre1", 1527 "aggre0"; 1528 1529 iommus = <&apps_smmu 0x1c00 0x7f>; 1530 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1531 <0x100 &apps_smmu 0x1c01 0x1>; 1532 1533 resets = <&gcc GCC_PCIE_0_BCR>; 1534 reset-names = "pci"; 1535 1536 power-domains = <&gcc PCIE_0_GDSC>; 1537 1538 phys = <&pcie0_phy>; 1539 phy-names = "pciephy"; 1540 1541 status = "disabled"; 1542 }; 1543 1544 pcie0_phy: phy@1c06000 { 1545 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1546 reg = <0 0x01c06000 0 0x2000>; 1547 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1548 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1549 <&gcc GCC_PCIE_0_CLKREF_EN>, 1550 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1551 <&gcc GCC_PCIE_0_PIPE_CLK>; 1552 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1553 1554 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1555 reset-names = "phy"; 1556 1557 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1558 assigned-clock-rates = <100000000>; 1559 1560 #clock-cells = <0>; 1561 clock-output-names = "pcie_0_pipe_clk"; 1562 1563 #phy-cells = <0>; 1564 1565 status = "disabled"; 1566 }; 1567 1568 pcie1: pci@1c08000 { 1569 compatible = "qcom,pcie-sm8350"; 1570 reg = <0 0x01c08000 0 0x3000>, 1571 <0 0x40000000 0 0xf1d>, 1572 <0 0x40000f20 0 0xa8>, 1573 <0 0x40001000 0 0x1000>, 1574 <0 0x40100000 0 0x100000>; 1575 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1576 device_type = "pci"; 1577 linux,pci-domain = <1>; 1578 bus-range = <0x00 0xff>; 1579 num-lanes = <2>; 1580 1581 #address-cells = <3>; 1582 #size-cells = <2>; 1583 1584 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1585 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1586 1587 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1588 interrupt-names = "msi"; 1589 #interrupt-cells = <1>; 1590 interrupt-map-mask = <0 0 0 0x7>; 1591 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1592 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1593 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1594 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1595 1596 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1597 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1598 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1599 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1600 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1601 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1602 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1603 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1604 clock-names = "aux", 1605 "cfg", 1606 "bus_master", 1607 "bus_slave", 1608 "slave_q2a", 1609 "tbu", 1610 "ddrss_sf_tbu", 1611 "aggre1"; 1612 1613 iommus = <&apps_smmu 0x1c80 0x7f>; 1614 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1615 <0x100 &apps_smmu 0x1c81 0x1>; 1616 1617 resets = <&gcc GCC_PCIE_1_BCR>; 1618 reset-names = "pci"; 1619 1620 power-domains = <&gcc PCIE_1_GDSC>; 1621 1622 phys = <&pcie1_phy>; 1623 phy-names = "pciephy"; 1624 1625 status = "disabled"; 1626 }; 1627 1628 pcie1_phy: phy@1c0f000 { 1629 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1630 reg = <0 0x01c0e000 0 0x2000>; 1631 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1632 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1633 <&gcc GCC_PCIE_1_CLKREF_EN>, 1634 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1635 <&gcc GCC_PCIE_1_PIPE_CLK>; 1636 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1637 1638 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1639 reset-names = "phy"; 1640 1641 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1642 assigned-clock-rates = <100000000>; 1643 1644 #clock-cells = <0>; 1645 clock-output-names = "pcie_1_pipe_clk"; 1646 1647 #phy-cells = <0>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 ufs_mem_hc: ufshc@1d84000 { 1653 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1654 "jedec,ufs-2.0"; 1655 reg = <0 0x01d84000 0 0x3000>; 1656 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1657 phys = <&ufs_mem_phy_lanes>; 1658 phy-names = "ufsphy"; 1659 lanes-per-direction = <2>; 1660 #reset-cells = <1>; 1661 resets = <&gcc GCC_UFS_PHY_BCR>; 1662 reset-names = "rst"; 1663 1664 power-domains = <&gcc UFS_PHY_GDSC>; 1665 1666 iommus = <&apps_smmu 0xe0 0x0>; 1667 dma-coherent; 1668 1669 clock-names = 1670 "core_clk", 1671 "bus_aggr_clk", 1672 "iface_clk", 1673 "core_clk_unipro", 1674 "ref_clk", 1675 "tx_lane0_sync_clk", 1676 "rx_lane0_sync_clk", 1677 "rx_lane1_sync_clk"; 1678 clocks = 1679 <&gcc GCC_UFS_PHY_AXI_CLK>, 1680 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1681 <&gcc GCC_UFS_PHY_AHB_CLK>, 1682 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1683 <&rpmhcc RPMH_CXO_CLK>, 1684 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1685 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1686 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1687 freq-table-hz = 1688 <75000000 300000000>, 1689 <0 0>, 1690 <0 0>, 1691 <75000000 300000000>, 1692 <0 0>, 1693 <0 0>, 1694 <0 0>, 1695 <0 0>; 1696 status = "disabled"; 1697 }; 1698 1699 ufs_mem_phy: phy@1d87000 { 1700 compatible = "qcom,sm8350-qmp-ufs-phy"; 1701 reg = <0 0x01d87000 0 0x1c4>; 1702 #address-cells = <2>; 1703 #size-cells = <2>; 1704 ranges; 1705 clock-names = "ref", 1706 "ref_aux"; 1707 clocks = <&rpmhcc RPMH_CXO_CLK>, 1708 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1709 1710 resets = <&ufs_mem_hc 0>; 1711 reset-names = "ufsphy"; 1712 status = "disabled"; 1713 1714 ufs_mem_phy_lanes: phy@1d87400 { 1715 reg = <0 0x01d87400 0 0x188>, 1716 <0 0x01d87600 0 0x200>, 1717 <0 0x01d87c00 0 0x200>, 1718 <0 0x01d87800 0 0x188>, 1719 <0 0x01d87a00 0 0x200>; 1720 #clock-cells = <1>; 1721 #phy-cells = <0>; 1722 }; 1723 }; 1724 1725 ipa: ipa@1e40000 { 1726 compatible = "qcom,sm8350-ipa"; 1727 1728 iommus = <&apps_smmu 0x5c0 0x0>, 1729 <&apps_smmu 0x5c2 0x0>; 1730 reg = <0 0x01e40000 0 0x8000>, 1731 <0 0x01e50000 0 0x4b20>, 1732 <0 0x01e04000 0 0x23000>; 1733 reg-names = "ipa-reg", 1734 "ipa-shared", 1735 "gsi"; 1736 1737 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1738 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1739 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1740 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1741 interrupt-names = "ipa", 1742 "gsi", 1743 "ipa-clock-query", 1744 "ipa-setup-ready"; 1745 1746 clocks = <&rpmhcc RPMH_IPA_CLK>; 1747 clock-names = "core"; 1748 1749 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1750 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1751 interconnect-names = "memory", 1752 "config"; 1753 1754 qcom,qmp = <&aoss_qmp>; 1755 1756 qcom,smem-states = <&ipa_smp2p_out 0>, 1757 <&ipa_smp2p_out 1>; 1758 qcom,smem-state-names = "ipa-clock-enabled-valid", 1759 "ipa-clock-enabled"; 1760 1761 status = "disabled"; 1762 }; 1763 1764 tcsr_mutex: hwlock@1f40000 { 1765 compatible = "qcom,tcsr-mutex"; 1766 reg = <0x0 0x01f40000 0x0 0x40000>; 1767 #hwlock-cells = <1>; 1768 }; 1769 1770 gpu: gpu@3d00000 { 1771 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1772 1773 reg = <0 0x03d00000 0 0x40000>, 1774 <0 0x03d9e000 0 0x1000>, 1775 <0 0x03d61000 0 0x800>; 1776 reg-names = "kgsl_3d0_reg_memory", 1777 "cx_mem", 1778 "cx_dbgc"; 1779 1780 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1781 1782 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1783 1784 operating-points-v2 = <&gpu_opp_table>; 1785 1786 qcom,gmu = <&gmu>; 1787 1788 status = "disabled"; 1789 1790 zap-shader { 1791 memory-region = <&pil_gpu_mem>; 1792 }; 1793 1794 /* note: downstream checks gpu binning for 670 Mhz */ 1795 gpu_opp_table: opp-table { 1796 compatible = "operating-points-v2"; 1797 1798 opp-840000000 { 1799 opp-hz = /bits/ 64 <840000000>; 1800 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1801 }; 1802 1803 opp-778000000 { 1804 opp-hz = /bits/ 64 <778000000>; 1805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1806 }; 1807 1808 opp-738000000 { 1809 opp-hz = /bits/ 64 <738000000>; 1810 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1811 }; 1812 1813 opp-676000000 { 1814 opp-hz = /bits/ 64 <676000000>; 1815 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1816 }; 1817 1818 opp-608000000 { 1819 opp-hz = /bits/ 64 <608000000>; 1820 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1821 }; 1822 1823 opp-540000000 { 1824 opp-hz = /bits/ 64 <540000000>; 1825 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1826 }; 1827 1828 opp-491000000 { 1829 opp-hz = /bits/ 64 <491000000>; 1830 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1831 }; 1832 1833 opp-443000000 { 1834 opp-hz = /bits/ 64 <443000000>; 1835 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1836 }; 1837 1838 opp-379000000 { 1839 opp-hz = /bits/ 64 <379000000>; 1840 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1841 }; 1842 1843 opp-315000000 { 1844 opp-hz = /bits/ 64 <315000000>; 1845 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1846 }; 1847 }; 1848 }; 1849 1850 gmu: gmu@3d6a000 { 1851 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1852 1853 reg = <0 0x03d6a000 0 0x34000>, 1854 <0 0x03de0000 0 0x10000>, 1855 <0 0x0b290000 0 0x10000>; 1856 reg-names = "gmu", "rscc", "gmu_pdc"; 1857 1858 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupt-names = "hfi", "gmu"; 1861 1862 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1863 <&gpucc GPU_CC_CXO_CLK>, 1864 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1865 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1866 <&gpucc GPU_CC_AHB_CLK>, 1867 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1868 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1869 clock-names = "gmu", 1870 "cxo", 1871 "axi", 1872 "memnoc", 1873 "ahb", 1874 "hub", 1875 "smmu_vote"; 1876 1877 power-domains = <&gpucc GPU_CX_GDSC>, 1878 <&gpucc GPU_GX_GDSC>; 1879 power-domain-names = "cx", 1880 "gx"; 1881 1882 iommus = <&adreno_smmu 5 0x400>; 1883 1884 operating-points-v2 = <&gmu_opp_table>; 1885 1886 gmu_opp_table: opp-table { 1887 compatible = "operating-points-v2"; 1888 1889 opp-200000000 { 1890 opp-hz = /bits/ 64 <200000000>; 1891 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1892 }; 1893 }; 1894 }; 1895 1896 gpucc: clock-controller@3d90000 { 1897 compatible = "qcom,sm8350-gpucc"; 1898 reg = <0 0x03d90000 0 0x9000>; 1899 clocks = <&rpmhcc RPMH_CXO_CLK>, 1900 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1901 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1902 clock-names = "bi_tcxo", 1903 "gcc_gpu_gpll0_clk_src", 1904 "gcc_gpu_gpll0_div_clk_src"; 1905 #clock-cells = <1>; 1906 #reset-cells = <1>; 1907 #power-domain-cells = <1>; 1908 }; 1909 1910 adreno_smmu: iommu@3da0000 { 1911 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1912 reg = <0 0x03da0000 0 0x20000>; 1913 #iommu-cells = <2>; 1914 #global-interrupts = <2>; 1915 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1927 1928 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1929 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1930 <&gpucc GPU_CC_AHB_CLK>, 1931 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1932 <&gpucc GPU_CC_CX_GMU_CLK>, 1933 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1934 <&gpucc GPU_CC_HUB_AON_CLK>; 1935 clock-names = "bus", 1936 "iface", 1937 "ahb", 1938 "hlos1_vote_gpu_smmu", 1939 "cx_gmu", 1940 "hub_cx_int", 1941 "hub_aon"; 1942 1943 power-domains = <&gpucc GPU_CX_GDSC>; 1944 dma-coherent; 1945 }; 1946 1947 lpass_ag_noc: interconnect@3c40000 { 1948 compatible = "qcom,sm8350-lpass-ag-noc"; 1949 reg = <0 0x03c40000 0 0xf080>; 1950 #interconnect-cells = <2>; 1951 qcom,bcm-voters = <&apps_bcm_voter>; 1952 }; 1953 1954 mpss: remoteproc@4080000 { 1955 compatible = "qcom,sm8350-mpss-pas"; 1956 reg = <0x0 0x04080000 0x0 0x4040>; 1957 1958 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1959 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1960 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1961 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1962 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1963 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1964 interrupt-names = "wdog", "fatal", "ready", "handover", 1965 "stop-ack", "shutdown-ack"; 1966 1967 clocks = <&rpmhcc RPMH_CXO_CLK>; 1968 clock-names = "xo"; 1969 1970 power-domains = <&rpmhpd SM8350_CX>, 1971 <&rpmhpd SM8350_MSS>; 1972 power-domain-names = "cx", "mss"; 1973 1974 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1975 1976 memory-region = <&pil_modem_mem>; 1977 1978 qcom,qmp = <&aoss_qmp>; 1979 1980 qcom,smem-states = <&smp2p_modem_out 0>; 1981 qcom,smem-state-names = "stop"; 1982 1983 status = "disabled"; 1984 1985 glink-edge { 1986 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1987 IPCC_MPROC_SIGNAL_GLINK_QMP 1988 IRQ_TYPE_EDGE_RISING>; 1989 mboxes = <&ipcc IPCC_CLIENT_MPSS 1990 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1991 label = "modem"; 1992 qcom,remote-pid = <1>; 1993 }; 1994 }; 1995 1996 slpi: remoteproc@5c00000 { 1997 compatible = "qcom,sm8350-slpi-pas"; 1998 reg = <0 0x05c00000 0 0x4000>; 1999 2000 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2001 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2002 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2003 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2004 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2005 interrupt-names = "wdog", "fatal", "ready", 2006 "handover", "stop-ack"; 2007 2008 clocks = <&rpmhcc RPMH_CXO_CLK>; 2009 clock-names = "xo"; 2010 2011 power-domains = <&rpmhpd SM8350_LCX>, 2012 <&rpmhpd SM8350_LMX>; 2013 power-domain-names = "lcx", "lmx"; 2014 2015 memory-region = <&pil_slpi_mem>; 2016 2017 qcom,qmp = <&aoss_qmp>; 2018 2019 qcom,smem-states = <&smp2p_slpi_out 0>; 2020 qcom,smem-state-names = "stop"; 2021 2022 status = "disabled"; 2023 2024 glink-edge { 2025 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2026 IPCC_MPROC_SIGNAL_GLINK_QMP 2027 IRQ_TYPE_EDGE_RISING>; 2028 mboxes = <&ipcc IPCC_CLIENT_SLPI 2029 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2030 2031 label = "slpi"; 2032 qcom,remote-pid = <3>; 2033 2034 fastrpc { 2035 compatible = "qcom,fastrpc"; 2036 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2037 label = "sdsp"; 2038 qcom,non-secure-domain; 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 2042 compute-cb@1 { 2043 compatible = "qcom,fastrpc-compute-cb"; 2044 reg = <1>; 2045 iommus = <&apps_smmu 0x0541 0x0>; 2046 }; 2047 2048 compute-cb@2 { 2049 compatible = "qcom,fastrpc-compute-cb"; 2050 reg = <2>; 2051 iommus = <&apps_smmu 0x0542 0x0>; 2052 }; 2053 2054 compute-cb@3 { 2055 compatible = "qcom,fastrpc-compute-cb"; 2056 reg = <3>; 2057 iommus = <&apps_smmu 0x0543 0x0>; 2058 /* note: shared-cb = <4> in downstream */ 2059 }; 2060 }; 2061 }; 2062 }; 2063 2064 sdhc_2: mmc@8804000 { 2065 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2066 reg = <0 0x08804000 0 0x1000>; 2067 2068 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2070 interrupt-names = "hc_irq", "pwr_irq"; 2071 2072 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2073 <&gcc GCC_SDCC2_APPS_CLK>, 2074 <&rpmhcc RPMH_CXO_CLK>; 2075 clock-names = "iface", "core", "xo"; 2076 resets = <&gcc GCC_SDCC2_BCR>; 2077 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2079 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2080 iommus = <&apps_smmu 0x4a0 0x0>; 2081 power-domains = <&rpmhpd SM8350_CX>; 2082 operating-points-v2 = <&sdhc2_opp_table>; 2083 bus-width = <4>; 2084 dma-coherent; 2085 2086 status = "disabled"; 2087 2088 sdhc2_opp_table: opp-table { 2089 compatible = "operating-points-v2"; 2090 2091 opp-100000000 { 2092 opp-hz = /bits/ 64 <100000000>; 2093 required-opps = <&rpmhpd_opp_low_svs>; 2094 }; 2095 2096 opp-202000000 { 2097 opp-hz = /bits/ 64 <202000000>; 2098 required-opps = <&rpmhpd_opp_svs_l1>; 2099 }; 2100 }; 2101 }; 2102 2103 usb_1_hsphy: phy@88e3000 { 2104 compatible = "qcom,sm8350-usb-hs-phy", 2105 "qcom,usb-snps-hs-7nm-phy"; 2106 reg = <0 0x088e3000 0 0x400>; 2107 status = "disabled"; 2108 #phy-cells = <0>; 2109 2110 clocks = <&rpmhcc RPMH_CXO_CLK>; 2111 clock-names = "ref"; 2112 2113 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2114 }; 2115 2116 usb_2_hsphy: phy@88e4000 { 2117 compatible = "qcom,sm8250-usb-hs-phy", 2118 "qcom,usb-snps-hs-7nm-phy"; 2119 reg = <0 0x088e4000 0 0x400>; 2120 status = "disabled"; 2121 #phy-cells = <0>; 2122 2123 clocks = <&rpmhcc RPMH_CXO_CLK>; 2124 clock-names = "ref"; 2125 2126 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2127 }; 2128 2129 usb_1_qmpphy: phy-wrapper@88e9000 { 2130 compatible = "qcom,sm8350-qmp-usb3-phy"; 2131 reg = <0 0x088e9000 0 0x200>, 2132 <0 0x088e8000 0 0x20>; 2133 status = "disabled"; 2134 #address-cells = <2>; 2135 #size-cells = <2>; 2136 ranges; 2137 2138 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2139 <&rpmhcc RPMH_CXO_CLK>, 2140 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2141 clock-names = "aux", "ref_clk_src", "com_aux"; 2142 2143 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2144 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2145 reset-names = "phy", "common"; 2146 2147 usb_1_ssphy: phy@88e9200 { 2148 reg = <0 0x088e9200 0 0x200>, 2149 <0 0x088e9400 0 0x200>, 2150 <0 0x088e9c00 0 0x400>, 2151 <0 0x088e9600 0 0x200>, 2152 <0 0x088e9800 0 0x200>, 2153 <0 0x088e9a00 0 0x100>; 2154 #phy-cells = <0>; 2155 #clock-cells = <0>; 2156 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2157 clock-names = "pipe0"; 2158 clock-output-names = "usb3_phy_pipe_clk_src"; 2159 }; 2160 }; 2161 2162 usb_2_qmpphy: phy-wrapper@88eb000 { 2163 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2164 reg = <0 0x088eb000 0 0x200>; 2165 status = "disabled"; 2166 #address-cells = <2>; 2167 #size-cells = <2>; 2168 ranges; 2169 2170 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2171 <&rpmhcc RPMH_CXO_CLK>, 2172 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2173 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2174 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2175 2176 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2177 <&gcc GCC_USB3_PHY_SEC_BCR>; 2178 reset-names = "phy", "common"; 2179 2180 usb_2_ssphy: phy@88ebe00 { 2181 reg = <0 0x088ebe00 0 0x200>, 2182 <0 0x088ec000 0 0x200>, 2183 <0 0x088eb200 0 0x1100>; 2184 #phy-cells = <0>; 2185 #clock-cells = <0>; 2186 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2187 clock-names = "pipe0"; 2188 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2189 }; 2190 }; 2191 2192 dc_noc: interconnect@90c0000 { 2193 compatible = "qcom,sm8350-dc-noc"; 2194 reg = <0 0x090c0000 0 0x4200>; 2195 #interconnect-cells = <2>; 2196 qcom,bcm-voters = <&apps_bcm_voter>; 2197 }; 2198 2199 gem_noc: interconnect@9100000 { 2200 compatible = "qcom,sm8350-gem-noc"; 2201 reg = <0 0x09100000 0 0xb4000>; 2202 #interconnect-cells = <2>; 2203 qcom,bcm-voters = <&apps_bcm_voter>; 2204 }; 2205 2206 system-cache-controller@9200000 { 2207 compatible = "qcom,sm8350-llcc"; 2208 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2209 reg-names = "llcc_base", "llcc_broadcast_base"; 2210 }; 2211 2212 compute_noc: interconnect@a0c0000 { 2213 compatible = "qcom,sm8350-compute-noc"; 2214 reg = <0 0x0a0c0000 0 0xa180>; 2215 #interconnect-cells = <2>; 2216 qcom,bcm-voters = <&apps_bcm_voter>; 2217 }; 2218 2219 usb_1: usb@a6f8800 { 2220 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2221 reg = <0 0x0a6f8800 0 0x400>; 2222 status = "disabled"; 2223 #address-cells = <2>; 2224 #size-cells = <2>; 2225 ranges; 2226 2227 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2228 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2229 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2230 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2231 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2232 clock-names = "cfg_noc", 2233 "core", 2234 "iface", 2235 "sleep", 2236 "mock_utmi"; 2237 2238 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2239 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2240 assigned-clock-rates = <19200000>, <200000000>; 2241 2242 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2243 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2244 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2245 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2246 interrupt-names = "hs_phy_irq", 2247 "ss_phy_irq", 2248 "dm_hs_phy_irq", 2249 "dp_hs_phy_irq"; 2250 2251 power-domains = <&gcc USB30_PRIM_GDSC>; 2252 2253 resets = <&gcc GCC_USB30_PRIM_BCR>; 2254 2255 usb_1_dwc3: usb@a600000 { 2256 compatible = "snps,dwc3"; 2257 reg = <0 0x0a600000 0 0xcd00>; 2258 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2259 iommus = <&apps_smmu 0x0 0x0>; 2260 snps,dis_u2_susphy_quirk; 2261 snps,dis_enblslpm_quirk; 2262 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2263 phy-names = "usb2-phy", "usb3-phy"; 2264 }; 2265 }; 2266 2267 usb_2: usb@a8f8800 { 2268 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2269 reg = <0 0x0a8f8800 0 0x400>; 2270 status = "disabled"; 2271 #address-cells = <2>; 2272 #size-cells = <2>; 2273 ranges; 2274 2275 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2276 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2277 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2278 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2279 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2280 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2281 clock-names = "cfg_noc", 2282 "core", 2283 "iface", 2284 "sleep", 2285 "mock_utmi", 2286 "xo"; 2287 2288 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2289 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2290 assigned-clock-rates = <19200000>, <200000000>; 2291 2292 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2293 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2294 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2295 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2296 interrupt-names = "hs_phy_irq", 2297 "ss_phy_irq", 2298 "dm_hs_phy_irq", 2299 "dp_hs_phy_irq"; 2300 2301 power-domains = <&gcc USB30_SEC_GDSC>; 2302 2303 resets = <&gcc GCC_USB30_SEC_BCR>; 2304 2305 usb_2_dwc3: usb@a800000 { 2306 compatible = "snps,dwc3"; 2307 reg = <0 0x0a800000 0 0xcd00>; 2308 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2309 iommus = <&apps_smmu 0x20 0x0>; 2310 snps,dis_u2_susphy_quirk; 2311 snps,dis_enblslpm_quirk; 2312 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2313 phy-names = "usb2-phy", "usb3-phy"; 2314 }; 2315 }; 2316 2317 mdss: display-subsystem@ae00000 { 2318 compatible = "qcom,sm8350-mdss"; 2319 reg = <0 0x0ae00000 0 0x1000>; 2320 reg-names = "mdss"; 2321 2322 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2323 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2324 interconnect-names = "mdp0-mem", "mdp1-mem"; 2325 2326 power-domains = <&dispcc MDSS_GDSC>; 2327 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2328 2329 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2330 <&gcc GCC_DISP_HF_AXI_CLK>, 2331 <&gcc GCC_DISP_SF_AXI_CLK>, 2332 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2333 clock-names = "iface", "bus", "nrt_bus", "core"; 2334 2335 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2336 interrupt-controller; 2337 #interrupt-cells = <1>; 2338 2339 iommus = <&apps_smmu 0x820 0x402>; 2340 2341 status = "disabled"; 2342 2343 #address-cells = <2>; 2344 #size-cells = <2>; 2345 ranges; 2346 2347 dpu_opp_table: opp-table { 2348 compatible = "operating-points-v2"; 2349 2350 /* TODO: opp-200000000 should work with 2351 * &rpmhpd_opp_low_svs, but one some of 2352 * sm8350_hdk boards reboot using this 2353 * opp. 2354 */ 2355 opp-200000000 { 2356 opp-hz = /bits/ 64 <200000000>; 2357 required-opps = <&rpmhpd_opp_svs>; 2358 }; 2359 2360 opp-300000000 { 2361 opp-hz = /bits/ 64 <300000000>; 2362 required-opps = <&rpmhpd_opp_svs>; 2363 }; 2364 2365 opp-345000000 { 2366 opp-hz = /bits/ 64 <345000000>; 2367 required-opps = <&rpmhpd_opp_svs_l1>; 2368 }; 2369 2370 opp-460000000 { 2371 opp-hz = /bits/ 64 <460000000>; 2372 required-opps = <&rpmhpd_opp_nom>; 2373 }; 2374 }; 2375 2376 mdss_mdp: display-controller@ae01000 { 2377 compatible = "qcom,sm8350-dpu"; 2378 reg = <0 0x0ae01000 0 0x8f000>, 2379 <0 0x0aeb0000 0 0x2008>; 2380 reg-names = "mdp", "vbif"; 2381 2382 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2383 <&gcc GCC_DISP_SF_AXI_CLK>, 2384 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2385 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2386 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2387 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2388 clock-names = "bus", 2389 "nrt_bus", 2390 "iface", 2391 "lut", 2392 "core", 2393 "vsync"; 2394 2395 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2396 assigned-clock-rates = <19200000>; 2397 2398 operating-points-v2 = <&dpu_opp_table>; 2399 power-domains = <&rpmhpd SM8350_MMCX>; 2400 2401 interrupt-parent = <&mdss>; 2402 interrupts = <0>; 2403 2404 ports { 2405 #address-cells = <1>; 2406 #size-cells = <0>; 2407 2408 port@0 { 2409 reg = <0>; 2410 dpu_intf1_out: endpoint { 2411 remote-endpoint = <&mdss_dsi0_in>; 2412 }; 2413 }; 2414 2415 port@1 { 2416 reg = <1>; 2417 dpu_intf2_out: endpoint { 2418 remote-endpoint = <&mdss_dsi1_in>; 2419 }; 2420 }; 2421 }; 2422 }; 2423 2424 mdss_dsi0: dsi@ae94000 { 2425 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2426 reg = <0 0x0ae94000 0 0x400>; 2427 reg-names = "dsi_ctrl"; 2428 2429 interrupt-parent = <&mdss>; 2430 interrupts = <4>; 2431 2432 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2433 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2434 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2435 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2436 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2437 <&gcc GCC_DISP_HF_AXI_CLK>; 2438 clock-names = "byte", 2439 "byte_intf", 2440 "pixel", 2441 "core", 2442 "iface", 2443 "bus"; 2444 2445 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2446 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2447 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2448 <&mdss_dsi0_phy 1>; 2449 2450 operating-points-v2 = <&dsi0_opp_table>; 2451 power-domains = <&rpmhpd SM8350_MMCX>; 2452 2453 phys = <&mdss_dsi0_phy>; 2454 2455 #address-cells = <1>; 2456 #size-cells = <0>; 2457 2458 status = "disabled"; 2459 2460 dsi0_opp_table: opp-table { 2461 compatible = "operating-points-v2"; 2462 2463 /* TODO: opp-187500000 should work with 2464 * &rpmhpd_opp_low_svs, but one some of 2465 * sm8350_hdk boards reboot using this 2466 * opp. 2467 */ 2468 opp-187500000 { 2469 opp-hz = /bits/ 64 <187500000>; 2470 required-opps = <&rpmhpd_opp_svs>; 2471 }; 2472 2473 opp-300000000 { 2474 opp-hz = /bits/ 64 <300000000>; 2475 required-opps = <&rpmhpd_opp_svs>; 2476 }; 2477 2478 opp-358000000 { 2479 opp-hz = /bits/ 64 <358000000>; 2480 required-opps = <&rpmhpd_opp_svs_l1>; 2481 }; 2482 }; 2483 2484 ports { 2485 #address-cells = <1>; 2486 #size-cells = <0>; 2487 2488 port@0 { 2489 reg = <0>; 2490 mdss_dsi0_in: endpoint { 2491 remote-endpoint = <&dpu_intf1_out>; 2492 }; 2493 }; 2494 2495 port@1 { 2496 reg = <1>; 2497 mdss_dsi0_out: endpoint { 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 mdss_dsi0_phy: phy@ae94400 { 2504 compatible = "qcom,sm8350-dsi-phy-5nm"; 2505 reg = <0 0x0ae94400 0 0x200>, 2506 <0 0x0ae94600 0 0x280>, 2507 <0 0x0ae94900 0 0x27c>; 2508 reg-names = "dsi_phy", 2509 "dsi_phy_lane", 2510 "dsi_pll"; 2511 2512 #clock-cells = <1>; 2513 #phy-cells = <0>; 2514 2515 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2516 <&rpmhcc RPMH_CXO_CLK>; 2517 clock-names = "iface", "ref"; 2518 2519 status = "disabled"; 2520 }; 2521 2522 mdss_dsi1: dsi@ae96000 { 2523 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2524 reg = <0 0x0ae96000 0 0x400>; 2525 reg-names = "dsi_ctrl"; 2526 2527 interrupt-parent = <&mdss>; 2528 interrupts = <5>; 2529 2530 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2531 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2532 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2533 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2534 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2535 <&gcc GCC_DISP_HF_AXI_CLK>; 2536 clock-names = "byte", 2537 "byte_intf", 2538 "pixel", 2539 "core", 2540 "iface", 2541 "bus"; 2542 2543 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2544 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2545 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2546 <&mdss_dsi1_phy 1>; 2547 2548 operating-points-v2 = <&dsi1_opp_table>; 2549 power-domains = <&rpmhpd SM8350_MMCX>; 2550 2551 phys = <&mdss_dsi1_phy>; 2552 2553 #address-cells = <1>; 2554 #size-cells = <0>; 2555 2556 status = "disabled"; 2557 2558 dsi1_opp_table: opp-table { 2559 compatible = "operating-points-v2"; 2560 2561 /* TODO: opp-187500000 should work with 2562 * &rpmhpd_opp_low_svs, but one some of 2563 * sm8350_hdk boards reboot using this 2564 * opp. 2565 */ 2566 opp-187500000 { 2567 opp-hz = /bits/ 64 <187500000>; 2568 required-opps = <&rpmhpd_opp_svs>; 2569 }; 2570 2571 opp-300000000 { 2572 opp-hz = /bits/ 64 <300000000>; 2573 required-opps = <&rpmhpd_opp_svs>; 2574 }; 2575 2576 opp-358000000 { 2577 opp-hz = /bits/ 64 <358000000>; 2578 required-opps = <&rpmhpd_opp_svs_l1>; 2579 }; 2580 }; 2581 2582 ports { 2583 #address-cells = <1>; 2584 #size-cells = <0>; 2585 2586 port@0 { 2587 reg = <0>; 2588 mdss_dsi1_in: endpoint { 2589 remote-endpoint = <&dpu_intf2_out>; 2590 }; 2591 }; 2592 2593 port@1 { 2594 reg = <1>; 2595 mdss_dsi1_out: endpoint { 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 mdss_dsi1_phy: phy@ae96400 { 2602 compatible = "qcom,sm8350-dsi-phy-5nm"; 2603 reg = <0 0x0ae96400 0 0x200>, 2604 <0 0x0ae96600 0 0x280>, 2605 <0 0x0ae96900 0 0x27c>; 2606 reg-names = "dsi_phy", 2607 "dsi_phy_lane", 2608 "dsi_pll"; 2609 2610 #clock-cells = <1>; 2611 #phy-cells = <0>; 2612 2613 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2614 <&rpmhcc RPMH_CXO_CLK>; 2615 clock-names = "iface", "ref"; 2616 2617 status = "disabled"; 2618 }; 2619 }; 2620 2621 dispcc: clock-controller@af00000 { 2622 compatible = "qcom,sm8350-dispcc"; 2623 reg = <0 0x0af00000 0 0x10000>; 2624 clocks = <&rpmhcc RPMH_CXO_CLK>, 2625 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2626 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2627 <0>, 2628 <0>; 2629 clock-names = "bi_tcxo", 2630 "dsi0_phy_pll_out_byteclk", 2631 "dsi0_phy_pll_out_dsiclk", 2632 "dsi1_phy_pll_out_byteclk", 2633 "dsi1_phy_pll_out_dsiclk", 2634 "dp_phy_pll_link_clk", 2635 "dp_phy_pll_vco_div_clk"; 2636 #clock-cells = <1>; 2637 #reset-cells = <1>; 2638 #power-domain-cells = <1>; 2639 2640 power-domains = <&rpmhpd SM8350_MMCX>; 2641 }; 2642 2643 pdc: interrupt-controller@b220000 { 2644 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2645 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2646 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2647 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2648 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2649 <156 716 12>; 2650 #interrupt-cells = <2>; 2651 interrupt-parent = <&intc>; 2652 interrupt-controller; 2653 }; 2654 2655 tsens0: thermal-sensor@c263000 { 2656 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2657 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2658 <0 0x0c222000 0 0x8>; /* SROT */ 2659 #qcom,sensors = <15>; 2660 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2661 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2662 interrupt-names = "uplow", "critical"; 2663 #thermal-sensor-cells = <1>; 2664 }; 2665 2666 tsens1: thermal-sensor@c265000 { 2667 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2668 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2669 <0 0x0c223000 0 0x8>; /* SROT */ 2670 #qcom,sensors = <14>; 2671 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2672 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2673 interrupt-names = "uplow", "critical"; 2674 #thermal-sensor-cells = <1>; 2675 }; 2676 2677 aoss_qmp: power-management@c300000 { 2678 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2679 reg = <0 0x0c300000 0 0x400>; 2680 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2681 IRQ_TYPE_EDGE_RISING>; 2682 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2683 2684 #clock-cells = <0>; 2685 }; 2686 2687 sram@c3f0000 { 2688 compatible = "qcom,rpmh-stats"; 2689 reg = <0 0x0c3f0000 0 0x400>; 2690 }; 2691 2692 spmi_bus: spmi@c440000 { 2693 compatible = "qcom,spmi-pmic-arb"; 2694 reg = <0x0 0x0c440000 0x0 0x1100>, 2695 <0x0 0x0c600000 0x0 0x2000000>, 2696 <0x0 0x0e600000 0x0 0x100000>, 2697 <0x0 0x0e700000 0x0 0xa0000>, 2698 <0x0 0x0c40a000 0x0 0x26000>; 2699 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2700 interrupt-names = "periph_irq"; 2701 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2702 qcom,ee = <0>; 2703 qcom,channel = <0>; 2704 #address-cells = <2>; 2705 #size-cells = <0>; 2706 interrupt-controller; 2707 #interrupt-cells = <4>; 2708 }; 2709 2710 tlmm: pinctrl@f100000 { 2711 compatible = "qcom,sm8350-tlmm"; 2712 reg = <0 0x0f100000 0 0x300000>; 2713 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2714 gpio-controller; 2715 #gpio-cells = <2>; 2716 interrupt-controller; 2717 #interrupt-cells = <2>; 2718 gpio-ranges = <&tlmm 0 0 204>; 2719 wakeup-parent = <&pdc>; 2720 2721 sdc2_default_state: sdc2-default-state { 2722 clk-pins { 2723 pins = "sdc2_clk"; 2724 drive-strength = <16>; 2725 bias-disable; 2726 }; 2727 2728 cmd-pins { 2729 pins = "sdc2_cmd"; 2730 drive-strength = <16>; 2731 bias-pull-up; 2732 }; 2733 2734 data-pins { 2735 pins = "sdc2_data"; 2736 drive-strength = <16>; 2737 bias-pull-up; 2738 }; 2739 }; 2740 2741 sdc2_sleep_state: sdc2-sleep-state { 2742 clk-pins { 2743 pins = "sdc2_clk"; 2744 drive-strength = <2>; 2745 bias-disable; 2746 }; 2747 2748 cmd-pins { 2749 pins = "sdc2_cmd"; 2750 drive-strength = <2>; 2751 bias-pull-up; 2752 }; 2753 2754 data-pins { 2755 pins = "sdc2_data"; 2756 drive-strength = <2>; 2757 bias-pull-up; 2758 }; 2759 }; 2760 2761 qup_uart3_default_state: qup-uart3-default-state { 2762 rx-pins { 2763 pins = "gpio18"; 2764 function = "qup3"; 2765 }; 2766 tx-pins { 2767 pins = "gpio19"; 2768 function = "qup3"; 2769 }; 2770 }; 2771 2772 qup_uart6_default: qup-uart6-default-state { 2773 pins = "gpio30", "gpio31"; 2774 function = "qup6"; 2775 drive-strength = <2>; 2776 bias-disable; 2777 }; 2778 2779 qup_uart18_default: qup-uart18-default-state { 2780 pins = "gpio58", "gpio59"; 2781 function = "qup18"; 2782 drive-strength = <2>; 2783 bias-disable; 2784 }; 2785 2786 qup_i2c0_default: qup-i2c0-default-state { 2787 pins = "gpio4", "gpio5"; 2788 function = "qup0"; 2789 drive-strength = <2>; 2790 bias-pull-up; 2791 }; 2792 2793 qup_i2c1_default: qup-i2c1-default-state { 2794 pins = "gpio8", "gpio9"; 2795 function = "qup1"; 2796 drive-strength = <2>; 2797 bias-pull-up; 2798 }; 2799 2800 qup_i2c2_default: qup-i2c2-default-state { 2801 pins = "gpio12", "gpio13"; 2802 function = "qup2"; 2803 drive-strength = <2>; 2804 bias-pull-up; 2805 }; 2806 2807 qup_i2c4_default: qup-i2c4-default-state { 2808 pins = "gpio20", "gpio21"; 2809 function = "qup4"; 2810 drive-strength = <2>; 2811 bias-pull-up; 2812 }; 2813 2814 qup_i2c5_default: qup-i2c5-default-state { 2815 pins = "gpio24", "gpio25"; 2816 function = "qup5"; 2817 drive-strength = <2>; 2818 bias-pull-up; 2819 }; 2820 2821 qup_i2c6_default: qup-i2c6-default-state { 2822 pins = "gpio28", "gpio29"; 2823 function = "qup6"; 2824 drive-strength = <2>; 2825 bias-pull-up; 2826 }; 2827 2828 qup_i2c7_default: qup-i2c7-default-state { 2829 pins = "gpio32", "gpio33"; 2830 function = "qup7"; 2831 drive-strength = <2>; 2832 bias-disable; 2833 }; 2834 2835 qup_i2c8_default: qup-i2c8-default-state { 2836 pins = "gpio36", "gpio37"; 2837 function = "qup8"; 2838 drive-strength = <2>; 2839 bias-pull-up; 2840 }; 2841 2842 qup_i2c9_default: qup-i2c9-default-state { 2843 pins = "gpio40", "gpio41"; 2844 function = "qup9"; 2845 drive-strength = <2>; 2846 bias-pull-up; 2847 }; 2848 2849 qup_i2c10_default: qup-i2c10-default-state { 2850 pins = "gpio44", "gpio45"; 2851 function = "qup10"; 2852 drive-strength = <2>; 2853 bias-pull-up; 2854 }; 2855 2856 qup_i2c11_default: qup-i2c11-default-state { 2857 pins = "gpio48", "gpio49"; 2858 function = "qup11"; 2859 drive-strength = <2>; 2860 bias-pull-up; 2861 }; 2862 2863 qup_i2c12_default: qup-i2c12-default-state { 2864 pins = "gpio52", "gpio53"; 2865 function = "qup12"; 2866 drive-strength = <2>; 2867 bias-pull-up; 2868 }; 2869 2870 qup_i2c13_default: qup-i2c13-default-state { 2871 pins = "gpio0", "gpio1"; 2872 function = "qup13"; 2873 drive-strength = <2>; 2874 bias-pull-up; 2875 }; 2876 2877 qup_i2c14_default: qup-i2c14-default-state { 2878 pins = "gpio56", "gpio57"; 2879 function = "qup14"; 2880 drive-strength = <2>; 2881 bias-disable; 2882 }; 2883 2884 qup_i2c15_default: qup-i2c15-default-state { 2885 pins = "gpio60", "gpio61"; 2886 function = "qup15"; 2887 drive-strength = <2>; 2888 bias-disable; 2889 }; 2890 2891 qup_i2c16_default: qup-i2c16-default-state { 2892 pins = "gpio64", "gpio65"; 2893 function = "qup16"; 2894 drive-strength = <2>; 2895 bias-disable; 2896 }; 2897 2898 qup_i2c17_default: qup-i2c17-default-state { 2899 pins = "gpio72", "gpio73"; 2900 function = "qup17"; 2901 drive-strength = <2>; 2902 bias-disable; 2903 }; 2904 2905 qup_i2c19_default: qup-i2c19-default-state { 2906 pins = "gpio76", "gpio77"; 2907 function = "qup19"; 2908 drive-strength = <2>; 2909 bias-disable; 2910 }; 2911 }; 2912 2913 apps_smmu: iommu@15000000 { 2914 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 2915 reg = <0 0x15000000 0 0x100000>; 2916 #iommu-cells = <2>; 2917 #global-interrupts = <2>; 2918 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 2919 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2921 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2925 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2926 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2933 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2934 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2935 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2936 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2960 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2984 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2985 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2986 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2987 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2988 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2989 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2991 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2992 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2993 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2994 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2995 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2996 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2997 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2998 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2999 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3000 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3001 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3002 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3003 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3004 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3005 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3006 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3008 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3009 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3010 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3011 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3012 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3013 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3014 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3016 }; 3017 3018 adsp: remoteproc@17300000 { 3019 compatible = "qcom,sm8350-adsp-pas"; 3020 reg = <0 0x17300000 0 0x100>; 3021 3022 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3023 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3024 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3025 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3026 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3027 interrupt-names = "wdog", "fatal", "ready", 3028 "handover", "stop-ack"; 3029 3030 clocks = <&rpmhcc RPMH_CXO_CLK>; 3031 clock-names = "xo"; 3032 3033 power-domains = <&rpmhpd SM8350_LCX>, 3034 <&rpmhpd SM8350_LMX>; 3035 power-domain-names = "lcx", "lmx"; 3036 3037 memory-region = <&pil_adsp_mem>; 3038 3039 qcom,qmp = <&aoss_qmp>; 3040 3041 qcom,smem-states = <&smp2p_adsp_out 0>; 3042 qcom,smem-state-names = "stop"; 3043 3044 status = "disabled"; 3045 3046 glink-edge { 3047 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3048 IPCC_MPROC_SIGNAL_GLINK_QMP 3049 IRQ_TYPE_EDGE_RISING>; 3050 mboxes = <&ipcc IPCC_CLIENT_LPASS 3051 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3052 3053 label = "lpass"; 3054 qcom,remote-pid = <2>; 3055 3056 fastrpc { 3057 compatible = "qcom,fastrpc"; 3058 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3059 label = "adsp"; 3060 qcom,non-secure-domain; 3061 #address-cells = <1>; 3062 #size-cells = <0>; 3063 3064 compute-cb@3 { 3065 compatible = "qcom,fastrpc-compute-cb"; 3066 reg = <3>; 3067 iommus = <&apps_smmu 0x1803 0x0>; 3068 }; 3069 3070 compute-cb@4 { 3071 compatible = "qcom,fastrpc-compute-cb"; 3072 reg = <4>; 3073 iommus = <&apps_smmu 0x1804 0x0>; 3074 }; 3075 3076 compute-cb@5 { 3077 compatible = "qcom,fastrpc-compute-cb"; 3078 reg = <5>; 3079 iommus = <&apps_smmu 0x1805 0x0>; 3080 }; 3081 }; 3082 }; 3083 }; 3084 3085 intc: interrupt-controller@17a00000 { 3086 compatible = "arm,gic-v3"; 3087 #interrupt-cells = <3>; 3088 interrupt-controller; 3089 #redistributor-regions = <1>; 3090 redistributor-stride = <0 0x20000>; 3091 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3092 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3093 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3094 }; 3095 3096 timer@17c20000 { 3097 compatible = "arm,armv7-timer-mem"; 3098 #address-cells = <1>; 3099 #size-cells = <1>; 3100 ranges = <0 0 0 0x20000000>; 3101 reg = <0x0 0x17c20000 0x0 0x1000>; 3102 clock-frequency = <19200000>; 3103 3104 frame@17c21000 { 3105 frame-number = <0>; 3106 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3108 reg = <0x17c21000 0x1000>, 3109 <0x17c22000 0x1000>; 3110 }; 3111 3112 frame@17c23000 { 3113 frame-number = <1>; 3114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3115 reg = <0x17c23000 0x1000>; 3116 status = "disabled"; 3117 }; 3118 3119 frame@17c25000 { 3120 frame-number = <2>; 3121 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3122 reg = <0x17c25000 0x1000>; 3123 status = "disabled"; 3124 }; 3125 3126 frame@17c27000 { 3127 frame-number = <3>; 3128 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3129 reg = <0x17c27000 0x1000>; 3130 status = "disabled"; 3131 }; 3132 3133 frame@17c29000 { 3134 frame-number = <4>; 3135 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3136 reg = <0x17c29000 0x1000>; 3137 status = "disabled"; 3138 }; 3139 3140 frame@17c2b000 { 3141 frame-number = <5>; 3142 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3143 reg = <0x17c2b000 0x1000>; 3144 status = "disabled"; 3145 }; 3146 3147 frame@17c2d000 { 3148 frame-number = <6>; 3149 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3150 reg = <0x17c2d000 0x1000>; 3151 status = "disabled"; 3152 }; 3153 }; 3154 3155 apps_rsc: rsc@18200000 { 3156 label = "apps_rsc"; 3157 compatible = "qcom,rpmh-rsc"; 3158 reg = <0x0 0x18200000 0x0 0x10000>, 3159 <0x0 0x18210000 0x0 0x10000>, 3160 <0x0 0x18220000 0x0 0x10000>; 3161 reg-names = "drv-0", "drv-1", "drv-2"; 3162 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3165 qcom,tcs-offset = <0xd00>; 3166 qcom,drv-id = <2>; 3167 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3168 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3169 power-domains = <&CLUSTER_PD>; 3170 3171 rpmhcc: clock-controller { 3172 compatible = "qcom,sm8350-rpmh-clk"; 3173 #clock-cells = <1>; 3174 clock-names = "xo"; 3175 clocks = <&xo_board>; 3176 }; 3177 3178 rpmhpd: power-controller { 3179 compatible = "qcom,sm8350-rpmhpd"; 3180 #power-domain-cells = <1>; 3181 operating-points-v2 = <&rpmhpd_opp_table>; 3182 3183 rpmhpd_opp_table: opp-table { 3184 compatible = "operating-points-v2"; 3185 3186 rpmhpd_opp_ret: opp1 { 3187 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3188 }; 3189 3190 rpmhpd_opp_min_svs: opp2 { 3191 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3192 }; 3193 3194 rpmhpd_opp_low_svs: opp3 { 3195 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3196 }; 3197 3198 rpmhpd_opp_svs: opp4 { 3199 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3200 }; 3201 3202 rpmhpd_opp_svs_l1: opp5 { 3203 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3204 }; 3205 3206 rpmhpd_opp_nom: opp6 { 3207 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3208 }; 3209 3210 rpmhpd_opp_nom_l1: opp7 { 3211 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3212 }; 3213 3214 rpmhpd_opp_nom_l2: opp8 { 3215 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3216 }; 3217 3218 rpmhpd_opp_turbo: opp9 { 3219 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3220 }; 3221 3222 rpmhpd_opp_turbo_l1: opp10 { 3223 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3224 }; 3225 }; 3226 }; 3227 3228 apps_bcm_voter: bcm-voter { 3229 compatible = "qcom,bcm-voter"; 3230 }; 3231 }; 3232 3233 cpufreq_hw: cpufreq@18591000 { 3234 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3235 reg = <0 0x18591000 0 0x1000>, 3236 <0 0x18592000 0 0x1000>, 3237 <0 0x18593000 0 0x1000>; 3238 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3239 3240 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3241 clock-names = "xo", "alternate"; 3242 3243 #freq-domain-cells = <1>; 3244 }; 3245 3246 cdsp: remoteproc@98900000 { 3247 compatible = "qcom,sm8350-cdsp-pas"; 3248 reg = <0 0x98900000 0 0x1400000>; 3249 3250 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3251 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3252 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3253 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3254 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3255 interrupt-names = "wdog", "fatal", "ready", 3256 "handover", "stop-ack"; 3257 3258 clocks = <&rpmhcc RPMH_CXO_CLK>; 3259 clock-names = "xo"; 3260 3261 power-domains = <&rpmhpd SM8350_CX>, 3262 <&rpmhpd SM8350_MXC>; 3263 power-domain-names = "cx", "mxc"; 3264 3265 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3266 3267 memory-region = <&pil_cdsp_mem>; 3268 3269 qcom,qmp = <&aoss_qmp>; 3270 3271 qcom,smem-states = <&smp2p_cdsp_out 0>; 3272 qcom,smem-state-names = "stop"; 3273 3274 status = "disabled"; 3275 3276 glink-edge { 3277 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3278 IPCC_MPROC_SIGNAL_GLINK_QMP 3279 IRQ_TYPE_EDGE_RISING>; 3280 mboxes = <&ipcc IPCC_CLIENT_CDSP 3281 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3282 3283 label = "cdsp"; 3284 qcom,remote-pid = <5>; 3285 3286 fastrpc { 3287 compatible = "qcom,fastrpc"; 3288 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3289 label = "cdsp"; 3290 qcom,non-secure-domain; 3291 #address-cells = <1>; 3292 #size-cells = <0>; 3293 3294 compute-cb@1 { 3295 compatible = "qcom,fastrpc-compute-cb"; 3296 reg = <1>; 3297 iommus = <&apps_smmu 0x2161 0x0400>, 3298 <&apps_smmu 0x1181 0x0420>; 3299 }; 3300 3301 compute-cb@2 { 3302 compatible = "qcom,fastrpc-compute-cb"; 3303 reg = <2>; 3304 iommus = <&apps_smmu 0x2162 0x0400>, 3305 <&apps_smmu 0x1182 0x0420>; 3306 }; 3307 3308 compute-cb@3 { 3309 compatible = "qcom,fastrpc-compute-cb"; 3310 reg = <3>; 3311 iommus = <&apps_smmu 0x2163 0x0400>, 3312 <&apps_smmu 0x1183 0x0420>; 3313 }; 3314 3315 compute-cb@4 { 3316 compatible = "qcom,fastrpc-compute-cb"; 3317 reg = <4>; 3318 iommus = <&apps_smmu 0x2164 0x0400>, 3319 <&apps_smmu 0x1184 0x0420>; 3320 }; 3321 3322 compute-cb@5 { 3323 compatible = "qcom,fastrpc-compute-cb"; 3324 reg = <5>; 3325 iommus = <&apps_smmu 0x2165 0x0400>, 3326 <&apps_smmu 0x1185 0x0420>; 3327 }; 3328 3329 compute-cb@6 { 3330 compatible = "qcom,fastrpc-compute-cb"; 3331 reg = <6>; 3332 iommus = <&apps_smmu 0x2166 0x0400>, 3333 <&apps_smmu 0x1186 0x0420>; 3334 }; 3335 3336 compute-cb@7 { 3337 compatible = "qcom,fastrpc-compute-cb"; 3338 reg = <7>; 3339 iommus = <&apps_smmu 0x2167 0x0400>, 3340 <&apps_smmu 0x1187 0x0420>; 3341 }; 3342 3343 compute-cb@8 { 3344 compatible = "qcom,fastrpc-compute-cb"; 3345 reg = <8>; 3346 iommus = <&apps_smmu 0x2168 0x0400>, 3347 <&apps_smmu 0x1188 0x0420>; 3348 }; 3349 3350 /* note: secure cb9 in downstream */ 3351 }; 3352 }; 3353 }; 3354 }; 3355 3356 thermal_zones: thermal-zones { 3357 cpu0-thermal { 3358 polling-delay-passive = <250>; 3359 polling-delay = <1000>; 3360 3361 thermal-sensors = <&tsens0 1>; 3362 3363 trips { 3364 cpu0_alert0: trip-point0 { 3365 temperature = <90000>; 3366 hysteresis = <2000>; 3367 type = "passive"; 3368 }; 3369 3370 cpu0_alert1: trip-point1 { 3371 temperature = <95000>; 3372 hysteresis = <2000>; 3373 type = "passive"; 3374 }; 3375 3376 cpu0_crit: cpu-crit { 3377 temperature = <110000>; 3378 hysteresis = <1000>; 3379 type = "critical"; 3380 }; 3381 }; 3382 3383 cooling-maps { 3384 map0 { 3385 trip = <&cpu0_alert0>; 3386 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3387 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3388 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3389 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3390 }; 3391 map1 { 3392 trip = <&cpu0_alert1>; 3393 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3394 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3395 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3396 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3397 }; 3398 }; 3399 }; 3400 3401 cpu1-thermal { 3402 polling-delay-passive = <250>; 3403 polling-delay = <1000>; 3404 3405 thermal-sensors = <&tsens0 2>; 3406 3407 trips { 3408 cpu1_alert0: trip-point0 { 3409 temperature = <90000>; 3410 hysteresis = <2000>; 3411 type = "passive"; 3412 }; 3413 3414 cpu1_alert1: trip-point1 { 3415 temperature = <95000>; 3416 hysteresis = <2000>; 3417 type = "passive"; 3418 }; 3419 3420 cpu1_crit: cpu-crit { 3421 temperature = <110000>; 3422 hysteresis = <1000>; 3423 type = "critical"; 3424 }; 3425 }; 3426 3427 cooling-maps { 3428 map0 { 3429 trip = <&cpu1_alert0>; 3430 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3431 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3432 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3433 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3434 }; 3435 map1 { 3436 trip = <&cpu1_alert1>; 3437 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3438 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3439 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3440 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3441 }; 3442 }; 3443 }; 3444 3445 cpu2-thermal { 3446 polling-delay-passive = <250>; 3447 polling-delay = <1000>; 3448 3449 thermal-sensors = <&tsens0 3>; 3450 3451 trips { 3452 cpu2_alert0: trip-point0 { 3453 temperature = <90000>; 3454 hysteresis = <2000>; 3455 type = "passive"; 3456 }; 3457 3458 cpu2_alert1: trip-point1 { 3459 temperature = <95000>; 3460 hysteresis = <2000>; 3461 type = "passive"; 3462 }; 3463 3464 cpu2_crit: cpu-crit { 3465 temperature = <110000>; 3466 hysteresis = <1000>; 3467 type = "critical"; 3468 }; 3469 }; 3470 3471 cooling-maps { 3472 map0 { 3473 trip = <&cpu2_alert0>; 3474 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3475 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3476 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3477 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3478 }; 3479 map1 { 3480 trip = <&cpu2_alert1>; 3481 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3482 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3483 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3484 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3485 }; 3486 }; 3487 }; 3488 3489 cpu3-thermal { 3490 polling-delay-passive = <250>; 3491 polling-delay = <1000>; 3492 3493 thermal-sensors = <&tsens0 4>; 3494 3495 trips { 3496 cpu3_alert0: trip-point0 { 3497 temperature = <90000>; 3498 hysteresis = <2000>; 3499 type = "passive"; 3500 }; 3501 3502 cpu3_alert1: trip-point1 { 3503 temperature = <95000>; 3504 hysteresis = <2000>; 3505 type = "passive"; 3506 }; 3507 3508 cpu3_crit: cpu-crit { 3509 temperature = <110000>; 3510 hysteresis = <1000>; 3511 type = "critical"; 3512 }; 3513 }; 3514 3515 cooling-maps { 3516 map0 { 3517 trip = <&cpu3_alert0>; 3518 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3519 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3520 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3521 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3522 }; 3523 map1 { 3524 trip = <&cpu3_alert1>; 3525 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3526 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3527 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3528 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3529 }; 3530 }; 3531 }; 3532 3533 cpu4-top-thermal { 3534 polling-delay-passive = <250>; 3535 polling-delay = <1000>; 3536 3537 thermal-sensors = <&tsens0 7>; 3538 3539 trips { 3540 cpu4_top_alert0: trip-point0 { 3541 temperature = <90000>; 3542 hysteresis = <2000>; 3543 type = "passive"; 3544 }; 3545 3546 cpu4_top_alert1: trip-point1 { 3547 temperature = <95000>; 3548 hysteresis = <2000>; 3549 type = "passive"; 3550 }; 3551 3552 cpu4_top_crit: cpu-crit { 3553 temperature = <110000>; 3554 hysteresis = <1000>; 3555 type = "critical"; 3556 }; 3557 }; 3558 3559 cooling-maps { 3560 map0 { 3561 trip = <&cpu4_top_alert0>; 3562 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3563 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3564 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3565 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3566 }; 3567 map1 { 3568 trip = <&cpu4_top_alert1>; 3569 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3570 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3571 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3572 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3573 }; 3574 }; 3575 }; 3576 3577 cpu5-top-thermal { 3578 polling-delay-passive = <250>; 3579 polling-delay = <1000>; 3580 3581 thermal-sensors = <&tsens0 8>; 3582 3583 trips { 3584 cpu5_top_alert0: trip-point0 { 3585 temperature = <90000>; 3586 hysteresis = <2000>; 3587 type = "passive"; 3588 }; 3589 3590 cpu5_top_alert1: trip-point1 { 3591 temperature = <95000>; 3592 hysteresis = <2000>; 3593 type = "passive"; 3594 }; 3595 3596 cpu5_top_crit: cpu-crit { 3597 temperature = <110000>; 3598 hysteresis = <1000>; 3599 type = "critical"; 3600 }; 3601 }; 3602 3603 cooling-maps { 3604 map0 { 3605 trip = <&cpu5_top_alert0>; 3606 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3607 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3608 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3609 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3610 }; 3611 map1 { 3612 trip = <&cpu5_top_alert1>; 3613 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3614 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3615 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3616 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3617 }; 3618 }; 3619 }; 3620 3621 cpu6-top-thermal { 3622 polling-delay-passive = <250>; 3623 polling-delay = <1000>; 3624 3625 thermal-sensors = <&tsens0 9>; 3626 3627 trips { 3628 cpu6_top_alert0: trip-point0 { 3629 temperature = <90000>; 3630 hysteresis = <2000>; 3631 type = "passive"; 3632 }; 3633 3634 cpu6_top_alert1: trip-point1 { 3635 temperature = <95000>; 3636 hysteresis = <2000>; 3637 type = "passive"; 3638 }; 3639 3640 cpu6_top_crit: cpu-crit { 3641 temperature = <110000>; 3642 hysteresis = <1000>; 3643 type = "critical"; 3644 }; 3645 }; 3646 3647 cooling-maps { 3648 map0 { 3649 trip = <&cpu6_top_alert0>; 3650 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3651 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3652 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3653 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3654 }; 3655 map1 { 3656 trip = <&cpu6_top_alert1>; 3657 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3658 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3659 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3660 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3661 }; 3662 }; 3663 }; 3664 3665 cpu7-top-thermal { 3666 polling-delay-passive = <250>; 3667 polling-delay = <1000>; 3668 3669 thermal-sensors = <&tsens0 10>; 3670 3671 trips { 3672 cpu7_top_alert0: trip-point0 { 3673 temperature = <90000>; 3674 hysteresis = <2000>; 3675 type = "passive"; 3676 }; 3677 3678 cpu7_top_alert1: trip-point1 { 3679 temperature = <95000>; 3680 hysteresis = <2000>; 3681 type = "passive"; 3682 }; 3683 3684 cpu7_top_crit: cpu-crit { 3685 temperature = <110000>; 3686 hysteresis = <1000>; 3687 type = "critical"; 3688 }; 3689 }; 3690 3691 cooling-maps { 3692 map0 { 3693 trip = <&cpu7_top_alert0>; 3694 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3695 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3698 }; 3699 map1 { 3700 trip = <&cpu7_top_alert1>; 3701 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3702 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3703 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3705 }; 3706 }; 3707 }; 3708 3709 cpu4-bottom-thermal { 3710 polling-delay-passive = <250>; 3711 polling-delay = <1000>; 3712 3713 thermal-sensors = <&tsens0 11>; 3714 3715 trips { 3716 cpu4_bottom_alert0: trip-point0 { 3717 temperature = <90000>; 3718 hysteresis = <2000>; 3719 type = "passive"; 3720 }; 3721 3722 cpu4_bottom_alert1: trip-point1 { 3723 temperature = <95000>; 3724 hysteresis = <2000>; 3725 type = "passive"; 3726 }; 3727 3728 cpu4_bottom_crit: cpu-crit { 3729 temperature = <110000>; 3730 hysteresis = <1000>; 3731 type = "critical"; 3732 }; 3733 }; 3734 3735 cooling-maps { 3736 map0 { 3737 trip = <&cpu4_bottom_alert0>; 3738 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3742 }; 3743 map1 { 3744 trip = <&cpu4_bottom_alert1>; 3745 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3749 }; 3750 }; 3751 }; 3752 3753 cpu5-bottom-thermal { 3754 polling-delay-passive = <250>; 3755 polling-delay = <1000>; 3756 3757 thermal-sensors = <&tsens0 12>; 3758 3759 trips { 3760 cpu5_bottom_alert0: trip-point0 { 3761 temperature = <90000>; 3762 hysteresis = <2000>; 3763 type = "passive"; 3764 }; 3765 3766 cpu5_bottom_alert1: trip-point1 { 3767 temperature = <95000>; 3768 hysteresis = <2000>; 3769 type = "passive"; 3770 }; 3771 3772 cpu5_bottom_crit: cpu-crit { 3773 temperature = <110000>; 3774 hysteresis = <1000>; 3775 type = "critical"; 3776 }; 3777 }; 3778 3779 cooling-maps { 3780 map0 { 3781 trip = <&cpu5_bottom_alert0>; 3782 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3786 }; 3787 map1 { 3788 trip = <&cpu5_bottom_alert1>; 3789 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3790 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3793 }; 3794 }; 3795 }; 3796 3797 cpu6-bottom-thermal { 3798 polling-delay-passive = <250>; 3799 polling-delay = <1000>; 3800 3801 thermal-sensors = <&tsens0 13>; 3802 3803 trips { 3804 cpu6_bottom_alert0: trip-point0 { 3805 temperature = <90000>; 3806 hysteresis = <2000>; 3807 type = "passive"; 3808 }; 3809 3810 cpu6_bottom_alert1: trip-point1 { 3811 temperature = <95000>; 3812 hysteresis = <2000>; 3813 type = "passive"; 3814 }; 3815 3816 cpu6_bottom_crit: cpu-crit { 3817 temperature = <110000>; 3818 hysteresis = <1000>; 3819 type = "critical"; 3820 }; 3821 }; 3822 3823 cooling-maps { 3824 map0 { 3825 trip = <&cpu6_bottom_alert0>; 3826 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3830 }; 3831 map1 { 3832 trip = <&cpu6_bottom_alert1>; 3833 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3837 }; 3838 }; 3839 }; 3840 3841 cpu7-bottom-thermal { 3842 polling-delay-passive = <250>; 3843 polling-delay = <1000>; 3844 3845 thermal-sensors = <&tsens0 14>; 3846 3847 trips { 3848 cpu7_bottom_alert0: trip-point0 { 3849 temperature = <90000>; 3850 hysteresis = <2000>; 3851 type = "passive"; 3852 }; 3853 3854 cpu7_bottom_alert1: trip-point1 { 3855 temperature = <95000>; 3856 hysteresis = <2000>; 3857 type = "passive"; 3858 }; 3859 3860 cpu7_bottom_crit: cpu-crit { 3861 temperature = <110000>; 3862 hysteresis = <1000>; 3863 type = "critical"; 3864 }; 3865 }; 3866 3867 cooling-maps { 3868 map0 { 3869 trip = <&cpu7_bottom_alert0>; 3870 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3874 }; 3875 map1 { 3876 trip = <&cpu7_bottom_alert1>; 3877 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3881 }; 3882 }; 3883 }; 3884 3885 aoss0-thermal { 3886 polling-delay-passive = <250>; 3887 polling-delay = <1000>; 3888 3889 thermal-sensors = <&tsens0 0>; 3890 3891 trips { 3892 aoss0_alert0: trip-point0 { 3893 temperature = <90000>; 3894 hysteresis = <2000>; 3895 type = "hot"; 3896 }; 3897 }; 3898 }; 3899 3900 cluster0-thermal { 3901 polling-delay-passive = <250>; 3902 polling-delay = <1000>; 3903 3904 thermal-sensors = <&tsens0 5>; 3905 3906 trips { 3907 cluster0_alert0: trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "hot"; 3911 }; 3912 cluster0_crit: cluster0_crit { 3913 temperature = <110000>; 3914 hysteresis = <2000>; 3915 type = "critical"; 3916 }; 3917 }; 3918 }; 3919 3920 cluster1-thermal { 3921 polling-delay-passive = <250>; 3922 polling-delay = <1000>; 3923 3924 thermal-sensors = <&tsens0 6>; 3925 3926 trips { 3927 cluster1_alert0: trip-point0 { 3928 temperature = <90000>; 3929 hysteresis = <2000>; 3930 type = "hot"; 3931 }; 3932 cluster1_crit: cluster1_crit { 3933 temperature = <110000>; 3934 hysteresis = <2000>; 3935 type = "critical"; 3936 }; 3937 }; 3938 }; 3939 3940 aoss1-thermal { 3941 polling-delay-passive = <250>; 3942 polling-delay = <1000>; 3943 3944 thermal-sensors = <&tsens1 0>; 3945 3946 trips { 3947 aoss1_alert0: trip-point0 { 3948 temperature = <90000>; 3949 hysteresis = <2000>; 3950 type = "hot"; 3951 }; 3952 }; 3953 }; 3954 3955 gpu-top-thermal { 3956 polling-delay-passive = <250>; 3957 polling-delay = <1000>; 3958 3959 thermal-sensors = <&tsens1 1>; 3960 3961 trips { 3962 gpu1_alert0: trip-point0 { 3963 temperature = <90000>; 3964 hysteresis = <1000>; 3965 type = "hot"; 3966 }; 3967 }; 3968 }; 3969 3970 gpu-bottom-thermal { 3971 polling-delay-passive = <250>; 3972 polling-delay = <1000>; 3973 3974 thermal-sensors = <&tsens1 2>; 3975 3976 trips { 3977 gpu2_alert0: trip-point0 { 3978 temperature = <90000>; 3979 hysteresis = <1000>; 3980 type = "hot"; 3981 }; 3982 }; 3983 }; 3984 3985 nspss1-thermal { 3986 polling-delay-passive = <250>; 3987 polling-delay = <1000>; 3988 3989 thermal-sensors = <&tsens1 3>; 3990 3991 trips { 3992 nspss1_alert0: trip-point0 { 3993 temperature = <90000>; 3994 hysteresis = <1000>; 3995 type = "hot"; 3996 }; 3997 }; 3998 }; 3999 4000 nspss2-thermal { 4001 polling-delay-passive = <250>; 4002 polling-delay = <1000>; 4003 4004 thermal-sensors = <&tsens1 4>; 4005 4006 trips { 4007 nspss2_alert0: trip-point0 { 4008 temperature = <90000>; 4009 hysteresis = <1000>; 4010 type = "hot"; 4011 }; 4012 }; 4013 }; 4014 4015 nspss3-thermal { 4016 polling-delay-passive = <250>; 4017 polling-delay = <1000>; 4018 4019 thermal-sensors = <&tsens1 5>; 4020 4021 trips { 4022 nspss3_alert0: trip-point0 { 4023 temperature = <90000>; 4024 hysteresis = <1000>; 4025 type = "hot"; 4026 }; 4027 }; 4028 }; 4029 4030 video-thermal { 4031 polling-delay-passive = <250>; 4032 polling-delay = <1000>; 4033 4034 thermal-sensors = <&tsens1 6>; 4035 4036 trips { 4037 video_alert0: trip-point0 { 4038 temperature = <90000>; 4039 hysteresis = <2000>; 4040 type = "hot"; 4041 }; 4042 }; 4043 }; 4044 4045 mem-thermal { 4046 polling-delay-passive = <250>; 4047 polling-delay = <1000>; 4048 4049 thermal-sensors = <&tsens1 7>; 4050 4051 trips { 4052 mem_alert0: trip-point0 { 4053 temperature = <90000>; 4054 hysteresis = <2000>; 4055 type = "hot"; 4056 }; 4057 }; 4058 }; 4059 4060 modem1-top-thermal { 4061 polling-delay-passive = <250>; 4062 polling-delay = <1000>; 4063 4064 thermal-sensors = <&tsens1 8>; 4065 4066 trips { 4067 modem1_alert0: trip-point0 { 4068 temperature = <90000>; 4069 hysteresis = <2000>; 4070 type = "hot"; 4071 }; 4072 }; 4073 }; 4074 4075 modem2-top-thermal { 4076 polling-delay-passive = <250>; 4077 polling-delay = <1000>; 4078 4079 thermal-sensors = <&tsens1 9>; 4080 4081 trips { 4082 modem2_alert0: trip-point0 { 4083 temperature = <90000>; 4084 hysteresis = <2000>; 4085 type = "hot"; 4086 }; 4087 }; 4088 }; 4089 4090 modem3-top-thermal { 4091 polling-delay-passive = <250>; 4092 polling-delay = <1000>; 4093 4094 thermal-sensors = <&tsens1 10>; 4095 4096 trips { 4097 modem3_alert0: trip-point0 { 4098 temperature = <90000>; 4099 hysteresis = <2000>; 4100 type = "hot"; 4101 }; 4102 }; 4103 }; 4104 4105 modem4-top-thermal { 4106 polling-delay-passive = <250>; 4107 polling-delay = <1000>; 4108 4109 thermal-sensors = <&tsens1 11>; 4110 4111 trips { 4112 modem4_alert0: trip-point0 { 4113 temperature = <90000>; 4114 hysteresis = <2000>; 4115 type = "hot"; 4116 }; 4117 }; 4118 }; 4119 4120 camera-top-thermal { 4121 polling-delay-passive = <250>; 4122 polling-delay = <1000>; 4123 4124 thermal-sensors = <&tsens1 12>; 4125 4126 trips { 4127 camera1_alert0: trip-point0 { 4128 temperature = <90000>; 4129 hysteresis = <2000>; 4130 type = "hot"; 4131 }; 4132 }; 4133 }; 4134 4135 cam-bottom-thermal { 4136 polling-delay-passive = <250>; 4137 polling-delay = <1000>; 4138 4139 thermal-sensors = <&tsens1 13>; 4140 4141 trips { 4142 camera2_alert0: trip-point0 { 4143 temperature = <90000>; 4144 hysteresis = <2000>; 4145 type = "hot"; 4146 }; 4147 }; 4148 }; 4149 }; 4150 4151 timer { 4152 compatible = "arm,armv8-timer"; 4153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4157 }; 4158}; 4159