1b7e8f433SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2b7e8f433SVinod Koul/* 34f23d2a5SVinod Koul * Copyright (c) 2020, Linaro Limited 4b7e8f433SVinod Koul */ 5b7e8f433SVinod Koul 6d4a44105SRobert Foss#include <dt-bindings/interconnect/qcom,sm8350.h> 7b7e8f433SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 89fd4887cSRobert Foss#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 96d91e201SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8350.h> 1054af0cebSDmitry Baryshkov#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11b7e8f433SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12bc08fbf4SBjorn Andersson#include <dt-bindings/dma/qcom-gpi.h> 13f0360a7cSKonrad Dybcio#include <dt-bindings/gpio/gpio.h> 1484c856d0SVinod Koul#include <dt-bindings/interconnect/qcom,sm8350.h> 15b7e8f433SVinod Koul#include <dt-bindings/mailbox/qcom-ipcc.h> 162458a305SNeil Armstrong#include <dt-bindings/phy/phy-qcom-qmp.h> 17b7e8f433SVinod Koul#include <dt-bindings/power/qcom-rpmpd.h> 18b7e8f433SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1920f9d94eSRobert Foss#include <dt-bindings/thermal/thermal.h> 20f11d3e7dSAlex Elder#include <dt-bindings/interconnect/qcom,sm8350.h> 21b7e8f433SVinod Koul 22b7e8f433SVinod Koul/ { 23b7e8f433SVinod Koul interrupt-parent = <&intc>; 24b7e8f433SVinod Koul 25b7e8f433SVinod Koul #address-cells = <2>; 26b7e8f433SVinod Koul #size-cells = <2>; 27b7e8f433SVinod Koul 28b7e8f433SVinod Koul chosen { }; 29b7e8f433SVinod Koul 30b7e8f433SVinod Koul clocks { 31b7e8f433SVinod Koul xo_board: xo-board { 32b7e8f433SVinod Koul compatible = "fixed-clock"; 33b7e8f433SVinod Koul #clock-cells = <0>; 34b7e8f433SVinod Koul clock-frequency = <38400000>; 35b7e8f433SVinod Koul clock-output-names = "xo_board"; 36b7e8f433SVinod Koul }; 37b7e8f433SVinod Koul 38b7e8f433SVinod Koul sleep_clk: sleep-clk { 39b7e8f433SVinod Koul compatible = "fixed-clock"; 40b7e8f433SVinod Koul clock-frequency = <32000>; 41b7e8f433SVinod Koul #clock-cells = <0>; 42b7e8f433SVinod Koul }; 43b7e8f433SVinod Koul }; 44b7e8f433SVinod Koul 45b7e8f433SVinod Koul cpus { 46b7e8f433SVinod Koul #address-cells = <2>; 47b7e8f433SVinod Koul #size-cells = <0>; 48b7e8f433SVinod Koul 49b7e8f433SVinod Koul CPU0: cpu@0 { 50b7e8f433SVinod Koul device_type = "cpu"; 51b7e8f433SVinod Koul compatible = "qcom,kryo685"; 52b7e8f433SVinod Koul reg = <0x0 0x0>; 53c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 54b7e8f433SVinod Koul enable-method = "psci"; 55b7e8f433SVinod Koul next-level-cache = <&L2_0>; 56ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 5707ddb302SBjorn Andersson power-domains = <&CPU_PD0>; 5807ddb302SBjorn Andersson power-domain-names = "psci"; 5920f9d94eSRobert Foss #cooling-cells = <2>; 60b7e8f433SVinod Koul L2_0: l2-cache { 61b7e8f433SVinod Koul compatible = "cache"; 629435294cSPierre Gondois cache-level = <2>; 63b7e8f433SVinod Koul next-level-cache = <&L3_0>; 64b7e8f433SVinod Koul L3_0: l3-cache { 65b7e8f433SVinod Koul compatible = "cache"; 669435294cSPierre Gondois cache-level = <3>; 67b7e8f433SVinod Koul }; 68b7e8f433SVinod Koul }; 69b7e8f433SVinod Koul }; 70b7e8f433SVinod Koul 71b7e8f433SVinod Koul CPU1: cpu@100 { 72b7e8f433SVinod Koul device_type = "cpu"; 73b7e8f433SVinod Koul compatible = "qcom,kryo685"; 74b7e8f433SVinod Koul reg = <0x0 0x100>; 75c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 76b7e8f433SVinod Koul enable-method = "psci"; 77b7e8f433SVinod Koul next-level-cache = <&L2_100>; 78ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 7907ddb302SBjorn Andersson power-domains = <&CPU_PD1>; 8007ddb302SBjorn Andersson power-domain-names = "psci"; 8120f9d94eSRobert Foss #cooling-cells = <2>; 82b7e8f433SVinod Koul L2_100: l2-cache { 83b7e8f433SVinod Koul compatible = "cache"; 849435294cSPierre Gondois cache-level = <2>; 85b7e8f433SVinod Koul next-level-cache = <&L3_0>; 86b7e8f433SVinod Koul }; 87b7e8f433SVinod Koul }; 88b7e8f433SVinod Koul 89b7e8f433SVinod Koul CPU2: cpu@200 { 90b7e8f433SVinod Koul device_type = "cpu"; 91b7e8f433SVinod Koul compatible = "qcom,kryo685"; 92b7e8f433SVinod Koul reg = <0x0 0x200>; 93c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 94b7e8f433SVinod Koul enable-method = "psci"; 95b7e8f433SVinod Koul next-level-cache = <&L2_200>; 96ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 9707ddb302SBjorn Andersson power-domains = <&CPU_PD2>; 9807ddb302SBjorn Andersson power-domain-names = "psci"; 9920f9d94eSRobert Foss #cooling-cells = <2>; 100b7e8f433SVinod Koul L2_200: l2-cache { 101b7e8f433SVinod Koul compatible = "cache"; 1029435294cSPierre Gondois cache-level = <2>; 103b7e8f433SVinod Koul next-level-cache = <&L3_0>; 104b7e8f433SVinod Koul }; 105b7e8f433SVinod Koul }; 106b7e8f433SVinod Koul 107b7e8f433SVinod Koul CPU3: cpu@300 { 108b7e8f433SVinod Koul device_type = "cpu"; 109b7e8f433SVinod Koul compatible = "qcom,kryo685"; 110b7e8f433SVinod Koul reg = <0x0 0x300>; 111c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 112b7e8f433SVinod Koul enable-method = "psci"; 113b7e8f433SVinod Koul next-level-cache = <&L2_300>; 114ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 11507ddb302SBjorn Andersson power-domains = <&CPU_PD3>; 11607ddb302SBjorn Andersson power-domain-names = "psci"; 11720f9d94eSRobert Foss #cooling-cells = <2>; 118b7e8f433SVinod Koul L2_300: l2-cache { 119b7e8f433SVinod Koul compatible = "cache"; 1209435294cSPierre Gondois cache-level = <2>; 121b7e8f433SVinod Koul next-level-cache = <&L3_0>; 122b7e8f433SVinod Koul }; 123b7e8f433SVinod Koul }; 124b7e8f433SVinod Koul 125b7e8f433SVinod Koul CPU4: cpu@400 { 126b7e8f433SVinod Koul device_type = "cpu"; 127b7e8f433SVinod Koul compatible = "qcom,kryo685"; 128b7e8f433SVinod Koul reg = <0x0 0x400>; 129c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 130b7e8f433SVinod Koul enable-method = "psci"; 131b7e8f433SVinod Koul next-level-cache = <&L2_400>; 132ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 1>; 13307ddb302SBjorn Andersson power-domains = <&CPU_PD4>; 13407ddb302SBjorn Andersson power-domain-names = "psci"; 13520f9d94eSRobert Foss #cooling-cells = <2>; 136b7e8f433SVinod Koul L2_400: l2-cache { 137b7e8f433SVinod Koul compatible = "cache"; 1389435294cSPierre Gondois cache-level = <2>; 139b7e8f433SVinod Koul next-level-cache = <&L3_0>; 140b7e8f433SVinod Koul }; 141b7e8f433SVinod Koul }; 142b7e8f433SVinod Koul 143b7e8f433SVinod Koul CPU5: cpu@500 { 144b7e8f433SVinod Koul device_type = "cpu"; 145b7e8f433SVinod Koul compatible = "qcom,kryo685"; 146b7e8f433SVinod Koul reg = <0x0 0x500>; 147c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 148b7e8f433SVinod Koul enable-method = "psci"; 149b7e8f433SVinod Koul next-level-cache = <&L2_500>; 150ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 1>; 15107ddb302SBjorn Andersson power-domains = <&CPU_PD5>; 15207ddb302SBjorn Andersson power-domain-names = "psci"; 15320f9d94eSRobert Foss #cooling-cells = <2>; 154b7e8f433SVinod Koul L2_500: l2-cache { 155b7e8f433SVinod Koul compatible = "cache"; 1569435294cSPierre Gondois cache-level = <2>; 157b7e8f433SVinod Koul next-level-cache = <&L3_0>; 158b7e8f433SVinod Koul }; 159b7e8f433SVinod Koul }; 160b7e8f433SVinod Koul 161b7e8f433SVinod Koul CPU6: cpu@600 { 162b7e8f433SVinod Koul device_type = "cpu"; 163b7e8f433SVinod Koul compatible = "qcom,kryo685"; 164b7e8f433SVinod Koul reg = <0x0 0x600>; 165c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 166b7e8f433SVinod Koul enable-method = "psci"; 167b7e8f433SVinod Koul next-level-cache = <&L2_600>; 168ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 1>; 16907ddb302SBjorn Andersson power-domains = <&CPU_PD6>; 17007ddb302SBjorn Andersson power-domain-names = "psci"; 17120f9d94eSRobert Foss #cooling-cells = <2>; 172b7e8f433SVinod Koul L2_600: l2-cache { 173b7e8f433SVinod Koul compatible = "cache"; 1749435294cSPierre Gondois cache-level = <2>; 175b7e8f433SVinod Koul next-level-cache = <&L3_0>; 176b7e8f433SVinod Koul }; 177b7e8f433SVinod Koul }; 178b7e8f433SVinod Koul 179b7e8f433SVinod Koul CPU7: cpu@700 { 180b7e8f433SVinod Koul device_type = "cpu"; 181b7e8f433SVinod Koul compatible = "qcom,kryo685"; 182b7e8f433SVinod Koul reg = <0x0 0x700>; 183c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 2>; 184b7e8f433SVinod Koul enable-method = "psci"; 185b7e8f433SVinod Koul next-level-cache = <&L2_700>; 186ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 2>; 18707ddb302SBjorn Andersson power-domains = <&CPU_PD7>; 18807ddb302SBjorn Andersson power-domain-names = "psci"; 18920f9d94eSRobert Foss #cooling-cells = <2>; 190b7e8f433SVinod Koul L2_700: l2-cache { 191b7e8f433SVinod Koul compatible = "cache"; 1929435294cSPierre Gondois cache-level = <2>; 193b7e8f433SVinod Koul next-level-cache = <&L3_0>; 194b7e8f433SVinod Koul }; 195b7e8f433SVinod Koul }; 19607ddb302SBjorn Andersson 19707ddb302SBjorn Andersson cpu-map { 19807ddb302SBjorn Andersson cluster0 { 19907ddb302SBjorn Andersson core0 { 20007ddb302SBjorn Andersson cpu = <&CPU0>; 20107ddb302SBjorn Andersson }; 20207ddb302SBjorn Andersson 20307ddb302SBjorn Andersson core1 { 20407ddb302SBjorn Andersson cpu = <&CPU1>; 20507ddb302SBjorn Andersson }; 20607ddb302SBjorn Andersson 20707ddb302SBjorn Andersson core2 { 20807ddb302SBjorn Andersson cpu = <&CPU2>; 20907ddb302SBjorn Andersson }; 21007ddb302SBjorn Andersson 21107ddb302SBjorn Andersson core3 { 21207ddb302SBjorn Andersson cpu = <&CPU3>; 21307ddb302SBjorn Andersson }; 21407ddb302SBjorn Andersson 21507ddb302SBjorn Andersson core4 { 21607ddb302SBjorn Andersson cpu = <&CPU4>; 21707ddb302SBjorn Andersson }; 21807ddb302SBjorn Andersson 21907ddb302SBjorn Andersson core5 { 22007ddb302SBjorn Andersson cpu = <&CPU5>; 22107ddb302SBjorn Andersson }; 22207ddb302SBjorn Andersson 22307ddb302SBjorn Andersson core6 { 22407ddb302SBjorn Andersson cpu = <&CPU6>; 22507ddb302SBjorn Andersson }; 22607ddb302SBjorn Andersson 22707ddb302SBjorn Andersson core7 { 22807ddb302SBjorn Andersson cpu = <&CPU7>; 22907ddb302SBjorn Andersson }; 23007ddb302SBjorn Andersson }; 23107ddb302SBjorn Andersson }; 23207ddb302SBjorn Andersson 23307ddb302SBjorn Andersson idle-states { 23407ddb302SBjorn Andersson entry-method = "psci"; 23507ddb302SBjorn Andersson 23607ddb302SBjorn Andersson LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 23707ddb302SBjorn Andersson compatible = "arm,idle-state"; 23807ddb302SBjorn Andersson idle-state-name = "silver-rail-power-collapse"; 23907ddb302SBjorn Andersson arm,psci-suspend-param = <0x40000004>; 24007ddb302SBjorn Andersson entry-latency-us = <355>; 24107ddb302SBjorn Andersson exit-latency-us = <909>; 24207ddb302SBjorn Andersson min-residency-us = <3934>; 24307ddb302SBjorn Andersson local-timer-stop; 24407ddb302SBjorn Andersson }; 24507ddb302SBjorn Andersson 24607ddb302SBjorn Andersson BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 24707ddb302SBjorn Andersson compatible = "arm,idle-state"; 24807ddb302SBjorn Andersson idle-state-name = "gold-rail-power-collapse"; 24907ddb302SBjorn Andersson arm,psci-suspend-param = <0x40000004>; 25007ddb302SBjorn Andersson entry-latency-us = <241>; 25107ddb302SBjorn Andersson exit-latency-us = <1461>; 25207ddb302SBjorn Andersson min-residency-us = <4488>; 25307ddb302SBjorn Andersson local-timer-stop; 25407ddb302SBjorn Andersson }; 25507ddb302SBjorn Andersson }; 25607ddb302SBjorn Andersson 25707ddb302SBjorn Andersson domain-idle-states { 25807ddb302SBjorn Andersson CLUSTER_SLEEP_0: cluster-sleep-0 { 25907ddb302SBjorn Andersson compatible = "domain-idle-state"; 26007ddb302SBjorn Andersson arm,psci-suspend-param = <0x4100c344>; 26107ddb302SBjorn Andersson entry-latency-us = <3263>; 26207ddb302SBjorn Andersson exit-latency-us = <6562>; 26307ddb302SBjorn Andersson min-residency-us = <9987>; 26407ddb302SBjorn Andersson }; 26507ddb302SBjorn Andersson }; 266b7e8f433SVinod Koul }; 267b7e8f433SVinod Koul 268b7e8f433SVinod Koul firmware { 269b7e8f433SVinod Koul scm: scm { 270b7e8f433SVinod Koul compatible = "qcom,scm-sm8350", "qcom,scm"; 271b7e8f433SVinod Koul #reset-cells = <1>; 272b7e8f433SVinod Koul }; 273b7e8f433SVinod Koul }; 274b7e8f433SVinod Koul 275b7e8f433SVinod Koul memory@80000000 { 276b7e8f433SVinod Koul device_type = "memory"; 277b7e8f433SVinod Koul /* We expect the bootloader to fill in the size */ 278b7e8f433SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 279b7e8f433SVinod Koul }; 280b7e8f433SVinod Koul 281b7e8f433SVinod Koul pmu { 282b7e8f433SVinod Koul compatible = "arm,armv8-pmuv3"; 283794d3e30SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 284b7e8f433SVinod Koul }; 285b7e8f433SVinod Koul 286b7e8f433SVinod Koul psci { 287b7e8f433SVinod Koul compatible = "arm,psci-1.0"; 288b7e8f433SVinod Koul method = "smc"; 28907ddb302SBjorn Andersson 290a9371962SKrzysztof Kozlowski CPU_PD0: power-domain-cpu0 { 29107ddb302SBjorn Andersson #power-domain-cells = <0>; 29207ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 29307ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 29407ddb302SBjorn Andersson }; 29507ddb302SBjorn Andersson 296a9371962SKrzysztof Kozlowski CPU_PD1: power-domain-cpu1 { 29707ddb302SBjorn Andersson #power-domain-cells = <0>; 29807ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 29907ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 30007ddb302SBjorn Andersson }; 30107ddb302SBjorn Andersson 302a9371962SKrzysztof Kozlowski CPU_PD2: power-domain-cpu2 { 30307ddb302SBjorn Andersson #power-domain-cells = <0>; 30407ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 30507ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 30607ddb302SBjorn Andersson }; 30707ddb302SBjorn Andersson 308a9371962SKrzysztof Kozlowski CPU_PD3: power-domain-cpu3 { 30907ddb302SBjorn Andersson #power-domain-cells = <0>; 31007ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 31107ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 31207ddb302SBjorn Andersson }; 31307ddb302SBjorn Andersson 314a9371962SKrzysztof Kozlowski CPU_PD4: power-domain-cpu4 { 31507ddb302SBjorn Andersson #power-domain-cells = <0>; 31607ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 31707ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 31807ddb302SBjorn Andersson }; 31907ddb302SBjorn Andersson 320a9371962SKrzysztof Kozlowski CPU_PD5: power-domain-cpu5 { 32107ddb302SBjorn Andersson #power-domain-cells = <0>; 32207ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 32307ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 32407ddb302SBjorn Andersson }; 32507ddb302SBjorn Andersson 326a9371962SKrzysztof Kozlowski CPU_PD6: power-domain-cpu6 { 32707ddb302SBjorn Andersson #power-domain-cells = <0>; 32807ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 32907ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 33007ddb302SBjorn Andersson }; 33107ddb302SBjorn Andersson 332a9371962SKrzysztof Kozlowski CPU_PD7: power-domain-cpu7 { 33307ddb302SBjorn Andersson #power-domain-cells = <0>; 33407ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 33507ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 33607ddb302SBjorn Andersson }; 33707ddb302SBjorn Andersson 338a9371962SKrzysztof Kozlowski CLUSTER_PD: power-domain-cpu-cluster0 { 33907ddb302SBjorn Andersson #power-domain-cells = <0>; 34007ddb302SBjorn Andersson domain-idle-states = <&CLUSTER_SLEEP_0>; 34107ddb302SBjorn Andersson }; 342b7e8f433SVinod Koul }; 343b7e8f433SVinod Koul 344e2eedde4SVinod Koul qup_opp_table_100mhz: opp-table-qup100mhz { 345e2eedde4SVinod Koul compatible = "operating-points-v2"; 346e2eedde4SVinod Koul 347e2eedde4SVinod Koul opp-50000000 { 348e2eedde4SVinod Koul opp-hz = /bits/ 64 <50000000>; 349e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_min_svs>; 350e2eedde4SVinod Koul }; 351e2eedde4SVinod Koul 352e2eedde4SVinod Koul opp-75000000 { 353e2eedde4SVinod Koul opp-hz = /bits/ 64 <75000000>; 354e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_low_svs>; 355e2eedde4SVinod Koul }; 356e2eedde4SVinod Koul 357e2eedde4SVinod Koul opp-100000000 { 358e2eedde4SVinod Koul opp-hz = /bits/ 64 <100000000>; 359e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_svs>; 360e2eedde4SVinod Koul }; 361e2eedde4SVinod Koul }; 362e2eedde4SVinod Koul 363e2eedde4SVinod Koul qup_opp_table_120mhz: opp-table-qup120mhz { 364e2eedde4SVinod Koul compatible = "operating-points-v2"; 365e2eedde4SVinod Koul 366e2eedde4SVinod Koul opp-50000000 { 367e2eedde4SVinod Koul opp-hz = /bits/ 64 <50000000>; 368e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_min_svs>; 369e2eedde4SVinod Koul }; 370e2eedde4SVinod Koul 371e2eedde4SVinod Koul opp-75000000 { 372e2eedde4SVinod Koul opp-hz = /bits/ 64 <75000000>; 373e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_low_svs>; 374e2eedde4SVinod Koul }; 375e2eedde4SVinod Koul 376e2eedde4SVinod Koul opp-120000000 { 377e2eedde4SVinod Koul opp-hz = /bits/ 64 <120000000>; 378e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_svs>; 379e2eedde4SVinod Koul }; 380e2eedde4SVinod Koul }; 381e2eedde4SVinod Koul 382b7e8f433SVinod Koul reserved_memory: reserved-memory { 383b7e8f433SVinod Koul #address-cells = <2>; 384b7e8f433SVinod Koul #size-cells = <2>; 385b7e8f433SVinod Koul ranges; 386b7e8f433SVinod Koul 387b7e8f433SVinod Koul hyp_mem: memory@80000000 { 388b7e8f433SVinod Koul reg = <0x0 0x80000000 0x0 0x600000>; 389b7e8f433SVinod Koul no-map; 390b7e8f433SVinod Koul }; 391b7e8f433SVinod Koul 392b7e8f433SVinod Koul xbl_aop_mem: memory@80700000 { 393b7e8f433SVinod Koul no-map; 394b7e8f433SVinod Koul reg = <0x0 0x80700000 0x0 0x160000>; 395b7e8f433SVinod Koul }; 396b7e8f433SVinod Koul 397b7e8f433SVinod Koul cmd_db: memory@80860000 { 398b7e8f433SVinod Koul compatible = "qcom,cmd-db"; 399b7e8f433SVinod Koul reg = <0x0 0x80860000 0x0 0x20000>; 400b7e8f433SVinod Koul no-map; 401b7e8f433SVinod Koul }; 402b7e8f433SVinod Koul 403b7e8f433SVinod Koul reserved_xbl_uefi_log: memory@80880000 { 404b7e8f433SVinod Koul reg = <0x0 0x80880000 0x0 0x14000>; 405b7e8f433SVinod Koul no-map; 406b7e8f433SVinod Koul }; 407b7e8f433SVinod Koul 4088503babcSKonrad Dybcio smem@80900000 { 4098503babcSKonrad Dybcio compatible = "qcom,smem"; 410b7e8f433SVinod Koul reg = <0x0 0x80900000 0x0 0x200000>; 4118503babcSKonrad Dybcio hwlocks = <&tcsr_mutex 3>; 412b7e8f433SVinod Koul no-map; 413b7e8f433SVinod Koul }; 414b7e8f433SVinod Koul 415b7e8f433SVinod Koul cpucp_fw_mem: memory@80b00000 { 416b7e8f433SVinod Koul reg = <0x0 0x80b00000 0x0 0x100000>; 417b7e8f433SVinod Koul no-map; 418b7e8f433SVinod Koul }; 419b7e8f433SVinod Koul 420b7e8f433SVinod Koul cdsp_secure_heap: memory@80c00000 { 421b7e8f433SVinod Koul reg = <0x0 0x80c00000 0x0 0x4600000>; 422b7e8f433SVinod Koul no-map; 423b7e8f433SVinod Koul }; 424b7e8f433SVinod Koul 425b7e8f433SVinod Koul pil_camera_mem: mmeory@85200000 { 426b7e8f433SVinod Koul reg = <0x0 0x85200000 0x0 0x500000>; 427b7e8f433SVinod Koul no-map; 428b7e8f433SVinod Koul }; 429b7e8f433SVinod Koul 430b7e8f433SVinod Koul pil_video_mem: memory@85700000 { 431b7e8f433SVinod Koul reg = <0x0 0x85700000 0x0 0x500000>; 432b7e8f433SVinod Koul no-map; 433b7e8f433SVinod Koul }; 434b7e8f433SVinod Koul 435b7e8f433SVinod Koul pil_cvp_mem: memory@85c00000 { 436b7e8f433SVinod Koul reg = <0x0 0x85c00000 0x0 0x500000>; 437b7e8f433SVinod Koul no-map; 438b7e8f433SVinod Koul }; 439b7e8f433SVinod Koul 440b7e8f433SVinod Koul pil_adsp_mem: memory@86100000 { 441b7e8f433SVinod Koul reg = <0x0 0x86100000 0x0 0x2100000>; 442b7e8f433SVinod Koul no-map; 443b7e8f433SVinod Koul }; 444b7e8f433SVinod Koul 445b7e8f433SVinod Koul pil_slpi_mem: memory@88200000 { 446b7e8f433SVinod Koul reg = <0x0 0x88200000 0x0 0x1500000>; 447b7e8f433SVinod Koul no-map; 448b7e8f433SVinod Koul }; 449b7e8f433SVinod Koul 450b7e8f433SVinod Koul pil_cdsp_mem: memory@89700000 { 451b7e8f433SVinod Koul reg = <0x0 0x89700000 0x0 0x1e00000>; 452b7e8f433SVinod Koul no-map; 453b7e8f433SVinod Koul }; 454b7e8f433SVinod Koul 455b7e8f433SVinod Koul pil_ipa_fw_mem: memory@8b500000 { 456b7e8f433SVinod Koul reg = <0x0 0x8b500000 0x0 0x10000>; 457b7e8f433SVinod Koul no-map; 458b7e8f433SVinod Koul }; 459b7e8f433SVinod Koul 460b7e8f433SVinod Koul pil_ipa_gsi_mem: memory@8b510000 { 461b7e8f433SVinod Koul reg = <0x0 0x8b510000 0x0 0xa000>; 462b7e8f433SVinod Koul no-map; 463b7e8f433SVinod Koul }; 464b7e8f433SVinod Koul 465b7e8f433SVinod Koul pil_gpu_mem: memory@8b51a000 { 466b7e8f433SVinod Koul reg = <0x0 0x8b51a000 0x0 0x2000>; 467b7e8f433SVinod Koul no-map; 468b7e8f433SVinod Koul }; 469b7e8f433SVinod Koul 470b7e8f433SVinod Koul pil_spss_mem: memory@8b600000 { 471b7e8f433SVinod Koul reg = <0x0 0x8b600000 0x0 0x100000>; 472b7e8f433SVinod Koul no-map; 473b7e8f433SVinod Koul }; 474b7e8f433SVinod Koul 475b7e8f433SVinod Koul pil_modem_mem: memory@8b800000 { 476b7e8f433SVinod Koul reg = <0x0 0x8b800000 0x0 0x10000000>; 477b7e8f433SVinod Koul no-map; 478b7e8f433SVinod Koul }; 479b7e8f433SVinod Koul 480774890c9SVinod Koul rmtfs_mem: memory@9b800000 { 481774890c9SVinod Koul compatible = "qcom,rmtfs-mem"; 482774890c9SVinod Koul reg = <0x0 0x9b800000 0x0 0x280000>; 483774890c9SVinod Koul no-map; 484774890c9SVinod Koul 485774890c9SVinod Koul qcom,client-id = <1>; 486774890c9SVinod Koul qcom,vmid = <15>; 487774890c9SVinod Koul }; 488774890c9SVinod Koul 489b7e8f433SVinod Koul hyp_reserved_mem: memory@d0000000 { 490b7e8f433SVinod Koul reg = <0x0 0xd0000000 0x0 0x800000>; 491b7e8f433SVinod Koul no-map; 492b7e8f433SVinod Koul }; 493b7e8f433SVinod Koul 494b7e8f433SVinod Koul pil_trustedvm_mem: memory@d0800000 { 495b7e8f433SVinod Koul reg = <0x0 0xd0800000 0x0 0x76f7000>; 496b7e8f433SVinod Koul no-map; 497b7e8f433SVinod Koul }; 498b7e8f433SVinod Koul 499b7e8f433SVinod Koul qrtr_shbuf: memory@d7ef7000 { 500b7e8f433SVinod Koul reg = <0x0 0xd7ef7000 0x0 0x9000>; 501b7e8f433SVinod Koul no-map; 502b7e8f433SVinod Koul }; 503b7e8f433SVinod Koul 504b7e8f433SVinod Koul chan0_shbuf: memory@d7f00000 { 505b7e8f433SVinod Koul reg = <0x0 0xd7f00000 0x0 0x80000>; 506b7e8f433SVinod Koul no-map; 507b7e8f433SVinod Koul }; 508b7e8f433SVinod Koul 509b7e8f433SVinod Koul chan1_shbuf: memory@d7f80000 { 510b7e8f433SVinod Koul reg = <0x0 0xd7f80000 0x0 0x80000>; 511b7e8f433SVinod Koul no-map; 512b7e8f433SVinod Koul }; 513b7e8f433SVinod Koul 514b7e8f433SVinod Koul removed_mem: memory@d8800000 { 515b7e8f433SVinod Koul reg = <0x0 0xd8800000 0x0 0x6800000>; 516b7e8f433SVinod Koul no-map; 517b7e8f433SVinod Koul }; 518b7e8f433SVinod Koul }; 519b7e8f433SVinod Koul 52003a41991SVinod Koul smp2p-adsp { 52103a41991SVinod Koul compatible = "qcom,smp2p"; 52203a41991SVinod Koul qcom,smem = <443>, <429>; 52303a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 52403a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 52503a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 52603a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_LPASS 52703a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 52803a41991SVinod Koul 52903a41991SVinod Koul qcom,local-pid = <0>; 53003a41991SVinod Koul qcom,remote-pid = <2>; 53103a41991SVinod Koul 53203a41991SVinod Koul smp2p_adsp_out: master-kernel { 53303a41991SVinod Koul qcom,entry-name = "master-kernel"; 53403a41991SVinod Koul #qcom,smem-state-cells = <1>; 53503a41991SVinod Koul }; 53603a41991SVinod Koul 53703a41991SVinod Koul smp2p_adsp_in: slave-kernel { 53803a41991SVinod Koul qcom,entry-name = "slave-kernel"; 53903a41991SVinod Koul interrupt-controller; 54003a41991SVinod Koul #interrupt-cells = <2>; 54103a41991SVinod Koul }; 54203a41991SVinod Koul }; 54303a41991SVinod Koul 54403a41991SVinod Koul smp2p-cdsp { 54503a41991SVinod Koul compatible = "qcom,smp2p"; 54603a41991SVinod Koul qcom,smem = <94>, <432>; 54703a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 54803a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 54903a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 55003a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_CDSP 55103a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 55203a41991SVinod Koul 55303a41991SVinod Koul qcom,local-pid = <0>; 55403a41991SVinod Koul qcom,remote-pid = <5>; 55503a41991SVinod Koul 55603a41991SVinod Koul smp2p_cdsp_out: master-kernel { 55703a41991SVinod Koul qcom,entry-name = "master-kernel"; 55803a41991SVinod Koul #qcom,smem-state-cells = <1>; 55903a41991SVinod Koul }; 56003a41991SVinod Koul 56103a41991SVinod Koul smp2p_cdsp_in: slave-kernel { 56203a41991SVinod Koul qcom,entry-name = "slave-kernel"; 56303a41991SVinod Koul interrupt-controller; 56403a41991SVinod Koul #interrupt-cells = <2>; 56503a41991SVinod Koul }; 56603a41991SVinod Koul }; 56703a41991SVinod Koul 56803a41991SVinod Koul smp2p-modem { 56903a41991SVinod Koul compatible = "qcom,smp2p"; 57003a41991SVinod Koul qcom,smem = <435>, <428>; 57103a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 57203a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 57303a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 57403a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_MPSS 57503a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 57603a41991SVinod Koul 57703a41991SVinod Koul qcom,local-pid = <0>; 57803a41991SVinod Koul qcom,remote-pid = <1>; 57903a41991SVinod Koul 58003a41991SVinod Koul smp2p_modem_out: master-kernel { 58103a41991SVinod Koul qcom,entry-name = "master-kernel"; 58203a41991SVinod Koul #qcom,smem-state-cells = <1>; 58303a41991SVinod Koul }; 58403a41991SVinod Koul 58503a41991SVinod Koul smp2p_modem_in: slave-kernel { 58603a41991SVinod Koul qcom,entry-name = "slave-kernel"; 58703a41991SVinod Koul interrupt-controller; 58803a41991SVinod Koul #interrupt-cells = <2>; 58903a41991SVinod Koul }; 590f11d3e7dSAlex Elder 591f11d3e7dSAlex Elder ipa_smp2p_out: ipa-ap-to-modem { 592f11d3e7dSAlex Elder qcom,entry-name = "ipa"; 593f11d3e7dSAlex Elder #qcom,smem-state-cells = <1>; 594f11d3e7dSAlex Elder }; 595f11d3e7dSAlex Elder 596f11d3e7dSAlex Elder ipa_smp2p_in: ipa-modem-to-ap { 597f11d3e7dSAlex Elder qcom,entry-name = "ipa"; 598f11d3e7dSAlex Elder interrupt-controller; 599f11d3e7dSAlex Elder #interrupt-cells = <2>; 600f11d3e7dSAlex Elder }; 60103a41991SVinod Koul }; 60203a41991SVinod Koul 60303a41991SVinod Koul smp2p-slpi { 60403a41991SVinod Koul compatible = "qcom,smp2p"; 60503a41991SVinod Koul qcom,smem = <481>, <430>; 60603a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 60703a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 60803a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 60903a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_SLPI 61003a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 61103a41991SVinod Koul 61203a41991SVinod Koul qcom,local-pid = <0>; 61303a41991SVinod Koul qcom,remote-pid = <3>; 61403a41991SVinod Koul 61503a41991SVinod Koul smp2p_slpi_out: master-kernel { 61603a41991SVinod Koul qcom,entry-name = "master-kernel"; 61703a41991SVinod Koul #qcom,smem-state-cells = <1>; 61803a41991SVinod Koul }; 61903a41991SVinod Koul 62003a41991SVinod Koul smp2p_slpi_in: slave-kernel { 62103a41991SVinod Koul qcom,entry-name = "slave-kernel"; 62203a41991SVinod Koul interrupt-controller; 62303a41991SVinod Koul #interrupt-cells = <2>; 62403a41991SVinod Koul }; 62503a41991SVinod Koul }; 62603a41991SVinod Koul 627b7e8f433SVinod Koul soc: soc@0 { 628b7e8f433SVinod Koul #address-cells = <2>; 629b7e8f433SVinod Koul #size-cells = <2>; 630b7e8f433SVinod Koul ranges = <0 0 0 0 0x10 0>; 631b7e8f433SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 632b7e8f433SVinod Koul compatible = "simple-bus"; 633b7e8f433SVinod Koul 634b7e8f433SVinod Koul gcc: clock-controller@100000 { 635b7e8f433SVinod Koul compatible = "qcom,gcc-sm8350"; 636b7e8f433SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 637b7e8f433SVinod Koul #clock-cells = <1>; 638b7e8f433SVinod Koul #reset-cells = <1>; 639b7e8f433SVinod Koul #power-domain-cells = <1>; 6409ea9eb36SKonrad Dybcio clock-names = "bi_tcxo", 6419ea9eb36SKonrad Dybcio "sleep_clk", 6429ea9eb36SKonrad Dybcio "pcie_0_pipe_clk", 6439ea9eb36SKonrad Dybcio "pcie_1_pipe_clk", 6449ea9eb36SKonrad Dybcio "ufs_card_rx_symbol_0_clk", 6459ea9eb36SKonrad Dybcio "ufs_card_rx_symbol_1_clk", 6469ea9eb36SKonrad Dybcio "ufs_card_tx_symbol_0_clk", 6479ea9eb36SKonrad Dybcio "ufs_phy_rx_symbol_0_clk", 6489ea9eb36SKonrad Dybcio "ufs_phy_rx_symbol_1_clk", 6499ea9eb36SKonrad Dybcio "ufs_phy_tx_symbol_0_clk", 6509ea9eb36SKonrad Dybcio "usb3_phy_wrapper_gcc_usb30_pipe_clk", 6519ea9eb36SKonrad Dybcio "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 6529ea9eb36SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 6539ea9eb36SKonrad Dybcio <&sleep_clk>, 6546daee406SDmitry Baryshkov <&pcie0_phy>, 6556daee406SDmitry Baryshkov <&pcie1_phy>, 6569ea9eb36SKonrad Dybcio <0>, 6579ea9eb36SKonrad Dybcio <0>, 6589ea9eb36SKonrad Dybcio <0>, 65986543bc6SDmitry Baryshkov <&ufs_mem_phy_lanes 0>, 66086543bc6SDmitry Baryshkov <&ufs_mem_phy_lanes 1>, 66186543bc6SDmitry Baryshkov <&ufs_mem_phy_lanes 2>, 6622458a305SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 6639ea9eb36SKonrad Dybcio <0>; 664b7e8f433SVinod Koul }; 665b7e8f433SVinod Koul 666b7e8f433SVinod Koul ipcc: mailbox@408000 { 667b7e8f433SVinod Koul compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 668b7e8f433SVinod Koul reg = <0 0x00408000 0 0x1000>; 669b7e8f433SVinod Koul interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 670b7e8f433SVinod Koul interrupt-controller; 671b7e8f433SVinod Koul #interrupt-cells = <3>; 672b7e8f433SVinod Koul #mbox-cells = <2>; 673b7e8f433SVinod Koul }; 674b7e8f433SVinod Koul 675bc08fbf4SBjorn Andersson gpi_dma2: dma-controller@800000 { 676b561e225SKrzysztof Kozlowski compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 677bc08fbf4SBjorn Andersson reg = <0 0x00800000 0 0x60000>; 678bc08fbf4SBjorn Andersson interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 679bc08fbf4SBjorn Andersson <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 680bc08fbf4SBjorn Andersson <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 681bc08fbf4SBjorn Andersson <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 682bc08fbf4SBjorn Andersson <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 683bc08fbf4SBjorn Andersson <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 684bc08fbf4SBjorn Andersson <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 685bc08fbf4SBjorn Andersson <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 686bc08fbf4SBjorn Andersson <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 687bc08fbf4SBjorn Andersson <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 688bc08fbf4SBjorn Andersson <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 689bc08fbf4SBjorn Andersson <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 690bc08fbf4SBjorn Andersson dma-channels = <12>; 691bc08fbf4SBjorn Andersson dma-channel-mask = <0xff>; 692bc08fbf4SBjorn Andersson iommus = <&apps_smmu 0x5f6 0x0>; 693bc08fbf4SBjorn Andersson #dma-cells = <3>; 694bc08fbf4SBjorn Andersson status = "disabled"; 695bc08fbf4SBjorn Andersson }; 696bc08fbf4SBjorn Andersson 697e84d04a2SKonrad Dybcio qupv3_id_2: geniqup@8c0000 { 698e84d04a2SKonrad Dybcio compatible = "qcom,geni-se-qup"; 699e84d04a2SKonrad Dybcio reg = <0x0 0x008c0000 0x0 0x6000>; 700e84d04a2SKonrad Dybcio clock-names = "m-ahb", "s-ahb"; 701e84d04a2SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 702e84d04a2SKonrad Dybcio <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 7039bc2c8feSKonrad Dybcio iommus = <&apps_smmu 0x5e3 0x0>; 704e84d04a2SKonrad Dybcio #address-cells = <2>; 705e84d04a2SKonrad Dybcio #size-cells = <2>; 706e84d04a2SKonrad Dybcio ranges; 707e84d04a2SKonrad Dybcio status = "disabled"; 70898374e69SKonrad Dybcio 70998374e69SKonrad Dybcio i2c14: i2c@880000 { 71098374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 71198374e69SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 71298374e69SKonrad Dybcio clock-names = "se"; 71398374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 71498374e69SKonrad Dybcio pinctrl-names = "default"; 71598374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c14_default>; 71698374e69SKonrad Dybcio interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 717ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 718ddc97e7dSBjorn Andersson <&gpi_dma2 1 0 QCOM_GPI_I2C>; 719ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 72098374e69SKonrad Dybcio #address-cells = <1>; 72198374e69SKonrad Dybcio #size-cells = <0>; 72298374e69SKonrad Dybcio status = "disabled"; 72398374e69SKonrad Dybcio }; 72498374e69SKonrad Dybcio 72598374e69SKonrad Dybcio spi14: spi@880000 { 72698374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 72798374e69SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 72898374e69SKonrad Dybcio clock-names = "se"; 72998374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 73098374e69SKonrad Dybcio interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 73198374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 73298374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_120mhz>; 733ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 734ddc97e7dSBjorn Andersson <&gpi_dma2 1 0 QCOM_GPI_SPI>; 735ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 73698374e69SKonrad Dybcio #address-cells = <1>; 73798374e69SKonrad Dybcio #size-cells = <0>; 73898374e69SKonrad Dybcio status = "disabled"; 73998374e69SKonrad Dybcio }; 74098374e69SKonrad Dybcio 74198374e69SKonrad Dybcio i2c15: i2c@884000 { 74298374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 74398374e69SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 74498374e69SKonrad Dybcio clock-names = "se"; 74598374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 74698374e69SKonrad Dybcio pinctrl-names = "default"; 74798374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c15_default>; 74898374e69SKonrad Dybcio interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 749ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 750ddc97e7dSBjorn Andersson <&gpi_dma2 1 1 QCOM_GPI_I2C>; 751ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 75298374e69SKonrad Dybcio #address-cells = <1>; 75398374e69SKonrad Dybcio #size-cells = <0>; 75498374e69SKonrad Dybcio status = "disabled"; 75598374e69SKonrad Dybcio }; 75698374e69SKonrad Dybcio 75798374e69SKonrad Dybcio spi15: spi@884000 { 75898374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 75998374e69SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 76098374e69SKonrad Dybcio clock-names = "se"; 76198374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 76298374e69SKonrad Dybcio interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 76398374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 76498374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_120mhz>; 765ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 766ddc97e7dSBjorn Andersson <&gpi_dma2 1 1 QCOM_GPI_SPI>; 767ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 76898374e69SKonrad Dybcio #address-cells = <1>; 76998374e69SKonrad Dybcio #size-cells = <0>; 77098374e69SKonrad Dybcio status = "disabled"; 77198374e69SKonrad Dybcio }; 77298374e69SKonrad Dybcio 77398374e69SKonrad Dybcio i2c16: i2c@888000 { 77498374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 77598374e69SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 77698374e69SKonrad Dybcio clock-names = "se"; 77798374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 77898374e69SKonrad Dybcio pinctrl-names = "default"; 77998374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c16_default>; 78098374e69SKonrad Dybcio interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 781ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 782ddc97e7dSBjorn Andersson <&gpi_dma2 1 2 QCOM_GPI_I2C>; 783ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 78498374e69SKonrad Dybcio #address-cells = <1>; 78598374e69SKonrad Dybcio #size-cells = <0>; 78698374e69SKonrad Dybcio status = "disabled"; 78798374e69SKonrad Dybcio }; 78898374e69SKonrad Dybcio 78998374e69SKonrad Dybcio spi16: spi@888000 { 79098374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 79198374e69SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 79298374e69SKonrad Dybcio clock-names = "se"; 79398374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 79498374e69SKonrad Dybcio interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 79598374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 79698374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 797ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 798ddc97e7dSBjorn Andersson <&gpi_dma2 1 2 QCOM_GPI_SPI>; 799ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 80098374e69SKonrad Dybcio #address-cells = <1>; 80198374e69SKonrad Dybcio #size-cells = <0>; 80298374e69SKonrad Dybcio status = "disabled"; 80398374e69SKonrad Dybcio }; 80498374e69SKonrad Dybcio 80598374e69SKonrad Dybcio i2c17: i2c@88c000 { 80698374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 80798374e69SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 80898374e69SKonrad Dybcio clock-names = "se"; 80998374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 81098374e69SKonrad Dybcio pinctrl-names = "default"; 81198374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c17_default>; 81298374e69SKonrad Dybcio interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 813ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 814ddc97e7dSBjorn Andersson <&gpi_dma2 1 3 QCOM_GPI_I2C>; 815ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 81698374e69SKonrad Dybcio #address-cells = <1>; 81798374e69SKonrad Dybcio #size-cells = <0>; 81898374e69SKonrad Dybcio status = "disabled"; 81998374e69SKonrad Dybcio }; 82098374e69SKonrad Dybcio 82198374e69SKonrad Dybcio spi17: spi@88c000 { 82298374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 82398374e69SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 82498374e69SKonrad Dybcio clock-names = "se"; 82598374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 82698374e69SKonrad Dybcio interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 82798374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 82898374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 829ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 830ddc97e7dSBjorn Andersson <&gpi_dma2 1 3 QCOM_GPI_SPI>; 831ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 83298374e69SKonrad Dybcio #address-cells = <1>; 83398374e69SKonrad Dybcio #size-cells = <0>; 83498374e69SKonrad Dybcio status = "disabled"; 83598374e69SKonrad Dybcio }; 83698374e69SKonrad Dybcio 83798374e69SKonrad Dybcio /* QUP no. 18 seems to be strictly SPI/UART-only */ 83898374e69SKonrad Dybcio 83998374e69SKonrad Dybcio spi18: spi@890000 { 84098374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 84198374e69SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 84298374e69SKonrad Dybcio clock-names = "se"; 84398374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 84498374e69SKonrad Dybcio interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 84598374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 84698374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 847ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 848ddc97e7dSBjorn Andersson <&gpi_dma2 1 4 QCOM_GPI_SPI>; 849ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 85098374e69SKonrad Dybcio #address-cells = <1>; 85198374e69SKonrad Dybcio #size-cells = <0>; 85298374e69SKonrad Dybcio status = "disabled"; 85398374e69SKonrad Dybcio }; 85498374e69SKonrad Dybcio 85598374e69SKonrad Dybcio uart18: serial@890000 { 85698374e69SKonrad Dybcio compatible = "qcom,geni-uart"; 85798374e69SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 85898374e69SKonrad Dybcio clock-names = "se"; 85998374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 86098374e69SKonrad Dybcio pinctrl-names = "default"; 86198374e69SKonrad Dybcio pinctrl-0 = <&qup_uart18_default>; 86298374e69SKonrad Dybcio interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 86398374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 86498374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 86598374e69SKonrad Dybcio status = "disabled"; 86698374e69SKonrad Dybcio }; 86798374e69SKonrad Dybcio 86898374e69SKonrad Dybcio i2c19: i2c@894000 { 86998374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 87098374e69SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 87198374e69SKonrad Dybcio clock-names = "se"; 87298374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 87398374e69SKonrad Dybcio pinctrl-names = "default"; 87498374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c19_default>; 87598374e69SKonrad Dybcio interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 876ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 877ddc97e7dSBjorn Andersson <&gpi_dma2 1 5 QCOM_GPI_I2C>; 878ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 87998374e69SKonrad Dybcio #address-cells = <1>; 88098374e69SKonrad Dybcio #size-cells = <0>; 88198374e69SKonrad Dybcio status = "disabled"; 88298374e69SKonrad Dybcio }; 88398374e69SKonrad Dybcio 88498374e69SKonrad Dybcio spi19: spi@894000 { 88598374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 88698374e69SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 88798374e69SKonrad Dybcio clock-names = "se"; 88898374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 88998374e69SKonrad Dybcio interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 89098374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 89198374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 892bc08fbf4SBjorn Andersson dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 893bc08fbf4SBjorn Andersson <&gpi_dma2 1 5 QCOM_GPI_SPI>; 894bc08fbf4SBjorn Andersson dma-names = "tx", "rx"; 89598374e69SKonrad Dybcio #address-cells = <1>; 89698374e69SKonrad Dybcio #size-cells = <0>; 89798374e69SKonrad Dybcio status = "disabled"; 89898374e69SKonrad Dybcio }; 899e84d04a2SKonrad Dybcio }; 900e84d04a2SKonrad Dybcio 901bc08fbf4SBjorn Andersson gpi_dma0: dma-controller@900000 { 902b561e225SKrzysztof Kozlowski compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 903bc08fbf4SBjorn Andersson reg = <0 0x09800000 0 0x60000>; 904bc08fbf4SBjorn Andersson interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 905bc08fbf4SBjorn Andersson <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 906bc08fbf4SBjorn Andersson <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 907bc08fbf4SBjorn Andersson <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 908bc08fbf4SBjorn Andersson <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 909bc08fbf4SBjorn Andersson <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 910bc08fbf4SBjorn Andersson <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 911bc08fbf4SBjorn Andersson <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 912bc08fbf4SBjorn Andersson <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 913bc08fbf4SBjorn Andersson <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 914bc08fbf4SBjorn Andersson <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 915bc08fbf4SBjorn Andersson <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 916bc08fbf4SBjorn Andersson dma-channels = <12>; 917bc08fbf4SBjorn Andersson dma-channel-mask = <0x7e>; 918bc08fbf4SBjorn Andersson iommus = <&apps_smmu 0x5b6 0x0>; 919bc08fbf4SBjorn Andersson #dma-cells = <3>; 920bc08fbf4SBjorn Andersson status = "disabled"; 921bc08fbf4SBjorn Andersson }; 922bc08fbf4SBjorn Andersson 92387f0b434SRobert Foss qupv3_id_0: geniqup@9c0000 { 924b7e8f433SVinod Koul compatible = "qcom,geni-se-qup"; 925b7e8f433SVinod Koul reg = <0x0 0x009c0000 0x0 0x6000>; 926b7e8f433SVinod Koul clock-names = "m-ahb", "s-ahb"; 9276d91e201SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9286d91e201SVinod Koul <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9299bc2c8feSKonrad Dybcio iommus = <&apps_smmu 0x5a3 0>; 930b7e8f433SVinod Koul #address-cells = <2>; 931b7e8f433SVinod Koul #size-cells = <2>; 932b7e8f433SVinod Koul ranges; 933b7e8f433SVinod Koul status = "disabled"; 934b7e8f433SVinod Koul 935cf03cd7eSKonrad Dybcio i2c0: i2c@980000 { 936cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 937cf03cd7eSKonrad Dybcio reg = <0 0x00980000 0 0x4000>; 938cf03cd7eSKonrad Dybcio clock-names = "se"; 939cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 940cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 941cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c0_default>; 942cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 943ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 944ddc97e7dSBjorn Andersson <&gpi_dma0 1 0 QCOM_GPI_I2C>; 945ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 946cf03cd7eSKonrad Dybcio #address-cells = <1>; 947cf03cd7eSKonrad Dybcio #size-cells = <0>; 948cf03cd7eSKonrad Dybcio status = "disabled"; 949cf03cd7eSKonrad Dybcio }; 950cf03cd7eSKonrad Dybcio 951cf03cd7eSKonrad Dybcio spi0: spi@980000 { 952cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 953cf03cd7eSKonrad Dybcio reg = <0 0x00980000 0 0x4000>; 954cf03cd7eSKonrad Dybcio clock-names = "se"; 955cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 957cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 958cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 959ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 960ddc97e7dSBjorn Andersson <&gpi_dma0 1 0 QCOM_GPI_SPI>; 961ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 962cf03cd7eSKonrad Dybcio #address-cells = <1>; 963cf03cd7eSKonrad Dybcio #size-cells = <0>; 964cf03cd7eSKonrad Dybcio status = "disabled"; 965cf03cd7eSKonrad Dybcio }; 966cf03cd7eSKonrad Dybcio 967cf03cd7eSKonrad Dybcio i2c1: i2c@984000 { 968cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 969cf03cd7eSKonrad Dybcio reg = <0 0x00984000 0 0x4000>; 970cf03cd7eSKonrad Dybcio clock-names = "se"; 971cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 972cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 973cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c1_default>; 974cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 975ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 976ddc97e7dSBjorn Andersson <&gpi_dma0 1 1 QCOM_GPI_I2C>; 977ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 978cf03cd7eSKonrad Dybcio #address-cells = <1>; 979cf03cd7eSKonrad Dybcio #size-cells = <0>; 980cf03cd7eSKonrad Dybcio status = "disabled"; 981cf03cd7eSKonrad Dybcio }; 982cf03cd7eSKonrad Dybcio 983cf03cd7eSKonrad Dybcio spi1: spi@984000 { 984cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 985cf03cd7eSKonrad Dybcio reg = <0 0x00984000 0 0x4000>; 986cf03cd7eSKonrad Dybcio clock-names = "se"; 987cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 988cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 989cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 990cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 991ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 992ddc97e7dSBjorn Andersson <&gpi_dma0 1 1 QCOM_GPI_SPI>; 993ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 994cf03cd7eSKonrad Dybcio #address-cells = <1>; 995cf03cd7eSKonrad Dybcio #size-cells = <0>; 996cf03cd7eSKonrad Dybcio status = "disabled"; 997cf03cd7eSKonrad Dybcio }; 998cf03cd7eSKonrad Dybcio 999cf03cd7eSKonrad Dybcio i2c2: i2c@988000 { 1000cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1001cf03cd7eSKonrad Dybcio reg = <0 0x00988000 0 0x4000>; 1002cf03cd7eSKonrad Dybcio clock-names = "se"; 1003cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1004cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1005cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c2_default>; 1006cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1007ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1008ddc97e7dSBjorn Andersson <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1009ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1010cf03cd7eSKonrad Dybcio #address-cells = <1>; 1011cf03cd7eSKonrad Dybcio #size-cells = <0>; 1012cf03cd7eSKonrad Dybcio status = "disabled"; 1013cf03cd7eSKonrad Dybcio }; 1014cf03cd7eSKonrad Dybcio 1015cf03cd7eSKonrad Dybcio spi2: spi@988000 { 1016cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1017cf03cd7eSKonrad Dybcio reg = <0 0x00988000 0 0x4000>; 1018cf03cd7eSKonrad Dybcio clock-names = "se"; 1019cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1021cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1022cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1023ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1024ddc97e7dSBjorn Andersson <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1025ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1026cf03cd7eSKonrad Dybcio #address-cells = <1>; 1027cf03cd7eSKonrad Dybcio #size-cells = <0>; 1028cf03cd7eSKonrad Dybcio status = "disabled"; 1029cf03cd7eSKonrad Dybcio }; 1030cf03cd7eSKonrad Dybcio 1031b7e8f433SVinod Koul uart2: serial@98c000 { 1032b7e8f433SVinod Koul compatible = "qcom,geni-debug-uart"; 1033b7e8f433SVinod Koul reg = <0 0x0098c000 0 0x4000>; 1034b7e8f433SVinod Koul clock-names = "se"; 10356d91e201SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1036b7e8f433SVinod Koul pinctrl-names = "default"; 1037b7e8f433SVinod Koul pinctrl-0 = <&qup_uart3_default_state>; 1038b7e8f433SVinod Koul interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1039cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1040cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1041cf03cd7eSKonrad Dybcio status = "disabled"; 1042cf03cd7eSKonrad Dybcio }; 1043cf03cd7eSKonrad Dybcio 1044cf03cd7eSKonrad Dybcio /* QUP no. 3 seems to be strictly SPI-only */ 1045cf03cd7eSKonrad Dybcio 1046cf03cd7eSKonrad Dybcio spi3: spi@98c000 { 1047cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1048cf03cd7eSKonrad Dybcio reg = <0 0x0098c000 0 0x4000>; 1049cf03cd7eSKonrad Dybcio clock-names = "se"; 1050cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1051cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1052cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1053cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1054ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1055ddc97e7dSBjorn Andersson <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1056ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1057cf03cd7eSKonrad Dybcio #address-cells = <1>; 1058cf03cd7eSKonrad Dybcio #size-cells = <0>; 1059cf03cd7eSKonrad Dybcio status = "disabled"; 1060cf03cd7eSKonrad Dybcio }; 1061cf03cd7eSKonrad Dybcio 1062cf03cd7eSKonrad Dybcio i2c4: i2c@990000 { 1063cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1064cf03cd7eSKonrad Dybcio reg = <0 0x00990000 0 0x4000>; 1065cf03cd7eSKonrad Dybcio clock-names = "se"; 1066cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1067cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1068cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c4_default>; 1069cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1070ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1071ddc97e7dSBjorn Andersson <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1072ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1073cf03cd7eSKonrad Dybcio #address-cells = <1>; 1074cf03cd7eSKonrad Dybcio #size-cells = <0>; 1075cf03cd7eSKonrad Dybcio status = "disabled"; 1076cf03cd7eSKonrad Dybcio }; 1077cf03cd7eSKonrad Dybcio 1078cf03cd7eSKonrad Dybcio spi4: spi@990000 { 1079cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1080cf03cd7eSKonrad Dybcio reg = <0 0x00990000 0 0x4000>; 1081cf03cd7eSKonrad Dybcio clock-names = "se"; 1082cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1083cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1084cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1085cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1086ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1087ddc97e7dSBjorn Andersson <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1088ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1089cf03cd7eSKonrad Dybcio #address-cells = <1>; 1090cf03cd7eSKonrad Dybcio #size-cells = <0>; 1091cf03cd7eSKonrad Dybcio status = "disabled"; 1092cf03cd7eSKonrad Dybcio }; 1093cf03cd7eSKonrad Dybcio 1094cf03cd7eSKonrad Dybcio i2c5: i2c@994000 { 1095cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1096cf03cd7eSKonrad Dybcio reg = <0 0x00994000 0 0x4000>; 1097cf03cd7eSKonrad Dybcio clock-names = "se"; 1098cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1099cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1100cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c5_default>; 1101cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1102ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1103ddc97e7dSBjorn Andersson <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1104ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1105cf03cd7eSKonrad Dybcio #address-cells = <1>; 1106cf03cd7eSKonrad Dybcio #size-cells = <0>; 1107cf03cd7eSKonrad Dybcio status = "disabled"; 1108cf03cd7eSKonrad Dybcio }; 1109cf03cd7eSKonrad Dybcio 1110cf03cd7eSKonrad Dybcio spi5: spi@994000 { 1111cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1112cf03cd7eSKonrad Dybcio reg = <0 0x00994000 0 0x4000>; 1113cf03cd7eSKonrad Dybcio clock-names = "se"; 1114cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1115cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1116cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1117cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1118ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1119ddc97e7dSBjorn Andersson <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1120ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1121cf03cd7eSKonrad Dybcio #address-cells = <1>; 1122cf03cd7eSKonrad Dybcio #size-cells = <0>; 1123cf03cd7eSKonrad Dybcio status = "disabled"; 1124cf03cd7eSKonrad Dybcio }; 1125cf03cd7eSKonrad Dybcio 1126cf03cd7eSKonrad Dybcio i2c6: i2c@998000 { 1127cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1128cf03cd7eSKonrad Dybcio reg = <0 0x00998000 0 0x4000>; 1129cf03cd7eSKonrad Dybcio clock-names = "se"; 1130cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1131cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1132cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c6_default>; 1133cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1134ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1135ddc97e7dSBjorn Andersson <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1136ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1137cf03cd7eSKonrad Dybcio #address-cells = <1>; 1138cf03cd7eSKonrad Dybcio #size-cells = <0>; 1139cf03cd7eSKonrad Dybcio status = "disabled"; 1140cf03cd7eSKonrad Dybcio }; 1141cf03cd7eSKonrad Dybcio 1142cf03cd7eSKonrad Dybcio spi6: spi@998000 { 1143cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1144cf03cd7eSKonrad Dybcio reg = <0 0x00998000 0 0x4000>; 1145cf03cd7eSKonrad Dybcio clock-names = "se"; 1146cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1147cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1148cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1149cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1150ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1151ddc97e7dSBjorn Andersson <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1152ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1153cf03cd7eSKonrad Dybcio #address-cells = <1>; 1154cf03cd7eSKonrad Dybcio #size-cells = <0>; 1155cf03cd7eSKonrad Dybcio status = "disabled"; 1156cf03cd7eSKonrad Dybcio }; 1157cf03cd7eSKonrad Dybcio 1158cf03cd7eSKonrad Dybcio uart6: serial@998000 { 1159cf03cd7eSKonrad Dybcio compatible = "qcom,geni-uart"; 1160cf03cd7eSKonrad Dybcio reg = <0 0x00998000 0 0x4000>; 1161cf03cd7eSKonrad Dybcio clock-names = "se"; 1162cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1163cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1164cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_uart6_default>; 1165cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1166cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1167cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1168cf03cd7eSKonrad Dybcio status = "disabled"; 1169cf03cd7eSKonrad Dybcio }; 1170cf03cd7eSKonrad Dybcio 1171cf03cd7eSKonrad Dybcio i2c7: i2c@99c000 { 1172cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1173cf03cd7eSKonrad Dybcio reg = <0 0x0099c000 0 0x4000>; 1174cf03cd7eSKonrad Dybcio clock-names = "se"; 1175cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1176cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1177cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c7_default>; 1178cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1179ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1180ddc97e7dSBjorn Andersson <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1181ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1182cf03cd7eSKonrad Dybcio #address-cells = <1>; 1183cf03cd7eSKonrad Dybcio #size-cells = <0>; 1184cf03cd7eSKonrad Dybcio status = "disabled"; 1185cf03cd7eSKonrad Dybcio }; 1186cf03cd7eSKonrad Dybcio 1187cf03cd7eSKonrad Dybcio spi7: spi@99c000 { 1188cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1189cf03cd7eSKonrad Dybcio reg = <0 0x0099c000 0 0x4000>; 1190cf03cd7eSKonrad Dybcio clock-names = "se"; 1191cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1192cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1193cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1194cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1195bc08fbf4SBjorn Andersson dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1196bc08fbf4SBjorn Andersson <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1197bc08fbf4SBjorn Andersson dma-names = "tx", "rx"; 1198b7e8f433SVinod Koul #address-cells = <1>; 1199b7e8f433SVinod Koul #size-cells = <0>; 1200b7e8f433SVinod Koul status = "disabled"; 1201b7e8f433SVinod Koul }; 1202b7e8f433SVinod Koul }; 1203b7e8f433SVinod Koul 1204bc08fbf4SBjorn Andersson gpi_dma1: dma-controller@a00000 { 1205b561e225SKrzysztof Kozlowski compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1206bc08fbf4SBjorn Andersson reg = <0 0x00a00000 0 0x60000>; 1207bc08fbf4SBjorn Andersson interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1208bc08fbf4SBjorn Andersson <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1209bc08fbf4SBjorn Andersson <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1210bc08fbf4SBjorn Andersson <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1211bc08fbf4SBjorn Andersson <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1212bc08fbf4SBjorn Andersson <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1213bc08fbf4SBjorn Andersson <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1214bc08fbf4SBjorn Andersson <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1215bc08fbf4SBjorn Andersson <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1216bc08fbf4SBjorn Andersson <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1217bc08fbf4SBjorn Andersson <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1218bc08fbf4SBjorn Andersson <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1219bc08fbf4SBjorn Andersson dma-channels = <12>; 1220bc08fbf4SBjorn Andersson dma-channel-mask = <0xff>; 1221bc08fbf4SBjorn Andersson iommus = <&apps_smmu 0x56 0x0>; 1222bc08fbf4SBjorn Andersson #dma-cells = <3>; 1223bc08fbf4SBjorn Andersson status = "disabled"; 1224bc08fbf4SBjorn Andersson }; 1225bc08fbf4SBjorn Andersson 122606bf656eSJonathan Marek qupv3_id_1: geniqup@ac0000 { 122706bf656eSJonathan Marek compatible = "qcom,geni-se-qup"; 122806bf656eSJonathan Marek reg = <0x0 0x00ac0000 0x0 0x6000>; 122906bf656eSJonathan Marek clock-names = "m-ahb", "s-ahb"; 123006bf656eSJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 123106bf656eSJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12329bc2c8feSKonrad Dybcio iommus = <&apps_smmu 0x43 0>; 123306bf656eSJonathan Marek #address-cells = <2>; 123406bf656eSJonathan Marek #size-cells = <2>; 123506bf656eSJonathan Marek ranges; 123606bf656eSJonathan Marek status = "disabled"; 123706bf656eSJonathan Marek 123889345355SKonrad Dybcio i2c8: i2c@a80000 { 123989345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 124089345355SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 124189345355SKonrad Dybcio clock-names = "se"; 124289345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 124389345355SKonrad Dybcio pinctrl-names = "default"; 124489345355SKonrad Dybcio pinctrl-0 = <&qup_i2c8_default>; 124589345355SKonrad Dybcio interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1246ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1247ddc97e7dSBjorn Andersson <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1248ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 124989345355SKonrad Dybcio #address-cells = <1>; 125089345355SKonrad Dybcio #size-cells = <0>; 125189345355SKonrad Dybcio status = "disabled"; 125289345355SKonrad Dybcio }; 125389345355SKonrad Dybcio 125489345355SKonrad Dybcio spi8: spi@a80000 { 125589345355SKonrad Dybcio compatible = "qcom,geni-spi"; 125689345355SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 125789345355SKonrad Dybcio clock-names = "se"; 125889345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 125989345355SKonrad Dybcio interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 126089345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 126189345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_120mhz>; 1262ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1263ddc97e7dSBjorn Andersson <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1264ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 126589345355SKonrad Dybcio #address-cells = <1>; 126689345355SKonrad Dybcio #size-cells = <0>; 126789345355SKonrad Dybcio status = "disabled"; 126889345355SKonrad Dybcio }; 126989345355SKonrad Dybcio 127089345355SKonrad Dybcio i2c9: i2c@a84000 { 127189345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 127289345355SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 127389345355SKonrad Dybcio clock-names = "se"; 127489345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 127589345355SKonrad Dybcio pinctrl-names = "default"; 127689345355SKonrad Dybcio pinctrl-0 = <&qup_i2c9_default>; 127789345355SKonrad Dybcio interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1278ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1279ddc97e7dSBjorn Andersson <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1280ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 128189345355SKonrad Dybcio #address-cells = <1>; 128289345355SKonrad Dybcio #size-cells = <0>; 128389345355SKonrad Dybcio status = "disabled"; 128489345355SKonrad Dybcio }; 128589345355SKonrad Dybcio 128689345355SKonrad Dybcio spi9: spi@a84000 { 128789345355SKonrad Dybcio compatible = "qcom,geni-spi"; 128889345355SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 128989345355SKonrad Dybcio clock-names = "se"; 129089345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 129189345355SKonrad Dybcio interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 129289345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 129389345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1294ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1295ddc97e7dSBjorn Andersson <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1296ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 129789345355SKonrad Dybcio #address-cells = <1>; 129889345355SKonrad Dybcio #size-cells = <0>; 129989345355SKonrad Dybcio status = "disabled"; 130089345355SKonrad Dybcio }; 130189345355SKonrad Dybcio 130289345355SKonrad Dybcio i2c10: i2c@a88000 { 130389345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 130489345355SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 130589345355SKonrad Dybcio clock-names = "se"; 130689345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 130789345355SKonrad Dybcio pinctrl-names = "default"; 130889345355SKonrad Dybcio pinctrl-0 = <&qup_i2c10_default>; 130989345355SKonrad Dybcio interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1310ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1311ddc97e7dSBjorn Andersson <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1312ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 131389345355SKonrad Dybcio #address-cells = <1>; 131489345355SKonrad Dybcio #size-cells = <0>; 131589345355SKonrad Dybcio status = "disabled"; 131689345355SKonrad Dybcio }; 131789345355SKonrad Dybcio 131889345355SKonrad Dybcio spi10: spi@a88000 { 131989345355SKonrad Dybcio compatible = "qcom,geni-spi"; 132089345355SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 132189345355SKonrad Dybcio clock-names = "se"; 132289345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 132389345355SKonrad Dybcio interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 132489345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 132589345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1326ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1327ddc97e7dSBjorn Andersson <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1328ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 132989345355SKonrad Dybcio #address-cells = <1>; 133089345355SKonrad Dybcio #size-cells = <0>; 133189345355SKonrad Dybcio status = "disabled"; 133289345355SKonrad Dybcio }; 133389345355SKonrad Dybcio 133489345355SKonrad Dybcio i2c11: i2c@a8c000 { 133589345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 133689345355SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 133789345355SKonrad Dybcio clock-names = "se"; 133889345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 133989345355SKonrad Dybcio pinctrl-names = "default"; 134089345355SKonrad Dybcio pinctrl-0 = <&qup_i2c11_default>; 134189345355SKonrad Dybcio interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1342ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1343ddc97e7dSBjorn Andersson <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1344ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 134589345355SKonrad Dybcio #address-cells = <1>; 134689345355SKonrad Dybcio #size-cells = <0>; 134789345355SKonrad Dybcio status = "disabled"; 134889345355SKonrad Dybcio }; 134989345355SKonrad Dybcio 135089345355SKonrad Dybcio spi11: spi@a8c000 { 135189345355SKonrad Dybcio compatible = "qcom,geni-spi"; 135289345355SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 135389345355SKonrad Dybcio clock-names = "se"; 135489345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 135589345355SKonrad Dybcio interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 135689345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 135789345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1358ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1359ddc97e7dSBjorn Andersson <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1360ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 136189345355SKonrad Dybcio #address-cells = <1>; 136289345355SKonrad Dybcio #size-cells = <0>; 136389345355SKonrad Dybcio status = "disabled"; 136489345355SKonrad Dybcio }; 136589345355SKonrad Dybcio 136689345355SKonrad Dybcio i2c12: i2c@a90000 { 136789345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 136889345355SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 136989345355SKonrad Dybcio clock-names = "se"; 137089345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 137189345355SKonrad Dybcio pinctrl-names = "default"; 137289345355SKonrad Dybcio pinctrl-0 = <&qup_i2c12_default>; 137389345355SKonrad Dybcio interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1374ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1375ddc97e7dSBjorn Andersson <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1376ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 137789345355SKonrad Dybcio #address-cells = <1>; 137889345355SKonrad Dybcio #size-cells = <0>; 137989345355SKonrad Dybcio status = "disabled"; 138089345355SKonrad Dybcio }; 138189345355SKonrad Dybcio 138289345355SKonrad Dybcio spi12: spi@a90000 { 138389345355SKonrad Dybcio compatible = "qcom,geni-spi"; 138489345355SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 138589345355SKonrad Dybcio clock-names = "se"; 138689345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 138789345355SKonrad Dybcio interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 138889345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 138989345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1390ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1391ddc97e7dSBjorn Andersson <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1392ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 139389345355SKonrad Dybcio #address-cells = <1>; 139489345355SKonrad Dybcio #size-cells = <0>; 139589345355SKonrad Dybcio status = "disabled"; 139689345355SKonrad Dybcio }; 139789345355SKonrad Dybcio 139806bf656eSJonathan Marek i2c13: i2c@a94000 { 139906bf656eSJonathan Marek compatible = "qcom,geni-i2c"; 140006bf656eSJonathan Marek reg = <0 0x00a94000 0 0x4000>; 140106bf656eSJonathan Marek clock-names = "se"; 140206bf656eSJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 140306bf656eSJonathan Marek pinctrl-names = "default"; 140489345355SKonrad Dybcio pinctrl-0 = <&qup_i2c13_default>; 140506bf656eSJonathan Marek interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1406ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1407ddc97e7dSBjorn Andersson <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1408ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 140906bf656eSJonathan Marek #address-cells = <1>; 141006bf656eSJonathan Marek #size-cells = <0>; 141106bf656eSJonathan Marek status = "disabled"; 141206bf656eSJonathan Marek }; 141389345355SKonrad Dybcio 141489345355SKonrad Dybcio spi13: spi@a94000 { 141589345355SKonrad Dybcio compatible = "qcom,geni-spi"; 141689345355SKonrad Dybcio reg = <0 0x00a94000 0 0x4000>; 141789345355SKonrad Dybcio clock-names = "se"; 141889345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 141989345355SKonrad Dybcio interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 142089345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 142189345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1422ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1423ddc97e7dSBjorn Andersson <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1424ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 142589345355SKonrad Dybcio #address-cells = <1>; 142689345355SKonrad Dybcio #size-cells = <0>; 142789345355SKonrad Dybcio status = "disabled"; 142889345355SKonrad Dybcio }; 142906bf656eSJonathan Marek }; 143006bf656eSJonathan Marek 14311417372fSDmitry Baryshkov rng: rng@10d3000 { 14321417372fSDmitry Baryshkov compatible = "qcom,prng-ee"; 14331417372fSDmitry Baryshkov reg = <0 0x010d3000 0 0x1000>; 14341417372fSDmitry Baryshkov clocks = <&rpmhcc RPMH_HWKM_CLK>; 14351417372fSDmitry Baryshkov clock-names = "core"; 14361417372fSDmitry Baryshkov }; 14371417372fSDmitry Baryshkov 1438da6b2482SVinod Koul config_noc: interconnect@1500000 { 1439da6b2482SVinod Koul compatible = "qcom,sm8350-config-noc"; 1440da6b2482SVinod Koul reg = <0 0x01500000 0 0xa580>; 14414f287e31SRobert Foss #interconnect-cells = <2>; 1442da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1443da6b2482SVinod Koul }; 1444da6b2482SVinod Koul 1445da6b2482SVinod Koul mc_virt: interconnect@1580000 { 1446da6b2482SVinod Koul compatible = "qcom,sm8350-mc-virt"; 1447da6b2482SVinod Koul reg = <0 0x01580000 0 0x1000>; 14484f287e31SRobert Foss #interconnect-cells = <2>; 1449da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1450da6b2482SVinod Koul }; 1451da6b2482SVinod Koul 1452da6b2482SVinod Koul system_noc: interconnect@1680000 { 1453da6b2482SVinod Koul compatible = "qcom,sm8350-system-noc"; 1454da6b2482SVinod Koul reg = <0 0x01680000 0 0x1c200>; 14554f287e31SRobert Foss #interconnect-cells = <2>; 1456da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1457da6b2482SVinod Koul }; 1458da6b2482SVinod Koul 1459da6b2482SVinod Koul aggre1_noc: interconnect@16e0000 { 1460da6b2482SVinod Koul compatible = "qcom,sm8350-aggre1-noc"; 1461da6b2482SVinod Koul reg = <0 0x016e0000 0 0x1f180>; 14624f287e31SRobert Foss #interconnect-cells = <2>; 1463da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1464da6b2482SVinod Koul }; 1465da6b2482SVinod Koul 1466da6b2482SVinod Koul aggre2_noc: interconnect@1700000 { 1467da6b2482SVinod Koul compatible = "qcom,sm8350-aggre2-noc"; 1468da6b2482SVinod Koul reg = <0 0x01700000 0 0x33000>; 14694f287e31SRobert Foss #interconnect-cells = <2>; 1470da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1471da6b2482SVinod Koul }; 1472da6b2482SVinod Koul 1473da6b2482SVinod Koul mmss_noc: interconnect@1740000 { 1474da6b2482SVinod Koul compatible = "qcom,sm8350-mmss-noc"; 1475da6b2482SVinod Koul reg = <0 0x01740000 0 0x1f080>; 14764f287e31SRobert Foss #interconnect-cells = <2>; 1477da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1478da6b2482SVinod Koul }; 1479da6b2482SVinod Koul 14806daee406SDmitry Baryshkov pcie0: pci@1c00000 { 14816daee406SDmitry Baryshkov compatible = "qcom,pcie-sm8350"; 14826daee406SDmitry Baryshkov reg = <0 0x01c00000 0 0x3000>, 14836daee406SDmitry Baryshkov <0 0x60000000 0 0xf1d>, 14846daee406SDmitry Baryshkov <0 0x60000f20 0 0xa8>, 14856daee406SDmitry Baryshkov <0 0x60001000 0 0x1000>, 14866daee406SDmitry Baryshkov <0 0x60100000 0 0x100000>; 14876daee406SDmitry Baryshkov reg-names = "parf", "dbi", "elbi", "atu", "config"; 14886daee406SDmitry Baryshkov device_type = "pci"; 14896daee406SDmitry Baryshkov linux,pci-domain = <0>; 14906daee406SDmitry Baryshkov bus-range = <0x00 0xff>; 14916daee406SDmitry Baryshkov num-lanes = <1>; 14926daee406SDmitry Baryshkov 14936daee406SDmitry Baryshkov #address-cells = <3>; 14946daee406SDmitry Baryshkov #size-cells = <2>; 14956daee406SDmitry Baryshkov 1496cf4e716eSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1497cf4e716eSManivannan Sadhasivam <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 14986daee406SDmitry Baryshkov 14996daee406SDmitry Baryshkov interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 15006daee406SDmitry Baryshkov <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 15016daee406SDmitry Baryshkov <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 15026daee406SDmitry Baryshkov <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 15036daee406SDmitry Baryshkov <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 15046daee406SDmitry Baryshkov <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 15056daee406SDmitry Baryshkov <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 15066daee406SDmitry Baryshkov <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 15076daee406SDmitry Baryshkov interrupt-names = "msi0", "msi1", "msi2", "msi3", 15086daee406SDmitry Baryshkov "msi4", "msi5", "msi6", "msi7"; 15096daee406SDmitry Baryshkov #interrupt-cells = <1>; 15106daee406SDmitry Baryshkov interrupt-map-mask = <0 0 0 0x7>; 15116daee406SDmitry Baryshkov interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 15126daee406SDmitry Baryshkov <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 15136daee406SDmitry Baryshkov <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 15146daee406SDmitry Baryshkov <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 15156daee406SDmitry Baryshkov 15166daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 15176daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 15186daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 15196daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 15206daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 15216daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 15226daee406SDmitry Baryshkov <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 15236daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 15246daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 15256daee406SDmitry Baryshkov clock-names = "aux", 15266daee406SDmitry Baryshkov "cfg", 15276daee406SDmitry Baryshkov "bus_master", 15286daee406SDmitry Baryshkov "bus_slave", 15296daee406SDmitry Baryshkov "slave_q2a", 15306daee406SDmitry Baryshkov "tbu", 15316daee406SDmitry Baryshkov "ddrss_sf_tbu", 15326daee406SDmitry Baryshkov "aggre1", 15336daee406SDmitry Baryshkov "aggre0"; 15346daee406SDmitry Baryshkov 15356daee406SDmitry Baryshkov iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 15366daee406SDmitry Baryshkov <0x100 &apps_smmu 0x1c01 0x1>; 15376daee406SDmitry Baryshkov 15386daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_0_BCR>; 15396daee406SDmitry Baryshkov reset-names = "pci"; 15406daee406SDmitry Baryshkov 15416daee406SDmitry Baryshkov power-domains = <&gcc PCIE_0_GDSC>; 15426daee406SDmitry Baryshkov 15436daee406SDmitry Baryshkov phys = <&pcie0_phy>; 15446daee406SDmitry Baryshkov phy-names = "pciephy"; 15456daee406SDmitry Baryshkov 15466daee406SDmitry Baryshkov status = "disabled"; 15476daee406SDmitry Baryshkov }; 15486daee406SDmitry Baryshkov 15496daee406SDmitry Baryshkov pcie0_phy: phy@1c06000 { 15506daee406SDmitry Baryshkov compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 15516daee406SDmitry Baryshkov reg = <0 0x01c06000 0 0x2000>; 15526daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 15536daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 15546daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_CLKREF_EN>, 15556daee406SDmitry Baryshkov <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 15566daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_PIPE_CLK>; 15576daee406SDmitry Baryshkov clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 15586daee406SDmitry Baryshkov 15596daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_0_PHY_BCR>; 15606daee406SDmitry Baryshkov reset-names = "phy"; 15616daee406SDmitry Baryshkov 15626daee406SDmitry Baryshkov assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 15636daee406SDmitry Baryshkov assigned-clock-rates = <100000000>; 15646daee406SDmitry Baryshkov 15656daee406SDmitry Baryshkov #clock-cells = <0>; 15666daee406SDmitry Baryshkov clock-output-names = "pcie_0_pipe_clk"; 15676daee406SDmitry Baryshkov 15686daee406SDmitry Baryshkov #phy-cells = <0>; 15696daee406SDmitry Baryshkov 15706daee406SDmitry Baryshkov status = "disabled"; 15716daee406SDmitry Baryshkov }; 15726daee406SDmitry Baryshkov 15736daee406SDmitry Baryshkov pcie1: pci@1c08000 { 15746daee406SDmitry Baryshkov compatible = "qcom,pcie-sm8350"; 15756daee406SDmitry Baryshkov reg = <0 0x01c08000 0 0x3000>, 15766daee406SDmitry Baryshkov <0 0x40000000 0 0xf1d>, 15776daee406SDmitry Baryshkov <0 0x40000f20 0 0xa8>, 15786daee406SDmitry Baryshkov <0 0x40001000 0 0x1000>, 15796daee406SDmitry Baryshkov <0 0x40100000 0 0x100000>; 15806daee406SDmitry Baryshkov reg-names = "parf", "dbi", "elbi", "atu", "config"; 15816daee406SDmitry Baryshkov device_type = "pci"; 15826daee406SDmitry Baryshkov linux,pci-domain = <1>; 15836daee406SDmitry Baryshkov bus-range = <0x00 0xff>; 15846daee406SDmitry Baryshkov num-lanes = <2>; 15856daee406SDmitry Baryshkov 15866daee406SDmitry Baryshkov #address-cells = <3>; 15876daee406SDmitry Baryshkov #size-cells = <2>; 15886daee406SDmitry Baryshkov 1589cf4e716eSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1590cf4e716eSManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 15916daee406SDmitry Baryshkov 15926daee406SDmitry Baryshkov interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 15936daee406SDmitry Baryshkov interrupt-names = "msi"; 15946daee406SDmitry Baryshkov #interrupt-cells = <1>; 15956daee406SDmitry Baryshkov interrupt-map-mask = <0 0 0 0x7>; 15966daee406SDmitry Baryshkov interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 15976daee406SDmitry Baryshkov <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 15986daee406SDmitry Baryshkov <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 15996daee406SDmitry Baryshkov <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 16006daee406SDmitry Baryshkov 16016daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 16026daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 16036daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 16046daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 16056daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 16066daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 16076daee406SDmitry Baryshkov <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 16086daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 16096daee406SDmitry Baryshkov clock-names = "aux", 16106daee406SDmitry Baryshkov "cfg", 16116daee406SDmitry Baryshkov "bus_master", 16126daee406SDmitry Baryshkov "bus_slave", 16136daee406SDmitry Baryshkov "slave_q2a", 16146daee406SDmitry Baryshkov "tbu", 16156daee406SDmitry Baryshkov "ddrss_sf_tbu", 16166daee406SDmitry Baryshkov "aggre1"; 16176daee406SDmitry Baryshkov 16186daee406SDmitry Baryshkov iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 16196daee406SDmitry Baryshkov <0x100 &apps_smmu 0x1c81 0x1>; 16206daee406SDmitry Baryshkov 16216daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_1_BCR>; 16226daee406SDmitry Baryshkov reset-names = "pci"; 16236daee406SDmitry Baryshkov 16246daee406SDmitry Baryshkov power-domains = <&gcc PCIE_1_GDSC>; 16256daee406SDmitry Baryshkov 16266daee406SDmitry Baryshkov phys = <&pcie1_phy>; 16276daee406SDmitry Baryshkov phy-names = "pciephy"; 16286daee406SDmitry Baryshkov 16296daee406SDmitry Baryshkov status = "disabled"; 16306daee406SDmitry Baryshkov }; 16316daee406SDmitry Baryshkov 16326daee406SDmitry Baryshkov pcie1_phy: phy@1c0f000 { 16336daee406SDmitry Baryshkov compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 16346daee406SDmitry Baryshkov reg = <0 0x01c0e000 0 0x2000>; 16356daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 16366daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 16376daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_CLKREF_EN>, 16386daee406SDmitry Baryshkov <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 16396daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_PIPE_CLK>; 16406daee406SDmitry Baryshkov clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 16416daee406SDmitry Baryshkov 16426daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_1_PHY_BCR>; 16436daee406SDmitry Baryshkov reset-names = "phy"; 16446daee406SDmitry Baryshkov 16456daee406SDmitry Baryshkov assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 16466daee406SDmitry Baryshkov assigned-clock-rates = <100000000>; 16476daee406SDmitry Baryshkov 16486daee406SDmitry Baryshkov #clock-cells = <0>; 16496daee406SDmitry Baryshkov clock-output-names = "pcie_1_pipe_clk"; 16506daee406SDmitry Baryshkov 16516daee406SDmitry Baryshkov #phy-cells = <0>; 16526daee406SDmitry Baryshkov 16536daee406SDmitry Baryshkov status = "disabled"; 16546daee406SDmitry Baryshkov }; 16556daee406SDmitry Baryshkov 16561417372fSDmitry Baryshkov ufs_mem_hc: ufshc@1d84000 { 16571417372fSDmitry Baryshkov compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 16581417372fSDmitry Baryshkov "jedec,ufs-2.0"; 16591417372fSDmitry Baryshkov reg = <0 0x01d84000 0 0x3000>; 16601417372fSDmitry Baryshkov interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 16611417372fSDmitry Baryshkov phys = <&ufs_mem_phy_lanes>; 16621417372fSDmitry Baryshkov phy-names = "ufsphy"; 16631417372fSDmitry Baryshkov lanes-per-direction = <2>; 16641417372fSDmitry Baryshkov #reset-cells = <1>; 16651417372fSDmitry Baryshkov resets = <&gcc GCC_UFS_PHY_BCR>; 16661417372fSDmitry Baryshkov reset-names = "rst"; 16671417372fSDmitry Baryshkov 16681417372fSDmitry Baryshkov power-domains = <&gcc UFS_PHY_GDSC>; 16691417372fSDmitry Baryshkov 16701417372fSDmitry Baryshkov iommus = <&apps_smmu 0xe0 0x0>; 1671e607b3c1SManivannan Sadhasivam dma-coherent; 16721417372fSDmitry Baryshkov 16731417372fSDmitry Baryshkov clock-names = 16741417372fSDmitry Baryshkov "core_clk", 16751417372fSDmitry Baryshkov "bus_aggr_clk", 16761417372fSDmitry Baryshkov "iface_clk", 16771417372fSDmitry Baryshkov "core_clk_unipro", 16781417372fSDmitry Baryshkov "ref_clk", 16791417372fSDmitry Baryshkov "tx_lane0_sync_clk", 16801417372fSDmitry Baryshkov "rx_lane0_sync_clk", 16811417372fSDmitry Baryshkov "rx_lane1_sync_clk"; 16821417372fSDmitry Baryshkov clocks = 16831417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_AXI_CLK>, 16841417372fSDmitry Baryshkov <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 16851417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_AHB_CLK>, 16861417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 16871417372fSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>, 16881417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 16891417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 16901417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 16911417372fSDmitry Baryshkov freq-table-hz = 16921417372fSDmitry Baryshkov <75000000 300000000>, 16931417372fSDmitry Baryshkov <0 0>, 16941417372fSDmitry Baryshkov <0 0>, 16951417372fSDmitry Baryshkov <75000000 300000000>, 16961417372fSDmitry Baryshkov <0 0>, 16971417372fSDmitry Baryshkov <0 0>, 16981417372fSDmitry Baryshkov <0 0>, 16991417372fSDmitry Baryshkov <0 0>; 17001417372fSDmitry Baryshkov status = "disabled"; 1701da6b2482SVinod Koul }; 1702da6b2482SVinod Koul 17031417372fSDmitry Baryshkov ufs_mem_phy: phy@1d87000 { 17041417372fSDmitry Baryshkov compatible = "qcom,sm8350-qmp-ufs-phy"; 17051417372fSDmitry Baryshkov reg = <0 0x01d87000 0 0x1c4>; 17061417372fSDmitry Baryshkov #address-cells = <2>; 17071417372fSDmitry Baryshkov #size-cells = <2>; 17081417372fSDmitry Baryshkov ranges; 17091417372fSDmitry Baryshkov clock-names = "ref", 17101417372fSDmitry Baryshkov "ref_aux"; 17111417372fSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 17121417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 17131417372fSDmitry Baryshkov 17141417372fSDmitry Baryshkov resets = <&ufs_mem_hc 0>; 17151417372fSDmitry Baryshkov reset-names = "ufsphy"; 17161417372fSDmitry Baryshkov status = "disabled"; 17171417372fSDmitry Baryshkov 17181417372fSDmitry Baryshkov ufs_mem_phy_lanes: phy@1d87400 { 17191417372fSDmitry Baryshkov reg = <0 0x01d87400 0 0x188>, 17201417372fSDmitry Baryshkov <0 0x01d87600 0 0x200>, 17211417372fSDmitry Baryshkov <0 0x01d87c00 0 0x200>, 17221417372fSDmitry Baryshkov <0 0x01d87800 0 0x188>, 17231417372fSDmitry Baryshkov <0 0x01d87a00 0 0x200>; 17241417372fSDmitry Baryshkov #clock-cells = <1>; 17251417372fSDmitry Baryshkov #phy-cells = <0>; 17261417372fSDmitry Baryshkov }; 1727da6b2482SVinod Koul }; 1728da6b2482SVinod Koul 1729f11d3e7dSAlex Elder ipa: ipa@1e40000 { 1730f11d3e7dSAlex Elder compatible = "qcom,sm8350-ipa"; 1731f11d3e7dSAlex Elder 1732f11d3e7dSAlex Elder iommus = <&apps_smmu 0x5c0 0x0>, 1733f11d3e7dSAlex Elder <&apps_smmu 0x5c2 0x0>; 1734f3c08ae6SKonrad Dybcio reg = <0 0x01e40000 0 0x8000>, 1735f3c08ae6SKonrad Dybcio <0 0x01e50000 0 0x4b20>, 1736f3c08ae6SKonrad Dybcio <0 0x01e04000 0 0x23000>; 1737f11d3e7dSAlex Elder reg-names = "ipa-reg", 1738f11d3e7dSAlex Elder "ipa-shared", 1739f11d3e7dSAlex Elder "gsi"; 1740f11d3e7dSAlex Elder 1741f11d3e7dSAlex Elder interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1742f11d3e7dSAlex Elder <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1743f11d3e7dSAlex Elder <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1744f11d3e7dSAlex Elder <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1745f11d3e7dSAlex Elder interrupt-names = "ipa", 1746f11d3e7dSAlex Elder "gsi", 1747f11d3e7dSAlex Elder "ipa-clock-query", 1748f11d3e7dSAlex Elder "ipa-setup-ready"; 1749f11d3e7dSAlex Elder 1750f11d3e7dSAlex Elder clocks = <&rpmhcc RPMH_IPA_CLK>; 1751f11d3e7dSAlex Elder clock-names = "core"; 1752f11d3e7dSAlex Elder 17534f287e31SRobert Foss interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 17544f287e31SRobert Foss <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 175584173ca3SAlex Elder interconnect-names = "memory", 175684173ca3SAlex Elder "config"; 1757f11d3e7dSAlex Elder 175873419e4dSAlex Elder qcom,qmp = <&aoss_qmp>; 175973419e4dSAlex Elder 1760f11d3e7dSAlex Elder qcom,smem-states = <&ipa_smp2p_out 0>, 1761f11d3e7dSAlex Elder <&ipa_smp2p_out 1>; 1762f11d3e7dSAlex Elder qcom,smem-state-names = "ipa-clock-enabled-valid", 1763f11d3e7dSAlex Elder "ipa-clock-enabled"; 1764f11d3e7dSAlex Elder 1765f11d3e7dSAlex Elder status = "disabled"; 1766f11d3e7dSAlex Elder }; 1767f11d3e7dSAlex Elder 1768b7e8f433SVinod Koul tcsr_mutex: hwlock@1f40000 { 1769b7e8f433SVinod Koul compatible = "qcom,tcsr-mutex"; 1770b7e8f433SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 1771b7e8f433SVinod Koul #hwlock-cells = <1>; 1772b7e8f433SVinod Koul }; 1773b7e8f433SVinod Koul 177454af0cebSDmitry Baryshkov gpu: gpu@3d00000 { 177554af0cebSDmitry Baryshkov compatible = "qcom,adreno-660.1", "qcom,adreno"; 177654af0cebSDmitry Baryshkov 177754af0cebSDmitry Baryshkov reg = <0 0x03d00000 0 0x40000>, 177854af0cebSDmitry Baryshkov <0 0x03d9e000 0 0x1000>, 177954af0cebSDmitry Baryshkov <0 0x03d61000 0 0x800>; 178054af0cebSDmitry Baryshkov reg-names = "kgsl_3d0_reg_memory", 178154af0cebSDmitry Baryshkov "cx_mem", 178254af0cebSDmitry Baryshkov "cx_dbgc"; 178354af0cebSDmitry Baryshkov 178454af0cebSDmitry Baryshkov interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 178554af0cebSDmitry Baryshkov 178654af0cebSDmitry Baryshkov iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 178754af0cebSDmitry Baryshkov 178854af0cebSDmitry Baryshkov operating-points-v2 = <&gpu_opp_table>; 178954af0cebSDmitry Baryshkov 179054af0cebSDmitry Baryshkov qcom,gmu = <&gmu>; 179154af0cebSDmitry Baryshkov 179254af0cebSDmitry Baryshkov status = "disabled"; 179354af0cebSDmitry Baryshkov 179454af0cebSDmitry Baryshkov zap-shader { 179554af0cebSDmitry Baryshkov memory-region = <&pil_gpu_mem>; 179654af0cebSDmitry Baryshkov }; 179754af0cebSDmitry Baryshkov 179854af0cebSDmitry Baryshkov /* note: downstream checks gpu binning for 670 Mhz */ 179954af0cebSDmitry Baryshkov gpu_opp_table: opp-table { 180054af0cebSDmitry Baryshkov compatible = "operating-points-v2"; 180154af0cebSDmitry Baryshkov 180254af0cebSDmitry Baryshkov opp-840000000 { 180354af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <840000000>; 180454af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 180554af0cebSDmitry Baryshkov }; 180654af0cebSDmitry Baryshkov 180754af0cebSDmitry Baryshkov opp-778000000 { 180854af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <778000000>; 180954af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 181054af0cebSDmitry Baryshkov }; 181154af0cebSDmitry Baryshkov 181254af0cebSDmitry Baryshkov opp-738000000 { 181354af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <738000000>; 181454af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 181554af0cebSDmitry Baryshkov }; 181654af0cebSDmitry Baryshkov 181754af0cebSDmitry Baryshkov opp-676000000 { 181854af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <676000000>; 181954af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 182054af0cebSDmitry Baryshkov }; 182154af0cebSDmitry Baryshkov 182254af0cebSDmitry Baryshkov opp-608000000 { 182354af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <608000000>; 182454af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 182554af0cebSDmitry Baryshkov }; 182654af0cebSDmitry Baryshkov 182754af0cebSDmitry Baryshkov opp-540000000 { 182854af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <540000000>; 182954af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 183054af0cebSDmitry Baryshkov }; 183154af0cebSDmitry Baryshkov 183254af0cebSDmitry Baryshkov opp-491000000 { 183354af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <491000000>; 183454af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 183554af0cebSDmitry Baryshkov }; 183654af0cebSDmitry Baryshkov 183754af0cebSDmitry Baryshkov opp-443000000 { 183854af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <443000000>; 183954af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 184054af0cebSDmitry Baryshkov }; 184154af0cebSDmitry Baryshkov 184254af0cebSDmitry Baryshkov opp-379000000 { 184354af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <379000000>; 184454af0cebSDmitry Baryshkov opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 184554af0cebSDmitry Baryshkov }; 184654af0cebSDmitry Baryshkov 184754af0cebSDmitry Baryshkov opp-315000000 { 184854af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <315000000>; 184954af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 185054af0cebSDmitry Baryshkov }; 185154af0cebSDmitry Baryshkov }; 185254af0cebSDmitry Baryshkov }; 185354af0cebSDmitry Baryshkov 185454af0cebSDmitry Baryshkov gmu: gmu@3d6a000 { 185554af0cebSDmitry Baryshkov compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 185654af0cebSDmitry Baryshkov 185754af0cebSDmitry Baryshkov reg = <0 0x03d6a000 0 0x34000>, 185854af0cebSDmitry Baryshkov <0 0x03de0000 0 0x10000>, 185954af0cebSDmitry Baryshkov <0 0x0b290000 0 0x10000>; 186054af0cebSDmitry Baryshkov reg-names = "gmu", "rscc", "gmu_pdc"; 186154af0cebSDmitry Baryshkov 186254af0cebSDmitry Baryshkov interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 186354af0cebSDmitry Baryshkov <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 186454af0cebSDmitry Baryshkov interrupt-names = "hfi", "gmu"; 186554af0cebSDmitry Baryshkov 186654af0cebSDmitry Baryshkov clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 186754af0cebSDmitry Baryshkov <&gpucc GPU_CC_CXO_CLK>, 186854af0cebSDmitry Baryshkov <&gcc GCC_DDRSS_GPU_AXI_CLK>, 186954af0cebSDmitry Baryshkov <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 187054af0cebSDmitry Baryshkov <&gpucc GPU_CC_AHB_CLK>, 187154af0cebSDmitry Baryshkov <&gpucc GPU_CC_HUB_CX_INT_CLK>, 187254af0cebSDmitry Baryshkov <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 187354af0cebSDmitry Baryshkov clock-names = "gmu", 187454af0cebSDmitry Baryshkov "cxo", 187554af0cebSDmitry Baryshkov "axi", 187654af0cebSDmitry Baryshkov "memnoc", 187754af0cebSDmitry Baryshkov "ahb", 187854af0cebSDmitry Baryshkov "hub", 187954af0cebSDmitry Baryshkov "smmu_vote"; 188054af0cebSDmitry Baryshkov 188154af0cebSDmitry Baryshkov power-domains = <&gpucc GPU_CX_GDSC>, 188254af0cebSDmitry Baryshkov <&gpucc GPU_GX_GDSC>; 188354af0cebSDmitry Baryshkov power-domain-names = "cx", 188454af0cebSDmitry Baryshkov "gx"; 188554af0cebSDmitry Baryshkov 188654af0cebSDmitry Baryshkov iommus = <&adreno_smmu 5 0x400>; 188754af0cebSDmitry Baryshkov 188854af0cebSDmitry Baryshkov operating-points-v2 = <&gmu_opp_table>; 188954af0cebSDmitry Baryshkov 189054af0cebSDmitry Baryshkov gmu_opp_table: opp-table { 189154af0cebSDmitry Baryshkov compatible = "operating-points-v2"; 189254af0cebSDmitry Baryshkov 189354af0cebSDmitry Baryshkov opp-200000000 { 189454af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 189554af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 189654af0cebSDmitry Baryshkov }; 189754af0cebSDmitry Baryshkov }; 189854af0cebSDmitry Baryshkov }; 189954af0cebSDmitry Baryshkov 190054af0cebSDmitry Baryshkov gpucc: clock-controller@3d90000 { 190154af0cebSDmitry Baryshkov compatible = "qcom,sm8350-gpucc"; 190254af0cebSDmitry Baryshkov reg = <0 0x03d90000 0 0x9000>; 190354af0cebSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 190454af0cebSDmitry Baryshkov <&gcc GCC_GPU_GPLL0_CLK_SRC>, 190554af0cebSDmitry Baryshkov <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 190654af0cebSDmitry Baryshkov clock-names = "bi_tcxo", 190754af0cebSDmitry Baryshkov "gcc_gpu_gpll0_clk_src", 190854af0cebSDmitry Baryshkov "gcc_gpu_gpll0_div_clk_src"; 190954af0cebSDmitry Baryshkov #clock-cells = <1>; 191054af0cebSDmitry Baryshkov #reset-cells = <1>; 191154af0cebSDmitry Baryshkov #power-domain-cells = <1>; 191254af0cebSDmitry Baryshkov }; 191354af0cebSDmitry Baryshkov 191454af0cebSDmitry Baryshkov adreno_smmu: iommu@3da0000 { 191578c61b6bSKonrad Dybcio compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 191678c61b6bSKonrad Dybcio "qcom,smmu-500", "arm,mmu-500"; 191754af0cebSDmitry Baryshkov reg = <0 0x03da0000 0 0x20000>; 191854af0cebSDmitry Baryshkov #iommu-cells = <2>; 191954af0cebSDmitry Baryshkov #global-interrupts = <2>; 192054af0cebSDmitry Baryshkov interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 192154af0cebSDmitry Baryshkov <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 192254af0cebSDmitry Baryshkov <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 192354af0cebSDmitry Baryshkov <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 192454af0cebSDmitry Baryshkov <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 192554af0cebSDmitry Baryshkov <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 192654af0cebSDmitry Baryshkov <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 192754af0cebSDmitry Baryshkov <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 192854af0cebSDmitry Baryshkov <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 192954af0cebSDmitry Baryshkov <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 193054af0cebSDmitry Baryshkov <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 193154af0cebSDmitry Baryshkov <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 193254af0cebSDmitry Baryshkov 193354af0cebSDmitry Baryshkov clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 193454af0cebSDmitry Baryshkov <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 193554af0cebSDmitry Baryshkov <&gpucc GPU_CC_AHB_CLK>, 193654af0cebSDmitry Baryshkov <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 193754af0cebSDmitry Baryshkov <&gpucc GPU_CC_CX_GMU_CLK>, 193854af0cebSDmitry Baryshkov <&gpucc GPU_CC_HUB_CX_INT_CLK>, 193954af0cebSDmitry Baryshkov <&gpucc GPU_CC_HUB_AON_CLK>; 194054af0cebSDmitry Baryshkov clock-names = "bus", 194154af0cebSDmitry Baryshkov "iface", 194254af0cebSDmitry Baryshkov "ahb", 194354af0cebSDmitry Baryshkov "hlos1_vote_gpu_smmu", 194454af0cebSDmitry Baryshkov "cx_gmu", 194554af0cebSDmitry Baryshkov "hub_cx_int", 194654af0cebSDmitry Baryshkov "hub_aon"; 194754af0cebSDmitry Baryshkov 194854af0cebSDmitry Baryshkov power-domains = <&gpucc GPU_CX_GDSC>; 194954af0cebSDmitry Baryshkov dma-coherent; 195054af0cebSDmitry Baryshkov }; 195154af0cebSDmitry Baryshkov 19521417372fSDmitry Baryshkov lpass_ag_noc: interconnect@3c40000 { 19531417372fSDmitry Baryshkov compatible = "qcom,sm8350-lpass-ag-noc"; 19541417372fSDmitry Baryshkov reg = <0 0x03c40000 0 0xf080>; 19551417372fSDmitry Baryshkov #interconnect-cells = <2>; 19561417372fSDmitry Baryshkov qcom,bcm-voters = <&apps_bcm_voter>; 19571417372fSDmitry Baryshkov }; 19581417372fSDmitry Baryshkov 1959177fcf0aSVinod Koul mpss: remoteproc@4080000 { 1960177fcf0aSVinod Koul compatible = "qcom,sm8350-mpss-pas"; 1961177fcf0aSVinod Koul reg = <0x0 0x04080000 0x0 0x4040>; 1962177fcf0aSVinod Koul 1963177fcf0aSVinod Koul interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1964177fcf0aSVinod Koul <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1965177fcf0aSVinod Koul <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1966177fcf0aSVinod Koul <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1967177fcf0aSVinod Koul <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1968177fcf0aSVinod Koul <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1969177fcf0aSVinod Koul interrupt-names = "wdog", "fatal", "ready", "handover", 1970177fcf0aSVinod Koul "stop-ack", "shutdown-ack"; 1971177fcf0aSVinod Koul 1972177fcf0aSVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>; 1973177fcf0aSVinod Koul clock-names = "xo"; 1974177fcf0aSVinod Koul 1975d0e285c3SRobert Foss power-domains = <&rpmhpd SM8350_CX>, 1976d0e285c3SRobert Foss <&rpmhpd SM8350_MSS>; 19776b7cb2d2SSibi Sankar power-domain-names = "cx", "mss"; 1978177fcf0aSVinod Koul 19794f287e31SRobert Foss interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1980da6b2482SVinod Koul 1981177fcf0aSVinod Koul memory-region = <&pil_modem_mem>; 1982177fcf0aSVinod Koul 19836b7cb2d2SSibi Sankar qcom,qmp = <&aoss_qmp>; 19846b7cb2d2SSibi Sankar 1985177fcf0aSVinod Koul qcom,smem-states = <&smp2p_modem_out 0>; 1986177fcf0aSVinod Koul qcom,smem-state-names = "stop"; 1987177fcf0aSVinod Koul 1988177fcf0aSVinod Koul status = "disabled"; 1989177fcf0aSVinod Koul 1990177fcf0aSVinod Koul glink-edge { 1991177fcf0aSVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1992177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP 1993177fcf0aSVinod Koul IRQ_TYPE_EDGE_RISING>; 1994177fcf0aSVinod Koul mboxes = <&ipcc IPCC_CLIENT_MPSS 1995177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP>; 1996177fcf0aSVinod Koul label = "modem"; 1997177fcf0aSVinod Koul qcom,remote-pid = <1>; 1998177fcf0aSVinod Koul }; 1999177fcf0aSVinod Koul }; 2000177fcf0aSVinod Koul 20011417372fSDmitry Baryshkov slpi: remoteproc@5c00000 { 20021417372fSDmitry Baryshkov compatible = "qcom,sm8350-slpi-pas"; 20031417372fSDmitry Baryshkov reg = <0 0x05c00000 0 0x4000>; 20041417372fSDmitry Baryshkov 20051417372fSDmitry Baryshkov interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 20061417372fSDmitry Baryshkov <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 20071417372fSDmitry Baryshkov <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 20081417372fSDmitry Baryshkov <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 20091417372fSDmitry Baryshkov <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 20101417372fSDmitry Baryshkov interrupt-names = "wdog", "fatal", "ready", 20111417372fSDmitry Baryshkov "handover", "stop-ack"; 20121417372fSDmitry Baryshkov 20131417372fSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>; 20141417372fSDmitry Baryshkov clock-names = "xo"; 20151417372fSDmitry Baryshkov 20161417372fSDmitry Baryshkov power-domains = <&rpmhpd SM8350_LCX>, 20171417372fSDmitry Baryshkov <&rpmhpd SM8350_LMX>; 20181417372fSDmitry Baryshkov power-domain-names = "lcx", "lmx"; 20191417372fSDmitry Baryshkov 20201417372fSDmitry Baryshkov memory-region = <&pil_slpi_mem>; 20211417372fSDmitry Baryshkov 20221417372fSDmitry Baryshkov qcom,qmp = <&aoss_qmp>; 20231417372fSDmitry Baryshkov 20241417372fSDmitry Baryshkov qcom,smem-states = <&smp2p_slpi_out 0>; 20251417372fSDmitry Baryshkov qcom,smem-state-names = "stop"; 20261417372fSDmitry Baryshkov 20271417372fSDmitry Baryshkov status = "disabled"; 20281417372fSDmitry Baryshkov 20291417372fSDmitry Baryshkov glink-edge { 20301417372fSDmitry Baryshkov interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 20311417372fSDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP 20321417372fSDmitry Baryshkov IRQ_TYPE_EDGE_RISING>; 20331417372fSDmitry Baryshkov mboxes = <&ipcc IPCC_CLIENT_SLPI 20341417372fSDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP>; 20351417372fSDmitry Baryshkov 20361417372fSDmitry Baryshkov label = "slpi"; 20371417372fSDmitry Baryshkov qcom,remote-pid = <3>; 20381417372fSDmitry Baryshkov 20391417372fSDmitry Baryshkov fastrpc { 20401417372fSDmitry Baryshkov compatible = "qcom,fastrpc"; 20411417372fSDmitry Baryshkov qcom,glink-channels = "fastrpcglink-apps-dsp"; 20421417372fSDmitry Baryshkov label = "sdsp"; 20431417372fSDmitry Baryshkov qcom,non-secure-domain; 20441417372fSDmitry Baryshkov #address-cells = <1>; 20451417372fSDmitry Baryshkov #size-cells = <0>; 20461417372fSDmitry Baryshkov 20471417372fSDmitry Baryshkov compute-cb@1 { 20481417372fSDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 20491417372fSDmitry Baryshkov reg = <1>; 20501417372fSDmitry Baryshkov iommus = <&apps_smmu 0x0541 0x0>; 20511417372fSDmitry Baryshkov }; 20521417372fSDmitry Baryshkov 20531417372fSDmitry Baryshkov compute-cb@2 { 20541417372fSDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 20551417372fSDmitry Baryshkov reg = <2>; 20561417372fSDmitry Baryshkov iommus = <&apps_smmu 0x0542 0x0>; 20571417372fSDmitry Baryshkov }; 20581417372fSDmitry Baryshkov 20591417372fSDmitry Baryshkov compute-cb@3 { 20601417372fSDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 20611417372fSDmitry Baryshkov reg = <3>; 20621417372fSDmitry Baryshkov iommus = <&apps_smmu 0x0543 0x0>; 20631417372fSDmitry Baryshkov /* note: shared-cb = <4> in downstream */ 20641417372fSDmitry Baryshkov }; 20651417372fSDmitry Baryshkov }; 20661417372fSDmitry Baryshkov }; 20671417372fSDmitry Baryshkov }; 20681417372fSDmitry Baryshkov 206906a0676bSKrzysztof Kozlowski sdhc_2: mmc@8804000 { 207060477435SKonrad Dybcio compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 207160477435SKonrad Dybcio reg = <0 0x08804000 0 0x1000>; 207260477435SKonrad Dybcio 207360477435SKonrad Dybcio interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 207460477435SKonrad Dybcio <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 207560477435SKonrad Dybcio interrupt-names = "hc_irq", "pwr_irq"; 207660477435SKonrad Dybcio 207760477435SKonrad Dybcio clocks = <&gcc GCC_SDCC2_AHB_CLK>, 207860477435SKonrad Dybcio <&gcc GCC_SDCC2_APPS_CLK>, 207960477435SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 208060477435SKonrad Dybcio clock-names = "iface", "core", "xo"; 208160477435SKonrad Dybcio resets = <&gcc GCC_SDCC2_BCR>; 2082fc0ff3e7SKrzysztof Kozlowski interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2083fc0ff3e7SKrzysztof Kozlowski <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 208460477435SKonrad Dybcio interconnect-names = "sdhc-ddr","cpu-sdhc"; 208560477435SKonrad Dybcio iommus = <&apps_smmu 0x4a0 0x0>; 208660477435SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 208760477435SKonrad Dybcio operating-points-v2 = <&sdhc2_opp_table>; 208860477435SKonrad Dybcio bus-width = <4>; 208960477435SKonrad Dybcio dma-coherent; 209060477435SKonrad Dybcio 209160477435SKonrad Dybcio status = "disabled"; 209260477435SKonrad Dybcio 209360477435SKonrad Dybcio sdhc2_opp_table: opp-table { 209460477435SKonrad Dybcio compatible = "operating-points-v2"; 209560477435SKonrad Dybcio 209660477435SKonrad Dybcio opp-100000000 { 209760477435SKonrad Dybcio opp-hz = /bits/ 64 <100000000>; 209860477435SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 209960477435SKonrad Dybcio }; 210060477435SKonrad Dybcio 210160477435SKonrad Dybcio opp-202000000 { 210260477435SKonrad Dybcio opp-hz = /bits/ 64 <202000000>; 210360477435SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 210460477435SKonrad Dybcio }; 210560477435SKonrad Dybcio }; 210660477435SKonrad Dybcio }; 210760477435SKonrad Dybcio 2108e780fb31SJack Pham usb_1_hsphy: phy@88e3000 { 2109e780fb31SJack Pham compatible = "qcom,sm8350-usb-hs-phy", 2110e780fb31SJack Pham "qcom,usb-snps-hs-7nm-phy"; 2111e780fb31SJack Pham reg = <0 0x088e3000 0 0x400>; 2112e780fb31SJack Pham status = "disabled"; 2113e780fb31SJack Pham #phy-cells = <0>; 2114e780fb31SJack Pham 2115e780fb31SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 2116e780fb31SJack Pham clock-names = "ref"; 2117e780fb31SJack Pham 21186d91e201SVinod Koul resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2119e780fb31SJack Pham }; 2120e780fb31SJack Pham 2121e780fb31SJack Pham usb_2_hsphy: phy@88e4000 { 2122e780fb31SJack Pham compatible = "qcom,sm8250-usb-hs-phy", 2123e780fb31SJack Pham "qcom,usb-snps-hs-7nm-phy"; 2124e780fb31SJack Pham reg = <0 0x088e4000 0 0x400>; 2125e780fb31SJack Pham status = "disabled"; 2126e780fb31SJack Pham #phy-cells = <0>; 2127e780fb31SJack Pham 2128e780fb31SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 2129e780fb31SJack Pham clock-names = "ref"; 2130e780fb31SJack Pham 21316d91e201SVinod Koul resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2132e780fb31SJack Pham }; 2133e780fb31SJack Pham 21342458a305SNeil Armstrong usb_1_qmpphy: phy@88e9000 { 21352458a305SNeil Armstrong compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 21362458a305SNeil Armstrong reg = <0 0x088e8000 0 0x3000>; 2137e780fb31SJack Pham 21386d91e201SVinod Koul clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2139e780fb31SJack Pham <&rpmhcc RPMH_CXO_CLK>, 21402458a305SNeil Armstrong <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 21412458a305SNeil Armstrong <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 21422458a305SNeil Armstrong clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2143e780fb31SJack Pham 21446d91e201SVinod Koul resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 21456d91e201SVinod Koul <&gcc GCC_USB3_PHY_PRIM_BCR>; 2146e780fb31SJack Pham reset-names = "phy", "common"; 2147e780fb31SJack Pham 21482458a305SNeil Armstrong #clock-cells = <1>; 21492458a305SNeil Armstrong #phy-cells = <1>; 21502458a305SNeil Armstrong 21512458a305SNeil Armstrong status = "disabled"; 2152*d8313125SNeil Armstrong 2153*d8313125SNeil Armstrong ports { 2154*d8313125SNeil Armstrong #address-cells = <1>; 2155*d8313125SNeil Armstrong #size-cells = <0>; 2156*d8313125SNeil Armstrong 2157*d8313125SNeil Armstrong port@0 { 2158*d8313125SNeil Armstrong reg = <0>; 2159*d8313125SNeil Armstrong 2160*d8313125SNeil Armstrong usb_1_qmpphy_out: endpoint { 2161*d8313125SNeil Armstrong }; 2162*d8313125SNeil Armstrong }; 2163*d8313125SNeil Armstrong 2164*d8313125SNeil Armstrong port@1 { 2165*d8313125SNeil Armstrong reg = <1>; 2166*d8313125SNeil Armstrong 2167*d8313125SNeil Armstrong usb_1_qmpphy_usb_ss_in: endpoint { 2168*d8313125SNeil Armstrong }; 2169*d8313125SNeil Armstrong }; 2170*d8313125SNeil Armstrong 2171*d8313125SNeil Armstrong port@2 { 2172*d8313125SNeil Armstrong reg = <2>; 2173*d8313125SNeil Armstrong 2174*d8313125SNeil Armstrong usb_1_qmpphy_dp_in: endpoint { 2175*d8313125SNeil Armstrong }; 2176*d8313125SNeil Armstrong }; 2177*d8313125SNeil Armstrong }; 2178e780fb31SJack Pham }; 2179e780fb31SJack Pham 2180e780fb31SJack Pham usb_2_qmpphy: phy-wrapper@88eb000 { 2181e780fb31SJack Pham compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2182e780fb31SJack Pham reg = <0 0x088eb000 0 0x200>; 2183e780fb31SJack Pham status = "disabled"; 2184e780fb31SJack Pham #address-cells = <2>; 2185e780fb31SJack Pham #size-cells = <2>; 2186e780fb31SJack Pham ranges; 2187e780fb31SJack Pham 21886d91e201SVinod Koul clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2189e780fb31SJack Pham <&rpmhcc RPMH_CXO_CLK>, 21906d91e201SVinod Koul <&gcc GCC_USB3_SEC_CLKREF_EN>, 21916d91e201SVinod Koul <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2192e780fb31SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2193e780fb31SJack Pham 21946d91e201SVinod Koul resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 21956d91e201SVinod Koul <&gcc GCC_USB3_PHY_SEC_BCR>; 2196e780fb31SJack Pham reset-names = "phy", "common"; 2197e780fb31SJack Pham 2198e780fb31SJack Pham usb_2_ssphy: phy@88ebe00 { 2199e780fb31SJack Pham reg = <0 0x088ebe00 0 0x200>, 2200e780fb31SJack Pham <0 0x088ec000 0 0x200>, 2201e780fb31SJack Pham <0 0x088eb200 0 0x1100>; 2202e780fb31SJack Pham #phy-cells = <0>; 2203af551554SJohan Hovold #clock-cells = <0>; 22046d91e201SVinod Koul clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2205e780fb31SJack Pham clock-names = "pipe0"; 2206e780fb31SJack Pham clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2207e780fb31SJack Pham }; 2208e780fb31SJack Pham }; 2209e780fb31SJack Pham 22101dee9e3bSVinod Koul dc_noc: interconnect@90c0000 { 2211da6b2482SVinod Koul compatible = "qcom,sm8350-dc-noc"; 2212da6b2482SVinod Koul reg = <0 0x090c0000 0 0x4200>; 22134f287e31SRobert Foss #interconnect-cells = <2>; 2214da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 2215da6b2482SVinod Koul }; 2216da6b2482SVinod Koul 2217da6b2482SVinod Koul gem_noc: interconnect@9100000 { 2218da6b2482SVinod Koul compatible = "qcom,sm8350-gem-noc"; 2219da6b2482SVinod Koul reg = <0 0x09100000 0 0xb4000>; 22204f287e31SRobert Foss #interconnect-cells = <2>; 2221da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 2222da6b2482SVinod Koul }; 2223da6b2482SVinod Koul 22249ac8999eSKonrad Dybcio system-cache-controller@9200000 { 22259ac8999eSKonrad Dybcio compatible = "qcom,sm8350-llcc"; 22267ae317cbSManivannan Sadhasivam reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 22277ae317cbSManivannan Sadhasivam <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 22287ae317cbSManivannan Sadhasivam <0 0x09600000 0 0x58000>; 22297ae317cbSManivannan Sadhasivam reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 22307ae317cbSManivannan Sadhasivam "llcc3_base", "llcc_broadcast_base"; 22319ac8999eSKonrad Dybcio }; 22329ac8999eSKonrad Dybcio 22331417372fSDmitry Baryshkov compute_noc: interconnect@a0c0000 { 22341417372fSDmitry Baryshkov compatible = "qcom,sm8350-compute-noc"; 22351417372fSDmitry Baryshkov reg = <0 0x0a0c0000 0 0xa180>; 22361417372fSDmitry Baryshkov #interconnect-cells = <2>; 22371417372fSDmitry Baryshkov qcom,bcm-voters = <&apps_bcm_voter>; 22381417372fSDmitry Baryshkov }; 22391417372fSDmitry Baryshkov 2240e780fb31SJack Pham usb_1: usb@a6f8800 { 2241e780fb31SJack Pham compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2242e780fb31SJack Pham reg = <0 0x0a6f8800 0 0x400>; 2243e780fb31SJack Pham status = "disabled"; 2244e780fb31SJack Pham #address-cells = <2>; 2245e780fb31SJack Pham #size-cells = <2>; 2246e780fb31SJack Pham ranges; 2247e780fb31SJack Pham 22486d91e201SVinod Koul clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 22496d91e201SVinod Koul <&gcc GCC_USB30_PRIM_MASTER_CLK>, 22506d91e201SVinod Koul <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 22518d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 22528d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 22538d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 22548d5fd4e4SKrzysztof Kozlowski "core", 22558d5fd4e4SKrzysztof Kozlowski "iface", 22568d5fd4e4SKrzysztof Kozlowski "sleep", 22578d5fd4e4SKrzysztof Kozlowski "mock_utmi"; 2258e780fb31SJack Pham 22596d91e201SVinod Koul assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 22606d91e201SVinod Koul <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2261e780fb31SJack Pham assigned-clock-rates = <19200000>, <200000000>; 2262e780fb31SJack Pham 2263e780fb31SJack Pham interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 22645b7e3499SJohan Hovold <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2265e780fb31SJack Pham <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 22665b7e3499SJohan Hovold <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 22675b7e3499SJohan Hovold interrupt-names = "hs_phy_irq", 22685b7e3499SJohan Hovold "ss_phy_irq", 22695b7e3499SJohan Hovold "dm_hs_phy_irq", 22705b7e3499SJohan Hovold "dp_hs_phy_irq"; 2271e780fb31SJack Pham 22726d91e201SVinod Koul power-domains = <&gcc USB30_PRIM_GDSC>; 2273e780fb31SJack Pham 22746d91e201SVinod Koul resets = <&gcc GCC_USB30_PRIM_BCR>; 2275e780fb31SJack Pham 22762aa2b50dSBhupesh Sharma usb_1_dwc3: usb@a600000 { 2277e780fb31SJack Pham compatible = "snps,dwc3"; 2278e780fb31SJack Pham reg = <0 0x0a600000 0 0xcd00>; 2279e780fb31SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2280e780fb31SJack Pham iommus = <&apps_smmu 0x0 0x0>; 2281e780fb31SJack Pham snps,dis_u2_susphy_quirk; 2282e780fb31SJack Pham snps,dis_enblslpm_quirk; 22832458a305SNeil Armstrong phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2284e780fb31SJack Pham phy-names = "usb2-phy", "usb3-phy"; 228575b81e5aSNeil Armstrong 228675b81e5aSNeil Armstrong ports { 228775b81e5aSNeil Armstrong #address-cells = <1>; 228875b81e5aSNeil Armstrong #size-cells = <0>; 228975b81e5aSNeil Armstrong 229075b81e5aSNeil Armstrong port@0 { 229175b81e5aSNeil Armstrong reg = <0>; 229275b81e5aSNeil Armstrong 229375b81e5aSNeil Armstrong usb_1_dwc3_hs: endpoint { 229475b81e5aSNeil Armstrong }; 229575b81e5aSNeil Armstrong }; 229675b81e5aSNeil Armstrong 229775b81e5aSNeil Armstrong port@1 { 229875b81e5aSNeil Armstrong reg = <1>; 229975b81e5aSNeil Armstrong 230075b81e5aSNeil Armstrong usb_1_dwc3_ss: endpoint { 230175b81e5aSNeil Armstrong }; 230275b81e5aSNeil Armstrong }; 230375b81e5aSNeil Armstrong }; 2304e780fb31SJack Pham }; 2305e780fb31SJack Pham }; 2306e780fb31SJack Pham 2307e780fb31SJack Pham usb_2: usb@a8f8800 { 2308e780fb31SJack Pham compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2309e780fb31SJack Pham reg = <0 0x0a8f8800 0 0x400>; 2310e780fb31SJack Pham status = "disabled"; 2311e780fb31SJack Pham #address-cells = <2>; 2312e780fb31SJack Pham #size-cells = <2>; 2313e780fb31SJack Pham ranges; 2314e780fb31SJack Pham 23156d91e201SVinod Koul clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 23166d91e201SVinod Koul <&gcc GCC_USB30_SEC_MASTER_CLK>, 23176d91e201SVinod Koul <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 23186d91e201SVinod Koul <&gcc GCC_USB30_SEC_SLEEP_CLK>, 23198d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 23206d91e201SVinod Koul <&gcc GCC_USB3_SEC_CLKREF_EN>; 23218d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 23228d5fd4e4SKrzysztof Kozlowski "core", 23238d5fd4e4SKrzysztof Kozlowski "iface", 23248d5fd4e4SKrzysztof Kozlowski "sleep", 23258d5fd4e4SKrzysztof Kozlowski "mock_utmi", 23268d5fd4e4SKrzysztof Kozlowski "xo"; 2327e780fb31SJack Pham 23286d91e201SVinod Koul assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 23296d91e201SVinod Koul <&gcc GCC_USB30_SEC_MASTER_CLK>; 2330e780fb31SJack Pham assigned-clock-rates = <19200000>, <200000000>; 2331e780fb31SJack Pham 2332e780fb31SJack Pham interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 23335b7e3499SJohan Hovold <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2334e780fb31SJack Pham <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 23355b7e3499SJohan Hovold <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 23365b7e3499SJohan Hovold interrupt-names = "hs_phy_irq", 23375b7e3499SJohan Hovold "ss_phy_irq", 23385b7e3499SJohan Hovold "dm_hs_phy_irq", 23395b7e3499SJohan Hovold "dp_hs_phy_irq"; 2340e780fb31SJack Pham 23416d91e201SVinod Koul power-domains = <&gcc USB30_SEC_GDSC>; 2342e780fb31SJack Pham 23436d91e201SVinod Koul resets = <&gcc GCC_USB30_SEC_BCR>; 2344e780fb31SJack Pham 23452aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 2346e780fb31SJack Pham compatible = "snps,dwc3"; 2347e780fb31SJack Pham reg = <0 0x0a800000 0 0xcd00>; 2348e780fb31SJack Pham interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2349e780fb31SJack Pham iommus = <&apps_smmu 0x20 0x0>; 2350e780fb31SJack Pham snps,dis_u2_susphy_quirk; 2351e780fb31SJack Pham snps,dis_enblslpm_quirk; 2352e780fb31SJack Pham phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2353e780fb31SJack Pham phy-names = "usb2-phy", "usb3-phy"; 2354e780fb31SJack Pham }; 2355e780fb31SJack Pham }; 2356177fcf0aSVinod Koul 2357d4a44105SRobert Foss mdss: display-subsystem@ae00000 { 2358d4a44105SRobert Foss compatible = "qcom,sm8350-mdss"; 2359d4a44105SRobert Foss reg = <0 0x0ae00000 0 0x1000>; 2360d4a44105SRobert Foss reg-names = "mdss"; 2361d4a44105SRobert Foss 2362d4a44105SRobert Foss interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2363d4a44105SRobert Foss <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2364d4a44105SRobert Foss interconnect-names = "mdp0-mem", "mdp1-mem"; 2365d4a44105SRobert Foss 2366d4a44105SRobert Foss power-domains = <&dispcc MDSS_GDSC>; 2367d4a44105SRobert Foss resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2368d4a44105SRobert Foss 2369d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2370d4a44105SRobert Foss <&gcc GCC_DISP_HF_AXI_CLK>, 2371d4a44105SRobert Foss <&gcc GCC_DISP_SF_AXI_CLK>, 2372d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_MDP_CLK>; 2373d4a44105SRobert Foss clock-names = "iface", "bus", "nrt_bus", "core"; 2374d4a44105SRobert Foss 2375d4a44105SRobert Foss interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2376d4a44105SRobert Foss interrupt-controller; 2377d4a44105SRobert Foss #interrupt-cells = <1>; 2378d4a44105SRobert Foss 2379d4a44105SRobert Foss iommus = <&apps_smmu 0x820 0x402>; 2380d4a44105SRobert Foss 2381d4a44105SRobert Foss status = "disabled"; 2382d4a44105SRobert Foss 2383d4a44105SRobert Foss #address-cells = <2>; 2384d4a44105SRobert Foss #size-cells = <2>; 2385d4a44105SRobert Foss ranges; 2386d4a44105SRobert Foss 2387d4a44105SRobert Foss dpu_opp_table: opp-table { 2388d4a44105SRobert Foss compatible = "operating-points-v2"; 2389d4a44105SRobert Foss 2390d4a44105SRobert Foss /* TODO: opp-200000000 should work with 2391d4a44105SRobert Foss * &rpmhpd_opp_low_svs, but one some of 2392d4a44105SRobert Foss * sm8350_hdk boards reboot using this 2393d4a44105SRobert Foss * opp. 2394d4a44105SRobert Foss */ 2395d4a44105SRobert Foss opp-200000000 { 2396d4a44105SRobert Foss opp-hz = /bits/ 64 <200000000>; 2397d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2398d4a44105SRobert Foss }; 2399d4a44105SRobert Foss 2400d4a44105SRobert Foss opp-300000000 { 2401d4a44105SRobert Foss opp-hz = /bits/ 64 <300000000>; 2402d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2403d4a44105SRobert Foss }; 2404d4a44105SRobert Foss 2405d4a44105SRobert Foss opp-345000000 { 2406d4a44105SRobert Foss opp-hz = /bits/ 64 <345000000>; 2407d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs_l1>; 2408d4a44105SRobert Foss }; 2409d4a44105SRobert Foss 2410d4a44105SRobert Foss opp-460000000 { 2411d4a44105SRobert Foss opp-hz = /bits/ 64 <460000000>; 2412d4a44105SRobert Foss required-opps = <&rpmhpd_opp_nom>; 2413d4a44105SRobert Foss }; 2414d4a44105SRobert Foss }; 2415d4a44105SRobert Foss 2416d4a44105SRobert Foss mdss_mdp: display-controller@ae01000 { 2417d4a44105SRobert Foss compatible = "qcom,sm8350-dpu"; 2418d4a44105SRobert Foss reg = <0 0x0ae01000 0 0x8f000>, 2419d4a44105SRobert Foss <0 0x0aeb0000 0 0x2008>; 2420d4a44105SRobert Foss reg-names = "mdp", "vbif"; 2421d4a44105SRobert Foss 2422d4a44105SRobert Foss clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2423d4a44105SRobert Foss <&gcc GCC_DISP_SF_AXI_CLK>, 2424d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_AHB_CLK>, 2425d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2426d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_MDP_CLK>, 2427d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2428d4a44105SRobert Foss clock-names = "bus", 2429d4a44105SRobert Foss "nrt_bus", 2430d4a44105SRobert Foss "iface", 2431d4a44105SRobert Foss "lut", 2432d4a44105SRobert Foss "core", 2433d4a44105SRobert Foss "vsync"; 2434d4a44105SRobert Foss 2435d4a44105SRobert Foss assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2436d4a44105SRobert Foss assigned-clock-rates = <19200000>; 2437d4a44105SRobert Foss 2438d4a44105SRobert Foss operating-points-v2 = <&dpu_opp_table>; 2439d4a44105SRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 2440d4a44105SRobert Foss 2441d4a44105SRobert Foss interrupt-parent = <&mdss>; 2442d4a44105SRobert Foss interrupts = <0>; 2443d4a44105SRobert Foss 2444d4a44105SRobert Foss ports { 2445d4a44105SRobert Foss #address-cells = <1>; 2446d4a44105SRobert Foss #size-cells = <0>; 2447d4a44105SRobert Foss 2448d4a44105SRobert Foss port@0 { 2449d4a44105SRobert Foss reg = <0>; 2450d4a44105SRobert Foss dpu_intf1_out: endpoint { 24512a07efb8SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 2452d4a44105SRobert Foss }; 2453d4a44105SRobert Foss }; 2454b904227aSKonrad Dybcio 2455b904227aSKonrad Dybcio port@1 { 2456b904227aSKonrad Dybcio reg = <1>; 2457b904227aSKonrad Dybcio dpu_intf2_out: endpoint { 2458b904227aSKonrad Dybcio remote-endpoint = <&mdss_dsi1_in>; 2459b904227aSKonrad Dybcio }; 2460b904227aSKonrad Dybcio }; 2461a2802008SNeil Armstrong 2462a2802008SNeil Armstrong port@2 { 2463a2802008SNeil Armstrong reg = <2>; 2464a2802008SNeil Armstrong dpu_intf0_out: endpoint { 2465a2802008SNeil Armstrong remote-endpoint = <&mdss_dp_in>; 2466a2802008SNeil Armstrong }; 2467a2802008SNeil Armstrong }; 2468a2802008SNeil Armstrong }; 2469a2802008SNeil Armstrong }; 2470a2802008SNeil Armstrong 2471a2802008SNeil Armstrong mdss_dp: displayport-controller@ae90000 { 2472a2802008SNeil Armstrong compatible = "qcom,sm8350-dp"; 2473a2802008SNeil Armstrong reg = <0 0xae90000 0 0x200>, 2474a2802008SNeil Armstrong <0 0xae90200 0 0x200>, 2475a2802008SNeil Armstrong <0 0xae90400 0 0x600>, 2476a2802008SNeil Armstrong <0 0xae91000 0 0x400>, 2477a2802008SNeil Armstrong <0 0xae91400 0 0x400>; 2478a2802008SNeil Armstrong interrupt-parent = <&mdss>; 2479a2802008SNeil Armstrong interrupts = <12>; 2480a2802008SNeil Armstrong clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2481a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2482a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2483a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2484a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2485a2802008SNeil Armstrong clock-names = "core_iface", 2486a2802008SNeil Armstrong "core_aux", 2487a2802008SNeil Armstrong "ctrl_link", 2488a2802008SNeil Armstrong "ctrl_link_iface", 2489a2802008SNeil Armstrong "stream_pixel"; 2490a2802008SNeil Armstrong 2491a2802008SNeil Armstrong assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2492a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2493a2802008SNeil Armstrong assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2494a2802008SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2495a2802008SNeil Armstrong 2496a2802008SNeil Armstrong phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2497a2802008SNeil Armstrong phy-names = "dp"; 2498a2802008SNeil Armstrong 2499a2802008SNeil Armstrong #sound-dai-cells = <0>; 2500a2802008SNeil Armstrong 2501a2802008SNeil Armstrong operating-points-v2 = <&dp_opp_table>; 2502a2802008SNeil Armstrong power-domains = <&rpmhpd SM8350_MMCX>; 2503a2802008SNeil Armstrong 2504a2802008SNeil Armstrong status = "disabled"; 2505a2802008SNeil Armstrong 2506a2802008SNeil Armstrong ports { 2507a2802008SNeil Armstrong #address-cells = <1>; 2508a2802008SNeil Armstrong #size-cells = <0>; 2509a2802008SNeil Armstrong 2510a2802008SNeil Armstrong port@0 { 2511a2802008SNeil Armstrong reg = <0>; 2512a2802008SNeil Armstrong mdss_dp_in: endpoint { 2513a2802008SNeil Armstrong remote-endpoint = <&dpu_intf0_out>; 2514a2802008SNeil Armstrong }; 2515a2802008SNeil Armstrong }; 2516a2802008SNeil Armstrong }; 2517a2802008SNeil Armstrong 2518a2802008SNeil Armstrong dp_opp_table: opp-table { 2519a2802008SNeil Armstrong compatible = "operating-points-v2"; 2520a2802008SNeil Armstrong 2521a2802008SNeil Armstrong opp-160000000 { 2522a2802008SNeil Armstrong opp-hz = /bits/ 64 <160000000>; 2523a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_low_svs>; 2524a2802008SNeil Armstrong }; 2525a2802008SNeil Armstrong 2526a2802008SNeil Armstrong opp-270000000 { 2527a2802008SNeil Armstrong opp-hz = /bits/ 64 <270000000>; 2528a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_svs>; 2529a2802008SNeil Armstrong }; 2530a2802008SNeil Armstrong 2531a2802008SNeil Armstrong opp-540000000 { 2532a2802008SNeil Armstrong opp-hz = /bits/ 64 <540000000>; 2533a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_svs_l1>; 2534a2802008SNeil Armstrong }; 2535a2802008SNeil Armstrong 2536a2802008SNeil Armstrong opp-810000000 { 2537a2802008SNeil Armstrong opp-hz = /bits/ 64 <810000000>; 2538a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_nom>; 2539a2802008SNeil Armstrong }; 2540d4a44105SRobert Foss }; 2541d4a44105SRobert Foss }; 2542d4a44105SRobert Foss 2543d4a44105SRobert Foss mdss_dsi0: dsi@ae94000 { 2544d7133d6dSDmitry Baryshkov compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2545d4a44105SRobert Foss reg = <0 0x0ae94000 0 0x400>; 2546d4a44105SRobert Foss reg-names = "dsi_ctrl"; 2547d4a44105SRobert Foss 2548d4a44105SRobert Foss interrupt-parent = <&mdss>; 2549d4a44105SRobert Foss interrupts = <4>; 2550d4a44105SRobert Foss 2551d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2552d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2553d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2554d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2555d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_AHB_CLK>, 2556d4a44105SRobert Foss <&gcc GCC_DISP_HF_AXI_CLK>; 2557d4a44105SRobert Foss clock-names = "byte", 2558d4a44105SRobert Foss "byte_intf", 2559d4a44105SRobert Foss "pixel", 2560d4a44105SRobert Foss "core", 2561d4a44105SRobert Foss "iface", 2562d4a44105SRobert Foss "bus"; 2563d4a44105SRobert Foss 2564d4a44105SRobert Foss assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2565d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2566d4a44105SRobert Foss assigned-clock-parents = <&mdss_dsi0_phy 0>, 2567d4a44105SRobert Foss <&mdss_dsi0_phy 1>; 2568d4a44105SRobert Foss 2569d4a44105SRobert Foss operating-points-v2 = <&dsi0_opp_table>; 2570d4a44105SRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 2571d4a44105SRobert Foss 2572d4a44105SRobert Foss phys = <&mdss_dsi0_phy>; 2573d4a44105SRobert Foss 25746636818eSKonrad Dybcio #address-cells = <1>; 25756636818eSKonrad Dybcio #size-cells = <0>; 25766636818eSKonrad Dybcio 2577d4a44105SRobert Foss status = "disabled"; 2578d4a44105SRobert Foss 2579d4a44105SRobert Foss dsi0_opp_table: opp-table { 2580d4a44105SRobert Foss compatible = "operating-points-v2"; 2581d4a44105SRobert Foss 2582d4a44105SRobert Foss /* TODO: opp-187500000 should work with 2583d4a44105SRobert Foss * &rpmhpd_opp_low_svs, but one some of 2584d4a44105SRobert Foss * sm8350_hdk boards reboot using this 2585d4a44105SRobert Foss * opp. 2586d4a44105SRobert Foss */ 2587d4a44105SRobert Foss opp-187500000 { 2588d4a44105SRobert Foss opp-hz = /bits/ 64 <187500000>; 2589d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2590d4a44105SRobert Foss }; 2591d4a44105SRobert Foss 2592d4a44105SRobert Foss opp-300000000 { 2593d4a44105SRobert Foss opp-hz = /bits/ 64 <300000000>; 2594d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2595d4a44105SRobert Foss }; 2596d4a44105SRobert Foss 2597d4a44105SRobert Foss opp-358000000 { 2598d4a44105SRobert Foss opp-hz = /bits/ 64 <358000000>; 2599d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs_l1>; 2600d4a44105SRobert Foss }; 2601d4a44105SRobert Foss }; 2602d4a44105SRobert Foss 2603d4a44105SRobert Foss ports { 2604d4a44105SRobert Foss #address-cells = <1>; 2605d4a44105SRobert Foss #size-cells = <0>; 2606d4a44105SRobert Foss 2607d4a44105SRobert Foss port@0 { 2608d4a44105SRobert Foss reg = <0>; 26092a07efb8SKonrad Dybcio mdss_dsi0_in: endpoint { 2610d4a44105SRobert Foss remote-endpoint = <&dpu_intf1_out>; 2611d4a44105SRobert Foss }; 2612d4a44105SRobert Foss }; 2613d4a44105SRobert Foss 2614d4a44105SRobert Foss port@1 { 2615d4a44105SRobert Foss reg = <1>; 26162a07efb8SKonrad Dybcio mdss_dsi0_out: endpoint { 2617d4a44105SRobert Foss }; 2618d4a44105SRobert Foss }; 2619d4a44105SRobert Foss }; 2620d4a44105SRobert Foss }; 2621d4a44105SRobert Foss 2622d4a44105SRobert Foss mdss_dsi0_phy: phy@ae94400 { 262345cd807dSKonrad Dybcio compatible = "qcom,sm8350-dsi-phy-5nm"; 2624d4a44105SRobert Foss reg = <0 0x0ae94400 0 0x200>, 2625d4a44105SRobert Foss <0 0x0ae94600 0 0x280>, 2626e3e654ceSKonrad Dybcio <0 0x0ae94900 0 0x27c>; 2627d4a44105SRobert Foss reg-names = "dsi_phy", 2628d4a44105SRobert Foss "dsi_phy_lane", 2629d4a44105SRobert Foss "dsi_pll"; 2630d4a44105SRobert Foss 2631d4a44105SRobert Foss #clock-cells = <1>; 2632d4a44105SRobert Foss #phy-cells = <0>; 2633d4a44105SRobert Foss 2634d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2635d4a44105SRobert Foss <&rpmhcc RPMH_CXO_CLK>; 2636d4a44105SRobert Foss clock-names = "iface", "ref"; 2637d4a44105SRobert Foss 2638d4a44105SRobert Foss status = "disabled"; 2639d4a44105SRobert Foss }; 2640d4a44105SRobert Foss 2641d4a44105SRobert Foss mdss_dsi1: dsi@ae96000 { 2642d7133d6dSDmitry Baryshkov compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2643d4a44105SRobert Foss reg = <0 0x0ae96000 0 0x400>; 2644d4a44105SRobert Foss reg-names = "dsi_ctrl"; 2645d4a44105SRobert Foss 2646d4a44105SRobert Foss interrupt-parent = <&mdss>; 26471eed7995SKonrad Dybcio interrupts = <5>; 2648d4a44105SRobert Foss 2649d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2650d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2651d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2652d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2653d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_AHB_CLK>, 2654d4a44105SRobert Foss <&gcc GCC_DISP_HF_AXI_CLK>; 2655d4a44105SRobert Foss clock-names = "byte", 2656d4a44105SRobert Foss "byte_intf", 2657d4a44105SRobert Foss "pixel", 2658d4a44105SRobert Foss "core", 2659d4a44105SRobert Foss "iface", 2660d4a44105SRobert Foss "bus"; 2661d4a44105SRobert Foss 2662d4a44105SRobert Foss assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2663d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2664d4a44105SRobert Foss assigned-clock-parents = <&mdss_dsi1_phy 0>, 2665d4a44105SRobert Foss <&mdss_dsi1_phy 1>; 2666d4a44105SRobert Foss 2667d4a44105SRobert Foss operating-points-v2 = <&dsi1_opp_table>; 2668d4a44105SRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 2669d4a44105SRobert Foss 2670d4a44105SRobert Foss phys = <&mdss_dsi1_phy>; 2671d4a44105SRobert Foss 26726636818eSKonrad Dybcio #address-cells = <1>; 26736636818eSKonrad Dybcio #size-cells = <0>; 26746636818eSKonrad Dybcio 2675d4a44105SRobert Foss status = "disabled"; 2676d4a44105SRobert Foss 2677d4a44105SRobert Foss dsi1_opp_table: opp-table { 2678d4a44105SRobert Foss compatible = "operating-points-v2"; 2679d4a44105SRobert Foss 2680d4a44105SRobert Foss /* TODO: opp-187500000 should work with 2681d4a44105SRobert Foss * &rpmhpd_opp_low_svs, but one some of 2682d4a44105SRobert Foss * sm8350_hdk boards reboot using this 2683d4a44105SRobert Foss * opp. 2684d4a44105SRobert Foss */ 2685d4a44105SRobert Foss opp-187500000 { 2686d4a44105SRobert Foss opp-hz = /bits/ 64 <187500000>; 2687d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2688d4a44105SRobert Foss }; 2689d4a44105SRobert Foss 2690d4a44105SRobert Foss opp-300000000 { 2691d4a44105SRobert Foss opp-hz = /bits/ 64 <300000000>; 2692d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2693d4a44105SRobert Foss }; 2694d4a44105SRobert Foss 2695d4a44105SRobert Foss opp-358000000 { 2696d4a44105SRobert Foss opp-hz = /bits/ 64 <358000000>; 2697d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs_l1>; 2698d4a44105SRobert Foss }; 2699d4a44105SRobert Foss }; 2700d4a44105SRobert Foss 2701d4a44105SRobert Foss ports { 2702d4a44105SRobert Foss #address-cells = <1>; 2703d4a44105SRobert Foss #size-cells = <0>; 2704d4a44105SRobert Foss 2705d4a44105SRobert Foss port@0 { 2706d4a44105SRobert Foss reg = <0>; 27072a07efb8SKonrad Dybcio mdss_dsi1_in: endpoint { 2708b904227aSKonrad Dybcio remote-endpoint = <&dpu_intf2_out>; 2709d4a44105SRobert Foss }; 2710d4a44105SRobert Foss }; 2711d4a44105SRobert Foss 2712d4a44105SRobert Foss port@1 { 2713d4a44105SRobert Foss reg = <1>; 27142a07efb8SKonrad Dybcio mdss_dsi1_out: endpoint { 2715d4a44105SRobert Foss }; 2716d4a44105SRobert Foss }; 2717d4a44105SRobert Foss }; 2718d4a44105SRobert Foss }; 2719d4a44105SRobert Foss 2720d4a44105SRobert Foss mdss_dsi1_phy: phy@ae96400 { 272145cd807dSKonrad Dybcio compatible = "qcom,sm8350-dsi-phy-5nm"; 2722d4a44105SRobert Foss reg = <0 0x0ae96400 0 0x200>, 2723d4a44105SRobert Foss <0 0x0ae96600 0 0x280>, 2724e3e654ceSKonrad Dybcio <0 0x0ae96900 0 0x27c>; 2725d4a44105SRobert Foss reg-names = "dsi_phy", 2726d4a44105SRobert Foss "dsi_phy_lane", 2727d4a44105SRobert Foss "dsi_pll"; 2728d4a44105SRobert Foss 2729d4a44105SRobert Foss #clock-cells = <1>; 2730d4a44105SRobert Foss #phy-cells = <0>; 2731d4a44105SRobert Foss 2732d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2733d4a44105SRobert Foss <&rpmhcc RPMH_CXO_CLK>; 2734d4a44105SRobert Foss clock-names = "iface", "ref"; 2735d4a44105SRobert Foss 2736d4a44105SRobert Foss status = "disabled"; 2737d4a44105SRobert Foss }; 2738d4a44105SRobert Foss }; 2739d4a44105SRobert Foss 27409fd4887cSRobert Foss dispcc: clock-controller@af00000 { 27419fd4887cSRobert Foss compatible = "qcom,sm8350-dispcc"; 27429fd4887cSRobert Foss reg = <0 0x0af00000 0 0x10000>; 27439fd4887cSRobert Foss clocks = <&rpmhcc RPMH_CXO_CLK>, 2744d4a44105SRobert Foss <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 27450af6a401SKonrad Dybcio <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 27462458a305SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 27472458a305SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 27489fd4887cSRobert Foss clock-names = "bi_tcxo", 27499fd4887cSRobert Foss "dsi0_phy_pll_out_byteclk", 27509fd4887cSRobert Foss "dsi0_phy_pll_out_dsiclk", 27519fd4887cSRobert Foss "dsi1_phy_pll_out_byteclk", 27529fd4887cSRobert Foss "dsi1_phy_pll_out_dsiclk", 27539fd4887cSRobert Foss "dp_phy_pll_link_clk", 27549fd4887cSRobert Foss "dp_phy_pll_vco_div_clk"; 27559fd4887cSRobert Foss #clock-cells = <1>; 27569fd4887cSRobert Foss #reset-cells = <1>; 27579fd4887cSRobert Foss #power-domain-cells = <1>; 27589fd4887cSRobert Foss 27599fd4887cSRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 27609fd4887cSRobert Foss }; 27619fd4887cSRobert Foss 276251f83fbbSDmitry Baryshkov pdc: interrupt-controller@b220000 { 276351f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-pdc", "qcom,pdc"; 276451f83fbbSDmitry Baryshkov reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 276551f83fbbSDmitry Baryshkov qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 276651f83fbbSDmitry Baryshkov <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 276751f83fbbSDmitry Baryshkov <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 276851f83fbbSDmitry Baryshkov <156 716 12>; 276951f83fbbSDmitry Baryshkov #interrupt-cells = <2>; 277051f83fbbSDmitry Baryshkov interrupt-parent = <&intc>; 277151f83fbbSDmitry Baryshkov interrupt-controller; 277251f83fbbSDmitry Baryshkov }; 277351f83fbbSDmitry Baryshkov 277451f83fbbSDmitry Baryshkov tsens0: thermal-sensor@c263000 { 277551f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 277651f83fbbSDmitry Baryshkov reg = <0 0x0c263000 0 0x1ff>, /* TM */ 277751f83fbbSDmitry Baryshkov <0 0x0c222000 0 0x8>; /* SROT */ 277851f83fbbSDmitry Baryshkov #qcom,sensors = <15>; 277951f83fbbSDmitry Baryshkov interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 278051f83fbbSDmitry Baryshkov <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 278151f83fbbSDmitry Baryshkov interrupt-names = "uplow", "critical"; 278251f83fbbSDmitry Baryshkov #thermal-sensor-cells = <1>; 278351f83fbbSDmitry Baryshkov }; 278451f83fbbSDmitry Baryshkov 278551f83fbbSDmitry Baryshkov tsens1: thermal-sensor@c265000 { 278651f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 278751f83fbbSDmitry Baryshkov reg = <0 0x0c265000 0 0x1ff>, /* TM */ 278851f83fbbSDmitry Baryshkov <0 0x0c223000 0 0x8>; /* SROT */ 278951f83fbbSDmitry Baryshkov #qcom,sensors = <14>; 279051f83fbbSDmitry Baryshkov interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 279151f83fbbSDmitry Baryshkov <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 279251f83fbbSDmitry Baryshkov interrupt-names = "uplow", "critical"; 279351f83fbbSDmitry Baryshkov #thermal-sensor-cells = <1>; 279451f83fbbSDmitry Baryshkov }; 279551f83fbbSDmitry Baryshkov 279651f83fbbSDmitry Baryshkov aoss_qmp: power-management@c300000 { 279751f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 279851f83fbbSDmitry Baryshkov reg = <0 0x0c300000 0 0x400>; 279951f83fbbSDmitry Baryshkov interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 280051f83fbbSDmitry Baryshkov IRQ_TYPE_EDGE_RISING>; 280151f83fbbSDmitry Baryshkov mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 280251f83fbbSDmitry Baryshkov 280351f83fbbSDmitry Baryshkov #clock-cells = <0>; 280451f83fbbSDmitry Baryshkov }; 280551f83fbbSDmitry Baryshkov 280651f83fbbSDmitry Baryshkov sram@c3f0000 { 280751f83fbbSDmitry Baryshkov compatible = "qcom,rpmh-stats"; 280851f83fbbSDmitry Baryshkov reg = <0 0x0c3f0000 0 0x400>; 280951f83fbbSDmitry Baryshkov }; 281051f83fbbSDmitry Baryshkov 281151f83fbbSDmitry Baryshkov spmi_bus: spmi@c440000 { 281251f83fbbSDmitry Baryshkov compatible = "qcom,spmi-pmic-arb"; 281351f83fbbSDmitry Baryshkov reg = <0x0 0x0c440000 0x0 0x1100>, 281451f83fbbSDmitry Baryshkov <0x0 0x0c600000 0x0 0x2000000>, 281551f83fbbSDmitry Baryshkov <0x0 0x0e600000 0x0 0x100000>, 281651f83fbbSDmitry Baryshkov <0x0 0x0e700000 0x0 0xa0000>, 281751f83fbbSDmitry Baryshkov <0x0 0x0c40a000 0x0 0x26000>; 281851f83fbbSDmitry Baryshkov reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 281951f83fbbSDmitry Baryshkov interrupt-names = "periph_irq"; 282051f83fbbSDmitry Baryshkov interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 282151f83fbbSDmitry Baryshkov qcom,ee = <0>; 282251f83fbbSDmitry Baryshkov qcom,channel = <0>; 282351f83fbbSDmitry Baryshkov #address-cells = <2>; 282451f83fbbSDmitry Baryshkov #size-cells = <0>; 282551f83fbbSDmitry Baryshkov interrupt-controller; 282651f83fbbSDmitry Baryshkov #interrupt-cells = <4>; 282751f83fbbSDmitry Baryshkov }; 282851f83fbbSDmitry Baryshkov 282951f83fbbSDmitry Baryshkov tlmm: pinctrl@f100000 { 283051f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-tlmm"; 283151f83fbbSDmitry Baryshkov reg = <0 0x0f100000 0 0x300000>; 283251f83fbbSDmitry Baryshkov interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 283351f83fbbSDmitry Baryshkov gpio-controller; 283451f83fbbSDmitry Baryshkov #gpio-cells = <2>; 283551f83fbbSDmitry Baryshkov interrupt-controller; 283651f83fbbSDmitry Baryshkov #interrupt-cells = <2>; 283751f83fbbSDmitry Baryshkov gpio-ranges = <&tlmm 0 0 204>; 283851f83fbbSDmitry Baryshkov wakeup-parent = <&pdc>; 283951f83fbbSDmitry Baryshkov 284051f83fbbSDmitry Baryshkov sdc2_default_state: sdc2-default-state { 284151f83fbbSDmitry Baryshkov clk-pins { 284251f83fbbSDmitry Baryshkov pins = "sdc2_clk"; 284351f83fbbSDmitry Baryshkov drive-strength = <16>; 284451f83fbbSDmitry Baryshkov bias-disable; 284551f83fbbSDmitry Baryshkov }; 284651f83fbbSDmitry Baryshkov 284751f83fbbSDmitry Baryshkov cmd-pins { 284851f83fbbSDmitry Baryshkov pins = "sdc2_cmd"; 284951f83fbbSDmitry Baryshkov drive-strength = <16>; 285051f83fbbSDmitry Baryshkov bias-pull-up; 285151f83fbbSDmitry Baryshkov }; 285251f83fbbSDmitry Baryshkov 285351f83fbbSDmitry Baryshkov data-pins { 285451f83fbbSDmitry Baryshkov pins = "sdc2_data"; 285551f83fbbSDmitry Baryshkov drive-strength = <16>; 285651f83fbbSDmitry Baryshkov bias-pull-up; 285751f83fbbSDmitry Baryshkov }; 285851f83fbbSDmitry Baryshkov }; 285951f83fbbSDmitry Baryshkov 286051f83fbbSDmitry Baryshkov sdc2_sleep_state: sdc2-sleep-state { 286151f83fbbSDmitry Baryshkov clk-pins { 286251f83fbbSDmitry Baryshkov pins = "sdc2_clk"; 286351f83fbbSDmitry Baryshkov drive-strength = <2>; 286451f83fbbSDmitry Baryshkov bias-disable; 286551f83fbbSDmitry Baryshkov }; 286651f83fbbSDmitry Baryshkov 286751f83fbbSDmitry Baryshkov cmd-pins { 286851f83fbbSDmitry Baryshkov pins = "sdc2_cmd"; 286951f83fbbSDmitry Baryshkov drive-strength = <2>; 287051f83fbbSDmitry Baryshkov bias-pull-up; 287151f83fbbSDmitry Baryshkov }; 287251f83fbbSDmitry Baryshkov 287351f83fbbSDmitry Baryshkov data-pins { 287451f83fbbSDmitry Baryshkov pins = "sdc2_data"; 287551f83fbbSDmitry Baryshkov drive-strength = <2>; 287651f83fbbSDmitry Baryshkov bias-pull-up; 287751f83fbbSDmitry Baryshkov }; 287851f83fbbSDmitry Baryshkov }; 287951f83fbbSDmitry Baryshkov 288051f83fbbSDmitry Baryshkov qup_uart3_default_state: qup-uart3-default-state { 288151f83fbbSDmitry Baryshkov rx-pins { 288251f83fbbSDmitry Baryshkov pins = "gpio18"; 288351f83fbbSDmitry Baryshkov function = "qup3"; 288451f83fbbSDmitry Baryshkov }; 288551f83fbbSDmitry Baryshkov tx-pins { 288651f83fbbSDmitry Baryshkov pins = "gpio19"; 288751f83fbbSDmitry Baryshkov function = "qup3"; 288851f83fbbSDmitry Baryshkov }; 288951f83fbbSDmitry Baryshkov }; 289051f83fbbSDmitry Baryshkov 289151f83fbbSDmitry Baryshkov qup_uart6_default: qup-uart6-default-state { 289251f83fbbSDmitry Baryshkov pins = "gpio30", "gpio31"; 289351f83fbbSDmitry Baryshkov function = "qup6"; 289451f83fbbSDmitry Baryshkov drive-strength = <2>; 289551f83fbbSDmitry Baryshkov bias-disable; 289651f83fbbSDmitry Baryshkov }; 289751f83fbbSDmitry Baryshkov 289851f83fbbSDmitry Baryshkov qup_uart18_default: qup-uart18-default-state { 289951f83fbbSDmitry Baryshkov pins = "gpio58", "gpio59"; 290051f83fbbSDmitry Baryshkov function = "qup18"; 290151f83fbbSDmitry Baryshkov drive-strength = <2>; 290251f83fbbSDmitry Baryshkov bias-disable; 290351f83fbbSDmitry Baryshkov }; 290451f83fbbSDmitry Baryshkov 290551f83fbbSDmitry Baryshkov qup_i2c0_default: qup-i2c0-default-state { 290651f83fbbSDmitry Baryshkov pins = "gpio4", "gpio5"; 290751f83fbbSDmitry Baryshkov function = "qup0"; 290851f83fbbSDmitry Baryshkov drive-strength = <2>; 290951f83fbbSDmitry Baryshkov bias-pull-up; 291051f83fbbSDmitry Baryshkov }; 291151f83fbbSDmitry Baryshkov 291251f83fbbSDmitry Baryshkov qup_i2c1_default: qup-i2c1-default-state { 291351f83fbbSDmitry Baryshkov pins = "gpio8", "gpio9"; 291451f83fbbSDmitry Baryshkov function = "qup1"; 291551f83fbbSDmitry Baryshkov drive-strength = <2>; 291651f83fbbSDmitry Baryshkov bias-pull-up; 291751f83fbbSDmitry Baryshkov }; 291851f83fbbSDmitry Baryshkov 291951f83fbbSDmitry Baryshkov qup_i2c2_default: qup-i2c2-default-state { 292051f83fbbSDmitry Baryshkov pins = "gpio12", "gpio13"; 292151f83fbbSDmitry Baryshkov function = "qup2"; 292251f83fbbSDmitry Baryshkov drive-strength = <2>; 292351f83fbbSDmitry Baryshkov bias-pull-up; 292451f83fbbSDmitry Baryshkov }; 292551f83fbbSDmitry Baryshkov 292651f83fbbSDmitry Baryshkov qup_i2c4_default: qup-i2c4-default-state { 292751f83fbbSDmitry Baryshkov pins = "gpio20", "gpio21"; 292851f83fbbSDmitry Baryshkov function = "qup4"; 292951f83fbbSDmitry Baryshkov drive-strength = <2>; 293051f83fbbSDmitry Baryshkov bias-pull-up; 293151f83fbbSDmitry Baryshkov }; 293251f83fbbSDmitry Baryshkov 293351f83fbbSDmitry Baryshkov qup_i2c5_default: qup-i2c5-default-state { 293451f83fbbSDmitry Baryshkov pins = "gpio24", "gpio25"; 293551f83fbbSDmitry Baryshkov function = "qup5"; 293651f83fbbSDmitry Baryshkov drive-strength = <2>; 293751f83fbbSDmitry Baryshkov bias-pull-up; 293851f83fbbSDmitry Baryshkov }; 293951f83fbbSDmitry Baryshkov 294051f83fbbSDmitry Baryshkov qup_i2c6_default: qup-i2c6-default-state { 294151f83fbbSDmitry Baryshkov pins = "gpio28", "gpio29"; 294251f83fbbSDmitry Baryshkov function = "qup6"; 294351f83fbbSDmitry Baryshkov drive-strength = <2>; 294451f83fbbSDmitry Baryshkov bias-pull-up; 294551f83fbbSDmitry Baryshkov }; 294651f83fbbSDmitry Baryshkov 294751f83fbbSDmitry Baryshkov qup_i2c7_default: qup-i2c7-default-state { 294851f83fbbSDmitry Baryshkov pins = "gpio32", "gpio33"; 294951f83fbbSDmitry Baryshkov function = "qup7"; 295051f83fbbSDmitry Baryshkov drive-strength = <2>; 295151f83fbbSDmitry Baryshkov bias-disable; 295251f83fbbSDmitry Baryshkov }; 295351f83fbbSDmitry Baryshkov 295451f83fbbSDmitry Baryshkov qup_i2c8_default: qup-i2c8-default-state { 295551f83fbbSDmitry Baryshkov pins = "gpio36", "gpio37"; 295651f83fbbSDmitry Baryshkov function = "qup8"; 295751f83fbbSDmitry Baryshkov drive-strength = <2>; 295851f83fbbSDmitry Baryshkov bias-pull-up; 295951f83fbbSDmitry Baryshkov }; 296051f83fbbSDmitry Baryshkov 296151f83fbbSDmitry Baryshkov qup_i2c9_default: qup-i2c9-default-state { 296251f83fbbSDmitry Baryshkov pins = "gpio40", "gpio41"; 296351f83fbbSDmitry Baryshkov function = "qup9"; 296451f83fbbSDmitry Baryshkov drive-strength = <2>; 296551f83fbbSDmitry Baryshkov bias-pull-up; 296651f83fbbSDmitry Baryshkov }; 296751f83fbbSDmitry Baryshkov 296851f83fbbSDmitry Baryshkov qup_i2c10_default: qup-i2c10-default-state { 296951f83fbbSDmitry Baryshkov pins = "gpio44", "gpio45"; 297051f83fbbSDmitry Baryshkov function = "qup10"; 297151f83fbbSDmitry Baryshkov drive-strength = <2>; 297251f83fbbSDmitry Baryshkov bias-pull-up; 297351f83fbbSDmitry Baryshkov }; 297451f83fbbSDmitry Baryshkov 297551f83fbbSDmitry Baryshkov qup_i2c11_default: qup-i2c11-default-state { 297651f83fbbSDmitry Baryshkov pins = "gpio48", "gpio49"; 297751f83fbbSDmitry Baryshkov function = "qup11"; 297851f83fbbSDmitry Baryshkov drive-strength = <2>; 297951f83fbbSDmitry Baryshkov bias-pull-up; 298051f83fbbSDmitry Baryshkov }; 298151f83fbbSDmitry Baryshkov 298251f83fbbSDmitry Baryshkov qup_i2c12_default: qup-i2c12-default-state { 298351f83fbbSDmitry Baryshkov pins = "gpio52", "gpio53"; 298451f83fbbSDmitry Baryshkov function = "qup12"; 298551f83fbbSDmitry Baryshkov drive-strength = <2>; 298651f83fbbSDmitry Baryshkov bias-pull-up; 298751f83fbbSDmitry Baryshkov }; 298851f83fbbSDmitry Baryshkov 298951f83fbbSDmitry Baryshkov qup_i2c13_default: qup-i2c13-default-state { 299051f83fbbSDmitry Baryshkov pins = "gpio0", "gpio1"; 299151f83fbbSDmitry Baryshkov function = "qup13"; 299251f83fbbSDmitry Baryshkov drive-strength = <2>; 299351f83fbbSDmitry Baryshkov bias-pull-up; 299451f83fbbSDmitry Baryshkov }; 299551f83fbbSDmitry Baryshkov 299651f83fbbSDmitry Baryshkov qup_i2c14_default: qup-i2c14-default-state { 299751f83fbbSDmitry Baryshkov pins = "gpio56", "gpio57"; 299851f83fbbSDmitry Baryshkov function = "qup14"; 299951f83fbbSDmitry Baryshkov drive-strength = <2>; 300051f83fbbSDmitry Baryshkov bias-disable; 300151f83fbbSDmitry Baryshkov }; 300251f83fbbSDmitry Baryshkov 300351f83fbbSDmitry Baryshkov qup_i2c15_default: qup-i2c15-default-state { 300451f83fbbSDmitry Baryshkov pins = "gpio60", "gpio61"; 300551f83fbbSDmitry Baryshkov function = "qup15"; 300651f83fbbSDmitry Baryshkov drive-strength = <2>; 300751f83fbbSDmitry Baryshkov bias-disable; 300851f83fbbSDmitry Baryshkov }; 300951f83fbbSDmitry Baryshkov 301051f83fbbSDmitry Baryshkov qup_i2c16_default: qup-i2c16-default-state { 301151f83fbbSDmitry Baryshkov pins = "gpio64", "gpio65"; 301251f83fbbSDmitry Baryshkov function = "qup16"; 301351f83fbbSDmitry Baryshkov drive-strength = <2>; 301451f83fbbSDmitry Baryshkov bias-disable; 301551f83fbbSDmitry Baryshkov }; 301651f83fbbSDmitry Baryshkov 301751f83fbbSDmitry Baryshkov qup_i2c17_default: qup-i2c17-default-state { 301851f83fbbSDmitry Baryshkov pins = "gpio72", "gpio73"; 301951f83fbbSDmitry Baryshkov function = "qup17"; 302051f83fbbSDmitry Baryshkov drive-strength = <2>; 302151f83fbbSDmitry Baryshkov bias-disable; 302251f83fbbSDmitry Baryshkov }; 302351f83fbbSDmitry Baryshkov 302451f83fbbSDmitry Baryshkov qup_i2c19_default: qup-i2c19-default-state { 302551f83fbbSDmitry Baryshkov pins = "gpio76", "gpio77"; 302651f83fbbSDmitry Baryshkov function = "qup19"; 302751f83fbbSDmitry Baryshkov drive-strength = <2>; 302851f83fbbSDmitry Baryshkov bias-disable; 302951f83fbbSDmitry Baryshkov }; 303051f83fbbSDmitry Baryshkov }; 303151f83fbbSDmitry Baryshkov 3032f5f6bd58SDmitry Baryshkov apps_smmu: iommu@15000000 { 3033f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3034f5f6bd58SDmitry Baryshkov reg = <0 0x15000000 0 0x100000>; 3035f5f6bd58SDmitry Baryshkov #iommu-cells = <2>; 3036f5f6bd58SDmitry Baryshkov #global-interrupts = <2>; 3037f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3038f5f6bd58SDmitry Baryshkov <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3039f5f6bd58SDmitry Baryshkov <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3040f5f6bd58SDmitry Baryshkov <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3041f5f6bd58SDmitry Baryshkov <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3042f5f6bd58SDmitry Baryshkov <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3043f5f6bd58SDmitry Baryshkov <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3044f5f6bd58SDmitry Baryshkov <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3045f5f6bd58SDmitry Baryshkov <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3046f5f6bd58SDmitry Baryshkov <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3047f5f6bd58SDmitry Baryshkov <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3048f5f6bd58SDmitry Baryshkov <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3049f5f6bd58SDmitry Baryshkov <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3050f5f6bd58SDmitry Baryshkov <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3051f5f6bd58SDmitry Baryshkov <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3052f5f6bd58SDmitry Baryshkov <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3053f5f6bd58SDmitry Baryshkov <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3054f5f6bd58SDmitry Baryshkov <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3055f5f6bd58SDmitry Baryshkov <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3056f5f6bd58SDmitry Baryshkov <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3057f5f6bd58SDmitry Baryshkov <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3058f5f6bd58SDmitry Baryshkov <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3059f5f6bd58SDmitry Baryshkov <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3060f5f6bd58SDmitry Baryshkov <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3061f5f6bd58SDmitry Baryshkov <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3062f5f6bd58SDmitry Baryshkov <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3063f5f6bd58SDmitry Baryshkov <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3064f5f6bd58SDmitry Baryshkov <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3065f5f6bd58SDmitry Baryshkov <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3066f5f6bd58SDmitry Baryshkov <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3067f5f6bd58SDmitry Baryshkov <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3068f5f6bd58SDmitry Baryshkov <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3069f5f6bd58SDmitry Baryshkov <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3070f5f6bd58SDmitry Baryshkov <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3071f5f6bd58SDmitry Baryshkov <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3072f5f6bd58SDmitry Baryshkov <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3073f5f6bd58SDmitry Baryshkov <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3074f5f6bd58SDmitry Baryshkov <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3075f5f6bd58SDmitry Baryshkov <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3076f5f6bd58SDmitry Baryshkov <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3077f5f6bd58SDmitry Baryshkov <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3078f5f6bd58SDmitry Baryshkov <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3079f5f6bd58SDmitry Baryshkov <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3080f5f6bd58SDmitry Baryshkov <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3081f5f6bd58SDmitry Baryshkov <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3082f5f6bd58SDmitry Baryshkov <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3083f5f6bd58SDmitry Baryshkov <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3084f5f6bd58SDmitry Baryshkov <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3085f5f6bd58SDmitry Baryshkov <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3086f5f6bd58SDmitry Baryshkov <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3087f5f6bd58SDmitry Baryshkov <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3088f5f6bd58SDmitry Baryshkov <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3089f5f6bd58SDmitry Baryshkov <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3090f5f6bd58SDmitry Baryshkov <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3091f5f6bd58SDmitry Baryshkov <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3092f5f6bd58SDmitry Baryshkov <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3093f5f6bd58SDmitry Baryshkov <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3094f5f6bd58SDmitry Baryshkov <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3095f5f6bd58SDmitry Baryshkov <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3096f5f6bd58SDmitry Baryshkov <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3097f5f6bd58SDmitry Baryshkov <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3098f5f6bd58SDmitry Baryshkov <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3099f5f6bd58SDmitry Baryshkov <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3100f5f6bd58SDmitry Baryshkov <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3101f5f6bd58SDmitry Baryshkov <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3102f5f6bd58SDmitry Baryshkov <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3103f5f6bd58SDmitry Baryshkov <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3104f5f6bd58SDmitry Baryshkov <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3105f5f6bd58SDmitry Baryshkov <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3106f5f6bd58SDmitry Baryshkov <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3107f5f6bd58SDmitry Baryshkov <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3108f5f6bd58SDmitry Baryshkov <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3109f5f6bd58SDmitry Baryshkov <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3110f5f6bd58SDmitry Baryshkov <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3111f5f6bd58SDmitry Baryshkov <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3112f5f6bd58SDmitry Baryshkov <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3113f5f6bd58SDmitry Baryshkov <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3114f5f6bd58SDmitry Baryshkov <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3115f5f6bd58SDmitry Baryshkov <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3116f5f6bd58SDmitry Baryshkov <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3117f5f6bd58SDmitry Baryshkov <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3118f5f6bd58SDmitry Baryshkov <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3119f5f6bd58SDmitry Baryshkov <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3120f5f6bd58SDmitry Baryshkov <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3121f5f6bd58SDmitry Baryshkov <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3122f5f6bd58SDmitry Baryshkov <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3123f5f6bd58SDmitry Baryshkov <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3124f5f6bd58SDmitry Baryshkov <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3125f5f6bd58SDmitry Baryshkov <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3126f5f6bd58SDmitry Baryshkov <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3127f5f6bd58SDmitry Baryshkov <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3128f5f6bd58SDmitry Baryshkov <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3129f5f6bd58SDmitry Baryshkov <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3130f5f6bd58SDmitry Baryshkov <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3131f5f6bd58SDmitry Baryshkov <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3132f5f6bd58SDmitry Baryshkov <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3133f5f6bd58SDmitry Baryshkov <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3134f5f6bd58SDmitry Baryshkov <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3135f5f6bd58SDmitry Baryshkov }; 3136f5f6bd58SDmitry Baryshkov 3137177fcf0aSVinod Koul adsp: remoteproc@17300000 { 3138177fcf0aSVinod Koul compatible = "qcom,sm8350-adsp-pas"; 3139177fcf0aSVinod Koul reg = <0 0x17300000 0 0x100>; 3140177fcf0aSVinod Koul 3141177fcf0aSVinod Koul interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3142177fcf0aSVinod Koul <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3143177fcf0aSVinod Koul <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3144177fcf0aSVinod Koul <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3145177fcf0aSVinod Koul <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3146177fcf0aSVinod Koul interrupt-names = "wdog", "fatal", "ready", 3147177fcf0aSVinod Koul "handover", "stop-ack"; 3148177fcf0aSVinod Koul 3149177fcf0aSVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>; 3150177fcf0aSVinod Koul clock-names = "xo"; 3151177fcf0aSVinod Koul 3152d0e285c3SRobert Foss power-domains = <&rpmhpd SM8350_LCX>, 3153d0e285c3SRobert Foss <&rpmhpd SM8350_LMX>; 31546b7cb2d2SSibi Sankar power-domain-names = "lcx", "lmx"; 3155177fcf0aSVinod Koul 3156177fcf0aSVinod Koul memory-region = <&pil_adsp_mem>; 3157177fcf0aSVinod Koul 31586b7cb2d2SSibi Sankar qcom,qmp = <&aoss_qmp>; 31596b7cb2d2SSibi Sankar 3160177fcf0aSVinod Koul qcom,smem-states = <&smp2p_adsp_out 0>; 3161177fcf0aSVinod Koul qcom,smem-state-names = "stop"; 3162177fcf0aSVinod Koul 3163177fcf0aSVinod Koul status = "disabled"; 3164177fcf0aSVinod Koul 3165177fcf0aSVinod Koul glink-edge { 3166177fcf0aSVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3167177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP 3168177fcf0aSVinod Koul IRQ_TYPE_EDGE_RISING>; 3169177fcf0aSVinod Koul mboxes = <&ipcc IPCC_CLIENT_LPASS 3170177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP>; 3171177fcf0aSVinod Koul 3172177fcf0aSVinod Koul label = "lpass"; 3173177fcf0aSVinod Koul qcom,remote-pid = <2>; 3174178056a4SOla Jeppsson 3175178056a4SOla Jeppsson fastrpc { 3176178056a4SOla Jeppsson compatible = "qcom,fastrpc"; 3177178056a4SOla Jeppsson qcom,glink-channels = "fastrpcglink-apps-dsp"; 3178178056a4SOla Jeppsson label = "adsp"; 31798c8ce95bSJeya R qcom,non-secure-domain; 3180178056a4SOla Jeppsson #address-cells = <1>; 3181178056a4SOla Jeppsson #size-cells = <0>; 3182178056a4SOla Jeppsson 3183178056a4SOla Jeppsson compute-cb@3 { 3184178056a4SOla Jeppsson compatible = "qcom,fastrpc-compute-cb"; 3185178056a4SOla Jeppsson reg = <3>; 3186178056a4SOla Jeppsson iommus = <&apps_smmu 0x1803 0x0>; 3187178056a4SOla Jeppsson }; 3188178056a4SOla Jeppsson 3189178056a4SOla Jeppsson compute-cb@4 { 3190178056a4SOla Jeppsson compatible = "qcom,fastrpc-compute-cb"; 3191178056a4SOla Jeppsson reg = <4>; 3192178056a4SOla Jeppsson iommus = <&apps_smmu 0x1804 0x0>; 3193178056a4SOla Jeppsson }; 3194178056a4SOla Jeppsson 3195178056a4SOla Jeppsson compute-cb@5 { 3196178056a4SOla Jeppsson compatible = "qcom,fastrpc-compute-cb"; 3197178056a4SOla Jeppsson reg = <5>; 3198178056a4SOla Jeppsson iommus = <&apps_smmu 0x1805 0x0>; 3199178056a4SOla Jeppsson }; 3200178056a4SOla Jeppsson }; 3201177fcf0aSVinod Koul }; 3202177fcf0aSVinod Koul }; 3203f5f6bd58SDmitry Baryshkov 3204f5f6bd58SDmitry Baryshkov intc: interrupt-controller@17a00000 { 3205f5f6bd58SDmitry Baryshkov compatible = "arm,gic-v3"; 3206f5f6bd58SDmitry Baryshkov #interrupt-cells = <3>; 3207f5f6bd58SDmitry Baryshkov interrupt-controller; 3208f5f6bd58SDmitry Baryshkov #redistributor-regions = <1>; 3209f5f6bd58SDmitry Baryshkov redistributor-stride = <0 0x20000>; 3210f5f6bd58SDmitry Baryshkov reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3211f5f6bd58SDmitry Baryshkov <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3212f5f6bd58SDmitry Baryshkov interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3213f5f6bd58SDmitry Baryshkov }; 3214f5f6bd58SDmitry Baryshkov 3215f5f6bd58SDmitry Baryshkov timer@17c20000 { 3216f5f6bd58SDmitry Baryshkov compatible = "arm,armv7-timer-mem"; 3217f5f6bd58SDmitry Baryshkov #address-cells = <1>; 3218f5f6bd58SDmitry Baryshkov #size-cells = <1>; 3219f5f6bd58SDmitry Baryshkov ranges = <0 0 0 0x20000000>; 3220f5f6bd58SDmitry Baryshkov reg = <0x0 0x17c20000 0x0 0x1000>; 3221f5f6bd58SDmitry Baryshkov clock-frequency = <19200000>; 3222f5f6bd58SDmitry Baryshkov 3223f5f6bd58SDmitry Baryshkov frame@17c21000 { 3224f5f6bd58SDmitry Baryshkov frame-number = <0>; 3225f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3226f5f6bd58SDmitry Baryshkov <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3227f5f6bd58SDmitry Baryshkov reg = <0x17c21000 0x1000>, 3228f5f6bd58SDmitry Baryshkov <0x17c22000 0x1000>; 3229f5f6bd58SDmitry Baryshkov }; 3230f5f6bd58SDmitry Baryshkov 3231f5f6bd58SDmitry Baryshkov frame@17c23000 { 3232f5f6bd58SDmitry Baryshkov frame-number = <1>; 3233f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3234f5f6bd58SDmitry Baryshkov reg = <0x17c23000 0x1000>; 3235f5f6bd58SDmitry Baryshkov status = "disabled"; 3236f5f6bd58SDmitry Baryshkov }; 3237f5f6bd58SDmitry Baryshkov 3238f5f6bd58SDmitry Baryshkov frame@17c25000 { 3239f5f6bd58SDmitry Baryshkov frame-number = <2>; 3240f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3241f5f6bd58SDmitry Baryshkov reg = <0x17c25000 0x1000>; 3242f5f6bd58SDmitry Baryshkov status = "disabled"; 3243f5f6bd58SDmitry Baryshkov }; 3244f5f6bd58SDmitry Baryshkov 3245f5f6bd58SDmitry Baryshkov frame@17c27000 { 3246f5f6bd58SDmitry Baryshkov frame-number = <3>; 3247f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3248f5f6bd58SDmitry Baryshkov reg = <0x17c27000 0x1000>; 3249f5f6bd58SDmitry Baryshkov status = "disabled"; 3250f5f6bd58SDmitry Baryshkov }; 3251f5f6bd58SDmitry Baryshkov 3252f5f6bd58SDmitry Baryshkov frame@17c29000 { 3253f5f6bd58SDmitry Baryshkov frame-number = <4>; 3254f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3255f5f6bd58SDmitry Baryshkov reg = <0x17c29000 0x1000>; 3256f5f6bd58SDmitry Baryshkov status = "disabled"; 3257f5f6bd58SDmitry Baryshkov }; 3258f5f6bd58SDmitry Baryshkov 3259f5f6bd58SDmitry Baryshkov frame@17c2b000 { 3260f5f6bd58SDmitry Baryshkov frame-number = <5>; 3261f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3262f5f6bd58SDmitry Baryshkov reg = <0x17c2b000 0x1000>; 3263f5f6bd58SDmitry Baryshkov status = "disabled"; 3264f5f6bd58SDmitry Baryshkov }; 3265f5f6bd58SDmitry Baryshkov 3266f5f6bd58SDmitry Baryshkov frame@17c2d000 { 3267f5f6bd58SDmitry Baryshkov frame-number = <6>; 3268f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3269f5f6bd58SDmitry Baryshkov reg = <0x17c2d000 0x1000>; 3270f5f6bd58SDmitry Baryshkov status = "disabled"; 3271f5f6bd58SDmitry Baryshkov }; 3272f5f6bd58SDmitry Baryshkov }; 3273f5f6bd58SDmitry Baryshkov 3274f5f6bd58SDmitry Baryshkov apps_rsc: rsc@18200000 { 3275f5f6bd58SDmitry Baryshkov label = "apps_rsc"; 3276f5f6bd58SDmitry Baryshkov compatible = "qcom,rpmh-rsc"; 3277f5f6bd58SDmitry Baryshkov reg = <0x0 0x18200000 0x0 0x10000>, 3278f5f6bd58SDmitry Baryshkov <0x0 0x18210000 0x0 0x10000>, 3279f5f6bd58SDmitry Baryshkov <0x0 0x18220000 0x0 0x10000>; 3280f5f6bd58SDmitry Baryshkov reg-names = "drv-0", "drv-1", "drv-2"; 3281f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3282f5f6bd58SDmitry Baryshkov <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3283f5f6bd58SDmitry Baryshkov <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3284f5f6bd58SDmitry Baryshkov qcom,tcs-offset = <0xd00>; 3285f5f6bd58SDmitry Baryshkov qcom,drv-id = <2>; 3286f5f6bd58SDmitry Baryshkov qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3287f5f6bd58SDmitry Baryshkov <WAKE_TCS 3>, <CONTROL_TCS 0>; 3288f5f6bd58SDmitry Baryshkov power-domains = <&CLUSTER_PD>; 3289f5f6bd58SDmitry Baryshkov 3290f5f6bd58SDmitry Baryshkov rpmhcc: clock-controller { 3291f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-rpmh-clk"; 3292f5f6bd58SDmitry Baryshkov #clock-cells = <1>; 3293f5f6bd58SDmitry Baryshkov clock-names = "xo"; 3294f5f6bd58SDmitry Baryshkov clocks = <&xo_board>; 3295f5f6bd58SDmitry Baryshkov }; 3296f5f6bd58SDmitry Baryshkov 3297f5f6bd58SDmitry Baryshkov rpmhpd: power-controller { 3298f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-rpmhpd"; 3299f5f6bd58SDmitry Baryshkov #power-domain-cells = <1>; 3300f5f6bd58SDmitry Baryshkov operating-points-v2 = <&rpmhpd_opp_table>; 3301f5f6bd58SDmitry Baryshkov 3302f5f6bd58SDmitry Baryshkov rpmhpd_opp_table: opp-table { 3303f5f6bd58SDmitry Baryshkov compatible = "operating-points-v2"; 3304f5f6bd58SDmitry Baryshkov 3305f5f6bd58SDmitry Baryshkov rpmhpd_opp_ret: opp1 { 3306f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3307f5f6bd58SDmitry Baryshkov }; 3308f5f6bd58SDmitry Baryshkov 3309f5f6bd58SDmitry Baryshkov rpmhpd_opp_min_svs: opp2 { 3310f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3311f5f6bd58SDmitry Baryshkov }; 3312f5f6bd58SDmitry Baryshkov 3313f5f6bd58SDmitry Baryshkov rpmhpd_opp_low_svs: opp3 { 3314f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3315f5f6bd58SDmitry Baryshkov }; 3316f5f6bd58SDmitry Baryshkov 3317f5f6bd58SDmitry Baryshkov rpmhpd_opp_svs: opp4 { 3318f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3319f5f6bd58SDmitry Baryshkov }; 3320f5f6bd58SDmitry Baryshkov 3321f5f6bd58SDmitry Baryshkov rpmhpd_opp_svs_l1: opp5 { 3322f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3323f5f6bd58SDmitry Baryshkov }; 3324f5f6bd58SDmitry Baryshkov 3325f5f6bd58SDmitry Baryshkov rpmhpd_opp_nom: opp6 { 3326f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3327f5f6bd58SDmitry Baryshkov }; 3328f5f6bd58SDmitry Baryshkov 3329f5f6bd58SDmitry Baryshkov rpmhpd_opp_nom_l1: opp7 { 3330f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3331f5f6bd58SDmitry Baryshkov }; 3332f5f6bd58SDmitry Baryshkov 3333f5f6bd58SDmitry Baryshkov rpmhpd_opp_nom_l2: opp8 { 3334f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3335f5f6bd58SDmitry Baryshkov }; 3336f5f6bd58SDmitry Baryshkov 3337f5f6bd58SDmitry Baryshkov rpmhpd_opp_turbo: opp9 { 3338f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3339f5f6bd58SDmitry Baryshkov }; 3340f5f6bd58SDmitry Baryshkov 3341f5f6bd58SDmitry Baryshkov rpmhpd_opp_turbo_l1: opp10 { 3342f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3343f5f6bd58SDmitry Baryshkov }; 3344f5f6bd58SDmitry Baryshkov }; 3345f5f6bd58SDmitry Baryshkov }; 3346f5f6bd58SDmitry Baryshkov 3347f5f6bd58SDmitry Baryshkov apps_bcm_voter: bcm-voter { 3348f5f6bd58SDmitry Baryshkov compatible = "qcom,bcm-voter"; 3349f5f6bd58SDmitry Baryshkov }; 3350f5f6bd58SDmitry Baryshkov }; 3351f5f6bd58SDmitry Baryshkov 3352f5f6bd58SDmitry Baryshkov cpufreq_hw: cpufreq@18591000 { 3353f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3354f5f6bd58SDmitry Baryshkov reg = <0 0x18591000 0 0x1000>, 3355f5f6bd58SDmitry Baryshkov <0 0x18592000 0 0x1000>, 3356f5f6bd58SDmitry Baryshkov <0 0x18593000 0 0x1000>; 3357f5f6bd58SDmitry Baryshkov reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3358f5f6bd58SDmitry Baryshkov 3359f5f6bd58SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3360f5f6bd58SDmitry Baryshkov clock-names = "xo", "alternate"; 3361f5f6bd58SDmitry Baryshkov 3362f5f6bd58SDmitry Baryshkov #freq-domain-cells = <1>; 3363c2a18730SManivannan Sadhasivam #clock-cells = <1>; 3364f5f6bd58SDmitry Baryshkov }; 3365f5f6bd58SDmitry Baryshkov 3366f5f6bd58SDmitry Baryshkov cdsp: remoteproc@98900000 { 3367f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-cdsp-pas"; 3368f5f6bd58SDmitry Baryshkov reg = <0 0x98900000 0 0x1400000>; 3369f5f6bd58SDmitry Baryshkov 3370f5f6bd58SDmitry Baryshkov interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3371f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3372f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3373f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3374f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3375f5f6bd58SDmitry Baryshkov interrupt-names = "wdog", "fatal", "ready", 3376f5f6bd58SDmitry Baryshkov "handover", "stop-ack"; 3377f5f6bd58SDmitry Baryshkov 3378f5f6bd58SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>; 3379f5f6bd58SDmitry Baryshkov clock-names = "xo"; 3380f5f6bd58SDmitry Baryshkov 3381f5f6bd58SDmitry Baryshkov power-domains = <&rpmhpd SM8350_CX>, 3382f5f6bd58SDmitry Baryshkov <&rpmhpd SM8350_MXC>; 3383f5f6bd58SDmitry Baryshkov power-domain-names = "cx", "mxc"; 3384f5f6bd58SDmitry Baryshkov 3385f5f6bd58SDmitry Baryshkov interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3386f5f6bd58SDmitry Baryshkov 3387f5f6bd58SDmitry Baryshkov memory-region = <&pil_cdsp_mem>; 3388f5f6bd58SDmitry Baryshkov 3389f5f6bd58SDmitry Baryshkov qcom,qmp = <&aoss_qmp>; 3390f5f6bd58SDmitry Baryshkov 3391f5f6bd58SDmitry Baryshkov qcom,smem-states = <&smp2p_cdsp_out 0>; 3392f5f6bd58SDmitry Baryshkov qcom,smem-state-names = "stop"; 3393f5f6bd58SDmitry Baryshkov 3394f5f6bd58SDmitry Baryshkov status = "disabled"; 3395f5f6bd58SDmitry Baryshkov 3396f5f6bd58SDmitry Baryshkov glink-edge { 3397f5f6bd58SDmitry Baryshkov interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3398f5f6bd58SDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP 3399f5f6bd58SDmitry Baryshkov IRQ_TYPE_EDGE_RISING>; 3400f5f6bd58SDmitry Baryshkov mboxes = <&ipcc IPCC_CLIENT_CDSP 3401f5f6bd58SDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP>; 3402f5f6bd58SDmitry Baryshkov 3403f5f6bd58SDmitry Baryshkov label = "cdsp"; 3404f5f6bd58SDmitry Baryshkov qcom,remote-pid = <5>; 3405f5f6bd58SDmitry Baryshkov 3406f5f6bd58SDmitry Baryshkov fastrpc { 3407f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc"; 3408f5f6bd58SDmitry Baryshkov qcom,glink-channels = "fastrpcglink-apps-dsp"; 3409f5f6bd58SDmitry Baryshkov label = "cdsp"; 3410f5f6bd58SDmitry Baryshkov qcom,non-secure-domain; 3411f5f6bd58SDmitry Baryshkov #address-cells = <1>; 3412f5f6bd58SDmitry Baryshkov #size-cells = <0>; 3413f5f6bd58SDmitry Baryshkov 3414f5f6bd58SDmitry Baryshkov compute-cb@1 { 3415f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3416f5f6bd58SDmitry Baryshkov reg = <1>; 3417f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2161 0x0400>, 3418f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1181 0x0420>; 3419f5f6bd58SDmitry Baryshkov }; 3420f5f6bd58SDmitry Baryshkov 3421f5f6bd58SDmitry Baryshkov compute-cb@2 { 3422f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3423f5f6bd58SDmitry Baryshkov reg = <2>; 3424f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2162 0x0400>, 3425f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1182 0x0420>; 3426f5f6bd58SDmitry Baryshkov }; 3427f5f6bd58SDmitry Baryshkov 3428f5f6bd58SDmitry Baryshkov compute-cb@3 { 3429f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3430f5f6bd58SDmitry Baryshkov reg = <3>; 3431f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2163 0x0400>, 3432f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1183 0x0420>; 3433f5f6bd58SDmitry Baryshkov }; 3434f5f6bd58SDmitry Baryshkov 3435f5f6bd58SDmitry Baryshkov compute-cb@4 { 3436f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3437f5f6bd58SDmitry Baryshkov reg = <4>; 3438f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2164 0x0400>, 3439f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1184 0x0420>; 3440f5f6bd58SDmitry Baryshkov }; 3441f5f6bd58SDmitry Baryshkov 3442f5f6bd58SDmitry Baryshkov compute-cb@5 { 3443f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3444f5f6bd58SDmitry Baryshkov reg = <5>; 3445f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2165 0x0400>, 3446f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1185 0x0420>; 3447f5f6bd58SDmitry Baryshkov }; 3448f5f6bd58SDmitry Baryshkov 3449f5f6bd58SDmitry Baryshkov compute-cb@6 { 3450f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3451f5f6bd58SDmitry Baryshkov reg = <6>; 3452f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2166 0x0400>, 3453f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1186 0x0420>; 3454f5f6bd58SDmitry Baryshkov }; 3455f5f6bd58SDmitry Baryshkov 3456f5f6bd58SDmitry Baryshkov compute-cb@7 { 3457f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3458f5f6bd58SDmitry Baryshkov reg = <7>; 3459f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2167 0x0400>, 3460f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1187 0x0420>; 3461f5f6bd58SDmitry Baryshkov }; 3462f5f6bd58SDmitry Baryshkov 3463f5f6bd58SDmitry Baryshkov compute-cb@8 { 3464f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3465f5f6bd58SDmitry Baryshkov reg = <8>; 3466f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2168 0x0400>, 3467f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1188 0x0420>; 3468f5f6bd58SDmitry Baryshkov }; 3469f5f6bd58SDmitry Baryshkov 3470f5f6bd58SDmitry Baryshkov /* note: secure cb9 in downstream */ 3471f5f6bd58SDmitry Baryshkov }; 3472f5f6bd58SDmitry Baryshkov }; 3473f5f6bd58SDmitry Baryshkov }; 3474b7e8f433SVinod Koul }; 3475b7e8f433SVinod Koul 34764dcaa68eSsatya priya thermal_zones: thermal-zones { 347720f9d94eSRobert Foss cpu0-thermal { 347820f9d94eSRobert Foss polling-delay-passive = <250>; 347920f9d94eSRobert Foss polling-delay = <1000>; 348020f9d94eSRobert Foss 348120f9d94eSRobert Foss thermal-sensors = <&tsens0 1>; 348220f9d94eSRobert Foss 348320f9d94eSRobert Foss trips { 348420f9d94eSRobert Foss cpu0_alert0: trip-point0 { 348520f9d94eSRobert Foss temperature = <90000>; 348620f9d94eSRobert Foss hysteresis = <2000>; 348720f9d94eSRobert Foss type = "passive"; 348820f9d94eSRobert Foss }; 348920f9d94eSRobert Foss 349020f9d94eSRobert Foss cpu0_alert1: trip-point1 { 349120f9d94eSRobert Foss temperature = <95000>; 349220f9d94eSRobert Foss hysteresis = <2000>; 349320f9d94eSRobert Foss type = "passive"; 349420f9d94eSRobert Foss }; 349520f9d94eSRobert Foss 34961364acc3SKrzysztof Kozlowski cpu0_crit: cpu-crit { 349720f9d94eSRobert Foss temperature = <110000>; 349820f9d94eSRobert Foss hysteresis = <1000>; 349920f9d94eSRobert Foss type = "critical"; 350020f9d94eSRobert Foss }; 350120f9d94eSRobert Foss }; 350220f9d94eSRobert Foss 350320f9d94eSRobert Foss cooling-maps { 350420f9d94eSRobert Foss map0 { 350520f9d94eSRobert Foss trip = <&cpu0_alert0>; 350620f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350720f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350820f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350920f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 351020f9d94eSRobert Foss }; 351120f9d94eSRobert Foss map1 { 351220f9d94eSRobert Foss trip = <&cpu0_alert1>; 351320f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351420f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351520f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351620f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 351720f9d94eSRobert Foss }; 351820f9d94eSRobert Foss }; 351920f9d94eSRobert Foss }; 352020f9d94eSRobert Foss 352120f9d94eSRobert Foss cpu1-thermal { 352220f9d94eSRobert Foss polling-delay-passive = <250>; 352320f9d94eSRobert Foss polling-delay = <1000>; 352420f9d94eSRobert Foss 352520f9d94eSRobert Foss thermal-sensors = <&tsens0 2>; 352620f9d94eSRobert Foss 352720f9d94eSRobert Foss trips { 352820f9d94eSRobert Foss cpu1_alert0: trip-point0 { 352920f9d94eSRobert Foss temperature = <90000>; 353020f9d94eSRobert Foss hysteresis = <2000>; 353120f9d94eSRobert Foss type = "passive"; 353220f9d94eSRobert Foss }; 353320f9d94eSRobert Foss 353420f9d94eSRobert Foss cpu1_alert1: trip-point1 { 353520f9d94eSRobert Foss temperature = <95000>; 353620f9d94eSRobert Foss hysteresis = <2000>; 353720f9d94eSRobert Foss type = "passive"; 353820f9d94eSRobert Foss }; 353920f9d94eSRobert Foss 35401364acc3SKrzysztof Kozlowski cpu1_crit: cpu-crit { 354120f9d94eSRobert Foss temperature = <110000>; 354220f9d94eSRobert Foss hysteresis = <1000>; 354320f9d94eSRobert Foss type = "critical"; 354420f9d94eSRobert Foss }; 354520f9d94eSRobert Foss }; 354620f9d94eSRobert Foss 354720f9d94eSRobert Foss cooling-maps { 354820f9d94eSRobert Foss map0 { 354920f9d94eSRobert Foss trip = <&cpu1_alert0>; 355020f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355120f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355220f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355320f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 355420f9d94eSRobert Foss }; 355520f9d94eSRobert Foss map1 { 355620f9d94eSRobert Foss trip = <&cpu1_alert1>; 355720f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355820f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355920f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356020f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 356120f9d94eSRobert Foss }; 356220f9d94eSRobert Foss }; 356320f9d94eSRobert Foss }; 356420f9d94eSRobert Foss 356520f9d94eSRobert Foss cpu2-thermal { 356620f9d94eSRobert Foss polling-delay-passive = <250>; 356720f9d94eSRobert Foss polling-delay = <1000>; 356820f9d94eSRobert Foss 356920f9d94eSRobert Foss thermal-sensors = <&tsens0 3>; 357020f9d94eSRobert Foss 357120f9d94eSRobert Foss trips { 357220f9d94eSRobert Foss cpu2_alert0: trip-point0 { 357320f9d94eSRobert Foss temperature = <90000>; 357420f9d94eSRobert Foss hysteresis = <2000>; 357520f9d94eSRobert Foss type = "passive"; 357620f9d94eSRobert Foss }; 357720f9d94eSRobert Foss 357820f9d94eSRobert Foss cpu2_alert1: trip-point1 { 357920f9d94eSRobert Foss temperature = <95000>; 358020f9d94eSRobert Foss hysteresis = <2000>; 358120f9d94eSRobert Foss type = "passive"; 358220f9d94eSRobert Foss }; 358320f9d94eSRobert Foss 35841364acc3SKrzysztof Kozlowski cpu2_crit: cpu-crit { 358520f9d94eSRobert Foss temperature = <110000>; 358620f9d94eSRobert Foss hysteresis = <1000>; 358720f9d94eSRobert Foss type = "critical"; 358820f9d94eSRobert Foss }; 358920f9d94eSRobert Foss }; 359020f9d94eSRobert Foss 359120f9d94eSRobert Foss cooling-maps { 359220f9d94eSRobert Foss map0 { 359320f9d94eSRobert Foss trip = <&cpu2_alert0>; 359420f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 359520f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 359620f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 359720f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 359820f9d94eSRobert Foss }; 359920f9d94eSRobert Foss map1 { 360020f9d94eSRobert Foss trip = <&cpu2_alert1>; 360120f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 360220f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 360320f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 360420f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 360520f9d94eSRobert Foss }; 360620f9d94eSRobert Foss }; 360720f9d94eSRobert Foss }; 360820f9d94eSRobert Foss 360920f9d94eSRobert Foss cpu3-thermal { 361020f9d94eSRobert Foss polling-delay-passive = <250>; 361120f9d94eSRobert Foss polling-delay = <1000>; 361220f9d94eSRobert Foss 361320f9d94eSRobert Foss thermal-sensors = <&tsens0 4>; 361420f9d94eSRobert Foss 361520f9d94eSRobert Foss trips { 361620f9d94eSRobert Foss cpu3_alert0: trip-point0 { 361720f9d94eSRobert Foss temperature = <90000>; 361820f9d94eSRobert Foss hysteresis = <2000>; 361920f9d94eSRobert Foss type = "passive"; 362020f9d94eSRobert Foss }; 362120f9d94eSRobert Foss 362220f9d94eSRobert Foss cpu3_alert1: trip-point1 { 362320f9d94eSRobert Foss temperature = <95000>; 362420f9d94eSRobert Foss hysteresis = <2000>; 362520f9d94eSRobert Foss type = "passive"; 362620f9d94eSRobert Foss }; 362720f9d94eSRobert Foss 36281364acc3SKrzysztof Kozlowski cpu3_crit: cpu-crit { 362920f9d94eSRobert Foss temperature = <110000>; 363020f9d94eSRobert Foss hysteresis = <1000>; 363120f9d94eSRobert Foss type = "critical"; 363220f9d94eSRobert Foss }; 363320f9d94eSRobert Foss }; 363420f9d94eSRobert Foss 363520f9d94eSRobert Foss cooling-maps { 363620f9d94eSRobert Foss map0 { 363720f9d94eSRobert Foss trip = <&cpu3_alert0>; 363820f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 363920f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 364020f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 364120f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 364220f9d94eSRobert Foss }; 364320f9d94eSRobert Foss map1 { 364420f9d94eSRobert Foss trip = <&cpu3_alert1>; 364520f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 364620f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 364720f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 364820f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 364920f9d94eSRobert Foss }; 365020f9d94eSRobert Foss }; 365120f9d94eSRobert Foss }; 365220f9d94eSRobert Foss 365320f9d94eSRobert Foss cpu4-top-thermal { 365420f9d94eSRobert Foss polling-delay-passive = <250>; 365520f9d94eSRobert Foss polling-delay = <1000>; 365620f9d94eSRobert Foss 365720f9d94eSRobert Foss thermal-sensors = <&tsens0 7>; 365820f9d94eSRobert Foss 365920f9d94eSRobert Foss trips { 366020f9d94eSRobert Foss cpu4_top_alert0: trip-point0 { 366120f9d94eSRobert Foss temperature = <90000>; 366220f9d94eSRobert Foss hysteresis = <2000>; 366320f9d94eSRobert Foss type = "passive"; 366420f9d94eSRobert Foss }; 366520f9d94eSRobert Foss 366620f9d94eSRobert Foss cpu4_top_alert1: trip-point1 { 366720f9d94eSRobert Foss temperature = <95000>; 366820f9d94eSRobert Foss hysteresis = <2000>; 366920f9d94eSRobert Foss type = "passive"; 367020f9d94eSRobert Foss }; 367120f9d94eSRobert Foss 36721364acc3SKrzysztof Kozlowski cpu4_top_crit: cpu-crit { 367320f9d94eSRobert Foss temperature = <110000>; 367420f9d94eSRobert Foss hysteresis = <1000>; 367520f9d94eSRobert Foss type = "critical"; 367620f9d94eSRobert Foss }; 367720f9d94eSRobert Foss }; 367820f9d94eSRobert Foss 367920f9d94eSRobert Foss cooling-maps { 368020f9d94eSRobert Foss map0 { 368120f9d94eSRobert Foss trip = <&cpu4_top_alert0>; 368220f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 368320f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 368420f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 368520f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 368620f9d94eSRobert Foss }; 368720f9d94eSRobert Foss map1 { 368820f9d94eSRobert Foss trip = <&cpu4_top_alert1>; 368920f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 369020f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 369120f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 369220f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 369320f9d94eSRobert Foss }; 369420f9d94eSRobert Foss }; 369520f9d94eSRobert Foss }; 369620f9d94eSRobert Foss 369720f9d94eSRobert Foss cpu5-top-thermal { 369820f9d94eSRobert Foss polling-delay-passive = <250>; 369920f9d94eSRobert Foss polling-delay = <1000>; 370020f9d94eSRobert Foss 370120f9d94eSRobert Foss thermal-sensors = <&tsens0 8>; 370220f9d94eSRobert Foss 370320f9d94eSRobert Foss trips { 370420f9d94eSRobert Foss cpu5_top_alert0: trip-point0 { 370520f9d94eSRobert Foss temperature = <90000>; 370620f9d94eSRobert Foss hysteresis = <2000>; 370720f9d94eSRobert Foss type = "passive"; 370820f9d94eSRobert Foss }; 370920f9d94eSRobert Foss 371020f9d94eSRobert Foss cpu5_top_alert1: trip-point1 { 371120f9d94eSRobert Foss temperature = <95000>; 371220f9d94eSRobert Foss hysteresis = <2000>; 371320f9d94eSRobert Foss type = "passive"; 371420f9d94eSRobert Foss }; 371520f9d94eSRobert Foss 37161364acc3SKrzysztof Kozlowski cpu5_top_crit: cpu-crit { 371720f9d94eSRobert Foss temperature = <110000>; 371820f9d94eSRobert Foss hysteresis = <1000>; 371920f9d94eSRobert Foss type = "critical"; 372020f9d94eSRobert Foss }; 372120f9d94eSRobert Foss }; 372220f9d94eSRobert Foss 372320f9d94eSRobert Foss cooling-maps { 372420f9d94eSRobert Foss map0 { 372520f9d94eSRobert Foss trip = <&cpu5_top_alert0>; 372620f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 372720f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 372820f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 372920f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 373020f9d94eSRobert Foss }; 373120f9d94eSRobert Foss map1 { 373220f9d94eSRobert Foss trip = <&cpu5_top_alert1>; 373320f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 373420f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 373520f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 373620f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 373720f9d94eSRobert Foss }; 373820f9d94eSRobert Foss }; 373920f9d94eSRobert Foss }; 374020f9d94eSRobert Foss 374120f9d94eSRobert Foss cpu6-top-thermal { 374220f9d94eSRobert Foss polling-delay-passive = <250>; 374320f9d94eSRobert Foss polling-delay = <1000>; 374420f9d94eSRobert Foss 374520f9d94eSRobert Foss thermal-sensors = <&tsens0 9>; 374620f9d94eSRobert Foss 374720f9d94eSRobert Foss trips { 374820f9d94eSRobert Foss cpu6_top_alert0: trip-point0 { 374920f9d94eSRobert Foss temperature = <90000>; 375020f9d94eSRobert Foss hysteresis = <2000>; 375120f9d94eSRobert Foss type = "passive"; 375220f9d94eSRobert Foss }; 375320f9d94eSRobert Foss 375420f9d94eSRobert Foss cpu6_top_alert1: trip-point1 { 375520f9d94eSRobert Foss temperature = <95000>; 375620f9d94eSRobert Foss hysteresis = <2000>; 375720f9d94eSRobert Foss type = "passive"; 375820f9d94eSRobert Foss }; 375920f9d94eSRobert Foss 37601364acc3SKrzysztof Kozlowski cpu6_top_crit: cpu-crit { 376120f9d94eSRobert Foss temperature = <110000>; 376220f9d94eSRobert Foss hysteresis = <1000>; 376320f9d94eSRobert Foss type = "critical"; 376420f9d94eSRobert Foss }; 376520f9d94eSRobert Foss }; 376620f9d94eSRobert Foss 376720f9d94eSRobert Foss cooling-maps { 376820f9d94eSRobert Foss map0 { 376920f9d94eSRobert Foss trip = <&cpu6_top_alert0>; 377020f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 377120f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 377220f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 377320f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 377420f9d94eSRobert Foss }; 377520f9d94eSRobert Foss map1 { 377620f9d94eSRobert Foss trip = <&cpu6_top_alert1>; 377720f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 377820f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 377920f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 378020f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 378120f9d94eSRobert Foss }; 378220f9d94eSRobert Foss }; 378320f9d94eSRobert Foss }; 378420f9d94eSRobert Foss 378520f9d94eSRobert Foss cpu7-top-thermal { 378620f9d94eSRobert Foss polling-delay-passive = <250>; 378720f9d94eSRobert Foss polling-delay = <1000>; 378820f9d94eSRobert Foss 378920f9d94eSRobert Foss thermal-sensors = <&tsens0 10>; 379020f9d94eSRobert Foss 379120f9d94eSRobert Foss trips { 379220f9d94eSRobert Foss cpu7_top_alert0: trip-point0 { 379320f9d94eSRobert Foss temperature = <90000>; 379420f9d94eSRobert Foss hysteresis = <2000>; 379520f9d94eSRobert Foss type = "passive"; 379620f9d94eSRobert Foss }; 379720f9d94eSRobert Foss 379820f9d94eSRobert Foss cpu7_top_alert1: trip-point1 { 379920f9d94eSRobert Foss temperature = <95000>; 380020f9d94eSRobert Foss hysteresis = <2000>; 380120f9d94eSRobert Foss type = "passive"; 380220f9d94eSRobert Foss }; 380320f9d94eSRobert Foss 38041364acc3SKrzysztof Kozlowski cpu7_top_crit: cpu-crit { 380520f9d94eSRobert Foss temperature = <110000>; 380620f9d94eSRobert Foss hysteresis = <1000>; 380720f9d94eSRobert Foss type = "critical"; 380820f9d94eSRobert Foss }; 380920f9d94eSRobert Foss }; 381020f9d94eSRobert Foss 381120f9d94eSRobert Foss cooling-maps { 381220f9d94eSRobert Foss map0 { 381320f9d94eSRobert Foss trip = <&cpu7_top_alert0>; 381420f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 381520f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 381620f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 381720f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 381820f9d94eSRobert Foss }; 381920f9d94eSRobert Foss map1 { 382020f9d94eSRobert Foss trip = <&cpu7_top_alert1>; 382120f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382220f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382320f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382420f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 382520f9d94eSRobert Foss }; 382620f9d94eSRobert Foss }; 382720f9d94eSRobert Foss }; 382820f9d94eSRobert Foss 382920f9d94eSRobert Foss cpu4-bottom-thermal { 383020f9d94eSRobert Foss polling-delay-passive = <250>; 383120f9d94eSRobert Foss polling-delay = <1000>; 383220f9d94eSRobert Foss 383320f9d94eSRobert Foss thermal-sensors = <&tsens0 11>; 383420f9d94eSRobert Foss 383520f9d94eSRobert Foss trips { 383620f9d94eSRobert Foss cpu4_bottom_alert0: trip-point0 { 383720f9d94eSRobert Foss temperature = <90000>; 383820f9d94eSRobert Foss hysteresis = <2000>; 383920f9d94eSRobert Foss type = "passive"; 384020f9d94eSRobert Foss }; 384120f9d94eSRobert Foss 384220f9d94eSRobert Foss cpu4_bottom_alert1: trip-point1 { 384320f9d94eSRobert Foss temperature = <95000>; 384420f9d94eSRobert Foss hysteresis = <2000>; 384520f9d94eSRobert Foss type = "passive"; 384620f9d94eSRobert Foss }; 384720f9d94eSRobert Foss 38481364acc3SKrzysztof Kozlowski cpu4_bottom_crit: cpu-crit { 384920f9d94eSRobert Foss temperature = <110000>; 385020f9d94eSRobert Foss hysteresis = <1000>; 385120f9d94eSRobert Foss type = "critical"; 385220f9d94eSRobert Foss }; 385320f9d94eSRobert Foss }; 385420f9d94eSRobert Foss 385520f9d94eSRobert Foss cooling-maps { 385620f9d94eSRobert Foss map0 { 385720f9d94eSRobert Foss trip = <&cpu4_bottom_alert0>; 385820f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 385920f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386020f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386120f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 386220f9d94eSRobert Foss }; 386320f9d94eSRobert Foss map1 { 386420f9d94eSRobert Foss trip = <&cpu4_bottom_alert1>; 386520f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386620f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386720f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386820f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 386920f9d94eSRobert Foss }; 387020f9d94eSRobert Foss }; 387120f9d94eSRobert Foss }; 387220f9d94eSRobert Foss 387320f9d94eSRobert Foss cpu5-bottom-thermal { 387420f9d94eSRobert Foss polling-delay-passive = <250>; 387520f9d94eSRobert Foss polling-delay = <1000>; 387620f9d94eSRobert Foss 387720f9d94eSRobert Foss thermal-sensors = <&tsens0 12>; 387820f9d94eSRobert Foss 387920f9d94eSRobert Foss trips { 388020f9d94eSRobert Foss cpu5_bottom_alert0: trip-point0 { 388120f9d94eSRobert Foss temperature = <90000>; 388220f9d94eSRobert Foss hysteresis = <2000>; 388320f9d94eSRobert Foss type = "passive"; 388420f9d94eSRobert Foss }; 388520f9d94eSRobert Foss 388620f9d94eSRobert Foss cpu5_bottom_alert1: trip-point1 { 388720f9d94eSRobert Foss temperature = <95000>; 388820f9d94eSRobert Foss hysteresis = <2000>; 388920f9d94eSRobert Foss type = "passive"; 389020f9d94eSRobert Foss }; 389120f9d94eSRobert Foss 38921364acc3SKrzysztof Kozlowski cpu5_bottom_crit: cpu-crit { 389320f9d94eSRobert Foss temperature = <110000>; 389420f9d94eSRobert Foss hysteresis = <1000>; 389520f9d94eSRobert Foss type = "critical"; 389620f9d94eSRobert Foss }; 389720f9d94eSRobert Foss }; 389820f9d94eSRobert Foss 389920f9d94eSRobert Foss cooling-maps { 390020f9d94eSRobert Foss map0 { 390120f9d94eSRobert Foss trip = <&cpu5_bottom_alert0>; 390220f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 390320f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 390420f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 390520f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 390620f9d94eSRobert Foss }; 390720f9d94eSRobert Foss map1 { 390820f9d94eSRobert Foss trip = <&cpu5_bottom_alert1>; 390920f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 391020f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 391120f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 391220f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 391320f9d94eSRobert Foss }; 391420f9d94eSRobert Foss }; 391520f9d94eSRobert Foss }; 391620f9d94eSRobert Foss 391720f9d94eSRobert Foss cpu6-bottom-thermal { 391820f9d94eSRobert Foss polling-delay-passive = <250>; 391920f9d94eSRobert Foss polling-delay = <1000>; 392020f9d94eSRobert Foss 392120f9d94eSRobert Foss thermal-sensors = <&tsens0 13>; 392220f9d94eSRobert Foss 392320f9d94eSRobert Foss trips { 392420f9d94eSRobert Foss cpu6_bottom_alert0: trip-point0 { 392520f9d94eSRobert Foss temperature = <90000>; 392620f9d94eSRobert Foss hysteresis = <2000>; 392720f9d94eSRobert Foss type = "passive"; 392820f9d94eSRobert Foss }; 392920f9d94eSRobert Foss 393020f9d94eSRobert Foss cpu6_bottom_alert1: trip-point1 { 393120f9d94eSRobert Foss temperature = <95000>; 393220f9d94eSRobert Foss hysteresis = <2000>; 393320f9d94eSRobert Foss type = "passive"; 393420f9d94eSRobert Foss }; 393520f9d94eSRobert Foss 39361364acc3SKrzysztof Kozlowski cpu6_bottom_crit: cpu-crit { 393720f9d94eSRobert Foss temperature = <110000>; 393820f9d94eSRobert Foss hysteresis = <1000>; 393920f9d94eSRobert Foss type = "critical"; 394020f9d94eSRobert Foss }; 394120f9d94eSRobert Foss }; 394220f9d94eSRobert Foss 394320f9d94eSRobert Foss cooling-maps { 394420f9d94eSRobert Foss map0 { 394520f9d94eSRobert Foss trip = <&cpu6_bottom_alert0>; 394620f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 394720f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 394820f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 394920f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 395020f9d94eSRobert Foss }; 395120f9d94eSRobert Foss map1 { 395220f9d94eSRobert Foss trip = <&cpu6_bottom_alert1>; 395320f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395420f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395520f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395620f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 395720f9d94eSRobert Foss }; 395820f9d94eSRobert Foss }; 395920f9d94eSRobert Foss }; 396020f9d94eSRobert Foss 396120f9d94eSRobert Foss cpu7-bottom-thermal { 396220f9d94eSRobert Foss polling-delay-passive = <250>; 396320f9d94eSRobert Foss polling-delay = <1000>; 396420f9d94eSRobert Foss 396520f9d94eSRobert Foss thermal-sensors = <&tsens0 14>; 396620f9d94eSRobert Foss 396720f9d94eSRobert Foss trips { 396820f9d94eSRobert Foss cpu7_bottom_alert0: trip-point0 { 396920f9d94eSRobert Foss temperature = <90000>; 397020f9d94eSRobert Foss hysteresis = <2000>; 397120f9d94eSRobert Foss type = "passive"; 397220f9d94eSRobert Foss }; 397320f9d94eSRobert Foss 397420f9d94eSRobert Foss cpu7_bottom_alert1: trip-point1 { 397520f9d94eSRobert Foss temperature = <95000>; 397620f9d94eSRobert Foss hysteresis = <2000>; 397720f9d94eSRobert Foss type = "passive"; 397820f9d94eSRobert Foss }; 397920f9d94eSRobert Foss 39801364acc3SKrzysztof Kozlowski cpu7_bottom_crit: cpu-crit { 398120f9d94eSRobert Foss temperature = <110000>; 398220f9d94eSRobert Foss hysteresis = <1000>; 398320f9d94eSRobert Foss type = "critical"; 398420f9d94eSRobert Foss }; 398520f9d94eSRobert Foss }; 398620f9d94eSRobert Foss 398720f9d94eSRobert Foss cooling-maps { 398820f9d94eSRobert Foss map0 { 398920f9d94eSRobert Foss trip = <&cpu7_bottom_alert0>; 399020f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 399120f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 399220f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 399320f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 399420f9d94eSRobert Foss }; 399520f9d94eSRobert Foss map1 { 399620f9d94eSRobert Foss trip = <&cpu7_bottom_alert1>; 399720f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 399820f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 399920f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 400020f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 400120f9d94eSRobert Foss }; 400220f9d94eSRobert Foss }; 400320f9d94eSRobert Foss }; 400420f9d94eSRobert Foss 400520f9d94eSRobert Foss aoss0-thermal { 400620f9d94eSRobert Foss polling-delay-passive = <250>; 400720f9d94eSRobert Foss polling-delay = <1000>; 400820f9d94eSRobert Foss 400920f9d94eSRobert Foss thermal-sensors = <&tsens0 0>; 401020f9d94eSRobert Foss 401120f9d94eSRobert Foss trips { 401220f9d94eSRobert Foss aoss0_alert0: trip-point0 { 401320f9d94eSRobert Foss temperature = <90000>; 401420f9d94eSRobert Foss hysteresis = <2000>; 401520f9d94eSRobert Foss type = "hot"; 401620f9d94eSRobert Foss }; 401720f9d94eSRobert Foss }; 401820f9d94eSRobert Foss }; 401920f9d94eSRobert Foss 402020f9d94eSRobert Foss cluster0-thermal { 402120f9d94eSRobert Foss polling-delay-passive = <250>; 402220f9d94eSRobert Foss polling-delay = <1000>; 402320f9d94eSRobert Foss 402420f9d94eSRobert Foss thermal-sensors = <&tsens0 5>; 402520f9d94eSRobert Foss 402620f9d94eSRobert Foss trips { 402720f9d94eSRobert Foss cluster0_alert0: trip-point0 { 402820f9d94eSRobert Foss temperature = <90000>; 402920f9d94eSRobert Foss hysteresis = <2000>; 403020f9d94eSRobert Foss type = "hot"; 403120f9d94eSRobert Foss }; 403220f9d94eSRobert Foss cluster0_crit: cluster0_crit { 403320f9d94eSRobert Foss temperature = <110000>; 403420f9d94eSRobert Foss hysteresis = <2000>; 403520f9d94eSRobert Foss type = "critical"; 403620f9d94eSRobert Foss }; 403720f9d94eSRobert Foss }; 403820f9d94eSRobert Foss }; 403920f9d94eSRobert Foss 404020f9d94eSRobert Foss cluster1-thermal { 404120f9d94eSRobert Foss polling-delay-passive = <250>; 404220f9d94eSRobert Foss polling-delay = <1000>; 404320f9d94eSRobert Foss 404420f9d94eSRobert Foss thermal-sensors = <&tsens0 6>; 404520f9d94eSRobert Foss 404620f9d94eSRobert Foss trips { 404720f9d94eSRobert Foss cluster1_alert0: trip-point0 { 404820f9d94eSRobert Foss temperature = <90000>; 404920f9d94eSRobert Foss hysteresis = <2000>; 405020f9d94eSRobert Foss type = "hot"; 405120f9d94eSRobert Foss }; 405220f9d94eSRobert Foss cluster1_crit: cluster1_crit { 405320f9d94eSRobert Foss temperature = <110000>; 405420f9d94eSRobert Foss hysteresis = <2000>; 405520f9d94eSRobert Foss type = "critical"; 405620f9d94eSRobert Foss }; 405720f9d94eSRobert Foss }; 405820f9d94eSRobert Foss }; 405920f9d94eSRobert Foss 406020f9d94eSRobert Foss aoss1-thermal { 406120f9d94eSRobert Foss polling-delay-passive = <250>; 406220f9d94eSRobert Foss polling-delay = <1000>; 406320f9d94eSRobert Foss 406420f9d94eSRobert Foss thermal-sensors = <&tsens1 0>; 406520f9d94eSRobert Foss 406620f9d94eSRobert Foss trips { 406720f9d94eSRobert Foss aoss1_alert0: trip-point0 { 406820f9d94eSRobert Foss temperature = <90000>; 406920f9d94eSRobert Foss hysteresis = <2000>; 407020f9d94eSRobert Foss type = "hot"; 407120f9d94eSRobert Foss }; 407220f9d94eSRobert Foss }; 407320f9d94eSRobert Foss }; 407420f9d94eSRobert Foss 40757be1c395SDavid Heidelberg gpu-top-thermal { 407620f9d94eSRobert Foss polling-delay-passive = <250>; 407720f9d94eSRobert Foss polling-delay = <1000>; 407820f9d94eSRobert Foss 407920f9d94eSRobert Foss thermal-sensors = <&tsens1 1>; 408020f9d94eSRobert Foss 408120f9d94eSRobert Foss trips { 408220f9d94eSRobert Foss gpu1_alert0: trip-point0 { 408320f9d94eSRobert Foss temperature = <90000>; 408420f9d94eSRobert Foss hysteresis = <1000>; 408520f9d94eSRobert Foss type = "hot"; 408620f9d94eSRobert Foss }; 408720f9d94eSRobert Foss }; 408820f9d94eSRobert Foss }; 408920f9d94eSRobert Foss 40907be1c395SDavid Heidelberg gpu-bottom-thermal { 409120f9d94eSRobert Foss polling-delay-passive = <250>; 409220f9d94eSRobert Foss polling-delay = <1000>; 409320f9d94eSRobert Foss 409420f9d94eSRobert Foss thermal-sensors = <&tsens1 2>; 409520f9d94eSRobert Foss 409620f9d94eSRobert Foss trips { 409720f9d94eSRobert Foss gpu2_alert0: trip-point0 { 409820f9d94eSRobert Foss temperature = <90000>; 409920f9d94eSRobert Foss hysteresis = <1000>; 410020f9d94eSRobert Foss type = "hot"; 410120f9d94eSRobert Foss }; 410220f9d94eSRobert Foss }; 410320f9d94eSRobert Foss }; 410420f9d94eSRobert Foss 410520f9d94eSRobert Foss nspss1-thermal { 410620f9d94eSRobert Foss polling-delay-passive = <250>; 410720f9d94eSRobert Foss polling-delay = <1000>; 410820f9d94eSRobert Foss 410920f9d94eSRobert Foss thermal-sensors = <&tsens1 3>; 411020f9d94eSRobert Foss 411120f9d94eSRobert Foss trips { 411220f9d94eSRobert Foss nspss1_alert0: trip-point0 { 411320f9d94eSRobert Foss temperature = <90000>; 411420f9d94eSRobert Foss hysteresis = <1000>; 411520f9d94eSRobert Foss type = "hot"; 411620f9d94eSRobert Foss }; 411720f9d94eSRobert Foss }; 411820f9d94eSRobert Foss }; 411920f9d94eSRobert Foss 412020f9d94eSRobert Foss nspss2-thermal { 412120f9d94eSRobert Foss polling-delay-passive = <250>; 412220f9d94eSRobert Foss polling-delay = <1000>; 412320f9d94eSRobert Foss 412420f9d94eSRobert Foss thermal-sensors = <&tsens1 4>; 412520f9d94eSRobert Foss 412620f9d94eSRobert Foss trips { 412720f9d94eSRobert Foss nspss2_alert0: trip-point0 { 412820f9d94eSRobert Foss temperature = <90000>; 412920f9d94eSRobert Foss hysteresis = <1000>; 413020f9d94eSRobert Foss type = "hot"; 413120f9d94eSRobert Foss }; 413220f9d94eSRobert Foss }; 413320f9d94eSRobert Foss }; 413420f9d94eSRobert Foss 413520f9d94eSRobert Foss nspss3-thermal { 413620f9d94eSRobert Foss polling-delay-passive = <250>; 413720f9d94eSRobert Foss polling-delay = <1000>; 413820f9d94eSRobert Foss 413920f9d94eSRobert Foss thermal-sensors = <&tsens1 5>; 414020f9d94eSRobert Foss 414120f9d94eSRobert Foss trips { 414220f9d94eSRobert Foss nspss3_alert0: trip-point0 { 414320f9d94eSRobert Foss temperature = <90000>; 414420f9d94eSRobert Foss hysteresis = <1000>; 414520f9d94eSRobert Foss type = "hot"; 414620f9d94eSRobert Foss }; 414720f9d94eSRobert Foss }; 414820f9d94eSRobert Foss }; 414920f9d94eSRobert Foss 415020f9d94eSRobert Foss video-thermal { 415120f9d94eSRobert Foss polling-delay-passive = <250>; 415220f9d94eSRobert Foss polling-delay = <1000>; 415320f9d94eSRobert Foss 415420f9d94eSRobert Foss thermal-sensors = <&tsens1 6>; 415520f9d94eSRobert Foss 415620f9d94eSRobert Foss trips { 415720f9d94eSRobert Foss video_alert0: trip-point0 { 415820f9d94eSRobert Foss temperature = <90000>; 415920f9d94eSRobert Foss hysteresis = <2000>; 416020f9d94eSRobert Foss type = "hot"; 416120f9d94eSRobert Foss }; 416220f9d94eSRobert Foss }; 416320f9d94eSRobert Foss }; 416420f9d94eSRobert Foss 416520f9d94eSRobert Foss mem-thermal { 416620f9d94eSRobert Foss polling-delay-passive = <250>; 416720f9d94eSRobert Foss polling-delay = <1000>; 416820f9d94eSRobert Foss 416920f9d94eSRobert Foss thermal-sensors = <&tsens1 7>; 417020f9d94eSRobert Foss 417120f9d94eSRobert Foss trips { 417220f9d94eSRobert Foss mem_alert0: trip-point0 { 417320f9d94eSRobert Foss temperature = <90000>; 417420f9d94eSRobert Foss hysteresis = <2000>; 417520f9d94eSRobert Foss type = "hot"; 417620f9d94eSRobert Foss }; 417720f9d94eSRobert Foss }; 417820f9d94eSRobert Foss }; 417920f9d94eSRobert Foss 41807be1c395SDavid Heidelberg modem1-top-thermal { 418120f9d94eSRobert Foss polling-delay-passive = <250>; 418220f9d94eSRobert Foss polling-delay = <1000>; 418320f9d94eSRobert Foss 418420f9d94eSRobert Foss thermal-sensors = <&tsens1 8>; 418520f9d94eSRobert Foss 418620f9d94eSRobert Foss trips { 418720f9d94eSRobert Foss modem1_alert0: trip-point0 { 418820f9d94eSRobert Foss temperature = <90000>; 418920f9d94eSRobert Foss hysteresis = <2000>; 419020f9d94eSRobert Foss type = "hot"; 419120f9d94eSRobert Foss }; 419220f9d94eSRobert Foss }; 419320f9d94eSRobert Foss }; 419420f9d94eSRobert Foss 41957be1c395SDavid Heidelberg modem2-top-thermal { 419620f9d94eSRobert Foss polling-delay-passive = <250>; 419720f9d94eSRobert Foss polling-delay = <1000>; 419820f9d94eSRobert Foss 419920f9d94eSRobert Foss thermal-sensors = <&tsens1 9>; 420020f9d94eSRobert Foss 420120f9d94eSRobert Foss trips { 420220f9d94eSRobert Foss modem2_alert0: trip-point0 { 420320f9d94eSRobert Foss temperature = <90000>; 420420f9d94eSRobert Foss hysteresis = <2000>; 420520f9d94eSRobert Foss type = "hot"; 420620f9d94eSRobert Foss }; 420720f9d94eSRobert Foss }; 420820f9d94eSRobert Foss }; 420920f9d94eSRobert Foss 42107be1c395SDavid Heidelberg modem3-top-thermal { 421120f9d94eSRobert Foss polling-delay-passive = <250>; 421220f9d94eSRobert Foss polling-delay = <1000>; 421320f9d94eSRobert Foss 421420f9d94eSRobert Foss thermal-sensors = <&tsens1 10>; 421520f9d94eSRobert Foss 421620f9d94eSRobert Foss trips { 421720f9d94eSRobert Foss modem3_alert0: trip-point0 { 421820f9d94eSRobert Foss temperature = <90000>; 421920f9d94eSRobert Foss hysteresis = <2000>; 422020f9d94eSRobert Foss type = "hot"; 422120f9d94eSRobert Foss }; 422220f9d94eSRobert Foss }; 422320f9d94eSRobert Foss }; 422420f9d94eSRobert Foss 42257be1c395SDavid Heidelberg modem4-top-thermal { 422620f9d94eSRobert Foss polling-delay-passive = <250>; 422720f9d94eSRobert Foss polling-delay = <1000>; 422820f9d94eSRobert Foss 422920f9d94eSRobert Foss thermal-sensors = <&tsens1 11>; 423020f9d94eSRobert Foss 423120f9d94eSRobert Foss trips { 423220f9d94eSRobert Foss modem4_alert0: trip-point0 { 423320f9d94eSRobert Foss temperature = <90000>; 423420f9d94eSRobert Foss hysteresis = <2000>; 423520f9d94eSRobert Foss type = "hot"; 423620f9d94eSRobert Foss }; 423720f9d94eSRobert Foss }; 423820f9d94eSRobert Foss }; 423920f9d94eSRobert Foss 42407be1c395SDavid Heidelberg camera-top-thermal { 424120f9d94eSRobert Foss polling-delay-passive = <250>; 424220f9d94eSRobert Foss polling-delay = <1000>; 424320f9d94eSRobert Foss 424420f9d94eSRobert Foss thermal-sensors = <&tsens1 12>; 424520f9d94eSRobert Foss 424620f9d94eSRobert Foss trips { 424720f9d94eSRobert Foss camera1_alert0: trip-point0 { 424820f9d94eSRobert Foss temperature = <90000>; 424920f9d94eSRobert Foss hysteresis = <2000>; 425020f9d94eSRobert Foss type = "hot"; 425120f9d94eSRobert Foss }; 425220f9d94eSRobert Foss }; 425320f9d94eSRobert Foss }; 425420f9d94eSRobert Foss 42557be1c395SDavid Heidelberg cam-bottom-thermal { 425620f9d94eSRobert Foss polling-delay-passive = <250>; 425720f9d94eSRobert Foss polling-delay = <1000>; 425820f9d94eSRobert Foss 425920f9d94eSRobert Foss thermal-sensors = <&tsens1 13>; 426020f9d94eSRobert Foss 426120f9d94eSRobert Foss trips { 426220f9d94eSRobert Foss camera2_alert0: trip-point0 { 426320f9d94eSRobert Foss temperature = <90000>; 426420f9d94eSRobert Foss hysteresis = <2000>; 426520f9d94eSRobert Foss type = "hot"; 426620f9d94eSRobert Foss }; 426720f9d94eSRobert Foss }; 426820f9d94eSRobert Foss }; 426920f9d94eSRobert Foss }; 427020f9d94eSRobert Foss 4271b7e8f433SVinod Koul timer { 4272b7e8f433SVinod Koul compatible = "arm,armv8-timer"; 4273b7e8f433SVinod Koul interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4274b7e8f433SVinod Koul <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4275b7e8f433SVinod Koul <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4276b7e8f433SVinod Koul <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4277b7e8f433SVinod Koul }; 4278b7e8f433SVinod Koul}; 4279