1b7e8f433SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2b7e8f433SVinod Koul/* 3b7e8f433SVinod Koul * Copyright (c) 2020, Linaro Limaited 4b7e8f433SVinod Koul */ 5b7e8f433SVinod Koul 6b7e8f433SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 7b7e8f433SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 8b7e8f433SVinod Koul#include <dt-bindings/mailbox/qcom-ipcc.h> 9b7e8f433SVinod Koul#include <dt-bindings/power/qcom-aoss-qmp.h> 10b7e8f433SVinod Koul#include <dt-bindings/power/qcom-rpmpd.h> 11b7e8f433SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12b7e8f433SVinod Koul 13b7e8f433SVinod Koul/ { 14b7e8f433SVinod Koul interrupt-parent = <&intc>; 15b7e8f433SVinod Koul 16b7e8f433SVinod Koul #address-cells = <2>; 17b7e8f433SVinod Koul #size-cells = <2>; 18b7e8f433SVinod Koul 19b7e8f433SVinod Koul chosen { }; 20b7e8f433SVinod Koul 21b7e8f433SVinod Koul clocks { 22b7e8f433SVinod Koul xo_board: xo-board { 23b7e8f433SVinod Koul compatible = "fixed-clock"; 24b7e8f433SVinod Koul #clock-cells = <0>; 25b7e8f433SVinod Koul clock-frequency = <38400000>; 26b7e8f433SVinod Koul clock-output-names = "xo_board"; 27b7e8f433SVinod Koul }; 28b7e8f433SVinod Koul 29b7e8f433SVinod Koul sleep_clk: sleep-clk { 30b7e8f433SVinod Koul compatible = "fixed-clock"; 31b7e8f433SVinod Koul clock-frequency = <32000>; 32b7e8f433SVinod Koul #clock-cells = <0>; 33b7e8f433SVinod Koul }; 34b7e8f433SVinod Koul }; 35b7e8f433SVinod Koul 36b7e8f433SVinod Koul cpus { 37b7e8f433SVinod Koul #address-cells = <2>; 38b7e8f433SVinod Koul #size-cells = <0>; 39b7e8f433SVinod Koul 40b7e8f433SVinod Koul CPU0: cpu@0 { 41b7e8f433SVinod Koul device_type = "cpu"; 42b7e8f433SVinod Koul compatible = "qcom,kryo685"; 43b7e8f433SVinod Koul reg = <0x0 0x0>; 44b7e8f433SVinod Koul enable-method = "psci"; 45b7e8f433SVinod Koul next-level-cache = <&L2_0>; 46b7e8f433SVinod Koul L2_0: l2-cache { 47b7e8f433SVinod Koul compatible = "cache"; 48b7e8f433SVinod Koul next-level-cache = <&L3_0>; 49b7e8f433SVinod Koul L3_0: l3-cache { 50b7e8f433SVinod Koul compatible = "cache"; 51b7e8f433SVinod Koul }; 52b7e8f433SVinod Koul }; 53b7e8f433SVinod Koul }; 54b7e8f433SVinod Koul 55b7e8f433SVinod Koul CPU1: cpu@100 { 56b7e8f433SVinod Koul device_type = "cpu"; 57b7e8f433SVinod Koul compatible = "qcom,kryo685"; 58b7e8f433SVinod Koul reg = <0x0 0x100>; 59b7e8f433SVinod Koul enable-method = "psci"; 60b7e8f433SVinod Koul next-level-cache = <&L2_100>; 61b7e8f433SVinod Koul L2_100: l2-cache { 62b7e8f433SVinod Koul compatible = "cache"; 63b7e8f433SVinod Koul next-level-cache = <&L3_0>; 64b7e8f433SVinod Koul }; 65b7e8f433SVinod Koul }; 66b7e8f433SVinod Koul 67b7e8f433SVinod Koul CPU2: cpu@200 { 68b7e8f433SVinod Koul device_type = "cpu"; 69b7e8f433SVinod Koul compatible = "qcom,kryo685"; 70b7e8f433SVinod Koul reg = <0x0 0x200>; 71b7e8f433SVinod Koul enable-method = "psci"; 72b7e8f433SVinod Koul next-level-cache = <&L2_200>; 73b7e8f433SVinod Koul L2_200: l2-cache { 74b7e8f433SVinod Koul compatible = "cache"; 75b7e8f433SVinod Koul next-level-cache = <&L3_0>; 76b7e8f433SVinod Koul }; 77b7e8f433SVinod Koul }; 78b7e8f433SVinod Koul 79b7e8f433SVinod Koul CPU3: cpu@300 { 80b7e8f433SVinod Koul device_type = "cpu"; 81b7e8f433SVinod Koul compatible = "qcom,kryo685"; 82b7e8f433SVinod Koul reg = <0x0 0x300>; 83b7e8f433SVinod Koul enable-method = "psci"; 84b7e8f433SVinod Koul next-level-cache = <&L2_300>; 85b7e8f433SVinod Koul L2_300: l2-cache { 86b7e8f433SVinod Koul compatible = "cache"; 87b7e8f433SVinod Koul next-level-cache = <&L3_0>; 88b7e8f433SVinod Koul }; 89b7e8f433SVinod Koul }; 90b7e8f433SVinod Koul 91b7e8f433SVinod Koul CPU4: cpu@400 { 92b7e8f433SVinod Koul device_type = "cpu"; 93b7e8f433SVinod Koul compatible = "qcom,kryo685"; 94b7e8f433SVinod Koul reg = <0x0 0x400>; 95b7e8f433SVinod Koul enable-method = "psci"; 96b7e8f433SVinod Koul next-level-cache = <&L2_400>; 97b7e8f433SVinod Koul L2_400: l2-cache { 98b7e8f433SVinod Koul compatible = "cache"; 99b7e8f433SVinod Koul next-level-cache = <&L3_0>; 100b7e8f433SVinod Koul }; 101b7e8f433SVinod Koul }; 102b7e8f433SVinod Koul 103b7e8f433SVinod Koul CPU5: cpu@500 { 104b7e8f433SVinod Koul device_type = "cpu"; 105b7e8f433SVinod Koul compatible = "qcom,kryo685"; 106b7e8f433SVinod Koul reg = <0x0 0x500>; 107b7e8f433SVinod Koul enable-method = "psci"; 108b7e8f433SVinod Koul next-level-cache = <&L2_500>; 109b7e8f433SVinod Koul L2_500: l2-cache { 110b7e8f433SVinod Koul compatible = "cache"; 111b7e8f433SVinod Koul next-level-cache = <&L3_0>; 112b7e8f433SVinod Koul }; 113b7e8f433SVinod Koul 114b7e8f433SVinod Koul }; 115b7e8f433SVinod Koul 116b7e8f433SVinod Koul CPU6: cpu@600 { 117b7e8f433SVinod Koul device_type = "cpu"; 118b7e8f433SVinod Koul compatible = "qcom,kryo685"; 119b7e8f433SVinod Koul reg = <0x0 0x600>; 120b7e8f433SVinod Koul enable-method = "psci"; 121b7e8f433SVinod Koul next-level-cache = <&L2_600>; 122b7e8f433SVinod Koul L2_600: l2-cache { 123b7e8f433SVinod Koul compatible = "cache"; 124b7e8f433SVinod Koul next-level-cache = <&L3_0>; 125b7e8f433SVinod Koul }; 126b7e8f433SVinod Koul }; 127b7e8f433SVinod Koul 128b7e8f433SVinod Koul CPU7: cpu@700 { 129b7e8f433SVinod Koul device_type = "cpu"; 130b7e8f433SVinod Koul compatible = "qcom,kryo685"; 131b7e8f433SVinod Koul reg = <0x0 0x700>; 132b7e8f433SVinod Koul enable-method = "psci"; 133b7e8f433SVinod Koul next-level-cache = <&L2_700>; 134b7e8f433SVinod Koul L2_700: l2-cache { 135b7e8f433SVinod Koul compatible = "cache"; 136b7e8f433SVinod Koul next-level-cache = <&L3_0>; 137b7e8f433SVinod Koul }; 138b7e8f433SVinod Koul }; 139b7e8f433SVinod Koul }; 140b7e8f433SVinod Koul 141b7e8f433SVinod Koul firmware { 142b7e8f433SVinod Koul scm: scm { 143b7e8f433SVinod Koul compatible = "qcom,scm-sm8350", "qcom,scm"; 144b7e8f433SVinod Koul #reset-cells = <1>; 145b7e8f433SVinod Koul }; 146b7e8f433SVinod Koul }; 147b7e8f433SVinod Koul 148b7e8f433SVinod Koul memory@80000000 { 149b7e8f433SVinod Koul device_type = "memory"; 150b7e8f433SVinod Koul /* We expect the bootloader to fill in the size */ 151b7e8f433SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 152b7e8f433SVinod Koul }; 153b7e8f433SVinod Koul 154b7e8f433SVinod Koul pmu { 155b7e8f433SVinod Koul compatible = "arm,armv8-pmuv3"; 156794d3e30SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 157b7e8f433SVinod Koul }; 158b7e8f433SVinod Koul 159b7e8f433SVinod Koul psci { 160b7e8f433SVinod Koul compatible = "arm,psci-1.0"; 161b7e8f433SVinod Koul method = "smc"; 162b7e8f433SVinod Koul }; 163b7e8f433SVinod Koul 164b7e8f433SVinod Koul reserved_memory: reserved-memory { 165b7e8f433SVinod Koul #address-cells = <2>; 166b7e8f433SVinod Koul #size-cells = <2>; 167b7e8f433SVinod Koul ranges; 168b7e8f433SVinod Koul 169b7e8f433SVinod Koul hyp_mem: memory@80000000 { 170b7e8f433SVinod Koul reg = <0x0 0x80000000 0x0 0x600000>; 171b7e8f433SVinod Koul no-map; 172b7e8f433SVinod Koul }; 173b7e8f433SVinod Koul 174b7e8f433SVinod Koul xbl_aop_mem: memory@80700000 { 175b7e8f433SVinod Koul no-map; 176b7e8f433SVinod Koul reg = <0x0 0x80700000 0x0 0x160000>; 177b7e8f433SVinod Koul }; 178b7e8f433SVinod Koul 179b7e8f433SVinod Koul cmd_db: memory@80860000 { 180b7e8f433SVinod Koul compatible = "qcom,cmd-db"; 181b7e8f433SVinod Koul reg = <0x0 0x80860000 0x0 0x20000>; 182b7e8f433SVinod Koul no-map; 183b7e8f433SVinod Koul }; 184b7e8f433SVinod Koul 185b7e8f433SVinod Koul reserved_xbl_uefi_log: memory@80880000 { 186b7e8f433SVinod Koul reg = <0x0 0x80880000 0x0 0x14000>; 187b7e8f433SVinod Koul no-map; 188b7e8f433SVinod Koul }; 189b7e8f433SVinod Koul 190b7e8f433SVinod Koul smem_mem: memory@80900000 { 191b7e8f433SVinod Koul reg = <0x0 0x80900000 0x0 0x200000>; 192b7e8f433SVinod Koul no-map; 193b7e8f433SVinod Koul }; 194b7e8f433SVinod Koul 195b7e8f433SVinod Koul cpucp_fw_mem: memory@80b00000 { 196b7e8f433SVinod Koul reg = <0x0 0x80b00000 0x0 0x100000>; 197b7e8f433SVinod Koul no-map; 198b7e8f433SVinod Koul }; 199b7e8f433SVinod Koul 200b7e8f433SVinod Koul cdsp_secure_heap: memory@80c00000 { 201b7e8f433SVinod Koul reg = <0x0 0x80c00000 0x0 0x4600000>; 202b7e8f433SVinod Koul no-map; 203b7e8f433SVinod Koul }; 204b7e8f433SVinod Koul 205b7e8f433SVinod Koul pil_camera_mem: mmeory@85200000 { 206b7e8f433SVinod Koul reg = <0x0 0x85200000 0x0 0x500000>; 207b7e8f433SVinod Koul no-map; 208b7e8f433SVinod Koul }; 209b7e8f433SVinod Koul 210b7e8f433SVinod Koul pil_video_mem: memory@85700000 { 211b7e8f433SVinod Koul reg = <0x0 0x85700000 0x0 0x500000>; 212b7e8f433SVinod Koul no-map; 213b7e8f433SVinod Koul }; 214b7e8f433SVinod Koul 215b7e8f433SVinod Koul pil_cvp_mem: memory@85c00000 { 216b7e8f433SVinod Koul reg = <0x0 0x85c00000 0x0 0x500000>; 217b7e8f433SVinod Koul no-map; 218b7e8f433SVinod Koul }; 219b7e8f433SVinod Koul 220b7e8f433SVinod Koul pil_adsp_mem: memory@86100000 { 221b7e8f433SVinod Koul reg = <0x0 0x86100000 0x0 0x2100000>; 222b7e8f433SVinod Koul no-map; 223b7e8f433SVinod Koul }; 224b7e8f433SVinod Koul 225b7e8f433SVinod Koul pil_slpi_mem: memory@88200000 { 226b7e8f433SVinod Koul reg = <0x0 0x88200000 0x0 0x1500000>; 227b7e8f433SVinod Koul no-map; 228b7e8f433SVinod Koul }; 229b7e8f433SVinod Koul 230b7e8f433SVinod Koul pil_cdsp_mem: memory@89700000 { 231b7e8f433SVinod Koul reg = <0x0 0x89700000 0x0 0x1e00000>; 232b7e8f433SVinod Koul no-map; 233b7e8f433SVinod Koul }; 234b7e8f433SVinod Koul 235b7e8f433SVinod Koul pil_ipa_fw_mem: memory@8b500000 { 236b7e8f433SVinod Koul reg = <0x0 0x8b500000 0x0 0x10000>; 237b7e8f433SVinod Koul no-map; 238b7e8f433SVinod Koul }; 239b7e8f433SVinod Koul 240b7e8f433SVinod Koul pil_ipa_gsi_mem: memory@8b510000 { 241b7e8f433SVinod Koul reg = <0x0 0x8b510000 0x0 0xa000>; 242b7e8f433SVinod Koul no-map; 243b7e8f433SVinod Koul }; 244b7e8f433SVinod Koul 245b7e8f433SVinod Koul pil_gpu_mem: memory@8b51a000 { 246b7e8f433SVinod Koul reg = <0x0 0x8b51a000 0x0 0x2000>; 247b7e8f433SVinod Koul no-map; 248b7e8f433SVinod Koul }; 249b7e8f433SVinod Koul 250b7e8f433SVinod Koul pil_spss_mem: memory@8b600000 { 251b7e8f433SVinod Koul reg = <0x0 0x8b600000 0x0 0x100000>; 252b7e8f433SVinod Koul no-map; 253b7e8f433SVinod Koul }; 254b7e8f433SVinod Koul 255b7e8f433SVinod Koul pil_modem_mem: memory@8b800000 { 256b7e8f433SVinod Koul reg = <0x0 0x8b800000 0x0 0x10000000>; 257b7e8f433SVinod Koul no-map; 258b7e8f433SVinod Koul }; 259b7e8f433SVinod Koul 260b7e8f433SVinod Koul hyp_reserved_mem: memory@d0000000 { 261b7e8f433SVinod Koul reg = <0x0 0xd0000000 0x0 0x800000>; 262b7e8f433SVinod Koul no-map; 263b7e8f433SVinod Koul }; 264b7e8f433SVinod Koul 265b7e8f433SVinod Koul pil_trustedvm_mem: memory@d0800000 { 266b7e8f433SVinod Koul reg = <0x0 0xd0800000 0x0 0x76f7000>; 267b7e8f433SVinod Koul no-map; 268b7e8f433SVinod Koul }; 269b7e8f433SVinod Koul 270b7e8f433SVinod Koul qrtr_shbuf: memory@d7ef7000 { 271b7e8f433SVinod Koul reg = <0x0 0xd7ef7000 0x0 0x9000>; 272b7e8f433SVinod Koul no-map; 273b7e8f433SVinod Koul }; 274b7e8f433SVinod Koul 275b7e8f433SVinod Koul chan0_shbuf: memory@d7f00000 { 276b7e8f433SVinod Koul reg = <0x0 0xd7f00000 0x0 0x80000>; 277b7e8f433SVinod Koul no-map; 278b7e8f433SVinod Koul }; 279b7e8f433SVinod Koul 280b7e8f433SVinod Koul chan1_shbuf: memory@d7f80000 { 281b7e8f433SVinod Koul reg = <0x0 0xd7f80000 0x0 0x80000>; 282b7e8f433SVinod Koul no-map; 283b7e8f433SVinod Koul }; 284b7e8f433SVinod Koul 285b7e8f433SVinod Koul removed_mem: memory@d8800000 { 286b7e8f433SVinod Koul reg = <0x0 0xd8800000 0x0 0x6800000>; 287b7e8f433SVinod Koul no-map; 288b7e8f433SVinod Koul }; 289b7e8f433SVinod Koul }; 290b7e8f433SVinod Koul 291b7e8f433SVinod Koul smem: qcom,smem { 292b7e8f433SVinod Koul compatible = "qcom,smem"; 293b7e8f433SVinod Koul memory-region = <&smem_mem>; 294b7e8f433SVinod Koul hwlocks = <&tcsr_mutex 3>; 295b7e8f433SVinod Koul }; 296b7e8f433SVinod Koul 297b7e8f433SVinod Koul soc: soc@0 { 298b7e8f433SVinod Koul #address-cells = <2>; 299b7e8f433SVinod Koul #size-cells = <2>; 300b7e8f433SVinod Koul ranges = <0 0 0 0 0x10 0>; 301b7e8f433SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 302b7e8f433SVinod Koul compatible = "simple-bus"; 303b7e8f433SVinod Koul 304b7e8f433SVinod Koul gcc: clock-controller@100000 { 305b7e8f433SVinod Koul compatible = "qcom,gcc-sm8350"; 306b7e8f433SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 307b7e8f433SVinod Koul #clock-cells = <1>; 308b7e8f433SVinod Koul #reset-cells = <1>; 309b7e8f433SVinod Koul #power-domain-cells = <1>; 310b7e8f433SVinod Koul clock-names = "bi_tcxo", "sleep_clk"; 311b7e8f433SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 312b7e8f433SVinod Koul }; 313b7e8f433SVinod Koul 314b7e8f433SVinod Koul ipcc: mailbox@408000 { 315b7e8f433SVinod Koul compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 316b7e8f433SVinod Koul reg = <0 0x00408000 0 0x1000>; 317b7e8f433SVinod Koul interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 318b7e8f433SVinod Koul interrupt-controller; 319b7e8f433SVinod Koul #interrupt-cells = <3>; 320b7e8f433SVinod Koul #mbox-cells = <2>; 321b7e8f433SVinod Koul }; 322b7e8f433SVinod Koul 323b7e8f433SVinod Koul qupv3_id_1: geniqup@9c0000 { 324b7e8f433SVinod Koul compatible = "qcom,geni-se-qup"; 325b7e8f433SVinod Koul reg = <0x0 0x009c0000 0x0 0x6000>; 326b7e8f433SVinod Koul clock-names = "m-ahb", "s-ahb"; 327b7e8f433SVinod Koul clocks = <&gcc 121>, 328b7e8f433SVinod Koul <&gcc 122>; 329b7e8f433SVinod Koul #address-cells = <2>; 330b7e8f433SVinod Koul #size-cells = <2>; 331b7e8f433SVinod Koul ranges; 332b7e8f433SVinod Koul status = "disabled"; 333b7e8f433SVinod Koul 334b7e8f433SVinod Koul uart2: serial@98c000 { 335b7e8f433SVinod Koul compatible = "qcom,geni-debug-uart"; 336b7e8f433SVinod Koul reg = <0 0x0098c000 0 0x4000>; 337b7e8f433SVinod Koul clock-names = "se"; 338b7e8f433SVinod Koul clocks = <&gcc 83>; 339b7e8f433SVinod Koul pinctrl-names = "default"; 340b7e8f433SVinod Koul pinctrl-0 = <&qup_uart3_default_state>; 341b7e8f433SVinod Koul interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 342b7e8f433SVinod Koul #address-cells = <1>; 343b7e8f433SVinod Koul #size-cells = <0>; 344b7e8f433SVinod Koul status = "disabled"; 345b7e8f433SVinod Koul }; 346b7e8f433SVinod Koul }; 347b7e8f433SVinod Koul 348187f65b7SVinod Koul apps_smmu: iommu@15000000 { 349187f65b7SVinod Koul compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 350187f65b7SVinod Koul reg = <0 0x15000000 0 0x100000>; 351187f65b7SVinod Koul #iommu-cells = <2>; 352187f65b7SVinod Koul #global-interrupts = <2>; 353187f65b7SVinod Koul interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 354187f65b7SVinod Koul <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 355187f65b7SVinod Koul <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 356187f65b7SVinod Koul <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 357187f65b7SVinod Koul <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 358187f65b7SVinod Koul <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 359187f65b7SVinod Koul <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 360187f65b7SVinod Koul <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 361187f65b7SVinod Koul <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 362187f65b7SVinod Koul <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 363187f65b7SVinod Koul <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 364187f65b7SVinod Koul <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 365187f65b7SVinod Koul <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 366187f65b7SVinod Koul <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 367187f65b7SVinod Koul <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 368187f65b7SVinod Koul <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 369187f65b7SVinod Koul <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 370187f65b7SVinod Koul <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 371187f65b7SVinod Koul <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 372187f65b7SVinod Koul <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 373187f65b7SVinod Koul <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 374187f65b7SVinod Koul <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 375187f65b7SVinod Koul <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 376187f65b7SVinod Koul <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 377187f65b7SVinod Koul <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 378187f65b7SVinod Koul <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 379187f65b7SVinod Koul <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 380187f65b7SVinod Koul <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 381187f65b7SVinod Koul <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 382187f65b7SVinod Koul <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 383187f65b7SVinod Koul <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 384187f65b7SVinod Koul <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 385187f65b7SVinod Koul <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 386187f65b7SVinod Koul <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 387187f65b7SVinod Koul <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 388187f65b7SVinod Koul <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 389187f65b7SVinod Koul <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 390187f65b7SVinod Koul <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 391187f65b7SVinod Koul <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 392187f65b7SVinod Koul <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 393187f65b7SVinod Koul <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 394187f65b7SVinod Koul <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 395187f65b7SVinod Koul <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 396187f65b7SVinod Koul <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 397187f65b7SVinod Koul <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 398187f65b7SVinod Koul <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 399187f65b7SVinod Koul <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 400187f65b7SVinod Koul <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 401187f65b7SVinod Koul <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 402187f65b7SVinod Koul <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 403187f65b7SVinod Koul <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 404187f65b7SVinod Koul <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 405187f65b7SVinod Koul <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 406187f65b7SVinod Koul <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 407187f65b7SVinod Koul <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 408187f65b7SVinod Koul <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 409187f65b7SVinod Koul <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 410187f65b7SVinod Koul <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 411187f65b7SVinod Koul <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 412187f65b7SVinod Koul <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 413187f65b7SVinod Koul <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 414187f65b7SVinod Koul <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 415187f65b7SVinod Koul <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 416187f65b7SVinod Koul <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 417187f65b7SVinod Koul <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 418187f65b7SVinod Koul <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 419187f65b7SVinod Koul <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 420187f65b7SVinod Koul <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 421187f65b7SVinod Koul <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 422187f65b7SVinod Koul <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 423187f65b7SVinod Koul <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 424187f65b7SVinod Koul <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 425187f65b7SVinod Koul <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 426187f65b7SVinod Koul <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 427187f65b7SVinod Koul <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 428187f65b7SVinod Koul <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 429187f65b7SVinod Koul <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 430187f65b7SVinod Koul <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 431187f65b7SVinod Koul <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 432187f65b7SVinod Koul <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 433187f65b7SVinod Koul <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 434187f65b7SVinod Koul <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 435187f65b7SVinod Koul <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 436187f65b7SVinod Koul <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 437187f65b7SVinod Koul <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 438187f65b7SVinod Koul <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 439187f65b7SVinod Koul <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 440187f65b7SVinod Koul <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 441187f65b7SVinod Koul <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 442187f65b7SVinod Koul <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 443187f65b7SVinod Koul <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 444187f65b7SVinod Koul <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 445187f65b7SVinod Koul <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 446187f65b7SVinod Koul <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 447187f65b7SVinod Koul <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 448187f65b7SVinod Koul <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 449187f65b7SVinod Koul <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 450187f65b7SVinod Koul <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 451187f65b7SVinod Koul }; 452187f65b7SVinod Koul 453b7e8f433SVinod Koul tcsr_mutex: hwlock@1f40000 { 454b7e8f433SVinod Koul compatible = "qcom,tcsr-mutex"; 455b7e8f433SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 456b7e8f433SVinod Koul #hwlock-cells = <1>; 457b7e8f433SVinod Koul }; 458b7e8f433SVinod Koul 459b7e8f433SVinod Koul pdc: interrupt-controller@b220000 { 460b7e8f433SVinod Koul compatible = "qcom,sm8350-pdc", "qcom,pdc"; 461b7e8f433SVinod Koul reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 462b7e8f433SVinod Koul qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 463b7e8f433SVinod Koul <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 464b7e8f433SVinod Koul <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 465b7e8f433SVinod Koul <156 716 12>; 466b7e8f433SVinod Koul #interrupt-cells = <2>; 467b7e8f433SVinod Koul interrupt-parent = <&intc>; 468b7e8f433SVinod Koul interrupt-controller; 469b7e8f433SVinod Koul }; 470b7e8f433SVinod Koul 47197832fa8SSai Prakash Ranjan aoss_qmp: power-controller@c300000 { 472b7e8f433SVinod Koul compatible = "qcom,sm8350-aoss-qmp"; 473b7e8f433SVinod Koul reg = <0 0x0c300000 0 0x100000>; 474b7e8f433SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 475b7e8f433SVinod Koul IRQ_TYPE_EDGE_RISING>; 476b7e8f433SVinod Koul mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 477b7e8f433SVinod Koul 478b7e8f433SVinod Koul #clock-cells = <0>; 479b7e8f433SVinod Koul #power-domain-cells = <1>; 480b7e8f433SVinod Koul }; 481b7e8f433SVinod Koul 482b7e8f433SVinod Koul tlmm: pinctrl@f100000 { 483b7e8f433SVinod Koul compatible = "qcom,sm8350-tlmm"; 484b7e8f433SVinod Koul reg = <0 0x0f100000 0 0x300000>; 485b7e8f433SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 486b7e8f433SVinod Koul gpio-controller; 487b7e8f433SVinod Koul #gpio-cells = <2>; 488b7e8f433SVinod Koul interrupt-controller; 489b7e8f433SVinod Koul #interrupt-cells = <2>; 490b7e8f433SVinod Koul gpio-ranges = <&tlmm 0 0 203>; 491b7e8f433SVinod Koul 492b7e8f433SVinod Koul qup_uart3_default_state: qup-uart3-default-state { 493b7e8f433SVinod Koul rx { 494b7e8f433SVinod Koul pins = "gpio18"; 495b7e8f433SVinod Koul function = "qup3"; 496b7e8f433SVinod Koul }; 497b7e8f433SVinod Koul tx { 498b7e8f433SVinod Koul pins = "gpio19"; 499b7e8f433SVinod Koul function = "qup3"; 500b7e8f433SVinod Koul }; 501b7e8f433SVinod Koul }; 502b7e8f433SVinod Koul }; 503b7e8f433SVinod Koul 504b7e8f433SVinod Koul intc: interrupt-controller@17a00000 { 505b7e8f433SVinod Koul compatible = "arm,gic-v3"; 506b7e8f433SVinod Koul #interrupt-cells = <3>; 507b7e8f433SVinod Koul interrupt-controller; 508b7e8f433SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 509b7e8f433SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 510b7e8f433SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 511b7e8f433SVinod Koul }; 512b7e8f433SVinod Koul 513b7e8f433SVinod Koul timer@17c20000 { 514b7e8f433SVinod Koul compatible = "arm,armv7-timer-mem"; 515b7e8f433SVinod Koul #address-cells = <2>; 516b7e8f433SVinod Koul #size-cells = <2>; 517b7e8f433SVinod Koul ranges; 518b7e8f433SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 519b7e8f433SVinod Koul clock-frequency = <19200000>; 520b7e8f433SVinod Koul 521b7e8f433SVinod Koul frame@17c21000 { 522b7e8f433SVinod Koul frame-number = <0>; 523b7e8f433SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 524b7e8f433SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 525b7e8f433SVinod Koul reg = <0x0 0x17c21000 0x0 0x1000>, 526b7e8f433SVinod Koul <0x0 0x17c22000 0x0 0x1000>; 527b7e8f433SVinod Koul }; 528b7e8f433SVinod Koul 529b7e8f433SVinod Koul frame@17c23000 { 530b7e8f433SVinod Koul frame-number = <1>; 531b7e8f433SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 532b7e8f433SVinod Koul reg = <0x0 0x17c23000 0x0 0x1000>; 533b7e8f433SVinod Koul status = "disabled"; 534b7e8f433SVinod Koul }; 535b7e8f433SVinod Koul 536b7e8f433SVinod Koul frame@17c25000 { 537b7e8f433SVinod Koul frame-number = <2>; 538b7e8f433SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 539b7e8f433SVinod Koul reg = <0x0 0x17c25000 0x0 0x1000>; 540b7e8f433SVinod Koul status = "disabled"; 541b7e8f433SVinod Koul }; 542b7e8f433SVinod Koul 543b7e8f433SVinod Koul frame@17c27000 { 544b7e8f433SVinod Koul frame-number = <3>; 545b7e8f433SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 546b7e8f433SVinod Koul reg = <0x0 0x17c27000 0x0 0x1000>; 547b7e8f433SVinod Koul status = "disabled"; 548b7e8f433SVinod Koul }; 549b7e8f433SVinod Koul 550b7e8f433SVinod Koul frame@17c29000 { 551b7e8f433SVinod Koul frame-number = <4>; 552b7e8f433SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 553b7e8f433SVinod Koul reg = <0x0 0x17c29000 0x0 0x1000>; 554b7e8f433SVinod Koul status = "disabled"; 555b7e8f433SVinod Koul }; 556b7e8f433SVinod Koul 557b7e8f433SVinod Koul frame@17c2b000 { 558b7e8f433SVinod Koul frame-number = <5>; 559b7e8f433SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 560b7e8f433SVinod Koul reg = <0x0 0x17c2b000 0x0 0x1000>; 561b7e8f433SVinod Koul status = "disabled"; 562b7e8f433SVinod Koul }; 563b7e8f433SVinod Koul 564b7e8f433SVinod Koul frame@17c2d000 { 565b7e8f433SVinod Koul frame-number = <6>; 566b7e8f433SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 567b7e8f433SVinod Koul reg = <0x0 0x17c2d000 0x0 0x1000>; 568b7e8f433SVinod Koul status = "disabled"; 569b7e8f433SVinod Koul }; 570b7e8f433SVinod Koul }; 571b7e8f433SVinod Koul 572b7e8f433SVinod Koul apps_rsc: rsc@18200000 { 573b7e8f433SVinod Koul label = "apps_rsc"; 574b7e8f433SVinod Koul compatible = "qcom,rpmh-rsc"; 575b7e8f433SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 576b7e8f433SVinod Koul <0x0 0x18210000 0x0 0x10000>, 577b7e8f433SVinod Koul <0x0 0x18220000 0x0 0x10000>; 578b7e8f433SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 579b7e8f433SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 580b7e8f433SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 581b7e8f433SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 582b7e8f433SVinod Koul qcom,tcs-offset = <0xd00>; 583b7e8f433SVinod Koul qcom,drv-id = <2>; 584b7e8f433SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 585b7e8f433SVinod Koul <WAKE_TCS 3>, <CONTROL_TCS 1>; 586b7e8f433SVinod Koul 587b7e8f433SVinod Koul rpmhcc: clock-controller { 588b7e8f433SVinod Koul compatible = "qcom,sm8350-rpmh-clk"; 589b7e8f433SVinod Koul #clock-cells = <1>; 590b7e8f433SVinod Koul clock-names = "xo"; 591b7e8f433SVinod Koul clocks = <&xo_board>; 592b7e8f433SVinod Koul }; 593b7e8f433SVinod Koul 594b7e8f433SVinod Koul }; 595e780fb31SJack Pham 596*59c7cf81SVinod Koul ufs_mem_hc: ufshc@1d84000 { 597*59c7cf81SVinod Koul compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 598*59c7cf81SVinod Koul "jedec,ufs-2.0"; 599*59c7cf81SVinod Koul reg = <0 0x01d84000 0 0x3000>; 600*59c7cf81SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 601*59c7cf81SVinod Koul phys = <&ufs_mem_phy_lanes>; 602*59c7cf81SVinod Koul phy-names = "ufsphy"; 603*59c7cf81SVinod Koul lanes-per-direction = <2>; 604*59c7cf81SVinod Koul #reset-cells = <1>; 605*59c7cf81SVinod Koul resets = <&gcc 25>; 606*59c7cf81SVinod Koul reset-names = "rst"; 607*59c7cf81SVinod Koul 608*59c7cf81SVinod Koul power-domains = <&gcc 3>; 609*59c7cf81SVinod Koul 610*59c7cf81SVinod Koul iommus = <&apps_smmu 0xe0 0x0>; 611*59c7cf81SVinod Koul 612*59c7cf81SVinod Koul clock-names = 613*59c7cf81SVinod Koul "ref_clk", 614*59c7cf81SVinod Koul "core_clk", 615*59c7cf81SVinod Koul "bus_aggr_clk", 616*59c7cf81SVinod Koul "iface_clk", 617*59c7cf81SVinod Koul "core_clk_unipro", 618*59c7cf81SVinod Koul "ref_clk", 619*59c7cf81SVinod Koul "tx_lane0_sync_clk", 620*59c7cf81SVinod Koul "rx_lane0_sync_clk", 621*59c7cf81SVinod Koul "rx_lane1_sync_clk"; 622*59c7cf81SVinod Koul clocks = 623*59c7cf81SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 624*59c7cf81SVinod Koul <&gcc 155>, 625*59c7cf81SVinod Koul <&gcc 16>, 626*59c7cf81SVinod Koul <&gcc 154>, 627*59c7cf81SVinod Koul <&gcc 170>, 628*59c7cf81SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 629*59c7cf81SVinod Koul <&gcc 168>, 630*59c7cf81SVinod Koul <&gcc 164>, 631*59c7cf81SVinod Koul <&gcc 166>; 632*59c7cf81SVinod Koul freq-table-hz = 633*59c7cf81SVinod Koul <75000000 300000000>, 634*59c7cf81SVinod Koul <75000000 300000000>, 635*59c7cf81SVinod Koul <0 0>, 636*59c7cf81SVinod Koul <0 0>, 637*59c7cf81SVinod Koul <75000000 300000000>, 638*59c7cf81SVinod Koul <0 0>, 639*59c7cf81SVinod Koul <0 0>, 640*59c7cf81SVinod Koul <75000000 300000000>, 641*59c7cf81SVinod Koul <75000000 300000000>; 642*59c7cf81SVinod Koul status = "disabled"; 643*59c7cf81SVinod Koul }; 644*59c7cf81SVinod Koul 645*59c7cf81SVinod Koul ufs_mem_phy: phy@1d87000 { 646*59c7cf81SVinod Koul compatible = "qcom,sm8350-qmp-ufs-phy"; 647*59c7cf81SVinod Koul reg = <0 0x01d87000 0 0xe10>; 648*59c7cf81SVinod Koul #address-cells = <2>; 649*59c7cf81SVinod Koul #size-cells = <2>; 650*59c7cf81SVinod Koul #clock-cells = <1>; 651*59c7cf81SVinod Koul ranges; 652*59c7cf81SVinod Koul clock-names = "ref", 653*59c7cf81SVinod Koul "ref_aux"; 654*59c7cf81SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 655*59c7cf81SVinod Koul <&gcc 161>; 656*59c7cf81SVinod Koul 657*59c7cf81SVinod Koul resets = <&ufs_mem_hc 0>; 658*59c7cf81SVinod Koul reset-names = "ufsphy"; 659*59c7cf81SVinod Koul status = "disabled"; 660*59c7cf81SVinod Koul 661*59c7cf81SVinod Koul ufs_mem_phy_lanes: lanes@1d87400 { 662*59c7cf81SVinod Koul reg = <0 0x01d87400 0 0x108>, 663*59c7cf81SVinod Koul <0 0x01d87600 0 0x1e0>, 664*59c7cf81SVinod Koul <0 0x01d87c00 0 0x1dc>, 665*59c7cf81SVinod Koul <0 0x01d87800 0 0x108>, 666*59c7cf81SVinod Koul <0 0x01d87a00 0 0x1e0>; 667*59c7cf81SVinod Koul #phy-cells = <0>; 668*59c7cf81SVinod Koul #clock-cells = <0>; 669*59c7cf81SVinod Koul }; 670*59c7cf81SVinod Koul }; 671*59c7cf81SVinod Koul 672e780fb31SJack Pham usb_1_hsphy: phy@88e3000 { 673e780fb31SJack Pham compatible = "qcom,sm8350-usb-hs-phy", 674e780fb31SJack Pham "qcom,usb-snps-hs-7nm-phy"; 675e780fb31SJack Pham reg = <0 0x088e3000 0 0x400>; 676e780fb31SJack Pham status = "disabled"; 677e780fb31SJack Pham #phy-cells = <0>; 678e780fb31SJack Pham 679e780fb31SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 680e780fb31SJack Pham clock-names = "ref"; 681e780fb31SJack Pham 682e780fb31SJack Pham resets = <&gcc 20>; 683e780fb31SJack Pham }; 684e780fb31SJack Pham 685e780fb31SJack Pham usb_2_hsphy: phy@88e4000 { 686e780fb31SJack Pham compatible = "qcom,sm8250-usb-hs-phy", 687e780fb31SJack Pham "qcom,usb-snps-hs-7nm-phy"; 688e780fb31SJack Pham reg = <0 0x088e4000 0 0x400>; 689e780fb31SJack Pham status = "disabled"; 690e780fb31SJack Pham #phy-cells = <0>; 691e780fb31SJack Pham 692e780fb31SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 693e780fb31SJack Pham clock-names = "ref"; 694e780fb31SJack Pham 695e780fb31SJack Pham resets = <&gcc 21>; 696e780fb31SJack Pham }; 697e780fb31SJack Pham 698e780fb31SJack Pham usb_1_qmpphy: phy-wrapper@88e9000 { 699e780fb31SJack Pham compatible = "qcom,sm8350-qmp-usb3-phy"; 700e780fb31SJack Pham reg = <0 0x088e9000 0 0x200>, 701e780fb31SJack Pham <0 0x088e8000 0 0x20>; 702e780fb31SJack Pham reg-names = "reg-base", "dp_com"; 703e780fb31SJack Pham status = "disabled"; 704e780fb31SJack Pham #clock-cells = <1>; 705e780fb31SJack Pham #address-cells = <2>; 706e780fb31SJack Pham #size-cells = <2>; 707e780fb31SJack Pham ranges; 708e780fb31SJack Pham 709e780fb31SJack Pham clocks = <&gcc 187>, 710e780fb31SJack Pham <&rpmhcc RPMH_CXO_CLK>, 711e780fb31SJack Pham <&gcc 189>; 712e780fb31SJack Pham clock-names = "aux", "ref_clk_src", "com_aux"; 713e780fb31SJack Pham 714e780fb31SJack Pham resets = <&gcc 28>, 715e780fb31SJack Pham <&gcc 30>; 716e780fb31SJack Pham reset-names = "phy", "common"; 717e780fb31SJack Pham 718e780fb31SJack Pham usb_1_ssphy: phy@88e9200 { 719e780fb31SJack Pham reg = <0 0x088e9200 0 0x200>, 720e780fb31SJack Pham <0 0x088e9400 0 0x200>, 721e780fb31SJack Pham <0 0x088e9c00 0 0x400>, 722e780fb31SJack Pham <0 0x088e9600 0 0x200>, 723e780fb31SJack Pham <0 0x088e9800 0 0x200>, 724e780fb31SJack Pham <0 0x088e9a00 0 0x100>; 725e780fb31SJack Pham #phy-cells = <0>; 726e780fb31SJack Pham #clock-cells = <1>; 727e780fb31SJack Pham clocks = <&gcc 190>; 728e780fb31SJack Pham clock-names = "pipe0"; 729e780fb31SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 730e780fb31SJack Pham }; 731e780fb31SJack Pham }; 732e780fb31SJack Pham 733e780fb31SJack Pham usb_2_qmpphy: phy-wrapper@88eb000 { 734e780fb31SJack Pham compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 735e780fb31SJack Pham reg = <0 0x088eb000 0 0x200>; 736e780fb31SJack Pham status = "disabled"; 737e780fb31SJack Pham #clock-cells = <1>; 738e780fb31SJack Pham #address-cells = <2>; 739e780fb31SJack Pham #size-cells = <2>; 740e780fb31SJack Pham ranges; 741e780fb31SJack Pham 742e780fb31SJack Pham clocks = <&gcc 193>, 743e780fb31SJack Pham <&rpmhcc RPMH_CXO_CLK>, 744e780fb31SJack Pham <&gcc 192>, 745e780fb31SJack Pham <&gcc 195>; 746e780fb31SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 747e780fb31SJack Pham 748e780fb31SJack Pham resets = <&gcc 33>, 749e780fb31SJack Pham <&gcc 31>; 750e780fb31SJack Pham reset-names = "phy", "common"; 751e780fb31SJack Pham 752e780fb31SJack Pham usb_2_ssphy: phy@88ebe00 { 753e780fb31SJack Pham reg = <0 0x088ebe00 0 0x200>, 754e780fb31SJack Pham <0 0x088ec000 0 0x200>, 755e780fb31SJack Pham <0 0x088eb200 0 0x1100>; 756e780fb31SJack Pham #phy-cells = <0>; 757e780fb31SJack Pham #clock-cells = <1>; 758e780fb31SJack Pham clocks = <&gcc 196>; 759e780fb31SJack Pham clock-names = "pipe0"; 760e780fb31SJack Pham clock-output-names = "usb3_uni_phy_pipe_clk_src"; 761e780fb31SJack Pham }; 762e780fb31SJack Pham }; 763e780fb31SJack Pham 764e780fb31SJack Pham usb_1: usb@a6f8800 { 765e780fb31SJack Pham compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 766e780fb31SJack Pham reg = <0 0x0a6f8800 0 0x400>; 767e780fb31SJack Pham status = "disabled"; 768e780fb31SJack Pham #address-cells = <2>; 769e780fb31SJack Pham #size-cells = <2>; 770e780fb31SJack Pham ranges; 771e780fb31SJack Pham 772e780fb31SJack Pham clocks = <&gcc 23>, 773e780fb31SJack Pham <&gcc 173>, 774e780fb31SJack Pham <&gcc 18>, 775e780fb31SJack Pham <&gcc 176>, 776e780fb31SJack Pham <&gcc 179>; 777e780fb31SJack Pham clock-names = "cfg_noc", "core", "iface", "mock_utmi", 778e780fb31SJack Pham "sleep"; 779e780fb31SJack Pham 780e780fb31SJack Pham assigned-clocks = <&gcc 176>, 781e780fb31SJack Pham <&gcc 173>; 782e780fb31SJack Pham assigned-clock-rates = <19200000>, <200000000>; 783e780fb31SJack Pham 784e780fb31SJack Pham interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 785e780fb31SJack Pham <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 786e780fb31SJack Pham <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 787e780fb31SJack Pham <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 788e780fb31SJack Pham interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 789e780fb31SJack Pham "dm_hs_phy_irq", "ss_phy_irq"; 790e780fb31SJack Pham 791e780fb31SJack Pham power-domains = <&gcc 4>; 792e780fb31SJack Pham 793e780fb31SJack Pham resets = <&gcc 26>; 794e780fb31SJack Pham 795e780fb31SJack Pham usb_1_dwc3: dwc3@a600000 { 796e780fb31SJack Pham compatible = "snps,dwc3"; 797e780fb31SJack Pham reg = <0 0x0a600000 0 0xcd00>; 798e780fb31SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 799e780fb31SJack Pham iommus = <&apps_smmu 0x0 0x0>; 800e780fb31SJack Pham snps,dis_u2_susphy_quirk; 801e780fb31SJack Pham snps,dis_enblslpm_quirk; 802e780fb31SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 803e780fb31SJack Pham phy-names = "usb2-phy", "usb3-phy"; 804e780fb31SJack Pham }; 805e780fb31SJack Pham }; 806e780fb31SJack Pham 807e780fb31SJack Pham usb_2: usb@a8f8800 { 808e780fb31SJack Pham compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 809e780fb31SJack Pham reg = <0 0x0a8f8800 0 0x400>; 810e780fb31SJack Pham status = "disabled"; 811e780fb31SJack Pham #address-cells = <2>; 812e780fb31SJack Pham #size-cells = <2>; 813e780fb31SJack Pham ranges; 814e780fb31SJack Pham 815e780fb31SJack Pham clocks = <&gcc 24>, 816e780fb31SJack Pham <&gcc 180>, 817e780fb31SJack Pham <&gcc 19>, 818e780fb31SJack Pham <&gcc 183>, 819e780fb31SJack Pham <&gcc 186>, 820e780fb31SJack Pham <&gcc 192>; 821e780fb31SJack Pham clock-names = "cfg_noc", "core", "iface", "mock_utmi", 822e780fb31SJack Pham "sleep", "xo"; 823e780fb31SJack Pham 824e780fb31SJack Pham assigned-clocks = <&gcc 183>, 825e780fb31SJack Pham <&gcc 180>; 826e780fb31SJack Pham assigned-clock-rates = <19200000>, <200000000>; 827e780fb31SJack Pham 828e780fb31SJack Pham interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 829e780fb31SJack Pham <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 830e780fb31SJack Pham <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 831e780fb31SJack Pham <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 832e780fb31SJack Pham interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 833e780fb31SJack Pham "dm_hs_phy_irq", "ss_phy_irq"; 834e780fb31SJack Pham 835e780fb31SJack Pham power-domains = <&gcc 5>; 836e780fb31SJack Pham 837e780fb31SJack Pham resets = <&gcc 27>; 838e780fb31SJack Pham 839e780fb31SJack Pham usb_2_dwc3: dwc3@a800000 { 840e780fb31SJack Pham compatible = "snps,dwc3"; 841e780fb31SJack Pham reg = <0 0x0a800000 0 0xcd00>; 842e780fb31SJack Pham interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 843e780fb31SJack Pham iommus = <&apps_smmu 0x20 0x0>; 844e780fb31SJack Pham snps,dis_u2_susphy_quirk; 845e780fb31SJack Pham snps,dis_enblslpm_quirk; 846e780fb31SJack Pham phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 847e780fb31SJack Pham phy-names = "usb2-phy", "usb3-phy"; 848e780fb31SJack Pham }; 849e780fb31SJack Pham }; 850b7e8f433SVinod Koul }; 851b7e8f433SVinod Koul 852b7e8f433SVinod Koul timer { 853b7e8f433SVinod Koul compatible = "arm,armv8-timer"; 854b7e8f433SVinod Koul interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 855b7e8f433SVinod Koul <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 856b7e8f433SVinod Koul <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 857b7e8f433SVinod Koul <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 858b7e8f433SVinod Koul }; 859b7e8f433SVinod Koul}; 860