1b7e8f433SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2b7e8f433SVinod Koul/* 34f23d2a5SVinod Koul * Copyright (c) 2020, Linaro Limited 4b7e8f433SVinod Koul */ 5b7e8f433SVinod Koul 6d4a44105SRobert Foss#include <dt-bindings/interconnect/qcom,sm8350.h> 7b7e8f433SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 89fd4887cSRobert Foss#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 96d91e201SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8350.h> 1054af0cebSDmitry Baryshkov#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11b7e8f433SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 12bc08fbf4SBjorn Andersson#include <dt-bindings/dma/qcom-gpi.h> 13f0360a7cSKonrad Dybcio#include <dt-bindings/gpio/gpio.h> 1484c856d0SVinod Koul#include <dt-bindings/interconnect/qcom,sm8350.h> 15b7e8f433SVinod Koul#include <dt-bindings/mailbox/qcom-ipcc.h> 162458a305SNeil Armstrong#include <dt-bindings/phy/phy-qcom-qmp.h> 17b7e8f433SVinod Koul#include <dt-bindings/power/qcom-rpmpd.h> 18b7e8f433SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 1920f9d94eSRobert Foss#include <dt-bindings/thermal/thermal.h> 20f11d3e7dSAlex Elder#include <dt-bindings/interconnect/qcom,sm8350.h> 21b7e8f433SVinod Koul 22b7e8f433SVinod Koul/ { 23b7e8f433SVinod Koul interrupt-parent = <&intc>; 24b7e8f433SVinod Koul 25b7e8f433SVinod Koul #address-cells = <2>; 26b7e8f433SVinod Koul #size-cells = <2>; 27b7e8f433SVinod Koul 28b7e8f433SVinod Koul chosen { }; 29b7e8f433SVinod Koul 30b7e8f433SVinod Koul clocks { 31b7e8f433SVinod Koul xo_board: xo-board { 32b7e8f433SVinod Koul compatible = "fixed-clock"; 33b7e8f433SVinod Koul #clock-cells = <0>; 34b7e8f433SVinod Koul clock-frequency = <38400000>; 35b7e8f433SVinod Koul clock-output-names = "xo_board"; 36b7e8f433SVinod Koul }; 37b7e8f433SVinod Koul 38b7e8f433SVinod Koul sleep_clk: sleep-clk { 39b7e8f433SVinod Koul compatible = "fixed-clock"; 40b7e8f433SVinod Koul clock-frequency = <32000>; 41b7e8f433SVinod Koul #clock-cells = <0>; 42b7e8f433SVinod Koul }; 43b7e8f433SVinod Koul }; 44b7e8f433SVinod Koul 45b7e8f433SVinod Koul cpus { 46b7e8f433SVinod Koul #address-cells = <2>; 47b7e8f433SVinod Koul #size-cells = <0>; 48b7e8f433SVinod Koul 49b7e8f433SVinod Koul CPU0: cpu@0 { 50b7e8f433SVinod Koul device_type = "cpu"; 51*4390730cSKonrad Dybcio compatible = "arm,cortex-a55"; 52b7e8f433SVinod Koul reg = <0x0 0x0>; 53c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 54b7e8f433SVinod Koul enable-method = "psci"; 55b7e8f433SVinod Koul next-level-cache = <&L2_0>; 56ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 5707ddb302SBjorn Andersson power-domains = <&CPU_PD0>; 5807ddb302SBjorn Andersson power-domain-names = "psci"; 5920f9d94eSRobert Foss #cooling-cells = <2>; 60b7e8f433SVinod Koul L2_0: l2-cache { 61b7e8f433SVinod Koul compatible = "cache"; 629435294cSPierre Gondois cache-level = <2>; 639c6e72fbSKrzysztof Kozlowski cache-unified; 64b7e8f433SVinod Koul next-level-cache = <&L3_0>; 65b7e8f433SVinod Koul L3_0: l3-cache { 66b7e8f433SVinod Koul compatible = "cache"; 679435294cSPierre Gondois cache-level = <3>; 689c6e72fbSKrzysztof Kozlowski cache-unified; 69b7e8f433SVinod Koul }; 70b7e8f433SVinod Koul }; 71b7e8f433SVinod Koul }; 72b7e8f433SVinod Koul 73b7e8f433SVinod Koul CPU1: cpu@100 { 74b7e8f433SVinod Koul device_type = "cpu"; 75*4390730cSKonrad Dybcio compatible = "arm,cortex-a55"; 76b7e8f433SVinod Koul reg = <0x0 0x100>; 77c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 78b7e8f433SVinod Koul enable-method = "psci"; 79b7e8f433SVinod Koul next-level-cache = <&L2_100>; 80ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 8107ddb302SBjorn Andersson power-domains = <&CPU_PD1>; 8207ddb302SBjorn Andersson power-domain-names = "psci"; 8320f9d94eSRobert Foss #cooling-cells = <2>; 84b7e8f433SVinod Koul L2_100: l2-cache { 85b7e8f433SVinod Koul compatible = "cache"; 869435294cSPierre Gondois cache-level = <2>; 879c6e72fbSKrzysztof Kozlowski cache-unified; 88b7e8f433SVinod Koul next-level-cache = <&L3_0>; 89b7e8f433SVinod Koul }; 90b7e8f433SVinod Koul }; 91b7e8f433SVinod Koul 92b7e8f433SVinod Koul CPU2: cpu@200 { 93b7e8f433SVinod Koul device_type = "cpu"; 94*4390730cSKonrad Dybcio compatible = "arm,cortex-a55"; 95b7e8f433SVinod Koul reg = <0x0 0x200>; 96c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 97b7e8f433SVinod Koul enable-method = "psci"; 98b7e8f433SVinod Koul next-level-cache = <&L2_200>; 99ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 10007ddb302SBjorn Andersson power-domains = <&CPU_PD2>; 10107ddb302SBjorn Andersson power-domain-names = "psci"; 10220f9d94eSRobert Foss #cooling-cells = <2>; 103b7e8f433SVinod Koul L2_200: l2-cache { 104b7e8f433SVinod Koul compatible = "cache"; 1059435294cSPierre Gondois cache-level = <2>; 1069c6e72fbSKrzysztof Kozlowski cache-unified; 107b7e8f433SVinod Koul next-level-cache = <&L3_0>; 108b7e8f433SVinod Koul }; 109b7e8f433SVinod Koul }; 110b7e8f433SVinod Koul 111b7e8f433SVinod Koul CPU3: cpu@300 { 112b7e8f433SVinod Koul device_type = "cpu"; 113*4390730cSKonrad Dybcio compatible = "arm,cortex-a55"; 114b7e8f433SVinod Koul reg = <0x0 0x300>; 115c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 116b7e8f433SVinod Koul enable-method = "psci"; 117b7e8f433SVinod Koul next-level-cache = <&L2_300>; 118ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 0>; 11907ddb302SBjorn Andersson power-domains = <&CPU_PD3>; 12007ddb302SBjorn Andersson power-domain-names = "psci"; 12120f9d94eSRobert Foss #cooling-cells = <2>; 122b7e8f433SVinod Koul L2_300: l2-cache { 123b7e8f433SVinod Koul compatible = "cache"; 1249435294cSPierre Gondois cache-level = <2>; 1259c6e72fbSKrzysztof Kozlowski cache-unified; 126b7e8f433SVinod Koul next-level-cache = <&L3_0>; 127b7e8f433SVinod Koul }; 128b7e8f433SVinod Koul }; 129b7e8f433SVinod Koul 130b7e8f433SVinod Koul CPU4: cpu@400 { 131b7e8f433SVinod Koul device_type = "cpu"; 132*4390730cSKonrad Dybcio compatible = "arm,cortex-a78"; 133b7e8f433SVinod Koul reg = <0x0 0x400>; 134c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 135b7e8f433SVinod Koul enable-method = "psci"; 136b7e8f433SVinod Koul next-level-cache = <&L2_400>; 137ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 1>; 13807ddb302SBjorn Andersson power-domains = <&CPU_PD4>; 13907ddb302SBjorn Andersson power-domain-names = "psci"; 14020f9d94eSRobert Foss #cooling-cells = <2>; 141b7e8f433SVinod Koul L2_400: l2-cache { 142b7e8f433SVinod Koul compatible = "cache"; 1439435294cSPierre Gondois cache-level = <2>; 1449c6e72fbSKrzysztof Kozlowski cache-unified; 145b7e8f433SVinod Koul next-level-cache = <&L3_0>; 146b7e8f433SVinod Koul }; 147b7e8f433SVinod Koul }; 148b7e8f433SVinod Koul 149b7e8f433SVinod Koul CPU5: cpu@500 { 150b7e8f433SVinod Koul device_type = "cpu"; 151*4390730cSKonrad Dybcio compatible = "arm,cortex-a78"; 152b7e8f433SVinod Koul reg = <0x0 0x500>; 153c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 154b7e8f433SVinod Koul enable-method = "psci"; 155b7e8f433SVinod Koul next-level-cache = <&L2_500>; 156ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 1>; 15707ddb302SBjorn Andersson power-domains = <&CPU_PD5>; 15807ddb302SBjorn Andersson power-domain-names = "psci"; 15920f9d94eSRobert Foss #cooling-cells = <2>; 160b7e8f433SVinod Koul L2_500: l2-cache { 161b7e8f433SVinod Koul compatible = "cache"; 1629435294cSPierre Gondois cache-level = <2>; 1639c6e72fbSKrzysztof Kozlowski cache-unified; 164b7e8f433SVinod Koul next-level-cache = <&L3_0>; 165b7e8f433SVinod Koul }; 166b7e8f433SVinod Koul }; 167b7e8f433SVinod Koul 168b7e8f433SVinod Koul CPU6: cpu@600 { 169b7e8f433SVinod Koul device_type = "cpu"; 170*4390730cSKonrad Dybcio compatible = "arm,cortex-a78"; 171b7e8f433SVinod Koul reg = <0x0 0x600>; 172c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 173b7e8f433SVinod Koul enable-method = "psci"; 174b7e8f433SVinod Koul next-level-cache = <&L2_600>; 175ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 1>; 17607ddb302SBjorn Andersson power-domains = <&CPU_PD6>; 17707ddb302SBjorn Andersson power-domain-names = "psci"; 17820f9d94eSRobert Foss #cooling-cells = <2>; 179b7e8f433SVinod Koul L2_600: l2-cache { 180b7e8f433SVinod Koul compatible = "cache"; 1819435294cSPierre Gondois cache-level = <2>; 1829c6e72fbSKrzysztof Kozlowski cache-unified; 183b7e8f433SVinod Koul next-level-cache = <&L3_0>; 184b7e8f433SVinod Koul }; 185b7e8f433SVinod Koul }; 186b7e8f433SVinod Koul 187b7e8f433SVinod Koul CPU7: cpu@700 { 188b7e8f433SVinod Koul device_type = "cpu"; 189*4390730cSKonrad Dybcio compatible = "arm,cortex-x1"; 190b7e8f433SVinod Koul reg = <0x0 0x700>; 191c2a18730SManivannan Sadhasivam clocks = <&cpufreq_hw 2>; 192b7e8f433SVinod Koul enable-method = "psci"; 193b7e8f433SVinod Koul next-level-cache = <&L2_700>; 194ccbb3abbSVinod Koul qcom,freq-domain = <&cpufreq_hw 2>; 19507ddb302SBjorn Andersson power-domains = <&CPU_PD7>; 19607ddb302SBjorn Andersson power-domain-names = "psci"; 19720f9d94eSRobert Foss #cooling-cells = <2>; 198b7e8f433SVinod Koul L2_700: l2-cache { 199b7e8f433SVinod Koul compatible = "cache"; 2009435294cSPierre Gondois cache-level = <2>; 2019c6e72fbSKrzysztof Kozlowski cache-unified; 202b7e8f433SVinod Koul next-level-cache = <&L3_0>; 203b7e8f433SVinod Koul }; 204b7e8f433SVinod Koul }; 20507ddb302SBjorn Andersson 20607ddb302SBjorn Andersson cpu-map { 20707ddb302SBjorn Andersson cluster0 { 20807ddb302SBjorn Andersson core0 { 20907ddb302SBjorn Andersson cpu = <&CPU0>; 21007ddb302SBjorn Andersson }; 21107ddb302SBjorn Andersson 21207ddb302SBjorn Andersson core1 { 21307ddb302SBjorn Andersson cpu = <&CPU1>; 21407ddb302SBjorn Andersson }; 21507ddb302SBjorn Andersson 21607ddb302SBjorn Andersson core2 { 21707ddb302SBjorn Andersson cpu = <&CPU2>; 21807ddb302SBjorn Andersson }; 21907ddb302SBjorn Andersson 22007ddb302SBjorn Andersson core3 { 22107ddb302SBjorn Andersson cpu = <&CPU3>; 22207ddb302SBjorn Andersson }; 22307ddb302SBjorn Andersson 22407ddb302SBjorn Andersson core4 { 22507ddb302SBjorn Andersson cpu = <&CPU4>; 22607ddb302SBjorn Andersson }; 22707ddb302SBjorn Andersson 22807ddb302SBjorn Andersson core5 { 22907ddb302SBjorn Andersson cpu = <&CPU5>; 23007ddb302SBjorn Andersson }; 23107ddb302SBjorn Andersson 23207ddb302SBjorn Andersson core6 { 23307ddb302SBjorn Andersson cpu = <&CPU6>; 23407ddb302SBjorn Andersson }; 23507ddb302SBjorn Andersson 23607ddb302SBjorn Andersson core7 { 23707ddb302SBjorn Andersson cpu = <&CPU7>; 23807ddb302SBjorn Andersson }; 23907ddb302SBjorn Andersson }; 24007ddb302SBjorn Andersson }; 24107ddb302SBjorn Andersson 24207ddb302SBjorn Andersson idle-states { 24307ddb302SBjorn Andersson entry-method = "psci"; 24407ddb302SBjorn Andersson 24507ddb302SBjorn Andersson LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 24607ddb302SBjorn Andersson compatible = "arm,idle-state"; 24707ddb302SBjorn Andersson idle-state-name = "silver-rail-power-collapse"; 24807ddb302SBjorn Andersson arm,psci-suspend-param = <0x40000004>; 24991ce3693SKonrad Dybcio entry-latency-us = <360>; 25091ce3693SKonrad Dybcio exit-latency-us = <531>; 25107ddb302SBjorn Andersson min-residency-us = <3934>; 25207ddb302SBjorn Andersson local-timer-stop; 25307ddb302SBjorn Andersson }; 25407ddb302SBjorn Andersson 25507ddb302SBjorn Andersson BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 25607ddb302SBjorn Andersson compatible = "arm,idle-state"; 25707ddb302SBjorn Andersson idle-state-name = "gold-rail-power-collapse"; 25807ddb302SBjorn Andersson arm,psci-suspend-param = <0x40000004>; 25991ce3693SKonrad Dybcio entry-latency-us = <702>; 26091ce3693SKonrad Dybcio exit-latency-us = <1061>; 26107ddb302SBjorn Andersson min-residency-us = <4488>; 26207ddb302SBjorn Andersson local-timer-stop; 26307ddb302SBjorn Andersson }; 26407ddb302SBjorn Andersson }; 26507ddb302SBjorn Andersson 26607ddb302SBjorn Andersson domain-idle-states { 26729a687c2SKonrad Dybcio CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 26829a687c2SKonrad Dybcio compatible = "domain-idle-state"; 26929a687c2SKonrad Dybcio arm,psci-suspend-param = <0x41000044>; 27029a687c2SKonrad Dybcio entry-latency-us = <2752>; 27129a687c2SKonrad Dybcio exit-latency-us = <3048>; 27229a687c2SKonrad Dybcio min-residency-us = <6118>; 27329a687c2SKonrad Dybcio }; 27429a687c2SKonrad Dybcio 27529a687c2SKonrad Dybcio CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 27607ddb302SBjorn Andersson compatible = "domain-idle-state"; 27707ddb302SBjorn Andersson arm,psci-suspend-param = <0x4100c344>; 27807ddb302SBjorn Andersson entry-latency-us = <3263>; 27907ddb302SBjorn Andersson exit-latency-us = <6562>; 28007ddb302SBjorn Andersson min-residency-us = <9987>; 28107ddb302SBjorn Andersson }; 28207ddb302SBjorn Andersson }; 283b7e8f433SVinod Koul }; 284b7e8f433SVinod Koul 285b7e8f433SVinod Koul firmware { 286b7e8f433SVinod Koul scm: scm { 287b7e8f433SVinod Koul compatible = "qcom,scm-sm8350", "qcom,scm"; 288b7e8f433SVinod Koul #reset-cells = <1>; 289b7e8f433SVinod Koul }; 290b7e8f433SVinod Koul }; 291b7e8f433SVinod Koul 292b7e8f433SVinod Koul memory@80000000 { 293b7e8f433SVinod Koul device_type = "memory"; 294b7e8f433SVinod Koul /* We expect the bootloader to fill in the size */ 295b7e8f433SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 296b7e8f433SVinod Koul }; 297b7e8f433SVinod Koul 298b7e8f433SVinod Koul pmu { 299b7e8f433SVinod Koul compatible = "arm,armv8-pmuv3"; 300794d3e30SSai Prakash Ranjan interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 301b7e8f433SVinod Koul }; 302b7e8f433SVinod Koul 303b7e8f433SVinod Koul psci { 304b7e8f433SVinod Koul compatible = "arm,psci-1.0"; 305b7e8f433SVinod Koul method = "smc"; 30607ddb302SBjorn Andersson 307a9371962SKrzysztof Kozlowski CPU_PD0: power-domain-cpu0 { 30807ddb302SBjorn Andersson #power-domain-cells = <0>; 30907ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 31007ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 31107ddb302SBjorn Andersson }; 31207ddb302SBjorn Andersson 313a9371962SKrzysztof Kozlowski CPU_PD1: power-domain-cpu1 { 31407ddb302SBjorn Andersson #power-domain-cells = <0>; 31507ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 31607ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 31707ddb302SBjorn Andersson }; 31807ddb302SBjorn Andersson 319a9371962SKrzysztof Kozlowski CPU_PD2: power-domain-cpu2 { 32007ddb302SBjorn Andersson #power-domain-cells = <0>; 32107ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 32207ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 32307ddb302SBjorn Andersson }; 32407ddb302SBjorn Andersson 325a9371962SKrzysztof Kozlowski CPU_PD3: power-domain-cpu3 { 32607ddb302SBjorn Andersson #power-domain-cells = <0>; 32707ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 32807ddb302SBjorn Andersson domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 32907ddb302SBjorn Andersson }; 33007ddb302SBjorn Andersson 331a9371962SKrzysztof Kozlowski CPU_PD4: power-domain-cpu4 { 33207ddb302SBjorn Andersson #power-domain-cells = <0>; 33307ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 33407ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 33507ddb302SBjorn Andersson }; 33607ddb302SBjorn Andersson 337a9371962SKrzysztof Kozlowski CPU_PD5: power-domain-cpu5 { 33807ddb302SBjorn Andersson #power-domain-cells = <0>; 33907ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 34007ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 34107ddb302SBjorn Andersson }; 34207ddb302SBjorn Andersson 343a9371962SKrzysztof Kozlowski CPU_PD6: power-domain-cpu6 { 34407ddb302SBjorn Andersson #power-domain-cells = <0>; 34507ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 34607ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 34707ddb302SBjorn Andersson }; 34807ddb302SBjorn Andersson 349a9371962SKrzysztof Kozlowski CPU_PD7: power-domain-cpu7 { 35007ddb302SBjorn Andersson #power-domain-cells = <0>; 35107ddb302SBjorn Andersson power-domains = <&CLUSTER_PD>; 35207ddb302SBjorn Andersson domain-idle-states = <&BIG_CPU_SLEEP_0>; 35307ddb302SBjorn Andersson }; 35407ddb302SBjorn Andersson 355a9371962SKrzysztof Kozlowski CLUSTER_PD: power-domain-cpu-cluster0 { 35607ddb302SBjorn Andersson #power-domain-cells = <0>; 35729a687c2SKonrad Dybcio domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 35807ddb302SBjorn Andersson }; 359b7e8f433SVinod Koul }; 360b7e8f433SVinod Koul 361e2eedde4SVinod Koul qup_opp_table_100mhz: opp-table-qup100mhz { 362e2eedde4SVinod Koul compatible = "operating-points-v2"; 363e2eedde4SVinod Koul 364e2eedde4SVinod Koul opp-50000000 { 365e2eedde4SVinod Koul opp-hz = /bits/ 64 <50000000>; 366e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_min_svs>; 367e2eedde4SVinod Koul }; 368e2eedde4SVinod Koul 369e2eedde4SVinod Koul opp-75000000 { 370e2eedde4SVinod Koul opp-hz = /bits/ 64 <75000000>; 371e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_low_svs>; 372e2eedde4SVinod Koul }; 373e2eedde4SVinod Koul 374e2eedde4SVinod Koul opp-100000000 { 375e2eedde4SVinod Koul opp-hz = /bits/ 64 <100000000>; 376e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_svs>; 377e2eedde4SVinod Koul }; 378e2eedde4SVinod Koul }; 379e2eedde4SVinod Koul 380e2eedde4SVinod Koul qup_opp_table_120mhz: opp-table-qup120mhz { 381e2eedde4SVinod Koul compatible = "operating-points-v2"; 382e2eedde4SVinod Koul 383e2eedde4SVinod Koul opp-50000000 { 384e2eedde4SVinod Koul opp-hz = /bits/ 64 <50000000>; 385e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_min_svs>; 386e2eedde4SVinod Koul }; 387e2eedde4SVinod Koul 388e2eedde4SVinod Koul opp-75000000 { 389e2eedde4SVinod Koul opp-hz = /bits/ 64 <75000000>; 390e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_low_svs>; 391e2eedde4SVinod Koul }; 392e2eedde4SVinod Koul 393e2eedde4SVinod Koul opp-120000000 { 394e2eedde4SVinod Koul opp-hz = /bits/ 64 <120000000>; 395e2eedde4SVinod Koul required-opps = <&rpmhpd_opp_svs>; 396e2eedde4SVinod Koul }; 397e2eedde4SVinod Koul }; 398e2eedde4SVinod Koul 399b7e8f433SVinod Koul reserved_memory: reserved-memory { 400b7e8f433SVinod Koul #address-cells = <2>; 401b7e8f433SVinod Koul #size-cells = <2>; 402b7e8f433SVinod Koul ranges; 403b7e8f433SVinod Koul 404b7e8f433SVinod Koul hyp_mem: memory@80000000 { 405b7e8f433SVinod Koul reg = <0x0 0x80000000 0x0 0x600000>; 406b7e8f433SVinod Koul no-map; 407b7e8f433SVinod Koul }; 408b7e8f433SVinod Koul 409b7e8f433SVinod Koul xbl_aop_mem: memory@80700000 { 410b7e8f433SVinod Koul no-map; 411b7e8f433SVinod Koul reg = <0x0 0x80700000 0x0 0x160000>; 412b7e8f433SVinod Koul }; 413b7e8f433SVinod Koul 414b7e8f433SVinod Koul cmd_db: memory@80860000 { 415b7e8f433SVinod Koul compatible = "qcom,cmd-db"; 416b7e8f433SVinod Koul reg = <0x0 0x80860000 0x0 0x20000>; 417b7e8f433SVinod Koul no-map; 418b7e8f433SVinod Koul }; 419b7e8f433SVinod Koul 420b7e8f433SVinod Koul reserved_xbl_uefi_log: memory@80880000 { 421b7e8f433SVinod Koul reg = <0x0 0x80880000 0x0 0x14000>; 422b7e8f433SVinod Koul no-map; 423b7e8f433SVinod Koul }; 424b7e8f433SVinod Koul 4258503babcSKonrad Dybcio smem@80900000 { 4268503babcSKonrad Dybcio compatible = "qcom,smem"; 427b7e8f433SVinod Koul reg = <0x0 0x80900000 0x0 0x200000>; 4288503babcSKonrad Dybcio hwlocks = <&tcsr_mutex 3>; 429b7e8f433SVinod Koul no-map; 430b7e8f433SVinod Koul }; 431b7e8f433SVinod Koul 432b7e8f433SVinod Koul cpucp_fw_mem: memory@80b00000 { 433b7e8f433SVinod Koul reg = <0x0 0x80b00000 0x0 0x100000>; 434b7e8f433SVinod Koul no-map; 435b7e8f433SVinod Koul }; 436b7e8f433SVinod Koul 437b7e8f433SVinod Koul cdsp_secure_heap: memory@80c00000 { 438b7e8f433SVinod Koul reg = <0x0 0x80c00000 0x0 0x4600000>; 439b7e8f433SVinod Koul no-map; 440b7e8f433SVinod Koul }; 441b7e8f433SVinod Koul 442b7e8f433SVinod Koul pil_camera_mem: mmeory@85200000 { 443b7e8f433SVinod Koul reg = <0x0 0x85200000 0x0 0x500000>; 444b7e8f433SVinod Koul no-map; 445b7e8f433SVinod Koul }; 446b7e8f433SVinod Koul 447b7e8f433SVinod Koul pil_video_mem: memory@85700000 { 448b7e8f433SVinod Koul reg = <0x0 0x85700000 0x0 0x500000>; 449b7e8f433SVinod Koul no-map; 450b7e8f433SVinod Koul }; 451b7e8f433SVinod Koul 452b7e8f433SVinod Koul pil_cvp_mem: memory@85c00000 { 453b7e8f433SVinod Koul reg = <0x0 0x85c00000 0x0 0x500000>; 454b7e8f433SVinod Koul no-map; 455b7e8f433SVinod Koul }; 456b7e8f433SVinod Koul 457b7e8f433SVinod Koul pil_adsp_mem: memory@86100000 { 458b7e8f433SVinod Koul reg = <0x0 0x86100000 0x0 0x2100000>; 459b7e8f433SVinod Koul no-map; 460b7e8f433SVinod Koul }; 461b7e8f433SVinod Koul 462b7e8f433SVinod Koul pil_slpi_mem: memory@88200000 { 463b7e8f433SVinod Koul reg = <0x0 0x88200000 0x0 0x1500000>; 464b7e8f433SVinod Koul no-map; 465b7e8f433SVinod Koul }; 466b7e8f433SVinod Koul 467b7e8f433SVinod Koul pil_cdsp_mem: memory@89700000 { 468b7e8f433SVinod Koul reg = <0x0 0x89700000 0x0 0x1e00000>; 469b7e8f433SVinod Koul no-map; 470b7e8f433SVinod Koul }; 471b7e8f433SVinod Koul 472b7e8f433SVinod Koul pil_ipa_fw_mem: memory@8b500000 { 473b7e8f433SVinod Koul reg = <0x0 0x8b500000 0x0 0x10000>; 474b7e8f433SVinod Koul no-map; 475b7e8f433SVinod Koul }; 476b7e8f433SVinod Koul 477b7e8f433SVinod Koul pil_ipa_gsi_mem: memory@8b510000 { 478b7e8f433SVinod Koul reg = <0x0 0x8b510000 0x0 0xa000>; 479b7e8f433SVinod Koul no-map; 480b7e8f433SVinod Koul }; 481b7e8f433SVinod Koul 482b7e8f433SVinod Koul pil_gpu_mem: memory@8b51a000 { 483b7e8f433SVinod Koul reg = <0x0 0x8b51a000 0x0 0x2000>; 484b7e8f433SVinod Koul no-map; 485b7e8f433SVinod Koul }; 486b7e8f433SVinod Koul 487b7e8f433SVinod Koul pil_spss_mem: memory@8b600000 { 488b7e8f433SVinod Koul reg = <0x0 0x8b600000 0x0 0x100000>; 489b7e8f433SVinod Koul no-map; 490b7e8f433SVinod Koul }; 491b7e8f433SVinod Koul 492b7e8f433SVinod Koul pil_modem_mem: memory@8b800000 { 493b7e8f433SVinod Koul reg = <0x0 0x8b800000 0x0 0x10000000>; 494b7e8f433SVinod Koul no-map; 495b7e8f433SVinod Koul }; 496b7e8f433SVinod Koul 497774890c9SVinod Koul rmtfs_mem: memory@9b800000 { 498774890c9SVinod Koul compatible = "qcom,rmtfs-mem"; 499774890c9SVinod Koul reg = <0x0 0x9b800000 0x0 0x280000>; 500774890c9SVinod Koul no-map; 501774890c9SVinod Koul 502774890c9SVinod Koul qcom,client-id = <1>; 503774890c9SVinod Koul qcom,vmid = <15>; 504774890c9SVinod Koul }; 505774890c9SVinod Koul 506b7e8f433SVinod Koul hyp_reserved_mem: memory@d0000000 { 507b7e8f433SVinod Koul reg = <0x0 0xd0000000 0x0 0x800000>; 508b7e8f433SVinod Koul no-map; 509b7e8f433SVinod Koul }; 510b7e8f433SVinod Koul 511b7e8f433SVinod Koul pil_trustedvm_mem: memory@d0800000 { 512b7e8f433SVinod Koul reg = <0x0 0xd0800000 0x0 0x76f7000>; 513b7e8f433SVinod Koul no-map; 514b7e8f433SVinod Koul }; 515b7e8f433SVinod Koul 516b7e8f433SVinod Koul qrtr_shbuf: memory@d7ef7000 { 517b7e8f433SVinod Koul reg = <0x0 0xd7ef7000 0x0 0x9000>; 518b7e8f433SVinod Koul no-map; 519b7e8f433SVinod Koul }; 520b7e8f433SVinod Koul 521b7e8f433SVinod Koul chan0_shbuf: memory@d7f00000 { 522b7e8f433SVinod Koul reg = <0x0 0xd7f00000 0x0 0x80000>; 523b7e8f433SVinod Koul no-map; 524b7e8f433SVinod Koul }; 525b7e8f433SVinod Koul 526b7e8f433SVinod Koul chan1_shbuf: memory@d7f80000 { 527b7e8f433SVinod Koul reg = <0x0 0xd7f80000 0x0 0x80000>; 528b7e8f433SVinod Koul no-map; 529b7e8f433SVinod Koul }; 530b7e8f433SVinod Koul 531b7e8f433SVinod Koul removed_mem: memory@d8800000 { 532b7e8f433SVinod Koul reg = <0x0 0xd8800000 0x0 0x6800000>; 533b7e8f433SVinod Koul no-map; 534b7e8f433SVinod Koul }; 535b7e8f433SVinod Koul }; 536b7e8f433SVinod Koul 53703a41991SVinod Koul smp2p-adsp { 53803a41991SVinod Koul compatible = "qcom,smp2p"; 53903a41991SVinod Koul qcom,smem = <443>, <429>; 54003a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 54103a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 54203a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 54303a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_LPASS 54403a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 54503a41991SVinod Koul 54603a41991SVinod Koul qcom,local-pid = <0>; 54703a41991SVinod Koul qcom,remote-pid = <2>; 54803a41991SVinod Koul 54903a41991SVinod Koul smp2p_adsp_out: master-kernel { 55003a41991SVinod Koul qcom,entry-name = "master-kernel"; 55103a41991SVinod Koul #qcom,smem-state-cells = <1>; 55203a41991SVinod Koul }; 55303a41991SVinod Koul 55403a41991SVinod Koul smp2p_adsp_in: slave-kernel { 55503a41991SVinod Koul qcom,entry-name = "slave-kernel"; 55603a41991SVinod Koul interrupt-controller; 55703a41991SVinod Koul #interrupt-cells = <2>; 55803a41991SVinod Koul }; 55903a41991SVinod Koul }; 56003a41991SVinod Koul 56103a41991SVinod Koul smp2p-cdsp { 56203a41991SVinod Koul compatible = "qcom,smp2p"; 56303a41991SVinod Koul qcom,smem = <94>, <432>; 56403a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 56503a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 56603a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 56703a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_CDSP 56803a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 56903a41991SVinod Koul 57003a41991SVinod Koul qcom,local-pid = <0>; 57103a41991SVinod Koul qcom,remote-pid = <5>; 57203a41991SVinod Koul 57303a41991SVinod Koul smp2p_cdsp_out: master-kernel { 57403a41991SVinod Koul qcom,entry-name = "master-kernel"; 57503a41991SVinod Koul #qcom,smem-state-cells = <1>; 57603a41991SVinod Koul }; 57703a41991SVinod Koul 57803a41991SVinod Koul smp2p_cdsp_in: slave-kernel { 57903a41991SVinod Koul qcom,entry-name = "slave-kernel"; 58003a41991SVinod Koul interrupt-controller; 58103a41991SVinod Koul #interrupt-cells = <2>; 58203a41991SVinod Koul }; 58303a41991SVinod Koul }; 58403a41991SVinod Koul 58503a41991SVinod Koul smp2p-modem { 58603a41991SVinod Koul compatible = "qcom,smp2p"; 58703a41991SVinod Koul qcom,smem = <435>, <428>; 58803a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 58903a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 59003a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 59103a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_MPSS 59203a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 59303a41991SVinod Koul 59403a41991SVinod Koul qcom,local-pid = <0>; 59503a41991SVinod Koul qcom,remote-pid = <1>; 59603a41991SVinod Koul 59703a41991SVinod Koul smp2p_modem_out: master-kernel { 59803a41991SVinod Koul qcom,entry-name = "master-kernel"; 59903a41991SVinod Koul #qcom,smem-state-cells = <1>; 60003a41991SVinod Koul }; 60103a41991SVinod Koul 60203a41991SVinod Koul smp2p_modem_in: slave-kernel { 60303a41991SVinod Koul qcom,entry-name = "slave-kernel"; 60403a41991SVinod Koul interrupt-controller; 60503a41991SVinod Koul #interrupt-cells = <2>; 60603a41991SVinod Koul }; 607f11d3e7dSAlex Elder 608f11d3e7dSAlex Elder ipa_smp2p_out: ipa-ap-to-modem { 609f11d3e7dSAlex Elder qcom,entry-name = "ipa"; 610f11d3e7dSAlex Elder #qcom,smem-state-cells = <1>; 611f11d3e7dSAlex Elder }; 612f11d3e7dSAlex Elder 613f11d3e7dSAlex Elder ipa_smp2p_in: ipa-modem-to-ap { 614f11d3e7dSAlex Elder qcom,entry-name = "ipa"; 615f11d3e7dSAlex Elder interrupt-controller; 616f11d3e7dSAlex Elder #interrupt-cells = <2>; 617f11d3e7dSAlex Elder }; 61803a41991SVinod Koul }; 61903a41991SVinod Koul 62003a41991SVinod Koul smp2p-slpi { 62103a41991SVinod Koul compatible = "qcom,smp2p"; 62203a41991SVinod Koul qcom,smem = <481>, <430>; 62303a41991SVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 62403a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P 62503a41991SVinod Koul IRQ_TYPE_EDGE_RISING>; 62603a41991SVinod Koul mboxes = <&ipcc IPCC_CLIENT_SLPI 62703a41991SVinod Koul IPCC_MPROC_SIGNAL_SMP2P>; 62803a41991SVinod Koul 62903a41991SVinod Koul qcom,local-pid = <0>; 63003a41991SVinod Koul qcom,remote-pid = <3>; 63103a41991SVinod Koul 63203a41991SVinod Koul smp2p_slpi_out: master-kernel { 63303a41991SVinod Koul qcom,entry-name = "master-kernel"; 63403a41991SVinod Koul #qcom,smem-state-cells = <1>; 63503a41991SVinod Koul }; 63603a41991SVinod Koul 63703a41991SVinod Koul smp2p_slpi_in: slave-kernel { 63803a41991SVinod Koul qcom,entry-name = "slave-kernel"; 63903a41991SVinod Koul interrupt-controller; 64003a41991SVinod Koul #interrupt-cells = <2>; 64103a41991SVinod Koul }; 64203a41991SVinod Koul }; 64303a41991SVinod Koul 644b7e8f433SVinod Koul soc: soc@0 { 645b7e8f433SVinod Koul #address-cells = <2>; 646b7e8f433SVinod Koul #size-cells = <2>; 647b7e8f433SVinod Koul ranges = <0 0 0 0 0x10 0>; 648b7e8f433SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 649b7e8f433SVinod Koul compatible = "simple-bus"; 650b7e8f433SVinod Koul 651b7e8f433SVinod Koul gcc: clock-controller@100000 { 652b7e8f433SVinod Koul compatible = "qcom,gcc-sm8350"; 653b7e8f433SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 654b7e8f433SVinod Koul #clock-cells = <1>; 655b7e8f433SVinod Koul #reset-cells = <1>; 656b7e8f433SVinod Koul #power-domain-cells = <1>; 6579ea9eb36SKonrad Dybcio clock-names = "bi_tcxo", 6589ea9eb36SKonrad Dybcio "sleep_clk", 6599ea9eb36SKonrad Dybcio "pcie_0_pipe_clk", 6609ea9eb36SKonrad Dybcio "pcie_1_pipe_clk", 6619ea9eb36SKonrad Dybcio "ufs_card_rx_symbol_0_clk", 6629ea9eb36SKonrad Dybcio "ufs_card_rx_symbol_1_clk", 6639ea9eb36SKonrad Dybcio "ufs_card_tx_symbol_0_clk", 6649ea9eb36SKonrad Dybcio "ufs_phy_rx_symbol_0_clk", 6659ea9eb36SKonrad Dybcio "ufs_phy_rx_symbol_1_clk", 6669ea9eb36SKonrad Dybcio "ufs_phy_tx_symbol_0_clk", 6679ea9eb36SKonrad Dybcio "usb3_phy_wrapper_gcc_usb30_pipe_clk", 6689ea9eb36SKonrad Dybcio "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 6699ea9eb36SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 6709ea9eb36SKonrad Dybcio <&sleep_clk>, 6716daee406SDmitry Baryshkov <&pcie0_phy>, 6726daee406SDmitry Baryshkov <&pcie1_phy>, 6739ea9eb36SKonrad Dybcio <0>, 6749ea9eb36SKonrad Dybcio <0>, 6759ea9eb36SKonrad Dybcio <0>, 67686543bc6SDmitry Baryshkov <&ufs_mem_phy_lanes 0>, 67786543bc6SDmitry Baryshkov <&ufs_mem_phy_lanes 1>, 67886543bc6SDmitry Baryshkov <&ufs_mem_phy_lanes 2>, 6792458a305SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 6809ea9eb36SKonrad Dybcio <0>; 681b7e8f433SVinod Koul }; 682b7e8f433SVinod Koul 683b7e8f433SVinod Koul ipcc: mailbox@408000 { 684b7e8f433SVinod Koul compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 685b7e8f433SVinod Koul reg = <0 0x00408000 0 0x1000>; 686b7e8f433SVinod Koul interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 687b7e8f433SVinod Koul interrupt-controller; 688b7e8f433SVinod Koul #interrupt-cells = <3>; 689b7e8f433SVinod Koul #mbox-cells = <2>; 690b7e8f433SVinod Koul }; 691b7e8f433SVinod Koul 692bc08fbf4SBjorn Andersson gpi_dma2: dma-controller@800000 { 693b561e225SKrzysztof Kozlowski compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 694bc08fbf4SBjorn Andersson reg = <0 0x00800000 0 0x60000>; 695bc08fbf4SBjorn Andersson interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 696bc08fbf4SBjorn Andersson <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 697bc08fbf4SBjorn Andersson <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 698bc08fbf4SBjorn Andersson <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 699bc08fbf4SBjorn Andersson <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 700bc08fbf4SBjorn Andersson <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 701bc08fbf4SBjorn Andersson <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 702bc08fbf4SBjorn Andersson <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 703bc08fbf4SBjorn Andersson <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 704bc08fbf4SBjorn Andersson <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 705bc08fbf4SBjorn Andersson <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 706bc08fbf4SBjorn Andersson <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 707bc08fbf4SBjorn Andersson dma-channels = <12>; 708bc08fbf4SBjorn Andersson dma-channel-mask = <0xff>; 709bc08fbf4SBjorn Andersson iommus = <&apps_smmu 0x5f6 0x0>; 710bc08fbf4SBjorn Andersson #dma-cells = <3>; 711bc08fbf4SBjorn Andersson status = "disabled"; 712bc08fbf4SBjorn Andersson }; 713bc08fbf4SBjorn Andersson 714e84d04a2SKonrad Dybcio qupv3_id_2: geniqup@8c0000 { 715e84d04a2SKonrad Dybcio compatible = "qcom,geni-se-qup"; 716e84d04a2SKonrad Dybcio reg = <0x0 0x008c0000 0x0 0x6000>; 717e84d04a2SKonrad Dybcio clock-names = "m-ahb", "s-ahb"; 718e84d04a2SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 719e84d04a2SKonrad Dybcio <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 7209bc2c8feSKonrad Dybcio iommus = <&apps_smmu 0x5e3 0x0>; 721e84d04a2SKonrad Dybcio #address-cells = <2>; 722e84d04a2SKonrad Dybcio #size-cells = <2>; 723e84d04a2SKonrad Dybcio ranges; 724e84d04a2SKonrad Dybcio status = "disabled"; 72598374e69SKonrad Dybcio 72698374e69SKonrad Dybcio i2c14: i2c@880000 { 72798374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 72898374e69SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 72998374e69SKonrad Dybcio clock-names = "se"; 73098374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 73198374e69SKonrad Dybcio pinctrl-names = "default"; 73298374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c14_default>; 73398374e69SKonrad Dybcio interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 734ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 735ddc97e7dSBjorn Andersson <&gpi_dma2 1 0 QCOM_GPI_I2C>; 736ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 73798374e69SKonrad Dybcio #address-cells = <1>; 73898374e69SKonrad Dybcio #size-cells = <0>; 73998374e69SKonrad Dybcio status = "disabled"; 74098374e69SKonrad Dybcio }; 74198374e69SKonrad Dybcio 74298374e69SKonrad Dybcio spi14: spi@880000 { 74398374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 74498374e69SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 74598374e69SKonrad Dybcio clock-names = "se"; 74698374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 74798374e69SKonrad Dybcio interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 74898374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 74998374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_120mhz>; 750ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 751ddc97e7dSBjorn Andersson <&gpi_dma2 1 0 QCOM_GPI_SPI>; 752ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 75398374e69SKonrad Dybcio #address-cells = <1>; 75498374e69SKonrad Dybcio #size-cells = <0>; 75598374e69SKonrad Dybcio status = "disabled"; 75698374e69SKonrad Dybcio }; 75798374e69SKonrad Dybcio 75898374e69SKonrad Dybcio i2c15: i2c@884000 { 75998374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 76098374e69SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 76198374e69SKonrad Dybcio clock-names = "se"; 76298374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 76398374e69SKonrad Dybcio pinctrl-names = "default"; 76498374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c15_default>; 76598374e69SKonrad Dybcio interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 766ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 767ddc97e7dSBjorn Andersson <&gpi_dma2 1 1 QCOM_GPI_I2C>; 768ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 76998374e69SKonrad Dybcio #address-cells = <1>; 77098374e69SKonrad Dybcio #size-cells = <0>; 77198374e69SKonrad Dybcio status = "disabled"; 77298374e69SKonrad Dybcio }; 77398374e69SKonrad Dybcio 77498374e69SKonrad Dybcio spi15: spi@884000 { 77598374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 77698374e69SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 77798374e69SKonrad Dybcio clock-names = "se"; 77898374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 77998374e69SKonrad Dybcio interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 78098374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 78198374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_120mhz>; 782ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 783ddc97e7dSBjorn Andersson <&gpi_dma2 1 1 QCOM_GPI_SPI>; 784ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 78598374e69SKonrad Dybcio #address-cells = <1>; 78698374e69SKonrad Dybcio #size-cells = <0>; 78798374e69SKonrad Dybcio status = "disabled"; 78898374e69SKonrad Dybcio }; 78998374e69SKonrad Dybcio 79098374e69SKonrad Dybcio i2c16: i2c@888000 { 79198374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 79298374e69SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 79398374e69SKonrad Dybcio clock-names = "se"; 79498374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 79598374e69SKonrad Dybcio pinctrl-names = "default"; 79698374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c16_default>; 79798374e69SKonrad Dybcio interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 798ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 799ddc97e7dSBjorn Andersson <&gpi_dma2 1 2 QCOM_GPI_I2C>; 800ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 80198374e69SKonrad Dybcio #address-cells = <1>; 80298374e69SKonrad Dybcio #size-cells = <0>; 80398374e69SKonrad Dybcio status = "disabled"; 80498374e69SKonrad Dybcio }; 80598374e69SKonrad Dybcio 80698374e69SKonrad Dybcio spi16: spi@888000 { 80798374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 80898374e69SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 80998374e69SKonrad Dybcio clock-names = "se"; 81098374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 81198374e69SKonrad Dybcio interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 81298374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 81398374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 814ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 815ddc97e7dSBjorn Andersson <&gpi_dma2 1 2 QCOM_GPI_SPI>; 816ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 81798374e69SKonrad Dybcio #address-cells = <1>; 81898374e69SKonrad Dybcio #size-cells = <0>; 81998374e69SKonrad Dybcio status = "disabled"; 82098374e69SKonrad Dybcio }; 82198374e69SKonrad Dybcio 82298374e69SKonrad Dybcio i2c17: i2c@88c000 { 82398374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 82498374e69SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 82598374e69SKonrad Dybcio clock-names = "se"; 82698374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 82798374e69SKonrad Dybcio pinctrl-names = "default"; 82898374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c17_default>; 82998374e69SKonrad Dybcio interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 830ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 831ddc97e7dSBjorn Andersson <&gpi_dma2 1 3 QCOM_GPI_I2C>; 832ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 83398374e69SKonrad Dybcio #address-cells = <1>; 83498374e69SKonrad Dybcio #size-cells = <0>; 83598374e69SKonrad Dybcio status = "disabled"; 83698374e69SKonrad Dybcio }; 83798374e69SKonrad Dybcio 83898374e69SKonrad Dybcio spi17: spi@88c000 { 83998374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 84098374e69SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 84198374e69SKonrad Dybcio clock-names = "se"; 84298374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 84398374e69SKonrad Dybcio interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 84498374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 84598374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 846ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 847ddc97e7dSBjorn Andersson <&gpi_dma2 1 3 QCOM_GPI_SPI>; 848ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 84998374e69SKonrad Dybcio #address-cells = <1>; 85098374e69SKonrad Dybcio #size-cells = <0>; 85198374e69SKonrad Dybcio status = "disabled"; 85298374e69SKonrad Dybcio }; 85398374e69SKonrad Dybcio 85498374e69SKonrad Dybcio /* QUP no. 18 seems to be strictly SPI/UART-only */ 85598374e69SKonrad Dybcio 85698374e69SKonrad Dybcio spi18: spi@890000 { 85798374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 85898374e69SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 85998374e69SKonrad Dybcio clock-names = "se"; 86098374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 86198374e69SKonrad Dybcio interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 86298374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 86398374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 864ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 865ddc97e7dSBjorn Andersson <&gpi_dma2 1 4 QCOM_GPI_SPI>; 866ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 86798374e69SKonrad Dybcio #address-cells = <1>; 86898374e69SKonrad Dybcio #size-cells = <0>; 86998374e69SKonrad Dybcio status = "disabled"; 87098374e69SKonrad Dybcio }; 87198374e69SKonrad Dybcio 87298374e69SKonrad Dybcio uart18: serial@890000 { 87398374e69SKonrad Dybcio compatible = "qcom,geni-uart"; 87498374e69SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 87598374e69SKonrad Dybcio clock-names = "se"; 87698374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 87798374e69SKonrad Dybcio pinctrl-names = "default"; 87898374e69SKonrad Dybcio pinctrl-0 = <&qup_uart18_default>; 87998374e69SKonrad Dybcio interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 88098374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 88198374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 88298374e69SKonrad Dybcio status = "disabled"; 88398374e69SKonrad Dybcio }; 88498374e69SKonrad Dybcio 88598374e69SKonrad Dybcio i2c19: i2c@894000 { 88698374e69SKonrad Dybcio compatible = "qcom,geni-i2c"; 88798374e69SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 88898374e69SKonrad Dybcio clock-names = "se"; 88998374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 89098374e69SKonrad Dybcio pinctrl-names = "default"; 89198374e69SKonrad Dybcio pinctrl-0 = <&qup_i2c19_default>; 89298374e69SKonrad Dybcio interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 893ddc97e7dSBjorn Andersson dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 894ddc97e7dSBjorn Andersson <&gpi_dma2 1 5 QCOM_GPI_I2C>; 895ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 89698374e69SKonrad Dybcio #address-cells = <1>; 89798374e69SKonrad Dybcio #size-cells = <0>; 89898374e69SKonrad Dybcio status = "disabled"; 89998374e69SKonrad Dybcio }; 90098374e69SKonrad Dybcio 90198374e69SKonrad Dybcio spi19: spi@894000 { 90298374e69SKonrad Dybcio compatible = "qcom,geni-spi"; 90398374e69SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 90498374e69SKonrad Dybcio clock-names = "se"; 90598374e69SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 90698374e69SKonrad Dybcio interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 90798374e69SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 90898374e69SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 909bc08fbf4SBjorn Andersson dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 910bc08fbf4SBjorn Andersson <&gpi_dma2 1 5 QCOM_GPI_SPI>; 911bc08fbf4SBjorn Andersson dma-names = "tx", "rx"; 91298374e69SKonrad Dybcio #address-cells = <1>; 91398374e69SKonrad Dybcio #size-cells = <0>; 91498374e69SKonrad Dybcio status = "disabled"; 91598374e69SKonrad Dybcio }; 916e84d04a2SKonrad Dybcio }; 917e84d04a2SKonrad Dybcio 91841d6bca7SKrzysztof Kozlowski gpi_dma0: dma-controller@9800000 { 919b561e225SKrzysztof Kozlowski compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 920bc08fbf4SBjorn Andersson reg = <0 0x09800000 0 0x60000>; 921bc08fbf4SBjorn Andersson interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 922bc08fbf4SBjorn Andersson <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 923bc08fbf4SBjorn Andersson <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 924bc08fbf4SBjorn Andersson <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 925bc08fbf4SBjorn Andersson <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 926bc08fbf4SBjorn Andersson <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 927bc08fbf4SBjorn Andersson <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 928bc08fbf4SBjorn Andersson <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 929bc08fbf4SBjorn Andersson <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 930bc08fbf4SBjorn Andersson <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 931bc08fbf4SBjorn Andersson <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 932bc08fbf4SBjorn Andersson <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 933bc08fbf4SBjorn Andersson dma-channels = <12>; 934bc08fbf4SBjorn Andersson dma-channel-mask = <0x7e>; 935bc08fbf4SBjorn Andersson iommus = <&apps_smmu 0x5b6 0x0>; 936bc08fbf4SBjorn Andersson #dma-cells = <3>; 937bc08fbf4SBjorn Andersson status = "disabled"; 938bc08fbf4SBjorn Andersson }; 939bc08fbf4SBjorn Andersson 94087f0b434SRobert Foss qupv3_id_0: geniqup@9c0000 { 941b7e8f433SVinod Koul compatible = "qcom,geni-se-qup"; 942b7e8f433SVinod Koul reg = <0x0 0x009c0000 0x0 0x6000>; 943b7e8f433SVinod Koul clock-names = "m-ahb", "s-ahb"; 9446d91e201SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9456d91e201SVinod Koul <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9469bc2c8feSKonrad Dybcio iommus = <&apps_smmu 0x5a3 0>; 947b7e8f433SVinod Koul #address-cells = <2>; 948b7e8f433SVinod Koul #size-cells = <2>; 949b7e8f433SVinod Koul ranges; 950b7e8f433SVinod Koul status = "disabled"; 951b7e8f433SVinod Koul 952cf03cd7eSKonrad Dybcio i2c0: i2c@980000 { 953cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 954cf03cd7eSKonrad Dybcio reg = <0 0x00980000 0 0x4000>; 955cf03cd7eSKonrad Dybcio clock-names = "se"; 956cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 957cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 958cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c0_default>; 959cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 960ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 961ddc97e7dSBjorn Andersson <&gpi_dma0 1 0 QCOM_GPI_I2C>; 962ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 963cf03cd7eSKonrad Dybcio #address-cells = <1>; 964cf03cd7eSKonrad Dybcio #size-cells = <0>; 965cf03cd7eSKonrad Dybcio status = "disabled"; 966cf03cd7eSKonrad Dybcio }; 967cf03cd7eSKonrad Dybcio 968cf03cd7eSKonrad Dybcio spi0: spi@980000 { 969cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 970cf03cd7eSKonrad Dybcio reg = <0 0x00980000 0 0x4000>; 971cf03cd7eSKonrad Dybcio clock-names = "se"; 972cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 974cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 975cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 976ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 977ddc97e7dSBjorn Andersson <&gpi_dma0 1 0 QCOM_GPI_SPI>; 978ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 979cf03cd7eSKonrad Dybcio #address-cells = <1>; 980cf03cd7eSKonrad Dybcio #size-cells = <0>; 981cf03cd7eSKonrad Dybcio status = "disabled"; 982cf03cd7eSKonrad Dybcio }; 983cf03cd7eSKonrad Dybcio 984cf03cd7eSKonrad Dybcio i2c1: i2c@984000 { 985cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 986cf03cd7eSKonrad Dybcio reg = <0 0x00984000 0 0x4000>; 987cf03cd7eSKonrad Dybcio clock-names = "se"; 988cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 989cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 990cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c1_default>; 991cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 992ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 993ddc97e7dSBjorn Andersson <&gpi_dma0 1 1 QCOM_GPI_I2C>; 994ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 995cf03cd7eSKonrad Dybcio #address-cells = <1>; 996cf03cd7eSKonrad Dybcio #size-cells = <0>; 997cf03cd7eSKonrad Dybcio status = "disabled"; 998cf03cd7eSKonrad Dybcio }; 999cf03cd7eSKonrad Dybcio 1000cf03cd7eSKonrad Dybcio spi1: spi@984000 { 1001cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1002cf03cd7eSKonrad Dybcio reg = <0 0x00984000 0 0x4000>; 1003cf03cd7eSKonrad Dybcio clock-names = "se"; 1004cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1005cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1006cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1007cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1008ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1009ddc97e7dSBjorn Andersson <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1010ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1011cf03cd7eSKonrad Dybcio #address-cells = <1>; 1012cf03cd7eSKonrad Dybcio #size-cells = <0>; 1013cf03cd7eSKonrad Dybcio status = "disabled"; 1014cf03cd7eSKonrad Dybcio }; 1015cf03cd7eSKonrad Dybcio 1016cf03cd7eSKonrad Dybcio i2c2: i2c@988000 { 1017cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1018cf03cd7eSKonrad Dybcio reg = <0 0x00988000 0 0x4000>; 1019cf03cd7eSKonrad Dybcio clock-names = "se"; 1020cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1021cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1022cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c2_default>; 1023cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1024ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1025ddc97e7dSBjorn Andersson <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1026ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1027cf03cd7eSKonrad Dybcio #address-cells = <1>; 1028cf03cd7eSKonrad Dybcio #size-cells = <0>; 1029cf03cd7eSKonrad Dybcio status = "disabled"; 1030cf03cd7eSKonrad Dybcio }; 1031cf03cd7eSKonrad Dybcio 1032cf03cd7eSKonrad Dybcio spi2: spi@988000 { 1033cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1034cf03cd7eSKonrad Dybcio reg = <0 0x00988000 0 0x4000>; 1035cf03cd7eSKonrad Dybcio clock-names = "se"; 1036cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1037cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1038cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1039cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1040ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1041ddc97e7dSBjorn Andersson <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1042ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1043cf03cd7eSKonrad Dybcio #address-cells = <1>; 1044cf03cd7eSKonrad Dybcio #size-cells = <0>; 1045cf03cd7eSKonrad Dybcio status = "disabled"; 1046cf03cd7eSKonrad Dybcio }; 1047cf03cd7eSKonrad Dybcio 1048b7e8f433SVinod Koul uart2: serial@98c000 { 1049b7e8f433SVinod Koul compatible = "qcom,geni-debug-uart"; 1050b7e8f433SVinod Koul reg = <0 0x0098c000 0 0x4000>; 1051b7e8f433SVinod Koul clock-names = "se"; 10526d91e201SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1053b7e8f433SVinod Koul pinctrl-names = "default"; 1054b7e8f433SVinod Koul pinctrl-0 = <&qup_uart3_default_state>; 1055b7e8f433SVinod Koul interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1056cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1057cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1058cf03cd7eSKonrad Dybcio status = "disabled"; 1059cf03cd7eSKonrad Dybcio }; 1060cf03cd7eSKonrad Dybcio 1061cf03cd7eSKonrad Dybcio /* QUP no. 3 seems to be strictly SPI-only */ 1062cf03cd7eSKonrad Dybcio 1063cf03cd7eSKonrad Dybcio spi3: spi@98c000 { 1064cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1065cf03cd7eSKonrad Dybcio reg = <0 0x0098c000 0 0x4000>; 1066cf03cd7eSKonrad Dybcio clock-names = "se"; 1067cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1068cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1069cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1070cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1071ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1072ddc97e7dSBjorn Andersson <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1073ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1074cf03cd7eSKonrad Dybcio #address-cells = <1>; 1075cf03cd7eSKonrad Dybcio #size-cells = <0>; 1076cf03cd7eSKonrad Dybcio status = "disabled"; 1077cf03cd7eSKonrad Dybcio }; 1078cf03cd7eSKonrad Dybcio 1079cf03cd7eSKonrad Dybcio i2c4: i2c@990000 { 1080cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1081cf03cd7eSKonrad Dybcio reg = <0 0x00990000 0 0x4000>; 1082cf03cd7eSKonrad Dybcio clock-names = "se"; 1083cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1084cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1085cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c4_default>; 1086cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1087ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1088ddc97e7dSBjorn Andersson <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1089ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1090cf03cd7eSKonrad Dybcio #address-cells = <1>; 1091cf03cd7eSKonrad Dybcio #size-cells = <0>; 1092cf03cd7eSKonrad Dybcio status = "disabled"; 1093cf03cd7eSKonrad Dybcio }; 1094cf03cd7eSKonrad Dybcio 1095cf03cd7eSKonrad Dybcio spi4: spi@990000 { 1096cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1097cf03cd7eSKonrad Dybcio reg = <0 0x00990000 0 0x4000>; 1098cf03cd7eSKonrad Dybcio clock-names = "se"; 1099cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1100cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1101cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1102cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1103ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1104ddc97e7dSBjorn Andersson <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1105ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1106cf03cd7eSKonrad Dybcio #address-cells = <1>; 1107cf03cd7eSKonrad Dybcio #size-cells = <0>; 1108cf03cd7eSKonrad Dybcio status = "disabled"; 1109cf03cd7eSKonrad Dybcio }; 1110cf03cd7eSKonrad Dybcio 1111cf03cd7eSKonrad Dybcio i2c5: i2c@994000 { 1112cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1113cf03cd7eSKonrad Dybcio reg = <0 0x00994000 0 0x4000>; 1114cf03cd7eSKonrad Dybcio clock-names = "se"; 1115cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1116cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1117cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c5_default>; 1118cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1119ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1120ddc97e7dSBjorn Andersson <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1121ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1122cf03cd7eSKonrad Dybcio #address-cells = <1>; 1123cf03cd7eSKonrad Dybcio #size-cells = <0>; 1124cf03cd7eSKonrad Dybcio status = "disabled"; 1125cf03cd7eSKonrad Dybcio }; 1126cf03cd7eSKonrad Dybcio 1127cf03cd7eSKonrad Dybcio spi5: spi@994000 { 1128cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1129cf03cd7eSKonrad Dybcio reg = <0 0x00994000 0 0x4000>; 1130cf03cd7eSKonrad Dybcio clock-names = "se"; 1131cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1132cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1133cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1134cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1135ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1136ddc97e7dSBjorn Andersson <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1137ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1138cf03cd7eSKonrad Dybcio #address-cells = <1>; 1139cf03cd7eSKonrad Dybcio #size-cells = <0>; 1140cf03cd7eSKonrad Dybcio status = "disabled"; 1141cf03cd7eSKonrad Dybcio }; 1142cf03cd7eSKonrad Dybcio 1143cf03cd7eSKonrad Dybcio i2c6: i2c@998000 { 1144cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1145cf03cd7eSKonrad Dybcio reg = <0 0x00998000 0 0x4000>; 1146cf03cd7eSKonrad Dybcio clock-names = "se"; 1147cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1148cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1149cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c6_default>; 1150cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1151ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1152ddc97e7dSBjorn Andersson <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1153ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1154cf03cd7eSKonrad Dybcio #address-cells = <1>; 1155cf03cd7eSKonrad Dybcio #size-cells = <0>; 1156cf03cd7eSKonrad Dybcio status = "disabled"; 1157cf03cd7eSKonrad Dybcio }; 1158cf03cd7eSKonrad Dybcio 1159cf03cd7eSKonrad Dybcio spi6: spi@998000 { 1160cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1161cf03cd7eSKonrad Dybcio reg = <0 0x00998000 0 0x4000>; 1162cf03cd7eSKonrad Dybcio clock-names = "se"; 1163cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1164cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1165cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1166cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1167ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1168ddc97e7dSBjorn Andersson <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1169ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1170cf03cd7eSKonrad Dybcio #address-cells = <1>; 1171cf03cd7eSKonrad Dybcio #size-cells = <0>; 1172cf03cd7eSKonrad Dybcio status = "disabled"; 1173cf03cd7eSKonrad Dybcio }; 1174cf03cd7eSKonrad Dybcio 1175cf03cd7eSKonrad Dybcio uart6: serial@998000 { 1176cf03cd7eSKonrad Dybcio compatible = "qcom,geni-uart"; 1177cf03cd7eSKonrad Dybcio reg = <0 0x00998000 0 0x4000>; 1178cf03cd7eSKonrad Dybcio clock-names = "se"; 1179cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1180cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1181cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_uart6_default>; 1182cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1184cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1185cf03cd7eSKonrad Dybcio status = "disabled"; 1186cf03cd7eSKonrad Dybcio }; 1187cf03cd7eSKonrad Dybcio 1188cf03cd7eSKonrad Dybcio i2c7: i2c@99c000 { 1189cf03cd7eSKonrad Dybcio compatible = "qcom,geni-i2c"; 1190cf03cd7eSKonrad Dybcio reg = <0 0x0099c000 0 0x4000>; 1191cf03cd7eSKonrad Dybcio clock-names = "se"; 1192cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1193cf03cd7eSKonrad Dybcio pinctrl-names = "default"; 1194cf03cd7eSKonrad Dybcio pinctrl-0 = <&qup_i2c7_default>; 1195cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1196ddc97e7dSBjorn Andersson dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1197ddc97e7dSBjorn Andersson <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1198ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 1199cf03cd7eSKonrad Dybcio #address-cells = <1>; 1200cf03cd7eSKonrad Dybcio #size-cells = <0>; 1201cf03cd7eSKonrad Dybcio status = "disabled"; 1202cf03cd7eSKonrad Dybcio }; 1203cf03cd7eSKonrad Dybcio 1204cf03cd7eSKonrad Dybcio spi7: spi@99c000 { 1205cf03cd7eSKonrad Dybcio compatible = "qcom,geni-spi"; 1206cf03cd7eSKonrad Dybcio reg = <0 0x0099c000 0 0x4000>; 1207cf03cd7eSKonrad Dybcio clock-names = "se"; 1208cf03cd7eSKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1209cf03cd7eSKonrad Dybcio interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1210cf03cd7eSKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 1211cf03cd7eSKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1212bc08fbf4SBjorn Andersson dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1213bc08fbf4SBjorn Andersson <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1214bc08fbf4SBjorn Andersson dma-names = "tx", "rx"; 1215b7e8f433SVinod Koul #address-cells = <1>; 1216b7e8f433SVinod Koul #size-cells = <0>; 1217b7e8f433SVinod Koul status = "disabled"; 1218b7e8f433SVinod Koul }; 1219b7e8f433SVinod Koul }; 1220b7e8f433SVinod Koul 1221bc08fbf4SBjorn Andersson gpi_dma1: dma-controller@a00000 { 1222b561e225SKrzysztof Kozlowski compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1223bc08fbf4SBjorn Andersson reg = <0 0x00a00000 0 0x60000>; 1224bc08fbf4SBjorn Andersson interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1225bc08fbf4SBjorn Andersson <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1226bc08fbf4SBjorn Andersson <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1227bc08fbf4SBjorn Andersson <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1228bc08fbf4SBjorn Andersson <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1229bc08fbf4SBjorn Andersson <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1230bc08fbf4SBjorn Andersson <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1231bc08fbf4SBjorn Andersson <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1232bc08fbf4SBjorn Andersson <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1233bc08fbf4SBjorn Andersson <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1234bc08fbf4SBjorn Andersson <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1235bc08fbf4SBjorn Andersson <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1236bc08fbf4SBjorn Andersson dma-channels = <12>; 1237bc08fbf4SBjorn Andersson dma-channel-mask = <0xff>; 1238bc08fbf4SBjorn Andersson iommus = <&apps_smmu 0x56 0x0>; 1239bc08fbf4SBjorn Andersson #dma-cells = <3>; 1240bc08fbf4SBjorn Andersson status = "disabled"; 1241bc08fbf4SBjorn Andersson }; 1242bc08fbf4SBjorn Andersson 124306bf656eSJonathan Marek qupv3_id_1: geniqup@ac0000 { 124406bf656eSJonathan Marek compatible = "qcom,geni-se-qup"; 124506bf656eSJonathan Marek reg = <0x0 0x00ac0000 0x0 0x6000>; 124606bf656eSJonathan Marek clock-names = "m-ahb", "s-ahb"; 124706bf656eSJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 124806bf656eSJonathan Marek <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12499bc2c8feSKonrad Dybcio iommus = <&apps_smmu 0x43 0>; 125006bf656eSJonathan Marek #address-cells = <2>; 125106bf656eSJonathan Marek #size-cells = <2>; 125206bf656eSJonathan Marek ranges; 125306bf656eSJonathan Marek status = "disabled"; 125406bf656eSJonathan Marek 125589345355SKonrad Dybcio i2c8: i2c@a80000 { 125689345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 125789345355SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 125889345355SKonrad Dybcio clock-names = "se"; 125989345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 126089345355SKonrad Dybcio pinctrl-names = "default"; 126189345355SKonrad Dybcio pinctrl-0 = <&qup_i2c8_default>; 126289345355SKonrad Dybcio interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1263ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1264ddc97e7dSBjorn Andersson <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1265ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 126689345355SKonrad Dybcio #address-cells = <1>; 126789345355SKonrad Dybcio #size-cells = <0>; 126889345355SKonrad Dybcio status = "disabled"; 126989345355SKonrad Dybcio }; 127089345355SKonrad Dybcio 127189345355SKonrad Dybcio spi8: spi@a80000 { 127289345355SKonrad Dybcio compatible = "qcom,geni-spi"; 127389345355SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 127489345355SKonrad Dybcio clock-names = "se"; 127589345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 127689345355SKonrad Dybcio interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 127789345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 127889345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_120mhz>; 1279ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1280ddc97e7dSBjorn Andersson <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1281ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 128289345355SKonrad Dybcio #address-cells = <1>; 128389345355SKonrad Dybcio #size-cells = <0>; 128489345355SKonrad Dybcio status = "disabled"; 128589345355SKonrad Dybcio }; 128689345355SKonrad Dybcio 128789345355SKonrad Dybcio i2c9: i2c@a84000 { 128889345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 128989345355SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 129089345355SKonrad Dybcio clock-names = "se"; 129189345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 129289345355SKonrad Dybcio pinctrl-names = "default"; 129389345355SKonrad Dybcio pinctrl-0 = <&qup_i2c9_default>; 129489345355SKonrad Dybcio interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1295ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1296ddc97e7dSBjorn Andersson <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1297ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 129889345355SKonrad Dybcio #address-cells = <1>; 129989345355SKonrad Dybcio #size-cells = <0>; 130089345355SKonrad Dybcio status = "disabled"; 130189345355SKonrad Dybcio }; 130289345355SKonrad Dybcio 130389345355SKonrad Dybcio spi9: spi@a84000 { 130489345355SKonrad Dybcio compatible = "qcom,geni-spi"; 130589345355SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 130689345355SKonrad Dybcio clock-names = "se"; 130789345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 130889345355SKonrad Dybcio interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 130989345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 131089345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1311ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1312ddc97e7dSBjorn Andersson <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1313ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 131489345355SKonrad Dybcio #address-cells = <1>; 131589345355SKonrad Dybcio #size-cells = <0>; 131689345355SKonrad Dybcio status = "disabled"; 131789345355SKonrad Dybcio }; 131889345355SKonrad Dybcio 131989345355SKonrad Dybcio i2c10: i2c@a88000 { 132089345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 132189345355SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 132289345355SKonrad Dybcio clock-names = "se"; 132389345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 132489345355SKonrad Dybcio pinctrl-names = "default"; 132589345355SKonrad Dybcio pinctrl-0 = <&qup_i2c10_default>; 132689345355SKonrad Dybcio interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1327ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1328ddc97e7dSBjorn Andersson <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1329ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 133089345355SKonrad Dybcio #address-cells = <1>; 133189345355SKonrad Dybcio #size-cells = <0>; 133289345355SKonrad Dybcio status = "disabled"; 133389345355SKonrad Dybcio }; 133489345355SKonrad Dybcio 133589345355SKonrad Dybcio spi10: spi@a88000 { 133689345355SKonrad Dybcio compatible = "qcom,geni-spi"; 133789345355SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 133889345355SKonrad Dybcio clock-names = "se"; 133989345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 134089345355SKonrad Dybcio interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 134189345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 134289345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1343ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1344ddc97e7dSBjorn Andersson <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1345ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 134689345355SKonrad Dybcio #address-cells = <1>; 134789345355SKonrad Dybcio #size-cells = <0>; 134889345355SKonrad Dybcio status = "disabled"; 134989345355SKonrad Dybcio }; 135089345355SKonrad Dybcio 135189345355SKonrad Dybcio i2c11: i2c@a8c000 { 135289345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 135389345355SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 135489345355SKonrad Dybcio clock-names = "se"; 135589345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 135689345355SKonrad Dybcio pinctrl-names = "default"; 135789345355SKonrad Dybcio pinctrl-0 = <&qup_i2c11_default>; 135889345355SKonrad Dybcio interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1359ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1360ddc97e7dSBjorn Andersson <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1361ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 136289345355SKonrad Dybcio #address-cells = <1>; 136389345355SKonrad Dybcio #size-cells = <0>; 136489345355SKonrad Dybcio status = "disabled"; 136589345355SKonrad Dybcio }; 136689345355SKonrad Dybcio 136789345355SKonrad Dybcio spi11: spi@a8c000 { 136889345355SKonrad Dybcio compatible = "qcom,geni-spi"; 136989345355SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 137089345355SKonrad Dybcio clock-names = "se"; 137189345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 137289345355SKonrad Dybcio interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 137389345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 137489345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1375ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1376ddc97e7dSBjorn Andersson <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1377ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 137889345355SKonrad Dybcio #address-cells = <1>; 137989345355SKonrad Dybcio #size-cells = <0>; 138089345355SKonrad Dybcio status = "disabled"; 138189345355SKonrad Dybcio }; 138289345355SKonrad Dybcio 138389345355SKonrad Dybcio i2c12: i2c@a90000 { 138489345355SKonrad Dybcio compatible = "qcom,geni-i2c"; 138589345355SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 138689345355SKonrad Dybcio clock-names = "se"; 138789345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 138889345355SKonrad Dybcio pinctrl-names = "default"; 138989345355SKonrad Dybcio pinctrl-0 = <&qup_i2c12_default>; 139089345355SKonrad Dybcio interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1391ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1392ddc97e7dSBjorn Andersson <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1393ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 139489345355SKonrad Dybcio #address-cells = <1>; 139589345355SKonrad Dybcio #size-cells = <0>; 139689345355SKonrad Dybcio status = "disabled"; 139789345355SKonrad Dybcio }; 139889345355SKonrad Dybcio 139989345355SKonrad Dybcio spi12: spi@a90000 { 140089345355SKonrad Dybcio compatible = "qcom,geni-spi"; 140189345355SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 140289345355SKonrad Dybcio clock-names = "se"; 140389345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 140489345355SKonrad Dybcio interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 140589345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 140689345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1407ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1408ddc97e7dSBjorn Andersson <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1409ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 141089345355SKonrad Dybcio #address-cells = <1>; 141189345355SKonrad Dybcio #size-cells = <0>; 141289345355SKonrad Dybcio status = "disabled"; 141389345355SKonrad Dybcio }; 141489345355SKonrad Dybcio 141506bf656eSJonathan Marek i2c13: i2c@a94000 { 141606bf656eSJonathan Marek compatible = "qcom,geni-i2c"; 141706bf656eSJonathan Marek reg = <0 0x00a94000 0 0x4000>; 141806bf656eSJonathan Marek clock-names = "se"; 141906bf656eSJonathan Marek clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 142006bf656eSJonathan Marek pinctrl-names = "default"; 142189345355SKonrad Dybcio pinctrl-0 = <&qup_i2c13_default>; 142206bf656eSJonathan Marek interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1423ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1424ddc97e7dSBjorn Andersson <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1425ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 142606bf656eSJonathan Marek #address-cells = <1>; 142706bf656eSJonathan Marek #size-cells = <0>; 142806bf656eSJonathan Marek status = "disabled"; 142906bf656eSJonathan Marek }; 143089345355SKonrad Dybcio 143189345355SKonrad Dybcio spi13: spi@a94000 { 143289345355SKonrad Dybcio compatible = "qcom,geni-spi"; 143389345355SKonrad Dybcio reg = <0 0x00a94000 0 0x4000>; 143489345355SKonrad Dybcio clock-names = "se"; 143589345355SKonrad Dybcio clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 143689345355SKonrad Dybcio interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 143789345355SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 143889345355SKonrad Dybcio operating-points-v2 = <&qup_opp_table_100mhz>; 1439ddc97e7dSBjorn Andersson dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1440ddc97e7dSBjorn Andersson <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1441ddc97e7dSBjorn Andersson dma-names = "tx", "rx"; 144289345355SKonrad Dybcio #address-cells = <1>; 144389345355SKonrad Dybcio #size-cells = <0>; 144489345355SKonrad Dybcio status = "disabled"; 144589345355SKonrad Dybcio }; 144606bf656eSJonathan Marek }; 144706bf656eSJonathan Marek 14481417372fSDmitry Baryshkov rng: rng@10d3000 { 14491417372fSDmitry Baryshkov compatible = "qcom,prng-ee"; 14501417372fSDmitry Baryshkov reg = <0 0x010d3000 0 0x1000>; 14511417372fSDmitry Baryshkov clocks = <&rpmhcc RPMH_HWKM_CLK>; 14521417372fSDmitry Baryshkov clock-names = "core"; 14531417372fSDmitry Baryshkov }; 14541417372fSDmitry Baryshkov 1455da6b2482SVinod Koul config_noc: interconnect@1500000 { 1456da6b2482SVinod Koul compatible = "qcom,sm8350-config-noc"; 1457da6b2482SVinod Koul reg = <0 0x01500000 0 0xa580>; 14584f287e31SRobert Foss #interconnect-cells = <2>; 1459da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1460da6b2482SVinod Koul }; 1461da6b2482SVinod Koul 1462da6b2482SVinod Koul mc_virt: interconnect@1580000 { 1463da6b2482SVinod Koul compatible = "qcom,sm8350-mc-virt"; 1464da6b2482SVinod Koul reg = <0 0x01580000 0 0x1000>; 14654f287e31SRobert Foss #interconnect-cells = <2>; 1466da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1467da6b2482SVinod Koul }; 1468da6b2482SVinod Koul 1469da6b2482SVinod Koul system_noc: interconnect@1680000 { 1470da6b2482SVinod Koul compatible = "qcom,sm8350-system-noc"; 1471da6b2482SVinod Koul reg = <0 0x01680000 0 0x1c200>; 14724f287e31SRobert Foss #interconnect-cells = <2>; 1473da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1474da6b2482SVinod Koul }; 1475da6b2482SVinod Koul 1476da6b2482SVinod Koul aggre1_noc: interconnect@16e0000 { 1477da6b2482SVinod Koul compatible = "qcom,sm8350-aggre1-noc"; 1478da6b2482SVinod Koul reg = <0 0x016e0000 0 0x1f180>; 14794f287e31SRobert Foss #interconnect-cells = <2>; 1480da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1481da6b2482SVinod Koul }; 1482da6b2482SVinod Koul 1483da6b2482SVinod Koul aggre2_noc: interconnect@1700000 { 1484da6b2482SVinod Koul compatible = "qcom,sm8350-aggre2-noc"; 1485da6b2482SVinod Koul reg = <0 0x01700000 0 0x33000>; 14864f287e31SRobert Foss #interconnect-cells = <2>; 1487da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1488da6b2482SVinod Koul }; 1489da6b2482SVinod Koul 1490da6b2482SVinod Koul mmss_noc: interconnect@1740000 { 1491da6b2482SVinod Koul compatible = "qcom,sm8350-mmss-noc"; 1492da6b2482SVinod Koul reg = <0 0x01740000 0 0x1f080>; 14934f287e31SRobert Foss #interconnect-cells = <2>; 1494da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 1495da6b2482SVinod Koul }; 1496da6b2482SVinod Koul 14976daee406SDmitry Baryshkov pcie0: pci@1c00000 { 14986daee406SDmitry Baryshkov compatible = "qcom,pcie-sm8350"; 14996daee406SDmitry Baryshkov reg = <0 0x01c00000 0 0x3000>, 15006daee406SDmitry Baryshkov <0 0x60000000 0 0xf1d>, 15016daee406SDmitry Baryshkov <0 0x60000f20 0 0xa8>, 15026daee406SDmitry Baryshkov <0 0x60001000 0 0x1000>, 15036daee406SDmitry Baryshkov <0 0x60100000 0 0x100000>; 15046daee406SDmitry Baryshkov reg-names = "parf", "dbi", "elbi", "atu", "config"; 15056daee406SDmitry Baryshkov device_type = "pci"; 15066daee406SDmitry Baryshkov linux,pci-domain = <0>; 15076daee406SDmitry Baryshkov bus-range = <0x00 0xff>; 15086daee406SDmitry Baryshkov num-lanes = <1>; 15096daee406SDmitry Baryshkov 15106daee406SDmitry Baryshkov #address-cells = <3>; 15116daee406SDmitry Baryshkov #size-cells = <2>; 15126daee406SDmitry Baryshkov 1513cf4e716eSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1514cf4e716eSManivannan Sadhasivam <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 15156daee406SDmitry Baryshkov 15166daee406SDmitry Baryshkov interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 15176daee406SDmitry Baryshkov <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 15186daee406SDmitry Baryshkov <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 15196daee406SDmitry Baryshkov <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 15206daee406SDmitry Baryshkov <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 15216daee406SDmitry Baryshkov <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 15226daee406SDmitry Baryshkov <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 15236daee406SDmitry Baryshkov <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 15246daee406SDmitry Baryshkov interrupt-names = "msi0", "msi1", "msi2", "msi3", 15256daee406SDmitry Baryshkov "msi4", "msi5", "msi6", "msi7"; 15266daee406SDmitry Baryshkov #interrupt-cells = <1>; 15276daee406SDmitry Baryshkov interrupt-map-mask = <0 0 0 0x7>; 15286daee406SDmitry Baryshkov interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 15296daee406SDmitry Baryshkov <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 15306daee406SDmitry Baryshkov <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 15316daee406SDmitry Baryshkov <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 15326daee406SDmitry Baryshkov 15336daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 15346daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 15356daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 15366daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 15376daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 15386daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 15396daee406SDmitry Baryshkov <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 15406daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 15416daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 15426daee406SDmitry Baryshkov clock-names = "aux", 15436daee406SDmitry Baryshkov "cfg", 15446daee406SDmitry Baryshkov "bus_master", 15456daee406SDmitry Baryshkov "bus_slave", 15466daee406SDmitry Baryshkov "slave_q2a", 15476daee406SDmitry Baryshkov "tbu", 15486daee406SDmitry Baryshkov "ddrss_sf_tbu", 15496daee406SDmitry Baryshkov "aggre1", 15506daee406SDmitry Baryshkov "aggre0"; 15516daee406SDmitry Baryshkov 15526daee406SDmitry Baryshkov iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 15536daee406SDmitry Baryshkov <0x100 &apps_smmu 0x1c01 0x1>; 15546daee406SDmitry Baryshkov 15556daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_0_BCR>; 15566daee406SDmitry Baryshkov reset-names = "pci"; 15576daee406SDmitry Baryshkov 15586daee406SDmitry Baryshkov power-domains = <&gcc PCIE_0_GDSC>; 15596daee406SDmitry Baryshkov 15606daee406SDmitry Baryshkov phys = <&pcie0_phy>; 15616daee406SDmitry Baryshkov phy-names = "pciephy"; 15626daee406SDmitry Baryshkov 15636daee406SDmitry Baryshkov status = "disabled"; 15646daee406SDmitry Baryshkov }; 15656daee406SDmitry Baryshkov 15666daee406SDmitry Baryshkov pcie0_phy: phy@1c06000 { 15676daee406SDmitry Baryshkov compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 15686daee406SDmitry Baryshkov reg = <0 0x01c06000 0 0x2000>; 15696daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 15706daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 15716daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_CLKREF_EN>, 15726daee406SDmitry Baryshkov <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 15736daee406SDmitry Baryshkov <&gcc GCC_PCIE_0_PIPE_CLK>; 15746daee406SDmitry Baryshkov clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 15756daee406SDmitry Baryshkov 15766daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_0_PHY_BCR>; 15776daee406SDmitry Baryshkov reset-names = "phy"; 15786daee406SDmitry Baryshkov 15796daee406SDmitry Baryshkov assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 15806daee406SDmitry Baryshkov assigned-clock-rates = <100000000>; 15816daee406SDmitry Baryshkov 15826daee406SDmitry Baryshkov #clock-cells = <0>; 15836daee406SDmitry Baryshkov clock-output-names = "pcie_0_pipe_clk"; 15846daee406SDmitry Baryshkov 15856daee406SDmitry Baryshkov #phy-cells = <0>; 15866daee406SDmitry Baryshkov 15876daee406SDmitry Baryshkov status = "disabled"; 15886daee406SDmitry Baryshkov }; 15896daee406SDmitry Baryshkov 15906daee406SDmitry Baryshkov pcie1: pci@1c08000 { 15916daee406SDmitry Baryshkov compatible = "qcom,pcie-sm8350"; 15926daee406SDmitry Baryshkov reg = <0 0x01c08000 0 0x3000>, 15936daee406SDmitry Baryshkov <0 0x40000000 0 0xf1d>, 15946daee406SDmitry Baryshkov <0 0x40000f20 0 0xa8>, 15956daee406SDmitry Baryshkov <0 0x40001000 0 0x1000>, 15966daee406SDmitry Baryshkov <0 0x40100000 0 0x100000>; 15976daee406SDmitry Baryshkov reg-names = "parf", "dbi", "elbi", "atu", "config"; 15986daee406SDmitry Baryshkov device_type = "pci"; 15996daee406SDmitry Baryshkov linux,pci-domain = <1>; 16006daee406SDmitry Baryshkov bus-range = <0x00 0xff>; 16016daee406SDmitry Baryshkov num-lanes = <2>; 16026daee406SDmitry Baryshkov 16036daee406SDmitry Baryshkov #address-cells = <3>; 16046daee406SDmitry Baryshkov #size-cells = <2>; 16056daee406SDmitry Baryshkov 1606cf4e716eSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1607cf4e716eSManivannan Sadhasivam <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 16086daee406SDmitry Baryshkov 16096daee406SDmitry Baryshkov interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 16106daee406SDmitry Baryshkov interrupt-names = "msi"; 16116daee406SDmitry Baryshkov #interrupt-cells = <1>; 16126daee406SDmitry Baryshkov interrupt-map-mask = <0 0 0 0x7>; 16136daee406SDmitry Baryshkov interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 16146daee406SDmitry Baryshkov <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 16156daee406SDmitry Baryshkov <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 16166daee406SDmitry Baryshkov <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 16176daee406SDmitry Baryshkov 16186daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 16196daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 16206daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 16216daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 16226daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 16236daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 16246daee406SDmitry Baryshkov <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 16256daee406SDmitry Baryshkov <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 16266daee406SDmitry Baryshkov clock-names = "aux", 16276daee406SDmitry Baryshkov "cfg", 16286daee406SDmitry Baryshkov "bus_master", 16296daee406SDmitry Baryshkov "bus_slave", 16306daee406SDmitry Baryshkov "slave_q2a", 16316daee406SDmitry Baryshkov "tbu", 16326daee406SDmitry Baryshkov "ddrss_sf_tbu", 16336daee406SDmitry Baryshkov "aggre1"; 16346daee406SDmitry Baryshkov 16356daee406SDmitry Baryshkov iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 16366daee406SDmitry Baryshkov <0x100 &apps_smmu 0x1c81 0x1>; 16376daee406SDmitry Baryshkov 16386daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_1_BCR>; 16396daee406SDmitry Baryshkov reset-names = "pci"; 16406daee406SDmitry Baryshkov 16416daee406SDmitry Baryshkov power-domains = <&gcc PCIE_1_GDSC>; 16426daee406SDmitry Baryshkov 16436daee406SDmitry Baryshkov phys = <&pcie1_phy>; 16446daee406SDmitry Baryshkov phy-names = "pciephy"; 16456daee406SDmitry Baryshkov 16466daee406SDmitry Baryshkov status = "disabled"; 16476daee406SDmitry Baryshkov }; 16486daee406SDmitry Baryshkov 1649ab98c21bSKrzysztof Kozlowski pcie1_phy: phy@1c0e000 { 16506daee406SDmitry Baryshkov compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 16516daee406SDmitry Baryshkov reg = <0 0x01c0e000 0 0x2000>; 16526daee406SDmitry Baryshkov clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 16536daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 16546daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_CLKREF_EN>, 16556daee406SDmitry Baryshkov <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 16566daee406SDmitry Baryshkov <&gcc GCC_PCIE_1_PIPE_CLK>; 16576daee406SDmitry Baryshkov clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 16586daee406SDmitry Baryshkov 16596daee406SDmitry Baryshkov resets = <&gcc GCC_PCIE_1_PHY_BCR>; 16606daee406SDmitry Baryshkov reset-names = "phy"; 16616daee406SDmitry Baryshkov 16626daee406SDmitry Baryshkov assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 16636daee406SDmitry Baryshkov assigned-clock-rates = <100000000>; 16646daee406SDmitry Baryshkov 16656daee406SDmitry Baryshkov #clock-cells = <0>; 16666daee406SDmitry Baryshkov clock-output-names = "pcie_1_pipe_clk"; 16676daee406SDmitry Baryshkov 16686daee406SDmitry Baryshkov #phy-cells = <0>; 16696daee406SDmitry Baryshkov 16706daee406SDmitry Baryshkov status = "disabled"; 16716daee406SDmitry Baryshkov }; 16726daee406SDmitry Baryshkov 16731417372fSDmitry Baryshkov ufs_mem_hc: ufshc@1d84000 { 16741417372fSDmitry Baryshkov compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 16751417372fSDmitry Baryshkov "jedec,ufs-2.0"; 16761417372fSDmitry Baryshkov reg = <0 0x01d84000 0 0x3000>; 16771417372fSDmitry Baryshkov interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 16781417372fSDmitry Baryshkov phys = <&ufs_mem_phy_lanes>; 16791417372fSDmitry Baryshkov phy-names = "ufsphy"; 16801417372fSDmitry Baryshkov lanes-per-direction = <2>; 16811417372fSDmitry Baryshkov #reset-cells = <1>; 16821417372fSDmitry Baryshkov resets = <&gcc GCC_UFS_PHY_BCR>; 16831417372fSDmitry Baryshkov reset-names = "rst"; 16841417372fSDmitry Baryshkov 16851417372fSDmitry Baryshkov power-domains = <&gcc UFS_PHY_GDSC>; 16861417372fSDmitry Baryshkov 16871417372fSDmitry Baryshkov iommus = <&apps_smmu 0xe0 0x0>; 1688e607b3c1SManivannan Sadhasivam dma-coherent; 16891417372fSDmitry Baryshkov 16901417372fSDmitry Baryshkov clock-names = 16911417372fSDmitry Baryshkov "core_clk", 16921417372fSDmitry Baryshkov "bus_aggr_clk", 16931417372fSDmitry Baryshkov "iface_clk", 16941417372fSDmitry Baryshkov "core_clk_unipro", 16951417372fSDmitry Baryshkov "ref_clk", 16961417372fSDmitry Baryshkov "tx_lane0_sync_clk", 16971417372fSDmitry Baryshkov "rx_lane0_sync_clk", 16981417372fSDmitry Baryshkov "rx_lane1_sync_clk"; 16991417372fSDmitry Baryshkov clocks = 17001417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_AXI_CLK>, 17011417372fSDmitry Baryshkov <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 17021417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_AHB_CLK>, 17031417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 17041417372fSDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>, 17051417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 17061417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 17071417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 17081417372fSDmitry Baryshkov freq-table-hz = 17091417372fSDmitry Baryshkov <75000000 300000000>, 17101417372fSDmitry Baryshkov <0 0>, 17111417372fSDmitry Baryshkov <0 0>, 17121417372fSDmitry Baryshkov <75000000 300000000>, 17131417372fSDmitry Baryshkov <0 0>, 17141417372fSDmitry Baryshkov <0 0>, 17151417372fSDmitry Baryshkov <0 0>, 17161417372fSDmitry Baryshkov <0 0>; 17171417372fSDmitry Baryshkov status = "disabled"; 1718da6b2482SVinod Koul }; 1719da6b2482SVinod Koul 17201417372fSDmitry Baryshkov ufs_mem_phy: phy@1d87000 { 17211417372fSDmitry Baryshkov compatible = "qcom,sm8350-qmp-ufs-phy"; 17221417372fSDmitry Baryshkov reg = <0 0x01d87000 0 0x1c4>; 17231417372fSDmitry Baryshkov #address-cells = <2>; 17241417372fSDmitry Baryshkov #size-cells = <2>; 17251417372fSDmitry Baryshkov ranges; 17261417372fSDmitry Baryshkov clock-names = "ref", 17271417372fSDmitry Baryshkov "ref_aux"; 17281417372fSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 17291417372fSDmitry Baryshkov <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 17301417372fSDmitry Baryshkov 17311417372fSDmitry Baryshkov resets = <&ufs_mem_hc 0>; 17321417372fSDmitry Baryshkov reset-names = "ufsphy"; 17331417372fSDmitry Baryshkov status = "disabled"; 17341417372fSDmitry Baryshkov 17351417372fSDmitry Baryshkov ufs_mem_phy_lanes: phy@1d87400 { 17361417372fSDmitry Baryshkov reg = <0 0x01d87400 0 0x188>, 17371417372fSDmitry Baryshkov <0 0x01d87600 0 0x200>, 17381417372fSDmitry Baryshkov <0 0x01d87c00 0 0x200>, 17391417372fSDmitry Baryshkov <0 0x01d87800 0 0x188>, 17401417372fSDmitry Baryshkov <0 0x01d87a00 0 0x200>; 17411417372fSDmitry Baryshkov #clock-cells = <1>; 17421417372fSDmitry Baryshkov #phy-cells = <0>; 17431417372fSDmitry Baryshkov }; 1744da6b2482SVinod Koul }; 1745da6b2482SVinod Koul 1746f1040a7fSBhupesh Sharma cryptobam: dma-controller@1dc4000 { 1747f1040a7fSBhupesh Sharma compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1748f1040a7fSBhupesh Sharma reg = <0 0x01dc4000 0 0x24000>; 1749f1040a7fSBhupesh Sharma interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1750f1040a7fSBhupesh Sharma #dma-cells = <1>; 1751f1040a7fSBhupesh Sharma qcom,ee = <0>; 1752f1040a7fSBhupesh Sharma qcom,controlled-remotely; 1753f1040a7fSBhupesh Sharma iommus = <&apps_smmu 0x594 0x0011>, 1754f1040a7fSBhupesh Sharma <&apps_smmu 0x596 0x0011>; 1755f1040a7fSBhupesh Sharma }; 1756f1040a7fSBhupesh Sharma 1757f1040a7fSBhupesh Sharma crypto: crypto@1dfa000 { 1758f1040a7fSBhupesh Sharma compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1759f1040a7fSBhupesh Sharma reg = <0 0x01dfa000 0 0x6000>; 1760f1040a7fSBhupesh Sharma dmas = <&cryptobam 4>, <&cryptobam 5>; 1761f1040a7fSBhupesh Sharma dma-names = "rx", "tx"; 1762f1040a7fSBhupesh Sharma iommus = <&apps_smmu 0x594 0x0011>, 1763f1040a7fSBhupesh Sharma <&apps_smmu 0x596 0x0011>; 1764f1040a7fSBhupesh Sharma interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1765f1040a7fSBhupesh Sharma interconnect-names = "memory"; 1766f1040a7fSBhupesh Sharma }; 1767f1040a7fSBhupesh Sharma 1768f11d3e7dSAlex Elder ipa: ipa@1e40000 { 1769f11d3e7dSAlex Elder compatible = "qcom,sm8350-ipa"; 1770f11d3e7dSAlex Elder 1771f11d3e7dSAlex Elder iommus = <&apps_smmu 0x5c0 0x0>, 1772f11d3e7dSAlex Elder <&apps_smmu 0x5c2 0x0>; 1773f3c08ae6SKonrad Dybcio reg = <0 0x01e40000 0 0x8000>, 1774f3c08ae6SKonrad Dybcio <0 0x01e50000 0 0x4b20>, 1775f3c08ae6SKonrad Dybcio <0 0x01e04000 0 0x23000>; 1776f11d3e7dSAlex Elder reg-names = "ipa-reg", 1777f11d3e7dSAlex Elder "ipa-shared", 1778f11d3e7dSAlex Elder "gsi"; 1779f11d3e7dSAlex Elder 1780f11d3e7dSAlex Elder interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1781f11d3e7dSAlex Elder <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1782f11d3e7dSAlex Elder <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1783f11d3e7dSAlex Elder <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1784f11d3e7dSAlex Elder interrupt-names = "ipa", 1785f11d3e7dSAlex Elder "gsi", 1786f11d3e7dSAlex Elder "ipa-clock-query", 1787f11d3e7dSAlex Elder "ipa-setup-ready"; 1788f11d3e7dSAlex Elder 1789f11d3e7dSAlex Elder clocks = <&rpmhcc RPMH_IPA_CLK>; 1790f11d3e7dSAlex Elder clock-names = "core"; 1791f11d3e7dSAlex Elder 17924f287e31SRobert Foss interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 17934f287e31SRobert Foss <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 179484173ca3SAlex Elder interconnect-names = "memory", 179584173ca3SAlex Elder "config"; 1796f11d3e7dSAlex Elder 179773419e4dSAlex Elder qcom,qmp = <&aoss_qmp>; 179873419e4dSAlex Elder 1799f11d3e7dSAlex Elder qcom,smem-states = <&ipa_smp2p_out 0>, 1800f11d3e7dSAlex Elder <&ipa_smp2p_out 1>; 1801f11d3e7dSAlex Elder qcom,smem-state-names = "ipa-clock-enabled-valid", 1802f11d3e7dSAlex Elder "ipa-clock-enabled"; 1803f11d3e7dSAlex Elder 1804f11d3e7dSAlex Elder status = "disabled"; 1805f11d3e7dSAlex Elder }; 1806f11d3e7dSAlex Elder 1807b7e8f433SVinod Koul tcsr_mutex: hwlock@1f40000 { 1808b7e8f433SVinod Koul compatible = "qcom,tcsr-mutex"; 1809b7e8f433SVinod Koul reg = <0x0 0x01f40000 0x0 0x40000>; 1810b7e8f433SVinod Koul #hwlock-cells = <1>; 1811b7e8f433SVinod Koul }; 1812b7e8f433SVinod Koul 181354af0cebSDmitry Baryshkov gpu: gpu@3d00000 { 181454af0cebSDmitry Baryshkov compatible = "qcom,adreno-660.1", "qcom,adreno"; 181554af0cebSDmitry Baryshkov 181654af0cebSDmitry Baryshkov reg = <0 0x03d00000 0 0x40000>, 181754af0cebSDmitry Baryshkov <0 0x03d9e000 0 0x1000>, 181854af0cebSDmitry Baryshkov <0 0x03d61000 0 0x800>; 181954af0cebSDmitry Baryshkov reg-names = "kgsl_3d0_reg_memory", 182054af0cebSDmitry Baryshkov "cx_mem", 182154af0cebSDmitry Baryshkov "cx_dbgc"; 182254af0cebSDmitry Baryshkov 182354af0cebSDmitry Baryshkov interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 182454af0cebSDmitry Baryshkov 182554af0cebSDmitry Baryshkov iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 182654af0cebSDmitry Baryshkov 182754af0cebSDmitry Baryshkov operating-points-v2 = <&gpu_opp_table>; 182854af0cebSDmitry Baryshkov 182954af0cebSDmitry Baryshkov qcom,gmu = <&gmu>; 183054af0cebSDmitry Baryshkov 183154af0cebSDmitry Baryshkov status = "disabled"; 183254af0cebSDmitry Baryshkov 183354af0cebSDmitry Baryshkov zap-shader { 183454af0cebSDmitry Baryshkov memory-region = <&pil_gpu_mem>; 183554af0cebSDmitry Baryshkov }; 183654af0cebSDmitry Baryshkov 183754af0cebSDmitry Baryshkov /* note: downstream checks gpu binning for 670 Mhz */ 183854af0cebSDmitry Baryshkov gpu_opp_table: opp-table { 183954af0cebSDmitry Baryshkov compatible = "operating-points-v2"; 184054af0cebSDmitry Baryshkov 184154af0cebSDmitry Baryshkov opp-840000000 { 184254af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <840000000>; 184354af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 184454af0cebSDmitry Baryshkov }; 184554af0cebSDmitry Baryshkov 184654af0cebSDmitry Baryshkov opp-778000000 { 184754af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <778000000>; 184854af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 184954af0cebSDmitry Baryshkov }; 185054af0cebSDmitry Baryshkov 185154af0cebSDmitry Baryshkov opp-738000000 { 185254af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <738000000>; 185354af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 185454af0cebSDmitry Baryshkov }; 185554af0cebSDmitry Baryshkov 185654af0cebSDmitry Baryshkov opp-676000000 { 185754af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <676000000>; 185854af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 185954af0cebSDmitry Baryshkov }; 186054af0cebSDmitry Baryshkov 186154af0cebSDmitry Baryshkov opp-608000000 { 186254af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <608000000>; 186354af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 186454af0cebSDmitry Baryshkov }; 186554af0cebSDmitry Baryshkov 186654af0cebSDmitry Baryshkov opp-540000000 { 186754af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <540000000>; 186854af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 186954af0cebSDmitry Baryshkov }; 187054af0cebSDmitry Baryshkov 187154af0cebSDmitry Baryshkov opp-491000000 { 187254af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <491000000>; 187354af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 187454af0cebSDmitry Baryshkov }; 187554af0cebSDmitry Baryshkov 187654af0cebSDmitry Baryshkov opp-443000000 { 187754af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <443000000>; 187854af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 187954af0cebSDmitry Baryshkov }; 188054af0cebSDmitry Baryshkov 188154af0cebSDmitry Baryshkov opp-379000000 { 188254af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <379000000>; 188354af0cebSDmitry Baryshkov opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 188454af0cebSDmitry Baryshkov }; 188554af0cebSDmitry Baryshkov 188654af0cebSDmitry Baryshkov opp-315000000 { 188754af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <315000000>; 188854af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 188954af0cebSDmitry Baryshkov }; 189054af0cebSDmitry Baryshkov }; 189154af0cebSDmitry Baryshkov }; 189254af0cebSDmitry Baryshkov 189354af0cebSDmitry Baryshkov gmu: gmu@3d6a000 { 189454af0cebSDmitry Baryshkov compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 189554af0cebSDmitry Baryshkov 189654af0cebSDmitry Baryshkov reg = <0 0x03d6a000 0 0x34000>, 189754af0cebSDmitry Baryshkov <0 0x03de0000 0 0x10000>, 189854af0cebSDmitry Baryshkov <0 0x0b290000 0 0x10000>; 189954af0cebSDmitry Baryshkov reg-names = "gmu", "rscc", "gmu_pdc"; 190054af0cebSDmitry Baryshkov 190154af0cebSDmitry Baryshkov interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 190254af0cebSDmitry Baryshkov <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 190354af0cebSDmitry Baryshkov interrupt-names = "hfi", "gmu"; 190454af0cebSDmitry Baryshkov 190554af0cebSDmitry Baryshkov clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 190654af0cebSDmitry Baryshkov <&gpucc GPU_CC_CXO_CLK>, 190754af0cebSDmitry Baryshkov <&gcc GCC_DDRSS_GPU_AXI_CLK>, 190854af0cebSDmitry Baryshkov <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 190954af0cebSDmitry Baryshkov <&gpucc GPU_CC_AHB_CLK>, 191054af0cebSDmitry Baryshkov <&gpucc GPU_CC_HUB_CX_INT_CLK>, 191154af0cebSDmitry Baryshkov <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 191254af0cebSDmitry Baryshkov clock-names = "gmu", 191354af0cebSDmitry Baryshkov "cxo", 191454af0cebSDmitry Baryshkov "axi", 191554af0cebSDmitry Baryshkov "memnoc", 191654af0cebSDmitry Baryshkov "ahb", 191754af0cebSDmitry Baryshkov "hub", 191854af0cebSDmitry Baryshkov "smmu_vote"; 191954af0cebSDmitry Baryshkov 192054af0cebSDmitry Baryshkov power-domains = <&gpucc GPU_CX_GDSC>, 192154af0cebSDmitry Baryshkov <&gpucc GPU_GX_GDSC>; 192254af0cebSDmitry Baryshkov power-domain-names = "cx", 192354af0cebSDmitry Baryshkov "gx"; 192454af0cebSDmitry Baryshkov 192554af0cebSDmitry Baryshkov iommus = <&adreno_smmu 5 0x400>; 192654af0cebSDmitry Baryshkov 192754af0cebSDmitry Baryshkov operating-points-v2 = <&gmu_opp_table>; 192854af0cebSDmitry Baryshkov 192954af0cebSDmitry Baryshkov gmu_opp_table: opp-table { 193054af0cebSDmitry Baryshkov compatible = "operating-points-v2"; 193154af0cebSDmitry Baryshkov 193254af0cebSDmitry Baryshkov opp-200000000 { 193354af0cebSDmitry Baryshkov opp-hz = /bits/ 64 <200000000>; 193454af0cebSDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 193554af0cebSDmitry Baryshkov }; 193654af0cebSDmitry Baryshkov }; 193754af0cebSDmitry Baryshkov }; 193854af0cebSDmitry Baryshkov 193954af0cebSDmitry Baryshkov gpucc: clock-controller@3d90000 { 194054af0cebSDmitry Baryshkov compatible = "qcom,sm8350-gpucc"; 194154af0cebSDmitry Baryshkov reg = <0 0x03d90000 0 0x9000>; 194254af0cebSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, 194354af0cebSDmitry Baryshkov <&gcc GCC_GPU_GPLL0_CLK_SRC>, 194454af0cebSDmitry Baryshkov <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 194554af0cebSDmitry Baryshkov clock-names = "bi_tcxo", 194654af0cebSDmitry Baryshkov "gcc_gpu_gpll0_clk_src", 194754af0cebSDmitry Baryshkov "gcc_gpu_gpll0_div_clk_src"; 194854af0cebSDmitry Baryshkov #clock-cells = <1>; 194954af0cebSDmitry Baryshkov #reset-cells = <1>; 195054af0cebSDmitry Baryshkov #power-domain-cells = <1>; 195154af0cebSDmitry Baryshkov }; 195254af0cebSDmitry Baryshkov 195354af0cebSDmitry Baryshkov adreno_smmu: iommu@3da0000 { 195478c61b6bSKonrad Dybcio compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 195578c61b6bSKonrad Dybcio "qcom,smmu-500", "arm,mmu-500"; 195654af0cebSDmitry Baryshkov reg = <0 0x03da0000 0 0x20000>; 195754af0cebSDmitry Baryshkov #iommu-cells = <2>; 195854af0cebSDmitry Baryshkov #global-interrupts = <2>; 195954af0cebSDmitry Baryshkov interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 196054af0cebSDmitry Baryshkov <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 196154af0cebSDmitry Baryshkov <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 196254af0cebSDmitry Baryshkov <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 196354af0cebSDmitry Baryshkov <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 196454af0cebSDmitry Baryshkov <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 196554af0cebSDmitry Baryshkov <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 196654af0cebSDmitry Baryshkov <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 196754af0cebSDmitry Baryshkov <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 196854af0cebSDmitry Baryshkov <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 196954af0cebSDmitry Baryshkov <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 197054af0cebSDmitry Baryshkov <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 197154af0cebSDmitry Baryshkov 197254af0cebSDmitry Baryshkov clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 197354af0cebSDmitry Baryshkov <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 197454af0cebSDmitry Baryshkov <&gpucc GPU_CC_AHB_CLK>, 197554af0cebSDmitry Baryshkov <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 197654af0cebSDmitry Baryshkov <&gpucc GPU_CC_CX_GMU_CLK>, 197754af0cebSDmitry Baryshkov <&gpucc GPU_CC_HUB_CX_INT_CLK>, 197854af0cebSDmitry Baryshkov <&gpucc GPU_CC_HUB_AON_CLK>; 197954af0cebSDmitry Baryshkov clock-names = "bus", 198054af0cebSDmitry Baryshkov "iface", 198154af0cebSDmitry Baryshkov "ahb", 198254af0cebSDmitry Baryshkov "hlos1_vote_gpu_smmu", 198354af0cebSDmitry Baryshkov "cx_gmu", 198454af0cebSDmitry Baryshkov "hub_cx_int", 198554af0cebSDmitry Baryshkov "hub_aon"; 198654af0cebSDmitry Baryshkov 198754af0cebSDmitry Baryshkov power-domains = <&gpucc GPU_CX_GDSC>; 198854af0cebSDmitry Baryshkov dma-coherent; 198954af0cebSDmitry Baryshkov }; 199054af0cebSDmitry Baryshkov 19911417372fSDmitry Baryshkov lpass_ag_noc: interconnect@3c40000 { 19921417372fSDmitry Baryshkov compatible = "qcom,sm8350-lpass-ag-noc"; 19931417372fSDmitry Baryshkov reg = <0 0x03c40000 0 0xf080>; 19941417372fSDmitry Baryshkov #interconnect-cells = <2>; 19951417372fSDmitry Baryshkov qcom,bcm-voters = <&apps_bcm_voter>; 19961417372fSDmitry Baryshkov }; 19971417372fSDmitry Baryshkov 1998177fcf0aSVinod Koul mpss: remoteproc@4080000 { 1999177fcf0aSVinod Koul compatible = "qcom,sm8350-mpss-pas"; 2000177fcf0aSVinod Koul reg = <0x0 0x04080000 0x0 0x4040>; 2001177fcf0aSVinod Koul 2002177fcf0aSVinod Koul interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2003177fcf0aSVinod Koul <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2004177fcf0aSVinod Koul <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2005177fcf0aSVinod Koul <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2006177fcf0aSVinod Koul <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2007177fcf0aSVinod Koul <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2008177fcf0aSVinod Koul interrupt-names = "wdog", "fatal", "ready", "handover", 2009177fcf0aSVinod Koul "stop-ack", "shutdown-ack"; 2010177fcf0aSVinod Koul 2011177fcf0aSVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>; 2012177fcf0aSVinod Koul clock-names = "xo"; 2013177fcf0aSVinod Koul 2014d0e285c3SRobert Foss power-domains = <&rpmhpd SM8350_CX>, 2015d0e285c3SRobert Foss <&rpmhpd SM8350_MSS>; 20166b7cb2d2SSibi Sankar power-domain-names = "cx", "mss"; 2017177fcf0aSVinod Koul 20184f287e31SRobert Foss interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2019da6b2482SVinod Koul 2020177fcf0aSVinod Koul memory-region = <&pil_modem_mem>; 2021177fcf0aSVinod Koul 20226b7cb2d2SSibi Sankar qcom,qmp = <&aoss_qmp>; 20236b7cb2d2SSibi Sankar 2024177fcf0aSVinod Koul qcom,smem-states = <&smp2p_modem_out 0>; 2025177fcf0aSVinod Koul qcom,smem-state-names = "stop"; 2026177fcf0aSVinod Koul 2027177fcf0aSVinod Koul status = "disabled"; 2028177fcf0aSVinod Koul 2029177fcf0aSVinod Koul glink-edge { 2030177fcf0aSVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2031177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP 2032177fcf0aSVinod Koul IRQ_TYPE_EDGE_RISING>; 2033177fcf0aSVinod Koul mboxes = <&ipcc IPCC_CLIENT_MPSS 2034177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP>; 2035177fcf0aSVinod Koul label = "modem"; 2036177fcf0aSVinod Koul qcom,remote-pid = <1>; 2037177fcf0aSVinod Koul }; 2038177fcf0aSVinod Koul }; 2039177fcf0aSVinod Koul 20401417372fSDmitry Baryshkov slpi: remoteproc@5c00000 { 20411417372fSDmitry Baryshkov compatible = "qcom,sm8350-slpi-pas"; 20421417372fSDmitry Baryshkov reg = <0 0x05c00000 0 0x4000>; 20431417372fSDmitry Baryshkov 20441417372fSDmitry Baryshkov interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 20451417372fSDmitry Baryshkov <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 20461417372fSDmitry Baryshkov <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 20471417372fSDmitry Baryshkov <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 20481417372fSDmitry Baryshkov <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 20491417372fSDmitry Baryshkov interrupt-names = "wdog", "fatal", "ready", 20501417372fSDmitry Baryshkov "handover", "stop-ack"; 20511417372fSDmitry Baryshkov 20521417372fSDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>; 20531417372fSDmitry Baryshkov clock-names = "xo"; 20541417372fSDmitry Baryshkov 20551417372fSDmitry Baryshkov power-domains = <&rpmhpd SM8350_LCX>, 20561417372fSDmitry Baryshkov <&rpmhpd SM8350_LMX>; 20571417372fSDmitry Baryshkov power-domain-names = "lcx", "lmx"; 20581417372fSDmitry Baryshkov 20591417372fSDmitry Baryshkov memory-region = <&pil_slpi_mem>; 20601417372fSDmitry Baryshkov 20611417372fSDmitry Baryshkov qcom,qmp = <&aoss_qmp>; 20621417372fSDmitry Baryshkov 20631417372fSDmitry Baryshkov qcom,smem-states = <&smp2p_slpi_out 0>; 20641417372fSDmitry Baryshkov qcom,smem-state-names = "stop"; 20651417372fSDmitry Baryshkov 20661417372fSDmitry Baryshkov status = "disabled"; 20671417372fSDmitry Baryshkov 20681417372fSDmitry Baryshkov glink-edge { 20691417372fSDmitry Baryshkov interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 20701417372fSDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP 20711417372fSDmitry Baryshkov IRQ_TYPE_EDGE_RISING>; 20721417372fSDmitry Baryshkov mboxes = <&ipcc IPCC_CLIENT_SLPI 20731417372fSDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP>; 20741417372fSDmitry Baryshkov 20751417372fSDmitry Baryshkov label = "slpi"; 20761417372fSDmitry Baryshkov qcom,remote-pid = <3>; 20771417372fSDmitry Baryshkov 20781417372fSDmitry Baryshkov fastrpc { 20791417372fSDmitry Baryshkov compatible = "qcom,fastrpc"; 20801417372fSDmitry Baryshkov qcom,glink-channels = "fastrpcglink-apps-dsp"; 20811417372fSDmitry Baryshkov label = "sdsp"; 20821417372fSDmitry Baryshkov qcom,non-secure-domain; 20831417372fSDmitry Baryshkov #address-cells = <1>; 20841417372fSDmitry Baryshkov #size-cells = <0>; 20851417372fSDmitry Baryshkov 20861417372fSDmitry Baryshkov compute-cb@1 { 20871417372fSDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 20881417372fSDmitry Baryshkov reg = <1>; 20891417372fSDmitry Baryshkov iommus = <&apps_smmu 0x0541 0x0>; 20901417372fSDmitry Baryshkov }; 20911417372fSDmitry Baryshkov 20921417372fSDmitry Baryshkov compute-cb@2 { 20931417372fSDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 20941417372fSDmitry Baryshkov reg = <2>; 20951417372fSDmitry Baryshkov iommus = <&apps_smmu 0x0542 0x0>; 20961417372fSDmitry Baryshkov }; 20971417372fSDmitry Baryshkov 20981417372fSDmitry Baryshkov compute-cb@3 { 20991417372fSDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 21001417372fSDmitry Baryshkov reg = <3>; 21011417372fSDmitry Baryshkov iommus = <&apps_smmu 0x0543 0x0>; 21021417372fSDmitry Baryshkov /* note: shared-cb = <4> in downstream */ 21031417372fSDmitry Baryshkov }; 21041417372fSDmitry Baryshkov }; 21051417372fSDmitry Baryshkov }; 21061417372fSDmitry Baryshkov }; 21071417372fSDmitry Baryshkov 210806a0676bSKrzysztof Kozlowski sdhc_2: mmc@8804000 { 210960477435SKonrad Dybcio compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 211060477435SKonrad Dybcio reg = <0 0x08804000 0 0x1000>; 211160477435SKonrad Dybcio 211260477435SKonrad Dybcio interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 211360477435SKonrad Dybcio <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 211460477435SKonrad Dybcio interrupt-names = "hc_irq", "pwr_irq"; 211560477435SKonrad Dybcio 211660477435SKonrad Dybcio clocks = <&gcc GCC_SDCC2_AHB_CLK>, 211760477435SKonrad Dybcio <&gcc GCC_SDCC2_APPS_CLK>, 211860477435SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 211960477435SKonrad Dybcio clock-names = "iface", "core", "xo"; 212060477435SKonrad Dybcio resets = <&gcc GCC_SDCC2_BCR>; 2121fc0ff3e7SKrzysztof Kozlowski interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2122fc0ff3e7SKrzysztof Kozlowski <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 212360477435SKonrad Dybcio interconnect-names = "sdhc-ddr","cpu-sdhc"; 212460477435SKonrad Dybcio iommus = <&apps_smmu 0x4a0 0x0>; 212560477435SKonrad Dybcio power-domains = <&rpmhpd SM8350_CX>; 212660477435SKonrad Dybcio operating-points-v2 = <&sdhc2_opp_table>; 212760477435SKonrad Dybcio bus-width = <4>; 212860477435SKonrad Dybcio dma-coherent; 212960477435SKonrad Dybcio 213060477435SKonrad Dybcio status = "disabled"; 213160477435SKonrad Dybcio 213260477435SKonrad Dybcio sdhc2_opp_table: opp-table { 213360477435SKonrad Dybcio compatible = "operating-points-v2"; 213460477435SKonrad Dybcio 213560477435SKonrad Dybcio opp-100000000 { 213660477435SKonrad Dybcio opp-hz = /bits/ 64 <100000000>; 213760477435SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 213860477435SKonrad Dybcio }; 213960477435SKonrad Dybcio 214060477435SKonrad Dybcio opp-202000000 { 214160477435SKonrad Dybcio opp-hz = /bits/ 64 <202000000>; 214260477435SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 214360477435SKonrad Dybcio }; 214460477435SKonrad Dybcio }; 214560477435SKonrad Dybcio }; 214660477435SKonrad Dybcio 2147e780fb31SJack Pham usb_1_hsphy: phy@88e3000 { 2148e780fb31SJack Pham compatible = "qcom,sm8350-usb-hs-phy", 2149e780fb31SJack Pham "qcom,usb-snps-hs-7nm-phy"; 2150e780fb31SJack Pham reg = <0 0x088e3000 0 0x400>; 2151e780fb31SJack Pham status = "disabled"; 2152e780fb31SJack Pham #phy-cells = <0>; 2153e780fb31SJack Pham 2154e780fb31SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 2155e780fb31SJack Pham clock-names = "ref"; 2156e780fb31SJack Pham 21576d91e201SVinod Koul resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2158e780fb31SJack Pham }; 2159e780fb31SJack Pham 2160e780fb31SJack Pham usb_2_hsphy: phy@88e4000 { 2161e780fb31SJack Pham compatible = "qcom,sm8250-usb-hs-phy", 2162e780fb31SJack Pham "qcom,usb-snps-hs-7nm-phy"; 2163e780fb31SJack Pham reg = <0 0x088e4000 0 0x400>; 2164e780fb31SJack Pham status = "disabled"; 2165e780fb31SJack Pham #phy-cells = <0>; 2166e780fb31SJack Pham 2167e780fb31SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 2168e780fb31SJack Pham clock-names = "ref"; 2169e780fb31SJack Pham 21706d91e201SVinod Koul resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2171e780fb31SJack Pham }; 2172e780fb31SJack Pham 2173a560ab70SKrzysztof Kozlowski usb_1_qmpphy: phy@88e8000 { 21742458a305SNeil Armstrong compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 21752458a305SNeil Armstrong reg = <0 0x088e8000 0 0x3000>; 2176e780fb31SJack Pham 21776d91e201SVinod Koul clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2178e780fb31SJack Pham <&rpmhcc RPMH_CXO_CLK>, 21792458a305SNeil Armstrong <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 21802458a305SNeil Armstrong <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 21812458a305SNeil Armstrong clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2182e780fb31SJack Pham 21836d91e201SVinod Koul resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 21846d91e201SVinod Koul <&gcc GCC_USB3_PHY_PRIM_BCR>; 2185e780fb31SJack Pham reset-names = "phy", "common"; 2186e780fb31SJack Pham 21872458a305SNeil Armstrong #clock-cells = <1>; 21882458a305SNeil Armstrong #phy-cells = <1>; 21892458a305SNeil Armstrong 21902458a305SNeil Armstrong status = "disabled"; 2191d8313125SNeil Armstrong 2192d8313125SNeil Armstrong ports { 2193d8313125SNeil Armstrong #address-cells = <1>; 2194d8313125SNeil Armstrong #size-cells = <0>; 2195d8313125SNeil Armstrong 2196d8313125SNeil Armstrong port@0 { 2197d8313125SNeil Armstrong reg = <0>; 2198d8313125SNeil Armstrong 2199d8313125SNeil Armstrong usb_1_qmpphy_out: endpoint { 2200d8313125SNeil Armstrong }; 2201d8313125SNeil Armstrong }; 2202d8313125SNeil Armstrong 2203d8313125SNeil Armstrong port@1 { 2204d8313125SNeil Armstrong reg = <1>; 2205d8313125SNeil Armstrong 2206d8313125SNeil Armstrong usb_1_qmpphy_usb_ss_in: endpoint { 2207d8313125SNeil Armstrong }; 2208d8313125SNeil Armstrong }; 2209d8313125SNeil Armstrong 2210d8313125SNeil Armstrong port@2 { 2211d8313125SNeil Armstrong reg = <2>; 2212d8313125SNeil Armstrong 2213d8313125SNeil Armstrong usb_1_qmpphy_dp_in: endpoint { 2214d8313125SNeil Armstrong }; 2215d8313125SNeil Armstrong }; 2216d8313125SNeil Armstrong }; 2217e780fb31SJack Pham }; 2218e780fb31SJack Pham 2219e780fb31SJack Pham usb_2_qmpphy: phy-wrapper@88eb000 { 2220e780fb31SJack Pham compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2221e780fb31SJack Pham reg = <0 0x088eb000 0 0x200>; 2222e780fb31SJack Pham status = "disabled"; 2223e780fb31SJack Pham #address-cells = <2>; 2224e780fb31SJack Pham #size-cells = <2>; 2225e780fb31SJack Pham ranges; 2226e780fb31SJack Pham 22276d91e201SVinod Koul clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2228e780fb31SJack Pham <&rpmhcc RPMH_CXO_CLK>, 22296d91e201SVinod Koul <&gcc GCC_USB3_SEC_CLKREF_EN>, 22306d91e201SVinod Koul <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2231e780fb31SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2232e780fb31SJack Pham 22336d91e201SVinod Koul resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 22346d91e201SVinod Koul <&gcc GCC_USB3_PHY_SEC_BCR>; 2235e780fb31SJack Pham reset-names = "phy", "common"; 2236e780fb31SJack Pham 2237e780fb31SJack Pham usb_2_ssphy: phy@88ebe00 { 2238e780fb31SJack Pham reg = <0 0x088ebe00 0 0x200>, 2239e780fb31SJack Pham <0 0x088ec000 0 0x200>, 2240e780fb31SJack Pham <0 0x088eb200 0 0x1100>; 2241e780fb31SJack Pham #phy-cells = <0>; 2242af551554SJohan Hovold #clock-cells = <0>; 22436d91e201SVinod Koul clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2244e780fb31SJack Pham clock-names = "pipe0"; 2245e780fb31SJack Pham clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2246e780fb31SJack Pham }; 2247e780fb31SJack Pham }; 2248e780fb31SJack Pham 22491dee9e3bSVinod Koul dc_noc: interconnect@90c0000 { 2250da6b2482SVinod Koul compatible = "qcom,sm8350-dc-noc"; 2251da6b2482SVinod Koul reg = <0 0x090c0000 0 0x4200>; 22524f287e31SRobert Foss #interconnect-cells = <2>; 2253da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 2254da6b2482SVinod Koul }; 2255da6b2482SVinod Koul 2256da6b2482SVinod Koul gem_noc: interconnect@9100000 { 2257da6b2482SVinod Koul compatible = "qcom,sm8350-gem-noc"; 2258da6b2482SVinod Koul reg = <0 0x09100000 0 0xb4000>; 22594f287e31SRobert Foss #interconnect-cells = <2>; 2260da6b2482SVinod Koul qcom,bcm-voters = <&apps_bcm_voter>; 2261da6b2482SVinod Koul }; 2262da6b2482SVinod Koul 22639ac8999eSKonrad Dybcio system-cache-controller@9200000 { 22649ac8999eSKonrad Dybcio compatible = "qcom,sm8350-llcc"; 22657ae317cbSManivannan Sadhasivam reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 22667ae317cbSManivannan Sadhasivam <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 22677ae317cbSManivannan Sadhasivam <0 0x09600000 0 0x58000>; 22687ae317cbSManivannan Sadhasivam reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 22697ae317cbSManivannan Sadhasivam "llcc3_base", "llcc_broadcast_base"; 22709ac8999eSKonrad Dybcio }; 22719ac8999eSKonrad Dybcio 22721417372fSDmitry Baryshkov compute_noc: interconnect@a0c0000 { 22731417372fSDmitry Baryshkov compatible = "qcom,sm8350-compute-noc"; 22741417372fSDmitry Baryshkov reg = <0 0x0a0c0000 0 0xa180>; 22751417372fSDmitry Baryshkov #interconnect-cells = <2>; 22761417372fSDmitry Baryshkov qcom,bcm-voters = <&apps_bcm_voter>; 22771417372fSDmitry Baryshkov }; 22781417372fSDmitry Baryshkov 2279e780fb31SJack Pham usb_1: usb@a6f8800 { 2280e780fb31SJack Pham compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2281e780fb31SJack Pham reg = <0 0x0a6f8800 0 0x400>; 2282e780fb31SJack Pham status = "disabled"; 2283e780fb31SJack Pham #address-cells = <2>; 2284e780fb31SJack Pham #size-cells = <2>; 2285e780fb31SJack Pham ranges; 2286e780fb31SJack Pham 22876d91e201SVinod Koul clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 22886d91e201SVinod Koul <&gcc GCC_USB30_PRIM_MASTER_CLK>, 22896d91e201SVinod Koul <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 22908d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 22918d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 22928d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 22938d5fd4e4SKrzysztof Kozlowski "core", 22948d5fd4e4SKrzysztof Kozlowski "iface", 22958d5fd4e4SKrzysztof Kozlowski "sleep", 22968d5fd4e4SKrzysztof Kozlowski "mock_utmi"; 2297e780fb31SJack Pham 22986d91e201SVinod Koul assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 22996d91e201SVinod Koul <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2300e780fb31SJack Pham assigned-clock-rates = <19200000>, <200000000>; 2301e780fb31SJack Pham 2302e780fb31SJack Pham interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 23035b7e3499SJohan Hovold <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2304e780fb31SJack Pham <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 23055b7e3499SJohan Hovold <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 23065b7e3499SJohan Hovold interrupt-names = "hs_phy_irq", 23075b7e3499SJohan Hovold "ss_phy_irq", 23085b7e3499SJohan Hovold "dm_hs_phy_irq", 23095b7e3499SJohan Hovold "dp_hs_phy_irq"; 2310e780fb31SJack Pham 23116d91e201SVinod Koul power-domains = <&gcc USB30_PRIM_GDSC>; 2312e780fb31SJack Pham 23136d91e201SVinod Koul resets = <&gcc GCC_USB30_PRIM_BCR>; 2314e780fb31SJack Pham 23158b51dc86SAbel Vesa interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 23168b51dc86SAbel Vesa <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 23178b51dc86SAbel Vesa interconnect-names = "usb-ddr", "apps-usb"; 23188b51dc86SAbel Vesa 23192aa2b50dSBhupesh Sharma usb_1_dwc3: usb@a600000 { 2320e780fb31SJack Pham compatible = "snps,dwc3"; 2321e780fb31SJack Pham reg = <0 0x0a600000 0 0xcd00>; 2322e780fb31SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2323e780fb31SJack Pham iommus = <&apps_smmu 0x0 0x0>; 2324e780fb31SJack Pham snps,dis_u2_susphy_quirk; 2325e780fb31SJack Pham snps,dis_enblslpm_quirk; 23262458a305SNeil Armstrong phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2327e780fb31SJack Pham phy-names = "usb2-phy", "usb3-phy"; 232875b81e5aSNeil Armstrong 232975b81e5aSNeil Armstrong ports { 233075b81e5aSNeil Armstrong #address-cells = <1>; 233175b81e5aSNeil Armstrong #size-cells = <0>; 233275b81e5aSNeil Armstrong 233375b81e5aSNeil Armstrong port@0 { 233475b81e5aSNeil Armstrong reg = <0>; 233575b81e5aSNeil Armstrong 233675b81e5aSNeil Armstrong usb_1_dwc3_hs: endpoint { 233775b81e5aSNeil Armstrong }; 233875b81e5aSNeil Armstrong }; 233975b81e5aSNeil Armstrong 234075b81e5aSNeil Armstrong port@1 { 234175b81e5aSNeil Armstrong reg = <1>; 234275b81e5aSNeil Armstrong 234375b81e5aSNeil Armstrong usb_1_dwc3_ss: endpoint { 234475b81e5aSNeil Armstrong }; 234575b81e5aSNeil Armstrong }; 234675b81e5aSNeil Armstrong }; 2347e780fb31SJack Pham }; 2348e780fb31SJack Pham }; 2349e780fb31SJack Pham 2350e780fb31SJack Pham usb_2: usb@a8f8800 { 2351e780fb31SJack Pham compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2352e780fb31SJack Pham reg = <0 0x0a8f8800 0 0x400>; 2353e780fb31SJack Pham status = "disabled"; 2354e780fb31SJack Pham #address-cells = <2>; 2355e780fb31SJack Pham #size-cells = <2>; 2356e780fb31SJack Pham ranges; 2357e780fb31SJack Pham 23586d91e201SVinod Koul clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 23596d91e201SVinod Koul <&gcc GCC_USB30_SEC_MASTER_CLK>, 23606d91e201SVinod Koul <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 23616d91e201SVinod Koul <&gcc GCC_USB30_SEC_SLEEP_CLK>, 23628d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 23636d91e201SVinod Koul <&gcc GCC_USB3_SEC_CLKREF_EN>; 23648d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 23658d5fd4e4SKrzysztof Kozlowski "core", 23668d5fd4e4SKrzysztof Kozlowski "iface", 23678d5fd4e4SKrzysztof Kozlowski "sleep", 23688d5fd4e4SKrzysztof Kozlowski "mock_utmi", 23698d5fd4e4SKrzysztof Kozlowski "xo"; 2370e780fb31SJack Pham 23716d91e201SVinod Koul assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 23726d91e201SVinod Koul <&gcc GCC_USB30_SEC_MASTER_CLK>; 2373e780fb31SJack Pham assigned-clock-rates = <19200000>, <200000000>; 2374e780fb31SJack Pham 2375e780fb31SJack Pham interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 23765b7e3499SJohan Hovold <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2377e780fb31SJack Pham <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 23785b7e3499SJohan Hovold <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 23795b7e3499SJohan Hovold interrupt-names = "hs_phy_irq", 23805b7e3499SJohan Hovold "ss_phy_irq", 23815b7e3499SJohan Hovold "dm_hs_phy_irq", 23825b7e3499SJohan Hovold "dp_hs_phy_irq"; 2383e780fb31SJack Pham 23846d91e201SVinod Koul power-domains = <&gcc USB30_SEC_GDSC>; 2385e780fb31SJack Pham 23866d91e201SVinod Koul resets = <&gcc GCC_USB30_SEC_BCR>; 2387e780fb31SJack Pham 23888b51dc86SAbel Vesa interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 23898b51dc86SAbel Vesa <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 23908b51dc86SAbel Vesa interconnect-names = "usb-ddr", "apps-usb"; 23918b51dc86SAbel Vesa 23922aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 2393e780fb31SJack Pham compatible = "snps,dwc3"; 2394e780fb31SJack Pham reg = <0 0x0a800000 0 0xcd00>; 2395e780fb31SJack Pham interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2396e780fb31SJack Pham iommus = <&apps_smmu 0x20 0x0>; 2397e780fb31SJack Pham snps,dis_u2_susphy_quirk; 2398e780fb31SJack Pham snps,dis_enblslpm_quirk; 2399e780fb31SJack Pham phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2400e780fb31SJack Pham phy-names = "usb2-phy", "usb3-phy"; 2401e780fb31SJack Pham }; 2402e780fb31SJack Pham }; 2403177fcf0aSVinod Koul 2404d4a44105SRobert Foss mdss: display-subsystem@ae00000 { 2405d4a44105SRobert Foss compatible = "qcom,sm8350-mdss"; 2406d4a44105SRobert Foss reg = <0 0x0ae00000 0 0x1000>; 2407d4a44105SRobert Foss reg-names = "mdss"; 2408d4a44105SRobert Foss 2409d4a44105SRobert Foss interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2410d4a44105SRobert Foss <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2411d4a44105SRobert Foss interconnect-names = "mdp0-mem", "mdp1-mem"; 2412d4a44105SRobert Foss 2413d4a44105SRobert Foss power-domains = <&dispcc MDSS_GDSC>; 2414d4a44105SRobert Foss resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2415d4a44105SRobert Foss 2416d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2417d4a44105SRobert Foss <&gcc GCC_DISP_HF_AXI_CLK>, 2418d4a44105SRobert Foss <&gcc GCC_DISP_SF_AXI_CLK>, 2419d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_MDP_CLK>; 2420d4a44105SRobert Foss clock-names = "iface", "bus", "nrt_bus", "core"; 2421d4a44105SRobert Foss 2422d4a44105SRobert Foss interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2423d4a44105SRobert Foss interrupt-controller; 2424d4a44105SRobert Foss #interrupt-cells = <1>; 2425d4a44105SRobert Foss 2426d4a44105SRobert Foss iommus = <&apps_smmu 0x820 0x402>; 2427d4a44105SRobert Foss 2428d4a44105SRobert Foss status = "disabled"; 2429d4a44105SRobert Foss 2430d4a44105SRobert Foss #address-cells = <2>; 2431d4a44105SRobert Foss #size-cells = <2>; 2432d4a44105SRobert Foss ranges; 2433d4a44105SRobert Foss 2434d4a44105SRobert Foss dpu_opp_table: opp-table { 2435d4a44105SRobert Foss compatible = "operating-points-v2"; 2436d4a44105SRobert Foss 2437d4a44105SRobert Foss /* TODO: opp-200000000 should work with 2438d4a44105SRobert Foss * &rpmhpd_opp_low_svs, but one some of 2439d4a44105SRobert Foss * sm8350_hdk boards reboot using this 2440d4a44105SRobert Foss * opp. 2441d4a44105SRobert Foss */ 2442d4a44105SRobert Foss opp-200000000 { 2443d4a44105SRobert Foss opp-hz = /bits/ 64 <200000000>; 2444d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2445d4a44105SRobert Foss }; 2446d4a44105SRobert Foss 2447d4a44105SRobert Foss opp-300000000 { 2448d4a44105SRobert Foss opp-hz = /bits/ 64 <300000000>; 2449d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2450d4a44105SRobert Foss }; 2451d4a44105SRobert Foss 2452d4a44105SRobert Foss opp-345000000 { 2453d4a44105SRobert Foss opp-hz = /bits/ 64 <345000000>; 2454d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs_l1>; 2455d4a44105SRobert Foss }; 2456d4a44105SRobert Foss 2457d4a44105SRobert Foss opp-460000000 { 2458d4a44105SRobert Foss opp-hz = /bits/ 64 <460000000>; 2459d4a44105SRobert Foss required-opps = <&rpmhpd_opp_nom>; 2460d4a44105SRobert Foss }; 2461d4a44105SRobert Foss }; 2462d4a44105SRobert Foss 2463d4a44105SRobert Foss mdss_mdp: display-controller@ae01000 { 2464d4a44105SRobert Foss compatible = "qcom,sm8350-dpu"; 2465d4a44105SRobert Foss reg = <0 0x0ae01000 0 0x8f000>, 2466d4a44105SRobert Foss <0 0x0aeb0000 0 0x2008>; 2467d4a44105SRobert Foss reg-names = "mdp", "vbif"; 2468d4a44105SRobert Foss 2469d4a44105SRobert Foss clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2470d4a44105SRobert Foss <&gcc GCC_DISP_SF_AXI_CLK>, 2471d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_AHB_CLK>, 2472d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2473d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_MDP_CLK>, 2474d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2475d4a44105SRobert Foss clock-names = "bus", 2476d4a44105SRobert Foss "nrt_bus", 2477d4a44105SRobert Foss "iface", 2478d4a44105SRobert Foss "lut", 2479d4a44105SRobert Foss "core", 2480d4a44105SRobert Foss "vsync"; 2481d4a44105SRobert Foss 2482d4a44105SRobert Foss assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2483d4a44105SRobert Foss assigned-clock-rates = <19200000>; 2484d4a44105SRobert Foss 2485d4a44105SRobert Foss operating-points-v2 = <&dpu_opp_table>; 2486d4a44105SRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 2487d4a44105SRobert Foss 2488d4a44105SRobert Foss interrupt-parent = <&mdss>; 2489d4a44105SRobert Foss interrupts = <0>; 2490d4a44105SRobert Foss 2491d4a44105SRobert Foss ports { 2492d4a44105SRobert Foss #address-cells = <1>; 2493d4a44105SRobert Foss #size-cells = <0>; 2494d4a44105SRobert Foss 2495d4a44105SRobert Foss port@0 { 2496d4a44105SRobert Foss reg = <0>; 2497d4a44105SRobert Foss dpu_intf1_out: endpoint { 24982a07efb8SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 2499d4a44105SRobert Foss }; 2500d4a44105SRobert Foss }; 2501b904227aSKonrad Dybcio 2502b904227aSKonrad Dybcio port@1 { 2503b904227aSKonrad Dybcio reg = <1>; 2504b904227aSKonrad Dybcio dpu_intf2_out: endpoint { 2505b904227aSKonrad Dybcio remote-endpoint = <&mdss_dsi1_in>; 2506b904227aSKonrad Dybcio }; 2507b904227aSKonrad Dybcio }; 2508a2802008SNeil Armstrong 2509a2802008SNeil Armstrong port@2 { 2510a2802008SNeil Armstrong reg = <2>; 2511a2802008SNeil Armstrong dpu_intf0_out: endpoint { 2512a2802008SNeil Armstrong remote-endpoint = <&mdss_dp_in>; 2513a2802008SNeil Armstrong }; 2514a2802008SNeil Armstrong }; 2515a2802008SNeil Armstrong }; 2516a2802008SNeil Armstrong }; 2517a2802008SNeil Armstrong 2518a2802008SNeil Armstrong mdss_dp: displayport-controller@ae90000 { 2519a2802008SNeil Armstrong compatible = "qcom,sm8350-dp"; 2520a2802008SNeil Armstrong reg = <0 0xae90000 0 0x200>, 2521a2802008SNeil Armstrong <0 0xae90200 0 0x200>, 2522a2802008SNeil Armstrong <0 0xae90400 0 0x600>, 2523a2802008SNeil Armstrong <0 0xae91000 0 0x400>, 2524a2802008SNeil Armstrong <0 0xae91400 0 0x400>; 2525a2802008SNeil Armstrong interrupt-parent = <&mdss>; 2526a2802008SNeil Armstrong interrupts = <12>; 2527a2802008SNeil Armstrong clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2528a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2529a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2530a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2531a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2532a2802008SNeil Armstrong clock-names = "core_iface", 2533a2802008SNeil Armstrong "core_aux", 2534a2802008SNeil Armstrong "ctrl_link", 2535a2802008SNeil Armstrong "ctrl_link_iface", 2536a2802008SNeil Armstrong "stream_pixel"; 2537a2802008SNeil Armstrong 2538a2802008SNeil Armstrong assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2539a2802008SNeil Armstrong <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2540a2802008SNeil Armstrong assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2541a2802008SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2542a2802008SNeil Armstrong 2543a2802008SNeil Armstrong phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2544a2802008SNeil Armstrong phy-names = "dp"; 2545a2802008SNeil Armstrong 2546a2802008SNeil Armstrong #sound-dai-cells = <0>; 2547a2802008SNeil Armstrong 2548a2802008SNeil Armstrong operating-points-v2 = <&dp_opp_table>; 2549a2802008SNeil Armstrong power-domains = <&rpmhpd SM8350_MMCX>; 2550a2802008SNeil Armstrong 2551a2802008SNeil Armstrong status = "disabled"; 2552a2802008SNeil Armstrong 2553a2802008SNeil Armstrong ports { 2554a2802008SNeil Armstrong #address-cells = <1>; 2555a2802008SNeil Armstrong #size-cells = <0>; 2556a2802008SNeil Armstrong 2557a2802008SNeil Armstrong port@0 { 2558a2802008SNeil Armstrong reg = <0>; 2559a2802008SNeil Armstrong mdss_dp_in: endpoint { 2560a2802008SNeil Armstrong remote-endpoint = <&dpu_intf0_out>; 2561a2802008SNeil Armstrong }; 2562a2802008SNeil Armstrong }; 2563a2802008SNeil Armstrong }; 2564a2802008SNeil Armstrong 2565a2802008SNeil Armstrong dp_opp_table: opp-table { 2566a2802008SNeil Armstrong compatible = "operating-points-v2"; 2567a2802008SNeil Armstrong 2568a2802008SNeil Armstrong opp-160000000 { 2569a2802008SNeil Armstrong opp-hz = /bits/ 64 <160000000>; 2570a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_low_svs>; 2571a2802008SNeil Armstrong }; 2572a2802008SNeil Armstrong 2573a2802008SNeil Armstrong opp-270000000 { 2574a2802008SNeil Armstrong opp-hz = /bits/ 64 <270000000>; 2575a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_svs>; 2576a2802008SNeil Armstrong }; 2577a2802008SNeil Armstrong 2578a2802008SNeil Armstrong opp-540000000 { 2579a2802008SNeil Armstrong opp-hz = /bits/ 64 <540000000>; 2580a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_svs_l1>; 2581a2802008SNeil Armstrong }; 2582a2802008SNeil Armstrong 2583a2802008SNeil Armstrong opp-810000000 { 2584a2802008SNeil Armstrong opp-hz = /bits/ 64 <810000000>; 2585a2802008SNeil Armstrong required-opps = <&rpmhpd_opp_nom>; 2586a2802008SNeil Armstrong }; 2587d4a44105SRobert Foss }; 2588d4a44105SRobert Foss }; 2589d4a44105SRobert Foss 2590d4a44105SRobert Foss mdss_dsi0: dsi@ae94000 { 2591d7133d6dSDmitry Baryshkov compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2592d4a44105SRobert Foss reg = <0 0x0ae94000 0 0x400>; 2593d4a44105SRobert Foss reg-names = "dsi_ctrl"; 2594d4a44105SRobert Foss 2595d4a44105SRobert Foss interrupt-parent = <&mdss>; 2596d4a44105SRobert Foss interrupts = <4>; 2597d4a44105SRobert Foss 2598d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2599d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2600d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2601d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2602d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_AHB_CLK>, 2603d4a44105SRobert Foss <&gcc GCC_DISP_HF_AXI_CLK>; 2604d4a44105SRobert Foss clock-names = "byte", 2605d4a44105SRobert Foss "byte_intf", 2606d4a44105SRobert Foss "pixel", 2607d4a44105SRobert Foss "core", 2608d4a44105SRobert Foss "iface", 2609d4a44105SRobert Foss "bus"; 2610d4a44105SRobert Foss 2611d4a44105SRobert Foss assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2612d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2613d4a44105SRobert Foss assigned-clock-parents = <&mdss_dsi0_phy 0>, 2614d4a44105SRobert Foss <&mdss_dsi0_phy 1>; 2615d4a44105SRobert Foss 2616d4a44105SRobert Foss operating-points-v2 = <&dsi0_opp_table>; 2617d4a44105SRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 2618d4a44105SRobert Foss 2619d4a44105SRobert Foss phys = <&mdss_dsi0_phy>; 2620d4a44105SRobert Foss 26216636818eSKonrad Dybcio #address-cells = <1>; 26226636818eSKonrad Dybcio #size-cells = <0>; 26236636818eSKonrad Dybcio 2624d4a44105SRobert Foss status = "disabled"; 2625d4a44105SRobert Foss 2626d4a44105SRobert Foss dsi0_opp_table: opp-table { 2627d4a44105SRobert Foss compatible = "operating-points-v2"; 2628d4a44105SRobert Foss 2629d4a44105SRobert Foss /* TODO: opp-187500000 should work with 2630d4a44105SRobert Foss * &rpmhpd_opp_low_svs, but one some of 2631d4a44105SRobert Foss * sm8350_hdk boards reboot using this 2632d4a44105SRobert Foss * opp. 2633d4a44105SRobert Foss */ 2634d4a44105SRobert Foss opp-187500000 { 2635d4a44105SRobert Foss opp-hz = /bits/ 64 <187500000>; 2636d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2637d4a44105SRobert Foss }; 2638d4a44105SRobert Foss 2639d4a44105SRobert Foss opp-300000000 { 2640d4a44105SRobert Foss opp-hz = /bits/ 64 <300000000>; 2641d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2642d4a44105SRobert Foss }; 2643d4a44105SRobert Foss 2644d4a44105SRobert Foss opp-358000000 { 2645d4a44105SRobert Foss opp-hz = /bits/ 64 <358000000>; 2646d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs_l1>; 2647d4a44105SRobert Foss }; 2648d4a44105SRobert Foss }; 2649d4a44105SRobert Foss 2650d4a44105SRobert Foss ports { 2651d4a44105SRobert Foss #address-cells = <1>; 2652d4a44105SRobert Foss #size-cells = <0>; 2653d4a44105SRobert Foss 2654d4a44105SRobert Foss port@0 { 2655d4a44105SRobert Foss reg = <0>; 26562a07efb8SKonrad Dybcio mdss_dsi0_in: endpoint { 2657d4a44105SRobert Foss remote-endpoint = <&dpu_intf1_out>; 2658d4a44105SRobert Foss }; 2659d4a44105SRobert Foss }; 2660d4a44105SRobert Foss 2661d4a44105SRobert Foss port@1 { 2662d4a44105SRobert Foss reg = <1>; 26632a07efb8SKonrad Dybcio mdss_dsi0_out: endpoint { 2664d4a44105SRobert Foss }; 2665d4a44105SRobert Foss }; 2666d4a44105SRobert Foss }; 2667d4a44105SRobert Foss }; 2668d4a44105SRobert Foss 2669d4a44105SRobert Foss mdss_dsi0_phy: phy@ae94400 { 267045cd807dSKonrad Dybcio compatible = "qcom,sm8350-dsi-phy-5nm"; 2671d4a44105SRobert Foss reg = <0 0x0ae94400 0 0x200>, 2672d4a44105SRobert Foss <0 0x0ae94600 0 0x280>, 2673e3e654ceSKonrad Dybcio <0 0x0ae94900 0 0x27c>; 2674d4a44105SRobert Foss reg-names = "dsi_phy", 2675d4a44105SRobert Foss "dsi_phy_lane", 2676d4a44105SRobert Foss "dsi_pll"; 2677d4a44105SRobert Foss 2678d4a44105SRobert Foss #clock-cells = <1>; 2679d4a44105SRobert Foss #phy-cells = <0>; 2680d4a44105SRobert Foss 2681d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2682d4a44105SRobert Foss <&rpmhcc RPMH_CXO_CLK>; 2683d4a44105SRobert Foss clock-names = "iface", "ref"; 2684d4a44105SRobert Foss 2685d4a44105SRobert Foss status = "disabled"; 2686d4a44105SRobert Foss }; 2687d4a44105SRobert Foss 2688d4a44105SRobert Foss mdss_dsi1: dsi@ae96000 { 2689d7133d6dSDmitry Baryshkov compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2690d4a44105SRobert Foss reg = <0 0x0ae96000 0 0x400>; 2691d4a44105SRobert Foss reg-names = "dsi_ctrl"; 2692d4a44105SRobert Foss 2693d4a44105SRobert Foss interrupt-parent = <&mdss>; 26941eed7995SKonrad Dybcio interrupts = <5>; 2695d4a44105SRobert Foss 2696d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2697d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2698d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2699d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2700d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_AHB_CLK>, 2701d4a44105SRobert Foss <&gcc GCC_DISP_HF_AXI_CLK>; 2702d4a44105SRobert Foss clock-names = "byte", 2703d4a44105SRobert Foss "byte_intf", 2704d4a44105SRobert Foss "pixel", 2705d4a44105SRobert Foss "core", 2706d4a44105SRobert Foss "iface", 2707d4a44105SRobert Foss "bus"; 2708d4a44105SRobert Foss 2709d4a44105SRobert Foss assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2710d4a44105SRobert Foss <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2711d4a44105SRobert Foss assigned-clock-parents = <&mdss_dsi1_phy 0>, 2712d4a44105SRobert Foss <&mdss_dsi1_phy 1>; 2713d4a44105SRobert Foss 2714d4a44105SRobert Foss operating-points-v2 = <&dsi1_opp_table>; 2715d4a44105SRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 2716d4a44105SRobert Foss 2717d4a44105SRobert Foss phys = <&mdss_dsi1_phy>; 2718d4a44105SRobert Foss 27196636818eSKonrad Dybcio #address-cells = <1>; 27206636818eSKonrad Dybcio #size-cells = <0>; 27216636818eSKonrad Dybcio 2722d4a44105SRobert Foss status = "disabled"; 2723d4a44105SRobert Foss 2724d4a44105SRobert Foss dsi1_opp_table: opp-table { 2725d4a44105SRobert Foss compatible = "operating-points-v2"; 2726d4a44105SRobert Foss 2727d4a44105SRobert Foss /* TODO: opp-187500000 should work with 2728d4a44105SRobert Foss * &rpmhpd_opp_low_svs, but one some of 2729d4a44105SRobert Foss * sm8350_hdk boards reboot using this 2730d4a44105SRobert Foss * opp. 2731d4a44105SRobert Foss */ 2732d4a44105SRobert Foss opp-187500000 { 2733d4a44105SRobert Foss opp-hz = /bits/ 64 <187500000>; 2734d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2735d4a44105SRobert Foss }; 2736d4a44105SRobert Foss 2737d4a44105SRobert Foss opp-300000000 { 2738d4a44105SRobert Foss opp-hz = /bits/ 64 <300000000>; 2739d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs>; 2740d4a44105SRobert Foss }; 2741d4a44105SRobert Foss 2742d4a44105SRobert Foss opp-358000000 { 2743d4a44105SRobert Foss opp-hz = /bits/ 64 <358000000>; 2744d4a44105SRobert Foss required-opps = <&rpmhpd_opp_svs_l1>; 2745d4a44105SRobert Foss }; 2746d4a44105SRobert Foss }; 2747d4a44105SRobert Foss 2748d4a44105SRobert Foss ports { 2749d4a44105SRobert Foss #address-cells = <1>; 2750d4a44105SRobert Foss #size-cells = <0>; 2751d4a44105SRobert Foss 2752d4a44105SRobert Foss port@0 { 2753d4a44105SRobert Foss reg = <0>; 27542a07efb8SKonrad Dybcio mdss_dsi1_in: endpoint { 2755b904227aSKonrad Dybcio remote-endpoint = <&dpu_intf2_out>; 2756d4a44105SRobert Foss }; 2757d4a44105SRobert Foss }; 2758d4a44105SRobert Foss 2759d4a44105SRobert Foss port@1 { 2760d4a44105SRobert Foss reg = <1>; 27612a07efb8SKonrad Dybcio mdss_dsi1_out: endpoint { 2762d4a44105SRobert Foss }; 2763d4a44105SRobert Foss }; 2764d4a44105SRobert Foss }; 2765d4a44105SRobert Foss }; 2766d4a44105SRobert Foss 2767d4a44105SRobert Foss mdss_dsi1_phy: phy@ae96400 { 276845cd807dSKonrad Dybcio compatible = "qcom,sm8350-dsi-phy-5nm"; 2769d4a44105SRobert Foss reg = <0 0x0ae96400 0 0x200>, 2770d4a44105SRobert Foss <0 0x0ae96600 0 0x280>, 2771e3e654ceSKonrad Dybcio <0 0x0ae96900 0 0x27c>; 2772d4a44105SRobert Foss reg-names = "dsi_phy", 2773d4a44105SRobert Foss "dsi_phy_lane", 2774d4a44105SRobert Foss "dsi_pll"; 2775d4a44105SRobert Foss 2776d4a44105SRobert Foss #clock-cells = <1>; 2777d4a44105SRobert Foss #phy-cells = <0>; 2778d4a44105SRobert Foss 2779d4a44105SRobert Foss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2780d4a44105SRobert Foss <&rpmhcc RPMH_CXO_CLK>; 2781d4a44105SRobert Foss clock-names = "iface", "ref"; 2782d4a44105SRobert Foss 2783d4a44105SRobert Foss status = "disabled"; 2784d4a44105SRobert Foss }; 2785d4a44105SRobert Foss }; 2786d4a44105SRobert Foss 27879fd4887cSRobert Foss dispcc: clock-controller@af00000 { 27889fd4887cSRobert Foss compatible = "qcom,sm8350-dispcc"; 27899fd4887cSRobert Foss reg = <0 0x0af00000 0 0x10000>; 27909fd4887cSRobert Foss clocks = <&rpmhcc RPMH_CXO_CLK>, 2791d4a44105SRobert Foss <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 27920af6a401SKonrad Dybcio <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 27932458a305SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 27942458a305SNeil Armstrong <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 27959fd4887cSRobert Foss clock-names = "bi_tcxo", 27969fd4887cSRobert Foss "dsi0_phy_pll_out_byteclk", 27979fd4887cSRobert Foss "dsi0_phy_pll_out_dsiclk", 27989fd4887cSRobert Foss "dsi1_phy_pll_out_byteclk", 27999fd4887cSRobert Foss "dsi1_phy_pll_out_dsiclk", 28009fd4887cSRobert Foss "dp_phy_pll_link_clk", 28019fd4887cSRobert Foss "dp_phy_pll_vco_div_clk"; 28029fd4887cSRobert Foss #clock-cells = <1>; 28039fd4887cSRobert Foss #reset-cells = <1>; 28049fd4887cSRobert Foss #power-domain-cells = <1>; 28059fd4887cSRobert Foss 28069fd4887cSRobert Foss power-domains = <&rpmhpd SM8350_MMCX>; 28079fd4887cSRobert Foss }; 28089fd4887cSRobert Foss 280951f83fbbSDmitry Baryshkov pdc: interrupt-controller@b220000 { 281051f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-pdc", "qcom,pdc"; 281151f83fbbSDmitry Baryshkov reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 281251f83fbbSDmitry Baryshkov qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 281351f83fbbSDmitry Baryshkov <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 281451f83fbbSDmitry Baryshkov <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 281551f83fbbSDmitry Baryshkov <156 716 12>; 281651f83fbbSDmitry Baryshkov #interrupt-cells = <2>; 281751f83fbbSDmitry Baryshkov interrupt-parent = <&intc>; 281851f83fbbSDmitry Baryshkov interrupt-controller; 281951f83fbbSDmitry Baryshkov }; 282051f83fbbSDmitry Baryshkov 282151f83fbbSDmitry Baryshkov tsens0: thermal-sensor@c263000 { 282251f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 282351f83fbbSDmitry Baryshkov reg = <0 0x0c263000 0 0x1ff>, /* TM */ 282451f83fbbSDmitry Baryshkov <0 0x0c222000 0 0x8>; /* SROT */ 282551f83fbbSDmitry Baryshkov #qcom,sensors = <15>; 282651f83fbbSDmitry Baryshkov interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 282751f83fbbSDmitry Baryshkov <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 282851f83fbbSDmitry Baryshkov interrupt-names = "uplow", "critical"; 282951f83fbbSDmitry Baryshkov #thermal-sensor-cells = <1>; 283051f83fbbSDmitry Baryshkov }; 283151f83fbbSDmitry Baryshkov 283251f83fbbSDmitry Baryshkov tsens1: thermal-sensor@c265000 { 283351f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 283451f83fbbSDmitry Baryshkov reg = <0 0x0c265000 0 0x1ff>, /* TM */ 283551f83fbbSDmitry Baryshkov <0 0x0c223000 0 0x8>; /* SROT */ 283651f83fbbSDmitry Baryshkov #qcom,sensors = <14>; 283751f83fbbSDmitry Baryshkov interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 283851f83fbbSDmitry Baryshkov <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 283951f83fbbSDmitry Baryshkov interrupt-names = "uplow", "critical"; 284051f83fbbSDmitry Baryshkov #thermal-sensor-cells = <1>; 284151f83fbbSDmitry Baryshkov }; 284251f83fbbSDmitry Baryshkov 284351f83fbbSDmitry Baryshkov aoss_qmp: power-management@c300000 { 284451f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 284551f83fbbSDmitry Baryshkov reg = <0 0x0c300000 0 0x400>; 284651f83fbbSDmitry Baryshkov interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 284751f83fbbSDmitry Baryshkov IRQ_TYPE_EDGE_RISING>; 284851f83fbbSDmitry Baryshkov mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 284951f83fbbSDmitry Baryshkov 285051f83fbbSDmitry Baryshkov #clock-cells = <0>; 285151f83fbbSDmitry Baryshkov }; 285251f83fbbSDmitry Baryshkov 285351f83fbbSDmitry Baryshkov sram@c3f0000 { 285451f83fbbSDmitry Baryshkov compatible = "qcom,rpmh-stats"; 285551f83fbbSDmitry Baryshkov reg = <0 0x0c3f0000 0 0x400>; 285651f83fbbSDmitry Baryshkov }; 285751f83fbbSDmitry Baryshkov 285851f83fbbSDmitry Baryshkov spmi_bus: spmi@c440000 { 285951f83fbbSDmitry Baryshkov compatible = "qcom,spmi-pmic-arb"; 286051f83fbbSDmitry Baryshkov reg = <0x0 0x0c440000 0x0 0x1100>, 286151f83fbbSDmitry Baryshkov <0x0 0x0c600000 0x0 0x2000000>, 286251f83fbbSDmitry Baryshkov <0x0 0x0e600000 0x0 0x100000>, 286351f83fbbSDmitry Baryshkov <0x0 0x0e700000 0x0 0xa0000>, 286451f83fbbSDmitry Baryshkov <0x0 0x0c40a000 0x0 0x26000>; 286551f83fbbSDmitry Baryshkov reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 286651f83fbbSDmitry Baryshkov interrupt-names = "periph_irq"; 286751f83fbbSDmitry Baryshkov interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 286851f83fbbSDmitry Baryshkov qcom,ee = <0>; 286951f83fbbSDmitry Baryshkov qcom,channel = <0>; 287051f83fbbSDmitry Baryshkov #address-cells = <2>; 287151f83fbbSDmitry Baryshkov #size-cells = <0>; 287251f83fbbSDmitry Baryshkov interrupt-controller; 287351f83fbbSDmitry Baryshkov #interrupt-cells = <4>; 287451f83fbbSDmitry Baryshkov }; 287551f83fbbSDmitry Baryshkov 287651f83fbbSDmitry Baryshkov tlmm: pinctrl@f100000 { 287751f83fbbSDmitry Baryshkov compatible = "qcom,sm8350-tlmm"; 287851f83fbbSDmitry Baryshkov reg = <0 0x0f100000 0 0x300000>; 287951f83fbbSDmitry Baryshkov interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 288051f83fbbSDmitry Baryshkov gpio-controller; 288151f83fbbSDmitry Baryshkov #gpio-cells = <2>; 288251f83fbbSDmitry Baryshkov interrupt-controller; 288351f83fbbSDmitry Baryshkov #interrupt-cells = <2>; 288451f83fbbSDmitry Baryshkov gpio-ranges = <&tlmm 0 0 204>; 288551f83fbbSDmitry Baryshkov wakeup-parent = <&pdc>; 288651f83fbbSDmitry Baryshkov 288751f83fbbSDmitry Baryshkov sdc2_default_state: sdc2-default-state { 288851f83fbbSDmitry Baryshkov clk-pins { 288951f83fbbSDmitry Baryshkov pins = "sdc2_clk"; 289051f83fbbSDmitry Baryshkov drive-strength = <16>; 289151f83fbbSDmitry Baryshkov bias-disable; 289251f83fbbSDmitry Baryshkov }; 289351f83fbbSDmitry Baryshkov 289451f83fbbSDmitry Baryshkov cmd-pins { 289551f83fbbSDmitry Baryshkov pins = "sdc2_cmd"; 289651f83fbbSDmitry Baryshkov drive-strength = <16>; 289751f83fbbSDmitry Baryshkov bias-pull-up; 289851f83fbbSDmitry Baryshkov }; 289951f83fbbSDmitry Baryshkov 290051f83fbbSDmitry Baryshkov data-pins { 290151f83fbbSDmitry Baryshkov pins = "sdc2_data"; 290251f83fbbSDmitry Baryshkov drive-strength = <16>; 290351f83fbbSDmitry Baryshkov bias-pull-up; 290451f83fbbSDmitry Baryshkov }; 290551f83fbbSDmitry Baryshkov }; 290651f83fbbSDmitry Baryshkov 290751f83fbbSDmitry Baryshkov sdc2_sleep_state: sdc2-sleep-state { 290851f83fbbSDmitry Baryshkov clk-pins { 290951f83fbbSDmitry Baryshkov pins = "sdc2_clk"; 291051f83fbbSDmitry Baryshkov drive-strength = <2>; 291151f83fbbSDmitry Baryshkov bias-disable; 291251f83fbbSDmitry Baryshkov }; 291351f83fbbSDmitry Baryshkov 291451f83fbbSDmitry Baryshkov cmd-pins { 291551f83fbbSDmitry Baryshkov pins = "sdc2_cmd"; 291651f83fbbSDmitry Baryshkov drive-strength = <2>; 291751f83fbbSDmitry Baryshkov bias-pull-up; 291851f83fbbSDmitry Baryshkov }; 291951f83fbbSDmitry Baryshkov 292051f83fbbSDmitry Baryshkov data-pins { 292151f83fbbSDmitry Baryshkov pins = "sdc2_data"; 292251f83fbbSDmitry Baryshkov drive-strength = <2>; 292351f83fbbSDmitry Baryshkov bias-pull-up; 292451f83fbbSDmitry Baryshkov }; 292551f83fbbSDmitry Baryshkov }; 292651f83fbbSDmitry Baryshkov 292751f83fbbSDmitry Baryshkov qup_uart3_default_state: qup-uart3-default-state { 292851f83fbbSDmitry Baryshkov rx-pins { 292951f83fbbSDmitry Baryshkov pins = "gpio18"; 293051f83fbbSDmitry Baryshkov function = "qup3"; 293151f83fbbSDmitry Baryshkov }; 293251f83fbbSDmitry Baryshkov tx-pins { 293351f83fbbSDmitry Baryshkov pins = "gpio19"; 293451f83fbbSDmitry Baryshkov function = "qup3"; 293551f83fbbSDmitry Baryshkov }; 293651f83fbbSDmitry Baryshkov }; 293751f83fbbSDmitry Baryshkov 293851f83fbbSDmitry Baryshkov qup_uart6_default: qup-uart6-default-state { 293951f83fbbSDmitry Baryshkov pins = "gpio30", "gpio31"; 294051f83fbbSDmitry Baryshkov function = "qup6"; 294151f83fbbSDmitry Baryshkov drive-strength = <2>; 294251f83fbbSDmitry Baryshkov bias-disable; 294351f83fbbSDmitry Baryshkov }; 294451f83fbbSDmitry Baryshkov 294551f83fbbSDmitry Baryshkov qup_uart18_default: qup-uart18-default-state { 294651f83fbbSDmitry Baryshkov pins = "gpio58", "gpio59"; 294751f83fbbSDmitry Baryshkov function = "qup18"; 294851f83fbbSDmitry Baryshkov drive-strength = <2>; 294951f83fbbSDmitry Baryshkov bias-disable; 295051f83fbbSDmitry Baryshkov }; 295151f83fbbSDmitry Baryshkov 295251f83fbbSDmitry Baryshkov qup_i2c0_default: qup-i2c0-default-state { 295351f83fbbSDmitry Baryshkov pins = "gpio4", "gpio5"; 295451f83fbbSDmitry Baryshkov function = "qup0"; 295551f83fbbSDmitry Baryshkov drive-strength = <2>; 295651f83fbbSDmitry Baryshkov bias-pull-up; 295751f83fbbSDmitry Baryshkov }; 295851f83fbbSDmitry Baryshkov 295951f83fbbSDmitry Baryshkov qup_i2c1_default: qup-i2c1-default-state { 296051f83fbbSDmitry Baryshkov pins = "gpio8", "gpio9"; 296151f83fbbSDmitry Baryshkov function = "qup1"; 296251f83fbbSDmitry Baryshkov drive-strength = <2>; 296351f83fbbSDmitry Baryshkov bias-pull-up; 296451f83fbbSDmitry Baryshkov }; 296551f83fbbSDmitry Baryshkov 296651f83fbbSDmitry Baryshkov qup_i2c2_default: qup-i2c2-default-state { 296751f83fbbSDmitry Baryshkov pins = "gpio12", "gpio13"; 296851f83fbbSDmitry Baryshkov function = "qup2"; 296951f83fbbSDmitry Baryshkov drive-strength = <2>; 297051f83fbbSDmitry Baryshkov bias-pull-up; 297151f83fbbSDmitry Baryshkov }; 297251f83fbbSDmitry Baryshkov 297351f83fbbSDmitry Baryshkov qup_i2c4_default: qup-i2c4-default-state { 297451f83fbbSDmitry Baryshkov pins = "gpio20", "gpio21"; 297551f83fbbSDmitry Baryshkov function = "qup4"; 297651f83fbbSDmitry Baryshkov drive-strength = <2>; 297751f83fbbSDmitry Baryshkov bias-pull-up; 297851f83fbbSDmitry Baryshkov }; 297951f83fbbSDmitry Baryshkov 298051f83fbbSDmitry Baryshkov qup_i2c5_default: qup-i2c5-default-state { 298151f83fbbSDmitry Baryshkov pins = "gpio24", "gpio25"; 298251f83fbbSDmitry Baryshkov function = "qup5"; 298351f83fbbSDmitry Baryshkov drive-strength = <2>; 298451f83fbbSDmitry Baryshkov bias-pull-up; 298551f83fbbSDmitry Baryshkov }; 298651f83fbbSDmitry Baryshkov 298751f83fbbSDmitry Baryshkov qup_i2c6_default: qup-i2c6-default-state { 298851f83fbbSDmitry Baryshkov pins = "gpio28", "gpio29"; 298951f83fbbSDmitry Baryshkov function = "qup6"; 299051f83fbbSDmitry Baryshkov drive-strength = <2>; 299151f83fbbSDmitry Baryshkov bias-pull-up; 299251f83fbbSDmitry Baryshkov }; 299351f83fbbSDmitry Baryshkov 299451f83fbbSDmitry Baryshkov qup_i2c7_default: qup-i2c7-default-state { 299551f83fbbSDmitry Baryshkov pins = "gpio32", "gpio33"; 299651f83fbbSDmitry Baryshkov function = "qup7"; 299751f83fbbSDmitry Baryshkov drive-strength = <2>; 299851f83fbbSDmitry Baryshkov bias-disable; 299951f83fbbSDmitry Baryshkov }; 300051f83fbbSDmitry Baryshkov 300151f83fbbSDmitry Baryshkov qup_i2c8_default: qup-i2c8-default-state { 300251f83fbbSDmitry Baryshkov pins = "gpio36", "gpio37"; 300351f83fbbSDmitry Baryshkov function = "qup8"; 300451f83fbbSDmitry Baryshkov drive-strength = <2>; 300551f83fbbSDmitry Baryshkov bias-pull-up; 300651f83fbbSDmitry Baryshkov }; 300751f83fbbSDmitry Baryshkov 300851f83fbbSDmitry Baryshkov qup_i2c9_default: qup-i2c9-default-state { 300951f83fbbSDmitry Baryshkov pins = "gpio40", "gpio41"; 301051f83fbbSDmitry Baryshkov function = "qup9"; 301151f83fbbSDmitry Baryshkov drive-strength = <2>; 301251f83fbbSDmitry Baryshkov bias-pull-up; 301351f83fbbSDmitry Baryshkov }; 301451f83fbbSDmitry Baryshkov 301551f83fbbSDmitry Baryshkov qup_i2c10_default: qup-i2c10-default-state { 301651f83fbbSDmitry Baryshkov pins = "gpio44", "gpio45"; 301751f83fbbSDmitry Baryshkov function = "qup10"; 301851f83fbbSDmitry Baryshkov drive-strength = <2>; 301951f83fbbSDmitry Baryshkov bias-pull-up; 302051f83fbbSDmitry Baryshkov }; 302151f83fbbSDmitry Baryshkov 302251f83fbbSDmitry Baryshkov qup_i2c11_default: qup-i2c11-default-state { 302351f83fbbSDmitry Baryshkov pins = "gpio48", "gpio49"; 302451f83fbbSDmitry Baryshkov function = "qup11"; 302551f83fbbSDmitry Baryshkov drive-strength = <2>; 302651f83fbbSDmitry Baryshkov bias-pull-up; 302751f83fbbSDmitry Baryshkov }; 302851f83fbbSDmitry Baryshkov 302951f83fbbSDmitry Baryshkov qup_i2c12_default: qup-i2c12-default-state { 303051f83fbbSDmitry Baryshkov pins = "gpio52", "gpio53"; 303151f83fbbSDmitry Baryshkov function = "qup12"; 303251f83fbbSDmitry Baryshkov drive-strength = <2>; 303351f83fbbSDmitry Baryshkov bias-pull-up; 303451f83fbbSDmitry Baryshkov }; 303551f83fbbSDmitry Baryshkov 303651f83fbbSDmitry Baryshkov qup_i2c13_default: qup-i2c13-default-state { 303751f83fbbSDmitry Baryshkov pins = "gpio0", "gpio1"; 303851f83fbbSDmitry Baryshkov function = "qup13"; 303951f83fbbSDmitry Baryshkov drive-strength = <2>; 304051f83fbbSDmitry Baryshkov bias-pull-up; 304151f83fbbSDmitry Baryshkov }; 304251f83fbbSDmitry Baryshkov 304351f83fbbSDmitry Baryshkov qup_i2c14_default: qup-i2c14-default-state { 304451f83fbbSDmitry Baryshkov pins = "gpio56", "gpio57"; 304551f83fbbSDmitry Baryshkov function = "qup14"; 304651f83fbbSDmitry Baryshkov drive-strength = <2>; 304751f83fbbSDmitry Baryshkov bias-disable; 304851f83fbbSDmitry Baryshkov }; 304951f83fbbSDmitry Baryshkov 305051f83fbbSDmitry Baryshkov qup_i2c15_default: qup-i2c15-default-state { 305151f83fbbSDmitry Baryshkov pins = "gpio60", "gpio61"; 305251f83fbbSDmitry Baryshkov function = "qup15"; 305351f83fbbSDmitry Baryshkov drive-strength = <2>; 305451f83fbbSDmitry Baryshkov bias-disable; 305551f83fbbSDmitry Baryshkov }; 305651f83fbbSDmitry Baryshkov 305751f83fbbSDmitry Baryshkov qup_i2c16_default: qup-i2c16-default-state { 305851f83fbbSDmitry Baryshkov pins = "gpio64", "gpio65"; 305951f83fbbSDmitry Baryshkov function = "qup16"; 306051f83fbbSDmitry Baryshkov drive-strength = <2>; 306151f83fbbSDmitry Baryshkov bias-disable; 306251f83fbbSDmitry Baryshkov }; 306351f83fbbSDmitry Baryshkov 306451f83fbbSDmitry Baryshkov qup_i2c17_default: qup-i2c17-default-state { 306551f83fbbSDmitry Baryshkov pins = "gpio72", "gpio73"; 306651f83fbbSDmitry Baryshkov function = "qup17"; 306751f83fbbSDmitry Baryshkov drive-strength = <2>; 306851f83fbbSDmitry Baryshkov bias-disable; 306951f83fbbSDmitry Baryshkov }; 307051f83fbbSDmitry Baryshkov 307151f83fbbSDmitry Baryshkov qup_i2c19_default: qup-i2c19-default-state { 307251f83fbbSDmitry Baryshkov pins = "gpio76", "gpio77"; 307351f83fbbSDmitry Baryshkov function = "qup19"; 307451f83fbbSDmitry Baryshkov drive-strength = <2>; 307551f83fbbSDmitry Baryshkov bias-disable; 307651f83fbbSDmitry Baryshkov }; 307751f83fbbSDmitry Baryshkov }; 307851f83fbbSDmitry Baryshkov 3079f5f6bd58SDmitry Baryshkov apps_smmu: iommu@15000000 { 3080f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3081f5f6bd58SDmitry Baryshkov reg = <0 0x15000000 0 0x100000>; 3082f5f6bd58SDmitry Baryshkov #iommu-cells = <2>; 3083f5f6bd58SDmitry Baryshkov #global-interrupts = <2>; 3084f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3085f5f6bd58SDmitry Baryshkov <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3086f5f6bd58SDmitry Baryshkov <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3087f5f6bd58SDmitry Baryshkov <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3088f5f6bd58SDmitry Baryshkov <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3089f5f6bd58SDmitry Baryshkov <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3090f5f6bd58SDmitry Baryshkov <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3091f5f6bd58SDmitry Baryshkov <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3092f5f6bd58SDmitry Baryshkov <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3093f5f6bd58SDmitry Baryshkov <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3094f5f6bd58SDmitry Baryshkov <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3095f5f6bd58SDmitry Baryshkov <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3096f5f6bd58SDmitry Baryshkov <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3097f5f6bd58SDmitry Baryshkov <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3098f5f6bd58SDmitry Baryshkov <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3099f5f6bd58SDmitry Baryshkov <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3100f5f6bd58SDmitry Baryshkov <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3101f5f6bd58SDmitry Baryshkov <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3102f5f6bd58SDmitry Baryshkov <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3103f5f6bd58SDmitry Baryshkov <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3104f5f6bd58SDmitry Baryshkov <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3105f5f6bd58SDmitry Baryshkov <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3106f5f6bd58SDmitry Baryshkov <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3107f5f6bd58SDmitry Baryshkov <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3108f5f6bd58SDmitry Baryshkov <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3109f5f6bd58SDmitry Baryshkov <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3110f5f6bd58SDmitry Baryshkov <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3111f5f6bd58SDmitry Baryshkov <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3112f5f6bd58SDmitry Baryshkov <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3113f5f6bd58SDmitry Baryshkov <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3114f5f6bd58SDmitry Baryshkov <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3115f5f6bd58SDmitry Baryshkov <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3116f5f6bd58SDmitry Baryshkov <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3117f5f6bd58SDmitry Baryshkov <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3118f5f6bd58SDmitry Baryshkov <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3119f5f6bd58SDmitry Baryshkov <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3120f5f6bd58SDmitry Baryshkov <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3121f5f6bd58SDmitry Baryshkov <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3122f5f6bd58SDmitry Baryshkov <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3123f5f6bd58SDmitry Baryshkov <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3124f5f6bd58SDmitry Baryshkov <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3125f5f6bd58SDmitry Baryshkov <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3126f5f6bd58SDmitry Baryshkov <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3127f5f6bd58SDmitry Baryshkov <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3128f5f6bd58SDmitry Baryshkov <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3129f5f6bd58SDmitry Baryshkov <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3130f5f6bd58SDmitry Baryshkov <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3131f5f6bd58SDmitry Baryshkov <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3132f5f6bd58SDmitry Baryshkov <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3133f5f6bd58SDmitry Baryshkov <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3134f5f6bd58SDmitry Baryshkov <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3135f5f6bd58SDmitry Baryshkov <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3136f5f6bd58SDmitry Baryshkov <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3137f5f6bd58SDmitry Baryshkov <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3138f5f6bd58SDmitry Baryshkov <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3139f5f6bd58SDmitry Baryshkov <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3140f5f6bd58SDmitry Baryshkov <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3141f5f6bd58SDmitry Baryshkov <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3142f5f6bd58SDmitry Baryshkov <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3143f5f6bd58SDmitry Baryshkov <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3144f5f6bd58SDmitry Baryshkov <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3145f5f6bd58SDmitry Baryshkov <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3146f5f6bd58SDmitry Baryshkov <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3147f5f6bd58SDmitry Baryshkov <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3148f5f6bd58SDmitry Baryshkov <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3149f5f6bd58SDmitry Baryshkov <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3150f5f6bd58SDmitry Baryshkov <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3151f5f6bd58SDmitry Baryshkov <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3152f5f6bd58SDmitry Baryshkov <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3153f5f6bd58SDmitry Baryshkov <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3154f5f6bd58SDmitry Baryshkov <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3155f5f6bd58SDmitry Baryshkov <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3156f5f6bd58SDmitry Baryshkov <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3157f5f6bd58SDmitry Baryshkov <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3158f5f6bd58SDmitry Baryshkov <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3159f5f6bd58SDmitry Baryshkov <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3160f5f6bd58SDmitry Baryshkov <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3161f5f6bd58SDmitry Baryshkov <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3162f5f6bd58SDmitry Baryshkov <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3163f5f6bd58SDmitry Baryshkov <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3164f5f6bd58SDmitry Baryshkov <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3165f5f6bd58SDmitry Baryshkov <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3166f5f6bd58SDmitry Baryshkov <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3167f5f6bd58SDmitry Baryshkov <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3168f5f6bd58SDmitry Baryshkov <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3169f5f6bd58SDmitry Baryshkov <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3170f5f6bd58SDmitry Baryshkov <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3171f5f6bd58SDmitry Baryshkov <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3172f5f6bd58SDmitry Baryshkov <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3173f5f6bd58SDmitry Baryshkov <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3174f5f6bd58SDmitry Baryshkov <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3175f5f6bd58SDmitry Baryshkov <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3176f5f6bd58SDmitry Baryshkov <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3177f5f6bd58SDmitry Baryshkov <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3178f5f6bd58SDmitry Baryshkov <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3179f5f6bd58SDmitry Baryshkov <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3180f5f6bd58SDmitry Baryshkov <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3181f5f6bd58SDmitry Baryshkov <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3182f5f6bd58SDmitry Baryshkov }; 3183f5f6bd58SDmitry Baryshkov 3184177fcf0aSVinod Koul adsp: remoteproc@17300000 { 3185177fcf0aSVinod Koul compatible = "qcom,sm8350-adsp-pas"; 3186177fcf0aSVinod Koul reg = <0 0x17300000 0 0x100>; 3187177fcf0aSVinod Koul 3188177fcf0aSVinod Koul interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3189177fcf0aSVinod Koul <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3190177fcf0aSVinod Koul <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3191177fcf0aSVinod Koul <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3192177fcf0aSVinod Koul <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3193177fcf0aSVinod Koul interrupt-names = "wdog", "fatal", "ready", 3194177fcf0aSVinod Koul "handover", "stop-ack"; 3195177fcf0aSVinod Koul 3196177fcf0aSVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>; 3197177fcf0aSVinod Koul clock-names = "xo"; 3198177fcf0aSVinod Koul 3199d0e285c3SRobert Foss power-domains = <&rpmhpd SM8350_LCX>, 3200d0e285c3SRobert Foss <&rpmhpd SM8350_LMX>; 32016b7cb2d2SSibi Sankar power-domain-names = "lcx", "lmx"; 3202177fcf0aSVinod Koul 3203177fcf0aSVinod Koul memory-region = <&pil_adsp_mem>; 3204177fcf0aSVinod Koul 32056b7cb2d2SSibi Sankar qcom,qmp = <&aoss_qmp>; 32066b7cb2d2SSibi Sankar 3207177fcf0aSVinod Koul qcom,smem-states = <&smp2p_adsp_out 0>; 3208177fcf0aSVinod Koul qcom,smem-state-names = "stop"; 3209177fcf0aSVinod Koul 3210177fcf0aSVinod Koul status = "disabled"; 3211177fcf0aSVinod Koul 3212177fcf0aSVinod Koul glink-edge { 3213177fcf0aSVinod Koul interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3214177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP 3215177fcf0aSVinod Koul IRQ_TYPE_EDGE_RISING>; 3216177fcf0aSVinod Koul mboxes = <&ipcc IPCC_CLIENT_LPASS 3217177fcf0aSVinod Koul IPCC_MPROC_SIGNAL_GLINK_QMP>; 3218177fcf0aSVinod Koul 3219177fcf0aSVinod Koul label = "lpass"; 3220177fcf0aSVinod Koul qcom,remote-pid = <2>; 3221178056a4SOla Jeppsson 3222178056a4SOla Jeppsson fastrpc { 3223178056a4SOla Jeppsson compatible = "qcom,fastrpc"; 3224178056a4SOla Jeppsson qcom,glink-channels = "fastrpcglink-apps-dsp"; 3225178056a4SOla Jeppsson label = "adsp"; 32268c8ce95bSJeya R qcom,non-secure-domain; 3227178056a4SOla Jeppsson #address-cells = <1>; 3228178056a4SOla Jeppsson #size-cells = <0>; 3229178056a4SOla Jeppsson 3230178056a4SOla Jeppsson compute-cb@3 { 3231178056a4SOla Jeppsson compatible = "qcom,fastrpc-compute-cb"; 3232178056a4SOla Jeppsson reg = <3>; 3233178056a4SOla Jeppsson iommus = <&apps_smmu 0x1803 0x0>; 3234178056a4SOla Jeppsson }; 3235178056a4SOla Jeppsson 3236178056a4SOla Jeppsson compute-cb@4 { 3237178056a4SOla Jeppsson compatible = "qcom,fastrpc-compute-cb"; 3238178056a4SOla Jeppsson reg = <4>; 3239178056a4SOla Jeppsson iommus = <&apps_smmu 0x1804 0x0>; 3240178056a4SOla Jeppsson }; 3241178056a4SOla Jeppsson 3242178056a4SOla Jeppsson compute-cb@5 { 3243178056a4SOla Jeppsson compatible = "qcom,fastrpc-compute-cb"; 3244178056a4SOla Jeppsson reg = <5>; 3245178056a4SOla Jeppsson iommus = <&apps_smmu 0x1805 0x0>; 3246178056a4SOla Jeppsson }; 3247178056a4SOla Jeppsson }; 3248177fcf0aSVinod Koul }; 3249177fcf0aSVinod Koul }; 3250f5f6bd58SDmitry Baryshkov 3251f5f6bd58SDmitry Baryshkov intc: interrupt-controller@17a00000 { 3252f5f6bd58SDmitry Baryshkov compatible = "arm,gic-v3"; 3253f5f6bd58SDmitry Baryshkov #interrupt-cells = <3>; 3254f5f6bd58SDmitry Baryshkov interrupt-controller; 3255f5f6bd58SDmitry Baryshkov #redistributor-regions = <1>; 3256f5f6bd58SDmitry Baryshkov redistributor-stride = <0 0x20000>; 3257f5f6bd58SDmitry Baryshkov reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3258f5f6bd58SDmitry Baryshkov <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3259f5f6bd58SDmitry Baryshkov interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3260f5f6bd58SDmitry Baryshkov }; 3261f5f6bd58SDmitry Baryshkov 3262f5f6bd58SDmitry Baryshkov timer@17c20000 { 3263f5f6bd58SDmitry Baryshkov compatible = "arm,armv7-timer-mem"; 3264f5f6bd58SDmitry Baryshkov #address-cells = <1>; 3265f5f6bd58SDmitry Baryshkov #size-cells = <1>; 3266f5f6bd58SDmitry Baryshkov ranges = <0 0 0 0x20000000>; 3267f5f6bd58SDmitry Baryshkov reg = <0x0 0x17c20000 0x0 0x1000>; 3268f5f6bd58SDmitry Baryshkov clock-frequency = <19200000>; 3269f5f6bd58SDmitry Baryshkov 3270f5f6bd58SDmitry Baryshkov frame@17c21000 { 3271f5f6bd58SDmitry Baryshkov frame-number = <0>; 3272f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3273f5f6bd58SDmitry Baryshkov <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3274f5f6bd58SDmitry Baryshkov reg = <0x17c21000 0x1000>, 3275f5f6bd58SDmitry Baryshkov <0x17c22000 0x1000>; 3276f5f6bd58SDmitry Baryshkov }; 3277f5f6bd58SDmitry Baryshkov 3278f5f6bd58SDmitry Baryshkov frame@17c23000 { 3279f5f6bd58SDmitry Baryshkov frame-number = <1>; 3280f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3281f5f6bd58SDmitry Baryshkov reg = <0x17c23000 0x1000>; 3282f5f6bd58SDmitry Baryshkov status = "disabled"; 3283f5f6bd58SDmitry Baryshkov }; 3284f5f6bd58SDmitry Baryshkov 3285f5f6bd58SDmitry Baryshkov frame@17c25000 { 3286f5f6bd58SDmitry Baryshkov frame-number = <2>; 3287f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3288f5f6bd58SDmitry Baryshkov reg = <0x17c25000 0x1000>; 3289f5f6bd58SDmitry Baryshkov status = "disabled"; 3290f5f6bd58SDmitry Baryshkov }; 3291f5f6bd58SDmitry Baryshkov 3292f5f6bd58SDmitry Baryshkov frame@17c27000 { 3293f5f6bd58SDmitry Baryshkov frame-number = <3>; 3294f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3295f5f6bd58SDmitry Baryshkov reg = <0x17c27000 0x1000>; 3296f5f6bd58SDmitry Baryshkov status = "disabled"; 3297f5f6bd58SDmitry Baryshkov }; 3298f5f6bd58SDmitry Baryshkov 3299f5f6bd58SDmitry Baryshkov frame@17c29000 { 3300f5f6bd58SDmitry Baryshkov frame-number = <4>; 3301f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3302f5f6bd58SDmitry Baryshkov reg = <0x17c29000 0x1000>; 3303f5f6bd58SDmitry Baryshkov status = "disabled"; 3304f5f6bd58SDmitry Baryshkov }; 3305f5f6bd58SDmitry Baryshkov 3306f5f6bd58SDmitry Baryshkov frame@17c2b000 { 3307f5f6bd58SDmitry Baryshkov frame-number = <5>; 3308f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3309f5f6bd58SDmitry Baryshkov reg = <0x17c2b000 0x1000>; 3310f5f6bd58SDmitry Baryshkov status = "disabled"; 3311f5f6bd58SDmitry Baryshkov }; 3312f5f6bd58SDmitry Baryshkov 3313f5f6bd58SDmitry Baryshkov frame@17c2d000 { 3314f5f6bd58SDmitry Baryshkov frame-number = <6>; 3315f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3316f5f6bd58SDmitry Baryshkov reg = <0x17c2d000 0x1000>; 3317f5f6bd58SDmitry Baryshkov status = "disabled"; 3318f5f6bd58SDmitry Baryshkov }; 3319f5f6bd58SDmitry Baryshkov }; 3320f5f6bd58SDmitry Baryshkov 3321f5f6bd58SDmitry Baryshkov apps_rsc: rsc@18200000 { 3322f5f6bd58SDmitry Baryshkov label = "apps_rsc"; 3323f5f6bd58SDmitry Baryshkov compatible = "qcom,rpmh-rsc"; 3324f5f6bd58SDmitry Baryshkov reg = <0x0 0x18200000 0x0 0x10000>, 3325f5f6bd58SDmitry Baryshkov <0x0 0x18210000 0x0 0x10000>, 3326f5f6bd58SDmitry Baryshkov <0x0 0x18220000 0x0 0x10000>; 3327f5f6bd58SDmitry Baryshkov reg-names = "drv-0", "drv-1", "drv-2"; 3328f5f6bd58SDmitry Baryshkov interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3329f5f6bd58SDmitry Baryshkov <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3330f5f6bd58SDmitry Baryshkov <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3331f5f6bd58SDmitry Baryshkov qcom,tcs-offset = <0xd00>; 3332f5f6bd58SDmitry Baryshkov qcom,drv-id = <2>; 3333f5f6bd58SDmitry Baryshkov qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3334f5f6bd58SDmitry Baryshkov <WAKE_TCS 3>, <CONTROL_TCS 0>; 3335f5f6bd58SDmitry Baryshkov power-domains = <&CLUSTER_PD>; 3336f5f6bd58SDmitry Baryshkov 3337f5f6bd58SDmitry Baryshkov rpmhcc: clock-controller { 3338f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-rpmh-clk"; 3339f5f6bd58SDmitry Baryshkov #clock-cells = <1>; 3340f5f6bd58SDmitry Baryshkov clock-names = "xo"; 3341f5f6bd58SDmitry Baryshkov clocks = <&xo_board>; 3342f5f6bd58SDmitry Baryshkov }; 3343f5f6bd58SDmitry Baryshkov 3344f5f6bd58SDmitry Baryshkov rpmhpd: power-controller { 3345f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-rpmhpd"; 3346f5f6bd58SDmitry Baryshkov #power-domain-cells = <1>; 3347f5f6bd58SDmitry Baryshkov operating-points-v2 = <&rpmhpd_opp_table>; 3348f5f6bd58SDmitry Baryshkov 3349f5f6bd58SDmitry Baryshkov rpmhpd_opp_table: opp-table { 3350f5f6bd58SDmitry Baryshkov compatible = "operating-points-v2"; 3351f5f6bd58SDmitry Baryshkov 3352f5f6bd58SDmitry Baryshkov rpmhpd_opp_ret: opp1 { 3353f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3354f5f6bd58SDmitry Baryshkov }; 3355f5f6bd58SDmitry Baryshkov 3356f5f6bd58SDmitry Baryshkov rpmhpd_opp_min_svs: opp2 { 3357f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3358f5f6bd58SDmitry Baryshkov }; 3359f5f6bd58SDmitry Baryshkov 3360f5f6bd58SDmitry Baryshkov rpmhpd_opp_low_svs: opp3 { 3361f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3362f5f6bd58SDmitry Baryshkov }; 3363f5f6bd58SDmitry Baryshkov 3364f5f6bd58SDmitry Baryshkov rpmhpd_opp_svs: opp4 { 3365f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3366f5f6bd58SDmitry Baryshkov }; 3367f5f6bd58SDmitry Baryshkov 3368f5f6bd58SDmitry Baryshkov rpmhpd_opp_svs_l1: opp5 { 3369f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3370f5f6bd58SDmitry Baryshkov }; 3371f5f6bd58SDmitry Baryshkov 3372f5f6bd58SDmitry Baryshkov rpmhpd_opp_nom: opp6 { 3373f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3374f5f6bd58SDmitry Baryshkov }; 3375f5f6bd58SDmitry Baryshkov 3376f5f6bd58SDmitry Baryshkov rpmhpd_opp_nom_l1: opp7 { 3377f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3378f5f6bd58SDmitry Baryshkov }; 3379f5f6bd58SDmitry Baryshkov 3380f5f6bd58SDmitry Baryshkov rpmhpd_opp_nom_l2: opp8 { 3381f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3382f5f6bd58SDmitry Baryshkov }; 3383f5f6bd58SDmitry Baryshkov 3384f5f6bd58SDmitry Baryshkov rpmhpd_opp_turbo: opp9 { 3385f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3386f5f6bd58SDmitry Baryshkov }; 3387f5f6bd58SDmitry Baryshkov 3388f5f6bd58SDmitry Baryshkov rpmhpd_opp_turbo_l1: opp10 { 3389f5f6bd58SDmitry Baryshkov opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3390f5f6bd58SDmitry Baryshkov }; 3391f5f6bd58SDmitry Baryshkov }; 3392f5f6bd58SDmitry Baryshkov }; 3393f5f6bd58SDmitry Baryshkov 3394f5f6bd58SDmitry Baryshkov apps_bcm_voter: bcm-voter { 3395f5f6bd58SDmitry Baryshkov compatible = "qcom,bcm-voter"; 3396f5f6bd58SDmitry Baryshkov }; 3397f5f6bd58SDmitry Baryshkov }; 3398f5f6bd58SDmitry Baryshkov 3399f5f6bd58SDmitry Baryshkov cpufreq_hw: cpufreq@18591000 { 3400f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3401f5f6bd58SDmitry Baryshkov reg = <0 0x18591000 0 0x1000>, 3402f5f6bd58SDmitry Baryshkov <0 0x18592000 0 0x1000>, 3403f5f6bd58SDmitry Baryshkov <0 0x18593000 0 0x1000>; 3404f5f6bd58SDmitry Baryshkov reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3405f5f6bd58SDmitry Baryshkov 3406951151c2SKonrad Dybcio interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3407951151c2SKonrad Dybcio <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3408951151c2SKonrad Dybcio <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3409951151c2SKonrad Dybcio interrupt-names = "dcvsh-irq-0", 3410951151c2SKonrad Dybcio "dcvsh-irq-1", 3411951151c2SKonrad Dybcio "dcvsh-irq-2"; 3412951151c2SKonrad Dybcio 3413f5f6bd58SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3414f5f6bd58SDmitry Baryshkov clock-names = "xo", "alternate"; 3415f5f6bd58SDmitry Baryshkov 3416f5f6bd58SDmitry Baryshkov #freq-domain-cells = <1>; 3417c2a18730SManivannan Sadhasivam #clock-cells = <1>; 3418f5f6bd58SDmitry Baryshkov }; 3419f5f6bd58SDmitry Baryshkov 3420f5f6bd58SDmitry Baryshkov cdsp: remoteproc@98900000 { 3421f5f6bd58SDmitry Baryshkov compatible = "qcom,sm8350-cdsp-pas"; 3422f5f6bd58SDmitry Baryshkov reg = <0 0x98900000 0 0x1400000>; 3423f5f6bd58SDmitry Baryshkov 3424f5f6bd58SDmitry Baryshkov interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3425f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3426f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3427f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3428f5f6bd58SDmitry Baryshkov <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3429f5f6bd58SDmitry Baryshkov interrupt-names = "wdog", "fatal", "ready", 3430f5f6bd58SDmitry Baryshkov "handover", "stop-ack"; 3431f5f6bd58SDmitry Baryshkov 3432f5f6bd58SDmitry Baryshkov clocks = <&rpmhcc RPMH_CXO_CLK>; 3433f5f6bd58SDmitry Baryshkov clock-names = "xo"; 3434f5f6bd58SDmitry Baryshkov 3435f5f6bd58SDmitry Baryshkov power-domains = <&rpmhpd SM8350_CX>, 3436f5f6bd58SDmitry Baryshkov <&rpmhpd SM8350_MXC>; 3437f5f6bd58SDmitry Baryshkov power-domain-names = "cx", "mxc"; 3438f5f6bd58SDmitry Baryshkov 3439f5f6bd58SDmitry Baryshkov interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3440f5f6bd58SDmitry Baryshkov 3441f5f6bd58SDmitry Baryshkov memory-region = <&pil_cdsp_mem>; 3442f5f6bd58SDmitry Baryshkov 3443f5f6bd58SDmitry Baryshkov qcom,qmp = <&aoss_qmp>; 3444f5f6bd58SDmitry Baryshkov 3445f5f6bd58SDmitry Baryshkov qcom,smem-states = <&smp2p_cdsp_out 0>; 3446f5f6bd58SDmitry Baryshkov qcom,smem-state-names = "stop"; 3447f5f6bd58SDmitry Baryshkov 3448f5f6bd58SDmitry Baryshkov status = "disabled"; 3449f5f6bd58SDmitry Baryshkov 3450f5f6bd58SDmitry Baryshkov glink-edge { 3451f5f6bd58SDmitry Baryshkov interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3452f5f6bd58SDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP 3453f5f6bd58SDmitry Baryshkov IRQ_TYPE_EDGE_RISING>; 3454f5f6bd58SDmitry Baryshkov mboxes = <&ipcc IPCC_CLIENT_CDSP 3455f5f6bd58SDmitry Baryshkov IPCC_MPROC_SIGNAL_GLINK_QMP>; 3456f5f6bd58SDmitry Baryshkov 3457f5f6bd58SDmitry Baryshkov label = "cdsp"; 3458f5f6bd58SDmitry Baryshkov qcom,remote-pid = <5>; 3459f5f6bd58SDmitry Baryshkov 3460f5f6bd58SDmitry Baryshkov fastrpc { 3461f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc"; 3462f5f6bd58SDmitry Baryshkov qcom,glink-channels = "fastrpcglink-apps-dsp"; 3463f5f6bd58SDmitry Baryshkov label = "cdsp"; 3464f5f6bd58SDmitry Baryshkov qcom,non-secure-domain; 3465f5f6bd58SDmitry Baryshkov #address-cells = <1>; 3466f5f6bd58SDmitry Baryshkov #size-cells = <0>; 3467f5f6bd58SDmitry Baryshkov 3468f5f6bd58SDmitry Baryshkov compute-cb@1 { 3469f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3470f5f6bd58SDmitry Baryshkov reg = <1>; 3471f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2161 0x0400>, 3472f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1181 0x0420>; 3473f5f6bd58SDmitry Baryshkov }; 3474f5f6bd58SDmitry Baryshkov 3475f5f6bd58SDmitry Baryshkov compute-cb@2 { 3476f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3477f5f6bd58SDmitry Baryshkov reg = <2>; 3478f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2162 0x0400>, 3479f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1182 0x0420>; 3480f5f6bd58SDmitry Baryshkov }; 3481f5f6bd58SDmitry Baryshkov 3482f5f6bd58SDmitry Baryshkov compute-cb@3 { 3483f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3484f5f6bd58SDmitry Baryshkov reg = <3>; 3485f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2163 0x0400>, 3486f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1183 0x0420>; 3487f5f6bd58SDmitry Baryshkov }; 3488f5f6bd58SDmitry Baryshkov 3489f5f6bd58SDmitry Baryshkov compute-cb@4 { 3490f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3491f5f6bd58SDmitry Baryshkov reg = <4>; 3492f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2164 0x0400>, 3493f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1184 0x0420>; 3494f5f6bd58SDmitry Baryshkov }; 3495f5f6bd58SDmitry Baryshkov 3496f5f6bd58SDmitry Baryshkov compute-cb@5 { 3497f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3498f5f6bd58SDmitry Baryshkov reg = <5>; 3499f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2165 0x0400>, 3500f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1185 0x0420>; 3501f5f6bd58SDmitry Baryshkov }; 3502f5f6bd58SDmitry Baryshkov 3503f5f6bd58SDmitry Baryshkov compute-cb@6 { 3504f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3505f5f6bd58SDmitry Baryshkov reg = <6>; 3506f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2166 0x0400>, 3507f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1186 0x0420>; 3508f5f6bd58SDmitry Baryshkov }; 3509f5f6bd58SDmitry Baryshkov 3510f5f6bd58SDmitry Baryshkov compute-cb@7 { 3511f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3512f5f6bd58SDmitry Baryshkov reg = <7>; 3513f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2167 0x0400>, 3514f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1187 0x0420>; 3515f5f6bd58SDmitry Baryshkov }; 3516f5f6bd58SDmitry Baryshkov 3517f5f6bd58SDmitry Baryshkov compute-cb@8 { 3518f5f6bd58SDmitry Baryshkov compatible = "qcom,fastrpc-compute-cb"; 3519f5f6bd58SDmitry Baryshkov reg = <8>; 3520f5f6bd58SDmitry Baryshkov iommus = <&apps_smmu 0x2168 0x0400>, 3521f5f6bd58SDmitry Baryshkov <&apps_smmu 0x1188 0x0420>; 3522f5f6bd58SDmitry Baryshkov }; 3523f5f6bd58SDmitry Baryshkov 3524f5f6bd58SDmitry Baryshkov /* note: secure cb9 in downstream */ 3525f5f6bd58SDmitry Baryshkov }; 3526f5f6bd58SDmitry Baryshkov }; 3527f5f6bd58SDmitry Baryshkov }; 3528b7e8f433SVinod Koul }; 3529b7e8f433SVinod Koul 35304dcaa68eSsatya priya thermal_zones: thermal-zones { 353120f9d94eSRobert Foss cpu0-thermal { 353220f9d94eSRobert Foss polling-delay-passive = <250>; 353320f9d94eSRobert Foss polling-delay = <1000>; 353420f9d94eSRobert Foss 353520f9d94eSRobert Foss thermal-sensors = <&tsens0 1>; 353620f9d94eSRobert Foss 353720f9d94eSRobert Foss trips { 353820f9d94eSRobert Foss cpu0_alert0: trip-point0 { 353920f9d94eSRobert Foss temperature = <90000>; 354020f9d94eSRobert Foss hysteresis = <2000>; 354120f9d94eSRobert Foss type = "passive"; 354220f9d94eSRobert Foss }; 354320f9d94eSRobert Foss 354420f9d94eSRobert Foss cpu0_alert1: trip-point1 { 354520f9d94eSRobert Foss temperature = <95000>; 354620f9d94eSRobert Foss hysteresis = <2000>; 354720f9d94eSRobert Foss type = "passive"; 354820f9d94eSRobert Foss }; 354920f9d94eSRobert Foss 35501364acc3SKrzysztof Kozlowski cpu0_crit: cpu-crit { 355120f9d94eSRobert Foss temperature = <110000>; 355220f9d94eSRobert Foss hysteresis = <1000>; 355320f9d94eSRobert Foss type = "critical"; 355420f9d94eSRobert Foss }; 355520f9d94eSRobert Foss }; 355620f9d94eSRobert Foss 355720f9d94eSRobert Foss cooling-maps { 355820f9d94eSRobert Foss map0 { 355920f9d94eSRobert Foss trip = <&cpu0_alert0>; 356020f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356120f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356220f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356320f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 356420f9d94eSRobert Foss }; 356520f9d94eSRobert Foss map1 { 356620f9d94eSRobert Foss trip = <&cpu0_alert1>; 356720f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356820f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356920f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 357020f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 357120f9d94eSRobert Foss }; 357220f9d94eSRobert Foss }; 357320f9d94eSRobert Foss }; 357420f9d94eSRobert Foss 357520f9d94eSRobert Foss cpu1-thermal { 357620f9d94eSRobert Foss polling-delay-passive = <250>; 357720f9d94eSRobert Foss polling-delay = <1000>; 357820f9d94eSRobert Foss 357920f9d94eSRobert Foss thermal-sensors = <&tsens0 2>; 358020f9d94eSRobert Foss 358120f9d94eSRobert Foss trips { 358220f9d94eSRobert Foss cpu1_alert0: trip-point0 { 358320f9d94eSRobert Foss temperature = <90000>; 358420f9d94eSRobert Foss hysteresis = <2000>; 358520f9d94eSRobert Foss type = "passive"; 358620f9d94eSRobert Foss }; 358720f9d94eSRobert Foss 358820f9d94eSRobert Foss cpu1_alert1: trip-point1 { 358920f9d94eSRobert Foss temperature = <95000>; 359020f9d94eSRobert Foss hysteresis = <2000>; 359120f9d94eSRobert Foss type = "passive"; 359220f9d94eSRobert Foss }; 359320f9d94eSRobert Foss 35941364acc3SKrzysztof Kozlowski cpu1_crit: cpu-crit { 359520f9d94eSRobert Foss temperature = <110000>; 359620f9d94eSRobert Foss hysteresis = <1000>; 359720f9d94eSRobert Foss type = "critical"; 359820f9d94eSRobert Foss }; 359920f9d94eSRobert Foss }; 360020f9d94eSRobert Foss 360120f9d94eSRobert Foss cooling-maps { 360220f9d94eSRobert Foss map0 { 360320f9d94eSRobert Foss trip = <&cpu1_alert0>; 360420f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 360520f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 360620f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 360720f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 360820f9d94eSRobert Foss }; 360920f9d94eSRobert Foss map1 { 361020f9d94eSRobert Foss trip = <&cpu1_alert1>; 361120f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 361220f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 361320f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 361420f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 361520f9d94eSRobert Foss }; 361620f9d94eSRobert Foss }; 361720f9d94eSRobert Foss }; 361820f9d94eSRobert Foss 361920f9d94eSRobert Foss cpu2-thermal { 362020f9d94eSRobert Foss polling-delay-passive = <250>; 362120f9d94eSRobert Foss polling-delay = <1000>; 362220f9d94eSRobert Foss 362320f9d94eSRobert Foss thermal-sensors = <&tsens0 3>; 362420f9d94eSRobert Foss 362520f9d94eSRobert Foss trips { 362620f9d94eSRobert Foss cpu2_alert0: trip-point0 { 362720f9d94eSRobert Foss temperature = <90000>; 362820f9d94eSRobert Foss hysteresis = <2000>; 362920f9d94eSRobert Foss type = "passive"; 363020f9d94eSRobert Foss }; 363120f9d94eSRobert Foss 363220f9d94eSRobert Foss cpu2_alert1: trip-point1 { 363320f9d94eSRobert Foss temperature = <95000>; 363420f9d94eSRobert Foss hysteresis = <2000>; 363520f9d94eSRobert Foss type = "passive"; 363620f9d94eSRobert Foss }; 363720f9d94eSRobert Foss 36381364acc3SKrzysztof Kozlowski cpu2_crit: cpu-crit { 363920f9d94eSRobert Foss temperature = <110000>; 364020f9d94eSRobert Foss hysteresis = <1000>; 364120f9d94eSRobert Foss type = "critical"; 364220f9d94eSRobert Foss }; 364320f9d94eSRobert Foss }; 364420f9d94eSRobert Foss 364520f9d94eSRobert Foss cooling-maps { 364620f9d94eSRobert Foss map0 { 364720f9d94eSRobert Foss trip = <&cpu2_alert0>; 364820f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 364920f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 365020f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 365120f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 365220f9d94eSRobert Foss }; 365320f9d94eSRobert Foss map1 { 365420f9d94eSRobert Foss trip = <&cpu2_alert1>; 365520f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 365620f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 365720f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 365820f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 365920f9d94eSRobert Foss }; 366020f9d94eSRobert Foss }; 366120f9d94eSRobert Foss }; 366220f9d94eSRobert Foss 366320f9d94eSRobert Foss cpu3-thermal { 366420f9d94eSRobert Foss polling-delay-passive = <250>; 366520f9d94eSRobert Foss polling-delay = <1000>; 366620f9d94eSRobert Foss 366720f9d94eSRobert Foss thermal-sensors = <&tsens0 4>; 366820f9d94eSRobert Foss 366920f9d94eSRobert Foss trips { 367020f9d94eSRobert Foss cpu3_alert0: trip-point0 { 367120f9d94eSRobert Foss temperature = <90000>; 367220f9d94eSRobert Foss hysteresis = <2000>; 367320f9d94eSRobert Foss type = "passive"; 367420f9d94eSRobert Foss }; 367520f9d94eSRobert Foss 367620f9d94eSRobert Foss cpu3_alert1: trip-point1 { 367720f9d94eSRobert Foss temperature = <95000>; 367820f9d94eSRobert Foss hysteresis = <2000>; 367920f9d94eSRobert Foss type = "passive"; 368020f9d94eSRobert Foss }; 368120f9d94eSRobert Foss 36821364acc3SKrzysztof Kozlowski cpu3_crit: cpu-crit { 368320f9d94eSRobert Foss temperature = <110000>; 368420f9d94eSRobert Foss hysteresis = <1000>; 368520f9d94eSRobert Foss type = "critical"; 368620f9d94eSRobert Foss }; 368720f9d94eSRobert Foss }; 368820f9d94eSRobert Foss 368920f9d94eSRobert Foss cooling-maps { 369020f9d94eSRobert Foss map0 { 369120f9d94eSRobert Foss trip = <&cpu3_alert0>; 369220f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 369320f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 369420f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 369520f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 369620f9d94eSRobert Foss }; 369720f9d94eSRobert Foss map1 { 369820f9d94eSRobert Foss trip = <&cpu3_alert1>; 369920f9d94eSRobert Foss cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 370020f9d94eSRobert Foss <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 370120f9d94eSRobert Foss <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 370220f9d94eSRobert Foss <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 370320f9d94eSRobert Foss }; 370420f9d94eSRobert Foss }; 370520f9d94eSRobert Foss }; 370620f9d94eSRobert Foss 370720f9d94eSRobert Foss cpu4-top-thermal { 370820f9d94eSRobert Foss polling-delay-passive = <250>; 370920f9d94eSRobert Foss polling-delay = <1000>; 371020f9d94eSRobert Foss 371120f9d94eSRobert Foss thermal-sensors = <&tsens0 7>; 371220f9d94eSRobert Foss 371320f9d94eSRobert Foss trips { 371420f9d94eSRobert Foss cpu4_top_alert0: trip-point0 { 371520f9d94eSRobert Foss temperature = <90000>; 371620f9d94eSRobert Foss hysteresis = <2000>; 371720f9d94eSRobert Foss type = "passive"; 371820f9d94eSRobert Foss }; 371920f9d94eSRobert Foss 372020f9d94eSRobert Foss cpu4_top_alert1: trip-point1 { 372120f9d94eSRobert Foss temperature = <95000>; 372220f9d94eSRobert Foss hysteresis = <2000>; 372320f9d94eSRobert Foss type = "passive"; 372420f9d94eSRobert Foss }; 372520f9d94eSRobert Foss 37261364acc3SKrzysztof Kozlowski cpu4_top_crit: cpu-crit { 372720f9d94eSRobert Foss temperature = <110000>; 372820f9d94eSRobert Foss hysteresis = <1000>; 372920f9d94eSRobert Foss type = "critical"; 373020f9d94eSRobert Foss }; 373120f9d94eSRobert Foss }; 373220f9d94eSRobert Foss 373320f9d94eSRobert Foss cooling-maps { 373420f9d94eSRobert Foss map0 { 373520f9d94eSRobert Foss trip = <&cpu4_top_alert0>; 373620f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 373720f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 373820f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 373920f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 374020f9d94eSRobert Foss }; 374120f9d94eSRobert Foss map1 { 374220f9d94eSRobert Foss trip = <&cpu4_top_alert1>; 374320f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 374420f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 374520f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 374620f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 374720f9d94eSRobert Foss }; 374820f9d94eSRobert Foss }; 374920f9d94eSRobert Foss }; 375020f9d94eSRobert Foss 375120f9d94eSRobert Foss cpu5-top-thermal { 375220f9d94eSRobert Foss polling-delay-passive = <250>; 375320f9d94eSRobert Foss polling-delay = <1000>; 375420f9d94eSRobert Foss 375520f9d94eSRobert Foss thermal-sensors = <&tsens0 8>; 375620f9d94eSRobert Foss 375720f9d94eSRobert Foss trips { 375820f9d94eSRobert Foss cpu5_top_alert0: trip-point0 { 375920f9d94eSRobert Foss temperature = <90000>; 376020f9d94eSRobert Foss hysteresis = <2000>; 376120f9d94eSRobert Foss type = "passive"; 376220f9d94eSRobert Foss }; 376320f9d94eSRobert Foss 376420f9d94eSRobert Foss cpu5_top_alert1: trip-point1 { 376520f9d94eSRobert Foss temperature = <95000>; 376620f9d94eSRobert Foss hysteresis = <2000>; 376720f9d94eSRobert Foss type = "passive"; 376820f9d94eSRobert Foss }; 376920f9d94eSRobert Foss 37701364acc3SKrzysztof Kozlowski cpu5_top_crit: cpu-crit { 377120f9d94eSRobert Foss temperature = <110000>; 377220f9d94eSRobert Foss hysteresis = <1000>; 377320f9d94eSRobert Foss type = "critical"; 377420f9d94eSRobert Foss }; 377520f9d94eSRobert Foss }; 377620f9d94eSRobert Foss 377720f9d94eSRobert Foss cooling-maps { 377820f9d94eSRobert Foss map0 { 377920f9d94eSRobert Foss trip = <&cpu5_top_alert0>; 378020f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 378120f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 378220f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 378320f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 378420f9d94eSRobert Foss }; 378520f9d94eSRobert Foss map1 { 378620f9d94eSRobert Foss trip = <&cpu5_top_alert1>; 378720f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 378820f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 378920f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 379020f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 379120f9d94eSRobert Foss }; 379220f9d94eSRobert Foss }; 379320f9d94eSRobert Foss }; 379420f9d94eSRobert Foss 379520f9d94eSRobert Foss cpu6-top-thermal { 379620f9d94eSRobert Foss polling-delay-passive = <250>; 379720f9d94eSRobert Foss polling-delay = <1000>; 379820f9d94eSRobert Foss 379920f9d94eSRobert Foss thermal-sensors = <&tsens0 9>; 380020f9d94eSRobert Foss 380120f9d94eSRobert Foss trips { 380220f9d94eSRobert Foss cpu6_top_alert0: trip-point0 { 380320f9d94eSRobert Foss temperature = <90000>; 380420f9d94eSRobert Foss hysteresis = <2000>; 380520f9d94eSRobert Foss type = "passive"; 380620f9d94eSRobert Foss }; 380720f9d94eSRobert Foss 380820f9d94eSRobert Foss cpu6_top_alert1: trip-point1 { 380920f9d94eSRobert Foss temperature = <95000>; 381020f9d94eSRobert Foss hysteresis = <2000>; 381120f9d94eSRobert Foss type = "passive"; 381220f9d94eSRobert Foss }; 381320f9d94eSRobert Foss 38141364acc3SKrzysztof Kozlowski cpu6_top_crit: cpu-crit { 381520f9d94eSRobert Foss temperature = <110000>; 381620f9d94eSRobert Foss hysteresis = <1000>; 381720f9d94eSRobert Foss type = "critical"; 381820f9d94eSRobert Foss }; 381920f9d94eSRobert Foss }; 382020f9d94eSRobert Foss 382120f9d94eSRobert Foss cooling-maps { 382220f9d94eSRobert Foss map0 { 382320f9d94eSRobert Foss trip = <&cpu6_top_alert0>; 382420f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382520f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382620f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 382720f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 382820f9d94eSRobert Foss }; 382920f9d94eSRobert Foss map1 { 383020f9d94eSRobert Foss trip = <&cpu6_top_alert1>; 383120f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 383220f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 383320f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 383420f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 383520f9d94eSRobert Foss }; 383620f9d94eSRobert Foss }; 383720f9d94eSRobert Foss }; 383820f9d94eSRobert Foss 383920f9d94eSRobert Foss cpu7-top-thermal { 384020f9d94eSRobert Foss polling-delay-passive = <250>; 384120f9d94eSRobert Foss polling-delay = <1000>; 384220f9d94eSRobert Foss 384320f9d94eSRobert Foss thermal-sensors = <&tsens0 10>; 384420f9d94eSRobert Foss 384520f9d94eSRobert Foss trips { 384620f9d94eSRobert Foss cpu7_top_alert0: trip-point0 { 384720f9d94eSRobert Foss temperature = <90000>; 384820f9d94eSRobert Foss hysteresis = <2000>; 384920f9d94eSRobert Foss type = "passive"; 385020f9d94eSRobert Foss }; 385120f9d94eSRobert Foss 385220f9d94eSRobert Foss cpu7_top_alert1: trip-point1 { 385320f9d94eSRobert Foss temperature = <95000>; 385420f9d94eSRobert Foss hysteresis = <2000>; 385520f9d94eSRobert Foss type = "passive"; 385620f9d94eSRobert Foss }; 385720f9d94eSRobert Foss 38581364acc3SKrzysztof Kozlowski cpu7_top_crit: cpu-crit { 385920f9d94eSRobert Foss temperature = <110000>; 386020f9d94eSRobert Foss hysteresis = <1000>; 386120f9d94eSRobert Foss type = "critical"; 386220f9d94eSRobert Foss }; 386320f9d94eSRobert Foss }; 386420f9d94eSRobert Foss 386520f9d94eSRobert Foss cooling-maps { 386620f9d94eSRobert Foss map0 { 386720f9d94eSRobert Foss trip = <&cpu7_top_alert0>; 386820f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386920f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387020f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387120f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 387220f9d94eSRobert Foss }; 387320f9d94eSRobert Foss map1 { 387420f9d94eSRobert Foss trip = <&cpu7_top_alert1>; 387520f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387620f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387720f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387820f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 387920f9d94eSRobert Foss }; 388020f9d94eSRobert Foss }; 388120f9d94eSRobert Foss }; 388220f9d94eSRobert Foss 388320f9d94eSRobert Foss cpu4-bottom-thermal { 388420f9d94eSRobert Foss polling-delay-passive = <250>; 388520f9d94eSRobert Foss polling-delay = <1000>; 388620f9d94eSRobert Foss 388720f9d94eSRobert Foss thermal-sensors = <&tsens0 11>; 388820f9d94eSRobert Foss 388920f9d94eSRobert Foss trips { 389020f9d94eSRobert Foss cpu4_bottom_alert0: trip-point0 { 389120f9d94eSRobert Foss temperature = <90000>; 389220f9d94eSRobert Foss hysteresis = <2000>; 389320f9d94eSRobert Foss type = "passive"; 389420f9d94eSRobert Foss }; 389520f9d94eSRobert Foss 389620f9d94eSRobert Foss cpu4_bottom_alert1: trip-point1 { 389720f9d94eSRobert Foss temperature = <95000>; 389820f9d94eSRobert Foss hysteresis = <2000>; 389920f9d94eSRobert Foss type = "passive"; 390020f9d94eSRobert Foss }; 390120f9d94eSRobert Foss 39021364acc3SKrzysztof Kozlowski cpu4_bottom_crit: cpu-crit { 390320f9d94eSRobert Foss temperature = <110000>; 390420f9d94eSRobert Foss hysteresis = <1000>; 390520f9d94eSRobert Foss type = "critical"; 390620f9d94eSRobert Foss }; 390720f9d94eSRobert Foss }; 390820f9d94eSRobert Foss 390920f9d94eSRobert Foss cooling-maps { 391020f9d94eSRobert Foss map0 { 391120f9d94eSRobert Foss trip = <&cpu4_bottom_alert0>; 391220f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 391320f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 391420f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 391520f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 391620f9d94eSRobert Foss }; 391720f9d94eSRobert Foss map1 { 391820f9d94eSRobert Foss trip = <&cpu4_bottom_alert1>; 391920f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 392020f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 392120f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 392220f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 392320f9d94eSRobert Foss }; 392420f9d94eSRobert Foss }; 392520f9d94eSRobert Foss }; 392620f9d94eSRobert Foss 392720f9d94eSRobert Foss cpu5-bottom-thermal { 392820f9d94eSRobert Foss polling-delay-passive = <250>; 392920f9d94eSRobert Foss polling-delay = <1000>; 393020f9d94eSRobert Foss 393120f9d94eSRobert Foss thermal-sensors = <&tsens0 12>; 393220f9d94eSRobert Foss 393320f9d94eSRobert Foss trips { 393420f9d94eSRobert Foss cpu5_bottom_alert0: trip-point0 { 393520f9d94eSRobert Foss temperature = <90000>; 393620f9d94eSRobert Foss hysteresis = <2000>; 393720f9d94eSRobert Foss type = "passive"; 393820f9d94eSRobert Foss }; 393920f9d94eSRobert Foss 394020f9d94eSRobert Foss cpu5_bottom_alert1: trip-point1 { 394120f9d94eSRobert Foss temperature = <95000>; 394220f9d94eSRobert Foss hysteresis = <2000>; 394320f9d94eSRobert Foss type = "passive"; 394420f9d94eSRobert Foss }; 394520f9d94eSRobert Foss 39461364acc3SKrzysztof Kozlowski cpu5_bottom_crit: cpu-crit { 394720f9d94eSRobert Foss temperature = <110000>; 394820f9d94eSRobert Foss hysteresis = <1000>; 394920f9d94eSRobert Foss type = "critical"; 395020f9d94eSRobert Foss }; 395120f9d94eSRobert Foss }; 395220f9d94eSRobert Foss 395320f9d94eSRobert Foss cooling-maps { 395420f9d94eSRobert Foss map0 { 395520f9d94eSRobert Foss trip = <&cpu5_bottom_alert0>; 395620f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395720f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395820f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395920f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 396020f9d94eSRobert Foss }; 396120f9d94eSRobert Foss map1 { 396220f9d94eSRobert Foss trip = <&cpu5_bottom_alert1>; 396320f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396420f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396520f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396620f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 396720f9d94eSRobert Foss }; 396820f9d94eSRobert Foss }; 396920f9d94eSRobert Foss }; 397020f9d94eSRobert Foss 397120f9d94eSRobert Foss cpu6-bottom-thermal { 397220f9d94eSRobert Foss polling-delay-passive = <250>; 397320f9d94eSRobert Foss polling-delay = <1000>; 397420f9d94eSRobert Foss 397520f9d94eSRobert Foss thermal-sensors = <&tsens0 13>; 397620f9d94eSRobert Foss 397720f9d94eSRobert Foss trips { 397820f9d94eSRobert Foss cpu6_bottom_alert0: trip-point0 { 397920f9d94eSRobert Foss temperature = <90000>; 398020f9d94eSRobert Foss hysteresis = <2000>; 398120f9d94eSRobert Foss type = "passive"; 398220f9d94eSRobert Foss }; 398320f9d94eSRobert Foss 398420f9d94eSRobert Foss cpu6_bottom_alert1: trip-point1 { 398520f9d94eSRobert Foss temperature = <95000>; 398620f9d94eSRobert Foss hysteresis = <2000>; 398720f9d94eSRobert Foss type = "passive"; 398820f9d94eSRobert Foss }; 398920f9d94eSRobert Foss 39901364acc3SKrzysztof Kozlowski cpu6_bottom_crit: cpu-crit { 399120f9d94eSRobert Foss temperature = <110000>; 399220f9d94eSRobert Foss hysteresis = <1000>; 399320f9d94eSRobert Foss type = "critical"; 399420f9d94eSRobert Foss }; 399520f9d94eSRobert Foss }; 399620f9d94eSRobert Foss 399720f9d94eSRobert Foss cooling-maps { 399820f9d94eSRobert Foss map0 { 399920f9d94eSRobert Foss trip = <&cpu6_bottom_alert0>; 400020f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 400120f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 400220f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 400320f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 400420f9d94eSRobert Foss }; 400520f9d94eSRobert Foss map1 { 400620f9d94eSRobert Foss trip = <&cpu6_bottom_alert1>; 400720f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 400820f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 400920f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 401020f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 401120f9d94eSRobert Foss }; 401220f9d94eSRobert Foss }; 401320f9d94eSRobert Foss }; 401420f9d94eSRobert Foss 401520f9d94eSRobert Foss cpu7-bottom-thermal { 401620f9d94eSRobert Foss polling-delay-passive = <250>; 401720f9d94eSRobert Foss polling-delay = <1000>; 401820f9d94eSRobert Foss 401920f9d94eSRobert Foss thermal-sensors = <&tsens0 14>; 402020f9d94eSRobert Foss 402120f9d94eSRobert Foss trips { 402220f9d94eSRobert Foss cpu7_bottom_alert0: trip-point0 { 402320f9d94eSRobert Foss temperature = <90000>; 402420f9d94eSRobert Foss hysteresis = <2000>; 402520f9d94eSRobert Foss type = "passive"; 402620f9d94eSRobert Foss }; 402720f9d94eSRobert Foss 402820f9d94eSRobert Foss cpu7_bottom_alert1: trip-point1 { 402920f9d94eSRobert Foss temperature = <95000>; 403020f9d94eSRobert Foss hysteresis = <2000>; 403120f9d94eSRobert Foss type = "passive"; 403220f9d94eSRobert Foss }; 403320f9d94eSRobert Foss 40341364acc3SKrzysztof Kozlowski cpu7_bottom_crit: cpu-crit { 403520f9d94eSRobert Foss temperature = <110000>; 403620f9d94eSRobert Foss hysteresis = <1000>; 403720f9d94eSRobert Foss type = "critical"; 403820f9d94eSRobert Foss }; 403920f9d94eSRobert Foss }; 404020f9d94eSRobert Foss 404120f9d94eSRobert Foss cooling-maps { 404220f9d94eSRobert Foss map0 { 404320f9d94eSRobert Foss trip = <&cpu7_bottom_alert0>; 404420f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 404520f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 404620f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 404720f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 404820f9d94eSRobert Foss }; 404920f9d94eSRobert Foss map1 { 405020f9d94eSRobert Foss trip = <&cpu7_bottom_alert1>; 405120f9d94eSRobert Foss cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 405220f9d94eSRobert Foss <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 405320f9d94eSRobert Foss <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 405420f9d94eSRobert Foss <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 405520f9d94eSRobert Foss }; 405620f9d94eSRobert Foss }; 405720f9d94eSRobert Foss }; 405820f9d94eSRobert Foss 405920f9d94eSRobert Foss aoss0-thermal { 406020f9d94eSRobert Foss polling-delay-passive = <250>; 406120f9d94eSRobert Foss polling-delay = <1000>; 406220f9d94eSRobert Foss 406320f9d94eSRobert Foss thermal-sensors = <&tsens0 0>; 406420f9d94eSRobert Foss 406520f9d94eSRobert Foss trips { 406620f9d94eSRobert Foss aoss0_alert0: trip-point0 { 406720f9d94eSRobert Foss temperature = <90000>; 406820f9d94eSRobert Foss hysteresis = <2000>; 406920f9d94eSRobert Foss type = "hot"; 407020f9d94eSRobert Foss }; 407120f9d94eSRobert Foss }; 407220f9d94eSRobert Foss }; 407320f9d94eSRobert Foss 407420f9d94eSRobert Foss cluster0-thermal { 407520f9d94eSRobert Foss polling-delay-passive = <250>; 407620f9d94eSRobert Foss polling-delay = <1000>; 407720f9d94eSRobert Foss 407820f9d94eSRobert Foss thermal-sensors = <&tsens0 5>; 407920f9d94eSRobert Foss 408020f9d94eSRobert Foss trips { 408120f9d94eSRobert Foss cluster0_alert0: trip-point0 { 408220f9d94eSRobert Foss temperature = <90000>; 408320f9d94eSRobert Foss hysteresis = <2000>; 408420f9d94eSRobert Foss type = "hot"; 408520f9d94eSRobert Foss }; 408620f9d94eSRobert Foss cluster0_crit: cluster0_crit { 408720f9d94eSRobert Foss temperature = <110000>; 408820f9d94eSRobert Foss hysteresis = <2000>; 408920f9d94eSRobert Foss type = "critical"; 409020f9d94eSRobert Foss }; 409120f9d94eSRobert Foss }; 409220f9d94eSRobert Foss }; 409320f9d94eSRobert Foss 409420f9d94eSRobert Foss cluster1-thermal { 409520f9d94eSRobert Foss polling-delay-passive = <250>; 409620f9d94eSRobert Foss polling-delay = <1000>; 409720f9d94eSRobert Foss 409820f9d94eSRobert Foss thermal-sensors = <&tsens0 6>; 409920f9d94eSRobert Foss 410020f9d94eSRobert Foss trips { 410120f9d94eSRobert Foss cluster1_alert0: trip-point0 { 410220f9d94eSRobert Foss temperature = <90000>; 410320f9d94eSRobert Foss hysteresis = <2000>; 410420f9d94eSRobert Foss type = "hot"; 410520f9d94eSRobert Foss }; 410620f9d94eSRobert Foss cluster1_crit: cluster1_crit { 410720f9d94eSRobert Foss temperature = <110000>; 410820f9d94eSRobert Foss hysteresis = <2000>; 410920f9d94eSRobert Foss type = "critical"; 411020f9d94eSRobert Foss }; 411120f9d94eSRobert Foss }; 411220f9d94eSRobert Foss }; 411320f9d94eSRobert Foss 411420f9d94eSRobert Foss aoss1-thermal { 411520f9d94eSRobert Foss polling-delay-passive = <250>; 411620f9d94eSRobert Foss polling-delay = <1000>; 411720f9d94eSRobert Foss 411820f9d94eSRobert Foss thermal-sensors = <&tsens1 0>; 411920f9d94eSRobert Foss 412020f9d94eSRobert Foss trips { 412120f9d94eSRobert Foss aoss1_alert0: trip-point0 { 412220f9d94eSRobert Foss temperature = <90000>; 412320f9d94eSRobert Foss hysteresis = <2000>; 412420f9d94eSRobert Foss type = "hot"; 412520f9d94eSRobert Foss }; 412620f9d94eSRobert Foss }; 412720f9d94eSRobert Foss }; 412820f9d94eSRobert Foss 41297be1c395SDavid Heidelberg gpu-top-thermal { 413020f9d94eSRobert Foss polling-delay-passive = <250>; 413120f9d94eSRobert Foss polling-delay = <1000>; 413220f9d94eSRobert Foss 413320f9d94eSRobert Foss thermal-sensors = <&tsens1 1>; 413420f9d94eSRobert Foss 413520f9d94eSRobert Foss trips { 413620f9d94eSRobert Foss gpu1_alert0: trip-point0 { 413720f9d94eSRobert Foss temperature = <90000>; 413820f9d94eSRobert Foss hysteresis = <1000>; 413920f9d94eSRobert Foss type = "hot"; 414020f9d94eSRobert Foss }; 414120f9d94eSRobert Foss }; 414220f9d94eSRobert Foss }; 414320f9d94eSRobert Foss 41447be1c395SDavid Heidelberg gpu-bottom-thermal { 414520f9d94eSRobert Foss polling-delay-passive = <250>; 414620f9d94eSRobert Foss polling-delay = <1000>; 414720f9d94eSRobert Foss 414820f9d94eSRobert Foss thermal-sensors = <&tsens1 2>; 414920f9d94eSRobert Foss 415020f9d94eSRobert Foss trips { 415120f9d94eSRobert Foss gpu2_alert0: trip-point0 { 415220f9d94eSRobert Foss temperature = <90000>; 415320f9d94eSRobert Foss hysteresis = <1000>; 415420f9d94eSRobert Foss type = "hot"; 415520f9d94eSRobert Foss }; 415620f9d94eSRobert Foss }; 415720f9d94eSRobert Foss }; 415820f9d94eSRobert Foss 415920f9d94eSRobert Foss nspss1-thermal { 416020f9d94eSRobert Foss polling-delay-passive = <250>; 416120f9d94eSRobert Foss polling-delay = <1000>; 416220f9d94eSRobert Foss 416320f9d94eSRobert Foss thermal-sensors = <&tsens1 3>; 416420f9d94eSRobert Foss 416520f9d94eSRobert Foss trips { 416620f9d94eSRobert Foss nspss1_alert0: trip-point0 { 416720f9d94eSRobert Foss temperature = <90000>; 416820f9d94eSRobert Foss hysteresis = <1000>; 416920f9d94eSRobert Foss type = "hot"; 417020f9d94eSRobert Foss }; 417120f9d94eSRobert Foss }; 417220f9d94eSRobert Foss }; 417320f9d94eSRobert Foss 417420f9d94eSRobert Foss nspss2-thermal { 417520f9d94eSRobert Foss polling-delay-passive = <250>; 417620f9d94eSRobert Foss polling-delay = <1000>; 417720f9d94eSRobert Foss 417820f9d94eSRobert Foss thermal-sensors = <&tsens1 4>; 417920f9d94eSRobert Foss 418020f9d94eSRobert Foss trips { 418120f9d94eSRobert Foss nspss2_alert0: trip-point0 { 418220f9d94eSRobert Foss temperature = <90000>; 418320f9d94eSRobert Foss hysteresis = <1000>; 418420f9d94eSRobert Foss type = "hot"; 418520f9d94eSRobert Foss }; 418620f9d94eSRobert Foss }; 418720f9d94eSRobert Foss }; 418820f9d94eSRobert Foss 418920f9d94eSRobert Foss nspss3-thermal { 419020f9d94eSRobert Foss polling-delay-passive = <250>; 419120f9d94eSRobert Foss polling-delay = <1000>; 419220f9d94eSRobert Foss 419320f9d94eSRobert Foss thermal-sensors = <&tsens1 5>; 419420f9d94eSRobert Foss 419520f9d94eSRobert Foss trips { 419620f9d94eSRobert Foss nspss3_alert0: trip-point0 { 419720f9d94eSRobert Foss temperature = <90000>; 419820f9d94eSRobert Foss hysteresis = <1000>; 419920f9d94eSRobert Foss type = "hot"; 420020f9d94eSRobert Foss }; 420120f9d94eSRobert Foss }; 420220f9d94eSRobert Foss }; 420320f9d94eSRobert Foss 420420f9d94eSRobert Foss video-thermal { 420520f9d94eSRobert Foss polling-delay-passive = <250>; 420620f9d94eSRobert Foss polling-delay = <1000>; 420720f9d94eSRobert Foss 420820f9d94eSRobert Foss thermal-sensors = <&tsens1 6>; 420920f9d94eSRobert Foss 421020f9d94eSRobert Foss trips { 421120f9d94eSRobert Foss video_alert0: trip-point0 { 421220f9d94eSRobert Foss temperature = <90000>; 421320f9d94eSRobert Foss hysteresis = <2000>; 421420f9d94eSRobert Foss type = "hot"; 421520f9d94eSRobert Foss }; 421620f9d94eSRobert Foss }; 421720f9d94eSRobert Foss }; 421820f9d94eSRobert Foss 421920f9d94eSRobert Foss mem-thermal { 422020f9d94eSRobert Foss polling-delay-passive = <250>; 422120f9d94eSRobert Foss polling-delay = <1000>; 422220f9d94eSRobert Foss 422320f9d94eSRobert Foss thermal-sensors = <&tsens1 7>; 422420f9d94eSRobert Foss 422520f9d94eSRobert Foss trips { 422620f9d94eSRobert Foss mem_alert0: trip-point0 { 422720f9d94eSRobert Foss temperature = <90000>; 422820f9d94eSRobert Foss hysteresis = <2000>; 422920f9d94eSRobert Foss type = "hot"; 423020f9d94eSRobert Foss }; 423120f9d94eSRobert Foss }; 423220f9d94eSRobert Foss }; 423320f9d94eSRobert Foss 42347be1c395SDavid Heidelberg modem1-top-thermal { 423520f9d94eSRobert Foss polling-delay-passive = <250>; 423620f9d94eSRobert Foss polling-delay = <1000>; 423720f9d94eSRobert Foss 423820f9d94eSRobert Foss thermal-sensors = <&tsens1 8>; 423920f9d94eSRobert Foss 424020f9d94eSRobert Foss trips { 424120f9d94eSRobert Foss modem1_alert0: trip-point0 { 424220f9d94eSRobert Foss temperature = <90000>; 424320f9d94eSRobert Foss hysteresis = <2000>; 424420f9d94eSRobert Foss type = "hot"; 424520f9d94eSRobert Foss }; 424620f9d94eSRobert Foss }; 424720f9d94eSRobert Foss }; 424820f9d94eSRobert Foss 42497be1c395SDavid Heidelberg modem2-top-thermal { 425020f9d94eSRobert Foss polling-delay-passive = <250>; 425120f9d94eSRobert Foss polling-delay = <1000>; 425220f9d94eSRobert Foss 425320f9d94eSRobert Foss thermal-sensors = <&tsens1 9>; 425420f9d94eSRobert Foss 425520f9d94eSRobert Foss trips { 425620f9d94eSRobert Foss modem2_alert0: trip-point0 { 425720f9d94eSRobert Foss temperature = <90000>; 425820f9d94eSRobert Foss hysteresis = <2000>; 425920f9d94eSRobert Foss type = "hot"; 426020f9d94eSRobert Foss }; 426120f9d94eSRobert Foss }; 426220f9d94eSRobert Foss }; 426320f9d94eSRobert Foss 42647be1c395SDavid Heidelberg modem3-top-thermal { 426520f9d94eSRobert Foss polling-delay-passive = <250>; 426620f9d94eSRobert Foss polling-delay = <1000>; 426720f9d94eSRobert Foss 426820f9d94eSRobert Foss thermal-sensors = <&tsens1 10>; 426920f9d94eSRobert Foss 427020f9d94eSRobert Foss trips { 427120f9d94eSRobert Foss modem3_alert0: trip-point0 { 427220f9d94eSRobert Foss temperature = <90000>; 427320f9d94eSRobert Foss hysteresis = <2000>; 427420f9d94eSRobert Foss type = "hot"; 427520f9d94eSRobert Foss }; 427620f9d94eSRobert Foss }; 427720f9d94eSRobert Foss }; 427820f9d94eSRobert Foss 42797be1c395SDavid Heidelberg modem4-top-thermal { 428020f9d94eSRobert Foss polling-delay-passive = <250>; 428120f9d94eSRobert Foss polling-delay = <1000>; 428220f9d94eSRobert Foss 428320f9d94eSRobert Foss thermal-sensors = <&tsens1 11>; 428420f9d94eSRobert Foss 428520f9d94eSRobert Foss trips { 428620f9d94eSRobert Foss modem4_alert0: trip-point0 { 428720f9d94eSRobert Foss temperature = <90000>; 428820f9d94eSRobert Foss hysteresis = <2000>; 428920f9d94eSRobert Foss type = "hot"; 429020f9d94eSRobert Foss }; 429120f9d94eSRobert Foss }; 429220f9d94eSRobert Foss }; 429320f9d94eSRobert Foss 42947be1c395SDavid Heidelberg camera-top-thermal { 429520f9d94eSRobert Foss polling-delay-passive = <250>; 429620f9d94eSRobert Foss polling-delay = <1000>; 429720f9d94eSRobert Foss 429820f9d94eSRobert Foss thermal-sensors = <&tsens1 12>; 429920f9d94eSRobert Foss 430020f9d94eSRobert Foss trips { 430120f9d94eSRobert Foss camera1_alert0: trip-point0 { 430220f9d94eSRobert Foss temperature = <90000>; 430320f9d94eSRobert Foss hysteresis = <2000>; 430420f9d94eSRobert Foss type = "hot"; 430520f9d94eSRobert Foss }; 430620f9d94eSRobert Foss }; 430720f9d94eSRobert Foss }; 430820f9d94eSRobert Foss 43097be1c395SDavid Heidelberg cam-bottom-thermal { 431020f9d94eSRobert Foss polling-delay-passive = <250>; 431120f9d94eSRobert Foss polling-delay = <1000>; 431220f9d94eSRobert Foss 431320f9d94eSRobert Foss thermal-sensors = <&tsens1 13>; 431420f9d94eSRobert Foss 431520f9d94eSRobert Foss trips { 431620f9d94eSRobert Foss camera2_alert0: trip-point0 { 431720f9d94eSRobert Foss temperature = <90000>; 431820f9d94eSRobert Foss hysteresis = <2000>; 431920f9d94eSRobert Foss type = "hot"; 432020f9d94eSRobert Foss }; 432120f9d94eSRobert Foss }; 432220f9d94eSRobert Foss }; 432320f9d94eSRobert Foss }; 432420f9d94eSRobert Foss 4325b7e8f433SVinod Koul timer { 4326b7e8f433SVinod Koul compatible = "arm,armv8-timer"; 4327b7e8f433SVinod Koul interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4328b7e8f433SVinod Koul <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4329b7e8f433SVinod Koul <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4330b7e8f433SVinod Koul <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4331b7e8f433SVinod Koul }; 4332b7e8f433SVinod Koul}; 4333