1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <448>; 102 dynamic-power-coefficient = <205>; 103 next-level-cache = <&L2_0>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 110 #cooling-cells = <2>; 111 L2_0: l2-cache { 112 compatible = "cache"; 113 next-level-cache = <&L3_0>; 114 L3_0: l3-cache { 115 compatible = "cache"; 116 }; 117 }; 118 }; 119 120 CPU1: cpu@100 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo485"; 123 reg = <0x0 0x100>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <448>; 126 dynamic-power-coefficient = <205>; 127 next-level-cache = <&L2_100>; 128 power-domains = <&CPU_PD1>; 129 power-domain-names = "psci"; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 133 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 134 #cooling-cells = <2>; 135 L2_100: l2-cache { 136 compatible = "cache"; 137 next-level-cache = <&L3_0>; 138 }; 139 }; 140 141 CPU2: cpu@200 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo485"; 144 reg = <0x0 0x200>; 145 enable-method = "psci"; 146 capacity-dmips-mhz = <448>; 147 dynamic-power-coefficient = <205>; 148 next-level-cache = <&L2_200>; 149 power-domains = <&CPU_PD2>; 150 power-domain-names = "psci"; 151 qcom,freq-domain = <&cpufreq_hw 0>; 152 operating-points-v2 = <&cpu0_opp_table>; 153 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 154 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 155 #cooling-cells = <2>; 156 L2_200: l2-cache { 157 compatible = "cache"; 158 next-level-cache = <&L3_0>; 159 }; 160 }; 161 162 CPU3: cpu@300 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo485"; 165 reg = <0x0 0x300>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <448>; 168 dynamic-power-coefficient = <205>; 169 next-level-cache = <&L2_300>; 170 power-domains = <&CPU_PD3>; 171 power-domain-names = "psci"; 172 qcom,freq-domain = <&cpufreq_hw 0>; 173 operating-points-v2 = <&cpu0_opp_table>; 174 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 175 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 176 #cooling-cells = <2>; 177 L2_300: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU4: cpu@400 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo485"; 186 reg = <0x0 0x400>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 dynamic-power-coefficient = <379>; 190 next-level-cache = <&L2_400>; 191 power-domains = <&CPU_PD4>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 operating-points-v2 = <&cpu4_opp_table>; 195 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 196 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 197 #cooling-cells = <2>; 198 L2_400: l2-cache { 199 compatible = "cache"; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 CPU5: cpu@500 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo485"; 207 reg = <0x0 0x500>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&L2_500>; 212 power-domains = <&CPU_PD5>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 L2_500: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 224 }; 225 226 CPU6: cpu@600 { 227 device_type = "cpu"; 228 compatible = "qcom,kryo485"; 229 reg = <0x0 0x600>; 230 enable-method = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <379>; 233 next-level-cache = <&L2_600>; 234 power-domains = <&CPU_PD6>; 235 power-domain-names = "psci"; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 operating-points-v2 = <&cpu4_opp_table>; 238 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 239 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 240 #cooling-cells = <2>; 241 L2_600: l2-cache { 242 compatible = "cache"; 243 next-level-cache = <&L3_0>; 244 }; 245 }; 246 247 CPU7: cpu@700 { 248 device_type = "cpu"; 249 compatible = "qcom,kryo485"; 250 reg = <0x0 0x700>; 251 enable-method = "psci"; 252 capacity-dmips-mhz = <1024>; 253 dynamic-power-coefficient = <444>; 254 next-level-cache = <&L2_700>; 255 power-domains = <&CPU_PD7>; 256 power-domain-names = "psci"; 257 qcom,freq-domain = <&cpufreq_hw 2>; 258 operating-points-v2 = <&cpu7_opp_table>; 259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 261 #cooling-cells = <2>; 262 L2_700: l2-cache { 263 compatible = "cache"; 264 next-level-cache = <&L3_0>; 265 }; 266 }; 267 268 cpu-map { 269 cluster0 { 270 core0 { 271 cpu = <&CPU0>; 272 }; 273 274 core1 { 275 cpu = <&CPU1>; 276 }; 277 278 core2 { 279 cpu = <&CPU2>; 280 }; 281 282 core3 { 283 cpu = <&CPU3>; 284 }; 285 286 core4 { 287 cpu = <&CPU4>; 288 }; 289 290 core5 { 291 cpu = <&CPU5>; 292 }; 293 294 core6 { 295 cpu = <&CPU6>; 296 }; 297 298 core7 { 299 cpu = <&CPU7>; 300 }; 301 }; 302 }; 303 304 idle-states { 305 entry-method = "psci"; 306 307 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "silver-rail-power-collapse"; 310 arm,psci-suspend-param = <0x40000004>; 311 entry-latency-us = <360>; 312 exit-latency-us = <531>; 313 min-residency-us = <3934>; 314 local-timer-stop; 315 }; 316 317 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "gold-rail-power-collapse"; 320 arm,psci-suspend-param = <0x40000004>; 321 entry-latency-us = <702>; 322 exit-latency-us = <1061>; 323 min-residency-us = <4488>; 324 local-timer-stop; 325 }; 326 }; 327 328 domain-idle-states { 329 CLUSTER_SLEEP_0: cluster-sleep-0 { 330 compatible = "domain-idle-state"; 331 idle-state-name = "cluster-llcc-off"; 332 arm,psci-suspend-param = <0x4100c244>; 333 entry-latency-us = <3264>; 334 exit-latency-us = <6562>; 335 min-residency-us = <9987>; 336 local-timer-stop; 337 status = "disabled"; 338 }; 339 }; 340 }; 341 342 cpu0_opp_table: opp-table-cpu0 { 343 compatible = "operating-points-v2"; 344 opp-shared; 345 346 cpu0_opp1: opp-300000000 { 347 opp-hz = /bits/ 64 <300000000>; 348 opp-peak-kBps = <800000 9600000>; 349 }; 350 351 cpu0_opp2: opp-403200000 { 352 opp-hz = /bits/ 64 <403200000>; 353 opp-peak-kBps = <800000 9600000>; 354 }; 355 356 cpu0_opp3: opp-518400000 { 357 opp-hz = /bits/ 64 <518400000>; 358 opp-peak-kBps = <800000 16588800>; 359 }; 360 361 cpu0_opp4: opp-614400000 { 362 opp-hz = /bits/ 64 <614400000>; 363 opp-peak-kBps = <800000 16588800>; 364 }; 365 366 cpu0_opp5: opp-691200000 { 367 opp-hz = /bits/ 64 <691200000>; 368 opp-peak-kBps = <800000 19660800>; 369 }; 370 371 cpu0_opp6: opp-787200000 { 372 opp-hz = /bits/ 64 <787200000>; 373 opp-peak-kBps = <1804000 19660800>; 374 }; 375 376 cpu0_opp7: opp-883200000 { 377 opp-hz = /bits/ 64 <883200000>; 378 opp-peak-kBps = <1804000 23347200>; 379 }; 380 381 cpu0_opp8: opp-979200000 { 382 opp-hz = /bits/ 64 <979200000>; 383 opp-peak-kBps = <1804000 26419200>; 384 }; 385 386 cpu0_opp9: opp-1075200000 { 387 opp-hz = /bits/ 64 <1075200000>; 388 opp-peak-kBps = <1804000 29491200>; 389 }; 390 391 cpu0_opp10: opp-1171200000 { 392 opp-hz = /bits/ 64 <1171200000>; 393 opp-peak-kBps = <1804000 32563200>; 394 }; 395 396 cpu0_opp11: opp-1248000000 { 397 opp-hz = /bits/ 64 <1248000000>; 398 opp-peak-kBps = <1804000 36249600>; 399 }; 400 401 cpu0_opp12: opp-1344000000 { 402 opp-hz = /bits/ 64 <1344000000>; 403 opp-peak-kBps = <2188000 36249600>; 404 }; 405 406 cpu0_opp13: opp-1420800000 { 407 opp-hz = /bits/ 64 <1420800000>; 408 opp-peak-kBps = <2188000 39321600>; 409 }; 410 411 cpu0_opp14: opp-1516800000 { 412 opp-hz = /bits/ 64 <1516800000>; 413 opp-peak-kBps = <3072000 42393600>; 414 }; 415 416 cpu0_opp15: opp-1612800000 { 417 opp-hz = /bits/ 64 <1612800000>; 418 opp-peak-kBps = <3072000 42393600>; 419 }; 420 421 cpu0_opp16: opp-1708800000 { 422 opp-hz = /bits/ 64 <1708800000>; 423 opp-peak-kBps = <4068000 42393600>; 424 }; 425 426 cpu0_opp17: opp-1804800000 { 427 opp-hz = /bits/ 64 <1804800000>; 428 opp-peak-kBps = <4068000 42393600>; 429 }; 430 }; 431 432 cpu4_opp_table: opp-table-cpu4 { 433 compatible = "operating-points-v2"; 434 opp-shared; 435 436 cpu4_opp1: opp-710400000 { 437 opp-hz = /bits/ 64 <710400000>; 438 opp-peak-kBps = <1804000 19660800>; 439 }; 440 441 cpu4_opp2: opp-825600000 { 442 opp-hz = /bits/ 64 <825600000>; 443 opp-peak-kBps = <2188000 23347200>; 444 }; 445 446 cpu4_opp3: opp-940800000 { 447 opp-hz = /bits/ 64 <940800000>; 448 opp-peak-kBps = <2188000 26419200>; 449 }; 450 451 cpu4_opp4: opp-1056000000 { 452 opp-hz = /bits/ 64 <1056000000>; 453 opp-peak-kBps = <3072000 26419200>; 454 }; 455 456 cpu4_opp5: opp-1171200000 { 457 opp-hz = /bits/ 64 <1171200000>; 458 opp-peak-kBps = <3072000 29491200>; 459 }; 460 461 cpu4_opp6: opp-1286400000 { 462 opp-hz = /bits/ 64 <1286400000>; 463 opp-peak-kBps = <4068000 29491200>; 464 }; 465 466 cpu4_opp7: opp-1382400000 { 467 opp-hz = /bits/ 64 <1382400000>; 468 opp-peak-kBps = <4068000 32563200>; 469 }; 470 471 cpu4_opp8: opp-1478400000 { 472 opp-hz = /bits/ 64 <1478400000>; 473 opp-peak-kBps = <4068000 32563200>; 474 }; 475 476 cpu4_opp9: opp-1574400000 { 477 opp-hz = /bits/ 64 <1574400000>; 478 opp-peak-kBps = <5412000 39321600>; 479 }; 480 481 cpu4_opp10: opp-1670400000 { 482 opp-hz = /bits/ 64 <1670400000>; 483 opp-peak-kBps = <5412000 42393600>; 484 }; 485 486 cpu4_opp11: opp-1766400000 { 487 opp-hz = /bits/ 64 <1766400000>; 488 opp-peak-kBps = <5412000 45465600>; 489 }; 490 491 cpu4_opp12: opp-1862400000 { 492 opp-hz = /bits/ 64 <1862400000>; 493 opp-peak-kBps = <6220000 45465600>; 494 }; 495 496 cpu4_opp13: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <6220000 48537600>; 499 }; 500 501 cpu4_opp14: opp-2054400000 { 502 opp-hz = /bits/ 64 <2054400000>; 503 opp-peak-kBps = <7216000 48537600>; 504 }; 505 506 cpu4_opp15: opp-2150400000 { 507 opp-hz = /bits/ 64 <2150400000>; 508 opp-peak-kBps = <7216000 51609600>; 509 }; 510 511 cpu4_opp16: opp-2246400000 { 512 opp-hz = /bits/ 64 <2246400000>; 513 opp-peak-kBps = <7216000 51609600>; 514 }; 515 516 cpu4_opp17: opp-2342400000 { 517 opp-hz = /bits/ 64 <2342400000>; 518 opp-peak-kBps = <8368000 51609600>; 519 }; 520 521 cpu4_opp18: opp-2419200000 { 522 opp-hz = /bits/ 64 <2419200000>; 523 opp-peak-kBps = <8368000 51609600>; 524 }; 525 }; 526 527 cpu7_opp_table: opp-table-cpu7 { 528 compatible = "operating-points-v2"; 529 opp-shared; 530 531 cpu7_opp1: opp-844800000 { 532 opp-hz = /bits/ 64 <844800000>; 533 opp-peak-kBps = <2188000 19660800>; 534 }; 535 536 cpu7_opp2: opp-960000000 { 537 opp-hz = /bits/ 64 <960000000>; 538 opp-peak-kBps = <2188000 26419200>; 539 }; 540 541 cpu7_opp3: opp-1075200000 { 542 opp-hz = /bits/ 64 <1075200000>; 543 opp-peak-kBps = <3072000 26419200>; 544 }; 545 546 cpu7_opp4: opp-1190400000 { 547 opp-hz = /bits/ 64 <1190400000>; 548 opp-peak-kBps = <3072000 29491200>; 549 }; 550 551 cpu7_opp5: opp-1305600000 { 552 opp-hz = /bits/ 64 <1305600000>; 553 opp-peak-kBps = <4068000 32563200>; 554 }; 555 556 cpu7_opp6: opp-1401600000 { 557 opp-hz = /bits/ 64 <1401600000>; 558 opp-peak-kBps = <4068000 32563200>; 559 }; 560 561 cpu7_opp7: opp-1516800000 { 562 opp-hz = /bits/ 64 <1516800000>; 563 opp-peak-kBps = <4068000 36249600>; 564 }; 565 566 cpu7_opp8: opp-1632000000 { 567 opp-hz = /bits/ 64 <1632000000>; 568 opp-peak-kBps = <5412000 39321600>; 569 }; 570 571 cpu7_opp9: opp-1747200000 { 572 opp-hz = /bits/ 64 <1708800000>; 573 opp-peak-kBps = <5412000 42393600>; 574 }; 575 576 cpu7_opp10: opp-1862400000 { 577 opp-hz = /bits/ 64 <1862400000>; 578 opp-peak-kBps = <6220000 45465600>; 579 }; 580 581 cpu7_opp11: opp-1977600000 { 582 opp-hz = /bits/ 64 <1977600000>; 583 opp-peak-kBps = <6220000 48537600>; 584 }; 585 586 cpu7_opp12: opp-2073600000 { 587 opp-hz = /bits/ 64 <2073600000>; 588 opp-peak-kBps = <7216000 48537600>; 589 }; 590 591 cpu7_opp13: opp-2169600000 { 592 opp-hz = /bits/ 64 <2169600000>; 593 opp-peak-kBps = <7216000 51609600>; 594 }; 595 596 cpu7_opp14: opp-2265600000 { 597 opp-hz = /bits/ 64 <2265600000>; 598 opp-peak-kBps = <7216000 51609600>; 599 }; 600 601 cpu7_opp15: opp-2361600000 { 602 opp-hz = /bits/ 64 <2361600000>; 603 opp-peak-kBps = <8368000 51609600>; 604 }; 605 606 cpu7_opp16: opp-2457600000 { 607 opp-hz = /bits/ 64 <2457600000>; 608 opp-peak-kBps = <8368000 51609600>; 609 }; 610 611 cpu7_opp17: opp-2553600000 { 612 opp-hz = /bits/ 64 <2553600000>; 613 opp-peak-kBps = <8368000 51609600>; 614 }; 615 616 cpu7_opp18: opp-2649600000 { 617 opp-hz = /bits/ 64 <2649600000>; 618 opp-peak-kBps = <8368000 51609600>; 619 }; 620 621 cpu7_opp19: opp-2745600000 { 622 opp-hz = /bits/ 64 <2745600000>; 623 opp-peak-kBps = <8368000 51609600>; 624 }; 625 626 cpu7_opp20: opp-2841600000 { 627 opp-hz = /bits/ 64 <2841600000>; 628 opp-peak-kBps = <8368000 51609600>; 629 }; 630 }; 631 632 firmware { 633 scm: scm { 634 compatible = "qcom,scm-sm8250", "qcom,scm"; 635 #reset-cells = <1>; 636 }; 637 }; 638 639 memory@80000000 { 640 device_type = "memory"; 641 /* We expect the bootloader to fill in the size */ 642 reg = <0x0 0x80000000 0x0 0x0>; 643 }; 644 645 pmu { 646 compatible = "arm,armv8-pmuv3"; 647 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 648 }; 649 650 psci { 651 compatible = "arm,psci-1.0"; 652 method = "smc"; 653 654 CPU_PD0: cpu0 { 655 #power-domain-cells = <0>; 656 power-domains = <&CLUSTER_PD>; 657 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 658 }; 659 660 CPU_PD1: cpu1 { 661 #power-domain-cells = <0>; 662 power-domains = <&CLUSTER_PD>; 663 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 664 }; 665 666 CPU_PD2: cpu2 { 667 #power-domain-cells = <0>; 668 power-domains = <&CLUSTER_PD>; 669 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 670 }; 671 672 CPU_PD3: cpu3 { 673 #power-domain-cells = <0>; 674 power-domains = <&CLUSTER_PD>; 675 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 676 }; 677 678 CPU_PD4: cpu4 { 679 #power-domain-cells = <0>; 680 power-domains = <&CLUSTER_PD>; 681 domain-idle-states = <&BIG_CPU_SLEEP_0>; 682 }; 683 684 CPU_PD5: cpu5 { 685 #power-domain-cells = <0>; 686 power-domains = <&CLUSTER_PD>; 687 domain-idle-states = <&BIG_CPU_SLEEP_0>; 688 }; 689 690 CPU_PD6: cpu6 { 691 #power-domain-cells = <0>; 692 power-domains = <&CLUSTER_PD>; 693 domain-idle-states = <&BIG_CPU_SLEEP_0>; 694 }; 695 696 CPU_PD7: cpu7 { 697 #power-domain-cells = <0>; 698 power-domains = <&CLUSTER_PD>; 699 domain-idle-states = <&BIG_CPU_SLEEP_0>; 700 }; 701 702 CLUSTER_PD: cpu-cluster0 { 703 #power-domain-cells = <0>; 704 domain-idle-states = <&CLUSTER_SLEEP_0>; 705 }; 706 }; 707 708 qup_opp_table: opp-table-qup { 709 compatible = "operating-points-v2"; 710 711 opp-50000000 { 712 opp-hz = /bits/ 64 <50000000>; 713 required-opps = <&rpmhpd_opp_min_svs>; 714 }; 715 716 opp-75000000 { 717 opp-hz = /bits/ 64 <75000000>; 718 required-opps = <&rpmhpd_opp_low_svs>; 719 }; 720 721 opp-120000000 { 722 opp-hz = /bits/ 64 <120000000>; 723 required-opps = <&rpmhpd_opp_svs>; 724 }; 725 }; 726 727 reserved-memory { 728 #address-cells = <2>; 729 #size-cells = <2>; 730 ranges; 731 732 hyp_mem: memory@80000000 { 733 reg = <0x0 0x80000000 0x0 0x600000>; 734 no-map; 735 }; 736 737 xbl_aop_mem: memory@80700000 { 738 reg = <0x0 0x80700000 0x0 0x160000>; 739 no-map; 740 }; 741 742 cmd_db: memory@80860000 { 743 compatible = "qcom,cmd-db"; 744 reg = <0x0 0x80860000 0x0 0x20000>; 745 no-map; 746 }; 747 748 smem_mem: memory@80900000 { 749 reg = <0x0 0x80900000 0x0 0x200000>; 750 no-map; 751 }; 752 753 removed_mem: memory@80b00000 { 754 reg = <0x0 0x80b00000 0x0 0x5300000>; 755 no-map; 756 }; 757 758 camera_mem: memory@86200000 { 759 reg = <0x0 0x86200000 0x0 0x500000>; 760 no-map; 761 }; 762 763 wlan_mem: memory@86700000 { 764 reg = <0x0 0x86700000 0x0 0x100000>; 765 no-map; 766 }; 767 768 ipa_fw_mem: memory@86800000 { 769 reg = <0x0 0x86800000 0x0 0x10000>; 770 no-map; 771 }; 772 773 ipa_gsi_mem: memory@86810000 { 774 reg = <0x0 0x86810000 0x0 0xa000>; 775 no-map; 776 }; 777 778 gpu_mem: memory@8681a000 { 779 reg = <0x0 0x8681a000 0x0 0x2000>; 780 no-map; 781 }; 782 783 npu_mem: memory@86900000 { 784 reg = <0x0 0x86900000 0x0 0x500000>; 785 no-map; 786 }; 787 788 video_mem: memory@86e00000 { 789 reg = <0x0 0x86e00000 0x0 0x500000>; 790 no-map; 791 }; 792 793 cvp_mem: memory@87300000 { 794 reg = <0x0 0x87300000 0x0 0x500000>; 795 no-map; 796 }; 797 798 cdsp_mem: memory@87800000 { 799 reg = <0x0 0x87800000 0x0 0x1400000>; 800 no-map; 801 }; 802 803 slpi_mem: memory@88c00000 { 804 reg = <0x0 0x88c00000 0x0 0x1500000>; 805 no-map; 806 }; 807 808 adsp_mem: memory@8a100000 { 809 reg = <0x0 0x8a100000 0x0 0x1d00000>; 810 no-map; 811 }; 812 813 spss_mem: memory@8be00000 { 814 reg = <0x0 0x8be00000 0x0 0x100000>; 815 no-map; 816 }; 817 818 cdsp_secure_heap: memory@8bf00000 { 819 reg = <0x0 0x8bf00000 0x0 0x4600000>; 820 no-map; 821 }; 822 }; 823 824 smem { 825 compatible = "qcom,smem"; 826 memory-region = <&smem_mem>; 827 hwlocks = <&tcsr_mutex 3>; 828 }; 829 830 smp2p-adsp { 831 compatible = "qcom,smp2p"; 832 qcom,smem = <443>, <429>; 833 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 834 IPCC_MPROC_SIGNAL_SMP2P 835 IRQ_TYPE_EDGE_RISING>; 836 mboxes = <&ipcc IPCC_CLIENT_LPASS 837 IPCC_MPROC_SIGNAL_SMP2P>; 838 839 qcom,local-pid = <0>; 840 qcom,remote-pid = <2>; 841 842 smp2p_adsp_out: master-kernel { 843 qcom,entry-name = "master-kernel"; 844 #qcom,smem-state-cells = <1>; 845 }; 846 847 smp2p_adsp_in: slave-kernel { 848 qcom,entry-name = "slave-kernel"; 849 interrupt-controller; 850 #interrupt-cells = <2>; 851 }; 852 }; 853 854 smp2p-cdsp { 855 compatible = "qcom,smp2p"; 856 qcom,smem = <94>, <432>; 857 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 858 IPCC_MPROC_SIGNAL_SMP2P 859 IRQ_TYPE_EDGE_RISING>; 860 mboxes = <&ipcc IPCC_CLIENT_CDSP 861 IPCC_MPROC_SIGNAL_SMP2P>; 862 863 qcom,local-pid = <0>; 864 qcom,remote-pid = <5>; 865 866 smp2p_cdsp_out: master-kernel { 867 qcom,entry-name = "master-kernel"; 868 #qcom,smem-state-cells = <1>; 869 }; 870 871 smp2p_cdsp_in: slave-kernel { 872 qcom,entry-name = "slave-kernel"; 873 interrupt-controller; 874 #interrupt-cells = <2>; 875 }; 876 }; 877 878 smp2p-slpi { 879 compatible = "qcom,smp2p"; 880 qcom,smem = <481>, <430>; 881 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 882 IPCC_MPROC_SIGNAL_SMP2P 883 IRQ_TYPE_EDGE_RISING>; 884 mboxes = <&ipcc IPCC_CLIENT_SLPI 885 IPCC_MPROC_SIGNAL_SMP2P>; 886 887 qcom,local-pid = <0>; 888 qcom,remote-pid = <3>; 889 890 smp2p_slpi_out: master-kernel { 891 qcom,entry-name = "master-kernel"; 892 #qcom,smem-state-cells = <1>; 893 }; 894 895 smp2p_slpi_in: slave-kernel { 896 qcom,entry-name = "slave-kernel"; 897 interrupt-controller; 898 #interrupt-cells = <2>; 899 }; 900 }; 901 902 soc: soc@0 { 903 #address-cells = <2>; 904 #size-cells = <2>; 905 ranges = <0 0 0 0 0x10 0>; 906 dma-ranges = <0 0 0 0 0x10 0>; 907 compatible = "simple-bus"; 908 909 gcc: clock-controller@100000 { 910 compatible = "qcom,gcc-sm8250"; 911 reg = <0x0 0x00100000 0x0 0x1f0000>; 912 #clock-cells = <1>; 913 #reset-cells = <1>; 914 #power-domain-cells = <1>; 915 clock-names = "bi_tcxo", 916 "bi_tcxo_ao", 917 "sleep_clk"; 918 clocks = <&rpmhcc RPMH_CXO_CLK>, 919 <&rpmhcc RPMH_CXO_CLK_A>, 920 <&sleep_clk>; 921 }; 922 923 ipcc: mailbox@408000 { 924 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 925 reg = <0 0x00408000 0 0x1000>; 926 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-controller; 928 #interrupt-cells = <3>; 929 #mbox-cells = <2>; 930 }; 931 932 rng: rng@793000 { 933 compatible = "qcom,prng-ee"; 934 reg = <0 0x00793000 0 0x1000>; 935 clocks = <&gcc GCC_PRNG_AHB_CLK>; 936 clock-names = "core"; 937 }; 938 939 gpi_dma2: dma-controller@800000 { 940 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 941 reg = <0 0x00800000 0 0x70000>; 942 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 952 dma-channels = <10>; 953 dma-channel-mask = <0x3f>; 954 iommus = <&apps_smmu 0x76 0x0>; 955 #dma-cells = <3>; 956 status = "disabled"; 957 }; 958 959 qupv3_id_2: geniqup@8c0000 { 960 compatible = "qcom,geni-se-qup"; 961 reg = <0x0 0x008c0000 0x0 0x6000>; 962 clock-names = "m-ahb", "s-ahb"; 963 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 964 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 965 #address-cells = <2>; 966 #size-cells = <2>; 967 iommus = <&apps_smmu 0x63 0x0>; 968 ranges; 969 status = "disabled"; 970 971 i2c14: i2c@880000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00880000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_i2c14_default>; 978 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 979 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 980 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 spi14: spi@880000 { 988 compatible = "qcom,geni-spi"; 989 reg = <0 0x00880000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 992 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 993 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 994 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 995 dma-names = "tx", "rx"; 996 power-domains = <&rpmhpd SM8250_CX>; 997 operating-points-v2 = <&qup_opp_table>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c15: i2c@884000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00884000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c15_default>; 1010 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1011 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1012 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 spi15: spi@884000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x00884000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1024 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1025 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1026 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1027 dma-names = "tx", "rx"; 1028 power-domains = <&rpmhpd SM8250_CX>; 1029 operating-points-v2 = <&qup_opp_table>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 i2c16: i2c@888000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00888000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c16_default>; 1042 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1043 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1044 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 spi16: spi@888000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x00888000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1056 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1058 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1059 dma-names = "tx", "rx"; 1060 power-domains = <&rpmhpd SM8250_CX>; 1061 operating-points-v2 = <&qup_opp_table>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c17: i2c@88c000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x0088c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_i2c17_default>; 1074 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1075 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1076 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1077 dma-names = "tx", "rx"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 spi17: spi@88c000 { 1084 compatible = "qcom,geni-spi"; 1085 reg = <0 0x0088c000 0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1088 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1089 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1090 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 power-domains = <&rpmhpd SM8250_CX>; 1093 operating-points-v2 = <&qup_opp_table>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 uart17: serial@88c000 { 1100 compatible = "qcom,geni-uart"; 1101 reg = <0 0x0088c000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_uart17_default>; 1106 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1107 power-domains = <&rpmhpd SM8250_CX>; 1108 operating-points-v2 = <&qup_opp_table>; 1109 status = "disabled"; 1110 }; 1111 1112 i2c18: i2c@890000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c18_default>; 1119 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1120 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1121 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 spi18: spi@890000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00890000 0 0x4000>; 1131 clock-names = "se"; 1132 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1133 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1134 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1135 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1136 dma-names = "tx", "rx"; 1137 power-domains = <&rpmhpd SM8250_CX>; 1138 operating-points-v2 = <&qup_opp_table>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 uart18: serial@890000 { 1145 compatible = "qcom,geni-uart"; 1146 reg = <0 0x00890000 0 0x4000>; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_uart18_default>; 1151 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1152 power-domains = <&rpmhpd SM8250_CX>; 1153 operating-points-v2 = <&qup_opp_table>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c19: i2c@894000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x00894000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c19_default>; 1164 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 spi19: spi@894000 { 1174 compatible = "qcom,geni-spi"; 1175 reg = <0 0x00894000 0 0x4000>; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1178 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1179 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1180 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1181 dma-names = "tx", "rx"; 1182 power-domains = <&rpmhpd SM8250_CX>; 1183 operating-points-v2 = <&qup_opp_table>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 }; 1189 1190 gpi_dma0: dma-controller@900000 { 1191 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1192 reg = <0 0x00900000 0 0x70000>; 1193 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1206 dma-channels = <15>; 1207 dma-channel-mask = <0x7ff>; 1208 iommus = <&apps_smmu 0x5b6 0x0>; 1209 #dma-cells = <3>; 1210 status = "disabled"; 1211 }; 1212 1213 qupv3_id_0: geniqup@9c0000 { 1214 compatible = "qcom,geni-se-qup"; 1215 reg = <0x0 0x009c0000 0x0 0x6000>; 1216 clock-names = "m-ahb", "s-ahb"; 1217 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1218 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1219 #address-cells = <2>; 1220 #size-cells = <2>; 1221 iommus = <&apps_smmu 0x5a3 0x0>; 1222 ranges; 1223 status = "disabled"; 1224 1225 i2c0: i2c@980000 { 1226 compatible = "qcom,geni-i2c"; 1227 reg = <0 0x00980000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_i2c0_default>; 1232 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1233 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1234 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1235 dma-names = "tx", "rx"; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 spi0: spi@980000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x00980000 0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1246 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1247 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1248 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&rpmhpd SM8250_CX>; 1251 operating-points-v2 = <&qup_opp_table>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 i2c1: i2c@984000 { 1258 compatible = "qcom,geni-i2c"; 1259 reg = <0 0x00984000 0 0x4000>; 1260 clock-names = "se"; 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&qup_i2c1_default>; 1264 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1265 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1266 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1267 dma-names = "tx", "rx"; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 1273 spi1: spi@984000 { 1274 compatible = "qcom,geni-spi"; 1275 reg = <0 0x00984000 0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1278 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1279 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 power-domains = <&rpmhpd SM8250_CX>; 1283 operating-points-v2 = <&qup_opp_table>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 i2c2: i2c@988000 { 1290 compatible = "qcom,geni-i2c"; 1291 reg = <0 0x00988000 0 0x4000>; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_i2c2_default>; 1296 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1297 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1298 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 spi2: spi@988000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x00988000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1310 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1312 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1313 dma-names = "tx", "rx"; 1314 power-domains = <&rpmhpd SM8250_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 uart2: serial@988000 { 1322 compatible = "qcom,geni-debug-uart"; 1323 reg = <0 0x00988000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_uart2_default>; 1328 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SM8250_CX>; 1330 operating-points-v2 = <&qup_opp_table>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c3: i2c@98c000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0 0x0098c000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c3_default>; 1341 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1343 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1344 dma-names = "tx", "rx"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 spi3: spi@98c000 { 1351 compatible = "qcom,geni-spi"; 1352 reg = <0 0x0098c000 0 0x4000>; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1355 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1356 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1357 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1358 dma-names = "tx", "rx"; 1359 power-domains = <&rpmhpd SM8250_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c4: i2c@990000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0 0x00990000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c4_default>; 1373 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1374 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 spi4: spi@990000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x00990000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1387 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1388 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1389 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1390 dma-names = "tx", "rx"; 1391 power-domains = <&rpmhpd SM8250_CX>; 1392 operating-points-v2 = <&qup_opp_table>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 i2c5: i2c@994000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00994000 0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_i2c5_default>; 1405 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1407 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1408 dma-names = "tx", "rx"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 spi5: spi@994000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00994000 0 0x4000>; 1417 clock-names = "se"; 1418 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1419 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1420 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1421 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1422 dma-names = "tx", "rx"; 1423 power-domains = <&rpmhpd SM8250_CX>; 1424 operating-points-v2 = <&qup_opp_table>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 1430 i2c6: i2c@998000 { 1431 compatible = "qcom,geni-i2c"; 1432 reg = <0 0x00998000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_i2c6_default>; 1437 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1438 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1439 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1440 dma-names = "tx", "rx"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 spi6: spi@998000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0x00998000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1451 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1452 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1453 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1454 dma-names = "tx", "rx"; 1455 power-domains = <&rpmhpd SM8250_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 status = "disabled"; 1460 }; 1461 1462 uart6: serial@998000 { 1463 compatible = "qcom,geni-uart"; 1464 reg = <0 0x00998000 0 0x4000>; 1465 clock-names = "se"; 1466 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1467 pinctrl-names = "default"; 1468 pinctrl-0 = <&qup_uart6_default>; 1469 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1470 power-domains = <&rpmhpd SM8250_CX>; 1471 operating-points-v2 = <&qup_opp_table>; 1472 status = "disabled"; 1473 }; 1474 1475 i2c7: i2c@99c000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x0099c000 0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c7_default>; 1482 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1483 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1484 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1485 dma-names = "tx", "rx"; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 }; 1490 1491 spi7: spi@99c000 { 1492 compatible = "qcom,geni-spi"; 1493 reg = <0 0x0099c000 0 0x4000>; 1494 clock-names = "se"; 1495 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1496 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1497 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1498 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1499 dma-names = "tx", "rx"; 1500 power-domains = <&rpmhpd SM8250_CX>; 1501 operating-points-v2 = <&qup_opp_table>; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 status = "disabled"; 1505 }; 1506 }; 1507 1508 gpi_dma1: dma-controller@a00000 { 1509 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1510 reg = <0 0x00a00000 0 0x70000>; 1511 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1521 dma-channels = <10>; 1522 dma-channel-mask = <0x3f>; 1523 iommus = <&apps_smmu 0x56 0x0>; 1524 #dma-cells = <3>; 1525 status = "disabled"; 1526 }; 1527 1528 qupv3_id_1: geniqup@ac0000 { 1529 compatible = "qcom,geni-se-qup"; 1530 reg = <0x0 0x00ac0000 0x0 0x6000>; 1531 clock-names = "m-ahb", "s-ahb"; 1532 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1533 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1534 #address-cells = <2>; 1535 #size-cells = <2>; 1536 iommus = <&apps_smmu 0x43 0x0>; 1537 ranges; 1538 status = "disabled"; 1539 1540 i2c8: i2c@a80000 { 1541 compatible = "qcom,geni-i2c"; 1542 reg = <0 0x00a80000 0 0x4000>; 1543 clock-names = "se"; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1545 pinctrl-names = "default"; 1546 pinctrl-0 = <&qup_i2c8_default>; 1547 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1548 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1549 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1550 dma-names = "tx", "rx"; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 status = "disabled"; 1554 }; 1555 1556 spi8: spi@a80000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x00a80000 0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1561 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1562 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1563 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1564 dma-names = "tx", "rx"; 1565 power-domains = <&rpmhpd SM8250_CX>; 1566 operating-points-v2 = <&qup_opp_table>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 1572 i2c9: i2c@a84000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00a84000 0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&qup_i2c9_default>; 1579 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1580 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1581 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1582 dma-names = "tx", "rx"; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 spi9: spi@a84000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0 0x00a84000 0 0x4000>; 1591 clock-names = "se"; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1593 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1595 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1596 dma-names = "tx", "rx"; 1597 power-domains = <&rpmhpd SM8250_CX>; 1598 operating-points-v2 = <&qup_opp_table>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 i2c10: i2c@a88000 { 1605 compatible = "qcom,geni-i2c"; 1606 reg = <0 0x00a88000 0 0x4000>; 1607 clock-names = "se"; 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&qup_i2c10_default>; 1611 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1612 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1613 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1614 dma-names = "tx", "rx"; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 status = "disabled"; 1618 }; 1619 1620 spi10: spi@a88000 { 1621 compatible = "qcom,geni-spi"; 1622 reg = <0 0x00a88000 0 0x4000>; 1623 clock-names = "se"; 1624 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1625 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1626 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1627 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1628 dma-names = "tx", "rx"; 1629 power-domains = <&rpmhpd SM8250_CX>; 1630 operating-points-v2 = <&qup_opp_table>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 status = "disabled"; 1634 }; 1635 1636 i2c11: i2c@a8c000 { 1637 compatible = "qcom,geni-i2c"; 1638 reg = <0 0x00a8c000 0 0x4000>; 1639 clock-names = "se"; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&qup_i2c11_default>; 1643 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1644 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1645 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1646 dma-names = "tx", "rx"; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 status = "disabled"; 1650 }; 1651 1652 spi11: spi@a8c000 { 1653 compatible = "qcom,geni-spi"; 1654 reg = <0 0x00a8c000 0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1657 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1658 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1660 dma-names = "tx", "rx"; 1661 power-domains = <&rpmhpd SM8250_CX>; 1662 operating-points-v2 = <&qup_opp_table>; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 i2c12: i2c@a90000 { 1669 compatible = "qcom,geni-i2c"; 1670 reg = <0 0x00a90000 0 0x4000>; 1671 clock-names = "se"; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_i2c12_default>; 1675 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1676 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1677 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1678 dma-names = "tx", "rx"; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 status = "disabled"; 1682 }; 1683 1684 spi12: spi@a90000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a90000 0 0x4000>; 1687 clock-names = "se"; 1688 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1689 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1690 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1691 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1692 dma-names = "tx", "rx"; 1693 power-domains = <&rpmhpd SM8250_CX>; 1694 operating-points-v2 = <&qup_opp_table>; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 status = "disabled"; 1698 }; 1699 1700 uart12: serial@a90000 { 1701 compatible = "qcom,geni-debug-uart"; 1702 reg = <0x0 0x00a90000 0x0 0x4000>; 1703 clock-names = "se"; 1704 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1705 pinctrl-names = "default"; 1706 pinctrl-0 = <&qup_uart12_default>; 1707 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1708 power-domains = <&rpmhpd SM8250_CX>; 1709 operating-points-v2 = <&qup_opp_table>; 1710 status = "disabled"; 1711 }; 1712 1713 i2c13: i2c@a94000 { 1714 compatible = "qcom,geni-i2c"; 1715 reg = <0 0x00a94000 0 0x4000>; 1716 clock-names = "se"; 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_i2c13_default>; 1720 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1721 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1722 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1723 dma-names = "tx", "rx"; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 status = "disabled"; 1727 }; 1728 1729 spi13: spi@a94000 { 1730 compatible = "qcom,geni-spi"; 1731 reg = <0 0x00a94000 0 0x4000>; 1732 clock-names = "se"; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1734 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1735 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1736 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1737 dma-names = "tx", "rx"; 1738 power-domains = <&rpmhpd SM8250_CX>; 1739 operating-points-v2 = <&qup_opp_table>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 status = "disabled"; 1743 }; 1744 }; 1745 1746 config_noc: interconnect@1500000 { 1747 compatible = "qcom,sm8250-config-noc"; 1748 reg = <0 0x01500000 0 0xa580>; 1749 #interconnect-cells = <1>; 1750 qcom,bcm-voters = <&apps_bcm_voter>; 1751 }; 1752 1753 system_noc: interconnect@1620000 { 1754 compatible = "qcom,sm8250-system-noc"; 1755 reg = <0 0x01620000 0 0x1c200>; 1756 #interconnect-cells = <1>; 1757 qcom,bcm-voters = <&apps_bcm_voter>; 1758 }; 1759 1760 mc_virt: interconnect@163d000 { 1761 compatible = "qcom,sm8250-mc-virt"; 1762 reg = <0 0x0163d000 0 0x1000>; 1763 #interconnect-cells = <1>; 1764 qcom,bcm-voters = <&apps_bcm_voter>; 1765 }; 1766 1767 aggre1_noc: interconnect@16e0000 { 1768 compatible = "qcom,sm8250-aggre1-noc"; 1769 reg = <0 0x016e0000 0 0x1f180>; 1770 #interconnect-cells = <1>; 1771 qcom,bcm-voters = <&apps_bcm_voter>; 1772 }; 1773 1774 aggre2_noc: interconnect@1700000 { 1775 compatible = "qcom,sm8250-aggre2-noc"; 1776 reg = <0 0x01700000 0 0x33000>; 1777 #interconnect-cells = <1>; 1778 qcom,bcm-voters = <&apps_bcm_voter>; 1779 }; 1780 1781 compute_noc: interconnect@1733000 { 1782 compatible = "qcom,sm8250-compute-noc"; 1783 reg = <0 0x01733000 0 0xa180>; 1784 #interconnect-cells = <1>; 1785 qcom,bcm-voters = <&apps_bcm_voter>; 1786 }; 1787 1788 mmss_noc: interconnect@1740000 { 1789 compatible = "qcom,sm8250-mmss-noc"; 1790 reg = <0 0x01740000 0 0x1f080>; 1791 #interconnect-cells = <1>; 1792 qcom,bcm-voters = <&apps_bcm_voter>; 1793 }; 1794 1795 pcie0: pci@1c00000 { 1796 compatible = "qcom,pcie-sm8250"; 1797 reg = <0 0x01c00000 0 0x3000>, 1798 <0 0x60000000 0 0xf1d>, 1799 <0 0x60000f20 0 0xa8>, 1800 <0 0x60001000 0 0x1000>, 1801 <0 0x60100000 0 0x100000>; 1802 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1803 device_type = "pci"; 1804 linux,pci-domain = <0>; 1805 bus-range = <0x00 0xff>; 1806 num-lanes = <1>; 1807 1808 #address-cells = <3>; 1809 #size-cells = <2>; 1810 1811 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1812 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1813 1814 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1822 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1823 "msi4", "msi5", "msi6", "msi7"; 1824 #interrupt-cells = <1>; 1825 interrupt-map-mask = <0 0 0 0x7>; 1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1830 1831 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1832 <&gcc GCC_PCIE_0_AUX_CLK>, 1833 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1834 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1835 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1836 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1837 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1838 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1839 clock-names = "pipe", 1840 "aux", 1841 "cfg", 1842 "bus_master", 1843 "bus_slave", 1844 "slave_q2a", 1845 "tbu", 1846 "ddrss_sf_tbu"; 1847 1848 iommus = <&apps_smmu 0x1c00 0x7f>; 1849 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1850 <0x100 &apps_smmu 0x1c01 0x1>; 1851 1852 resets = <&gcc GCC_PCIE_0_BCR>; 1853 reset-names = "pci"; 1854 1855 power-domains = <&gcc PCIE_0_GDSC>; 1856 1857 phys = <&pcie0_lane>; 1858 phy-names = "pciephy"; 1859 1860 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1861 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1862 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&pcie0_default_state>; 1865 1866 status = "disabled"; 1867 }; 1868 1869 pcie0_phy: phy@1c06000 { 1870 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1871 reg = <0 0x01c06000 0 0x1c0>; 1872 #address-cells = <2>; 1873 #size-cells = <2>; 1874 ranges; 1875 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1876 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1877 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1878 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1879 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1880 1881 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1882 reset-names = "phy"; 1883 1884 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1885 assigned-clock-rates = <100000000>; 1886 1887 status = "disabled"; 1888 1889 pcie0_lane: phy@1c06200 { 1890 reg = <0 0x1c06200 0 0x170>, /* tx */ 1891 <0 0x1c06400 0 0x200>, /* rx */ 1892 <0 0x1c06800 0 0x1f0>, /* pcs */ 1893 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1894 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1895 clock-names = "pipe0"; 1896 1897 #phy-cells = <0>; 1898 1899 #clock-cells = <0>; 1900 clock-output-names = "pcie_0_pipe_clk"; 1901 }; 1902 }; 1903 1904 pcie1: pci@1c08000 { 1905 compatible = "qcom,pcie-sm8250"; 1906 reg = <0 0x01c08000 0 0x3000>, 1907 <0 0x40000000 0 0xf1d>, 1908 <0 0x40000f20 0 0xa8>, 1909 <0 0x40001000 0 0x1000>, 1910 <0 0x40100000 0 0x100000>; 1911 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1912 device_type = "pci"; 1913 linux,pci-domain = <1>; 1914 bus-range = <0x00 0xff>; 1915 num-lanes = <2>; 1916 1917 #address-cells = <3>; 1918 #size-cells = <2>; 1919 1920 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1921 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1922 1923 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1924 interrupt-names = "msi"; 1925 #interrupt-cells = <1>; 1926 interrupt-map-mask = <0 0 0 0x7>; 1927 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1928 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1929 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1930 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1931 1932 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1933 <&gcc GCC_PCIE_1_AUX_CLK>, 1934 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1935 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1936 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1937 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1938 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1939 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1940 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1941 clock-names = "pipe", 1942 "aux", 1943 "cfg", 1944 "bus_master", 1945 "bus_slave", 1946 "slave_q2a", 1947 "ref", 1948 "tbu", 1949 "ddrss_sf_tbu"; 1950 1951 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1952 assigned-clock-rates = <19200000>; 1953 1954 iommus = <&apps_smmu 0x1c80 0x7f>; 1955 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1956 <0x100 &apps_smmu 0x1c81 0x1>; 1957 1958 resets = <&gcc GCC_PCIE_1_BCR>; 1959 reset-names = "pci"; 1960 1961 power-domains = <&gcc PCIE_1_GDSC>; 1962 1963 phys = <&pcie1_lane>; 1964 phy-names = "pciephy"; 1965 1966 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1967 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1968 1969 pinctrl-names = "default"; 1970 pinctrl-0 = <&pcie1_default_state>; 1971 1972 status = "disabled"; 1973 }; 1974 1975 pcie1_phy: phy@1c0e000 { 1976 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1977 reg = <0 0x01c0e000 0 0x1c0>; 1978 #address-cells = <2>; 1979 #size-cells = <2>; 1980 ranges; 1981 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1982 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1983 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1984 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1985 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1986 1987 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1988 reset-names = "phy"; 1989 1990 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1991 assigned-clock-rates = <100000000>; 1992 1993 status = "disabled"; 1994 1995 pcie1_lane: phy@1c0e200 { 1996 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1997 <0 0x1c0e400 0 0x200>, /* rx0 */ 1998 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1999 <0 0x1c0e600 0 0x170>, /* tx1 */ 2000 <0 0x1c0e800 0 0x200>, /* rx1 */ 2001 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2002 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2003 clock-names = "pipe0"; 2004 2005 #phy-cells = <0>; 2006 2007 #clock-cells = <0>; 2008 clock-output-names = "pcie_1_pipe_clk"; 2009 }; 2010 }; 2011 2012 pcie2: pci@1c10000 { 2013 compatible = "qcom,pcie-sm8250"; 2014 reg = <0 0x01c10000 0 0x3000>, 2015 <0 0x64000000 0 0xf1d>, 2016 <0 0x64000f20 0 0xa8>, 2017 <0 0x64001000 0 0x1000>, 2018 <0 0x64100000 0 0x100000>; 2019 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2020 device_type = "pci"; 2021 linux,pci-domain = <2>; 2022 bus-range = <0x00 0xff>; 2023 num-lanes = <2>; 2024 2025 #address-cells = <3>; 2026 #size-cells = <2>; 2027 2028 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2029 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2030 2031 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2032 interrupt-names = "msi"; 2033 #interrupt-cells = <1>; 2034 interrupt-map-mask = <0 0 0 0x7>; 2035 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2036 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2037 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2038 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2039 2040 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2041 <&gcc GCC_PCIE_2_AUX_CLK>, 2042 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2043 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2044 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2045 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2046 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2047 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2048 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2049 clock-names = "pipe", 2050 "aux", 2051 "cfg", 2052 "bus_master", 2053 "bus_slave", 2054 "slave_q2a", 2055 "ref", 2056 "tbu", 2057 "ddrss_sf_tbu"; 2058 2059 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2060 assigned-clock-rates = <19200000>; 2061 2062 iommus = <&apps_smmu 0x1d00 0x7f>; 2063 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2064 <0x100 &apps_smmu 0x1d01 0x1>; 2065 2066 resets = <&gcc GCC_PCIE_2_BCR>; 2067 reset-names = "pci"; 2068 2069 power-domains = <&gcc PCIE_2_GDSC>; 2070 2071 phys = <&pcie2_lane>; 2072 phy-names = "pciephy"; 2073 2074 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2075 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2076 2077 pinctrl-names = "default"; 2078 pinctrl-0 = <&pcie2_default_state>; 2079 2080 status = "disabled"; 2081 }; 2082 2083 pcie2_phy: phy@1c16000 { 2084 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2085 reg = <0 0x1c16000 0 0x1c0>; 2086 #address-cells = <2>; 2087 #size-cells = <2>; 2088 ranges; 2089 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2090 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2091 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2092 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2093 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2094 2095 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2096 reset-names = "phy"; 2097 2098 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2099 assigned-clock-rates = <100000000>; 2100 2101 status = "disabled"; 2102 2103 pcie2_lane: phy@1c16200 { 2104 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 2105 <0 0x1c16400 0 0x200>, /* rx0 */ 2106 <0 0x1c16a00 0 0x1f0>, /* pcs */ 2107 <0 0x1c16600 0 0x170>, /* tx1 */ 2108 <0 0x1c16800 0 0x200>, /* rx1 */ 2109 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2110 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2111 clock-names = "pipe0"; 2112 2113 #phy-cells = <0>; 2114 2115 #clock-cells = <0>; 2116 clock-output-names = "pcie_2_pipe_clk"; 2117 }; 2118 }; 2119 2120 ufs_mem_hc: ufshc@1d84000 { 2121 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2122 "jedec,ufs-2.0"; 2123 reg = <0 0x01d84000 0 0x3000>; 2124 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2125 phys = <&ufs_mem_phy_lanes>; 2126 phy-names = "ufsphy"; 2127 lanes-per-direction = <2>; 2128 #reset-cells = <1>; 2129 resets = <&gcc GCC_UFS_PHY_BCR>; 2130 reset-names = "rst"; 2131 2132 power-domains = <&gcc UFS_PHY_GDSC>; 2133 2134 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2135 2136 clock-names = 2137 "core_clk", 2138 "bus_aggr_clk", 2139 "iface_clk", 2140 "core_clk_unipro", 2141 "ref_clk", 2142 "tx_lane0_sync_clk", 2143 "rx_lane0_sync_clk", 2144 "rx_lane1_sync_clk"; 2145 clocks = 2146 <&gcc GCC_UFS_PHY_AXI_CLK>, 2147 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2148 <&gcc GCC_UFS_PHY_AHB_CLK>, 2149 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2150 <&rpmhcc RPMH_CXO_CLK>, 2151 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2152 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2153 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2154 freq-table-hz = 2155 <37500000 300000000>, 2156 <0 0>, 2157 <0 0>, 2158 <37500000 300000000>, 2159 <0 0>, 2160 <0 0>, 2161 <0 0>, 2162 <0 0>; 2163 2164 status = "disabled"; 2165 }; 2166 2167 ufs_mem_phy: phy@1d87000 { 2168 compatible = "qcom,sm8250-qmp-ufs-phy"; 2169 reg = <0 0x01d87000 0 0x1c0>; 2170 #address-cells = <2>; 2171 #size-cells = <2>; 2172 ranges; 2173 clock-names = "ref", 2174 "ref_aux"; 2175 clocks = <&rpmhcc RPMH_CXO_CLK>, 2176 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2177 2178 resets = <&ufs_mem_hc 0>; 2179 reset-names = "ufsphy"; 2180 status = "disabled"; 2181 2182 ufs_mem_phy_lanes: phy@1d87400 { 2183 reg = <0 0x01d87400 0 0x16c>, 2184 <0 0x01d87600 0 0x200>, 2185 <0 0x01d87c00 0 0x200>, 2186 <0 0x01d87800 0 0x16c>, 2187 <0 0x01d87a00 0 0x200>; 2188 #phy-cells = <0>; 2189 }; 2190 }; 2191 2192 ipa_virt: interconnect@1e00000 { 2193 compatible = "qcom,sm8250-ipa-virt"; 2194 reg = <0 0x01e00000 0 0x1000>; 2195 #interconnect-cells = <1>; 2196 qcom,bcm-voters = <&apps_bcm_voter>; 2197 }; 2198 2199 tcsr_mutex: hwlock@1f40000 { 2200 compatible = "qcom,tcsr-mutex"; 2201 reg = <0x0 0x01f40000 0x0 0x40000>; 2202 #hwlock-cells = <1>; 2203 }; 2204 2205 wsamacro: codec@3240000 { 2206 compatible = "qcom,sm8250-lpass-wsa-macro"; 2207 reg = <0 0x03240000 0 0x1000>; 2208 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2209 <&audiocc LPASS_CDC_WSA_NPL>, 2210 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2211 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2212 <&aoncc LPASS_CDC_VA_MCLK>, 2213 <&vamacro>; 2214 2215 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2216 2217 #clock-cells = <0>; 2218 clock-frequency = <9600000>; 2219 clock-output-names = "mclk"; 2220 #sound-dai-cells = <1>; 2221 2222 pinctrl-names = "default"; 2223 pinctrl-0 = <&wsa_swr_active>; 2224 }; 2225 2226 swr0: soundwire-controller@3250000 { 2227 reg = <0 0x03250000 0 0x2000>; 2228 compatible = "qcom,soundwire-v1.5.1"; 2229 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2230 clocks = <&wsamacro>; 2231 clock-names = "iface"; 2232 2233 qcom,din-ports = <2>; 2234 qcom,dout-ports = <6>; 2235 2236 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2237 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2238 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2239 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2240 2241 #sound-dai-cells = <1>; 2242 #address-cells = <2>; 2243 #size-cells = <0>; 2244 }; 2245 2246 audiocc: clock-controller@3300000 { 2247 compatible = "qcom,sm8250-lpass-audiocc"; 2248 reg = <0 0x03300000 0 0x30000>; 2249 #clock-cells = <1>; 2250 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2251 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2252 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2253 clock-names = "core", "audio", "bus"; 2254 }; 2255 2256 vamacro: codec@3370000 { 2257 compatible = "qcom,sm8250-lpass-va-macro"; 2258 reg = <0 0x03370000 0 0x1000>; 2259 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2260 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2262 2263 clock-names = "mclk", "macro", "dcodec"; 2264 2265 #clock-cells = <0>; 2266 clock-frequency = <9600000>; 2267 clock-output-names = "fsgen"; 2268 #sound-dai-cells = <1>; 2269 }; 2270 2271 rxmacro: rxmacro@3200000 { 2272 pinctrl-names = "default"; 2273 pinctrl-0 = <&rx_swr_active>; 2274 compatible = "qcom,sm8250-lpass-rx-macro"; 2275 reg = <0 0x3200000 0 0x1000>; 2276 status = "disabled"; 2277 2278 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2279 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2280 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2281 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2282 <&vamacro>; 2283 2284 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2285 2286 #clock-cells = <0>; 2287 clock-frequency = <9600000>; 2288 clock-output-names = "mclk"; 2289 #sound-dai-cells = <1>; 2290 }; 2291 2292 swr1: soundwire-controller@3210000 { 2293 reg = <0 0x3210000 0 0x2000>; 2294 compatible = "qcom,soundwire-v1.5.1"; 2295 status = "disabled"; 2296 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2297 clocks = <&rxmacro>; 2298 clock-names = "iface"; 2299 label = "RX"; 2300 qcom,din-ports = <0>; 2301 qcom,dout-ports = <5>; 2302 2303 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 2304 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2305 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2306 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 2307 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 2308 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 2309 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 2310 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2311 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 2312 2313 #sound-dai-cells = <1>; 2314 #address-cells = <2>; 2315 #size-cells = <0>; 2316 }; 2317 2318 txmacro: txmacro@3220000 { 2319 pinctrl-names = "default"; 2320 pinctrl-0 = <&tx_swr_active>; 2321 compatible = "qcom,sm8250-lpass-tx-macro"; 2322 reg = <0 0x3220000 0 0x1000>; 2323 status = "disabled"; 2324 2325 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2326 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2327 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2328 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2329 <&vamacro>; 2330 2331 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2332 2333 #clock-cells = <0>; 2334 clock-frequency = <9600000>; 2335 clock-output-names = "mclk"; 2336 #address-cells = <2>; 2337 #size-cells = <2>; 2338 #sound-dai-cells = <1>; 2339 }; 2340 2341 /* tx macro */ 2342 swr2: soundwire-controller@3230000 { 2343 reg = <0 0x3230000 0 0x2000>; 2344 compatible = "qcom,soundwire-v1.5.1"; 2345 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2346 interrupt-names = "core"; 2347 status = "disabled"; 2348 2349 clocks = <&txmacro>; 2350 clock-names = "iface"; 2351 label = "TX"; 2352 2353 qcom,din-ports = <5>; 2354 qcom,dout-ports = <0>; 2355 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 2356 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 2357 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 2358 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2359 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2360 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2361 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2362 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2363 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 2364 #sound-dai-cells = <1>; 2365 #address-cells = <2>; 2366 #size-cells = <0>; 2367 }; 2368 2369 aoncc: clock-controller@3380000 { 2370 compatible = "qcom,sm8250-lpass-aoncc"; 2371 reg = <0 0x03380000 0 0x40000>; 2372 #clock-cells = <1>; 2373 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2374 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2375 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2376 clock-names = "core", "audio", "bus"; 2377 }; 2378 2379 lpass_tlmm: pinctrl@33c0000{ 2380 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2381 reg = <0 0x033c0000 0x0 0x20000>, 2382 <0 0x03550000 0x0 0x10000>; 2383 gpio-controller; 2384 #gpio-cells = <2>; 2385 gpio-ranges = <&lpass_tlmm 0 0 14>; 2386 2387 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2388 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2389 clock-names = "core", "audio"; 2390 2391 wsa_swr_active: wsa-swr-active-state { 2392 clk-pins { 2393 pins = "gpio10"; 2394 function = "wsa_swr_clk"; 2395 drive-strength = <2>; 2396 slew-rate = <1>; 2397 bias-disable; 2398 }; 2399 2400 data-pins { 2401 pins = "gpio11"; 2402 function = "wsa_swr_data"; 2403 drive-strength = <2>; 2404 slew-rate = <1>; 2405 bias-bus-hold; 2406 2407 }; 2408 }; 2409 2410 wsa_swr_sleep: wsa-swr-sleep-state { 2411 clk-pins { 2412 pins = "gpio10"; 2413 function = "wsa_swr_clk"; 2414 drive-strength = <2>; 2415 input-enable; 2416 bias-pull-down; 2417 }; 2418 2419 data-pins { 2420 pins = "gpio11"; 2421 function = "wsa_swr_data"; 2422 drive-strength = <2>; 2423 input-enable; 2424 bias-pull-down; 2425 2426 }; 2427 }; 2428 2429 dmic01_active: dmic01-active-state { 2430 clk-pins { 2431 pins = "gpio6"; 2432 function = "dmic1_clk"; 2433 drive-strength = <8>; 2434 output-high; 2435 }; 2436 data-pins { 2437 pins = "gpio7"; 2438 function = "dmic1_data"; 2439 drive-strength = <8>; 2440 input-enable; 2441 }; 2442 }; 2443 2444 dmic01_sleep: dmic01-sleep-state { 2445 clk-pins { 2446 pins = "gpio6"; 2447 function = "dmic1_clk"; 2448 drive-strength = <2>; 2449 bias-disable; 2450 output-low; 2451 }; 2452 2453 data-pins { 2454 pins = "gpio7"; 2455 function = "dmic1_data"; 2456 drive-strength = <2>; 2457 bias-pull-down; 2458 input-enable; 2459 }; 2460 }; 2461 2462 rx_swr_active: rx-swr-active-state { 2463 clk-pins { 2464 pins = "gpio3"; 2465 function = "swr_rx_clk"; 2466 drive-strength = <2>; 2467 slew-rate = <1>; 2468 bias-disable; 2469 }; 2470 2471 data-pins { 2472 pins = "gpio4", "gpio5"; 2473 function = "swr_rx_data"; 2474 drive-strength = <2>; 2475 slew-rate = <1>; 2476 bias-bus-hold; 2477 }; 2478 }; 2479 2480 tx_swr_active: tx-swr-active-state { 2481 clk-pins { 2482 pins = "gpio0"; 2483 function = "swr_tx_clk"; 2484 drive-strength = <2>; 2485 slew-rate = <1>; 2486 bias-disable; 2487 }; 2488 2489 data-pins { 2490 pins = "gpio1", "gpio2"; 2491 function = "swr_tx_data"; 2492 drive-strength = <2>; 2493 slew-rate = <1>; 2494 bias-bus-hold; 2495 }; 2496 }; 2497 2498 tx_swr_sleep: tx-swr-sleep-state { 2499 clk-pins { 2500 pins = "gpio0"; 2501 function = "swr_tx_clk"; 2502 drive-strength = <2>; 2503 input-enable; 2504 bias-pull-down; 2505 }; 2506 2507 data1-pins { 2508 pins = "gpio1"; 2509 function = "swr_tx_data"; 2510 drive-strength = <2>; 2511 input-enable; 2512 bias-bus-hold; 2513 }; 2514 2515 data2-pins { 2516 pins = "gpio2"; 2517 function = "swr_tx_data"; 2518 drive-strength = <2>; 2519 input-enable; 2520 bias-pull-down; 2521 }; 2522 }; 2523 }; 2524 2525 gpu: gpu@3d00000 { 2526 compatible = "qcom,adreno-650.2", 2527 "qcom,adreno"; 2528 2529 reg = <0 0x03d00000 0 0x40000>; 2530 reg-names = "kgsl_3d0_reg_memory"; 2531 2532 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2533 2534 iommus = <&adreno_smmu 0 0x401>; 2535 2536 operating-points-v2 = <&gpu_opp_table>; 2537 2538 qcom,gmu = <&gmu>; 2539 2540 status = "disabled"; 2541 2542 zap-shader { 2543 memory-region = <&gpu_mem>; 2544 }; 2545 2546 /* note: downstream checks gpu binning for 670 Mhz */ 2547 gpu_opp_table: opp-table { 2548 compatible = "operating-points-v2"; 2549 2550 opp-670000000 { 2551 opp-hz = /bits/ 64 <670000000>; 2552 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2553 }; 2554 2555 opp-587000000 { 2556 opp-hz = /bits/ 64 <587000000>; 2557 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2558 }; 2559 2560 opp-525000000 { 2561 opp-hz = /bits/ 64 <525000000>; 2562 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2563 }; 2564 2565 opp-490000000 { 2566 opp-hz = /bits/ 64 <490000000>; 2567 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2568 }; 2569 2570 opp-441600000 { 2571 opp-hz = /bits/ 64 <441600000>; 2572 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2573 }; 2574 2575 opp-400000000 { 2576 opp-hz = /bits/ 64 <400000000>; 2577 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2578 }; 2579 2580 opp-305000000 { 2581 opp-hz = /bits/ 64 <305000000>; 2582 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2583 }; 2584 }; 2585 }; 2586 2587 gmu: gmu@3d6a000 { 2588 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2589 2590 reg = <0 0x03d6a000 0 0x30000>, 2591 <0 0x3de0000 0 0x10000>, 2592 <0 0xb290000 0 0x10000>, 2593 <0 0xb490000 0 0x10000>; 2594 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2595 2596 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2598 interrupt-names = "hfi", "gmu"; 2599 2600 clocks = <&gpucc GPU_CC_AHB_CLK>, 2601 <&gpucc GPU_CC_CX_GMU_CLK>, 2602 <&gpucc GPU_CC_CXO_CLK>, 2603 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2604 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2605 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2606 2607 power-domains = <&gpucc GPU_CX_GDSC>, 2608 <&gpucc GPU_GX_GDSC>; 2609 power-domain-names = "cx", "gx"; 2610 2611 iommus = <&adreno_smmu 5 0x400>; 2612 2613 operating-points-v2 = <&gmu_opp_table>; 2614 2615 status = "disabled"; 2616 2617 gmu_opp_table: opp-table { 2618 compatible = "operating-points-v2"; 2619 2620 opp-200000000 { 2621 opp-hz = /bits/ 64 <200000000>; 2622 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2623 }; 2624 }; 2625 }; 2626 2627 gpucc: clock-controller@3d90000 { 2628 compatible = "qcom,sm8250-gpucc"; 2629 reg = <0 0x03d90000 0 0x9000>; 2630 clocks = <&rpmhcc RPMH_CXO_CLK>, 2631 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2632 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2633 clock-names = "bi_tcxo", 2634 "gcc_gpu_gpll0_clk_src", 2635 "gcc_gpu_gpll0_div_clk_src"; 2636 #clock-cells = <1>; 2637 #reset-cells = <1>; 2638 #power-domain-cells = <1>; 2639 }; 2640 2641 adreno_smmu: iommu@3da0000 { 2642 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2643 reg = <0 0x03da0000 0 0x10000>; 2644 #iommu-cells = <2>; 2645 #global-interrupts = <2>; 2646 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2647 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2648 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2649 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2650 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2651 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2652 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2653 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2656 clocks = <&gpucc GPU_CC_AHB_CLK>, 2657 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2658 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2659 clock-names = "ahb", "bus", "iface"; 2660 2661 power-domains = <&gpucc GPU_CX_GDSC>; 2662 }; 2663 2664 slpi: remoteproc@5c00000 { 2665 compatible = "qcom,sm8250-slpi-pas"; 2666 reg = <0 0x05c00000 0 0x4000>; 2667 2668 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2669 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2670 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2671 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2672 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2673 interrupt-names = "wdog", "fatal", "ready", 2674 "handover", "stop-ack"; 2675 2676 clocks = <&rpmhcc RPMH_CXO_CLK>; 2677 clock-names = "xo"; 2678 2679 power-domains = <&rpmhpd SM8250_LCX>, 2680 <&rpmhpd SM8250_LMX>; 2681 power-domain-names = "lcx", "lmx"; 2682 2683 memory-region = <&slpi_mem>; 2684 2685 qcom,qmp = <&aoss_qmp>; 2686 2687 qcom,smem-states = <&smp2p_slpi_out 0>; 2688 qcom,smem-state-names = "stop"; 2689 2690 status = "disabled"; 2691 2692 glink-edge { 2693 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2694 IPCC_MPROC_SIGNAL_GLINK_QMP 2695 IRQ_TYPE_EDGE_RISING>; 2696 mboxes = <&ipcc IPCC_CLIENT_SLPI 2697 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2698 2699 label = "slpi"; 2700 qcom,remote-pid = <3>; 2701 2702 fastrpc { 2703 compatible = "qcom,fastrpc"; 2704 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2705 label = "sdsp"; 2706 qcom,non-secure-domain; 2707 #address-cells = <1>; 2708 #size-cells = <0>; 2709 2710 compute-cb@1 { 2711 compatible = "qcom,fastrpc-compute-cb"; 2712 reg = <1>; 2713 iommus = <&apps_smmu 0x0541 0x0>; 2714 }; 2715 2716 compute-cb@2 { 2717 compatible = "qcom,fastrpc-compute-cb"; 2718 reg = <2>; 2719 iommus = <&apps_smmu 0x0542 0x0>; 2720 }; 2721 2722 compute-cb@3 { 2723 compatible = "qcom,fastrpc-compute-cb"; 2724 reg = <3>; 2725 iommus = <&apps_smmu 0x0543 0x0>; 2726 /* note: shared-cb = <4> in downstream */ 2727 }; 2728 }; 2729 }; 2730 }; 2731 2732 stm@6002000 { 2733 compatible = "arm,coresight-stm", "arm,primecell"; 2734 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2735 reg-names = "stm-base", "stm-stimulus-base"; 2736 2737 clocks = <&aoss_qmp>; 2738 clock-names = "apb_pclk"; 2739 2740 out-ports { 2741 port { 2742 stm_out: endpoint { 2743 remote-endpoint = <&funnel0_in7>; 2744 }; 2745 }; 2746 }; 2747 }; 2748 2749 funnel@6041000 { 2750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2751 reg = <0 0x06041000 0 0x1000>; 2752 2753 clocks = <&aoss_qmp>; 2754 clock-names = "apb_pclk"; 2755 2756 out-ports { 2757 port { 2758 funnel_in0_out_funnel_merg: endpoint { 2759 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2760 }; 2761 }; 2762 }; 2763 2764 in-ports { 2765 #address-cells = <1>; 2766 #size-cells = <0>; 2767 2768 port@7 { 2769 reg = <7>; 2770 funnel0_in7: endpoint { 2771 remote-endpoint = <&stm_out>; 2772 }; 2773 }; 2774 }; 2775 }; 2776 2777 funnel@6042000 { 2778 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2779 reg = <0 0x06042000 0 0x1000>; 2780 2781 clocks = <&aoss_qmp>; 2782 clock-names = "apb_pclk"; 2783 2784 out-ports { 2785 #address-cells = <1>; 2786 #size-cells = <0>; 2787 2788 port@0 { 2789 reg = <0>; 2790 funnel_in1_out_funnel_merg: endpoint { 2791 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2792 }; 2793 }; 2794 }; 2795 2796 in-ports { 2797 #address-cells = <1>; 2798 #size-cells = <0>; 2799 2800 port@4 { 2801 reg = <4>; 2802 funnel_in1_in_funnel_apss_merg: endpoint { 2803 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2804 }; 2805 }; 2806 }; 2807 }; 2808 2809 funnel@6045000 { 2810 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2811 reg = <0 0x06045000 0 0x1000>; 2812 2813 clocks = <&aoss_qmp>; 2814 clock-names = "apb_pclk"; 2815 2816 out-ports { 2817 port { 2818 funnel_merg_out_funnel_swao: endpoint { 2819 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2820 }; 2821 }; 2822 }; 2823 2824 in-ports { 2825 #address-cells = <1>; 2826 #size-cells = <0>; 2827 2828 port@0 { 2829 reg = <0>; 2830 funnel_merg_in_funnel_in0: endpoint { 2831 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2832 }; 2833 }; 2834 2835 port@1 { 2836 reg = <1>; 2837 funnel_merg_in_funnel_in1: endpoint { 2838 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2839 }; 2840 }; 2841 }; 2842 }; 2843 2844 replicator@6046000 { 2845 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2846 reg = <0 0x06046000 0 0x1000>; 2847 2848 clocks = <&aoss_qmp>; 2849 clock-names = "apb_pclk"; 2850 2851 out-ports { 2852 port { 2853 replicator_out: endpoint { 2854 remote-endpoint = <&etr_in>; 2855 }; 2856 }; 2857 }; 2858 2859 in-ports { 2860 port { 2861 replicator_cx_in_swao_out: endpoint { 2862 remote-endpoint = <&replicator_swao_out_cx_in>; 2863 }; 2864 }; 2865 }; 2866 }; 2867 2868 etr@6048000 { 2869 compatible = "arm,coresight-tmc", "arm,primecell"; 2870 reg = <0 0x06048000 0 0x1000>; 2871 2872 clocks = <&aoss_qmp>; 2873 clock-names = "apb_pclk"; 2874 arm,scatter-gather; 2875 2876 in-ports { 2877 port { 2878 etr_in: endpoint { 2879 remote-endpoint = <&replicator_out>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 funnel@6b04000 { 2886 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2887 arm,primecell-periphid = <0x000bb908>; 2888 2889 reg = <0 0x06b04000 0 0x1000>; 2890 reg-names = "funnel-base"; 2891 2892 clocks = <&aoss_qmp>; 2893 clock-names = "apb_pclk"; 2894 2895 out-ports { 2896 port { 2897 funnel_swao_out_etf: endpoint { 2898 remote-endpoint = <&etf_in_funnel_swao_out>; 2899 }; 2900 }; 2901 }; 2902 2903 in-ports { 2904 #address-cells = <1>; 2905 #size-cells = <0>; 2906 2907 port@7 { 2908 reg = <7>; 2909 funnel_swao_in_funnel_merg: endpoint { 2910 remote-endpoint= <&funnel_merg_out_funnel_swao>; 2911 }; 2912 }; 2913 }; 2914 2915 }; 2916 2917 etf@6b05000 { 2918 compatible = "arm,coresight-tmc", "arm,primecell"; 2919 reg = <0 0x06b05000 0 0x1000>; 2920 2921 clocks = <&aoss_qmp>; 2922 clock-names = "apb_pclk"; 2923 2924 out-ports { 2925 port { 2926 etf_out: endpoint { 2927 remote-endpoint = <&replicator_in>; 2928 }; 2929 }; 2930 }; 2931 2932 in-ports { 2933 #address-cells = <1>; 2934 #size-cells = <0>; 2935 2936 port@0 { 2937 reg = <0>; 2938 etf_in_funnel_swao_out: endpoint { 2939 remote-endpoint = <&funnel_swao_out_etf>; 2940 }; 2941 }; 2942 }; 2943 }; 2944 2945 replicator@6b06000 { 2946 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2947 reg = <0 0x06b06000 0 0x1000>; 2948 2949 clocks = <&aoss_qmp>; 2950 clock-names = "apb_pclk"; 2951 2952 out-ports { 2953 port { 2954 replicator_swao_out_cx_in: endpoint { 2955 remote-endpoint = <&replicator_cx_in_swao_out>; 2956 }; 2957 }; 2958 }; 2959 2960 in-ports { 2961 port { 2962 replicator_in: endpoint { 2963 remote-endpoint = <&etf_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 etm@7040000 { 2970 compatible = "arm,coresight-etm4x", "arm,primecell"; 2971 reg = <0 0x07040000 0 0x1000>; 2972 2973 cpu = <&CPU0>; 2974 2975 clocks = <&aoss_qmp>; 2976 clock-names = "apb_pclk"; 2977 arm,coresight-loses-context-with-cpu; 2978 2979 out-ports { 2980 port { 2981 etm0_out: endpoint { 2982 remote-endpoint = <&apss_funnel_in0>; 2983 }; 2984 }; 2985 }; 2986 }; 2987 2988 etm@7140000 { 2989 compatible = "arm,coresight-etm4x", "arm,primecell"; 2990 reg = <0 0x07140000 0 0x1000>; 2991 2992 cpu = <&CPU1>; 2993 2994 clocks = <&aoss_qmp>; 2995 clock-names = "apb_pclk"; 2996 arm,coresight-loses-context-with-cpu; 2997 2998 out-ports { 2999 port { 3000 etm1_out: endpoint { 3001 remote-endpoint = <&apss_funnel_in1>; 3002 }; 3003 }; 3004 }; 3005 }; 3006 3007 etm@7240000 { 3008 compatible = "arm,coresight-etm4x", "arm,primecell"; 3009 reg = <0 0x07240000 0 0x1000>; 3010 3011 cpu = <&CPU2>; 3012 3013 clocks = <&aoss_qmp>; 3014 clock-names = "apb_pclk"; 3015 arm,coresight-loses-context-with-cpu; 3016 3017 out-ports { 3018 port { 3019 etm2_out: endpoint { 3020 remote-endpoint = <&apss_funnel_in2>; 3021 }; 3022 }; 3023 }; 3024 }; 3025 3026 etm@7340000 { 3027 compatible = "arm,coresight-etm4x", "arm,primecell"; 3028 reg = <0 0x07340000 0 0x1000>; 3029 3030 cpu = <&CPU3>; 3031 3032 clocks = <&aoss_qmp>; 3033 clock-names = "apb_pclk"; 3034 arm,coresight-loses-context-with-cpu; 3035 3036 out-ports { 3037 port { 3038 etm3_out: endpoint { 3039 remote-endpoint = <&apss_funnel_in3>; 3040 }; 3041 }; 3042 }; 3043 }; 3044 3045 etm@7440000 { 3046 compatible = "arm,coresight-etm4x", "arm,primecell"; 3047 reg = <0 0x07440000 0 0x1000>; 3048 3049 cpu = <&CPU4>; 3050 3051 clocks = <&aoss_qmp>; 3052 clock-names = "apb_pclk"; 3053 arm,coresight-loses-context-with-cpu; 3054 3055 out-ports { 3056 port { 3057 etm4_out: endpoint { 3058 remote-endpoint = <&apss_funnel_in4>; 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 etm@7540000 { 3065 compatible = "arm,coresight-etm4x", "arm,primecell"; 3066 reg = <0 0x07540000 0 0x1000>; 3067 3068 cpu = <&CPU5>; 3069 3070 clocks = <&aoss_qmp>; 3071 clock-names = "apb_pclk"; 3072 arm,coresight-loses-context-with-cpu; 3073 3074 out-ports { 3075 port { 3076 etm5_out: endpoint { 3077 remote-endpoint = <&apss_funnel_in5>; 3078 }; 3079 }; 3080 }; 3081 }; 3082 3083 etm@7640000 { 3084 compatible = "arm,coresight-etm4x", "arm,primecell"; 3085 reg = <0 0x07640000 0 0x1000>; 3086 3087 cpu = <&CPU6>; 3088 3089 clocks = <&aoss_qmp>; 3090 clock-names = "apb_pclk"; 3091 arm,coresight-loses-context-with-cpu; 3092 3093 out-ports { 3094 port { 3095 etm6_out: endpoint { 3096 remote-endpoint = <&apss_funnel_in6>; 3097 }; 3098 }; 3099 }; 3100 }; 3101 3102 etm@7740000 { 3103 compatible = "arm,coresight-etm4x", "arm,primecell"; 3104 reg = <0 0x07740000 0 0x1000>; 3105 3106 cpu = <&CPU7>; 3107 3108 clocks = <&aoss_qmp>; 3109 clock-names = "apb_pclk"; 3110 arm,coresight-loses-context-with-cpu; 3111 3112 out-ports { 3113 port { 3114 etm7_out: endpoint { 3115 remote-endpoint = <&apss_funnel_in7>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 funnel@7800000 { 3122 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3123 reg = <0 0x07800000 0 0x1000>; 3124 3125 clocks = <&aoss_qmp>; 3126 clock-names = "apb_pclk"; 3127 3128 out-ports { 3129 port { 3130 funnel_apss_out_funnel_apss_merg: endpoint { 3131 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3132 }; 3133 }; 3134 }; 3135 3136 in-ports { 3137 #address-cells = <1>; 3138 #size-cells = <0>; 3139 3140 port@0 { 3141 reg = <0>; 3142 apss_funnel_in0: endpoint { 3143 remote-endpoint = <&etm0_out>; 3144 }; 3145 }; 3146 3147 port@1 { 3148 reg = <1>; 3149 apss_funnel_in1: endpoint { 3150 remote-endpoint = <&etm1_out>; 3151 }; 3152 }; 3153 3154 port@2 { 3155 reg = <2>; 3156 apss_funnel_in2: endpoint { 3157 remote-endpoint = <&etm2_out>; 3158 }; 3159 }; 3160 3161 port@3 { 3162 reg = <3>; 3163 apss_funnel_in3: endpoint { 3164 remote-endpoint = <&etm3_out>; 3165 }; 3166 }; 3167 3168 port@4 { 3169 reg = <4>; 3170 apss_funnel_in4: endpoint { 3171 remote-endpoint = <&etm4_out>; 3172 }; 3173 }; 3174 3175 port@5 { 3176 reg = <5>; 3177 apss_funnel_in5: endpoint { 3178 remote-endpoint = <&etm5_out>; 3179 }; 3180 }; 3181 3182 port@6 { 3183 reg = <6>; 3184 apss_funnel_in6: endpoint { 3185 remote-endpoint = <&etm6_out>; 3186 }; 3187 }; 3188 3189 port@7 { 3190 reg = <7>; 3191 apss_funnel_in7: endpoint { 3192 remote-endpoint = <&etm7_out>; 3193 }; 3194 }; 3195 }; 3196 }; 3197 3198 funnel@7810000 { 3199 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3200 reg = <0 0x07810000 0 0x1000>; 3201 3202 clocks = <&aoss_qmp>; 3203 clock-names = "apb_pclk"; 3204 3205 out-ports { 3206 #address-cells = <1>; 3207 #size-cells = <0>; 3208 3209 port { 3210 funnel_apss_merg_out_funnel_in1: endpoint { 3211 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3212 }; 3213 }; 3214 }; 3215 3216 in-ports { 3217 #address-cells = <1>; 3218 #size-cells = <0>; 3219 3220 port@0 { 3221 reg = <0>; 3222 funnel_apss_merg_in_funnel_apss: endpoint { 3223 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3224 }; 3225 }; 3226 }; 3227 }; 3228 3229 cdsp: remoteproc@8300000 { 3230 compatible = "qcom,sm8250-cdsp-pas"; 3231 reg = <0 0x08300000 0 0x10000>; 3232 3233 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3234 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3235 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3236 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3237 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3238 interrupt-names = "wdog", "fatal", "ready", 3239 "handover", "stop-ack"; 3240 3241 clocks = <&rpmhcc RPMH_CXO_CLK>; 3242 clock-names = "xo"; 3243 3244 power-domains = <&rpmhpd SM8250_CX>; 3245 3246 memory-region = <&cdsp_mem>; 3247 3248 qcom,qmp = <&aoss_qmp>; 3249 3250 qcom,smem-states = <&smp2p_cdsp_out 0>; 3251 qcom,smem-state-names = "stop"; 3252 3253 status = "disabled"; 3254 3255 glink-edge { 3256 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3257 IPCC_MPROC_SIGNAL_GLINK_QMP 3258 IRQ_TYPE_EDGE_RISING>; 3259 mboxes = <&ipcc IPCC_CLIENT_CDSP 3260 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3261 3262 label = "cdsp"; 3263 qcom,remote-pid = <5>; 3264 3265 fastrpc { 3266 compatible = "qcom,fastrpc"; 3267 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3268 label = "cdsp"; 3269 qcom,non-secure-domain; 3270 #address-cells = <1>; 3271 #size-cells = <0>; 3272 3273 compute-cb@1 { 3274 compatible = "qcom,fastrpc-compute-cb"; 3275 reg = <1>; 3276 iommus = <&apps_smmu 0x1001 0x0460>; 3277 }; 3278 3279 compute-cb@2 { 3280 compatible = "qcom,fastrpc-compute-cb"; 3281 reg = <2>; 3282 iommus = <&apps_smmu 0x1002 0x0460>; 3283 }; 3284 3285 compute-cb@3 { 3286 compatible = "qcom,fastrpc-compute-cb"; 3287 reg = <3>; 3288 iommus = <&apps_smmu 0x1003 0x0460>; 3289 }; 3290 3291 compute-cb@4 { 3292 compatible = "qcom,fastrpc-compute-cb"; 3293 reg = <4>; 3294 iommus = <&apps_smmu 0x1004 0x0460>; 3295 }; 3296 3297 compute-cb@5 { 3298 compatible = "qcom,fastrpc-compute-cb"; 3299 reg = <5>; 3300 iommus = <&apps_smmu 0x1005 0x0460>; 3301 }; 3302 3303 compute-cb@6 { 3304 compatible = "qcom,fastrpc-compute-cb"; 3305 reg = <6>; 3306 iommus = <&apps_smmu 0x1006 0x0460>; 3307 }; 3308 3309 compute-cb@7 { 3310 compatible = "qcom,fastrpc-compute-cb"; 3311 reg = <7>; 3312 iommus = <&apps_smmu 0x1007 0x0460>; 3313 }; 3314 3315 compute-cb@8 { 3316 compatible = "qcom,fastrpc-compute-cb"; 3317 reg = <8>; 3318 iommus = <&apps_smmu 0x1008 0x0460>; 3319 }; 3320 3321 /* note: secure cb9 in downstream */ 3322 }; 3323 }; 3324 }; 3325 3326 sound: sound { 3327 }; 3328 3329 usb_1_hsphy: phy@88e3000 { 3330 compatible = "qcom,sm8250-usb-hs-phy", 3331 "qcom,usb-snps-hs-7nm-phy"; 3332 reg = <0 0x088e3000 0 0x400>; 3333 status = "disabled"; 3334 #phy-cells = <0>; 3335 3336 clocks = <&rpmhcc RPMH_CXO_CLK>; 3337 clock-names = "ref"; 3338 3339 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3340 }; 3341 3342 usb_2_hsphy: phy@88e4000 { 3343 compatible = "qcom,sm8250-usb-hs-phy", 3344 "qcom,usb-snps-hs-7nm-phy"; 3345 reg = <0 0x088e4000 0 0x400>; 3346 status = "disabled"; 3347 #phy-cells = <0>; 3348 3349 clocks = <&rpmhcc RPMH_CXO_CLK>; 3350 clock-names = "ref"; 3351 3352 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3353 }; 3354 3355 usb_1_qmpphy: phy@88e9000 { 3356 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3357 reg = <0 0x088e9000 0 0x200>, 3358 <0 0x088e8000 0 0x40>, 3359 <0 0x088ea000 0 0x200>; 3360 status = "disabled"; 3361 #address-cells = <2>; 3362 #size-cells = <2>; 3363 ranges; 3364 3365 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3366 <&rpmhcc RPMH_CXO_CLK>, 3367 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3368 clock-names = "aux", "ref_clk_src", "com_aux"; 3369 3370 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3371 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3372 reset-names = "phy", "common"; 3373 3374 usb_1_ssphy: usb3-phy@88e9200 { 3375 reg = <0 0x088e9200 0 0x200>, 3376 <0 0x088e9400 0 0x200>, 3377 <0 0x088e9c00 0 0x400>, 3378 <0 0x088e9600 0 0x200>, 3379 <0 0x088e9800 0 0x200>, 3380 <0 0x088e9a00 0 0x100>; 3381 #clock-cells = <0>; 3382 #phy-cells = <0>; 3383 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3384 clock-names = "pipe0"; 3385 clock-output-names = "usb3_phy_pipe_clk_src"; 3386 }; 3387 3388 dp_phy: dp-phy@88ea200 { 3389 reg = <0 0x088ea200 0 0x200>, 3390 <0 0x088ea400 0 0x200>, 3391 <0 0x088eaa00 0 0x200>, 3392 <0 0x088ea600 0 0x200>, 3393 <0 0x088ea800 0 0x200>; 3394 #phy-cells = <0>; 3395 #clock-cells = <1>; 3396 }; 3397 }; 3398 3399 usb_2_qmpphy: phy@88eb000 { 3400 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3401 reg = <0 0x088eb000 0 0x200>; 3402 status = "disabled"; 3403 #address-cells = <2>; 3404 #size-cells = <2>; 3405 ranges; 3406 3407 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3408 <&rpmhcc RPMH_CXO_CLK>, 3409 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3410 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3411 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3412 3413 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3414 <&gcc GCC_USB3_PHY_SEC_BCR>; 3415 reset-names = "phy", "common"; 3416 3417 usb_2_ssphy: phy@88eb200 { 3418 reg = <0 0x088eb200 0 0x200>, 3419 <0 0x088eb400 0 0x200>, 3420 <0 0x088eb800 0 0x800>; 3421 #clock-cells = <0>; 3422 #phy-cells = <0>; 3423 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3424 clock-names = "pipe0"; 3425 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3426 }; 3427 }; 3428 3429 sdhc_2: mmc@8804000 { 3430 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3431 reg = <0 0x08804000 0 0x1000>; 3432 3433 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3435 interrupt-names = "hc_irq", "pwr_irq"; 3436 3437 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3438 <&gcc GCC_SDCC2_APPS_CLK>, 3439 <&rpmhcc RPMH_CXO_CLK>; 3440 clock-names = "iface", "core", "xo"; 3441 iommus = <&apps_smmu 0x4a0 0x0>; 3442 qcom,dll-config = <0x0007642c>; 3443 qcom,ddr-config = <0x80040868>; 3444 power-domains = <&rpmhpd SM8250_CX>; 3445 operating-points-v2 = <&sdhc2_opp_table>; 3446 3447 status = "disabled"; 3448 3449 sdhc2_opp_table: opp-table { 3450 compatible = "operating-points-v2"; 3451 3452 opp-19200000 { 3453 opp-hz = /bits/ 64 <19200000>; 3454 required-opps = <&rpmhpd_opp_min_svs>; 3455 }; 3456 3457 opp-50000000 { 3458 opp-hz = /bits/ 64 <50000000>; 3459 required-opps = <&rpmhpd_opp_low_svs>; 3460 }; 3461 3462 opp-100000000 { 3463 opp-hz = /bits/ 64 <100000000>; 3464 required-opps = <&rpmhpd_opp_svs>; 3465 }; 3466 3467 opp-202000000 { 3468 opp-hz = /bits/ 64 <202000000>; 3469 required-opps = <&rpmhpd_opp_svs_l1>; 3470 }; 3471 }; 3472 }; 3473 3474 dc_noc: interconnect@90c0000 { 3475 compatible = "qcom,sm8250-dc-noc"; 3476 reg = <0 0x090c0000 0 0x4200>; 3477 #interconnect-cells = <1>; 3478 qcom,bcm-voters = <&apps_bcm_voter>; 3479 }; 3480 3481 gem_noc: interconnect@9100000 { 3482 compatible = "qcom,sm8250-gem-noc"; 3483 reg = <0 0x09100000 0 0xb4000>; 3484 #interconnect-cells = <1>; 3485 qcom,bcm-voters = <&apps_bcm_voter>; 3486 }; 3487 3488 npu_noc: interconnect@9990000 { 3489 compatible = "qcom,sm8250-npu-noc"; 3490 reg = <0 0x09990000 0 0x1600>; 3491 #interconnect-cells = <1>; 3492 qcom,bcm-voters = <&apps_bcm_voter>; 3493 }; 3494 3495 usb_1: usb@a6f8800 { 3496 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3497 reg = <0 0x0a6f8800 0 0x400>; 3498 status = "disabled"; 3499 #address-cells = <2>; 3500 #size-cells = <2>; 3501 ranges; 3502 dma-ranges; 3503 3504 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3505 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3506 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3507 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3508 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3509 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3510 clock-names = "cfg_noc", 3511 "core", 3512 "iface", 3513 "sleep", 3514 "mock_utmi", 3515 "xo"; 3516 3517 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3518 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3519 assigned-clock-rates = <19200000>, <200000000>; 3520 3521 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3522 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3523 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3524 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3525 interrupt-names = "hs_phy_irq", 3526 "ss_phy_irq", 3527 "dm_hs_phy_irq", 3528 "dp_hs_phy_irq"; 3529 3530 power-domains = <&gcc USB30_PRIM_GDSC>; 3531 3532 resets = <&gcc GCC_USB30_PRIM_BCR>; 3533 3534 usb_1_dwc3: usb@a600000 { 3535 compatible = "snps,dwc3"; 3536 reg = <0 0x0a600000 0 0xcd00>; 3537 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3538 iommus = <&apps_smmu 0x0 0x0>; 3539 snps,dis_u2_susphy_quirk; 3540 snps,dis_enblslpm_quirk; 3541 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3542 phy-names = "usb2-phy", "usb3-phy"; 3543 }; 3544 }; 3545 3546 system-cache-controller@9200000 { 3547 compatible = "qcom,sm8250-llcc"; 3548 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3549 reg-names = "llcc_base", "llcc_broadcast_base"; 3550 }; 3551 3552 usb_2: usb@a8f8800 { 3553 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3554 reg = <0 0x0a8f8800 0 0x400>; 3555 status = "disabled"; 3556 #address-cells = <2>; 3557 #size-cells = <2>; 3558 ranges; 3559 dma-ranges; 3560 3561 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3562 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3563 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3564 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3565 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3566 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3567 clock-names = "cfg_noc", 3568 "core", 3569 "iface", 3570 "sleep", 3571 "mock_utmi", 3572 "xo"; 3573 3574 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3575 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3576 assigned-clock-rates = <19200000>, <200000000>; 3577 3578 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3579 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3580 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3581 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3582 interrupt-names = "hs_phy_irq", 3583 "ss_phy_irq", 3584 "dm_hs_phy_irq", 3585 "dp_hs_phy_irq"; 3586 3587 power-domains = <&gcc USB30_SEC_GDSC>; 3588 3589 resets = <&gcc GCC_USB30_SEC_BCR>; 3590 3591 usb_2_dwc3: usb@a800000 { 3592 compatible = "snps,dwc3"; 3593 reg = <0 0x0a800000 0 0xcd00>; 3594 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3595 iommus = <&apps_smmu 0x20 0>; 3596 snps,dis_u2_susphy_quirk; 3597 snps,dis_enblslpm_quirk; 3598 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3599 phy-names = "usb2-phy", "usb3-phy"; 3600 }; 3601 }; 3602 3603 venus: video-codec@aa00000 { 3604 compatible = "qcom,sm8250-venus"; 3605 reg = <0 0x0aa00000 0 0x100000>; 3606 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3607 power-domains = <&videocc MVS0C_GDSC>, 3608 <&videocc MVS0_GDSC>, 3609 <&rpmhpd SM8250_MX>; 3610 power-domain-names = "venus", "vcodec0", "mx"; 3611 operating-points-v2 = <&venus_opp_table>; 3612 3613 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3614 <&videocc VIDEO_CC_MVS0C_CLK>, 3615 <&videocc VIDEO_CC_MVS0_CLK>; 3616 clock-names = "iface", "core", "vcodec0_core"; 3617 3618 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3619 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3620 interconnect-names = "cpu-cfg", "video-mem"; 3621 3622 iommus = <&apps_smmu 0x2100 0x0400>; 3623 memory-region = <&video_mem>; 3624 3625 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3626 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3627 reset-names = "bus", "core"; 3628 3629 status = "disabled"; 3630 3631 video-decoder { 3632 compatible = "venus-decoder"; 3633 }; 3634 3635 video-encoder { 3636 compatible = "venus-encoder"; 3637 }; 3638 3639 venus_opp_table: opp-table { 3640 compatible = "operating-points-v2"; 3641 3642 opp-720000000 { 3643 opp-hz = /bits/ 64 <720000000>; 3644 required-opps = <&rpmhpd_opp_low_svs>; 3645 }; 3646 3647 opp-1014000000 { 3648 opp-hz = /bits/ 64 <1014000000>; 3649 required-opps = <&rpmhpd_opp_svs>; 3650 }; 3651 3652 opp-1098000000 { 3653 opp-hz = /bits/ 64 <1098000000>; 3654 required-opps = <&rpmhpd_opp_svs_l1>; 3655 }; 3656 3657 opp-1332000000 { 3658 opp-hz = /bits/ 64 <1332000000>; 3659 required-opps = <&rpmhpd_opp_nom>; 3660 }; 3661 }; 3662 }; 3663 3664 videocc: clock-controller@abf0000 { 3665 compatible = "qcom,sm8250-videocc"; 3666 reg = <0 0x0abf0000 0 0x10000>; 3667 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3668 <&rpmhcc RPMH_CXO_CLK>, 3669 <&rpmhcc RPMH_CXO_CLK_A>; 3670 power-domains = <&rpmhpd SM8250_MMCX>; 3671 required-opps = <&rpmhpd_opp_low_svs>; 3672 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3673 #clock-cells = <1>; 3674 #reset-cells = <1>; 3675 #power-domain-cells = <1>; 3676 }; 3677 3678 cci0: cci@ac4f000 { 3679 compatible = "qcom,sm8250-cci"; 3680 #address-cells = <1>; 3681 #size-cells = <0>; 3682 3683 reg = <0 0x0ac4f000 0 0x1000>; 3684 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3685 power-domains = <&camcc TITAN_TOP_GDSC>; 3686 3687 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3688 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3689 <&camcc CAM_CC_CPAS_AHB_CLK>, 3690 <&camcc CAM_CC_CCI_0_CLK>, 3691 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3692 clock-names = "camnoc_axi", 3693 "slow_ahb_src", 3694 "cpas_ahb", 3695 "cci", 3696 "cci_src"; 3697 3698 pinctrl-0 = <&cci0_default>; 3699 pinctrl-1 = <&cci0_sleep>; 3700 pinctrl-names = "default", "sleep"; 3701 3702 status = "disabled"; 3703 3704 cci0_i2c0: i2c-bus@0 { 3705 reg = <0>; 3706 clock-frequency = <1000000>; 3707 #address-cells = <1>; 3708 #size-cells = <0>; 3709 }; 3710 3711 cci0_i2c1: i2c-bus@1 { 3712 reg = <1>; 3713 clock-frequency = <1000000>; 3714 #address-cells = <1>; 3715 #size-cells = <0>; 3716 }; 3717 }; 3718 3719 cci1: cci@ac50000 { 3720 compatible = "qcom,sm8250-cci"; 3721 #address-cells = <1>; 3722 #size-cells = <0>; 3723 3724 reg = <0 0x0ac50000 0 0x1000>; 3725 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3726 power-domains = <&camcc TITAN_TOP_GDSC>; 3727 3728 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3729 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3730 <&camcc CAM_CC_CPAS_AHB_CLK>, 3731 <&camcc CAM_CC_CCI_1_CLK>, 3732 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3733 clock-names = "camnoc_axi", 3734 "slow_ahb_src", 3735 "cpas_ahb", 3736 "cci", 3737 "cci_src"; 3738 3739 pinctrl-0 = <&cci1_default>; 3740 pinctrl-1 = <&cci1_sleep>; 3741 pinctrl-names = "default", "sleep"; 3742 3743 status = "disabled"; 3744 3745 cci1_i2c0: i2c-bus@0 { 3746 reg = <0>; 3747 clock-frequency = <1000000>; 3748 #address-cells = <1>; 3749 #size-cells = <0>; 3750 }; 3751 3752 cci1_i2c1: i2c-bus@1 { 3753 reg = <1>; 3754 clock-frequency = <1000000>; 3755 #address-cells = <1>; 3756 #size-cells = <0>; 3757 }; 3758 }; 3759 3760 camss: camss@ac6a000 { 3761 compatible = "qcom,sm8250-camss"; 3762 status = "disabled"; 3763 3764 reg = <0 0xac6a000 0 0x2000>, 3765 <0 0xac6c000 0 0x2000>, 3766 <0 0xac6e000 0 0x1000>, 3767 <0 0xac70000 0 0x1000>, 3768 <0 0xac72000 0 0x1000>, 3769 <0 0xac74000 0 0x1000>, 3770 <0 0xacb4000 0 0xd000>, 3771 <0 0xacc3000 0 0xd000>, 3772 <0 0xacd9000 0 0x2200>, 3773 <0 0xacdb200 0 0x2200>; 3774 reg-names = "csiphy0", 3775 "csiphy1", 3776 "csiphy2", 3777 "csiphy3", 3778 "csiphy4", 3779 "csiphy5", 3780 "vfe0", 3781 "vfe1", 3782 "vfe_lite0", 3783 "vfe_lite1"; 3784 3785 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3799 interrupt-names = "csiphy0", 3800 "csiphy1", 3801 "csiphy2", 3802 "csiphy3", 3803 "csiphy4", 3804 "csiphy5", 3805 "csid0", 3806 "csid1", 3807 "csid2", 3808 "csid3", 3809 "vfe0", 3810 "vfe1", 3811 "vfe_lite0", 3812 "vfe_lite1"; 3813 3814 power-domains = <&camcc IFE_0_GDSC>, 3815 <&camcc IFE_1_GDSC>, 3816 <&camcc TITAN_TOP_GDSC>; 3817 3818 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3819 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3820 <&gcc GCC_CAMERA_SF_AXI_CLK>, 3821 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3822 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 3823 <&camcc CAM_CC_CORE_AHB_CLK>, 3824 <&camcc CAM_CC_CPAS_AHB_CLK>, 3825 <&camcc CAM_CC_CSIPHY0_CLK>, 3826 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3827 <&camcc CAM_CC_CSIPHY1_CLK>, 3828 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3829 <&camcc CAM_CC_CSIPHY2_CLK>, 3830 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3831 <&camcc CAM_CC_CSIPHY3_CLK>, 3832 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3833 <&camcc CAM_CC_CSIPHY4_CLK>, 3834 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3835 <&camcc CAM_CC_CSIPHY5_CLK>, 3836 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3837 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3838 <&camcc CAM_CC_IFE_0_AHB_CLK>, 3839 <&camcc CAM_CC_IFE_0_AXI_CLK>, 3840 <&camcc CAM_CC_IFE_0_CLK>, 3841 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 3842 <&camcc CAM_CC_IFE_0_CSID_CLK>, 3843 <&camcc CAM_CC_IFE_0_AREG_CLK>, 3844 <&camcc CAM_CC_IFE_1_AHB_CLK>, 3845 <&camcc CAM_CC_IFE_1_AXI_CLK>, 3846 <&camcc CAM_CC_IFE_1_CLK>, 3847 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 3848 <&camcc CAM_CC_IFE_1_CSID_CLK>, 3849 <&camcc CAM_CC_IFE_1_AREG_CLK>, 3850 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3851 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 3852 <&camcc CAM_CC_IFE_LITE_CLK>, 3853 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3854 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3855 3856 clock-names = "cam_ahb_clk", 3857 "cam_hf_axi", 3858 "cam_sf_axi", 3859 "camnoc_axi", 3860 "camnoc_axi_src", 3861 "core_ahb", 3862 "cpas_ahb", 3863 "csiphy0", 3864 "csiphy0_timer", 3865 "csiphy1", 3866 "csiphy1_timer", 3867 "csiphy2", 3868 "csiphy2_timer", 3869 "csiphy3", 3870 "csiphy3_timer", 3871 "csiphy4", 3872 "csiphy4_timer", 3873 "csiphy5", 3874 "csiphy5_timer", 3875 "slow_ahb_src", 3876 "vfe0_ahb", 3877 "vfe0_axi", 3878 "vfe0", 3879 "vfe0_cphy_rx", 3880 "vfe0_csid", 3881 "vfe0_areg", 3882 "vfe1_ahb", 3883 "vfe1_axi", 3884 "vfe1", 3885 "vfe1_cphy_rx", 3886 "vfe1_csid", 3887 "vfe1_areg", 3888 "vfe_lite_ahb", 3889 "vfe_lite_axi", 3890 "vfe_lite", 3891 "vfe_lite_cphy_rx", 3892 "vfe_lite_csid"; 3893 3894 iommus = <&apps_smmu 0x800 0x400>, 3895 <&apps_smmu 0x801 0x400>, 3896 <&apps_smmu 0x840 0x400>, 3897 <&apps_smmu 0x841 0x400>, 3898 <&apps_smmu 0xc00 0x400>, 3899 <&apps_smmu 0xc01 0x400>, 3900 <&apps_smmu 0xc40 0x400>, 3901 <&apps_smmu 0xc41 0x400>; 3902 3903 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 3904 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 3905 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 3906 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 3907 interconnect-names = "cam_ahb", 3908 "cam_hf_0_mnoc", 3909 "cam_sf_0_mnoc", 3910 "cam_sf_icp_mnoc"; 3911 3912 ports { 3913 #address-cells = <1>; 3914 #size-cells = <0>; 3915 3916 port@0 { 3917 reg = <0>; 3918 }; 3919 3920 port@1 { 3921 reg = <1>; 3922 }; 3923 3924 port@2 { 3925 reg = <2>; 3926 }; 3927 3928 port@3 { 3929 reg = <3>; 3930 }; 3931 3932 port@4 { 3933 reg = <4>; 3934 }; 3935 3936 port@5 { 3937 reg = <5>; 3938 }; 3939 }; 3940 }; 3941 3942 camcc: clock-controller@ad00000 { 3943 compatible = "qcom,sm8250-camcc"; 3944 reg = <0 0x0ad00000 0 0x10000>; 3945 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3946 <&rpmhcc RPMH_CXO_CLK>, 3947 <&rpmhcc RPMH_CXO_CLK_A>, 3948 <&sleep_clk>; 3949 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3950 power-domains = <&rpmhpd SM8250_MMCX>; 3951 required-opps = <&rpmhpd_opp_low_svs>; 3952 status = "disabled"; 3953 #clock-cells = <1>; 3954 #reset-cells = <1>; 3955 #power-domain-cells = <1>; 3956 }; 3957 3958 mdss: mdss@ae00000 { 3959 compatible = "qcom,sm8250-mdss"; 3960 reg = <0 0x0ae00000 0 0x1000>; 3961 reg-names = "mdss"; 3962 3963 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3964 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3965 interconnect-names = "mdp0-mem", "mdp1-mem"; 3966 3967 power-domains = <&dispcc MDSS_GDSC>; 3968 3969 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3970 <&gcc GCC_DISP_HF_AXI_CLK>, 3971 <&gcc GCC_DISP_SF_AXI_CLK>, 3972 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3973 clock-names = "iface", "bus", "nrt_bus", "core"; 3974 3975 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3976 interrupt-controller; 3977 #interrupt-cells = <1>; 3978 3979 iommus = <&apps_smmu 0x820 0x402>; 3980 3981 status = "disabled"; 3982 3983 #address-cells = <2>; 3984 #size-cells = <2>; 3985 ranges; 3986 3987 mdss_mdp: display-controller@ae01000 { 3988 compatible = "qcom,sm8250-dpu"; 3989 reg = <0 0x0ae01000 0 0x8f000>, 3990 <0 0x0aeb0000 0 0x2008>; 3991 reg-names = "mdp", "vbif"; 3992 3993 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3994 <&gcc GCC_DISP_HF_AXI_CLK>, 3995 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3996 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3997 clock-names = "iface", "bus", "core", "vsync"; 3998 3999 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4000 assigned-clock-rates = <19200000>; 4001 4002 operating-points-v2 = <&mdp_opp_table>; 4003 power-domains = <&rpmhpd SM8250_MMCX>; 4004 4005 interrupt-parent = <&mdss>; 4006 interrupts = <0>; 4007 4008 ports { 4009 #address-cells = <1>; 4010 #size-cells = <0>; 4011 4012 port@0 { 4013 reg = <0>; 4014 dpu_intf1_out: endpoint { 4015 remote-endpoint = <&dsi0_in>; 4016 }; 4017 }; 4018 4019 port@1 { 4020 reg = <1>; 4021 dpu_intf2_out: endpoint { 4022 remote-endpoint = <&dsi1_in>; 4023 }; 4024 }; 4025 }; 4026 4027 mdp_opp_table: opp-table { 4028 compatible = "operating-points-v2"; 4029 4030 opp-200000000 { 4031 opp-hz = /bits/ 64 <200000000>; 4032 required-opps = <&rpmhpd_opp_low_svs>; 4033 }; 4034 4035 opp-300000000 { 4036 opp-hz = /bits/ 64 <300000000>; 4037 required-opps = <&rpmhpd_opp_svs>; 4038 }; 4039 4040 opp-345000000 { 4041 opp-hz = /bits/ 64 <345000000>; 4042 required-opps = <&rpmhpd_opp_svs_l1>; 4043 }; 4044 4045 opp-460000000 { 4046 opp-hz = /bits/ 64 <460000000>; 4047 required-opps = <&rpmhpd_opp_nom>; 4048 }; 4049 }; 4050 }; 4051 4052 dsi0: dsi@ae94000 { 4053 compatible = "qcom,mdss-dsi-ctrl"; 4054 reg = <0 0x0ae94000 0 0x400>; 4055 reg-names = "dsi_ctrl"; 4056 4057 interrupt-parent = <&mdss>; 4058 interrupts = <4>; 4059 4060 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4061 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4062 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4063 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4064 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4065 <&gcc GCC_DISP_HF_AXI_CLK>; 4066 clock-names = "byte", 4067 "byte_intf", 4068 "pixel", 4069 "core", 4070 "iface", 4071 "bus"; 4072 4073 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4074 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4075 4076 operating-points-v2 = <&dsi_opp_table>; 4077 power-domains = <&rpmhpd SM8250_MMCX>; 4078 4079 phys = <&dsi0_phy>; 4080 4081 status = "disabled"; 4082 4083 #address-cells = <1>; 4084 #size-cells = <0>; 4085 4086 ports { 4087 #address-cells = <1>; 4088 #size-cells = <0>; 4089 4090 port@0 { 4091 reg = <0>; 4092 dsi0_in: endpoint { 4093 remote-endpoint = <&dpu_intf1_out>; 4094 }; 4095 }; 4096 4097 port@1 { 4098 reg = <1>; 4099 dsi0_out: endpoint { 4100 }; 4101 }; 4102 }; 4103 4104 dsi_opp_table: opp-table { 4105 compatible = "operating-points-v2"; 4106 4107 opp-187500000 { 4108 opp-hz = /bits/ 64 <187500000>; 4109 required-opps = <&rpmhpd_opp_low_svs>; 4110 }; 4111 4112 opp-300000000 { 4113 opp-hz = /bits/ 64 <300000000>; 4114 required-opps = <&rpmhpd_opp_svs>; 4115 }; 4116 4117 opp-358000000 { 4118 opp-hz = /bits/ 64 <358000000>; 4119 required-opps = <&rpmhpd_opp_svs_l1>; 4120 }; 4121 }; 4122 }; 4123 4124 dsi0_phy: phy@ae94400 { 4125 compatible = "qcom,dsi-phy-7nm"; 4126 reg = <0 0x0ae94400 0 0x200>, 4127 <0 0x0ae94600 0 0x280>, 4128 <0 0x0ae94900 0 0x260>; 4129 reg-names = "dsi_phy", 4130 "dsi_phy_lane", 4131 "dsi_pll"; 4132 4133 #clock-cells = <1>; 4134 #phy-cells = <0>; 4135 4136 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4137 <&rpmhcc RPMH_CXO_CLK>; 4138 clock-names = "iface", "ref"; 4139 4140 status = "disabled"; 4141 }; 4142 4143 dsi1: dsi@ae96000 { 4144 compatible = "qcom,mdss-dsi-ctrl"; 4145 reg = <0 0x0ae96000 0 0x400>; 4146 reg-names = "dsi_ctrl"; 4147 4148 interrupt-parent = <&mdss>; 4149 interrupts = <5>; 4150 4151 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4152 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4153 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4154 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4155 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4156 <&gcc GCC_DISP_HF_AXI_CLK>; 4157 clock-names = "byte", 4158 "byte_intf", 4159 "pixel", 4160 "core", 4161 "iface", 4162 "bus"; 4163 4164 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4165 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4166 4167 operating-points-v2 = <&dsi_opp_table>; 4168 power-domains = <&rpmhpd SM8250_MMCX>; 4169 4170 phys = <&dsi1_phy>; 4171 4172 status = "disabled"; 4173 4174 #address-cells = <1>; 4175 #size-cells = <0>; 4176 4177 ports { 4178 #address-cells = <1>; 4179 #size-cells = <0>; 4180 4181 port@0 { 4182 reg = <0>; 4183 dsi1_in: endpoint { 4184 remote-endpoint = <&dpu_intf2_out>; 4185 }; 4186 }; 4187 4188 port@1 { 4189 reg = <1>; 4190 dsi1_out: endpoint { 4191 }; 4192 }; 4193 }; 4194 }; 4195 4196 dsi1_phy: phy@ae96400 { 4197 compatible = "qcom,dsi-phy-7nm"; 4198 reg = <0 0x0ae96400 0 0x200>, 4199 <0 0x0ae96600 0 0x280>, 4200 <0 0x0ae96900 0 0x260>; 4201 reg-names = "dsi_phy", 4202 "dsi_phy_lane", 4203 "dsi_pll"; 4204 4205 #clock-cells = <1>; 4206 #phy-cells = <0>; 4207 4208 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4209 <&rpmhcc RPMH_CXO_CLK>; 4210 clock-names = "iface", "ref"; 4211 4212 status = "disabled"; 4213 }; 4214 }; 4215 4216 dispcc: clock-controller@af00000 { 4217 compatible = "qcom,sm8250-dispcc"; 4218 reg = <0 0x0af00000 0 0x10000>; 4219 power-domains = <&rpmhpd SM8250_MMCX>; 4220 required-opps = <&rpmhpd_opp_low_svs>; 4221 clocks = <&rpmhcc RPMH_CXO_CLK>, 4222 <&dsi0_phy 0>, 4223 <&dsi0_phy 1>, 4224 <&dsi1_phy 0>, 4225 <&dsi1_phy 1>, 4226 <&dp_phy 0>, 4227 <&dp_phy 1>; 4228 clock-names = "bi_tcxo", 4229 "dsi0_phy_pll_out_byteclk", 4230 "dsi0_phy_pll_out_dsiclk", 4231 "dsi1_phy_pll_out_byteclk", 4232 "dsi1_phy_pll_out_dsiclk", 4233 "dp_phy_pll_link_clk", 4234 "dp_phy_pll_vco_div_clk"; 4235 #clock-cells = <1>; 4236 #reset-cells = <1>; 4237 #power-domain-cells = <1>; 4238 }; 4239 4240 pdc: interrupt-controller@b220000 { 4241 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4242 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4243 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4244 <125 63 1>, <126 716 12>; 4245 #interrupt-cells = <2>; 4246 interrupt-parent = <&intc>; 4247 interrupt-controller; 4248 }; 4249 4250 tsens0: thermal-sensor@c263000 { 4251 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4252 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4253 <0 0x0c222000 0 0x1ff>; /* SROT */ 4254 #qcom,sensors = <16>; 4255 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4257 interrupt-names = "uplow", "critical"; 4258 #thermal-sensor-cells = <1>; 4259 }; 4260 4261 tsens1: thermal-sensor@c265000 { 4262 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4263 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4264 <0 0x0c223000 0 0x1ff>; /* SROT */ 4265 #qcom,sensors = <9>; 4266 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4268 interrupt-names = "uplow", "critical"; 4269 #thermal-sensor-cells = <1>; 4270 }; 4271 4272 aoss_qmp: power-controller@c300000 { 4273 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4274 reg = <0 0x0c300000 0 0x400>; 4275 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4276 IPCC_MPROC_SIGNAL_GLINK_QMP 4277 IRQ_TYPE_EDGE_RISING>; 4278 mboxes = <&ipcc IPCC_CLIENT_AOP 4279 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4280 4281 #clock-cells = <0>; 4282 }; 4283 4284 sram@c3f0000 { 4285 compatible = "qcom,rpmh-stats"; 4286 reg = <0 0x0c3f0000 0 0x400>; 4287 }; 4288 4289 spmi_bus: spmi@c440000 { 4290 compatible = "qcom,spmi-pmic-arb"; 4291 reg = <0x0 0x0c440000 0x0 0x0001100>, 4292 <0x0 0x0c600000 0x0 0x2000000>, 4293 <0x0 0x0e600000 0x0 0x0100000>, 4294 <0x0 0x0e700000 0x0 0x00a0000>, 4295 <0x0 0x0c40a000 0x0 0x0026000>; 4296 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4297 interrupt-names = "periph_irq"; 4298 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4299 qcom,ee = <0>; 4300 qcom,channel = <0>; 4301 #address-cells = <2>; 4302 #size-cells = <0>; 4303 interrupt-controller; 4304 #interrupt-cells = <4>; 4305 }; 4306 4307 tlmm: pinctrl@f100000 { 4308 compatible = "qcom,sm8250-pinctrl"; 4309 reg = <0 0x0f100000 0 0x300000>, 4310 <0 0x0f500000 0 0x300000>, 4311 <0 0x0f900000 0 0x300000>; 4312 reg-names = "west", "south", "north"; 4313 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4314 gpio-controller; 4315 #gpio-cells = <2>; 4316 interrupt-controller; 4317 #interrupt-cells = <2>; 4318 gpio-ranges = <&tlmm 0 0 181>; 4319 wakeup-parent = <&pdc>; 4320 4321 cam2_default: cam2-default-state { 4322 rst-pins { 4323 pins = "gpio78"; 4324 function = "gpio"; 4325 drive-strength = <2>; 4326 bias-disable; 4327 }; 4328 4329 mclk-pins { 4330 pins = "gpio96"; 4331 function = "cam_mclk"; 4332 drive-strength = <16>; 4333 bias-disable; 4334 }; 4335 }; 4336 4337 cam2_suspend: cam2-suspend-state { 4338 rst-pins { 4339 pins = "gpio78"; 4340 function = "gpio"; 4341 drive-strength = <2>; 4342 bias-pull-down; 4343 output-low; 4344 }; 4345 4346 mclk-pins { 4347 pins = "gpio96"; 4348 function = "cam_mclk"; 4349 drive-strength = <2>; 4350 bias-disable; 4351 }; 4352 }; 4353 4354 cci0_default: cci0-default-state { 4355 cci0_i2c0_default: cci0-i2c0-default-pins { 4356 /* SDA, SCL */ 4357 pins = "gpio101", "gpio102"; 4358 function = "cci_i2c"; 4359 4360 bias-pull-up; 4361 drive-strength = <2>; /* 2 mA */ 4362 }; 4363 4364 cci0_i2c1_default: cci0-i2c1-default-pins { 4365 /* SDA, SCL */ 4366 pins = "gpio103", "gpio104"; 4367 function = "cci_i2c"; 4368 4369 bias-pull-up; 4370 drive-strength = <2>; /* 2 mA */ 4371 }; 4372 }; 4373 4374 cci0_sleep: cci0-sleep-state { 4375 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4376 /* SDA, SCL */ 4377 pins = "gpio101", "gpio102"; 4378 function = "cci_i2c"; 4379 4380 drive-strength = <2>; /* 2 mA */ 4381 bias-pull-down; 4382 }; 4383 4384 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4385 /* SDA, SCL */ 4386 pins = "gpio103", "gpio104"; 4387 function = "cci_i2c"; 4388 4389 drive-strength = <2>; /* 2 mA */ 4390 bias-pull-down; 4391 }; 4392 }; 4393 4394 cci1_default: cci1-default-state { 4395 cci1_i2c0_default: cci1-i2c0-default-pins { 4396 /* SDA, SCL */ 4397 pins = "gpio105","gpio106"; 4398 function = "cci_i2c"; 4399 4400 bias-pull-up; 4401 drive-strength = <2>; /* 2 mA */ 4402 }; 4403 4404 cci1_i2c1_default: cci1-i2c1-default-pins { 4405 /* SDA, SCL */ 4406 pins = "gpio107","gpio108"; 4407 function = "cci_i2c"; 4408 4409 bias-pull-up; 4410 drive-strength = <2>; /* 2 mA */ 4411 }; 4412 }; 4413 4414 cci1_sleep: cci1-sleep-state { 4415 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4416 /* SDA, SCL */ 4417 pins = "gpio105","gpio106"; 4418 function = "cci_i2c"; 4419 4420 bias-pull-down; 4421 drive-strength = <2>; /* 2 mA */ 4422 }; 4423 4424 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4425 /* SDA, SCL */ 4426 pins = "gpio107","gpio108"; 4427 function = "cci_i2c"; 4428 4429 bias-pull-down; 4430 drive-strength = <2>; /* 2 mA */ 4431 }; 4432 }; 4433 4434 pri_mi2s_active: pri-mi2s-active-state { 4435 sclk-pins { 4436 pins = "gpio138"; 4437 function = "mi2s0_sck"; 4438 drive-strength = <8>; 4439 bias-disable; 4440 }; 4441 4442 ws-pins { 4443 pins = "gpio141"; 4444 function = "mi2s0_ws"; 4445 drive-strength = <8>; 4446 output-high; 4447 }; 4448 4449 data0-pins { 4450 pins = "gpio139"; 4451 function = "mi2s0_data0"; 4452 drive-strength = <8>; 4453 bias-disable; 4454 output-high; 4455 }; 4456 4457 data1-pins { 4458 pins = "gpio140"; 4459 function = "mi2s0_data1"; 4460 drive-strength = <8>; 4461 output-high; 4462 }; 4463 }; 4464 4465 qup_i2c0_default: qup-i2c0-default-state { 4466 pins = "gpio28", "gpio29"; 4467 function = "qup0"; 4468 drive-strength = <2>; 4469 bias-disable; 4470 }; 4471 4472 qup_i2c1_default: qup-i2c1-default-state { 4473 pins = "gpio4", "gpio5"; 4474 function = "qup1"; 4475 drive-strength = <2>; 4476 bias-disable; 4477 }; 4478 4479 qup_i2c2_default: qup-i2c2-default-state { 4480 pins = "gpio115", "gpio116"; 4481 function = "qup2"; 4482 drive-strength = <2>; 4483 bias-disable; 4484 }; 4485 4486 qup_i2c3_default: qup-i2c3-default-state { 4487 pins = "gpio119", "gpio120"; 4488 function = "qup3"; 4489 drive-strength = <2>; 4490 bias-disable; 4491 }; 4492 4493 qup_i2c4_default: qup-i2c4-default-state { 4494 pins = "gpio8", "gpio9"; 4495 function = "qup4"; 4496 drive-strength = <2>; 4497 bias-disable; 4498 }; 4499 4500 qup_i2c5_default: qup-i2c5-default-state { 4501 pins = "gpio12", "gpio13"; 4502 function = "qup5"; 4503 drive-strength = <2>; 4504 bias-disable; 4505 }; 4506 4507 qup_i2c6_default: qup-i2c6-default-state { 4508 pins = "gpio16", "gpio17"; 4509 function = "qup6"; 4510 drive-strength = <2>; 4511 bias-disable; 4512 }; 4513 4514 qup_i2c7_default: qup-i2c7-default-state { 4515 pins = "gpio20", "gpio21"; 4516 function = "qup7"; 4517 drive-strength = <2>; 4518 bias-disable; 4519 }; 4520 4521 qup_i2c8_default: qup-i2c8-default-state { 4522 pins = "gpio24", "gpio25"; 4523 function = "qup8"; 4524 drive-strength = <2>; 4525 bias-disable; 4526 }; 4527 4528 qup_i2c9_default: qup-i2c9-default-state { 4529 pins = "gpio125", "gpio126"; 4530 function = "qup9"; 4531 drive-strength = <2>; 4532 bias-disable; 4533 }; 4534 4535 qup_i2c10_default: qup-i2c10-default-state { 4536 pins = "gpio129", "gpio130"; 4537 function = "qup10"; 4538 drive-strength = <2>; 4539 bias-disable; 4540 }; 4541 4542 qup_i2c11_default: qup-i2c11-default-state { 4543 pins = "gpio60", "gpio61"; 4544 function = "qup11"; 4545 drive-strength = <2>; 4546 bias-disable; 4547 }; 4548 4549 qup_i2c12_default: qup-i2c12-default-state { 4550 pins = "gpio32", "gpio33"; 4551 function = "qup12"; 4552 drive-strength = <2>; 4553 bias-disable; 4554 }; 4555 4556 qup_i2c13_default: qup-i2c13-default-state { 4557 pins = "gpio36", "gpio37"; 4558 function = "qup13"; 4559 drive-strength = <2>; 4560 bias-disable; 4561 }; 4562 4563 qup_i2c14_default: qup-i2c14-default-state { 4564 pins = "gpio40", "gpio41"; 4565 function = "qup14"; 4566 drive-strength = <2>; 4567 bias-disable; 4568 }; 4569 4570 qup_i2c15_default: qup-i2c15-default-state { 4571 pins = "gpio44", "gpio45"; 4572 function = "qup15"; 4573 drive-strength = <2>; 4574 bias-disable; 4575 }; 4576 4577 qup_i2c16_default: qup-i2c16-default-state { 4578 pins = "gpio48", "gpio49"; 4579 function = "qup16"; 4580 drive-strength = <2>; 4581 bias-disable; 4582 }; 4583 4584 qup_i2c17_default: qup-i2c17-default-state { 4585 pins = "gpio52", "gpio53"; 4586 function = "qup17"; 4587 drive-strength = <2>; 4588 bias-disable; 4589 }; 4590 4591 qup_i2c18_default: qup-i2c18-default-state { 4592 pins = "gpio56", "gpio57"; 4593 function = "qup18"; 4594 drive-strength = <2>; 4595 bias-disable; 4596 }; 4597 4598 qup_i2c19_default: qup-i2c19-default-state { 4599 pins = "gpio0", "gpio1"; 4600 function = "qup19"; 4601 drive-strength = <2>; 4602 bias-disable; 4603 }; 4604 4605 qup_spi0_cs: qup-spi0-cs-state { 4606 pins = "gpio31"; 4607 function = "qup0"; 4608 }; 4609 4610 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4611 pins = "gpio31"; 4612 function = "gpio"; 4613 }; 4614 4615 qup_spi0_data_clk: qup-spi0-data-clk-state { 4616 pins = "gpio28", "gpio29", 4617 "gpio30"; 4618 function = "qup0"; 4619 }; 4620 4621 qup_spi1_cs: qup-spi1-cs-state { 4622 pins = "gpio7"; 4623 function = "qup1"; 4624 }; 4625 4626 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4627 pins = "gpio7"; 4628 function = "gpio"; 4629 }; 4630 4631 qup_spi1_data_clk: qup-spi1-data-clk-state { 4632 pins = "gpio4", "gpio5", 4633 "gpio6"; 4634 function = "qup1"; 4635 }; 4636 4637 qup_spi2_cs: qup-spi2-cs-state { 4638 pins = "gpio118"; 4639 function = "qup2"; 4640 }; 4641 4642 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4643 pins = "gpio118"; 4644 function = "gpio"; 4645 }; 4646 4647 qup_spi2_data_clk: qup-spi2-data-clk-state { 4648 pins = "gpio115", "gpio116", 4649 "gpio117"; 4650 function = "qup2"; 4651 }; 4652 4653 qup_spi3_cs: qup-spi3-cs-state { 4654 pins = "gpio122"; 4655 function = "qup3"; 4656 }; 4657 4658 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4659 pins = "gpio122"; 4660 function = "gpio"; 4661 }; 4662 4663 qup_spi3_data_clk: qup-spi3-data-clk-state { 4664 pins = "gpio119", "gpio120", 4665 "gpio121"; 4666 function = "qup3"; 4667 }; 4668 4669 qup_spi4_cs: qup-spi4-cs-state { 4670 pins = "gpio11"; 4671 function = "qup4"; 4672 }; 4673 4674 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4675 pins = "gpio11"; 4676 function = "gpio"; 4677 }; 4678 4679 qup_spi4_data_clk: qup-spi4-data-clk-state { 4680 pins = "gpio8", "gpio9", 4681 "gpio10"; 4682 function = "qup4"; 4683 }; 4684 4685 qup_spi5_cs: qup-spi5-cs-state { 4686 pins = "gpio15"; 4687 function = "qup5"; 4688 }; 4689 4690 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4691 pins = "gpio15"; 4692 function = "gpio"; 4693 }; 4694 4695 qup_spi5_data_clk: qup-spi5-data-clk-state { 4696 pins = "gpio12", "gpio13", 4697 "gpio14"; 4698 function = "qup5"; 4699 }; 4700 4701 qup_spi6_cs: qup-spi6-cs-state { 4702 pins = "gpio19"; 4703 function = "qup6"; 4704 }; 4705 4706 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4707 pins = "gpio19"; 4708 function = "gpio"; 4709 }; 4710 4711 qup_spi6_data_clk: qup-spi6-data-clk-state { 4712 pins = "gpio16", "gpio17", 4713 "gpio18"; 4714 function = "qup6"; 4715 }; 4716 4717 qup_spi7_cs: qup-spi7-cs-state { 4718 pins = "gpio23"; 4719 function = "qup7"; 4720 }; 4721 4722 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4723 pins = "gpio23"; 4724 function = "gpio"; 4725 }; 4726 4727 qup_spi7_data_clk: qup-spi7-data-clk-state { 4728 pins = "gpio20", "gpio21", 4729 "gpio22"; 4730 function = "qup7"; 4731 }; 4732 4733 qup_spi8_cs: qup-spi8-cs-state { 4734 pins = "gpio27"; 4735 function = "qup8"; 4736 }; 4737 4738 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4739 pins = "gpio27"; 4740 function = "gpio"; 4741 }; 4742 4743 qup_spi8_data_clk: qup-spi8-data-clk-state { 4744 pins = "gpio24", "gpio25", 4745 "gpio26"; 4746 function = "qup8"; 4747 }; 4748 4749 qup_spi9_cs: qup-spi9-cs-state { 4750 pins = "gpio128"; 4751 function = "qup9"; 4752 }; 4753 4754 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4755 pins = "gpio128"; 4756 function = "gpio"; 4757 }; 4758 4759 qup_spi9_data_clk: qup-spi9-data-clk-state { 4760 pins = "gpio125", "gpio126", 4761 "gpio127"; 4762 function = "qup9"; 4763 }; 4764 4765 qup_spi10_cs: qup-spi10-cs-state { 4766 pins = "gpio132"; 4767 function = "qup10"; 4768 }; 4769 4770 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4771 pins = "gpio132"; 4772 function = "gpio"; 4773 }; 4774 4775 qup_spi10_data_clk: qup-spi10-data-clk-state { 4776 pins = "gpio129", "gpio130", 4777 "gpio131"; 4778 function = "qup10"; 4779 }; 4780 4781 qup_spi11_cs: qup-spi11-cs-state { 4782 pins = "gpio63"; 4783 function = "qup11"; 4784 }; 4785 4786 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4787 pins = "gpio63"; 4788 function = "gpio"; 4789 }; 4790 4791 qup_spi11_data_clk: qup-spi11-data-clk-state { 4792 pins = "gpio60", "gpio61", 4793 "gpio62"; 4794 function = "qup11"; 4795 }; 4796 4797 qup_spi12_cs: qup-spi12-cs-state { 4798 pins = "gpio35"; 4799 function = "qup12"; 4800 }; 4801 4802 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4803 pins = "gpio35"; 4804 function = "gpio"; 4805 }; 4806 4807 qup_spi12_data_clk: qup-spi12-data-clk-state { 4808 pins = "gpio32", "gpio33", 4809 "gpio34"; 4810 function = "qup12"; 4811 }; 4812 4813 qup_spi13_cs: qup-spi13-cs-state { 4814 pins = "gpio39"; 4815 function = "qup13"; 4816 }; 4817 4818 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4819 pins = "gpio39"; 4820 function = "gpio"; 4821 }; 4822 4823 qup_spi13_data_clk: qup-spi13-data-clk-state { 4824 pins = "gpio36", "gpio37", 4825 "gpio38"; 4826 function = "qup13"; 4827 }; 4828 4829 qup_spi14_cs: qup-spi14-cs-state { 4830 pins = "gpio43"; 4831 function = "qup14"; 4832 }; 4833 4834 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4835 pins = "gpio43"; 4836 function = "gpio"; 4837 }; 4838 4839 qup_spi14_data_clk: qup-spi14-data-clk-state { 4840 pins = "gpio40", "gpio41", 4841 "gpio42"; 4842 function = "qup14"; 4843 }; 4844 4845 qup_spi15_cs: qup-spi15-cs-state { 4846 pins = "gpio47"; 4847 function = "qup15"; 4848 }; 4849 4850 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4851 pins = "gpio47"; 4852 function = "gpio"; 4853 }; 4854 4855 qup_spi15_data_clk: qup-spi15-data-clk-state { 4856 pins = "gpio44", "gpio45", 4857 "gpio46"; 4858 function = "qup15"; 4859 }; 4860 4861 qup_spi16_cs: qup-spi16-cs-state { 4862 pins = "gpio51"; 4863 function = "qup16"; 4864 }; 4865 4866 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 4867 pins = "gpio51"; 4868 function = "gpio"; 4869 }; 4870 4871 qup_spi16_data_clk: qup-spi16-data-clk-state { 4872 pins = "gpio48", "gpio49", 4873 "gpio50"; 4874 function = "qup16"; 4875 }; 4876 4877 qup_spi17_cs: qup-spi17-cs-state { 4878 pins = "gpio55"; 4879 function = "qup17"; 4880 }; 4881 4882 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 4883 pins = "gpio55"; 4884 function = "gpio"; 4885 }; 4886 4887 qup_spi17_data_clk: qup-spi17-data-clk-state { 4888 pins = "gpio52", "gpio53", 4889 "gpio54"; 4890 function = "qup17"; 4891 }; 4892 4893 qup_spi18_cs: qup-spi18-cs-state { 4894 pins = "gpio59"; 4895 function = "qup18"; 4896 }; 4897 4898 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 4899 pins = "gpio59"; 4900 function = "gpio"; 4901 }; 4902 4903 qup_spi18_data_clk: qup-spi18-data-clk-state { 4904 pins = "gpio56", "gpio57", 4905 "gpio58"; 4906 function = "qup18"; 4907 }; 4908 4909 qup_spi19_cs: qup-spi19-cs-state { 4910 pins = "gpio3"; 4911 function = "qup19"; 4912 }; 4913 4914 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 4915 pins = "gpio3"; 4916 function = "gpio"; 4917 }; 4918 4919 qup_spi19_data_clk: qup-spi19-data-clk-state { 4920 pins = "gpio0", "gpio1", 4921 "gpio2"; 4922 function = "qup19"; 4923 }; 4924 4925 qup_uart2_default: qup-uart2-default-state { 4926 pins = "gpio117", "gpio118"; 4927 function = "qup2"; 4928 }; 4929 4930 qup_uart6_default: qup-uart6-default-state { 4931 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 4932 function = "qup6"; 4933 }; 4934 4935 qup_uart12_default: qup-uart12-default-state { 4936 pins = "gpio34", "gpio35"; 4937 function = "qup12"; 4938 }; 4939 4940 qup_uart17_default: qup-uart17-default-state { 4941 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 4942 function = "qup17"; 4943 }; 4944 4945 qup_uart18_default: qup-uart18-default-state { 4946 pins = "gpio58", "gpio59"; 4947 function = "qup18"; 4948 }; 4949 4950 tert_mi2s_active: tert-mi2s-active-state { 4951 sck-pins { 4952 pins = "gpio133"; 4953 function = "mi2s2_sck"; 4954 drive-strength = <8>; 4955 bias-disable; 4956 }; 4957 4958 data0-pins { 4959 pins = "gpio134"; 4960 function = "mi2s2_data0"; 4961 drive-strength = <8>; 4962 bias-disable; 4963 output-high; 4964 }; 4965 4966 ws-pins { 4967 pins = "gpio135"; 4968 function = "mi2s2_ws"; 4969 drive-strength = <8>; 4970 output-high; 4971 }; 4972 }; 4973 4974 sdc2_sleep_state: sdc2-sleep-state { 4975 clk-pins { 4976 pins = "sdc2_clk"; 4977 drive-strength = <2>; 4978 bias-disable; 4979 }; 4980 4981 cmd-pins { 4982 pins = "sdc2_cmd"; 4983 drive-strength = <2>; 4984 bias-pull-up; 4985 }; 4986 4987 data-pins { 4988 pins = "sdc2_data"; 4989 drive-strength = <2>; 4990 bias-pull-up; 4991 }; 4992 }; 4993 4994 pcie0_default_state: pcie0-default-state { 4995 perst-pins { 4996 pins = "gpio79"; 4997 function = "gpio"; 4998 drive-strength = <2>; 4999 bias-pull-down; 5000 }; 5001 5002 clkreq-pins { 5003 pins = "gpio80"; 5004 function = "pci_e0"; 5005 drive-strength = <2>; 5006 bias-pull-up; 5007 }; 5008 5009 wake-pins { 5010 pins = "gpio81"; 5011 function = "gpio"; 5012 drive-strength = <2>; 5013 bias-pull-up; 5014 }; 5015 }; 5016 5017 pcie1_default_state: pcie1-default-state { 5018 perst-pins { 5019 pins = "gpio82"; 5020 function = "gpio"; 5021 drive-strength = <2>; 5022 bias-pull-down; 5023 }; 5024 5025 clkreq-pins { 5026 pins = "gpio83"; 5027 function = "pci_e1"; 5028 drive-strength = <2>; 5029 bias-pull-up; 5030 }; 5031 5032 wake-pins { 5033 pins = "gpio84"; 5034 function = "gpio"; 5035 drive-strength = <2>; 5036 bias-pull-up; 5037 }; 5038 }; 5039 5040 pcie2_default_state: pcie2-default-state { 5041 perst-pins { 5042 pins = "gpio85"; 5043 function = "gpio"; 5044 drive-strength = <2>; 5045 bias-pull-down; 5046 }; 5047 5048 clkreq-pins { 5049 pins = "gpio86"; 5050 function = "pci_e2"; 5051 drive-strength = <2>; 5052 bias-pull-up; 5053 }; 5054 5055 wake-pins { 5056 pins = "gpio87"; 5057 function = "gpio"; 5058 drive-strength = <2>; 5059 bias-pull-up; 5060 }; 5061 }; 5062 }; 5063 5064 apps_smmu: iommu@15000000 { 5065 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 5066 reg = <0 0x15000000 0 0x100000>; 5067 #iommu-cells = <2>; 5068 #global-interrupts = <2>; 5069 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5167 }; 5168 5169 adsp: remoteproc@17300000 { 5170 compatible = "qcom,sm8250-adsp-pas"; 5171 reg = <0 0x17300000 0 0x100>; 5172 5173 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5174 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5175 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5176 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5177 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5178 interrupt-names = "wdog", "fatal", "ready", 5179 "handover", "stop-ack"; 5180 5181 clocks = <&rpmhcc RPMH_CXO_CLK>; 5182 clock-names = "xo"; 5183 5184 power-domains = <&rpmhpd SM8250_LCX>, 5185 <&rpmhpd SM8250_LMX>; 5186 power-domain-names = "lcx", "lmx"; 5187 5188 memory-region = <&adsp_mem>; 5189 5190 qcom,qmp = <&aoss_qmp>; 5191 5192 qcom,smem-states = <&smp2p_adsp_out 0>; 5193 qcom,smem-state-names = "stop"; 5194 5195 status = "disabled"; 5196 5197 glink-edge { 5198 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5199 IPCC_MPROC_SIGNAL_GLINK_QMP 5200 IRQ_TYPE_EDGE_RISING>; 5201 mboxes = <&ipcc IPCC_CLIENT_LPASS 5202 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5203 5204 label = "lpass"; 5205 qcom,remote-pid = <2>; 5206 5207 apr { 5208 compatible = "qcom,apr-v2"; 5209 qcom,glink-channels = "apr_audio_svc"; 5210 qcom,domain = <APR_DOMAIN_ADSP>; 5211 #address-cells = <1>; 5212 #size-cells = <0>; 5213 5214 service@3 { 5215 reg = <APR_SVC_ADSP_CORE>; 5216 compatible = "qcom,q6core"; 5217 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5218 }; 5219 5220 q6afe: service@4 { 5221 compatible = "qcom,q6afe"; 5222 reg = <APR_SVC_AFE>; 5223 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5224 q6afedai: dais { 5225 compatible = "qcom,q6afe-dais"; 5226 #address-cells = <1>; 5227 #size-cells = <0>; 5228 #sound-dai-cells = <1>; 5229 }; 5230 5231 q6afecc: clock-controller { 5232 compatible = "qcom,q6afe-clocks"; 5233 #clock-cells = <2>; 5234 }; 5235 }; 5236 5237 q6asm: service@7 { 5238 compatible = "qcom,q6asm"; 5239 reg = <APR_SVC_ASM>; 5240 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5241 q6asmdai: dais { 5242 compatible = "qcom,q6asm-dais"; 5243 #address-cells = <1>; 5244 #size-cells = <0>; 5245 #sound-dai-cells = <1>; 5246 iommus = <&apps_smmu 0x1801 0x0>; 5247 }; 5248 }; 5249 5250 q6adm: service@8 { 5251 compatible = "qcom,q6adm"; 5252 reg = <APR_SVC_ADM>; 5253 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5254 q6routing: routing { 5255 compatible = "qcom,q6adm-routing"; 5256 #sound-dai-cells = <0>; 5257 }; 5258 }; 5259 }; 5260 5261 fastrpc { 5262 compatible = "qcom,fastrpc"; 5263 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5264 label = "adsp"; 5265 qcom,non-secure-domain; 5266 #address-cells = <1>; 5267 #size-cells = <0>; 5268 5269 compute-cb@3 { 5270 compatible = "qcom,fastrpc-compute-cb"; 5271 reg = <3>; 5272 iommus = <&apps_smmu 0x1803 0x0>; 5273 }; 5274 5275 compute-cb@4 { 5276 compatible = "qcom,fastrpc-compute-cb"; 5277 reg = <4>; 5278 iommus = <&apps_smmu 0x1804 0x0>; 5279 }; 5280 5281 compute-cb@5 { 5282 compatible = "qcom,fastrpc-compute-cb"; 5283 reg = <5>; 5284 iommus = <&apps_smmu 0x1805 0x0>; 5285 }; 5286 }; 5287 }; 5288 }; 5289 5290 intc: interrupt-controller@17a00000 { 5291 compatible = "arm,gic-v3"; 5292 #interrupt-cells = <3>; 5293 interrupt-controller; 5294 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5295 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5296 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5297 }; 5298 5299 watchdog@17c10000 { 5300 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5301 reg = <0 0x17c10000 0 0x1000>; 5302 clocks = <&sleep_clk>; 5303 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5304 }; 5305 5306 timer@17c20000 { 5307 #address-cells = <1>; 5308 #size-cells = <1>; 5309 ranges = <0 0 0 0x20000000>; 5310 compatible = "arm,armv7-timer-mem"; 5311 reg = <0x0 0x17c20000 0x0 0x1000>; 5312 clock-frequency = <19200000>; 5313 5314 frame@17c21000 { 5315 frame-number = <0>; 5316 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5318 reg = <0x17c21000 0x1000>, 5319 <0x17c22000 0x1000>; 5320 }; 5321 5322 frame@17c23000 { 5323 frame-number = <1>; 5324 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5325 reg = <0x17c23000 0x1000>; 5326 status = "disabled"; 5327 }; 5328 5329 frame@17c25000 { 5330 frame-number = <2>; 5331 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5332 reg = <0x17c25000 0x1000>; 5333 status = "disabled"; 5334 }; 5335 5336 frame@17c27000 { 5337 frame-number = <3>; 5338 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5339 reg = <0x17c27000 0x1000>; 5340 status = "disabled"; 5341 }; 5342 5343 frame@17c29000 { 5344 frame-number = <4>; 5345 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5346 reg = <0x17c29000 0x1000>; 5347 status = "disabled"; 5348 }; 5349 5350 frame@17c2b000 { 5351 frame-number = <5>; 5352 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5353 reg = <0x17c2b000 0x1000>; 5354 status = "disabled"; 5355 }; 5356 5357 frame@17c2d000 { 5358 frame-number = <6>; 5359 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5360 reg = <0x17c2d000 0x1000>; 5361 status = "disabled"; 5362 }; 5363 }; 5364 5365 apps_rsc: rsc@18200000 { 5366 label = "apps_rsc"; 5367 compatible = "qcom,rpmh-rsc"; 5368 reg = <0x0 0x18200000 0x0 0x10000>, 5369 <0x0 0x18210000 0x0 0x10000>, 5370 <0x0 0x18220000 0x0 0x10000>; 5371 reg-names = "drv-0", "drv-1", "drv-2"; 5372 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5373 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5374 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5375 qcom,tcs-offset = <0xd00>; 5376 qcom,drv-id = <2>; 5377 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5378 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5379 power-domains = <&CLUSTER_PD>; 5380 5381 rpmhcc: clock-controller { 5382 compatible = "qcom,sm8250-rpmh-clk"; 5383 #clock-cells = <1>; 5384 clock-names = "xo"; 5385 clocks = <&xo_board>; 5386 }; 5387 5388 rpmhpd: power-controller { 5389 compatible = "qcom,sm8250-rpmhpd"; 5390 #power-domain-cells = <1>; 5391 operating-points-v2 = <&rpmhpd_opp_table>; 5392 5393 rpmhpd_opp_table: opp-table { 5394 compatible = "operating-points-v2"; 5395 5396 rpmhpd_opp_ret: opp1 { 5397 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5398 }; 5399 5400 rpmhpd_opp_min_svs: opp2 { 5401 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5402 }; 5403 5404 rpmhpd_opp_low_svs: opp3 { 5405 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5406 }; 5407 5408 rpmhpd_opp_svs: opp4 { 5409 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5410 }; 5411 5412 rpmhpd_opp_svs_l1: opp5 { 5413 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5414 }; 5415 5416 rpmhpd_opp_nom: opp6 { 5417 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5418 }; 5419 5420 rpmhpd_opp_nom_l1: opp7 { 5421 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5422 }; 5423 5424 rpmhpd_opp_nom_l2: opp8 { 5425 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5426 }; 5427 5428 rpmhpd_opp_turbo: opp9 { 5429 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5430 }; 5431 5432 rpmhpd_opp_turbo_l1: opp10 { 5433 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5434 }; 5435 }; 5436 }; 5437 5438 apps_bcm_voter: bcm-voter { 5439 compatible = "qcom,bcm-voter"; 5440 }; 5441 }; 5442 5443 epss_l3: interconnect@18590000 { 5444 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5445 reg = <0 0x18590000 0 0x1000>; 5446 5447 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5448 clock-names = "xo", "alternate"; 5449 5450 #interconnect-cells = <1>; 5451 }; 5452 5453 cpufreq_hw: cpufreq@18591000 { 5454 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5455 reg = <0 0x18591000 0 0x1000>, 5456 <0 0x18592000 0 0x1000>, 5457 <0 0x18593000 0 0x1000>; 5458 reg-names = "freq-domain0", "freq-domain1", 5459 "freq-domain2"; 5460 5461 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5462 clock-names = "xo", "alternate"; 5463 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5464 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5465 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5466 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5467 #freq-domain-cells = <1>; 5468 }; 5469 }; 5470 5471 timer { 5472 compatible = "arm,armv8-timer"; 5473 interrupts = <GIC_PPI 13 5474 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5475 <GIC_PPI 14 5476 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5477 <GIC_PPI 11 5478 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5479 <GIC_PPI 10 5480 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5481 }; 5482 5483 thermal-zones { 5484 cpu0-thermal { 5485 polling-delay-passive = <250>; 5486 polling-delay = <1000>; 5487 5488 thermal-sensors = <&tsens0 1>; 5489 5490 trips { 5491 cpu0_alert0: trip-point0 { 5492 temperature = <90000>; 5493 hysteresis = <2000>; 5494 type = "passive"; 5495 }; 5496 5497 cpu0_alert1: trip-point1 { 5498 temperature = <95000>; 5499 hysteresis = <2000>; 5500 type = "passive"; 5501 }; 5502 5503 cpu0_crit: cpu_crit { 5504 temperature = <110000>; 5505 hysteresis = <1000>; 5506 type = "critical"; 5507 }; 5508 }; 5509 5510 cooling-maps { 5511 map0 { 5512 trip = <&cpu0_alert0>; 5513 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5514 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5515 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5516 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5517 }; 5518 map1 { 5519 trip = <&cpu0_alert1>; 5520 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5521 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5522 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5523 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5524 }; 5525 }; 5526 }; 5527 5528 cpu1-thermal { 5529 polling-delay-passive = <250>; 5530 polling-delay = <1000>; 5531 5532 thermal-sensors = <&tsens0 2>; 5533 5534 trips { 5535 cpu1_alert0: trip-point0 { 5536 temperature = <90000>; 5537 hysteresis = <2000>; 5538 type = "passive"; 5539 }; 5540 5541 cpu1_alert1: trip-point1 { 5542 temperature = <95000>; 5543 hysteresis = <2000>; 5544 type = "passive"; 5545 }; 5546 5547 cpu1_crit: cpu_crit { 5548 temperature = <110000>; 5549 hysteresis = <1000>; 5550 type = "critical"; 5551 }; 5552 }; 5553 5554 cooling-maps { 5555 map0 { 5556 trip = <&cpu1_alert0>; 5557 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5558 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5559 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5560 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5561 }; 5562 map1 { 5563 trip = <&cpu1_alert1>; 5564 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5565 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5566 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5567 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5568 }; 5569 }; 5570 }; 5571 5572 cpu2-thermal { 5573 polling-delay-passive = <250>; 5574 polling-delay = <1000>; 5575 5576 thermal-sensors = <&tsens0 3>; 5577 5578 trips { 5579 cpu2_alert0: trip-point0 { 5580 temperature = <90000>; 5581 hysteresis = <2000>; 5582 type = "passive"; 5583 }; 5584 5585 cpu2_alert1: trip-point1 { 5586 temperature = <95000>; 5587 hysteresis = <2000>; 5588 type = "passive"; 5589 }; 5590 5591 cpu2_crit: cpu_crit { 5592 temperature = <110000>; 5593 hysteresis = <1000>; 5594 type = "critical"; 5595 }; 5596 }; 5597 5598 cooling-maps { 5599 map0 { 5600 trip = <&cpu2_alert0>; 5601 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5602 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5603 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5604 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5605 }; 5606 map1 { 5607 trip = <&cpu2_alert1>; 5608 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5609 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5610 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5611 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5612 }; 5613 }; 5614 }; 5615 5616 cpu3-thermal { 5617 polling-delay-passive = <250>; 5618 polling-delay = <1000>; 5619 5620 thermal-sensors = <&tsens0 4>; 5621 5622 trips { 5623 cpu3_alert0: trip-point0 { 5624 temperature = <90000>; 5625 hysteresis = <2000>; 5626 type = "passive"; 5627 }; 5628 5629 cpu3_alert1: trip-point1 { 5630 temperature = <95000>; 5631 hysteresis = <2000>; 5632 type = "passive"; 5633 }; 5634 5635 cpu3_crit: cpu_crit { 5636 temperature = <110000>; 5637 hysteresis = <1000>; 5638 type = "critical"; 5639 }; 5640 }; 5641 5642 cooling-maps { 5643 map0 { 5644 trip = <&cpu3_alert0>; 5645 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5646 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5647 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5648 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5649 }; 5650 map1 { 5651 trip = <&cpu3_alert1>; 5652 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5653 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5654 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5655 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5656 }; 5657 }; 5658 }; 5659 5660 cpu4-top-thermal { 5661 polling-delay-passive = <250>; 5662 polling-delay = <1000>; 5663 5664 thermal-sensors = <&tsens0 7>; 5665 5666 trips { 5667 cpu4_top_alert0: trip-point0 { 5668 temperature = <90000>; 5669 hysteresis = <2000>; 5670 type = "passive"; 5671 }; 5672 5673 cpu4_top_alert1: trip-point1 { 5674 temperature = <95000>; 5675 hysteresis = <2000>; 5676 type = "passive"; 5677 }; 5678 5679 cpu4_top_crit: cpu_crit { 5680 temperature = <110000>; 5681 hysteresis = <1000>; 5682 type = "critical"; 5683 }; 5684 }; 5685 5686 cooling-maps { 5687 map0 { 5688 trip = <&cpu4_top_alert0>; 5689 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5690 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5691 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5692 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5693 }; 5694 map1 { 5695 trip = <&cpu4_top_alert1>; 5696 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5697 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5698 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5699 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5700 }; 5701 }; 5702 }; 5703 5704 cpu5-top-thermal { 5705 polling-delay-passive = <250>; 5706 polling-delay = <1000>; 5707 5708 thermal-sensors = <&tsens0 8>; 5709 5710 trips { 5711 cpu5_top_alert0: trip-point0 { 5712 temperature = <90000>; 5713 hysteresis = <2000>; 5714 type = "passive"; 5715 }; 5716 5717 cpu5_top_alert1: trip-point1 { 5718 temperature = <95000>; 5719 hysteresis = <2000>; 5720 type = "passive"; 5721 }; 5722 5723 cpu5_top_crit: cpu_crit { 5724 temperature = <110000>; 5725 hysteresis = <1000>; 5726 type = "critical"; 5727 }; 5728 }; 5729 5730 cooling-maps { 5731 map0 { 5732 trip = <&cpu5_top_alert0>; 5733 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5734 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5735 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5736 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5737 }; 5738 map1 { 5739 trip = <&cpu5_top_alert1>; 5740 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5741 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5742 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5743 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5744 }; 5745 }; 5746 }; 5747 5748 cpu6-top-thermal { 5749 polling-delay-passive = <250>; 5750 polling-delay = <1000>; 5751 5752 thermal-sensors = <&tsens0 9>; 5753 5754 trips { 5755 cpu6_top_alert0: trip-point0 { 5756 temperature = <90000>; 5757 hysteresis = <2000>; 5758 type = "passive"; 5759 }; 5760 5761 cpu6_top_alert1: trip-point1 { 5762 temperature = <95000>; 5763 hysteresis = <2000>; 5764 type = "passive"; 5765 }; 5766 5767 cpu6_top_crit: cpu_crit { 5768 temperature = <110000>; 5769 hysteresis = <1000>; 5770 type = "critical"; 5771 }; 5772 }; 5773 5774 cooling-maps { 5775 map0 { 5776 trip = <&cpu6_top_alert0>; 5777 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5779 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5780 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5781 }; 5782 map1 { 5783 trip = <&cpu6_top_alert1>; 5784 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5785 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5786 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5787 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5788 }; 5789 }; 5790 }; 5791 5792 cpu7-top-thermal { 5793 polling-delay-passive = <250>; 5794 polling-delay = <1000>; 5795 5796 thermal-sensors = <&tsens0 10>; 5797 5798 trips { 5799 cpu7_top_alert0: trip-point0 { 5800 temperature = <90000>; 5801 hysteresis = <2000>; 5802 type = "passive"; 5803 }; 5804 5805 cpu7_top_alert1: trip-point1 { 5806 temperature = <95000>; 5807 hysteresis = <2000>; 5808 type = "passive"; 5809 }; 5810 5811 cpu7_top_crit: cpu_crit { 5812 temperature = <110000>; 5813 hysteresis = <1000>; 5814 type = "critical"; 5815 }; 5816 }; 5817 5818 cooling-maps { 5819 map0 { 5820 trip = <&cpu7_top_alert0>; 5821 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5822 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5823 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5824 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5825 }; 5826 map1 { 5827 trip = <&cpu7_top_alert1>; 5828 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5829 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5830 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5831 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5832 }; 5833 }; 5834 }; 5835 5836 cpu4-bottom-thermal { 5837 polling-delay-passive = <250>; 5838 polling-delay = <1000>; 5839 5840 thermal-sensors = <&tsens0 11>; 5841 5842 trips { 5843 cpu4_bottom_alert0: trip-point0 { 5844 temperature = <90000>; 5845 hysteresis = <2000>; 5846 type = "passive"; 5847 }; 5848 5849 cpu4_bottom_alert1: trip-point1 { 5850 temperature = <95000>; 5851 hysteresis = <2000>; 5852 type = "passive"; 5853 }; 5854 5855 cpu4_bottom_crit: cpu_crit { 5856 temperature = <110000>; 5857 hysteresis = <1000>; 5858 type = "critical"; 5859 }; 5860 }; 5861 5862 cooling-maps { 5863 map0 { 5864 trip = <&cpu4_bottom_alert0>; 5865 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5866 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5867 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5868 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5869 }; 5870 map1 { 5871 trip = <&cpu4_bottom_alert1>; 5872 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5873 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5874 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5875 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5876 }; 5877 }; 5878 }; 5879 5880 cpu5-bottom-thermal { 5881 polling-delay-passive = <250>; 5882 polling-delay = <1000>; 5883 5884 thermal-sensors = <&tsens0 12>; 5885 5886 trips { 5887 cpu5_bottom_alert0: trip-point0 { 5888 temperature = <90000>; 5889 hysteresis = <2000>; 5890 type = "passive"; 5891 }; 5892 5893 cpu5_bottom_alert1: trip-point1 { 5894 temperature = <95000>; 5895 hysteresis = <2000>; 5896 type = "passive"; 5897 }; 5898 5899 cpu5_bottom_crit: cpu_crit { 5900 temperature = <110000>; 5901 hysteresis = <1000>; 5902 type = "critical"; 5903 }; 5904 }; 5905 5906 cooling-maps { 5907 map0 { 5908 trip = <&cpu5_bottom_alert0>; 5909 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5910 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5911 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5912 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5913 }; 5914 map1 { 5915 trip = <&cpu5_bottom_alert1>; 5916 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5917 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5918 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5919 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5920 }; 5921 }; 5922 }; 5923 5924 cpu6-bottom-thermal { 5925 polling-delay-passive = <250>; 5926 polling-delay = <1000>; 5927 5928 thermal-sensors = <&tsens0 13>; 5929 5930 trips { 5931 cpu6_bottom_alert0: trip-point0 { 5932 temperature = <90000>; 5933 hysteresis = <2000>; 5934 type = "passive"; 5935 }; 5936 5937 cpu6_bottom_alert1: trip-point1 { 5938 temperature = <95000>; 5939 hysteresis = <2000>; 5940 type = "passive"; 5941 }; 5942 5943 cpu6_bottom_crit: cpu_crit { 5944 temperature = <110000>; 5945 hysteresis = <1000>; 5946 type = "critical"; 5947 }; 5948 }; 5949 5950 cooling-maps { 5951 map0 { 5952 trip = <&cpu6_bottom_alert0>; 5953 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5954 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5955 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5956 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5957 }; 5958 map1 { 5959 trip = <&cpu6_bottom_alert1>; 5960 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5961 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5962 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5963 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5964 }; 5965 }; 5966 }; 5967 5968 cpu7-bottom-thermal { 5969 polling-delay-passive = <250>; 5970 polling-delay = <1000>; 5971 5972 thermal-sensors = <&tsens0 14>; 5973 5974 trips { 5975 cpu7_bottom_alert0: trip-point0 { 5976 temperature = <90000>; 5977 hysteresis = <2000>; 5978 type = "passive"; 5979 }; 5980 5981 cpu7_bottom_alert1: trip-point1 { 5982 temperature = <95000>; 5983 hysteresis = <2000>; 5984 type = "passive"; 5985 }; 5986 5987 cpu7_bottom_crit: cpu_crit { 5988 temperature = <110000>; 5989 hysteresis = <1000>; 5990 type = "critical"; 5991 }; 5992 }; 5993 5994 cooling-maps { 5995 map0 { 5996 trip = <&cpu7_bottom_alert0>; 5997 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5998 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5999 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6000 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6001 }; 6002 map1 { 6003 trip = <&cpu7_bottom_alert1>; 6004 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6005 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6006 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6007 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6008 }; 6009 }; 6010 }; 6011 6012 aoss0-thermal { 6013 polling-delay-passive = <250>; 6014 polling-delay = <1000>; 6015 6016 thermal-sensors = <&tsens0 0>; 6017 6018 trips { 6019 aoss0_alert0: trip-point0 { 6020 temperature = <90000>; 6021 hysteresis = <2000>; 6022 type = "hot"; 6023 }; 6024 }; 6025 }; 6026 6027 cluster0-thermal { 6028 polling-delay-passive = <250>; 6029 polling-delay = <1000>; 6030 6031 thermal-sensors = <&tsens0 5>; 6032 6033 trips { 6034 cluster0_alert0: trip-point0 { 6035 temperature = <90000>; 6036 hysteresis = <2000>; 6037 type = "hot"; 6038 }; 6039 cluster0_crit: cluster0_crit { 6040 temperature = <110000>; 6041 hysteresis = <2000>; 6042 type = "critical"; 6043 }; 6044 }; 6045 }; 6046 6047 cluster1-thermal { 6048 polling-delay-passive = <250>; 6049 polling-delay = <1000>; 6050 6051 thermal-sensors = <&tsens0 6>; 6052 6053 trips { 6054 cluster1_alert0: trip-point0 { 6055 temperature = <90000>; 6056 hysteresis = <2000>; 6057 type = "hot"; 6058 }; 6059 cluster1_crit: cluster1_crit { 6060 temperature = <110000>; 6061 hysteresis = <2000>; 6062 type = "critical"; 6063 }; 6064 }; 6065 }; 6066 6067 gpu-top-thermal { 6068 polling-delay-passive = <250>; 6069 polling-delay = <1000>; 6070 6071 thermal-sensors = <&tsens0 15>; 6072 6073 trips { 6074 gpu1_alert0: trip-point0 { 6075 temperature = <90000>; 6076 hysteresis = <2000>; 6077 type = "hot"; 6078 }; 6079 }; 6080 }; 6081 6082 aoss1-thermal { 6083 polling-delay-passive = <250>; 6084 polling-delay = <1000>; 6085 6086 thermal-sensors = <&tsens1 0>; 6087 6088 trips { 6089 aoss1_alert0: trip-point0 { 6090 temperature = <90000>; 6091 hysteresis = <2000>; 6092 type = "hot"; 6093 }; 6094 }; 6095 }; 6096 6097 wlan-thermal { 6098 polling-delay-passive = <250>; 6099 polling-delay = <1000>; 6100 6101 thermal-sensors = <&tsens1 1>; 6102 6103 trips { 6104 wlan_alert0: trip-point0 { 6105 temperature = <90000>; 6106 hysteresis = <2000>; 6107 type = "hot"; 6108 }; 6109 }; 6110 }; 6111 6112 video-thermal { 6113 polling-delay-passive = <250>; 6114 polling-delay = <1000>; 6115 6116 thermal-sensors = <&tsens1 2>; 6117 6118 trips { 6119 video_alert0: trip-point0 { 6120 temperature = <90000>; 6121 hysteresis = <2000>; 6122 type = "hot"; 6123 }; 6124 }; 6125 }; 6126 6127 mem-thermal { 6128 polling-delay-passive = <250>; 6129 polling-delay = <1000>; 6130 6131 thermal-sensors = <&tsens1 3>; 6132 6133 trips { 6134 mem_alert0: trip-point0 { 6135 temperature = <90000>; 6136 hysteresis = <2000>; 6137 type = "hot"; 6138 }; 6139 }; 6140 }; 6141 6142 q6-hvx-thermal { 6143 polling-delay-passive = <250>; 6144 polling-delay = <1000>; 6145 6146 thermal-sensors = <&tsens1 4>; 6147 6148 trips { 6149 q6_hvx_alert0: trip-point0 { 6150 temperature = <90000>; 6151 hysteresis = <2000>; 6152 type = "hot"; 6153 }; 6154 }; 6155 }; 6156 6157 camera-thermal { 6158 polling-delay-passive = <250>; 6159 polling-delay = <1000>; 6160 6161 thermal-sensors = <&tsens1 5>; 6162 6163 trips { 6164 camera_alert0: trip-point0 { 6165 temperature = <90000>; 6166 hysteresis = <2000>; 6167 type = "hot"; 6168 }; 6169 }; 6170 }; 6171 6172 compute-thermal { 6173 polling-delay-passive = <250>; 6174 polling-delay = <1000>; 6175 6176 thermal-sensors = <&tsens1 6>; 6177 6178 trips { 6179 compute_alert0: trip-point0 { 6180 temperature = <90000>; 6181 hysteresis = <2000>; 6182 type = "hot"; 6183 }; 6184 }; 6185 }; 6186 6187 npu-thermal { 6188 polling-delay-passive = <250>; 6189 polling-delay = <1000>; 6190 6191 thermal-sensors = <&tsens1 7>; 6192 6193 trips { 6194 npu_alert0: trip-point0 { 6195 temperature = <90000>; 6196 hysteresis = <2000>; 6197 type = "hot"; 6198 }; 6199 }; 6200 }; 6201 6202 gpu-bottom-thermal { 6203 polling-delay-passive = <250>; 6204 polling-delay = <1000>; 6205 6206 thermal-sensors = <&tsens1 8>; 6207 6208 trips { 6209 gpu2_alert0: trip-point0 { 6210 temperature = <90000>; 6211 hysteresis = <2000>; 6212 type = "hot"; 6213 }; 6214 }; 6215 }; 6216 }; 6217}; 6218