1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/clock/qcom,camcc-sm8250.h> 25#include <dt-bindings/clock/qcom,videocc-sm8250.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 i2c16 = &i2c16; 51 i2c17 = &i2c17; 52 i2c18 = &i2c18; 53 i2c19 = &i2c19; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 spi16 = &spi16; 71 spi17 = &spi17; 72 spi18 = &spi18; 73 spi19 = &spi19; 74 }; 75 76 chosen { }; 77 78 clocks { 79 xo_board: xo-board { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <38400000>; 83 clock-output-names = "xo_board"; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32768>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <2>; 95 #size-cells = <0>; 96 97 CPU0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <448>; 104 dynamic-power-coefficient = <105>; 105 next-level-cache = <&L2_0>; 106 power-domains = <&CPU_PD0>; 107 power-domain-names = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 111 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 112 #cooling-cells = <2>; 113 L2_0: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-size = <0x20000>; 117 cache-unified; 118 next-level-cache = <&L3_0>; 119 L3_0: l3-cache { 120 compatible = "cache"; 121 cache-level = <3>; 122 cache-size = <0x400000>; 123 cache-unified; 124 }; 125 }; 126 }; 127 128 CPU1: cpu@100 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x100>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <105>; 136 next-level-cache = <&L2_100>; 137 power-domains = <&CPU_PD1>; 138 power-domain-names = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 142 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 143 #cooling-cells = <2>; 144 L2_100: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-size = <0x20000>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU2: cpu@200 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x200>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <448>; 160 dynamic-power-coefficient = <105>; 161 next-level-cache = <&L2_200>; 162 power-domains = <&CPU_PD2>; 163 power-domain-names = "psci"; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 operating-points-v2 = <&cpu0_opp_table>; 166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 167 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 168 #cooling-cells = <2>; 169 L2_200: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-size = <0x20000>; 173 cache-unified; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU3: cpu@300 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo485"; 181 reg = <0x0 0x300>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 capacity-dmips-mhz = <448>; 185 dynamic-power-coefficient = <105>; 186 next-level-cache = <&L2_300>; 187 power-domains = <&CPU_PD3>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 192 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 193 #cooling-cells = <2>; 194 L2_300: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-size = <0x20000>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU4: cpu@400 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo485"; 206 reg = <0x0 0x400>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&L2_400>; 212 power-domains = <&CPU_PD4>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 L2_400: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-size = <0x40000>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU5: cpu@500 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo485"; 231 reg = <0x0 0x500>; 232 clocks = <&cpufreq_hw 1>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <379>; 236 next-level-cache = <&L2_500>; 237 power-domains = <&CPU_PD5>; 238 power-domain-names = "psci"; 239 qcom,freq-domain = <&cpufreq_hw 1>; 240 operating-points-v2 = <&cpu4_opp_table>; 241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 242 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 243 #cooling-cells = <2>; 244 L2_500: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-size = <0x40000>; 248 cache-unified; 249 next-level-cache = <&L3_0>; 250 }; 251 }; 252 253 CPU6: cpu@600 { 254 device_type = "cpu"; 255 compatible = "qcom,kryo485"; 256 reg = <0x0 0x600>; 257 clocks = <&cpufreq_hw 1>; 258 enable-method = "psci"; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <379>; 261 next-level-cache = <&L2_600>; 262 power-domains = <&CPU_PD6>; 263 power-domain-names = "psci"; 264 qcom,freq-domain = <&cpufreq_hw 1>; 265 operating-points-v2 = <&cpu4_opp_table>; 266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 267 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 L2_600: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 cache-size = <0x40000>; 273 cache-unified; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 CPU7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "qcom,kryo485"; 281 reg = <0x0 0x700>; 282 clocks = <&cpufreq_hw 2>; 283 enable-method = "psci"; 284 capacity-dmips-mhz = <1024>; 285 dynamic-power-coefficient = <444>; 286 next-level-cache = <&L2_700>; 287 power-domains = <&CPU_PD7>; 288 power-domain-names = "psci"; 289 qcom,freq-domain = <&cpufreq_hw 2>; 290 operating-points-v2 = <&cpu7_opp_table>; 291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 292 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 293 #cooling-cells = <2>; 294 L2_700: l2-cache { 295 compatible = "cache"; 296 cache-level = <2>; 297 cache-size = <0x80000>; 298 cache-unified; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 cpu-map { 304 cluster0 { 305 core0 { 306 cpu = <&CPU0>; 307 }; 308 309 core1 { 310 cpu = <&CPU1>; 311 }; 312 313 core2 { 314 cpu = <&CPU2>; 315 }; 316 317 core3 { 318 cpu = <&CPU3>; 319 }; 320 321 core4 { 322 cpu = <&CPU4>; 323 }; 324 325 core5 { 326 cpu = <&CPU5>; 327 }; 328 329 core6 { 330 cpu = <&CPU6>; 331 }; 332 333 core7 { 334 cpu = <&CPU7>; 335 }; 336 }; 337 }; 338 339 idle-states { 340 entry-method = "psci"; 341 342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "silver-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <360>; 347 exit-latency-us = <531>; 348 min-residency-us = <3934>; 349 local-timer-stop; 350 }; 351 352 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 353 compatible = "arm,idle-state"; 354 idle-state-name = "gold-rail-power-collapse"; 355 arm,psci-suspend-param = <0x40000004>; 356 entry-latency-us = <702>; 357 exit-latency-us = <1061>; 358 min-residency-us = <4488>; 359 local-timer-stop; 360 }; 361 }; 362 363 domain-idle-states { 364 CLUSTER_SLEEP_0: cluster-sleep-0 { 365 compatible = "domain-idle-state"; 366 arm,psci-suspend-param = <0x4100c244>; 367 entry-latency-us = <3264>; 368 exit-latency-us = <6562>; 369 min-residency-us = <9987>; 370 }; 371 }; 372 }; 373 374 cpu0_opp_table: opp-table-cpu0 { 375 compatible = "operating-points-v2"; 376 opp-shared; 377 378 cpu0_opp1: opp-300000000 { 379 opp-hz = /bits/ 64 <300000000>; 380 opp-peak-kBps = <800000 9600000>; 381 }; 382 383 cpu0_opp2: opp-403200000 { 384 opp-hz = /bits/ 64 <403200000>; 385 opp-peak-kBps = <800000 9600000>; 386 }; 387 388 cpu0_opp3: opp-518400000 { 389 opp-hz = /bits/ 64 <518400000>; 390 opp-peak-kBps = <800000 16588800>; 391 }; 392 393 cpu0_opp4: opp-614400000 { 394 opp-hz = /bits/ 64 <614400000>; 395 opp-peak-kBps = <800000 16588800>; 396 }; 397 398 cpu0_opp5: opp-691200000 { 399 opp-hz = /bits/ 64 <691200000>; 400 opp-peak-kBps = <800000 19660800>; 401 }; 402 403 cpu0_opp6: opp-787200000 { 404 opp-hz = /bits/ 64 <787200000>; 405 opp-peak-kBps = <1804000 19660800>; 406 }; 407 408 cpu0_opp7: opp-883200000 { 409 opp-hz = /bits/ 64 <883200000>; 410 opp-peak-kBps = <1804000 23347200>; 411 }; 412 413 cpu0_opp8: opp-979200000 { 414 opp-hz = /bits/ 64 <979200000>; 415 opp-peak-kBps = <1804000 26419200>; 416 }; 417 418 cpu0_opp9: opp-1075200000 { 419 opp-hz = /bits/ 64 <1075200000>; 420 opp-peak-kBps = <1804000 29491200>; 421 }; 422 423 cpu0_opp10: opp-1171200000 { 424 opp-hz = /bits/ 64 <1171200000>; 425 opp-peak-kBps = <1804000 32563200>; 426 }; 427 428 cpu0_opp11: opp-1248000000 { 429 opp-hz = /bits/ 64 <1248000000>; 430 opp-peak-kBps = <1804000 36249600>; 431 }; 432 433 cpu0_opp12: opp-1344000000 { 434 opp-hz = /bits/ 64 <1344000000>; 435 opp-peak-kBps = <2188000 36249600>; 436 }; 437 438 cpu0_opp13: opp-1420800000 { 439 opp-hz = /bits/ 64 <1420800000>; 440 opp-peak-kBps = <2188000 39321600>; 441 }; 442 443 cpu0_opp14: opp-1516800000 { 444 opp-hz = /bits/ 64 <1516800000>; 445 opp-peak-kBps = <3072000 42393600>; 446 }; 447 448 cpu0_opp15: opp-1612800000 { 449 opp-hz = /bits/ 64 <1612800000>; 450 opp-peak-kBps = <3072000 42393600>; 451 }; 452 453 cpu0_opp16: opp-1708800000 { 454 opp-hz = /bits/ 64 <1708800000>; 455 opp-peak-kBps = <4068000 42393600>; 456 }; 457 458 cpu0_opp17: opp-1804800000 { 459 opp-hz = /bits/ 64 <1804800000>; 460 opp-peak-kBps = <4068000 42393600>; 461 }; 462 }; 463 464 cpu4_opp_table: opp-table-cpu4 { 465 compatible = "operating-points-v2"; 466 opp-shared; 467 468 cpu4_opp1: opp-710400000 { 469 opp-hz = /bits/ 64 <710400000>; 470 opp-peak-kBps = <1804000 19660800>; 471 }; 472 473 cpu4_opp2: opp-825600000 { 474 opp-hz = /bits/ 64 <825600000>; 475 opp-peak-kBps = <2188000 23347200>; 476 }; 477 478 cpu4_opp3: opp-940800000 { 479 opp-hz = /bits/ 64 <940800000>; 480 opp-peak-kBps = <2188000 26419200>; 481 }; 482 483 cpu4_opp4: opp-1056000000 { 484 opp-hz = /bits/ 64 <1056000000>; 485 opp-peak-kBps = <3072000 26419200>; 486 }; 487 488 cpu4_opp5: opp-1171200000 { 489 opp-hz = /bits/ 64 <1171200000>; 490 opp-peak-kBps = <3072000 29491200>; 491 }; 492 493 cpu4_opp6: opp-1286400000 { 494 opp-hz = /bits/ 64 <1286400000>; 495 opp-peak-kBps = <4068000 29491200>; 496 }; 497 498 cpu4_opp7: opp-1382400000 { 499 opp-hz = /bits/ 64 <1382400000>; 500 opp-peak-kBps = <4068000 32563200>; 501 }; 502 503 cpu4_opp8: opp-1478400000 { 504 opp-hz = /bits/ 64 <1478400000>; 505 opp-peak-kBps = <4068000 32563200>; 506 }; 507 508 cpu4_opp9: opp-1574400000 { 509 opp-hz = /bits/ 64 <1574400000>; 510 opp-peak-kBps = <5412000 39321600>; 511 }; 512 513 cpu4_opp10: opp-1670400000 { 514 opp-hz = /bits/ 64 <1670400000>; 515 opp-peak-kBps = <5412000 42393600>; 516 }; 517 518 cpu4_opp11: opp-1766400000 { 519 opp-hz = /bits/ 64 <1766400000>; 520 opp-peak-kBps = <5412000 45465600>; 521 }; 522 523 cpu4_opp12: opp-1862400000 { 524 opp-hz = /bits/ 64 <1862400000>; 525 opp-peak-kBps = <6220000 45465600>; 526 }; 527 528 cpu4_opp13: opp-1958400000 { 529 opp-hz = /bits/ 64 <1958400000>; 530 opp-peak-kBps = <6220000 48537600>; 531 }; 532 533 cpu4_opp14: opp-2054400000 { 534 opp-hz = /bits/ 64 <2054400000>; 535 opp-peak-kBps = <7216000 48537600>; 536 }; 537 538 cpu4_opp15: opp-2150400000 { 539 opp-hz = /bits/ 64 <2150400000>; 540 opp-peak-kBps = <7216000 51609600>; 541 }; 542 543 cpu4_opp16: opp-2246400000 { 544 opp-hz = /bits/ 64 <2246400000>; 545 opp-peak-kBps = <7216000 51609600>; 546 }; 547 548 cpu4_opp17: opp-2342400000 { 549 opp-hz = /bits/ 64 <2342400000>; 550 opp-peak-kBps = <8368000 51609600>; 551 }; 552 553 cpu4_opp18: opp-2419200000 { 554 opp-hz = /bits/ 64 <2419200000>; 555 opp-peak-kBps = <8368000 51609600>; 556 }; 557 }; 558 559 cpu7_opp_table: opp-table-cpu7 { 560 compatible = "operating-points-v2"; 561 opp-shared; 562 563 cpu7_opp1: opp-844800000 { 564 opp-hz = /bits/ 64 <844800000>; 565 opp-peak-kBps = <2188000 19660800>; 566 }; 567 568 cpu7_opp2: opp-960000000 { 569 opp-hz = /bits/ 64 <960000000>; 570 opp-peak-kBps = <2188000 26419200>; 571 }; 572 573 cpu7_opp3: opp-1075200000 { 574 opp-hz = /bits/ 64 <1075200000>; 575 opp-peak-kBps = <3072000 26419200>; 576 }; 577 578 cpu7_opp4: opp-1190400000 { 579 opp-hz = /bits/ 64 <1190400000>; 580 opp-peak-kBps = <3072000 29491200>; 581 }; 582 583 cpu7_opp5: opp-1305600000 { 584 opp-hz = /bits/ 64 <1305600000>; 585 opp-peak-kBps = <4068000 32563200>; 586 }; 587 588 cpu7_opp6: opp-1401600000 { 589 opp-hz = /bits/ 64 <1401600000>; 590 opp-peak-kBps = <4068000 32563200>; 591 }; 592 593 cpu7_opp7: opp-1516800000 { 594 opp-hz = /bits/ 64 <1516800000>; 595 opp-peak-kBps = <4068000 36249600>; 596 }; 597 598 cpu7_opp8: opp-1632000000 { 599 opp-hz = /bits/ 64 <1632000000>; 600 opp-peak-kBps = <5412000 39321600>; 601 }; 602 603 cpu7_opp9: opp-1747200000 { 604 opp-hz = /bits/ 64 <1708800000>; 605 opp-peak-kBps = <5412000 42393600>; 606 }; 607 608 cpu7_opp10: opp-1862400000 { 609 opp-hz = /bits/ 64 <1862400000>; 610 opp-peak-kBps = <6220000 45465600>; 611 }; 612 613 cpu7_opp11: opp-1977600000 { 614 opp-hz = /bits/ 64 <1977600000>; 615 opp-peak-kBps = <6220000 48537600>; 616 }; 617 618 cpu7_opp12: opp-2073600000 { 619 opp-hz = /bits/ 64 <2073600000>; 620 opp-peak-kBps = <7216000 48537600>; 621 }; 622 623 cpu7_opp13: opp-2169600000 { 624 opp-hz = /bits/ 64 <2169600000>; 625 opp-peak-kBps = <7216000 51609600>; 626 }; 627 628 cpu7_opp14: opp-2265600000 { 629 opp-hz = /bits/ 64 <2265600000>; 630 opp-peak-kBps = <7216000 51609600>; 631 }; 632 633 cpu7_opp15: opp-2361600000 { 634 opp-hz = /bits/ 64 <2361600000>; 635 opp-peak-kBps = <8368000 51609600>; 636 }; 637 638 cpu7_opp16: opp-2457600000 { 639 opp-hz = /bits/ 64 <2457600000>; 640 opp-peak-kBps = <8368000 51609600>; 641 }; 642 643 cpu7_opp17: opp-2553600000 { 644 opp-hz = /bits/ 64 <2553600000>; 645 opp-peak-kBps = <8368000 51609600>; 646 }; 647 648 cpu7_opp18: opp-2649600000 { 649 opp-hz = /bits/ 64 <2649600000>; 650 opp-peak-kBps = <8368000 51609600>; 651 }; 652 653 cpu7_opp19: opp-2745600000 { 654 opp-hz = /bits/ 64 <2745600000>; 655 opp-peak-kBps = <8368000 51609600>; 656 }; 657 658 cpu7_opp20: opp-2841600000 { 659 opp-hz = /bits/ 64 <2841600000>; 660 opp-peak-kBps = <8368000 51609600>; 661 }; 662 }; 663 664 firmware { 665 scm: scm { 666 compatible = "qcom,scm-sm8250", "qcom,scm"; 667 #reset-cells = <1>; 668 }; 669 }; 670 671 memory@80000000 { 672 device_type = "memory"; 673 /* We expect the bootloader to fill in the size */ 674 reg = <0x0 0x80000000 0x0 0x0>; 675 }; 676 677 pmu { 678 compatible = "arm,armv8-pmuv3"; 679 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 680 }; 681 682 psci { 683 compatible = "arm,psci-1.0"; 684 method = "smc"; 685 686 CPU_PD0: power-domain-cpu0 { 687 #power-domain-cells = <0>; 688 power-domains = <&CLUSTER_PD>; 689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 690 }; 691 692 CPU_PD1: power-domain-cpu1 { 693 #power-domain-cells = <0>; 694 power-domains = <&CLUSTER_PD>; 695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 696 }; 697 698 CPU_PD2: power-domain-cpu2 { 699 #power-domain-cells = <0>; 700 power-domains = <&CLUSTER_PD>; 701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 702 }; 703 704 CPU_PD3: power-domain-cpu3 { 705 #power-domain-cells = <0>; 706 power-domains = <&CLUSTER_PD>; 707 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 708 }; 709 710 CPU_PD4: power-domain-cpu4 { 711 #power-domain-cells = <0>; 712 power-domains = <&CLUSTER_PD>; 713 domain-idle-states = <&BIG_CPU_SLEEP_0>; 714 }; 715 716 CPU_PD5: power-domain-cpu5 { 717 #power-domain-cells = <0>; 718 power-domains = <&CLUSTER_PD>; 719 domain-idle-states = <&BIG_CPU_SLEEP_0>; 720 }; 721 722 CPU_PD6: power-domain-cpu6 { 723 #power-domain-cells = <0>; 724 power-domains = <&CLUSTER_PD>; 725 domain-idle-states = <&BIG_CPU_SLEEP_0>; 726 }; 727 728 CPU_PD7: power-domain-cpu7 { 729 #power-domain-cells = <0>; 730 power-domains = <&CLUSTER_PD>; 731 domain-idle-states = <&BIG_CPU_SLEEP_0>; 732 }; 733 734 CLUSTER_PD: power-domain-cpu-cluster0 { 735 #power-domain-cells = <0>; 736 domain-idle-states = <&CLUSTER_SLEEP_0>; 737 }; 738 }; 739 740 qup_opp_table: opp-table-qup { 741 compatible = "operating-points-v2"; 742 743 opp-50000000 { 744 opp-hz = /bits/ 64 <50000000>; 745 required-opps = <&rpmhpd_opp_min_svs>; 746 }; 747 748 opp-75000000 { 749 opp-hz = /bits/ 64 <75000000>; 750 required-opps = <&rpmhpd_opp_low_svs>; 751 }; 752 753 opp-120000000 { 754 opp-hz = /bits/ 64 <120000000>; 755 required-opps = <&rpmhpd_opp_svs>; 756 }; 757 }; 758 759 reserved-memory { 760 #address-cells = <2>; 761 #size-cells = <2>; 762 ranges; 763 764 hyp_mem: memory@80000000 { 765 reg = <0x0 0x80000000 0x0 0x600000>; 766 no-map; 767 }; 768 769 xbl_aop_mem: memory@80700000 { 770 reg = <0x0 0x80700000 0x0 0x160000>; 771 no-map; 772 }; 773 774 cmd_db: memory@80860000 { 775 compatible = "qcom,cmd-db"; 776 reg = <0x0 0x80860000 0x0 0x20000>; 777 no-map; 778 }; 779 780 smem_mem: memory@80900000 { 781 reg = <0x0 0x80900000 0x0 0x200000>; 782 no-map; 783 }; 784 785 removed_mem: memory@80b00000 { 786 reg = <0x0 0x80b00000 0x0 0x5300000>; 787 no-map; 788 }; 789 790 camera_mem: memory@86200000 { 791 reg = <0x0 0x86200000 0x0 0x500000>; 792 no-map; 793 }; 794 795 wlan_mem: memory@86700000 { 796 reg = <0x0 0x86700000 0x0 0x100000>; 797 no-map; 798 }; 799 800 ipa_fw_mem: memory@86800000 { 801 reg = <0x0 0x86800000 0x0 0x10000>; 802 no-map; 803 }; 804 805 ipa_gsi_mem: memory@86810000 { 806 reg = <0x0 0x86810000 0x0 0xa000>; 807 no-map; 808 }; 809 810 gpu_mem: memory@8681a000 { 811 reg = <0x0 0x8681a000 0x0 0x2000>; 812 no-map; 813 }; 814 815 npu_mem: memory@86900000 { 816 reg = <0x0 0x86900000 0x0 0x500000>; 817 no-map; 818 }; 819 820 video_mem: memory@86e00000 { 821 reg = <0x0 0x86e00000 0x0 0x500000>; 822 no-map; 823 }; 824 825 cvp_mem: memory@87300000 { 826 reg = <0x0 0x87300000 0x0 0x500000>; 827 no-map; 828 }; 829 830 cdsp_mem: memory@87800000 { 831 reg = <0x0 0x87800000 0x0 0x1400000>; 832 no-map; 833 }; 834 835 slpi_mem: memory@88c00000 { 836 reg = <0x0 0x88c00000 0x0 0x1500000>; 837 no-map; 838 }; 839 840 adsp_mem: memory@8a100000 { 841 reg = <0x0 0x8a100000 0x0 0x1d00000>; 842 no-map; 843 }; 844 845 spss_mem: memory@8be00000 { 846 reg = <0x0 0x8be00000 0x0 0x100000>; 847 no-map; 848 }; 849 850 cdsp_secure_heap: memory@8bf00000 { 851 reg = <0x0 0x8bf00000 0x0 0x4600000>; 852 no-map; 853 }; 854 }; 855 856 smem { 857 compatible = "qcom,smem"; 858 memory-region = <&smem_mem>; 859 hwlocks = <&tcsr_mutex 3>; 860 }; 861 862 smp2p-adsp { 863 compatible = "qcom,smp2p"; 864 qcom,smem = <443>, <429>; 865 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 866 IPCC_MPROC_SIGNAL_SMP2P 867 IRQ_TYPE_EDGE_RISING>; 868 mboxes = <&ipcc IPCC_CLIENT_LPASS 869 IPCC_MPROC_SIGNAL_SMP2P>; 870 871 qcom,local-pid = <0>; 872 qcom,remote-pid = <2>; 873 874 smp2p_adsp_out: master-kernel { 875 qcom,entry-name = "master-kernel"; 876 #qcom,smem-state-cells = <1>; 877 }; 878 879 smp2p_adsp_in: slave-kernel { 880 qcom,entry-name = "slave-kernel"; 881 interrupt-controller; 882 #interrupt-cells = <2>; 883 }; 884 }; 885 886 smp2p-cdsp { 887 compatible = "qcom,smp2p"; 888 qcom,smem = <94>, <432>; 889 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 890 IPCC_MPROC_SIGNAL_SMP2P 891 IRQ_TYPE_EDGE_RISING>; 892 mboxes = <&ipcc IPCC_CLIENT_CDSP 893 IPCC_MPROC_SIGNAL_SMP2P>; 894 895 qcom,local-pid = <0>; 896 qcom,remote-pid = <5>; 897 898 smp2p_cdsp_out: master-kernel { 899 qcom,entry-name = "master-kernel"; 900 #qcom,smem-state-cells = <1>; 901 }; 902 903 smp2p_cdsp_in: slave-kernel { 904 qcom,entry-name = "slave-kernel"; 905 interrupt-controller; 906 #interrupt-cells = <2>; 907 }; 908 }; 909 910 smp2p-slpi { 911 compatible = "qcom,smp2p"; 912 qcom,smem = <481>, <430>; 913 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 914 IPCC_MPROC_SIGNAL_SMP2P 915 IRQ_TYPE_EDGE_RISING>; 916 mboxes = <&ipcc IPCC_CLIENT_SLPI 917 IPCC_MPROC_SIGNAL_SMP2P>; 918 919 qcom,local-pid = <0>; 920 qcom,remote-pid = <3>; 921 922 smp2p_slpi_out: master-kernel { 923 qcom,entry-name = "master-kernel"; 924 #qcom,smem-state-cells = <1>; 925 }; 926 927 smp2p_slpi_in: slave-kernel { 928 qcom,entry-name = "slave-kernel"; 929 interrupt-controller; 930 #interrupt-cells = <2>; 931 }; 932 }; 933 934 soc: soc@0 { 935 #address-cells = <2>; 936 #size-cells = <2>; 937 ranges = <0 0 0 0 0x10 0>; 938 dma-ranges = <0 0 0 0 0x10 0>; 939 compatible = "simple-bus"; 940 941 gcc: clock-controller@100000 { 942 compatible = "qcom,gcc-sm8250"; 943 reg = <0x0 0x00100000 0x0 0x1f0000>; 944 #clock-cells = <1>; 945 #reset-cells = <1>; 946 #power-domain-cells = <1>; 947 clock-names = "bi_tcxo", 948 "bi_tcxo_ao", 949 "sleep_clk"; 950 clocks = <&rpmhcc RPMH_CXO_CLK>, 951 <&rpmhcc RPMH_CXO_CLK_A>, 952 <&sleep_clk>; 953 }; 954 955 ipcc: mailbox@408000 { 956 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 957 reg = <0 0x00408000 0 0x1000>; 958 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-controller; 960 #interrupt-cells = <3>; 961 #mbox-cells = <2>; 962 }; 963 964 qfprom: efuse@784000 { 965 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 966 reg = <0 0x00784000 0 0x8ff>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 970 gpu_speed_bin: gpu_speed_bin@19b { 971 reg = <0x19b 0x1>; 972 bits = <5 3>; 973 }; 974 }; 975 976 rng: rng@793000 { 977 compatible = "qcom,prng-ee"; 978 reg = <0 0x00793000 0 0x1000>; 979 clocks = <&gcc GCC_PRNG_AHB_CLK>; 980 clock-names = "core"; 981 }; 982 983 gpi_dma2: dma-controller@800000 { 984 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 985 reg = <0 0x00800000 0 0x70000>; 986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 996 dma-channels = <10>; 997 dma-channel-mask = <0x3f>; 998 iommus = <&apps_smmu 0x76 0x0>; 999 #dma-cells = <3>; 1000 status = "disabled"; 1001 }; 1002 1003 qupv3_id_2: geniqup@8c0000 { 1004 compatible = "qcom,geni-se-qup"; 1005 reg = <0x0 0x008c0000 0x0 0x6000>; 1006 clock-names = "m-ahb", "s-ahb"; 1007 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1008 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1009 #address-cells = <2>; 1010 #size-cells = <2>; 1011 iommus = <&apps_smmu 0x63 0x0>; 1012 ranges; 1013 status = "disabled"; 1014 1015 i2c14: i2c@880000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00880000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c14_default>; 1022 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1023 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1024 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 spi14: spi@880000 { 1032 compatible = "qcom,geni-spi"; 1033 reg = <0 0x00880000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1036 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1037 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1038 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1039 dma-names = "tx", "rx"; 1040 power-domains = <&rpmhpd RPMHPD_CX>; 1041 operating-points-v2 = <&qup_opp_table>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c15: i2c@884000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0 0x00884000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c15_default>; 1054 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1055 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1056 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1057 dma-names = "tx", "rx"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 spi15: spi@884000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0 0x00884000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1068 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1069 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1070 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1071 dma-names = "tx", "rx"; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 i2c16: i2c@888000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00888000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_i2c16_default>; 1086 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 spi16: spi@888000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x00888000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1100 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1101 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1102 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 power-domains = <&rpmhpd RPMHPD_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c17: i2c@88c000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x0088c000 0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c17_default>; 1118 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1119 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1120 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1121 dma-names = "tx", "rx"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 spi17: spi@88c000 { 1128 compatible = "qcom,geni-spi"; 1129 reg = <0 0x0088c000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1133 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1134 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1135 dma-names = "tx", "rx"; 1136 power-domains = <&rpmhpd RPMHPD_CX>; 1137 operating-points-v2 = <&qup_opp_table>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 uart17: serial@88c000 { 1144 compatible = "qcom,geni-uart"; 1145 reg = <0 0x0088c000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&qup_uart17_default>; 1150 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1151 power-domains = <&rpmhpd RPMHPD_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c18: i2c@890000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00890000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c18_default>; 1163 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1165 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1166 dma-names = "tx", "rx"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi18: spi@890000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0 0x00890000 0 0x4000>; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1178 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1179 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1180 dma-names = "tx", "rx"; 1181 power-domains = <&rpmhpd RPMHPD_CX>; 1182 operating-points-v2 = <&qup_opp_table>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 status = "disabled"; 1186 }; 1187 1188 uart18: serial@890000 { 1189 compatible = "qcom,geni-uart"; 1190 reg = <0 0x00890000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_uart18_default>; 1195 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1196 power-domains = <&rpmhpd RPMHPD_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 status = "disabled"; 1199 }; 1200 1201 i2c19: i2c@894000 { 1202 compatible = "qcom,geni-i2c"; 1203 reg = <0 0x00894000 0 0x4000>; 1204 clock-names = "se"; 1205 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_i2c19_default>; 1208 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1209 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1210 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1211 dma-names = "tx", "rx"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 spi19: spi@894000 { 1218 compatible = "qcom,geni-spi"; 1219 reg = <0 0x00894000 0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1222 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1223 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1224 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1225 dma-names = "tx", "rx"; 1226 power-domains = <&rpmhpd RPMHPD_CX>; 1227 operating-points-v2 = <&qup_opp_table>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 gpi_dma0: dma-controller@900000 { 1235 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1236 reg = <0 0x00900000 0 0x70000>; 1237 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1250 dma-channels = <15>; 1251 dma-channel-mask = <0x7ff>; 1252 iommus = <&apps_smmu 0x5b6 0x0>; 1253 #dma-cells = <3>; 1254 status = "disabled"; 1255 }; 1256 1257 qupv3_id_0: geniqup@9c0000 { 1258 compatible = "qcom,geni-se-qup"; 1259 reg = <0x0 0x009c0000 0x0 0x6000>; 1260 clock-names = "m-ahb", "s-ahb"; 1261 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1262 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1263 #address-cells = <2>; 1264 #size-cells = <2>; 1265 iommus = <&apps_smmu 0x5a3 0x0>; 1266 ranges; 1267 status = "disabled"; 1268 1269 i2c0: i2c@980000 { 1270 compatible = "qcom,geni-i2c"; 1271 reg = <0 0x00980000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&qup_i2c0_default>; 1276 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1277 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1278 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1279 dma-names = "tx", "rx"; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 spi0: spi@980000 { 1286 compatible = "qcom,geni-spi"; 1287 reg = <0 0x00980000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1290 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1292 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1293 dma-names = "tx", "rx"; 1294 power-domains = <&rpmhpd RPMHPD_CX>; 1295 operating-points-v2 = <&qup_opp_table>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 i2c1: i2c@984000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x00984000 0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_i2c1_default>; 1308 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1309 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 status = "disabled"; 1315 }; 1316 1317 spi1: spi@984000 { 1318 compatible = "qcom,geni-spi"; 1319 reg = <0 0x00984000 0 0x4000>; 1320 clock-names = "se"; 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1322 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1323 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1324 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1325 dma-names = "tx", "rx"; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c2: i2c@988000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00988000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c2_default>; 1340 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1341 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1342 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1343 dma-names = "tx", "rx"; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 spi2: spi@988000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00988000 0 0x4000>; 1352 clock-names = "se"; 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1354 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1355 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1356 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 power-domains = <&rpmhpd RPMHPD_CX>; 1359 operating-points-v2 = <&qup_opp_table>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 uart2: serial@988000 { 1366 compatible = "qcom,geni-debug-uart"; 1367 reg = <0 0x00988000 0 0x4000>; 1368 clock-names = "se"; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_uart2_default>; 1372 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1373 power-domains = <&rpmhpd RPMHPD_CX>; 1374 operating-points-v2 = <&qup_opp_table>; 1375 status = "disabled"; 1376 }; 1377 1378 i2c3: i2c@98c000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x0098c000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c3_default>; 1385 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1386 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1387 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1388 dma-names = "tx", "rx"; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 spi3: spi@98c000 { 1395 compatible = "qcom,geni-spi"; 1396 reg = <0 0x0098c000 0 0x4000>; 1397 clock-names = "se"; 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1399 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1401 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1402 dma-names = "tx", "rx"; 1403 power-domains = <&rpmhpd RPMHPD_CX>; 1404 operating-points-v2 = <&qup_opp_table>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 i2c4: i2c@990000 { 1411 compatible = "qcom,geni-i2c"; 1412 reg = <0 0x00990000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_i2c4_default>; 1417 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1418 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1419 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1420 dma-names = "tx", "rx"; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 spi4: spi@990000 { 1427 compatible = "qcom,geni-spi"; 1428 reg = <0 0x00990000 0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1431 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1432 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1433 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1434 dma-names = "tx", "rx"; 1435 power-domains = <&rpmhpd RPMHPD_CX>; 1436 operating-points-v2 = <&qup_opp_table>; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 i2c5: i2c@994000 { 1443 compatible = "qcom,geni-i2c"; 1444 reg = <0 0x00994000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_i2c5_default>; 1449 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1450 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1451 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1452 dma-names = "tx", "rx"; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 status = "disabled"; 1456 }; 1457 1458 spi5: spi@994000 { 1459 compatible = "qcom,geni-spi"; 1460 reg = <0 0x00994000 0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1463 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1465 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1466 dma-names = "tx", "rx"; 1467 power-domains = <&rpmhpd RPMHPD_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 i2c6: i2c@998000 { 1475 compatible = "qcom,geni-i2c"; 1476 reg = <0 0x00998000 0 0x4000>; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_i2c6_default>; 1481 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1482 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1483 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1484 dma-names = "tx", "rx"; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 status = "disabled"; 1488 }; 1489 1490 spi6: spi@998000 { 1491 compatible = "qcom,geni-spi"; 1492 reg = <0 0x00998000 0 0x4000>; 1493 clock-names = "se"; 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1496 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1497 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1498 dma-names = "tx", "rx"; 1499 power-domains = <&rpmhpd RPMHPD_CX>; 1500 operating-points-v2 = <&qup_opp_table>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 uart6: serial@998000 { 1507 compatible = "qcom,geni-uart"; 1508 reg = <0 0x00998000 0 0x4000>; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_uart6_default>; 1513 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1514 power-domains = <&rpmhpd RPMHPD_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 status = "disabled"; 1517 }; 1518 1519 i2c7: i2c@99c000 { 1520 compatible = "qcom,geni-i2c"; 1521 reg = <0 0x0099c000 0 0x4000>; 1522 clock-names = "se"; 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1524 pinctrl-names = "default"; 1525 pinctrl-0 = <&qup_i2c7_default>; 1526 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1528 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1529 dma-names = "tx", "rx"; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 status = "disabled"; 1533 }; 1534 1535 spi7: spi@99c000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0 0x0099c000 0 0x4000>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1540 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1541 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1542 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1543 dma-names = "tx", "rx"; 1544 power-domains = <&rpmhpd RPMHPD_CX>; 1545 operating-points-v2 = <&qup_opp_table>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 status = "disabled"; 1549 }; 1550 }; 1551 1552 gpi_dma1: dma-controller@a00000 { 1553 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1554 reg = <0 0x00a00000 0 0x70000>; 1555 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1565 dma-channels = <10>; 1566 dma-channel-mask = <0x3f>; 1567 iommus = <&apps_smmu 0x56 0x0>; 1568 #dma-cells = <3>; 1569 status = "disabled"; 1570 }; 1571 1572 qupv3_id_1: geniqup@ac0000 { 1573 compatible = "qcom,geni-se-qup"; 1574 reg = <0x0 0x00ac0000 0x0 0x6000>; 1575 clock-names = "m-ahb", "s-ahb"; 1576 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1577 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1578 #address-cells = <2>; 1579 #size-cells = <2>; 1580 iommus = <&apps_smmu 0x43 0x0>; 1581 ranges; 1582 status = "disabled"; 1583 1584 i2c8: i2c@a80000 { 1585 compatible = "qcom,geni-i2c"; 1586 reg = <0 0x00a80000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1589 pinctrl-names = "default"; 1590 pinctrl-0 = <&qup_i2c8_default>; 1591 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1592 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1593 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1594 dma-names = "tx", "rx"; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 status = "disabled"; 1598 }; 1599 1600 spi8: spi@a80000 { 1601 compatible = "qcom,geni-spi"; 1602 reg = <0 0x00a80000 0 0x4000>; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1605 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1606 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 power-domains = <&rpmhpd RPMHPD_CX>; 1610 operating-points-v2 = <&qup_opp_table>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c9: i2c@a84000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a84000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c9_default>; 1623 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1624 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1625 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1626 dma-names = "tx", "rx"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 spi9: spi@a84000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0 0x00a84000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1638 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1639 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1640 dma-names = "tx", "rx"; 1641 power-domains = <&rpmhpd RPMHPD_CX>; 1642 operating-points-v2 = <&qup_opp_table>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c10: i2c@a88000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00a88000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c10_default>; 1655 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1657 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1658 dma-names = "tx", "rx"; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 spi10: spi@a88000 { 1665 compatible = "qcom,geni-spi"; 1666 reg = <0 0x00a88000 0 0x4000>; 1667 clock-names = "se"; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1670 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1671 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1672 dma-names = "tx", "rx"; 1673 power-domains = <&rpmhpd RPMHPD_CX>; 1674 operating-points-v2 = <&qup_opp_table>; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 status = "disabled"; 1678 }; 1679 1680 i2c11: i2c@a8c000 { 1681 compatible = "qcom,geni-i2c"; 1682 reg = <0 0x00a8c000 0 0x4000>; 1683 clock-names = "se"; 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1685 pinctrl-names = "default"; 1686 pinctrl-0 = <&qup_i2c11_default>; 1687 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1688 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1689 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1690 dma-names = "tx", "rx"; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 spi11: spi@a8c000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0 0x00a8c000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1701 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1702 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1703 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1704 dma-names = "tx", "rx"; 1705 power-domains = <&rpmhpd RPMHPD_CX>; 1706 operating-points-v2 = <&qup_opp_table>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 i2c12: i2c@a90000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a90000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c12_default>; 1719 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1721 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1722 dma-names = "tx", "rx"; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 spi12: spi@a90000 { 1729 compatible = "qcom,geni-spi"; 1730 reg = <0 0x00a90000 0 0x4000>; 1731 clock-names = "se"; 1732 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1735 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1736 dma-names = "tx", "rx"; 1737 power-domains = <&rpmhpd RPMHPD_CX>; 1738 operating-points-v2 = <&qup_opp_table>; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 status = "disabled"; 1742 }; 1743 1744 uart12: serial@a90000 { 1745 compatible = "qcom,geni-debug-uart"; 1746 reg = <0x0 0x00a90000 0x0 0x4000>; 1747 clock-names = "se"; 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_uart12_default>; 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1752 power-domains = <&rpmhpd RPMHPD_CX>; 1753 operating-points-v2 = <&qup_opp_table>; 1754 status = "disabled"; 1755 }; 1756 1757 i2c13: i2c@a94000 { 1758 compatible = "qcom,geni-i2c"; 1759 reg = <0 0x00a94000 0 0x4000>; 1760 clock-names = "se"; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1762 pinctrl-names = "default"; 1763 pinctrl-0 = <&qup_i2c13_default>; 1764 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1765 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1767 dma-names = "tx", "rx"; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 status = "disabled"; 1771 }; 1772 1773 spi13: spi@a94000 { 1774 compatible = "qcom,geni-spi"; 1775 reg = <0 0x00a94000 0 0x4000>; 1776 clock-names = "se"; 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1778 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1779 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1780 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1781 dma-names = "tx", "rx"; 1782 power-domains = <&rpmhpd RPMHPD_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 #address-cells = <1>; 1785 #size-cells = <0>; 1786 status = "disabled"; 1787 }; 1788 }; 1789 1790 config_noc: interconnect@1500000 { 1791 compatible = "qcom,sm8250-config-noc"; 1792 reg = <0 0x01500000 0 0xa580>; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 system_noc: interconnect@1620000 { 1798 compatible = "qcom,sm8250-system-noc"; 1799 reg = <0 0x01620000 0 0x1c200>; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 mc_virt: interconnect@163d000 { 1805 compatible = "qcom,sm8250-mc-virt"; 1806 reg = <0 0x0163d000 0 0x1000>; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 aggre1_noc: interconnect@16e0000 { 1812 compatible = "qcom,sm8250-aggre1-noc"; 1813 reg = <0 0x016e0000 0 0x1f180>; 1814 #interconnect-cells = <2>; 1815 qcom,bcm-voters = <&apps_bcm_voter>; 1816 }; 1817 1818 aggre2_noc: interconnect@1700000 { 1819 compatible = "qcom,sm8250-aggre2-noc"; 1820 reg = <0 0x01700000 0 0x33000>; 1821 #interconnect-cells = <2>; 1822 qcom,bcm-voters = <&apps_bcm_voter>; 1823 }; 1824 1825 compute_noc: interconnect@1733000 { 1826 compatible = "qcom,sm8250-compute-noc"; 1827 reg = <0 0x01733000 0 0xa180>; 1828 #interconnect-cells = <2>; 1829 qcom,bcm-voters = <&apps_bcm_voter>; 1830 }; 1831 1832 mmss_noc: interconnect@1740000 { 1833 compatible = "qcom,sm8250-mmss-noc"; 1834 reg = <0 0x01740000 0 0x1f080>; 1835 #interconnect-cells = <2>; 1836 qcom,bcm-voters = <&apps_bcm_voter>; 1837 }; 1838 1839 pcie0: pci@1c00000 { 1840 compatible = "qcom,pcie-sm8250"; 1841 reg = <0 0x01c00000 0 0x3000>, 1842 <0 0x60000000 0 0xf1d>, 1843 <0 0x60000f20 0 0xa8>, 1844 <0 0x60001000 0 0x1000>, 1845 <0 0x60100000 0 0x100000>, 1846 <0 0x01c03000 0 0x1000>; 1847 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1848 device_type = "pci"; 1849 linux,pci-domain = <0>; 1850 bus-range = <0x00 0xff>; 1851 num-lanes = <1>; 1852 1853 #address-cells = <3>; 1854 #size-cells = <2>; 1855 1856 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1857 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1858 1859 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1867 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1868 "msi4", "msi5", "msi6", "msi7"; 1869 #interrupt-cells = <1>; 1870 interrupt-map-mask = <0 0 0 0x7>; 1871 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1872 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1873 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1874 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1875 1876 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1877 <&gcc GCC_PCIE_0_AUX_CLK>, 1878 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1879 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1880 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1881 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1882 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1883 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1884 clock-names = "pipe", 1885 "aux", 1886 "cfg", 1887 "bus_master", 1888 "bus_slave", 1889 "slave_q2a", 1890 "tbu", 1891 "ddrss_sf_tbu"; 1892 1893 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1894 <0x100 &apps_smmu 0x1c01 0x1>; 1895 1896 resets = <&gcc GCC_PCIE_0_BCR>; 1897 reset-names = "pci"; 1898 1899 power-domains = <&gcc PCIE_0_GDSC>; 1900 1901 phys = <&pcie0_lane>; 1902 phy-names = "pciephy"; 1903 1904 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1905 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1906 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&pcie0_default_state>; 1909 dma-coherent; 1910 1911 status = "disabled"; 1912 }; 1913 1914 pcie0_phy: phy@1c06000 { 1915 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1916 reg = <0 0x01c06000 0 0x1c0>; 1917 #address-cells = <2>; 1918 #size-cells = <2>; 1919 ranges; 1920 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1921 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1922 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1923 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1924 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1925 1926 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1927 reset-names = "phy"; 1928 1929 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1930 assigned-clock-rates = <100000000>; 1931 1932 status = "disabled"; 1933 1934 pcie0_lane: phy@1c06200 { 1935 reg = <0 0x01c06200 0 0x170>, /* tx */ 1936 <0 0x01c06400 0 0x200>, /* rx */ 1937 <0 0x01c06800 0 0x1f0>, /* pcs */ 1938 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1940 clock-names = "pipe0"; 1941 1942 #phy-cells = <0>; 1943 1944 #clock-cells = <0>; 1945 clock-output-names = "pcie_0_pipe_clk"; 1946 }; 1947 }; 1948 1949 pcie1: pci@1c08000 { 1950 compatible = "qcom,pcie-sm8250"; 1951 reg = <0 0x01c08000 0 0x3000>, 1952 <0 0x40000000 0 0xf1d>, 1953 <0 0x40000f20 0 0xa8>, 1954 <0 0x40001000 0 0x1000>, 1955 <0 0x40100000 0 0x100000>, 1956 <0 0x01c0b000 0 0x1000>; 1957 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1958 device_type = "pci"; 1959 linux,pci-domain = <1>; 1960 bus-range = <0x00 0xff>; 1961 num-lanes = <2>; 1962 1963 #address-cells = <3>; 1964 #size-cells = <2>; 1965 1966 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1967 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1968 1969 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupt-names = "msi"; 1971 #interrupt-cells = <1>; 1972 interrupt-map-mask = <0 0 0 0x7>; 1973 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1974 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1975 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1976 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1977 1978 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1979 <&gcc GCC_PCIE_1_AUX_CLK>, 1980 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1981 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1982 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1983 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1984 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1985 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1986 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1987 clock-names = "pipe", 1988 "aux", 1989 "cfg", 1990 "bus_master", 1991 "bus_slave", 1992 "slave_q2a", 1993 "ref", 1994 "tbu", 1995 "ddrss_sf_tbu"; 1996 1997 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1998 assigned-clock-rates = <19200000>; 1999 2000 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2001 <0x100 &apps_smmu 0x1c81 0x1>; 2002 2003 resets = <&gcc GCC_PCIE_1_BCR>; 2004 reset-names = "pci"; 2005 2006 power-domains = <&gcc PCIE_1_GDSC>; 2007 2008 phys = <&pcie1_lane>; 2009 phy-names = "pciephy"; 2010 2011 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2012 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2013 2014 pinctrl-names = "default"; 2015 pinctrl-0 = <&pcie1_default_state>; 2016 dma-coherent; 2017 2018 status = "disabled"; 2019 }; 2020 2021 pcie1_phy: phy@1c0e000 { 2022 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2023 reg = <0 0x01c0e000 0 0x1c0>; 2024 #address-cells = <2>; 2025 #size-cells = <2>; 2026 ranges; 2027 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2028 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2029 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2030 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2031 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2032 2033 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2034 reset-names = "phy"; 2035 2036 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2037 assigned-clock-rates = <100000000>; 2038 2039 status = "disabled"; 2040 2041 pcie1_lane: phy@1c0e200 { 2042 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2043 <0 0x01c0e400 0 0x200>, /* rx0 */ 2044 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2045 <0 0x01c0e600 0 0x170>, /* tx1 */ 2046 <0 0x01c0e800 0 0x200>, /* rx1 */ 2047 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2048 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2049 clock-names = "pipe0"; 2050 2051 #phy-cells = <0>; 2052 2053 #clock-cells = <0>; 2054 clock-output-names = "pcie_1_pipe_clk"; 2055 }; 2056 }; 2057 2058 pcie2: pci@1c10000 { 2059 compatible = "qcom,pcie-sm8250"; 2060 reg = <0 0x01c10000 0 0x3000>, 2061 <0 0x64000000 0 0xf1d>, 2062 <0 0x64000f20 0 0xa8>, 2063 <0 0x64001000 0 0x1000>, 2064 <0 0x64100000 0 0x100000>, 2065 <0 0x01c13000 0 0x1000>; 2066 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2067 device_type = "pci"; 2068 linux,pci-domain = <2>; 2069 bus-range = <0x00 0xff>; 2070 num-lanes = <2>; 2071 2072 #address-cells = <3>; 2073 #size-cells = <2>; 2074 2075 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2076 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2077 2078 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2079 interrupt-names = "msi"; 2080 #interrupt-cells = <1>; 2081 interrupt-map-mask = <0 0 0 0x7>; 2082 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2083 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2084 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2085 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2086 2087 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2088 <&gcc GCC_PCIE_2_AUX_CLK>, 2089 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2090 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2091 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2092 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2093 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2094 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2095 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2096 clock-names = "pipe", 2097 "aux", 2098 "cfg", 2099 "bus_master", 2100 "bus_slave", 2101 "slave_q2a", 2102 "ref", 2103 "tbu", 2104 "ddrss_sf_tbu"; 2105 2106 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2107 assigned-clock-rates = <19200000>; 2108 2109 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2110 <0x100 &apps_smmu 0x1d01 0x1>; 2111 2112 resets = <&gcc GCC_PCIE_2_BCR>; 2113 reset-names = "pci"; 2114 2115 power-domains = <&gcc PCIE_2_GDSC>; 2116 2117 phys = <&pcie2_lane>; 2118 phy-names = "pciephy"; 2119 2120 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2121 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2122 2123 pinctrl-names = "default"; 2124 pinctrl-0 = <&pcie2_default_state>; 2125 dma-coherent; 2126 2127 status = "disabled"; 2128 }; 2129 2130 pcie2_phy: phy@1c16000 { 2131 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2132 reg = <0 0x01c16000 0 0x1c0>; 2133 #address-cells = <2>; 2134 #size-cells = <2>; 2135 ranges; 2136 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2137 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2138 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2139 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2140 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2141 2142 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2143 reset-names = "phy"; 2144 2145 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2146 assigned-clock-rates = <100000000>; 2147 2148 status = "disabled"; 2149 2150 pcie2_lane: phy@1c16200 { 2151 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2152 <0 0x01c16400 0 0x200>, /* rx0 */ 2153 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2154 <0 0x01c16600 0 0x170>, /* tx1 */ 2155 <0 0x01c16800 0 0x200>, /* rx1 */ 2156 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2157 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2158 clock-names = "pipe0"; 2159 2160 #phy-cells = <0>; 2161 2162 #clock-cells = <0>; 2163 clock-output-names = "pcie_2_pipe_clk"; 2164 }; 2165 }; 2166 2167 ufs_mem_hc: ufshc@1d84000 { 2168 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2169 "jedec,ufs-2.0"; 2170 reg = <0 0x01d84000 0 0x3000>; 2171 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2172 phys = <&ufs_mem_phy>; 2173 phy-names = "ufsphy"; 2174 lanes-per-direction = <2>; 2175 #reset-cells = <1>; 2176 resets = <&gcc GCC_UFS_PHY_BCR>; 2177 reset-names = "rst"; 2178 2179 power-domains = <&gcc UFS_PHY_GDSC>; 2180 2181 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2182 2183 clock-names = 2184 "core_clk", 2185 "bus_aggr_clk", 2186 "iface_clk", 2187 "core_clk_unipro", 2188 "ref_clk", 2189 "tx_lane0_sync_clk", 2190 "rx_lane0_sync_clk", 2191 "rx_lane1_sync_clk"; 2192 clocks = 2193 <&gcc GCC_UFS_PHY_AXI_CLK>, 2194 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2195 <&gcc GCC_UFS_PHY_AHB_CLK>, 2196 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2197 <&rpmhcc RPMH_CXO_CLK>, 2198 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2199 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2200 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2201 freq-table-hz = 2202 <37500000 300000000>, 2203 <0 0>, 2204 <0 0>, 2205 <37500000 300000000>, 2206 <0 0>, 2207 <0 0>, 2208 <0 0>, 2209 <0 0>; 2210 2211 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2213 interconnect-names = "ufs-ddr", "cpu-ufs"; 2214 2215 status = "disabled"; 2216 }; 2217 2218 ufs_mem_phy: phy@1d87000 { 2219 compatible = "qcom,sm8250-qmp-ufs-phy"; 2220 reg = <0 0x01d87000 0 0x1000>; 2221 2222 clock-names = "ref", 2223 "ref_aux"; 2224 clocks = <&rpmhcc RPMH_CXO_CLK>, 2225 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2226 2227 resets = <&ufs_mem_hc 0>; 2228 reset-names = "ufsphy"; 2229 2230 power-domains = <&gcc UFS_PHY_GDSC>; 2231 2232 #phy-cells = <0>; 2233 2234 status = "disabled"; 2235 }; 2236 2237 cryptobam: dma-controller@1dc4000 { 2238 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2239 reg = <0 0x01dc4000 0 0x24000>; 2240 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2241 #dma-cells = <1>; 2242 qcom,ee = <0>; 2243 qcom,controlled-remotely; 2244 num-channels = <8>; 2245 qcom,num-ees = <2>; 2246 iommus = <&apps_smmu 0x592 0x0000>, 2247 <&apps_smmu 0x598 0x0000>, 2248 <&apps_smmu 0x599 0x0000>, 2249 <&apps_smmu 0x59f 0x0000>, 2250 <&apps_smmu 0x586 0x0011>, 2251 <&apps_smmu 0x596 0x0011>; 2252 }; 2253 2254 crypto: crypto@1dfa000 { 2255 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2256 reg = <0 0x01dfa000 0 0x6000>; 2257 dmas = <&cryptobam 4>, <&cryptobam 5>; 2258 dma-names = "rx", "tx"; 2259 iommus = <&apps_smmu 0x592 0x0000>, 2260 <&apps_smmu 0x598 0x0000>, 2261 <&apps_smmu 0x599 0x0000>, 2262 <&apps_smmu 0x59f 0x0000>, 2263 <&apps_smmu 0x586 0x0011>, 2264 <&apps_smmu 0x596 0x0011>; 2265 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2266 interconnect-names = "memory"; 2267 }; 2268 2269 tcsr_mutex: hwlock@1f40000 { 2270 compatible = "qcom,tcsr-mutex"; 2271 reg = <0x0 0x01f40000 0x0 0x40000>; 2272 #hwlock-cells = <1>; 2273 }; 2274 2275 wsamacro: codec@3240000 { 2276 compatible = "qcom,sm8250-lpass-wsa-macro"; 2277 reg = <0 0x03240000 0 0x1000>; 2278 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2279 <&audiocc LPASS_CDC_WSA_NPL>, 2280 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2281 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2282 <&aoncc LPASS_CDC_VA_MCLK>, 2283 <&vamacro>; 2284 2285 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2286 2287 #clock-cells = <0>; 2288 clock-output-names = "mclk"; 2289 #sound-dai-cells = <1>; 2290 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&wsa_swr_active>; 2293 2294 status = "disabled"; 2295 }; 2296 2297 swr0: soundwire-controller@3250000 { 2298 reg = <0 0x03250000 0 0x2000>; 2299 compatible = "qcom,soundwire-v1.5.1"; 2300 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2301 clocks = <&wsamacro>; 2302 clock-names = "iface"; 2303 2304 qcom,din-ports = <2>; 2305 qcom,dout-ports = <6>; 2306 2307 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2308 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2309 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2310 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2311 2312 #sound-dai-cells = <1>; 2313 #address-cells = <2>; 2314 #size-cells = <0>; 2315 2316 status = "disabled"; 2317 }; 2318 2319 audiocc: clock-controller@3300000 { 2320 compatible = "qcom,sm8250-lpass-audiocc"; 2321 reg = <0 0x03300000 0 0x30000>; 2322 #clock-cells = <1>; 2323 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2324 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2325 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2326 clock-names = "core", "audio", "bus"; 2327 }; 2328 2329 vamacro: codec@3370000 { 2330 compatible = "qcom,sm8250-lpass-va-macro"; 2331 reg = <0 0x03370000 0 0x1000>; 2332 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2333 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2334 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2335 2336 clock-names = "mclk", "macro", "dcodec"; 2337 2338 #clock-cells = <0>; 2339 clock-output-names = "fsgen"; 2340 #sound-dai-cells = <1>; 2341 }; 2342 2343 rxmacro: rxmacro@3200000 { 2344 pinctrl-names = "default"; 2345 pinctrl-0 = <&rx_swr_active>; 2346 compatible = "qcom,sm8250-lpass-rx-macro"; 2347 reg = <0 0x03200000 0 0x1000>; 2348 status = "disabled"; 2349 2350 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2351 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2352 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2353 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2354 <&vamacro>; 2355 2356 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2357 2358 #clock-cells = <0>; 2359 clock-output-names = "mclk"; 2360 #sound-dai-cells = <1>; 2361 }; 2362 2363 swr1: soundwire-controller@3210000 { 2364 reg = <0 0x03210000 0 0x2000>; 2365 compatible = "qcom,soundwire-v1.5.1"; 2366 status = "disabled"; 2367 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2368 clocks = <&rxmacro>; 2369 clock-names = "iface"; 2370 label = "RX"; 2371 qcom,din-ports = <0>; 2372 qcom,dout-ports = <5>; 2373 2374 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2375 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2376 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2377 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2378 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2379 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2380 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2381 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2382 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2383 2384 #sound-dai-cells = <1>; 2385 #address-cells = <2>; 2386 #size-cells = <0>; 2387 }; 2388 2389 txmacro: txmacro@3220000 { 2390 pinctrl-names = "default"; 2391 pinctrl-0 = <&tx_swr_active>; 2392 compatible = "qcom,sm8250-lpass-tx-macro"; 2393 reg = <0 0x03220000 0 0x1000>; 2394 status = "disabled"; 2395 2396 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2397 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2398 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2399 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2400 <&vamacro>; 2401 2402 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2403 2404 #clock-cells = <0>; 2405 clock-output-names = "mclk"; 2406 #sound-dai-cells = <1>; 2407 }; 2408 2409 /* tx macro */ 2410 swr2: soundwire-controller@3230000 { 2411 reg = <0 0x03230000 0 0x2000>; 2412 compatible = "qcom,soundwire-v1.5.1"; 2413 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2414 interrupt-names = "core"; 2415 status = "disabled"; 2416 2417 clocks = <&txmacro>; 2418 clock-names = "iface"; 2419 label = "TX"; 2420 2421 qcom,din-ports = <5>; 2422 qcom,dout-ports = <0>; 2423 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2424 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2425 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2426 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2427 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2428 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2429 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2431 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2432 #sound-dai-cells = <1>; 2433 #address-cells = <2>; 2434 #size-cells = <0>; 2435 }; 2436 2437 aoncc: clock-controller@3380000 { 2438 compatible = "qcom,sm8250-lpass-aoncc"; 2439 reg = <0 0x03380000 0 0x40000>; 2440 #clock-cells = <1>; 2441 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2442 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2443 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2444 clock-names = "core", "audio", "bus"; 2445 }; 2446 2447 lpass_tlmm: pinctrl@33c0000 { 2448 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2449 reg = <0 0x033c0000 0x0 0x20000>, 2450 <0 0x03550000 0x0 0x10000>; 2451 gpio-controller; 2452 #gpio-cells = <2>; 2453 gpio-ranges = <&lpass_tlmm 0 0 14>; 2454 2455 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2456 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2457 clock-names = "core", "audio"; 2458 2459 wsa_swr_active: wsa-swr-active-state { 2460 clk-pins { 2461 pins = "gpio10"; 2462 function = "wsa_swr_clk"; 2463 drive-strength = <2>; 2464 slew-rate = <1>; 2465 bias-disable; 2466 }; 2467 2468 data-pins { 2469 pins = "gpio11"; 2470 function = "wsa_swr_data"; 2471 drive-strength = <2>; 2472 slew-rate = <1>; 2473 bias-bus-hold; 2474 }; 2475 }; 2476 2477 wsa_swr_sleep: wsa-swr-sleep-state { 2478 clk-pins { 2479 pins = "gpio10"; 2480 function = "wsa_swr_clk"; 2481 drive-strength = <2>; 2482 bias-pull-down; 2483 }; 2484 2485 data-pins { 2486 pins = "gpio11"; 2487 function = "wsa_swr_data"; 2488 drive-strength = <2>; 2489 bias-pull-down; 2490 }; 2491 }; 2492 2493 dmic01_active: dmic01-active-state { 2494 clk-pins { 2495 pins = "gpio6"; 2496 function = "dmic1_clk"; 2497 drive-strength = <8>; 2498 output-high; 2499 }; 2500 data-pins { 2501 pins = "gpio7"; 2502 function = "dmic1_data"; 2503 drive-strength = <8>; 2504 }; 2505 }; 2506 2507 dmic01_sleep: dmic01-sleep-state { 2508 clk-pins { 2509 pins = "gpio6"; 2510 function = "dmic1_clk"; 2511 drive-strength = <2>; 2512 bias-disable; 2513 output-low; 2514 }; 2515 2516 data-pins { 2517 pins = "gpio7"; 2518 function = "dmic1_data"; 2519 drive-strength = <2>; 2520 bias-pull-down; 2521 }; 2522 }; 2523 2524 rx_swr_active: rx-swr-active-state { 2525 clk-pins { 2526 pins = "gpio3"; 2527 function = "swr_rx_clk"; 2528 drive-strength = <2>; 2529 slew-rate = <1>; 2530 bias-disable; 2531 }; 2532 2533 data-pins { 2534 pins = "gpio4", "gpio5"; 2535 function = "swr_rx_data"; 2536 drive-strength = <2>; 2537 slew-rate = <1>; 2538 bias-bus-hold; 2539 }; 2540 }; 2541 2542 tx_swr_active: tx-swr-active-state { 2543 clk-pins { 2544 pins = "gpio0"; 2545 function = "swr_tx_clk"; 2546 drive-strength = <2>; 2547 slew-rate = <1>; 2548 bias-disable; 2549 }; 2550 2551 data-pins { 2552 pins = "gpio1", "gpio2"; 2553 function = "swr_tx_data"; 2554 drive-strength = <2>; 2555 slew-rate = <1>; 2556 bias-bus-hold; 2557 }; 2558 }; 2559 2560 tx_swr_sleep: tx-swr-sleep-state { 2561 clk-pins { 2562 pins = "gpio0"; 2563 function = "swr_tx_clk"; 2564 drive-strength = <2>; 2565 bias-pull-down; 2566 }; 2567 2568 data1-pins { 2569 pins = "gpio1"; 2570 function = "swr_tx_data"; 2571 drive-strength = <2>; 2572 bias-bus-hold; 2573 }; 2574 2575 data2-pins { 2576 pins = "gpio2"; 2577 function = "swr_tx_data"; 2578 drive-strength = <2>; 2579 bias-pull-down; 2580 }; 2581 }; 2582 }; 2583 2584 gpu: gpu@3d00000 { 2585 compatible = "qcom,adreno-650.2", 2586 "qcom,adreno"; 2587 2588 reg = <0 0x03d00000 0 0x40000>; 2589 reg-names = "kgsl_3d0_reg_memory"; 2590 2591 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2592 2593 iommus = <&adreno_smmu 0 0x401>; 2594 2595 operating-points-v2 = <&gpu_opp_table>; 2596 2597 qcom,gmu = <&gmu>; 2598 2599 nvmem-cells = <&gpu_speed_bin>; 2600 nvmem-cell-names = "speed_bin"; 2601 2602 status = "disabled"; 2603 2604 zap-shader { 2605 memory-region = <&gpu_mem>; 2606 }; 2607 2608 gpu_opp_table: opp-table { 2609 compatible = "operating-points-v2"; 2610 2611 opp-670000000 { 2612 opp-hz = /bits/ 64 <670000000>; 2613 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2614 opp-supported-hw = <0xa>; 2615 }; 2616 2617 opp-587000000 { 2618 opp-hz = /bits/ 64 <587000000>; 2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2620 opp-supported-hw = <0xb>; 2621 }; 2622 2623 opp-525000000 { 2624 opp-hz = /bits/ 64 <525000000>; 2625 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2626 opp-supported-hw = <0xf>; 2627 }; 2628 2629 opp-490000000 { 2630 opp-hz = /bits/ 64 <490000000>; 2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2632 opp-supported-hw = <0xf>; 2633 }; 2634 2635 opp-441600000 { 2636 opp-hz = /bits/ 64 <441600000>; 2637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2638 opp-supported-hw = <0xf>; 2639 }; 2640 2641 opp-400000000 { 2642 opp-hz = /bits/ 64 <400000000>; 2643 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2644 opp-supported-hw = <0xf>; 2645 }; 2646 2647 opp-305000000 { 2648 opp-hz = /bits/ 64 <305000000>; 2649 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2650 opp-supported-hw = <0xf>; 2651 }; 2652 }; 2653 }; 2654 2655 gmu: gmu@3d6a000 { 2656 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2657 2658 reg = <0 0x03d6a000 0 0x30000>, 2659 <0 0x3de0000 0 0x10000>, 2660 <0 0xb290000 0 0x10000>, 2661 <0 0xb490000 0 0x10000>; 2662 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2663 2664 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2666 interrupt-names = "hfi", "gmu"; 2667 2668 clocks = <&gpucc GPU_CC_AHB_CLK>, 2669 <&gpucc GPU_CC_CX_GMU_CLK>, 2670 <&gpucc GPU_CC_CXO_CLK>, 2671 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2672 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2673 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2674 2675 power-domains = <&gpucc GPU_CX_GDSC>, 2676 <&gpucc GPU_GX_GDSC>; 2677 power-domain-names = "cx", "gx"; 2678 2679 iommus = <&adreno_smmu 5 0x400>; 2680 2681 operating-points-v2 = <&gmu_opp_table>; 2682 2683 status = "disabled"; 2684 2685 gmu_opp_table: opp-table { 2686 compatible = "operating-points-v2"; 2687 2688 opp-200000000 { 2689 opp-hz = /bits/ 64 <200000000>; 2690 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2691 }; 2692 }; 2693 }; 2694 2695 gpucc: clock-controller@3d90000 { 2696 compatible = "qcom,sm8250-gpucc"; 2697 reg = <0 0x03d90000 0 0x9000>; 2698 clocks = <&rpmhcc RPMH_CXO_CLK>, 2699 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2700 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2701 clock-names = "bi_tcxo", 2702 "gcc_gpu_gpll0_clk_src", 2703 "gcc_gpu_gpll0_div_clk_src"; 2704 #clock-cells = <1>; 2705 #reset-cells = <1>; 2706 #power-domain-cells = <1>; 2707 }; 2708 2709 adreno_smmu: iommu@3da0000 { 2710 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 2711 "qcom,smmu-500", "arm,mmu-500"; 2712 reg = <0 0x03da0000 0 0x10000>; 2713 #iommu-cells = <2>; 2714 #global-interrupts = <2>; 2715 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2725 clocks = <&gpucc GPU_CC_AHB_CLK>, 2726 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2727 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2728 clock-names = "ahb", "bus", "iface"; 2729 2730 power-domains = <&gpucc GPU_CX_GDSC>; 2731 dma-coherent; 2732 }; 2733 2734 slpi: remoteproc@5c00000 { 2735 compatible = "qcom,sm8250-slpi-pas"; 2736 reg = <0 0x05c00000 0 0x4000>; 2737 2738 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2739 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2740 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2741 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2742 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2743 interrupt-names = "wdog", "fatal", "ready", 2744 "handover", "stop-ack"; 2745 2746 clocks = <&rpmhcc RPMH_CXO_CLK>; 2747 clock-names = "xo"; 2748 2749 power-domains = <&rpmhpd RPMHPD_LCX>, 2750 <&rpmhpd RPMHPD_LMX>; 2751 power-domain-names = "lcx", "lmx"; 2752 2753 memory-region = <&slpi_mem>; 2754 2755 qcom,qmp = <&aoss_qmp>; 2756 2757 qcom,smem-states = <&smp2p_slpi_out 0>; 2758 qcom,smem-state-names = "stop"; 2759 2760 status = "disabled"; 2761 2762 glink-edge { 2763 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2764 IPCC_MPROC_SIGNAL_GLINK_QMP 2765 IRQ_TYPE_EDGE_RISING>; 2766 mboxes = <&ipcc IPCC_CLIENT_SLPI 2767 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2768 2769 label = "slpi"; 2770 qcom,remote-pid = <3>; 2771 2772 fastrpc { 2773 compatible = "qcom,fastrpc"; 2774 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2775 label = "sdsp"; 2776 qcom,non-secure-domain; 2777 #address-cells = <1>; 2778 #size-cells = <0>; 2779 2780 compute-cb@1 { 2781 compatible = "qcom,fastrpc-compute-cb"; 2782 reg = <1>; 2783 iommus = <&apps_smmu 0x0541 0x0>; 2784 }; 2785 2786 compute-cb@2 { 2787 compatible = "qcom,fastrpc-compute-cb"; 2788 reg = <2>; 2789 iommus = <&apps_smmu 0x0542 0x0>; 2790 }; 2791 2792 compute-cb@3 { 2793 compatible = "qcom,fastrpc-compute-cb"; 2794 reg = <3>; 2795 iommus = <&apps_smmu 0x0543 0x0>; 2796 /* note: shared-cb = <4> in downstream */ 2797 }; 2798 }; 2799 }; 2800 }; 2801 2802 stm@6002000 { 2803 compatible = "arm,coresight-stm", "arm,primecell"; 2804 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2805 reg-names = "stm-base", "stm-stimulus-base"; 2806 2807 clocks = <&aoss_qmp>; 2808 clock-names = "apb_pclk"; 2809 2810 out-ports { 2811 port { 2812 stm_out: endpoint { 2813 remote-endpoint = <&funnel0_in7>; 2814 }; 2815 }; 2816 }; 2817 }; 2818 2819 tpda@6004000 { 2820 compatible = "qcom,coresight-tpda", "arm,primecell"; 2821 reg = <0 0x06004000 0 0x1000>; 2822 2823 clocks = <&aoss_qmp>; 2824 clock-names = "apb_pclk"; 2825 2826 out-ports { 2827 2828 port { 2829 tpda_out_funnel_qatb: endpoint { 2830 remote-endpoint = <&funnel_qatb_in_tpda>; 2831 }; 2832 }; 2833 }; 2834 2835 in-ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@9 { 2840 reg = <9>; 2841 tpda_9_in_tpdm_mm: endpoint { 2842 remote-endpoint = <&tpdm_mm_out_tpda9>; 2843 }; 2844 }; 2845 2846 port@17 { 2847 reg = <23>; 2848 tpda_23_in_tpdm_prng: endpoint { 2849 remote-endpoint = <&tpdm_prng_out_tpda_23>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 funnel@6005000 { 2856 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2857 reg = <0 0x06005000 0 0x1000>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 out-ports { 2863 port { 2864 funnel_qatb_out_funnel_in0: endpoint { 2865 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 2866 }; 2867 }; 2868 }; 2869 2870 in-ports { 2871 port { 2872 funnel_qatb_in_tpda: endpoint { 2873 remote-endpoint = <&tpda_out_funnel_qatb>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 funnel@6041000 { 2880 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2881 reg = <0 0x06041000 0 0x1000>; 2882 2883 clocks = <&aoss_qmp>; 2884 clock-names = "apb_pclk"; 2885 2886 out-ports { 2887 port { 2888 funnel_in0_out_funnel_merg: endpoint { 2889 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2890 }; 2891 }; 2892 }; 2893 2894 in-ports { 2895 #address-cells = <1>; 2896 #size-cells = <0>; 2897 2898 port@6 { 2899 reg = <6>; 2900 funnel_in0_in_funnel_qatb: endpoint { 2901 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 2902 }; 2903 }; 2904 2905 port@7 { 2906 reg = <7>; 2907 funnel0_in7: endpoint { 2908 remote-endpoint = <&stm_out>; 2909 }; 2910 }; 2911 }; 2912 }; 2913 2914 funnel@6042000 { 2915 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2916 reg = <0 0x06042000 0 0x1000>; 2917 2918 clocks = <&aoss_qmp>; 2919 clock-names = "apb_pclk"; 2920 2921 out-ports { 2922 port { 2923 funnel_in1_out_funnel_merg: endpoint { 2924 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2925 }; 2926 }; 2927 }; 2928 2929 in-ports { 2930 #address-cells = <1>; 2931 #size-cells = <0>; 2932 2933 port@4 { 2934 reg = <4>; 2935 funnel_in1_in_funnel_apss_merg: endpoint { 2936 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2937 }; 2938 }; 2939 }; 2940 }; 2941 2942 funnel@6045000 { 2943 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2944 reg = <0 0x06045000 0 0x1000>; 2945 2946 clocks = <&aoss_qmp>; 2947 clock-names = "apb_pclk"; 2948 2949 out-ports { 2950 port { 2951 funnel_merg_out_funnel_swao: endpoint { 2952 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2953 }; 2954 }; 2955 }; 2956 2957 in-ports { 2958 #address-cells = <1>; 2959 #size-cells = <0>; 2960 2961 port@0 { 2962 reg = <0>; 2963 funnel_merg_in_funnel_in0: endpoint { 2964 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2965 }; 2966 }; 2967 2968 port@1 { 2969 reg = <1>; 2970 funnel_merg_in_funnel_in1: endpoint { 2971 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2972 }; 2973 }; 2974 }; 2975 }; 2976 2977 replicator@6046000 { 2978 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2979 reg = <0 0x06046000 0 0x1000>; 2980 2981 clocks = <&aoss_qmp>; 2982 clock-names = "apb_pclk"; 2983 2984 out-ports { 2985 port { 2986 replicator_out: endpoint { 2987 remote-endpoint = <&etr_in>; 2988 }; 2989 }; 2990 }; 2991 2992 in-ports { 2993 port { 2994 replicator_cx_in_swao_out: endpoint { 2995 remote-endpoint = <&replicator_swao_out_cx_in>; 2996 }; 2997 }; 2998 }; 2999 }; 3000 3001 etr@6048000 { 3002 compatible = "arm,coresight-tmc", "arm,primecell"; 3003 reg = <0 0x06048000 0 0x1000>; 3004 3005 clocks = <&aoss_qmp>; 3006 clock-names = "apb_pclk"; 3007 arm,scatter-gather; 3008 3009 in-ports { 3010 port { 3011 etr_in: endpoint { 3012 remote-endpoint = <&replicator_out>; 3013 }; 3014 }; 3015 }; 3016 }; 3017 3018 tpdm@684c000 { 3019 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3020 reg = <0 0x0684c000 0 0x1000>; 3021 3022 clocks = <&aoss_qmp>; 3023 clock-names = "apb_pclk"; 3024 3025 out-ports { 3026 port { 3027 tpdm_prng_out_tpda_23: endpoint { 3028 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3029 }; 3030 }; 3031 }; 3032 }; 3033 3034 funnel@6b04000 { 3035 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3036 arm,primecell-periphid = <0x000bb908>; 3037 3038 reg = <0 0x06b04000 0 0x1000>; 3039 3040 clocks = <&aoss_qmp>; 3041 clock-names = "apb_pclk"; 3042 3043 out-ports { 3044 port { 3045 funnel_swao_out_etf: endpoint { 3046 remote-endpoint = <&etf_in_funnel_swao_out>; 3047 }; 3048 }; 3049 }; 3050 3051 in-ports { 3052 #address-cells = <1>; 3053 #size-cells = <0>; 3054 3055 port@7 { 3056 reg = <7>; 3057 funnel_swao_in_funnel_merg: endpoint { 3058 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 etf@6b05000 { 3065 compatible = "arm,coresight-tmc", "arm,primecell"; 3066 reg = <0 0x06b05000 0 0x1000>; 3067 3068 clocks = <&aoss_qmp>; 3069 clock-names = "apb_pclk"; 3070 3071 out-ports { 3072 port { 3073 etf_out: endpoint { 3074 remote-endpoint = <&replicator_in>; 3075 }; 3076 }; 3077 }; 3078 3079 in-ports { 3080 3081 port { 3082 etf_in_funnel_swao_out: endpoint { 3083 remote-endpoint = <&funnel_swao_out_etf>; 3084 }; 3085 }; 3086 }; 3087 }; 3088 3089 replicator@6b06000 { 3090 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3091 reg = <0 0x06b06000 0 0x1000>; 3092 3093 clocks = <&aoss_qmp>; 3094 clock-names = "apb_pclk"; 3095 3096 out-ports { 3097 port { 3098 replicator_swao_out_cx_in: endpoint { 3099 remote-endpoint = <&replicator_cx_in_swao_out>; 3100 }; 3101 }; 3102 }; 3103 3104 in-ports { 3105 port { 3106 replicator_in: endpoint { 3107 remote-endpoint = <&etf_out>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 tpdm@6c08000 { 3114 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3115 reg = <0 0x06c08000 0 0x1000>; 3116 3117 clocks = <&aoss_qmp>; 3118 clock-names = "apb_pclk"; 3119 3120 out-ports { 3121 port { 3122 tpdm_mm_out_funnel_dl_mm: endpoint { 3123 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 funnel@6c0b000 { 3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3131 reg = <0 0x06c0b000 0 0x1000>; 3132 3133 clocks = <&aoss_qmp>; 3134 clock-names = "apb_pclk"; 3135 3136 out-ports { 3137 port { 3138 funnel_dl_mm_out_funnel_dl_center: endpoint { 3139 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3140 }; 3141 }; 3142 }; 3143 3144 in-ports { 3145 #address-cells = <1>; 3146 #size-cells = <0>; 3147 3148 port@3 { 3149 reg = <3>; 3150 funnel_dl_mm_in_tpdm_mm: endpoint { 3151 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3152 }; 3153 }; 3154 }; 3155 }; 3156 3157 funnel@6c2d000 { 3158 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3159 reg = <0 0x06c2d000 0 0x1000>; 3160 3161 clocks = <&aoss_qmp>; 3162 clock-names = "apb_pclk"; 3163 3164 out-ports { 3165 port { 3166 tpdm_mm_out_tpda9: endpoint { 3167 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3168 }; 3169 }; 3170 }; 3171 3172 in-ports { 3173 #address-cells = <1>; 3174 #size-cells = <0>; 3175 3176 port@2 { 3177 reg = <2>; 3178 funnel_dl_center_in_funnel_dl_mm: endpoint { 3179 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3180 }; 3181 }; 3182 }; 3183 }; 3184 3185 etm@7040000 { 3186 compatible = "arm,coresight-etm4x", "arm,primecell"; 3187 reg = <0 0x07040000 0 0x1000>; 3188 3189 cpu = <&CPU0>; 3190 3191 clocks = <&aoss_qmp>; 3192 clock-names = "apb_pclk"; 3193 arm,coresight-loses-context-with-cpu; 3194 3195 out-ports { 3196 port { 3197 etm0_out: endpoint { 3198 remote-endpoint = <&apss_funnel_in0>; 3199 }; 3200 }; 3201 }; 3202 }; 3203 3204 etm@7140000 { 3205 compatible = "arm,coresight-etm4x", "arm,primecell"; 3206 reg = <0 0x07140000 0 0x1000>; 3207 3208 cpu = <&CPU1>; 3209 3210 clocks = <&aoss_qmp>; 3211 clock-names = "apb_pclk"; 3212 arm,coresight-loses-context-with-cpu; 3213 3214 out-ports { 3215 port { 3216 etm1_out: endpoint { 3217 remote-endpoint = <&apss_funnel_in1>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 etm@7240000 { 3224 compatible = "arm,coresight-etm4x", "arm,primecell"; 3225 reg = <0 0x07240000 0 0x1000>; 3226 3227 cpu = <&CPU2>; 3228 3229 clocks = <&aoss_qmp>; 3230 clock-names = "apb_pclk"; 3231 arm,coresight-loses-context-with-cpu; 3232 3233 out-ports { 3234 port { 3235 etm2_out: endpoint { 3236 remote-endpoint = <&apss_funnel_in2>; 3237 }; 3238 }; 3239 }; 3240 }; 3241 3242 etm@7340000 { 3243 compatible = "arm,coresight-etm4x", "arm,primecell"; 3244 reg = <0 0x07340000 0 0x1000>; 3245 3246 cpu = <&CPU3>; 3247 3248 clocks = <&aoss_qmp>; 3249 clock-names = "apb_pclk"; 3250 arm,coresight-loses-context-with-cpu; 3251 3252 out-ports { 3253 port { 3254 etm3_out: endpoint { 3255 remote-endpoint = <&apss_funnel_in3>; 3256 }; 3257 }; 3258 }; 3259 }; 3260 3261 etm@7440000 { 3262 compatible = "arm,coresight-etm4x", "arm,primecell"; 3263 reg = <0 0x07440000 0 0x1000>; 3264 3265 cpu = <&CPU4>; 3266 3267 clocks = <&aoss_qmp>; 3268 clock-names = "apb_pclk"; 3269 arm,coresight-loses-context-with-cpu; 3270 3271 out-ports { 3272 port { 3273 etm4_out: endpoint { 3274 remote-endpoint = <&apss_funnel_in4>; 3275 }; 3276 }; 3277 }; 3278 }; 3279 3280 etm@7540000 { 3281 compatible = "arm,coresight-etm4x", "arm,primecell"; 3282 reg = <0 0x07540000 0 0x1000>; 3283 3284 cpu = <&CPU5>; 3285 3286 clocks = <&aoss_qmp>; 3287 clock-names = "apb_pclk"; 3288 arm,coresight-loses-context-with-cpu; 3289 3290 out-ports { 3291 port { 3292 etm5_out: endpoint { 3293 remote-endpoint = <&apss_funnel_in5>; 3294 }; 3295 }; 3296 }; 3297 }; 3298 3299 etm@7640000 { 3300 compatible = "arm,coresight-etm4x", "arm,primecell"; 3301 reg = <0 0x07640000 0 0x1000>; 3302 3303 cpu = <&CPU6>; 3304 3305 clocks = <&aoss_qmp>; 3306 clock-names = "apb_pclk"; 3307 arm,coresight-loses-context-with-cpu; 3308 3309 out-ports { 3310 port { 3311 etm6_out: endpoint { 3312 remote-endpoint = <&apss_funnel_in6>; 3313 }; 3314 }; 3315 }; 3316 }; 3317 3318 etm@7740000 { 3319 compatible = "arm,coresight-etm4x", "arm,primecell"; 3320 reg = <0 0x07740000 0 0x1000>; 3321 3322 cpu = <&CPU7>; 3323 3324 clocks = <&aoss_qmp>; 3325 clock-names = "apb_pclk"; 3326 arm,coresight-loses-context-with-cpu; 3327 3328 out-ports { 3329 port { 3330 etm7_out: endpoint { 3331 remote-endpoint = <&apss_funnel_in7>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 funnel@7800000 { 3338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3339 reg = <0 0x07800000 0 0x1000>; 3340 3341 clocks = <&aoss_qmp>; 3342 clock-names = "apb_pclk"; 3343 3344 out-ports { 3345 port { 3346 funnel_apss_out_funnel_apss_merg: endpoint { 3347 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3348 }; 3349 }; 3350 }; 3351 3352 in-ports { 3353 #address-cells = <1>; 3354 #size-cells = <0>; 3355 3356 port@0 { 3357 reg = <0>; 3358 apss_funnel_in0: endpoint { 3359 remote-endpoint = <&etm0_out>; 3360 }; 3361 }; 3362 3363 port@1 { 3364 reg = <1>; 3365 apss_funnel_in1: endpoint { 3366 remote-endpoint = <&etm1_out>; 3367 }; 3368 }; 3369 3370 port@2 { 3371 reg = <2>; 3372 apss_funnel_in2: endpoint { 3373 remote-endpoint = <&etm2_out>; 3374 }; 3375 }; 3376 3377 port@3 { 3378 reg = <3>; 3379 apss_funnel_in3: endpoint { 3380 remote-endpoint = <&etm3_out>; 3381 }; 3382 }; 3383 3384 port@4 { 3385 reg = <4>; 3386 apss_funnel_in4: endpoint { 3387 remote-endpoint = <&etm4_out>; 3388 }; 3389 }; 3390 3391 port@5 { 3392 reg = <5>; 3393 apss_funnel_in5: endpoint { 3394 remote-endpoint = <&etm5_out>; 3395 }; 3396 }; 3397 3398 port@6 { 3399 reg = <6>; 3400 apss_funnel_in6: endpoint { 3401 remote-endpoint = <&etm6_out>; 3402 }; 3403 }; 3404 3405 port@7 { 3406 reg = <7>; 3407 apss_funnel_in7: endpoint { 3408 remote-endpoint = <&etm7_out>; 3409 }; 3410 }; 3411 }; 3412 }; 3413 3414 funnel@7810000 { 3415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3416 reg = <0 0x07810000 0 0x1000>; 3417 3418 clocks = <&aoss_qmp>; 3419 clock-names = "apb_pclk"; 3420 3421 out-ports { 3422 port { 3423 funnel_apss_merg_out_funnel_in1: endpoint { 3424 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3425 }; 3426 }; 3427 }; 3428 3429 in-ports { 3430 port { 3431 funnel_apss_merg_in_funnel_apss: endpoint { 3432 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3433 }; 3434 }; 3435 }; 3436 }; 3437 3438 cdsp: remoteproc@8300000 { 3439 compatible = "qcom,sm8250-cdsp-pas"; 3440 reg = <0 0x08300000 0 0x10000>; 3441 3442 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3443 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3444 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3445 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3446 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3447 interrupt-names = "wdog", "fatal", "ready", 3448 "handover", "stop-ack"; 3449 3450 clocks = <&rpmhcc RPMH_CXO_CLK>; 3451 clock-names = "xo"; 3452 3453 power-domains = <&rpmhpd RPMHPD_CX>; 3454 3455 memory-region = <&cdsp_mem>; 3456 3457 qcom,qmp = <&aoss_qmp>; 3458 3459 qcom,smem-states = <&smp2p_cdsp_out 0>; 3460 qcom,smem-state-names = "stop"; 3461 3462 status = "disabled"; 3463 3464 glink-edge { 3465 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3466 IPCC_MPROC_SIGNAL_GLINK_QMP 3467 IRQ_TYPE_EDGE_RISING>; 3468 mboxes = <&ipcc IPCC_CLIENT_CDSP 3469 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3470 3471 label = "cdsp"; 3472 qcom,remote-pid = <5>; 3473 3474 fastrpc { 3475 compatible = "qcom,fastrpc"; 3476 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3477 label = "cdsp"; 3478 qcom,non-secure-domain; 3479 #address-cells = <1>; 3480 #size-cells = <0>; 3481 3482 compute-cb@1 { 3483 compatible = "qcom,fastrpc-compute-cb"; 3484 reg = <1>; 3485 iommus = <&apps_smmu 0x1001 0x0460>; 3486 }; 3487 3488 compute-cb@2 { 3489 compatible = "qcom,fastrpc-compute-cb"; 3490 reg = <2>; 3491 iommus = <&apps_smmu 0x1002 0x0460>; 3492 }; 3493 3494 compute-cb@3 { 3495 compatible = "qcom,fastrpc-compute-cb"; 3496 reg = <3>; 3497 iommus = <&apps_smmu 0x1003 0x0460>; 3498 }; 3499 3500 compute-cb@4 { 3501 compatible = "qcom,fastrpc-compute-cb"; 3502 reg = <4>; 3503 iommus = <&apps_smmu 0x1004 0x0460>; 3504 }; 3505 3506 compute-cb@5 { 3507 compatible = "qcom,fastrpc-compute-cb"; 3508 reg = <5>; 3509 iommus = <&apps_smmu 0x1005 0x0460>; 3510 }; 3511 3512 compute-cb@6 { 3513 compatible = "qcom,fastrpc-compute-cb"; 3514 reg = <6>; 3515 iommus = <&apps_smmu 0x1006 0x0460>; 3516 }; 3517 3518 compute-cb@7 { 3519 compatible = "qcom,fastrpc-compute-cb"; 3520 reg = <7>; 3521 iommus = <&apps_smmu 0x1007 0x0460>; 3522 }; 3523 3524 compute-cb@8 { 3525 compatible = "qcom,fastrpc-compute-cb"; 3526 reg = <8>; 3527 iommus = <&apps_smmu 0x1008 0x0460>; 3528 }; 3529 3530 /* note: secure cb9 in downstream */ 3531 }; 3532 }; 3533 }; 3534 3535 usb_1_hsphy: phy@88e3000 { 3536 compatible = "qcom,sm8250-usb-hs-phy", 3537 "qcom,usb-snps-hs-7nm-phy"; 3538 reg = <0 0x088e3000 0 0x400>; 3539 status = "disabled"; 3540 #phy-cells = <0>; 3541 3542 clocks = <&rpmhcc RPMH_CXO_CLK>; 3543 clock-names = "ref"; 3544 3545 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3546 }; 3547 3548 usb_2_hsphy: phy@88e4000 { 3549 compatible = "qcom,sm8250-usb-hs-phy", 3550 "qcom,usb-snps-hs-7nm-phy"; 3551 reg = <0 0x088e4000 0 0x400>; 3552 status = "disabled"; 3553 #phy-cells = <0>; 3554 3555 clocks = <&rpmhcc RPMH_CXO_CLK>; 3556 clock-names = "ref"; 3557 3558 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3559 }; 3560 3561 usb_1_qmpphy: phy@88e9000 { 3562 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3563 reg = <0 0x088e9000 0 0x200>, 3564 <0 0x088e8000 0 0x40>, 3565 <0 0x088ea000 0 0x200>; 3566 status = "disabled"; 3567 #address-cells = <2>; 3568 #size-cells = <2>; 3569 ranges; 3570 3571 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3572 <&rpmhcc RPMH_CXO_CLK>, 3573 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3574 clock-names = "aux", "ref_clk_src", "com_aux"; 3575 3576 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3577 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3578 reset-names = "phy", "common"; 3579 3580 usb_1_ssphy: usb3-phy@88e9200 { 3581 reg = <0 0x088e9200 0 0x200>, 3582 <0 0x088e9400 0 0x200>, 3583 <0 0x088e9c00 0 0x400>, 3584 <0 0x088e9600 0 0x200>, 3585 <0 0x088e9800 0 0x200>, 3586 <0 0x088e9a00 0 0x100>; 3587 #clock-cells = <0>; 3588 #phy-cells = <0>; 3589 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3590 clock-names = "pipe0"; 3591 clock-output-names = "usb3_phy_pipe_clk_src"; 3592 }; 3593 3594 dp_phy: dp-phy@88ea200 { 3595 reg = <0 0x088ea200 0 0x200>, 3596 <0 0x088ea400 0 0x200>, 3597 <0 0x088eaa00 0 0x200>, 3598 <0 0x088ea600 0 0x200>, 3599 <0 0x088ea800 0 0x200>; 3600 #phy-cells = <0>; 3601 #clock-cells = <1>; 3602 }; 3603 }; 3604 3605 usb_2_qmpphy: phy@88eb000 { 3606 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3607 reg = <0 0x088eb000 0 0x200>; 3608 status = "disabled"; 3609 #address-cells = <2>; 3610 #size-cells = <2>; 3611 ranges; 3612 3613 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3614 <&rpmhcc RPMH_CXO_CLK>, 3615 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3616 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3617 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3618 3619 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3620 <&gcc GCC_USB3_PHY_SEC_BCR>; 3621 reset-names = "phy", "common"; 3622 3623 usb_2_ssphy: phy@88eb200 { 3624 reg = <0 0x088eb200 0 0x200>, 3625 <0 0x088eb400 0 0x200>, 3626 <0 0x088eb800 0 0x800>; 3627 #clock-cells = <0>; 3628 #phy-cells = <0>; 3629 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3630 clock-names = "pipe0"; 3631 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3632 }; 3633 }; 3634 3635 sdhc_2: mmc@8804000 { 3636 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3637 reg = <0 0x08804000 0 0x1000>; 3638 3639 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3641 interrupt-names = "hc_irq", "pwr_irq"; 3642 3643 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3644 <&gcc GCC_SDCC2_APPS_CLK>, 3645 <&rpmhcc RPMH_CXO_CLK>; 3646 clock-names = "iface", "core", "xo"; 3647 iommus = <&apps_smmu 0x4a0 0x0>; 3648 qcom,dll-config = <0x0007642c>; 3649 qcom,ddr-config = <0x80040868>; 3650 power-domains = <&rpmhpd RPMHPD_CX>; 3651 operating-points-v2 = <&sdhc2_opp_table>; 3652 3653 status = "disabled"; 3654 3655 sdhc2_opp_table: opp-table { 3656 compatible = "operating-points-v2"; 3657 3658 opp-19200000 { 3659 opp-hz = /bits/ 64 <19200000>; 3660 required-opps = <&rpmhpd_opp_min_svs>; 3661 }; 3662 3663 opp-50000000 { 3664 opp-hz = /bits/ 64 <50000000>; 3665 required-opps = <&rpmhpd_opp_low_svs>; 3666 }; 3667 3668 opp-100000000 { 3669 opp-hz = /bits/ 64 <100000000>; 3670 required-opps = <&rpmhpd_opp_svs>; 3671 }; 3672 3673 opp-202000000 { 3674 opp-hz = /bits/ 64 <202000000>; 3675 required-opps = <&rpmhpd_opp_svs_l1>; 3676 }; 3677 }; 3678 }; 3679 3680 pmu@9091000 { 3681 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3682 reg = <0 0x09091000 0 0x1000>; 3683 3684 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3685 3686 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 3687 3688 operating-points-v2 = <&llcc_bwmon_opp_table>; 3689 3690 llcc_bwmon_opp_table: opp-table { 3691 compatible = "operating-points-v2"; 3692 3693 opp-800000 { 3694 opp-peak-kBps = <(200 * 4 * 1000)>; 3695 }; 3696 3697 opp-1200000 { 3698 opp-peak-kBps = <(300 * 4 * 1000)>; 3699 }; 3700 3701 opp-1804000 { 3702 opp-peak-kBps = <(451 * 4 * 1000)>; 3703 }; 3704 3705 opp-2188000 { 3706 opp-peak-kBps = <(547 * 4 * 1000)>; 3707 }; 3708 3709 opp-2724000 { 3710 opp-peak-kBps = <(681 * 4 * 1000)>; 3711 }; 3712 3713 opp-3072000 { 3714 opp-peak-kBps = <(768 * 4 * 1000)>; 3715 }; 3716 3717 opp-4068000 { 3718 opp-peak-kBps = <(1017 * 4 * 1000)>; 3719 }; 3720 3721 /* 1353 MHz, LPDDR4X */ 3722 3723 opp-6220000 { 3724 opp-peak-kBps = <(1555 * 4 * 1000)>; 3725 }; 3726 3727 opp-7216000 { 3728 opp-peak-kBps = <(1804 * 4 * 1000)>; 3729 }; 3730 3731 opp-8368000 { 3732 opp-peak-kBps = <(2092 * 4 * 1000)>; 3733 }; 3734 3735 /* LPDDR5 */ 3736 opp-10944000 { 3737 opp-peak-kBps = <(2736 * 4 * 1000)>; 3738 }; 3739 }; 3740 }; 3741 3742 pmu@90b6400 { 3743 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 3744 reg = <0 0x090b6400 0 0x600>; 3745 3746 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3747 3748 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 3749 operating-points-v2 = <&cpu_bwmon_opp_table>; 3750 3751 cpu_bwmon_opp_table: opp-table { 3752 compatible = "operating-points-v2"; 3753 3754 opp-800000 { 3755 opp-peak-kBps = <(200 * 4 * 1000)>; 3756 }; 3757 3758 opp-1804000 { 3759 opp-peak-kBps = <(451 * 4 * 1000)>; 3760 }; 3761 3762 opp-2188000 { 3763 opp-peak-kBps = <(547 * 4 * 1000)>; 3764 }; 3765 3766 opp-2724000 { 3767 opp-peak-kBps = <(681 * 4 * 1000)>; 3768 }; 3769 3770 opp-3072000 { 3771 opp-peak-kBps = <(768 * 4 * 1000)>; 3772 }; 3773 3774 /* 1017MHz, 1353 MHz, LPDDR4X */ 3775 3776 opp-6220000 { 3777 opp-peak-kBps = <(1555 * 4 * 1000)>; 3778 }; 3779 3780 opp-6832000 { 3781 opp-peak-kBps = <(1708 * 4 * 1000)>; 3782 }; 3783 3784 opp-8368000 { 3785 opp-peak-kBps = <(2092 * 4 * 1000)>; 3786 }; 3787 3788 /* 2133MHz, LPDDR4X */ 3789 3790 /* LPDDR5 */ 3791 opp-10944000 { 3792 opp-peak-kBps = <(2736 * 4 * 1000)>; 3793 }; 3794 3795 /* LPDDR5 */ 3796 opp-12784000 { 3797 opp-peak-kBps = <(3196 * 4 * 1000)>; 3798 }; 3799 }; 3800 }; 3801 3802 dc_noc: interconnect@90c0000 { 3803 compatible = "qcom,sm8250-dc-noc"; 3804 reg = <0 0x090c0000 0 0x4200>; 3805 #interconnect-cells = <2>; 3806 qcom,bcm-voters = <&apps_bcm_voter>; 3807 }; 3808 3809 gem_noc: interconnect@9100000 { 3810 compatible = "qcom,sm8250-gem-noc"; 3811 reg = <0 0x09100000 0 0xb4000>; 3812 #interconnect-cells = <2>; 3813 qcom,bcm-voters = <&apps_bcm_voter>; 3814 }; 3815 3816 npu_noc: interconnect@9990000 { 3817 compatible = "qcom,sm8250-npu-noc"; 3818 reg = <0 0x09990000 0 0x1600>; 3819 #interconnect-cells = <2>; 3820 qcom,bcm-voters = <&apps_bcm_voter>; 3821 }; 3822 3823 usb_1: usb@a6f8800 { 3824 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3825 reg = <0 0x0a6f8800 0 0x400>; 3826 status = "disabled"; 3827 #address-cells = <2>; 3828 #size-cells = <2>; 3829 ranges; 3830 dma-ranges; 3831 3832 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3833 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3834 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3835 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3836 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3837 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3838 clock-names = "cfg_noc", 3839 "core", 3840 "iface", 3841 "sleep", 3842 "mock_utmi", 3843 "xo"; 3844 3845 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3846 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3847 assigned-clock-rates = <19200000>, <200000000>; 3848 3849 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3850 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3851 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3852 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3853 interrupt-names = "hs_phy_irq", 3854 "ss_phy_irq", 3855 "dm_hs_phy_irq", 3856 "dp_hs_phy_irq"; 3857 3858 power-domains = <&gcc USB30_PRIM_GDSC>; 3859 3860 resets = <&gcc GCC_USB30_PRIM_BCR>; 3861 3862 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3863 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3864 interconnect-names = "usb-ddr", "apps-usb"; 3865 3866 usb_1_dwc3: usb@a600000 { 3867 compatible = "snps,dwc3"; 3868 reg = <0 0x0a600000 0 0xcd00>; 3869 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3870 iommus = <&apps_smmu 0x0 0x0>; 3871 snps,dis_u2_susphy_quirk; 3872 snps,dis_enblslpm_quirk; 3873 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3874 phy-names = "usb2-phy", "usb3-phy"; 3875 }; 3876 }; 3877 3878 system-cache-controller@9200000 { 3879 compatible = "qcom,sm8250-llcc"; 3880 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 3881 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 3882 <0 0x09600000 0 0x50000>; 3883 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3884 "llcc3_base", "llcc_broadcast_base"; 3885 }; 3886 3887 usb_2: usb@a8f8800 { 3888 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3889 reg = <0 0x0a8f8800 0 0x400>; 3890 status = "disabled"; 3891 #address-cells = <2>; 3892 #size-cells = <2>; 3893 ranges; 3894 dma-ranges; 3895 3896 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3897 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3898 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3899 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3900 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3901 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3902 clock-names = "cfg_noc", 3903 "core", 3904 "iface", 3905 "sleep", 3906 "mock_utmi", 3907 "xo"; 3908 3909 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3910 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3911 assigned-clock-rates = <19200000>, <200000000>; 3912 3913 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3914 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3915 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3916 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3917 interrupt-names = "hs_phy_irq", 3918 "ss_phy_irq", 3919 "dm_hs_phy_irq", 3920 "dp_hs_phy_irq"; 3921 3922 power-domains = <&gcc USB30_SEC_GDSC>; 3923 3924 resets = <&gcc GCC_USB30_SEC_BCR>; 3925 3926 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3927 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3928 interconnect-names = "usb-ddr", "apps-usb"; 3929 3930 usb_2_dwc3: usb@a800000 { 3931 compatible = "snps,dwc3"; 3932 reg = <0 0x0a800000 0 0xcd00>; 3933 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3934 iommus = <&apps_smmu 0x20 0>; 3935 snps,dis_u2_susphy_quirk; 3936 snps,dis_enblslpm_quirk; 3937 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3938 phy-names = "usb2-phy", "usb3-phy"; 3939 }; 3940 }; 3941 3942 venus: video-codec@aa00000 { 3943 compatible = "qcom,sm8250-venus"; 3944 reg = <0 0x0aa00000 0 0x100000>; 3945 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3946 power-domains = <&videocc MVS0C_GDSC>, 3947 <&videocc MVS0_GDSC>, 3948 <&rpmhpd RPMHPD_MX>; 3949 power-domain-names = "venus", "vcodec0", "mx"; 3950 operating-points-v2 = <&venus_opp_table>; 3951 3952 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3953 <&videocc VIDEO_CC_MVS0C_CLK>, 3954 <&videocc VIDEO_CC_MVS0_CLK>; 3955 clock-names = "iface", "core", "vcodec0_core"; 3956 3957 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 3958 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 3959 interconnect-names = "cpu-cfg", "video-mem"; 3960 3961 iommus = <&apps_smmu 0x2100 0x0400>; 3962 memory-region = <&video_mem>; 3963 3964 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3965 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3966 reset-names = "bus", "core"; 3967 3968 status = "disabled"; 3969 3970 video-decoder { 3971 compatible = "venus-decoder"; 3972 }; 3973 3974 video-encoder { 3975 compatible = "venus-encoder"; 3976 }; 3977 3978 venus_opp_table: opp-table { 3979 compatible = "operating-points-v2"; 3980 3981 opp-720000000 { 3982 opp-hz = /bits/ 64 <720000000>; 3983 required-opps = <&rpmhpd_opp_low_svs>; 3984 }; 3985 3986 opp-1014000000 { 3987 opp-hz = /bits/ 64 <1014000000>; 3988 required-opps = <&rpmhpd_opp_svs>; 3989 }; 3990 3991 opp-1098000000 { 3992 opp-hz = /bits/ 64 <1098000000>; 3993 required-opps = <&rpmhpd_opp_svs_l1>; 3994 }; 3995 3996 opp-1332000000 { 3997 opp-hz = /bits/ 64 <1332000000>; 3998 required-opps = <&rpmhpd_opp_nom>; 3999 }; 4000 }; 4001 }; 4002 4003 videocc: clock-controller@abf0000 { 4004 compatible = "qcom,sm8250-videocc"; 4005 reg = <0 0x0abf0000 0 0x10000>; 4006 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4007 <&rpmhcc RPMH_CXO_CLK>, 4008 <&rpmhcc RPMH_CXO_CLK_A>; 4009 power-domains = <&rpmhpd RPMHPD_MMCX>; 4010 required-opps = <&rpmhpd_opp_low_svs>; 4011 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4012 #clock-cells = <1>; 4013 #reset-cells = <1>; 4014 #power-domain-cells = <1>; 4015 }; 4016 4017 cci0: cci@ac4f000 { 4018 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4019 #address-cells = <1>; 4020 #size-cells = <0>; 4021 4022 reg = <0 0x0ac4f000 0 0x1000>; 4023 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4024 power-domains = <&camcc TITAN_TOP_GDSC>; 4025 4026 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4027 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4028 <&camcc CAM_CC_CPAS_AHB_CLK>, 4029 <&camcc CAM_CC_CCI_0_CLK>, 4030 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4031 clock-names = "camnoc_axi", 4032 "slow_ahb_src", 4033 "cpas_ahb", 4034 "cci", 4035 "cci_src"; 4036 4037 pinctrl-0 = <&cci0_default>; 4038 pinctrl-1 = <&cci0_sleep>; 4039 pinctrl-names = "default", "sleep"; 4040 4041 status = "disabled"; 4042 4043 cci0_i2c0: i2c-bus@0 { 4044 reg = <0>; 4045 clock-frequency = <1000000>; 4046 #address-cells = <1>; 4047 #size-cells = <0>; 4048 }; 4049 4050 cci0_i2c1: i2c-bus@1 { 4051 reg = <1>; 4052 clock-frequency = <1000000>; 4053 #address-cells = <1>; 4054 #size-cells = <0>; 4055 }; 4056 }; 4057 4058 cci1: cci@ac50000 { 4059 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4060 #address-cells = <1>; 4061 #size-cells = <0>; 4062 4063 reg = <0 0x0ac50000 0 0x1000>; 4064 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4065 power-domains = <&camcc TITAN_TOP_GDSC>; 4066 4067 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4068 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4069 <&camcc CAM_CC_CPAS_AHB_CLK>, 4070 <&camcc CAM_CC_CCI_1_CLK>, 4071 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4072 clock-names = "camnoc_axi", 4073 "slow_ahb_src", 4074 "cpas_ahb", 4075 "cci", 4076 "cci_src"; 4077 4078 pinctrl-0 = <&cci1_default>; 4079 pinctrl-1 = <&cci1_sleep>; 4080 pinctrl-names = "default", "sleep"; 4081 4082 status = "disabled"; 4083 4084 cci1_i2c0: i2c-bus@0 { 4085 reg = <0>; 4086 clock-frequency = <1000000>; 4087 #address-cells = <1>; 4088 #size-cells = <0>; 4089 }; 4090 4091 cci1_i2c1: i2c-bus@1 { 4092 reg = <1>; 4093 clock-frequency = <1000000>; 4094 #address-cells = <1>; 4095 #size-cells = <0>; 4096 }; 4097 }; 4098 4099 camss: camss@ac6a000 { 4100 compatible = "qcom,sm8250-camss"; 4101 status = "disabled"; 4102 4103 reg = <0 0x0ac6a000 0 0x2000>, 4104 <0 0x0ac6c000 0 0x2000>, 4105 <0 0x0ac6e000 0 0x1000>, 4106 <0 0x0ac70000 0 0x1000>, 4107 <0 0x0ac72000 0 0x1000>, 4108 <0 0x0ac74000 0 0x1000>, 4109 <0 0x0acb4000 0 0xd000>, 4110 <0 0x0acc3000 0 0xd000>, 4111 <0 0x0acd9000 0 0x2200>, 4112 <0 0x0acdb200 0 0x2200>; 4113 reg-names = "csiphy0", 4114 "csiphy1", 4115 "csiphy2", 4116 "csiphy3", 4117 "csiphy4", 4118 "csiphy5", 4119 "vfe0", 4120 "vfe1", 4121 "vfe_lite0", 4122 "vfe_lite1"; 4123 4124 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4138 interrupt-names = "csiphy0", 4139 "csiphy1", 4140 "csiphy2", 4141 "csiphy3", 4142 "csiphy4", 4143 "csiphy5", 4144 "csid0", 4145 "csid1", 4146 "csid2", 4147 "csid3", 4148 "vfe0", 4149 "vfe1", 4150 "vfe_lite0", 4151 "vfe_lite1"; 4152 4153 power-domains = <&camcc IFE_0_GDSC>, 4154 <&camcc IFE_1_GDSC>, 4155 <&camcc TITAN_TOP_GDSC>; 4156 4157 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4158 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4159 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4160 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4161 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4162 <&camcc CAM_CC_CORE_AHB_CLK>, 4163 <&camcc CAM_CC_CPAS_AHB_CLK>, 4164 <&camcc CAM_CC_CSIPHY0_CLK>, 4165 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4166 <&camcc CAM_CC_CSIPHY1_CLK>, 4167 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4168 <&camcc CAM_CC_CSIPHY2_CLK>, 4169 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4170 <&camcc CAM_CC_CSIPHY3_CLK>, 4171 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4172 <&camcc CAM_CC_CSIPHY4_CLK>, 4173 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4174 <&camcc CAM_CC_CSIPHY5_CLK>, 4175 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4176 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4177 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4178 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4179 <&camcc CAM_CC_IFE_0_CLK>, 4180 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4181 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4182 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4183 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4184 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4185 <&camcc CAM_CC_IFE_1_CLK>, 4186 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4187 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4188 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4189 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4190 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4191 <&camcc CAM_CC_IFE_LITE_CLK>, 4192 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4193 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4194 4195 clock-names = "cam_ahb_clk", 4196 "cam_hf_axi", 4197 "cam_sf_axi", 4198 "camnoc_axi", 4199 "camnoc_axi_src", 4200 "core_ahb", 4201 "cpas_ahb", 4202 "csiphy0", 4203 "csiphy0_timer", 4204 "csiphy1", 4205 "csiphy1_timer", 4206 "csiphy2", 4207 "csiphy2_timer", 4208 "csiphy3", 4209 "csiphy3_timer", 4210 "csiphy4", 4211 "csiphy4_timer", 4212 "csiphy5", 4213 "csiphy5_timer", 4214 "slow_ahb_src", 4215 "vfe0_ahb", 4216 "vfe0_axi", 4217 "vfe0", 4218 "vfe0_cphy_rx", 4219 "vfe0_csid", 4220 "vfe0_areg", 4221 "vfe1_ahb", 4222 "vfe1_axi", 4223 "vfe1", 4224 "vfe1_cphy_rx", 4225 "vfe1_csid", 4226 "vfe1_areg", 4227 "vfe_lite_ahb", 4228 "vfe_lite_axi", 4229 "vfe_lite", 4230 "vfe_lite_cphy_rx", 4231 "vfe_lite_csid"; 4232 4233 iommus = <&apps_smmu 0x800 0x400>, 4234 <&apps_smmu 0x801 0x400>, 4235 <&apps_smmu 0x840 0x400>, 4236 <&apps_smmu 0x841 0x400>, 4237 <&apps_smmu 0xc00 0x400>, 4238 <&apps_smmu 0xc01 0x400>, 4239 <&apps_smmu 0xc40 0x400>, 4240 <&apps_smmu 0xc41 0x400>; 4241 4242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4243 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4244 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4245 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4246 interconnect-names = "cam_ahb", 4247 "cam_hf_0_mnoc", 4248 "cam_sf_0_mnoc", 4249 "cam_sf_icp_mnoc"; 4250 4251 ports { 4252 #address-cells = <1>; 4253 #size-cells = <0>; 4254 4255 port@0 { 4256 reg = <0>; 4257 }; 4258 4259 port@1 { 4260 reg = <1>; 4261 }; 4262 4263 port@2 { 4264 reg = <2>; 4265 }; 4266 4267 port@3 { 4268 reg = <3>; 4269 }; 4270 4271 port@4 { 4272 reg = <4>; 4273 }; 4274 4275 port@5 { 4276 reg = <5>; 4277 }; 4278 }; 4279 }; 4280 4281 camcc: clock-controller@ad00000 { 4282 compatible = "qcom,sm8250-camcc"; 4283 reg = <0 0x0ad00000 0 0x10000>; 4284 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4285 <&rpmhcc RPMH_CXO_CLK>, 4286 <&rpmhcc RPMH_CXO_CLK_A>, 4287 <&sleep_clk>; 4288 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4289 power-domains = <&rpmhpd RPMHPD_MMCX>; 4290 required-opps = <&rpmhpd_opp_low_svs>; 4291 status = "disabled"; 4292 #clock-cells = <1>; 4293 #reset-cells = <1>; 4294 #power-domain-cells = <1>; 4295 }; 4296 4297 mdss: display-subsystem@ae00000 { 4298 compatible = "qcom,sm8250-mdss"; 4299 reg = <0 0x0ae00000 0 0x1000>; 4300 reg-names = "mdss"; 4301 4302 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4303 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4304 interconnect-names = "mdp0-mem", "mdp1-mem"; 4305 4306 power-domains = <&dispcc MDSS_GDSC>; 4307 4308 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4309 <&gcc GCC_DISP_HF_AXI_CLK>, 4310 <&gcc GCC_DISP_SF_AXI_CLK>, 4311 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4312 clock-names = "iface", "bus", "nrt_bus", "core"; 4313 4314 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4315 interrupt-controller; 4316 #interrupt-cells = <1>; 4317 4318 iommus = <&apps_smmu 0x820 0x402>; 4319 4320 status = "disabled"; 4321 4322 #address-cells = <2>; 4323 #size-cells = <2>; 4324 ranges; 4325 4326 mdss_mdp: display-controller@ae01000 { 4327 compatible = "qcom,sm8250-dpu"; 4328 reg = <0 0x0ae01000 0 0x8f000>, 4329 <0 0x0aeb0000 0 0x2008>; 4330 reg-names = "mdp", "vbif"; 4331 4332 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4333 <&gcc GCC_DISP_HF_AXI_CLK>, 4334 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4335 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4336 clock-names = "iface", "bus", "core", "vsync"; 4337 4338 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4339 assigned-clock-rates = <19200000>; 4340 4341 operating-points-v2 = <&mdp_opp_table>; 4342 power-domains = <&rpmhpd RPMHPD_MMCX>; 4343 4344 interrupt-parent = <&mdss>; 4345 interrupts = <0>; 4346 4347 ports { 4348 #address-cells = <1>; 4349 #size-cells = <0>; 4350 4351 port@0 { 4352 reg = <0>; 4353 dpu_intf1_out: endpoint { 4354 remote-endpoint = <&mdss_dsi0_in>; 4355 }; 4356 }; 4357 4358 port@1 { 4359 reg = <1>; 4360 dpu_intf2_out: endpoint { 4361 remote-endpoint = <&mdss_dsi1_in>; 4362 }; 4363 }; 4364 }; 4365 4366 mdp_opp_table: opp-table { 4367 compatible = "operating-points-v2"; 4368 4369 opp-200000000 { 4370 opp-hz = /bits/ 64 <200000000>; 4371 required-opps = <&rpmhpd_opp_low_svs>; 4372 }; 4373 4374 opp-300000000 { 4375 opp-hz = /bits/ 64 <300000000>; 4376 required-opps = <&rpmhpd_opp_svs>; 4377 }; 4378 4379 opp-345000000 { 4380 opp-hz = /bits/ 64 <345000000>; 4381 required-opps = <&rpmhpd_opp_svs_l1>; 4382 }; 4383 4384 opp-460000000 { 4385 opp-hz = /bits/ 64 <460000000>; 4386 required-opps = <&rpmhpd_opp_nom>; 4387 }; 4388 }; 4389 }; 4390 4391 mdss_dsi0: dsi@ae94000 { 4392 compatible = "qcom,sm8250-dsi-ctrl", 4393 "qcom,mdss-dsi-ctrl"; 4394 reg = <0 0x0ae94000 0 0x400>; 4395 reg-names = "dsi_ctrl"; 4396 4397 interrupt-parent = <&mdss>; 4398 interrupts = <4>; 4399 4400 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4401 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4402 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4403 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4404 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4405 <&gcc GCC_DISP_HF_AXI_CLK>; 4406 clock-names = "byte", 4407 "byte_intf", 4408 "pixel", 4409 "core", 4410 "iface", 4411 "bus"; 4412 4413 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4414 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4415 4416 operating-points-v2 = <&dsi_opp_table>; 4417 power-domains = <&rpmhpd RPMHPD_MMCX>; 4418 4419 phys = <&mdss_dsi0_phy>; 4420 4421 status = "disabled"; 4422 4423 #address-cells = <1>; 4424 #size-cells = <0>; 4425 4426 ports { 4427 #address-cells = <1>; 4428 #size-cells = <0>; 4429 4430 port@0 { 4431 reg = <0>; 4432 mdss_dsi0_in: endpoint { 4433 remote-endpoint = <&dpu_intf1_out>; 4434 }; 4435 }; 4436 4437 port@1 { 4438 reg = <1>; 4439 mdss_dsi0_out: endpoint { 4440 }; 4441 }; 4442 }; 4443 4444 dsi_opp_table: opp-table { 4445 compatible = "operating-points-v2"; 4446 4447 opp-187500000 { 4448 opp-hz = /bits/ 64 <187500000>; 4449 required-opps = <&rpmhpd_opp_low_svs>; 4450 }; 4451 4452 opp-300000000 { 4453 opp-hz = /bits/ 64 <300000000>; 4454 required-opps = <&rpmhpd_opp_svs>; 4455 }; 4456 4457 opp-358000000 { 4458 opp-hz = /bits/ 64 <358000000>; 4459 required-opps = <&rpmhpd_opp_svs_l1>; 4460 }; 4461 }; 4462 }; 4463 4464 mdss_dsi0_phy: phy@ae94400 { 4465 compatible = "qcom,dsi-phy-7nm"; 4466 reg = <0 0x0ae94400 0 0x200>, 4467 <0 0x0ae94600 0 0x280>, 4468 <0 0x0ae94900 0 0x260>; 4469 reg-names = "dsi_phy", 4470 "dsi_phy_lane", 4471 "dsi_pll"; 4472 4473 #clock-cells = <1>; 4474 #phy-cells = <0>; 4475 4476 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4477 <&rpmhcc RPMH_CXO_CLK>; 4478 clock-names = "iface", "ref"; 4479 4480 status = "disabled"; 4481 }; 4482 4483 mdss_dsi1: dsi@ae96000 { 4484 compatible = "qcom,sm8250-dsi-ctrl", 4485 "qcom,mdss-dsi-ctrl"; 4486 reg = <0 0x0ae96000 0 0x400>; 4487 reg-names = "dsi_ctrl"; 4488 4489 interrupt-parent = <&mdss>; 4490 interrupts = <5>; 4491 4492 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4493 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4494 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4495 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4496 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4497 <&gcc GCC_DISP_HF_AXI_CLK>; 4498 clock-names = "byte", 4499 "byte_intf", 4500 "pixel", 4501 "core", 4502 "iface", 4503 "bus"; 4504 4505 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4506 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4507 4508 operating-points-v2 = <&dsi_opp_table>; 4509 power-domains = <&rpmhpd RPMHPD_MMCX>; 4510 4511 phys = <&mdss_dsi1_phy>; 4512 4513 status = "disabled"; 4514 4515 #address-cells = <1>; 4516 #size-cells = <0>; 4517 4518 ports { 4519 #address-cells = <1>; 4520 #size-cells = <0>; 4521 4522 port@0 { 4523 reg = <0>; 4524 mdss_dsi1_in: endpoint { 4525 remote-endpoint = <&dpu_intf2_out>; 4526 }; 4527 }; 4528 4529 port@1 { 4530 reg = <1>; 4531 mdss_dsi1_out: endpoint { 4532 }; 4533 }; 4534 }; 4535 }; 4536 4537 mdss_dsi1_phy: phy@ae96400 { 4538 compatible = "qcom,dsi-phy-7nm"; 4539 reg = <0 0x0ae96400 0 0x200>, 4540 <0 0x0ae96600 0 0x280>, 4541 <0 0x0ae96900 0 0x260>; 4542 reg-names = "dsi_phy", 4543 "dsi_phy_lane", 4544 "dsi_pll"; 4545 4546 #clock-cells = <1>; 4547 #phy-cells = <0>; 4548 4549 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4550 <&rpmhcc RPMH_CXO_CLK>; 4551 clock-names = "iface", "ref"; 4552 4553 status = "disabled"; 4554 }; 4555 }; 4556 4557 dispcc: clock-controller@af00000 { 4558 compatible = "qcom,sm8250-dispcc"; 4559 reg = <0 0x0af00000 0 0x10000>; 4560 power-domains = <&rpmhpd RPMHPD_MMCX>; 4561 required-opps = <&rpmhpd_opp_low_svs>; 4562 clocks = <&rpmhcc RPMH_CXO_CLK>, 4563 <&mdss_dsi0_phy 0>, 4564 <&mdss_dsi0_phy 1>, 4565 <&mdss_dsi1_phy 0>, 4566 <&mdss_dsi1_phy 1>, 4567 <&dp_phy 0>, 4568 <&dp_phy 1>; 4569 clock-names = "bi_tcxo", 4570 "dsi0_phy_pll_out_byteclk", 4571 "dsi0_phy_pll_out_dsiclk", 4572 "dsi1_phy_pll_out_byteclk", 4573 "dsi1_phy_pll_out_dsiclk", 4574 "dp_phy_pll_link_clk", 4575 "dp_phy_pll_vco_div_clk"; 4576 #clock-cells = <1>; 4577 #reset-cells = <1>; 4578 #power-domain-cells = <1>; 4579 }; 4580 4581 pdc: interrupt-controller@b220000 { 4582 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4583 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4584 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4585 <125 63 1>, <126 716 12>; 4586 #interrupt-cells = <2>; 4587 interrupt-parent = <&intc>; 4588 interrupt-controller; 4589 }; 4590 4591 tsens0: thermal-sensor@c263000 { 4592 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4593 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4594 <0 0x0c222000 0 0x1ff>; /* SROT */ 4595 #qcom,sensors = <16>; 4596 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4598 interrupt-names = "uplow", "critical"; 4599 #thermal-sensor-cells = <1>; 4600 }; 4601 4602 tsens1: thermal-sensor@c265000 { 4603 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4604 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4605 <0 0x0c223000 0 0x1ff>; /* SROT */ 4606 #qcom,sensors = <9>; 4607 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4608 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4609 interrupt-names = "uplow", "critical"; 4610 #thermal-sensor-cells = <1>; 4611 }; 4612 4613 aoss_qmp: power-management@c300000 { 4614 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4615 reg = <0 0x0c300000 0 0x400>; 4616 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4617 IPCC_MPROC_SIGNAL_GLINK_QMP 4618 IRQ_TYPE_EDGE_RISING>; 4619 mboxes = <&ipcc IPCC_CLIENT_AOP 4620 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4621 4622 #clock-cells = <0>; 4623 }; 4624 4625 sram@c3f0000 { 4626 compatible = "qcom,rpmh-stats"; 4627 reg = <0 0x0c3f0000 0 0x400>; 4628 }; 4629 4630 spmi_bus: spmi@c440000 { 4631 compatible = "qcom,spmi-pmic-arb"; 4632 reg = <0x0 0x0c440000 0x0 0x0001100>, 4633 <0x0 0x0c600000 0x0 0x2000000>, 4634 <0x0 0x0e600000 0x0 0x0100000>, 4635 <0x0 0x0e700000 0x0 0x00a0000>, 4636 <0x0 0x0c40a000 0x0 0x0026000>; 4637 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4638 interrupt-names = "periph_irq"; 4639 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4640 qcom,ee = <0>; 4641 qcom,channel = <0>; 4642 #address-cells = <2>; 4643 #size-cells = <0>; 4644 interrupt-controller; 4645 #interrupt-cells = <4>; 4646 }; 4647 4648 tlmm: pinctrl@f100000 { 4649 compatible = "qcom,sm8250-pinctrl"; 4650 reg = <0 0x0f100000 0 0x300000>, 4651 <0 0x0f500000 0 0x300000>, 4652 <0 0x0f900000 0 0x300000>; 4653 reg-names = "west", "south", "north"; 4654 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4655 gpio-controller; 4656 #gpio-cells = <2>; 4657 interrupt-controller; 4658 #interrupt-cells = <2>; 4659 gpio-ranges = <&tlmm 0 0 181>; 4660 wakeup-parent = <&pdc>; 4661 4662 cam2_default: cam2-default-state { 4663 rst-pins { 4664 pins = "gpio78"; 4665 function = "gpio"; 4666 drive-strength = <2>; 4667 bias-disable; 4668 }; 4669 4670 mclk-pins { 4671 pins = "gpio96"; 4672 function = "cam_mclk"; 4673 drive-strength = <16>; 4674 bias-disable; 4675 }; 4676 }; 4677 4678 cam2_suspend: cam2-suspend-state { 4679 rst-pins { 4680 pins = "gpio78"; 4681 function = "gpio"; 4682 drive-strength = <2>; 4683 bias-pull-down; 4684 output-low; 4685 }; 4686 4687 mclk-pins { 4688 pins = "gpio96"; 4689 function = "cam_mclk"; 4690 drive-strength = <2>; 4691 bias-disable; 4692 }; 4693 }; 4694 4695 cci0_default: cci0-default-state { 4696 cci0_i2c0_default: cci0-i2c0-default-pins { 4697 /* SDA, SCL */ 4698 pins = "gpio101", "gpio102"; 4699 function = "cci_i2c"; 4700 4701 bias-pull-up; 4702 drive-strength = <2>; /* 2 mA */ 4703 }; 4704 4705 cci0_i2c1_default: cci0-i2c1-default-pins { 4706 /* SDA, SCL */ 4707 pins = "gpio103", "gpio104"; 4708 function = "cci_i2c"; 4709 4710 bias-pull-up; 4711 drive-strength = <2>; /* 2 mA */ 4712 }; 4713 }; 4714 4715 cci0_sleep: cci0-sleep-state { 4716 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4717 /* SDA, SCL */ 4718 pins = "gpio101", "gpio102"; 4719 function = "cci_i2c"; 4720 4721 drive-strength = <2>; /* 2 mA */ 4722 bias-pull-down; 4723 }; 4724 4725 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4726 /* SDA, SCL */ 4727 pins = "gpio103", "gpio104"; 4728 function = "cci_i2c"; 4729 4730 drive-strength = <2>; /* 2 mA */ 4731 bias-pull-down; 4732 }; 4733 }; 4734 4735 cci1_default: cci1-default-state { 4736 cci1_i2c0_default: cci1-i2c0-default-pins { 4737 /* SDA, SCL */ 4738 pins = "gpio105","gpio106"; 4739 function = "cci_i2c"; 4740 4741 bias-pull-up; 4742 drive-strength = <2>; /* 2 mA */ 4743 }; 4744 4745 cci1_i2c1_default: cci1-i2c1-default-pins { 4746 /* SDA, SCL */ 4747 pins = "gpio107","gpio108"; 4748 function = "cci_i2c"; 4749 4750 bias-pull-up; 4751 drive-strength = <2>; /* 2 mA */ 4752 }; 4753 }; 4754 4755 cci1_sleep: cci1-sleep-state { 4756 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4757 /* SDA, SCL */ 4758 pins = "gpio105","gpio106"; 4759 function = "cci_i2c"; 4760 4761 bias-pull-down; 4762 drive-strength = <2>; /* 2 mA */ 4763 }; 4764 4765 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4766 /* SDA, SCL */ 4767 pins = "gpio107","gpio108"; 4768 function = "cci_i2c"; 4769 4770 bias-pull-down; 4771 drive-strength = <2>; /* 2 mA */ 4772 }; 4773 }; 4774 4775 pri_mi2s_active: pri-mi2s-active-state { 4776 sclk-pins { 4777 pins = "gpio138"; 4778 function = "mi2s0_sck"; 4779 drive-strength = <8>; 4780 bias-disable; 4781 }; 4782 4783 ws-pins { 4784 pins = "gpio141"; 4785 function = "mi2s0_ws"; 4786 drive-strength = <8>; 4787 output-high; 4788 }; 4789 4790 data0-pins { 4791 pins = "gpio139"; 4792 function = "mi2s0_data0"; 4793 drive-strength = <8>; 4794 bias-disable; 4795 output-high; 4796 }; 4797 4798 data1-pins { 4799 pins = "gpio140"; 4800 function = "mi2s0_data1"; 4801 drive-strength = <8>; 4802 output-high; 4803 }; 4804 }; 4805 4806 qup_i2c0_default: qup-i2c0-default-state { 4807 pins = "gpio28", "gpio29"; 4808 function = "qup0"; 4809 drive-strength = <2>; 4810 bias-disable; 4811 }; 4812 4813 qup_i2c1_default: qup-i2c1-default-state { 4814 pins = "gpio4", "gpio5"; 4815 function = "qup1"; 4816 drive-strength = <2>; 4817 bias-disable; 4818 }; 4819 4820 qup_i2c2_default: qup-i2c2-default-state { 4821 pins = "gpio115", "gpio116"; 4822 function = "qup2"; 4823 drive-strength = <2>; 4824 bias-disable; 4825 }; 4826 4827 qup_i2c3_default: qup-i2c3-default-state { 4828 pins = "gpio119", "gpio120"; 4829 function = "qup3"; 4830 drive-strength = <2>; 4831 bias-disable; 4832 }; 4833 4834 qup_i2c4_default: qup-i2c4-default-state { 4835 pins = "gpio8", "gpio9"; 4836 function = "qup4"; 4837 drive-strength = <2>; 4838 bias-disable; 4839 }; 4840 4841 qup_i2c5_default: qup-i2c5-default-state { 4842 pins = "gpio12", "gpio13"; 4843 function = "qup5"; 4844 drive-strength = <2>; 4845 bias-disable; 4846 }; 4847 4848 qup_i2c6_default: qup-i2c6-default-state { 4849 pins = "gpio16", "gpio17"; 4850 function = "qup6"; 4851 drive-strength = <2>; 4852 bias-disable; 4853 }; 4854 4855 qup_i2c7_default: qup-i2c7-default-state { 4856 pins = "gpio20", "gpio21"; 4857 function = "qup7"; 4858 drive-strength = <2>; 4859 bias-disable; 4860 }; 4861 4862 qup_i2c8_default: qup-i2c8-default-state { 4863 pins = "gpio24", "gpio25"; 4864 function = "qup8"; 4865 drive-strength = <2>; 4866 bias-disable; 4867 }; 4868 4869 qup_i2c9_default: qup-i2c9-default-state { 4870 pins = "gpio125", "gpio126"; 4871 function = "qup9"; 4872 drive-strength = <2>; 4873 bias-disable; 4874 }; 4875 4876 qup_i2c10_default: qup-i2c10-default-state { 4877 pins = "gpio129", "gpio130"; 4878 function = "qup10"; 4879 drive-strength = <2>; 4880 bias-disable; 4881 }; 4882 4883 qup_i2c11_default: qup-i2c11-default-state { 4884 pins = "gpio60", "gpio61"; 4885 function = "qup11"; 4886 drive-strength = <2>; 4887 bias-disable; 4888 }; 4889 4890 qup_i2c12_default: qup-i2c12-default-state { 4891 pins = "gpio32", "gpio33"; 4892 function = "qup12"; 4893 drive-strength = <2>; 4894 bias-disable; 4895 }; 4896 4897 qup_i2c13_default: qup-i2c13-default-state { 4898 pins = "gpio36", "gpio37"; 4899 function = "qup13"; 4900 drive-strength = <2>; 4901 bias-disable; 4902 }; 4903 4904 qup_i2c14_default: qup-i2c14-default-state { 4905 pins = "gpio40", "gpio41"; 4906 function = "qup14"; 4907 drive-strength = <2>; 4908 bias-disable; 4909 }; 4910 4911 qup_i2c15_default: qup-i2c15-default-state { 4912 pins = "gpio44", "gpio45"; 4913 function = "qup15"; 4914 drive-strength = <2>; 4915 bias-disable; 4916 }; 4917 4918 qup_i2c16_default: qup-i2c16-default-state { 4919 pins = "gpio48", "gpio49"; 4920 function = "qup16"; 4921 drive-strength = <2>; 4922 bias-disable; 4923 }; 4924 4925 qup_i2c17_default: qup-i2c17-default-state { 4926 pins = "gpio52", "gpio53"; 4927 function = "qup17"; 4928 drive-strength = <2>; 4929 bias-disable; 4930 }; 4931 4932 qup_i2c18_default: qup-i2c18-default-state { 4933 pins = "gpio56", "gpio57"; 4934 function = "qup18"; 4935 drive-strength = <2>; 4936 bias-disable; 4937 }; 4938 4939 qup_i2c19_default: qup-i2c19-default-state { 4940 pins = "gpio0", "gpio1"; 4941 function = "qup19"; 4942 drive-strength = <2>; 4943 bias-disable; 4944 }; 4945 4946 qup_spi0_cs: qup-spi0-cs-state { 4947 pins = "gpio31"; 4948 function = "qup0"; 4949 }; 4950 4951 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4952 pins = "gpio31"; 4953 function = "gpio"; 4954 }; 4955 4956 qup_spi0_data_clk: qup-spi0-data-clk-state { 4957 pins = "gpio28", "gpio29", 4958 "gpio30"; 4959 function = "qup0"; 4960 }; 4961 4962 qup_spi1_cs: qup-spi1-cs-state { 4963 pins = "gpio7"; 4964 function = "qup1"; 4965 }; 4966 4967 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4968 pins = "gpio7"; 4969 function = "gpio"; 4970 }; 4971 4972 qup_spi1_data_clk: qup-spi1-data-clk-state { 4973 pins = "gpio4", "gpio5", 4974 "gpio6"; 4975 function = "qup1"; 4976 }; 4977 4978 qup_spi2_cs: qup-spi2-cs-state { 4979 pins = "gpio118"; 4980 function = "qup2"; 4981 }; 4982 4983 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4984 pins = "gpio118"; 4985 function = "gpio"; 4986 }; 4987 4988 qup_spi2_data_clk: qup-spi2-data-clk-state { 4989 pins = "gpio115", "gpio116", 4990 "gpio117"; 4991 function = "qup2"; 4992 }; 4993 4994 qup_spi3_cs: qup-spi3-cs-state { 4995 pins = "gpio122"; 4996 function = "qup3"; 4997 }; 4998 4999 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5000 pins = "gpio122"; 5001 function = "gpio"; 5002 }; 5003 5004 qup_spi3_data_clk: qup-spi3-data-clk-state { 5005 pins = "gpio119", "gpio120", 5006 "gpio121"; 5007 function = "qup3"; 5008 }; 5009 5010 qup_spi4_cs: qup-spi4-cs-state { 5011 pins = "gpio11"; 5012 function = "qup4"; 5013 }; 5014 5015 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5016 pins = "gpio11"; 5017 function = "gpio"; 5018 }; 5019 5020 qup_spi4_data_clk: qup-spi4-data-clk-state { 5021 pins = "gpio8", "gpio9", 5022 "gpio10"; 5023 function = "qup4"; 5024 }; 5025 5026 qup_spi5_cs: qup-spi5-cs-state { 5027 pins = "gpio15"; 5028 function = "qup5"; 5029 }; 5030 5031 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5032 pins = "gpio15"; 5033 function = "gpio"; 5034 }; 5035 5036 qup_spi5_data_clk: qup-spi5-data-clk-state { 5037 pins = "gpio12", "gpio13", 5038 "gpio14"; 5039 function = "qup5"; 5040 }; 5041 5042 qup_spi6_cs: qup-spi6-cs-state { 5043 pins = "gpio19"; 5044 function = "qup6"; 5045 }; 5046 5047 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5048 pins = "gpio19"; 5049 function = "gpio"; 5050 }; 5051 5052 qup_spi6_data_clk: qup-spi6-data-clk-state { 5053 pins = "gpio16", "gpio17", 5054 "gpio18"; 5055 function = "qup6"; 5056 }; 5057 5058 qup_spi7_cs: qup-spi7-cs-state { 5059 pins = "gpio23"; 5060 function = "qup7"; 5061 }; 5062 5063 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5064 pins = "gpio23"; 5065 function = "gpio"; 5066 }; 5067 5068 qup_spi7_data_clk: qup-spi7-data-clk-state { 5069 pins = "gpio20", "gpio21", 5070 "gpio22"; 5071 function = "qup7"; 5072 }; 5073 5074 qup_spi8_cs: qup-spi8-cs-state { 5075 pins = "gpio27"; 5076 function = "qup8"; 5077 }; 5078 5079 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5080 pins = "gpio27"; 5081 function = "gpio"; 5082 }; 5083 5084 qup_spi8_data_clk: qup-spi8-data-clk-state { 5085 pins = "gpio24", "gpio25", 5086 "gpio26"; 5087 function = "qup8"; 5088 }; 5089 5090 qup_spi9_cs: qup-spi9-cs-state { 5091 pins = "gpio128"; 5092 function = "qup9"; 5093 }; 5094 5095 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5096 pins = "gpio128"; 5097 function = "gpio"; 5098 }; 5099 5100 qup_spi9_data_clk: qup-spi9-data-clk-state { 5101 pins = "gpio125", "gpio126", 5102 "gpio127"; 5103 function = "qup9"; 5104 }; 5105 5106 qup_spi10_cs: qup-spi10-cs-state { 5107 pins = "gpio132"; 5108 function = "qup10"; 5109 }; 5110 5111 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5112 pins = "gpio132"; 5113 function = "gpio"; 5114 }; 5115 5116 qup_spi10_data_clk: qup-spi10-data-clk-state { 5117 pins = "gpio129", "gpio130", 5118 "gpio131"; 5119 function = "qup10"; 5120 }; 5121 5122 qup_spi11_cs: qup-spi11-cs-state { 5123 pins = "gpio63"; 5124 function = "qup11"; 5125 }; 5126 5127 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5128 pins = "gpio63"; 5129 function = "gpio"; 5130 }; 5131 5132 qup_spi11_data_clk: qup-spi11-data-clk-state { 5133 pins = "gpio60", "gpio61", 5134 "gpio62"; 5135 function = "qup11"; 5136 }; 5137 5138 qup_spi12_cs: qup-spi12-cs-state { 5139 pins = "gpio35"; 5140 function = "qup12"; 5141 }; 5142 5143 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5144 pins = "gpio35"; 5145 function = "gpio"; 5146 }; 5147 5148 qup_spi12_data_clk: qup-spi12-data-clk-state { 5149 pins = "gpio32", "gpio33", 5150 "gpio34"; 5151 function = "qup12"; 5152 }; 5153 5154 qup_spi13_cs: qup-spi13-cs-state { 5155 pins = "gpio39"; 5156 function = "qup13"; 5157 }; 5158 5159 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5160 pins = "gpio39"; 5161 function = "gpio"; 5162 }; 5163 5164 qup_spi13_data_clk: qup-spi13-data-clk-state { 5165 pins = "gpio36", "gpio37", 5166 "gpio38"; 5167 function = "qup13"; 5168 }; 5169 5170 qup_spi14_cs: qup-spi14-cs-state { 5171 pins = "gpio43"; 5172 function = "qup14"; 5173 }; 5174 5175 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5176 pins = "gpio43"; 5177 function = "gpio"; 5178 }; 5179 5180 qup_spi14_data_clk: qup-spi14-data-clk-state { 5181 pins = "gpio40", "gpio41", 5182 "gpio42"; 5183 function = "qup14"; 5184 }; 5185 5186 qup_spi15_cs: qup-spi15-cs-state { 5187 pins = "gpio47"; 5188 function = "qup15"; 5189 }; 5190 5191 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5192 pins = "gpio47"; 5193 function = "gpio"; 5194 }; 5195 5196 qup_spi15_data_clk: qup-spi15-data-clk-state { 5197 pins = "gpio44", "gpio45", 5198 "gpio46"; 5199 function = "qup15"; 5200 }; 5201 5202 qup_spi16_cs: qup-spi16-cs-state { 5203 pins = "gpio51"; 5204 function = "qup16"; 5205 }; 5206 5207 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5208 pins = "gpio51"; 5209 function = "gpio"; 5210 }; 5211 5212 qup_spi16_data_clk: qup-spi16-data-clk-state { 5213 pins = "gpio48", "gpio49", 5214 "gpio50"; 5215 function = "qup16"; 5216 }; 5217 5218 qup_spi17_cs: qup-spi17-cs-state { 5219 pins = "gpio55"; 5220 function = "qup17"; 5221 }; 5222 5223 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5224 pins = "gpio55"; 5225 function = "gpio"; 5226 }; 5227 5228 qup_spi17_data_clk: qup-spi17-data-clk-state { 5229 pins = "gpio52", "gpio53", 5230 "gpio54"; 5231 function = "qup17"; 5232 }; 5233 5234 qup_spi18_cs: qup-spi18-cs-state { 5235 pins = "gpio59"; 5236 function = "qup18"; 5237 }; 5238 5239 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5240 pins = "gpio59"; 5241 function = "gpio"; 5242 }; 5243 5244 qup_spi18_data_clk: qup-spi18-data-clk-state { 5245 pins = "gpio56", "gpio57", 5246 "gpio58"; 5247 function = "qup18"; 5248 }; 5249 5250 qup_spi19_cs: qup-spi19-cs-state { 5251 pins = "gpio3"; 5252 function = "qup19"; 5253 }; 5254 5255 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5256 pins = "gpio3"; 5257 function = "gpio"; 5258 }; 5259 5260 qup_spi19_data_clk: qup-spi19-data-clk-state { 5261 pins = "gpio0", "gpio1", 5262 "gpio2"; 5263 function = "qup19"; 5264 }; 5265 5266 qup_uart2_default: qup-uart2-default-state { 5267 pins = "gpio117", "gpio118"; 5268 function = "qup2"; 5269 }; 5270 5271 qup_uart6_default: qup-uart6-default-state { 5272 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5273 function = "qup6"; 5274 }; 5275 5276 qup_uart12_default: qup-uart12-default-state { 5277 pins = "gpio34", "gpio35"; 5278 function = "qup12"; 5279 }; 5280 5281 qup_uart17_default: qup-uart17-default-state { 5282 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5283 function = "qup17"; 5284 }; 5285 5286 qup_uart18_default: qup-uart18-default-state { 5287 pins = "gpio58", "gpio59"; 5288 function = "qup18"; 5289 }; 5290 5291 tert_mi2s_active: tert-mi2s-active-state { 5292 sck-pins { 5293 pins = "gpio133"; 5294 function = "mi2s2_sck"; 5295 drive-strength = <8>; 5296 bias-disable; 5297 }; 5298 5299 data0-pins { 5300 pins = "gpio134"; 5301 function = "mi2s2_data0"; 5302 drive-strength = <8>; 5303 bias-disable; 5304 output-high; 5305 }; 5306 5307 ws-pins { 5308 pins = "gpio135"; 5309 function = "mi2s2_ws"; 5310 drive-strength = <8>; 5311 output-high; 5312 }; 5313 }; 5314 5315 sdc2_sleep_state: sdc2-sleep-state { 5316 clk-pins { 5317 pins = "sdc2_clk"; 5318 drive-strength = <2>; 5319 bias-disable; 5320 }; 5321 5322 cmd-pins { 5323 pins = "sdc2_cmd"; 5324 drive-strength = <2>; 5325 bias-pull-up; 5326 }; 5327 5328 data-pins { 5329 pins = "sdc2_data"; 5330 drive-strength = <2>; 5331 bias-pull-up; 5332 }; 5333 }; 5334 5335 pcie0_default_state: pcie0-default-state { 5336 perst-pins { 5337 pins = "gpio79"; 5338 function = "gpio"; 5339 drive-strength = <2>; 5340 bias-pull-down; 5341 }; 5342 5343 clkreq-pins { 5344 pins = "gpio80"; 5345 function = "pci_e0"; 5346 drive-strength = <2>; 5347 bias-pull-up; 5348 }; 5349 5350 wake-pins { 5351 pins = "gpio81"; 5352 function = "gpio"; 5353 drive-strength = <2>; 5354 bias-pull-up; 5355 }; 5356 }; 5357 5358 pcie1_default_state: pcie1-default-state { 5359 perst-pins { 5360 pins = "gpio82"; 5361 function = "gpio"; 5362 drive-strength = <2>; 5363 bias-pull-down; 5364 }; 5365 5366 clkreq-pins { 5367 pins = "gpio83"; 5368 function = "pci_e1"; 5369 drive-strength = <2>; 5370 bias-pull-up; 5371 }; 5372 5373 wake-pins { 5374 pins = "gpio84"; 5375 function = "gpio"; 5376 drive-strength = <2>; 5377 bias-pull-up; 5378 }; 5379 }; 5380 5381 pcie2_default_state: pcie2-default-state { 5382 perst-pins { 5383 pins = "gpio85"; 5384 function = "gpio"; 5385 drive-strength = <2>; 5386 bias-pull-down; 5387 }; 5388 5389 clkreq-pins { 5390 pins = "gpio86"; 5391 function = "pci_e2"; 5392 drive-strength = <2>; 5393 bias-pull-up; 5394 }; 5395 5396 wake-pins { 5397 pins = "gpio87"; 5398 function = "gpio"; 5399 drive-strength = <2>; 5400 bias-pull-up; 5401 }; 5402 }; 5403 }; 5404 5405 apps_smmu: iommu@15000000 { 5406 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5407 reg = <0 0x15000000 0 0x100000>; 5408 #iommu-cells = <2>; 5409 #global-interrupts = <2>; 5410 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5411 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5412 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5413 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5414 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5415 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5416 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5417 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5418 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5419 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5420 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5421 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5422 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5423 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5424 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5425 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5426 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5427 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5428 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5429 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5430 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5431 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5432 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5433 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5434 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5435 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5436 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5437 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5438 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5439 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5440 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5441 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5442 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5443 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5444 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5445 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5446 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5447 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5448 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5449 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5450 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5451 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5452 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5453 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5454 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5455 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5456 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5457 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5458 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5459 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5460 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5461 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5462 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5463 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5464 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5465 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5466 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5467 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5468 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5469 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5470 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5471 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5472 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5473 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5474 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5475 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5476 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5477 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5478 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5479 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5481 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5482 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5483 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5484 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5485 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5486 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5487 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5488 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5489 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5490 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5491 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5492 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5493 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5494 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5495 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5496 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5497 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5498 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5499 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5500 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5501 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5502 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5503 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5504 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5505 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5506 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5507 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5508 dma-coherent; 5509 }; 5510 5511 adsp: remoteproc@17300000 { 5512 compatible = "qcom,sm8250-adsp-pas"; 5513 reg = <0 0x17300000 0 0x100>; 5514 5515 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5516 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5517 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5518 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5519 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5520 interrupt-names = "wdog", "fatal", "ready", 5521 "handover", "stop-ack"; 5522 5523 clocks = <&rpmhcc RPMH_CXO_CLK>; 5524 clock-names = "xo"; 5525 5526 power-domains = <&rpmhpd RPMHPD_LCX>, 5527 <&rpmhpd RPMHPD_LMX>; 5528 power-domain-names = "lcx", "lmx"; 5529 5530 memory-region = <&adsp_mem>; 5531 5532 qcom,qmp = <&aoss_qmp>; 5533 5534 qcom,smem-states = <&smp2p_adsp_out 0>; 5535 qcom,smem-state-names = "stop"; 5536 5537 status = "disabled"; 5538 5539 glink-edge { 5540 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5541 IPCC_MPROC_SIGNAL_GLINK_QMP 5542 IRQ_TYPE_EDGE_RISING>; 5543 mboxes = <&ipcc IPCC_CLIENT_LPASS 5544 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5545 5546 label = "lpass"; 5547 qcom,remote-pid = <2>; 5548 5549 apr { 5550 compatible = "qcom,apr-v2"; 5551 qcom,glink-channels = "apr_audio_svc"; 5552 qcom,domain = <APR_DOMAIN_ADSP>; 5553 #address-cells = <1>; 5554 #size-cells = <0>; 5555 5556 service@3 { 5557 reg = <APR_SVC_ADSP_CORE>; 5558 compatible = "qcom,q6core"; 5559 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5560 }; 5561 5562 q6afe: service@4 { 5563 compatible = "qcom,q6afe"; 5564 reg = <APR_SVC_AFE>; 5565 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5566 q6afedai: dais { 5567 compatible = "qcom,q6afe-dais"; 5568 #address-cells = <1>; 5569 #size-cells = <0>; 5570 #sound-dai-cells = <1>; 5571 }; 5572 5573 q6afecc: clock-controller { 5574 compatible = "qcom,q6afe-clocks"; 5575 #clock-cells = <2>; 5576 }; 5577 }; 5578 5579 q6asm: service@7 { 5580 compatible = "qcom,q6asm"; 5581 reg = <APR_SVC_ASM>; 5582 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5583 q6asmdai: dais { 5584 compatible = "qcom,q6asm-dais"; 5585 #address-cells = <1>; 5586 #size-cells = <0>; 5587 #sound-dai-cells = <1>; 5588 iommus = <&apps_smmu 0x1801 0x0>; 5589 }; 5590 }; 5591 5592 q6adm: service@8 { 5593 compatible = "qcom,q6adm"; 5594 reg = <APR_SVC_ADM>; 5595 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5596 q6routing: routing { 5597 compatible = "qcom,q6adm-routing"; 5598 #sound-dai-cells = <0>; 5599 }; 5600 }; 5601 }; 5602 5603 fastrpc { 5604 compatible = "qcom,fastrpc"; 5605 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5606 label = "adsp"; 5607 qcom,non-secure-domain; 5608 #address-cells = <1>; 5609 #size-cells = <0>; 5610 5611 compute-cb@3 { 5612 compatible = "qcom,fastrpc-compute-cb"; 5613 reg = <3>; 5614 iommus = <&apps_smmu 0x1803 0x0>; 5615 }; 5616 5617 compute-cb@4 { 5618 compatible = "qcom,fastrpc-compute-cb"; 5619 reg = <4>; 5620 iommus = <&apps_smmu 0x1804 0x0>; 5621 }; 5622 5623 compute-cb@5 { 5624 compatible = "qcom,fastrpc-compute-cb"; 5625 reg = <5>; 5626 iommus = <&apps_smmu 0x1805 0x0>; 5627 }; 5628 }; 5629 }; 5630 }; 5631 5632 intc: interrupt-controller@17a00000 { 5633 compatible = "arm,gic-v3"; 5634 #interrupt-cells = <3>; 5635 interrupt-controller; 5636 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5637 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5638 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5639 }; 5640 5641 watchdog@17c10000 { 5642 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5643 reg = <0 0x17c10000 0 0x1000>; 5644 clocks = <&sleep_clk>; 5645 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5646 }; 5647 5648 timer@17c20000 { 5649 #address-cells = <1>; 5650 #size-cells = <1>; 5651 ranges = <0 0 0 0x20000000>; 5652 compatible = "arm,armv7-timer-mem"; 5653 reg = <0x0 0x17c20000 0x0 0x1000>; 5654 clock-frequency = <19200000>; 5655 5656 frame@17c21000 { 5657 frame-number = <0>; 5658 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5659 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5660 reg = <0x17c21000 0x1000>, 5661 <0x17c22000 0x1000>; 5662 }; 5663 5664 frame@17c23000 { 5665 frame-number = <1>; 5666 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5667 reg = <0x17c23000 0x1000>; 5668 status = "disabled"; 5669 }; 5670 5671 frame@17c25000 { 5672 frame-number = <2>; 5673 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5674 reg = <0x17c25000 0x1000>; 5675 status = "disabled"; 5676 }; 5677 5678 frame@17c27000 { 5679 frame-number = <3>; 5680 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5681 reg = <0x17c27000 0x1000>; 5682 status = "disabled"; 5683 }; 5684 5685 frame@17c29000 { 5686 frame-number = <4>; 5687 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5688 reg = <0x17c29000 0x1000>; 5689 status = "disabled"; 5690 }; 5691 5692 frame@17c2b000 { 5693 frame-number = <5>; 5694 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5695 reg = <0x17c2b000 0x1000>; 5696 status = "disabled"; 5697 }; 5698 5699 frame@17c2d000 { 5700 frame-number = <6>; 5701 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5702 reg = <0x17c2d000 0x1000>; 5703 status = "disabled"; 5704 }; 5705 }; 5706 5707 apps_rsc: rsc@18200000 { 5708 label = "apps_rsc"; 5709 compatible = "qcom,rpmh-rsc"; 5710 reg = <0x0 0x18200000 0x0 0x10000>, 5711 <0x0 0x18210000 0x0 0x10000>, 5712 <0x0 0x18220000 0x0 0x10000>; 5713 reg-names = "drv-0", "drv-1", "drv-2"; 5714 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5717 qcom,tcs-offset = <0xd00>; 5718 qcom,drv-id = <2>; 5719 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5720 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5721 power-domains = <&CLUSTER_PD>; 5722 5723 rpmhcc: clock-controller { 5724 compatible = "qcom,sm8250-rpmh-clk"; 5725 #clock-cells = <1>; 5726 clock-names = "xo"; 5727 clocks = <&xo_board>; 5728 }; 5729 5730 rpmhpd: power-controller { 5731 compatible = "qcom,sm8250-rpmhpd"; 5732 #power-domain-cells = <1>; 5733 operating-points-v2 = <&rpmhpd_opp_table>; 5734 5735 rpmhpd_opp_table: opp-table { 5736 compatible = "operating-points-v2"; 5737 5738 rpmhpd_opp_ret: opp1 { 5739 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5740 }; 5741 5742 rpmhpd_opp_min_svs: opp2 { 5743 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5744 }; 5745 5746 rpmhpd_opp_low_svs: opp3 { 5747 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5748 }; 5749 5750 rpmhpd_opp_svs: opp4 { 5751 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5752 }; 5753 5754 rpmhpd_opp_svs_l1: opp5 { 5755 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5756 }; 5757 5758 rpmhpd_opp_nom: opp6 { 5759 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5760 }; 5761 5762 rpmhpd_opp_nom_l1: opp7 { 5763 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5764 }; 5765 5766 rpmhpd_opp_nom_l2: opp8 { 5767 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5768 }; 5769 5770 rpmhpd_opp_turbo: opp9 { 5771 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5772 }; 5773 5774 rpmhpd_opp_turbo_l1: opp10 { 5775 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5776 }; 5777 }; 5778 }; 5779 5780 apps_bcm_voter: bcm-voter { 5781 compatible = "qcom,bcm-voter"; 5782 }; 5783 }; 5784 5785 epss_l3: interconnect@18590000 { 5786 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5787 reg = <0 0x18590000 0 0x1000>; 5788 5789 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5790 clock-names = "xo", "alternate"; 5791 5792 #interconnect-cells = <1>; 5793 }; 5794 5795 cpufreq_hw: cpufreq@18591000 { 5796 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5797 reg = <0 0x18591000 0 0x1000>, 5798 <0 0x18592000 0 0x1000>, 5799 <0 0x18593000 0 0x1000>; 5800 reg-names = "freq-domain0", "freq-domain1", 5801 "freq-domain2"; 5802 5803 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5804 clock-names = "xo", "alternate"; 5805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5808 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5809 #freq-domain-cells = <1>; 5810 #clock-cells = <1>; 5811 }; 5812 }; 5813 5814 sound: sound { 5815 }; 5816 5817 timer { 5818 compatible = "arm,armv8-timer"; 5819 interrupts = <GIC_PPI 13 5820 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5821 <GIC_PPI 14 5822 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5823 <GIC_PPI 11 5824 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5825 <GIC_PPI 10 5826 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5827 }; 5828 5829 thermal-zones { 5830 cpu0-thermal { 5831 polling-delay-passive = <250>; 5832 polling-delay = <1000>; 5833 5834 thermal-sensors = <&tsens0 1>; 5835 5836 trips { 5837 cpu0_alert0: trip-point0 { 5838 temperature = <90000>; 5839 hysteresis = <2000>; 5840 type = "passive"; 5841 }; 5842 5843 cpu0_alert1: trip-point1 { 5844 temperature = <95000>; 5845 hysteresis = <2000>; 5846 type = "passive"; 5847 }; 5848 5849 cpu0_crit: cpu-crit { 5850 temperature = <110000>; 5851 hysteresis = <1000>; 5852 type = "critical"; 5853 }; 5854 }; 5855 5856 cooling-maps { 5857 map0 { 5858 trip = <&cpu0_alert0>; 5859 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5860 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5861 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5862 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5863 }; 5864 map1 { 5865 trip = <&cpu0_alert1>; 5866 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5867 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5868 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5869 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5870 }; 5871 }; 5872 }; 5873 5874 cpu1-thermal { 5875 polling-delay-passive = <250>; 5876 polling-delay = <1000>; 5877 5878 thermal-sensors = <&tsens0 2>; 5879 5880 trips { 5881 cpu1_alert0: trip-point0 { 5882 temperature = <90000>; 5883 hysteresis = <2000>; 5884 type = "passive"; 5885 }; 5886 5887 cpu1_alert1: trip-point1 { 5888 temperature = <95000>; 5889 hysteresis = <2000>; 5890 type = "passive"; 5891 }; 5892 5893 cpu1_crit: cpu-crit { 5894 temperature = <110000>; 5895 hysteresis = <1000>; 5896 type = "critical"; 5897 }; 5898 }; 5899 5900 cooling-maps { 5901 map0 { 5902 trip = <&cpu1_alert0>; 5903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5904 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5905 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5906 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5907 }; 5908 map1 { 5909 trip = <&cpu1_alert1>; 5910 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5911 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5912 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5913 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5914 }; 5915 }; 5916 }; 5917 5918 cpu2-thermal { 5919 polling-delay-passive = <250>; 5920 polling-delay = <1000>; 5921 5922 thermal-sensors = <&tsens0 3>; 5923 5924 trips { 5925 cpu2_alert0: trip-point0 { 5926 temperature = <90000>; 5927 hysteresis = <2000>; 5928 type = "passive"; 5929 }; 5930 5931 cpu2_alert1: trip-point1 { 5932 temperature = <95000>; 5933 hysteresis = <2000>; 5934 type = "passive"; 5935 }; 5936 5937 cpu2_crit: cpu-crit { 5938 temperature = <110000>; 5939 hysteresis = <1000>; 5940 type = "critical"; 5941 }; 5942 }; 5943 5944 cooling-maps { 5945 map0 { 5946 trip = <&cpu2_alert0>; 5947 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5948 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5949 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5950 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5951 }; 5952 map1 { 5953 trip = <&cpu2_alert1>; 5954 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5955 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5956 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5957 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5958 }; 5959 }; 5960 }; 5961 5962 cpu3-thermal { 5963 polling-delay-passive = <250>; 5964 polling-delay = <1000>; 5965 5966 thermal-sensors = <&tsens0 4>; 5967 5968 trips { 5969 cpu3_alert0: trip-point0 { 5970 temperature = <90000>; 5971 hysteresis = <2000>; 5972 type = "passive"; 5973 }; 5974 5975 cpu3_alert1: trip-point1 { 5976 temperature = <95000>; 5977 hysteresis = <2000>; 5978 type = "passive"; 5979 }; 5980 5981 cpu3_crit: cpu-crit { 5982 temperature = <110000>; 5983 hysteresis = <1000>; 5984 type = "critical"; 5985 }; 5986 }; 5987 5988 cooling-maps { 5989 map0 { 5990 trip = <&cpu3_alert0>; 5991 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5992 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5993 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5994 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5995 }; 5996 map1 { 5997 trip = <&cpu3_alert1>; 5998 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5999 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6000 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6001 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6002 }; 6003 }; 6004 }; 6005 6006 cpu4-top-thermal { 6007 polling-delay-passive = <250>; 6008 polling-delay = <1000>; 6009 6010 thermal-sensors = <&tsens0 7>; 6011 6012 trips { 6013 cpu4_top_alert0: trip-point0 { 6014 temperature = <90000>; 6015 hysteresis = <2000>; 6016 type = "passive"; 6017 }; 6018 6019 cpu4_top_alert1: trip-point1 { 6020 temperature = <95000>; 6021 hysteresis = <2000>; 6022 type = "passive"; 6023 }; 6024 6025 cpu4_top_crit: cpu-crit { 6026 temperature = <110000>; 6027 hysteresis = <1000>; 6028 type = "critical"; 6029 }; 6030 }; 6031 6032 cooling-maps { 6033 map0 { 6034 trip = <&cpu4_top_alert0>; 6035 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6036 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6037 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6038 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6039 }; 6040 map1 { 6041 trip = <&cpu4_top_alert1>; 6042 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6043 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6044 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6045 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6046 }; 6047 }; 6048 }; 6049 6050 cpu5-top-thermal { 6051 polling-delay-passive = <250>; 6052 polling-delay = <1000>; 6053 6054 thermal-sensors = <&tsens0 8>; 6055 6056 trips { 6057 cpu5_top_alert0: trip-point0 { 6058 temperature = <90000>; 6059 hysteresis = <2000>; 6060 type = "passive"; 6061 }; 6062 6063 cpu5_top_alert1: trip-point1 { 6064 temperature = <95000>; 6065 hysteresis = <2000>; 6066 type = "passive"; 6067 }; 6068 6069 cpu5_top_crit: cpu-crit { 6070 temperature = <110000>; 6071 hysteresis = <1000>; 6072 type = "critical"; 6073 }; 6074 }; 6075 6076 cooling-maps { 6077 map0 { 6078 trip = <&cpu5_top_alert0>; 6079 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6080 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6081 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6082 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6083 }; 6084 map1 { 6085 trip = <&cpu5_top_alert1>; 6086 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6087 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6088 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6089 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6090 }; 6091 }; 6092 }; 6093 6094 cpu6-top-thermal { 6095 polling-delay-passive = <250>; 6096 polling-delay = <1000>; 6097 6098 thermal-sensors = <&tsens0 9>; 6099 6100 trips { 6101 cpu6_top_alert0: trip-point0 { 6102 temperature = <90000>; 6103 hysteresis = <2000>; 6104 type = "passive"; 6105 }; 6106 6107 cpu6_top_alert1: trip-point1 { 6108 temperature = <95000>; 6109 hysteresis = <2000>; 6110 type = "passive"; 6111 }; 6112 6113 cpu6_top_crit: cpu-crit { 6114 temperature = <110000>; 6115 hysteresis = <1000>; 6116 type = "critical"; 6117 }; 6118 }; 6119 6120 cooling-maps { 6121 map0 { 6122 trip = <&cpu6_top_alert0>; 6123 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6124 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6125 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6126 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6127 }; 6128 map1 { 6129 trip = <&cpu6_top_alert1>; 6130 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6131 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6132 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6133 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6134 }; 6135 }; 6136 }; 6137 6138 cpu7-top-thermal { 6139 polling-delay-passive = <250>; 6140 polling-delay = <1000>; 6141 6142 thermal-sensors = <&tsens0 10>; 6143 6144 trips { 6145 cpu7_top_alert0: trip-point0 { 6146 temperature = <90000>; 6147 hysteresis = <2000>; 6148 type = "passive"; 6149 }; 6150 6151 cpu7_top_alert1: trip-point1 { 6152 temperature = <95000>; 6153 hysteresis = <2000>; 6154 type = "passive"; 6155 }; 6156 6157 cpu7_top_crit: cpu-crit { 6158 temperature = <110000>; 6159 hysteresis = <1000>; 6160 type = "critical"; 6161 }; 6162 }; 6163 6164 cooling-maps { 6165 map0 { 6166 trip = <&cpu7_top_alert0>; 6167 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6168 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6169 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6170 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6171 }; 6172 map1 { 6173 trip = <&cpu7_top_alert1>; 6174 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6175 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6176 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6177 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6178 }; 6179 }; 6180 }; 6181 6182 cpu4-bottom-thermal { 6183 polling-delay-passive = <250>; 6184 polling-delay = <1000>; 6185 6186 thermal-sensors = <&tsens0 11>; 6187 6188 trips { 6189 cpu4_bottom_alert0: trip-point0 { 6190 temperature = <90000>; 6191 hysteresis = <2000>; 6192 type = "passive"; 6193 }; 6194 6195 cpu4_bottom_alert1: trip-point1 { 6196 temperature = <95000>; 6197 hysteresis = <2000>; 6198 type = "passive"; 6199 }; 6200 6201 cpu4_bottom_crit: cpu-crit { 6202 temperature = <110000>; 6203 hysteresis = <1000>; 6204 type = "critical"; 6205 }; 6206 }; 6207 6208 cooling-maps { 6209 map0 { 6210 trip = <&cpu4_bottom_alert0>; 6211 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6212 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6213 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6214 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6215 }; 6216 map1 { 6217 trip = <&cpu4_bottom_alert1>; 6218 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6219 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6220 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6221 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6222 }; 6223 }; 6224 }; 6225 6226 cpu5-bottom-thermal { 6227 polling-delay-passive = <250>; 6228 polling-delay = <1000>; 6229 6230 thermal-sensors = <&tsens0 12>; 6231 6232 trips { 6233 cpu5_bottom_alert0: trip-point0 { 6234 temperature = <90000>; 6235 hysteresis = <2000>; 6236 type = "passive"; 6237 }; 6238 6239 cpu5_bottom_alert1: trip-point1 { 6240 temperature = <95000>; 6241 hysteresis = <2000>; 6242 type = "passive"; 6243 }; 6244 6245 cpu5_bottom_crit: cpu-crit { 6246 temperature = <110000>; 6247 hysteresis = <1000>; 6248 type = "critical"; 6249 }; 6250 }; 6251 6252 cooling-maps { 6253 map0 { 6254 trip = <&cpu5_bottom_alert0>; 6255 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6256 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6257 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6258 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6259 }; 6260 map1 { 6261 trip = <&cpu5_bottom_alert1>; 6262 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6263 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6264 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6265 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6266 }; 6267 }; 6268 }; 6269 6270 cpu6-bottom-thermal { 6271 polling-delay-passive = <250>; 6272 polling-delay = <1000>; 6273 6274 thermal-sensors = <&tsens0 13>; 6275 6276 trips { 6277 cpu6_bottom_alert0: trip-point0 { 6278 temperature = <90000>; 6279 hysteresis = <2000>; 6280 type = "passive"; 6281 }; 6282 6283 cpu6_bottom_alert1: trip-point1 { 6284 temperature = <95000>; 6285 hysteresis = <2000>; 6286 type = "passive"; 6287 }; 6288 6289 cpu6_bottom_crit: cpu-crit { 6290 temperature = <110000>; 6291 hysteresis = <1000>; 6292 type = "critical"; 6293 }; 6294 }; 6295 6296 cooling-maps { 6297 map0 { 6298 trip = <&cpu6_bottom_alert0>; 6299 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6300 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6301 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6302 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6303 }; 6304 map1 { 6305 trip = <&cpu6_bottom_alert1>; 6306 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6307 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6308 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6309 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6310 }; 6311 }; 6312 }; 6313 6314 cpu7-bottom-thermal { 6315 polling-delay-passive = <250>; 6316 polling-delay = <1000>; 6317 6318 thermal-sensors = <&tsens0 14>; 6319 6320 trips { 6321 cpu7_bottom_alert0: trip-point0 { 6322 temperature = <90000>; 6323 hysteresis = <2000>; 6324 type = "passive"; 6325 }; 6326 6327 cpu7_bottom_alert1: trip-point1 { 6328 temperature = <95000>; 6329 hysteresis = <2000>; 6330 type = "passive"; 6331 }; 6332 6333 cpu7_bottom_crit: cpu-crit { 6334 temperature = <110000>; 6335 hysteresis = <1000>; 6336 type = "critical"; 6337 }; 6338 }; 6339 6340 cooling-maps { 6341 map0 { 6342 trip = <&cpu7_bottom_alert0>; 6343 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6344 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6345 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6346 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6347 }; 6348 map1 { 6349 trip = <&cpu7_bottom_alert1>; 6350 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6351 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6352 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6353 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6354 }; 6355 }; 6356 }; 6357 6358 aoss0-thermal { 6359 polling-delay-passive = <250>; 6360 polling-delay = <1000>; 6361 6362 thermal-sensors = <&tsens0 0>; 6363 6364 trips { 6365 aoss0_alert0: trip-point0 { 6366 temperature = <90000>; 6367 hysteresis = <2000>; 6368 type = "hot"; 6369 }; 6370 }; 6371 }; 6372 6373 cluster0-thermal { 6374 polling-delay-passive = <250>; 6375 polling-delay = <1000>; 6376 6377 thermal-sensors = <&tsens0 5>; 6378 6379 trips { 6380 cluster0_alert0: trip-point0 { 6381 temperature = <90000>; 6382 hysteresis = <2000>; 6383 type = "hot"; 6384 }; 6385 cluster0_crit: cluster0_crit { 6386 temperature = <110000>; 6387 hysteresis = <2000>; 6388 type = "critical"; 6389 }; 6390 }; 6391 }; 6392 6393 cluster1-thermal { 6394 polling-delay-passive = <250>; 6395 polling-delay = <1000>; 6396 6397 thermal-sensors = <&tsens0 6>; 6398 6399 trips { 6400 cluster1_alert0: trip-point0 { 6401 temperature = <90000>; 6402 hysteresis = <2000>; 6403 type = "hot"; 6404 }; 6405 cluster1_crit: cluster1_crit { 6406 temperature = <110000>; 6407 hysteresis = <2000>; 6408 type = "critical"; 6409 }; 6410 }; 6411 }; 6412 6413 gpu-top-thermal { 6414 polling-delay-passive = <250>; 6415 polling-delay = <1000>; 6416 6417 thermal-sensors = <&tsens0 15>; 6418 6419 trips { 6420 gpu1_alert0: trip-point0 { 6421 temperature = <90000>; 6422 hysteresis = <2000>; 6423 type = "hot"; 6424 }; 6425 }; 6426 }; 6427 6428 aoss1-thermal { 6429 polling-delay-passive = <250>; 6430 polling-delay = <1000>; 6431 6432 thermal-sensors = <&tsens1 0>; 6433 6434 trips { 6435 aoss1_alert0: trip-point0 { 6436 temperature = <90000>; 6437 hysteresis = <2000>; 6438 type = "hot"; 6439 }; 6440 }; 6441 }; 6442 6443 wlan-thermal { 6444 polling-delay-passive = <250>; 6445 polling-delay = <1000>; 6446 6447 thermal-sensors = <&tsens1 1>; 6448 6449 trips { 6450 wlan_alert0: trip-point0 { 6451 temperature = <90000>; 6452 hysteresis = <2000>; 6453 type = "hot"; 6454 }; 6455 }; 6456 }; 6457 6458 video-thermal { 6459 polling-delay-passive = <250>; 6460 polling-delay = <1000>; 6461 6462 thermal-sensors = <&tsens1 2>; 6463 6464 trips { 6465 video_alert0: trip-point0 { 6466 temperature = <90000>; 6467 hysteresis = <2000>; 6468 type = "hot"; 6469 }; 6470 }; 6471 }; 6472 6473 mem-thermal { 6474 polling-delay-passive = <250>; 6475 polling-delay = <1000>; 6476 6477 thermal-sensors = <&tsens1 3>; 6478 6479 trips { 6480 mem_alert0: trip-point0 { 6481 temperature = <90000>; 6482 hysteresis = <2000>; 6483 type = "hot"; 6484 }; 6485 }; 6486 }; 6487 6488 q6-hvx-thermal { 6489 polling-delay-passive = <250>; 6490 polling-delay = <1000>; 6491 6492 thermal-sensors = <&tsens1 4>; 6493 6494 trips { 6495 q6_hvx_alert0: trip-point0 { 6496 temperature = <90000>; 6497 hysteresis = <2000>; 6498 type = "hot"; 6499 }; 6500 }; 6501 }; 6502 6503 camera-thermal { 6504 polling-delay-passive = <250>; 6505 polling-delay = <1000>; 6506 6507 thermal-sensors = <&tsens1 5>; 6508 6509 trips { 6510 camera_alert0: trip-point0 { 6511 temperature = <90000>; 6512 hysteresis = <2000>; 6513 type = "hot"; 6514 }; 6515 }; 6516 }; 6517 6518 compute-thermal { 6519 polling-delay-passive = <250>; 6520 polling-delay = <1000>; 6521 6522 thermal-sensors = <&tsens1 6>; 6523 6524 trips { 6525 compute_alert0: trip-point0 { 6526 temperature = <90000>; 6527 hysteresis = <2000>; 6528 type = "hot"; 6529 }; 6530 }; 6531 }; 6532 6533 npu-thermal { 6534 polling-delay-passive = <250>; 6535 polling-delay = <1000>; 6536 6537 thermal-sensors = <&tsens1 7>; 6538 6539 trips { 6540 npu_alert0: trip-point0 { 6541 temperature = <90000>; 6542 hysteresis = <2000>; 6543 type = "hot"; 6544 }; 6545 }; 6546 }; 6547 6548 gpu-bottom-thermal { 6549 polling-delay-passive = <250>; 6550 polling-delay = <1000>; 6551 6552 thermal-sensors = <&tsens1 8>; 6553 6554 trips { 6555 gpu2_alert0: trip-point0 { 6556 temperature = <90000>; 6557 hysteresis = <2000>; 6558 type = "hot"; 6559 }; 6560 }; 6561 }; 6562 }; 6563}; 6564